| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2643228535 |
| 90.05 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3386693181 |
| 91.17 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2287165434 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3785763916 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2341758890 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.1937175551 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3805695318 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3599456831 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1800802625 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1954325406 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2143535644 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2530842159 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.1125644777 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1244115227 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.78429510 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3641740997 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3771558031 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.2866533760 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4157459868 |
| /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.1870179198 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2341758890 | Sep 24 01:50:55 AM UTC 24 | Sep 24 01:50:57 AM UTC 24 | 4451474 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2287165434 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:57 AM UTC 24 | 4697367 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1244115227 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:57 AM UTC 24 | 4728714 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3386693181 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:57 AM UTC 24 | 5044847 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3641740997 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 4661482 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3771558031 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 4512275 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.78429510 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 4433007 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.1870179198 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 5283731 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4157459868 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 4203110 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2643228535 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 4748084 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.2866533760 | Sep 24 01:50:56 AM UTC 24 | Sep 24 01:50:58 AM UTC 24 | 5024269 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3785763916 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 5127354 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3805695318 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4452625 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.1937175551 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4875829 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3599456831 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4452502 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1800802625 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4798258 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1954325406 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4808937 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2143535644 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4862586 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2530842159 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 4867866 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.1125644777 | Sep 24 01:50:57 AM UTC 24 | Sep 24 01:50:59 AM UTC 24 | 5054316 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2643228535 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4748084 ps |
| CPU time | 0.36 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643228535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.2643228535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3386693181 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5044847 ps |
| CPU time | 0.34 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:57 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386693181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.3386693181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2287165434 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4697367 ps |
| CPU time | 0.37 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:57 AM UTC 24 |
| Peak memory | 155512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287165434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.2287165434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3785763916 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5127354 ps |
| CPU time | 0.36 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785763916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.3785763916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2341758890 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4451474 ps |
| CPU time | 0.35 seconds |
| Started | Sep 24 01:50:55 AM UTC 24 |
| Finished | Sep 24 01:50:57 AM UTC 24 |
| Peak memory | 155704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341758890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.2341758890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.1937175551 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4875829 ps |
| CPU time | 0.36 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937175551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.1937175551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3805695318 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4452625 ps |
| CPU time | 0.36 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805695318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3805695318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3599456831 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4452502 ps |
| CPU time | 0.34 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599456831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.3599456831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1800802625 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4798258 ps |
| CPU time | 0.34 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800802625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.1800802625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1954325406 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4808937 ps |
| CPU time | 0.41 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954325406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.1954325406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2143535644 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4862586 ps |
| CPU time | 0.34 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143535644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.2143535644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2530842159 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4867866 ps |
| CPU time | 0.36 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530842159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.2530842159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.1125644777 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5054316 ps |
| CPU time | 0.38 seconds |
| Started | Sep 24 01:50:57 AM UTC 24 |
| Finished | Sep 24 01:50:59 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125644777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.1125644777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1244115227 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4728714 ps |
| CPU time | 0.36 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:57 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244115227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.1244115227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.78429510 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4433007 ps |
| CPU time | 0.35 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78429510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.78429510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3641740997 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4661482 ps |
| CPU time | 0.35 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641740997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.3641740997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3771558031 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4512275 ps |
| CPU time | 0.35 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771558031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.3771558031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.2866533760 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5024269 ps |
| CPU time | 0.39 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866533760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.2866533760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4157459868 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4203110 ps |
| CPU time | 0.37 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157459868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.4157459868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.1870179198 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5283731 ps |
| CPU time | 0.35 seconds |
| Started | Sep 24 01:50:56 AM UTC 24 |
| Finished | Sep 24 01:50:58 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870179198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.1870179198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/9.prim_esc_test/latest |
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