| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.233805363 |
| 89.45 | 1.71 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3242121093 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3718508425 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.441826786 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1112439073 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1925561569 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2991528776 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.407859515 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2451150252 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.1347877264 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3382987053 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.596208847 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.508754419 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4085608582 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.4263734899 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.662134481 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.925579651 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2192990363 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.677359149 |
| /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2687210967 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1112439073 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4630426 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1925561569 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4817700 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.233805363 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4599307 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.662134481 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4429726 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.4263734899 | Oct 02 04:06:44 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 5350127 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.677359149 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4657563 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.925579651 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 5084094 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.407859515 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4592440 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2192990363 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4668912 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3718508425 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4748359 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2687210967 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4701061 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2991528776 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4565749 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2451150252 | Oct 02 04:06:45 PM UTC 24 | Oct 02 04:06:46 PM UTC 24 | 4770101 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3382987053 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:47 PM UTC 24 | 4526146 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.1347877264 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:47 PM UTC 24 | 4262570 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.441826786 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:47 PM UTC 24 | 5675530 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.596208847 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:47 PM UTC 24 | 4892700 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.508754419 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:48 PM UTC 24 | 4909359 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4085608582 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:48 PM UTC 24 | 4861828 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3242121093 | Oct 02 04:06:46 PM UTC 24 | Oct 02 04:06:48 PM UTC 24 | 5067473 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.233805363 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4599307 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233805363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.prim_esc_test.233805363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3242121093 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5067473 ps |
| CPU time | 0.41 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:48 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242121093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.3242121093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3718508425 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4748359 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718508425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.3718508425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.441826786 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5675530 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:47 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441826786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.prim_esc_test.441826786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1112439073 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4630426 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112439073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.1112439073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1925561569 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4817700 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925561569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.1925561569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2991528776 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4565749 ps |
| CPU time | 0.42 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991528776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.2991528776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.407859515 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4592440 ps |
| CPU time | 0.35 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407859515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 11.prim_esc_test.407859515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2451150252 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4770101 ps |
| CPU time | 0.37 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451150252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.2451150252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.1347877264 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4262570 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:47 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347877264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.1347877264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3382987053 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4526146 ps |
| CPU time | 0.4 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:47 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382987053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.3382987053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.596208847 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4892700 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:47 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596208847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.prim_esc_test.596208847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.508754419 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4909359 ps |
| CPU time | 0.51 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:48 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508754419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 17.prim_esc_test.508754419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4085608582 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4861828 ps |
| CPU time | 0.43 seconds |
| Started | Oct 02 04:06:46 PM UTC 24 |
| Finished | Oct 02 04:06:48 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085608582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.4085608582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.4263734899 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5350127 ps |
| CPU time | 0.49 seconds |
| Started | Oct 02 04:06:44 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263734899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.4263734899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.662134481 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4429726 ps |
| CPU time | 0.43 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662134481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.prim_esc_test.662134481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.925579651 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5084094 ps |
| CPU time | 0.46 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925579651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 5.prim_esc_test.925579651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2192990363 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4668912 ps |
| CPU time | 0.44 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192990363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.2192990363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.677359149 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4657563 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677359149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.prim_esc_test.677359149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2687210967 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4701061 ps |
| CPU time | 0.39 seconds |
| Started | Oct 02 04:06:45 PM UTC 24 |
| Finished | Oct 02 04:06:46 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687210967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.2687210967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/prim_esc-sim-vcs/9.prim_esc_test/latest |
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