| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.66 | 85.66 | 90.83 | 90.83 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2453267884 |
| 90.05 | 4.39 | 93.58 | 2.75 | 87.80 | 4.88 | 100.00 | 0.00 | 89.29 | 14.29 | 84.44 | 4.44 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1062490178 |
| 91.17 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.202971645 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1691436770 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1835935414 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3560615516 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2840465001 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.575251290 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.178678753 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.652215681 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2847250640 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.538003984 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3731630181 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.3406925812 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.658706267 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2839281128 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.604763834 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1365345405 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4040659797 |
| /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.924246863 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1691436770 | Oct 09 02:07:12 AM UTC 24 | Oct 09 02:07:14 AM UTC 24 | 5662216 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.202971645 | Oct 09 02:07:12 AM UTC 24 | Oct 09 02:07:14 AM UTC 24 | 5276394 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.3406925812 | Oct 09 02:07:12 AM UTC 24 | Oct 09 02:07:14 AM UTC 24 | 4547468 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2453267884 | Oct 09 02:07:13 AM UTC 24 | Oct 09 02:07:15 AM UTC 24 | 4911776 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2839281128 | Oct 09 02:07:13 AM UTC 24 | Oct 09 02:07:15 AM UTC 24 | 5237620 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.658706267 | Oct 09 02:07:13 AM UTC 24 | Oct 09 02:07:15 AM UTC 24 | 4795666 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1365345405 | Oct 09 02:07:13 AM UTC 24 | Oct 09 02:07:15 AM UTC 24 | 4727714 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.604763834 | Oct 09 02:07:13 AM UTC 24 | Oct 09 02:07:15 AM UTC 24 | 4934635 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4040659797 | Oct 09 02:07:15 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 4350589 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.924246863 | Oct 09 02:07:15 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 4135504 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1062490178 | Oct 09 02:07:15 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 5106308 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3560615516 | Oct 09 02:07:16 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 4918617 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1835935414 | Oct 09 02:07:15 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 5270198 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2840465001 | Oct 09 02:07:16 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 4697033 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.575251290 | Oct 09 02:07:16 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 5062485 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.178678753 | Oct 09 02:07:16 AM UTC 24 | Oct 09 02:07:17 AM UTC 24 | 5308059 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.652215681 | Oct 09 02:07:17 AM UTC 24 | Oct 09 02:07:18 AM UTC 24 | 4750876 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2847250640 | Oct 09 02:07:18 AM UTC 24 | Oct 09 02:07:19 AM UTC 24 | 4626332 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3731630181 | Oct 09 02:07:18 AM UTC 24 | Oct 09 02:07:19 AM UTC 24 | 5413139 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.538003984 | Oct 09 02:07:18 AM UTC 24 | Oct 09 02:07:19 AM UTC 24 | 4918182 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2453267884 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4911776 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:13 AM UTC 24 |
| Finished | Oct 09 02:07:15 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453267884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.2453267884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1062490178 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5106308 ps |
| CPU time | 0.35 seconds |
| Started | Oct 09 02:07:15 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062490178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.1062490178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.202971645 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5276394 ps |
| CPU time | 0.57 seconds |
| Started | Oct 09 02:07:12 AM UTC 24 |
| Finished | Oct 09 02:07:14 AM UTC 24 |
| Peak memory | 155844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202971645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.prim_esc_test.202971645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1691436770 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5662216 ps |
| CPU time | 0.45 seconds |
| Started | Oct 09 02:07:12 AM UTC 24 |
| Finished | Oct 09 02:07:14 AM UTC 24 |
| Peak memory | 155232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691436770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.1691436770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1835935414 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5270198 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:15 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835935414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.1835935414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3560615516 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4918617 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:16 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560615516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.3560615516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2840465001 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4697033 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:16 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840465001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.2840465001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.575251290 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5062485 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:16 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575251290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.prim_esc_test.575251290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.178678753 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5308059 ps |
| CPU time | 0.36 seconds |
| Started | Oct 09 02:07:16 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178678753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.prim_esc_test.178678753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.652215681 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4750876 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:17 AM UTC 24 |
| Finished | Oct 09 02:07:18 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652215681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.prim_esc_test.652215681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2847250640 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4626332 ps |
| CPU time | 0.41 seconds |
| Started | Oct 09 02:07:18 AM UTC 24 |
| Finished | Oct 09 02:07:19 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847250640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.2847250640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.538003984 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4918182 ps |
| CPU time | 0.39 seconds |
| Started | Oct 09 02:07:18 AM UTC 24 |
| Finished | Oct 09 02:07:19 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538003984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 18.prim_esc_test.538003984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3731630181 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5413139 ps |
| CPU time | 0.36 seconds |
| Started | Oct 09 02:07:18 AM UTC 24 |
| Finished | Oct 09 02:07:19 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731630181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.3731630181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.3406925812 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4547468 ps |
| CPU time | 0.41 seconds |
| Started | Oct 09 02:07:12 AM UTC 24 |
| Finished | Oct 09 02:07:14 AM UTC 24 |
| Peak memory | 155536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406925812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.3406925812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.658706267 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4795666 ps |
| CPU time | 0.38 seconds |
| Started | Oct 09 02:07:13 AM UTC 24 |
| Finished | Oct 09 02:07:15 AM UTC 24 |
| Peak memory | 157188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658706267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.prim_esc_test.658706267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2839281128 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5237620 ps |
| CPU time | 0.35 seconds |
| Started | Oct 09 02:07:13 AM UTC 24 |
| Finished | Oct 09 02:07:15 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839281128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.2839281128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.604763834 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4934635 ps |
| CPU time | 0.4 seconds |
| Started | Oct 09 02:07:13 AM UTC 24 |
| Finished | Oct 09 02:07:15 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604763834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.prim_esc_test.604763834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1365345405 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4727714 ps |
| CPU time | 0.37 seconds |
| Started | Oct 09 02:07:13 AM UTC 24 |
| Finished | Oct 09 02:07:15 AM UTC 24 |
| Peak memory | 156972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365345405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.1365345405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4040659797 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4350589 ps |
| CPU time | 0.37 seconds |
| Started | Oct 09 02:07:15 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 155732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040659797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.4040659797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.924246863 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4135504 ps |
| CPU time | 0.34 seconds |
| Started | Oct 09 02:07:15 AM UTC 24 |
| Finished | Oct 09 02:07:17 AM UTC 24 |
| Peak memory | 155716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924246863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 9.prim_esc_test.924246863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/prim_esc-sim-vcs/9.prim_esc_test/latest |
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