| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.3468302613 |
| 88.86 | 1.71 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2434107276 |
| 90.57 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.296096148 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.1798460763 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3961991285 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1052498433 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.2440102005 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.740597624 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2252564692 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2567508629 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3099260816 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4219649436 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.1337767958 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1809385667 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.6652202 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3358081030 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2584799306 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2803632161 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.3107096978 |
| /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.263681723 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.6652202 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 5084181 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1809385667 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 5009607 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3358081030 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4790466 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.3107096978 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4357397 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2803632161 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4594285 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.3468302613 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4832691 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.1798460763 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4795890 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.263681723 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 5370710 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3961991285 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4308024 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2584799306 | Oct 11 09:10:43 PM UTC 24 | Oct 11 09:10:45 PM UTC 24 | 4891242 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.2440102005 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 4402907 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1052498433 | Oct 11 09:10:44 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 5524928 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2434107276 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 4848534 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.296096148 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 4448501 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.740597624 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 4718875 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2252564692 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 4304969 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3099260816 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 5265365 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2567508629 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 4381450 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4219649436 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 5224071 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.1337767958 | Oct 11 09:10:45 PM UTC 24 | Oct 11 09:10:46 PM UTC 24 | 5222275 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.3468302613 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4832691 ps |
| CPU time | 0.51 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 156048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468302613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.3468302613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2434107276 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4848534 ps |
| CPU time | 0.45 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434107276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.2434107276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.296096148 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4448501 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296096148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.prim_esc_test.296096148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.1798460763 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4795890 ps |
| CPU time | 0.38 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 156008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798460763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.1798460763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/9.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3961991285 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4308024 ps |
| CPU time | 0.66 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 156064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961991285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.3961991285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1052498433 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5524928 ps |
| CPU time | 0.4 seconds |
| Started | Oct 11 09:10:44 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052498433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.1052498433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.2440102005 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4402907 ps |
| CPU time | 0.36 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440102005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.2440102005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.740597624 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4718875 ps |
| CPU time | 0.38 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740597624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.prim_esc_test.740597624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2252564692 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4304969 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252564692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.2252564692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2567508629 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4381450 ps |
| CPU time | 0.41 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 155804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567508629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.2567508629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3099260816 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5265365 ps |
| CPU time | 0.37 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099260816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.3099260816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4219649436 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5224071 ps |
| CPU time | 0.38 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219649436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.4219649436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.1337767958 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5222275 ps |
| CPU time | 0.4 seconds |
| Started | Oct 11 09:10:45 PM UTC 24 |
| Finished | Oct 11 09:10:46 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337767958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.1337767958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1809385667 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5009607 ps |
| CPU time | 0.44 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 154944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809385667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.1809385667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.6652202 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5084181 ps |
| CPU time | 0.43 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 153680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6652202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.6652202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3358081030 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4790466 ps |
| CPU time | 0.42 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 155896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358081030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.3358081030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2584799306 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4891242 ps |
| CPU time | 0.46 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 154176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584799306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.2584799306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2803632161 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4594285 ps |
| CPU time | 0.4 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803632161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.2803632161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.3107096978 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4357397 ps |
| CPU time | 0.42 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107096978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.3107096978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.263681723 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5370710 ps |
| CPU time | 0.39 seconds |
| Started | Oct 11 09:10:43 PM UTC 24 |
| Finished | Oct 11 09:10:45 PM UTC 24 |
| Peak memory | 156028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263681723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.prim_esc_test.263681723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/prim_esc-sim-vcs/8.prim_esc_test/latest |
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