| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.06 | 86.06 | 90.83 | 90.83 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1108030955 |
| 89.45 | 3.39 | 93.58 | 2.75 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 4.44 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1285848293 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2652838370 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.2539106407 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1748152622 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3161434265 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.2748580496 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.120467029 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.357675194 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2083202558 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1812960136 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3825202818 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.999001333 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3216475552 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2371239353 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2151190666 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3206520207 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1914863489 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4219679780 |
| /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2050296604 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3216475552 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 4627364 ps | ||
| T2 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1108030955 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 5313212 ps | ||
| T3 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2151190666 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 5116476 ps | ||
| T15 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1914863489 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 4594658 ps | ||
| T11 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3206520207 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 4752221 ps | ||
| T4 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2050296604 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:24 AM UTC 25 | 4805899 ps | ||
| T8 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3161434265 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 4788105 ps | ||
| T12 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4219679780 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 5003512 ps | ||
| T16 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2371239353 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 5351929 ps | ||
| T13 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1748152622 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 4940521 ps | ||
| T6 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1285848293 | Feb 08 05:39:21 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 4954550 ps | ||
| T17 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.120467029 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 5004795 ps | ||
| T9 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.357675194 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 5147533 ps | ||
| T7 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.2748580496 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 4969462 ps | ||
| T5 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.2539106407 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 5397958 ps | ||
| T10 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2652838370 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:25 AM UTC 25 | 4924496 ps | ||
| T14 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2083202558 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:26 AM UTC 25 | 4649248 ps | ||
| T18 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.999001333 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:26 AM UTC 25 | 5161092 ps | ||
| T19 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1812960136 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:26 AM UTC 25 | 4887186 ps | ||
| T20 | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3825202818 | Feb 08 05:39:22 AM UTC 25 | Feb 08 05:39:26 AM UTC 25 | 5005816 ps |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1108030955 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5313212 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108030955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc _test.1108030955 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1285848293 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4954550 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285848293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc _test.1285848293 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2652838370 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4924496 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652838370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_es c_test.2652838370 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.2539106407 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5397958 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539106407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_es c_test.2539106407 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1748152622 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4940521 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748152622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_es c_test.1748152622 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3161434265 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4788105 ps |
| CPU time | 0.4 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161434265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc _test.3161434265 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.2748580496 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4969462 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748580496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_es c_test.2748580496 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.120467029 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5004795 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120467029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc _test.120467029 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.357675194 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5147533 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357675194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc _test.357675194 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2083202558 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4649248 ps |
| CPU time | 0.35 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:26 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083202558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_es c_test.2083202558 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1812960136 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4887186 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:26 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812960136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_es c_test.1812960136 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3825202818 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5005816 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:26 AM UTC 25 |
| Peak memory | 156080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825202818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_es c_test.3825202818 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.999001333 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5161092 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:26 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999001333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc _test.999001333 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3216475552 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4627364 ps |
| CPU time | 0.33 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 156140 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216475552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc _test.3216475552 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2371239353 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5351929 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371239353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc _test.2371239353 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2151190666 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5116476 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151190666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc _test.2151190666 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3206520207 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4752221 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:21 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206520207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc _test.3206520207 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1914863489 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4594658 ps |
| CPU time | 0.38 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914863489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc _test.1914863489 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4219679780 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5003512 ps |
| CPU time | 0.34 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:25 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219679780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc _test.4219679780 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2050296604 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4805899 ps |
| CPU time | 0.36 seconds |
| Started | Feb 08 05:39:22 AM UTC 25 |
| Finished | Feb 08 05:39:24 AM UTC 25 |
| Peak memory | 156076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050296604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc _test.2050296604 |
| Directory | /workspaces/repo/scratch/os_regression/prim_esc-sim-vcs/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |