| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2777533513 |
| 89.45 | 1.71 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3333951624 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3259630329 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.417346489 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1262399765 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2613362497 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2459033370 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.999971482 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2261645420 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2267080569 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3889379641 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2490861393 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3496797555 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.4048238747 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1817853608 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3488890631 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1672322451 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.775957409 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.2451163022 |
| /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3386700612 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1262399765 | Oct 15 06:20:35 AM UTC 24 | Oct 15 06:20:36 AM UTC 24 | 5046146 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2613362497 | Oct 15 06:20:37 AM UTC 24 | Oct 15 06:20:38 AM UTC 24 | 4988366 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.4048238747 | Oct 15 06:20:39 AM UTC 24 | Oct 15 06:20:40 AM UTC 24 | 4933189 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1817853608 | Oct 15 06:20:40 AM UTC 24 | Oct 15 06:20:41 AM UTC 24 | 4407996 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3488890631 | Oct 15 06:20:41 AM UTC 24 | Oct 15 06:20:42 AM UTC 24 | 5282813 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2777533513 | Oct 15 06:20:41 AM UTC 24 | Oct 15 06:20:42 AM UTC 24 | 4781008 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1672322451 | Oct 15 06:20:42 AM UTC 24 | Oct 15 06:20:43 AM UTC 24 | 4974950 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.775957409 | Oct 15 06:20:43 AM UTC 24 | Oct 15 06:20:45 AM UTC 24 | 4759431 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.2451163022 | Oct 15 06:20:43 AM UTC 24 | Oct 15 06:20:45 AM UTC 24 | 5048264 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3386700612 | Oct 15 06:20:44 AM UTC 24 | Oct 15 06:20:46 AM UTC 24 | 4736193 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2459033370 | Oct 15 06:20:45 AM UTC 24 | Oct 15 06:20:47 AM UTC 24 | 4955060 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3333951624 | Oct 15 06:20:45 AM UTC 24 | Oct 15 06:20:47 AM UTC 24 | 4962762 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.999971482 | Oct 15 06:20:46 AM UTC 24 | Oct 15 06:20:48 AM UTC 24 | 5177153 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2261645420 | Oct 15 06:20:47 AM UTC 24 | Oct 15 06:20:49 AM UTC 24 | 4695840 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3259630329 | Oct 15 06:20:47 AM UTC 24 | Oct 15 06:20:49 AM UTC 24 | 4507659 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2267080569 | Oct 15 06:20:48 AM UTC 24 | Oct 15 06:20:50 AM UTC 24 | 5205025 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.417346489 | Oct 15 06:20:50 AM UTC 24 | Oct 15 06:20:51 AM UTC 24 | 4658989 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3889379641 | Oct 15 06:20:50 AM UTC 24 | Oct 15 06:20:51 AM UTC 24 | 4813782 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2490861393 | Oct 15 06:20:51 AM UTC 24 | Oct 15 06:20:52 AM UTC 24 | 4919805 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3496797555 | Oct 15 06:20:52 AM UTC 24 | Oct 15 06:20:53 AM UTC 24 | 4840914 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2777533513 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4781008 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 06:20:41 AM UTC 24 |
| Finished | Oct 15 06:20:42 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777533513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.2777533513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3333951624 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4962762 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 06:20:45 AM UTC 24 |
| Finished | Oct 15 06:20:47 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333951624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.3333951624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3259630329 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4507659 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 06:20:47 AM UTC 24 |
| Finished | Oct 15 06:20:49 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259630329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.3259630329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.417346489 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4658989 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 06:20:50 AM UTC 24 |
| Finished | Oct 15 06:20:51 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417346489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.prim_esc_test.417346489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1262399765 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5046146 ps |
| CPU time | 0.48 seconds |
| Started | Oct 15 06:20:35 AM UTC 24 |
| Finished | Oct 15 06:20:36 AM UTC 24 |
| Peak memory | 156144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262399765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.1262399765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2613362497 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4988366 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 06:20:37 AM UTC 24 |
| Finished | Oct 15 06:20:38 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613362497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.2613362497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2459033370 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4955060 ps |
| CPU time | 0.49 seconds |
| Started | Oct 15 06:20:45 AM UTC 24 |
| Finished | Oct 15 06:20:47 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459033370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.2459033370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.999971482 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5177153 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 06:20:46 AM UTC 24 |
| Finished | Oct 15 06:20:48 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999971482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.prim_esc_test.999971482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2261645420 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4695840 ps |
| CPU time | 0.51 seconds |
| Started | Oct 15 06:20:47 AM UTC 24 |
| Finished | Oct 15 06:20:49 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261645420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.2261645420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2267080569 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5205025 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 06:20:48 AM UTC 24 |
| Finished | Oct 15 06:20:50 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267080569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.2267080569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3889379641 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4813782 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 06:20:50 AM UTC 24 |
| Finished | Oct 15 06:20:51 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889379641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.3889379641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2490861393 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4919805 ps |
| CPU time | 0.55 seconds |
| Started | Oct 15 06:20:51 AM UTC 24 |
| Finished | Oct 15 06:20:52 AM UTC 24 |
| Peak memory | 156068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490861393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.2490861393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3496797555 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4840914 ps |
| CPU time | 0.56 seconds |
| Started | Oct 15 06:20:52 AM UTC 24 |
| Finished | Oct 15 06:20:53 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496797555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.3496797555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.4048238747 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4933189 ps |
| CPU time | 0.56 seconds |
| Started | Oct 15 06:20:39 AM UTC 24 |
| Finished | Oct 15 06:20:40 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048238747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.4048238747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1817853608 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4407996 ps |
| CPU time | 0.56 seconds |
| Started | Oct 15 06:20:40 AM UTC 24 |
| Finished | Oct 15 06:20:41 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817853608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.1817853608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3488890631 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5282813 ps |
| CPU time | 0.53 seconds |
| Started | Oct 15 06:20:41 AM UTC 24 |
| Finished | Oct 15 06:20:42 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488890631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.3488890631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1672322451 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4974950 ps |
| CPU time | 0.52 seconds |
| Started | Oct 15 06:20:42 AM UTC 24 |
| Finished | Oct 15 06:20:43 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672322451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.1672322451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.775957409 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4759431 ps |
| CPU time | 0.54 seconds |
| Started | Oct 15 06:20:43 AM UTC 24 |
| Finished | Oct 15 06:20:45 AM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775957409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.prim_esc_test.775957409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.2451163022 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5048264 ps |
| CPU time | 0.47 seconds |
| Started | Oct 15 06:20:43 AM UTC 24 |
| Finished | Oct 15 06:20:45 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451163022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.2451163022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3386700612 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4736193 ps |
| CPU time | 0.5 seconds |
| Started | Oct 15 06:20:44 AM UTC 24 |
| Finished | Oct 15 06:20:46 AM UTC 24 |
| Peak memory | 156060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386700612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.3386700612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_esc-sim-vcs/9.prim_esc_test/latest |
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