ASSERT | PROPERTIES | SEQUENCES | |
Total | 17 | 0 | 0 |
Category 0 | 17 | 0 | 0 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 17 | 0 | 0 |
Severity 0 | 17 | 0 | 0 |
NUMBER | PERCENT | |
Total Number | 17 | 100.00 |
Uncovered | 3 | 17.65 |
Success | 14 | 82.35 |
Failure | 0 | 0.00 |
Incomplete | 1 | 5.88 |
Without Attempts | 1 | 5.88 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_ext_seed_sva.ExtDefaultSeedInputCheck_A | 0 | 0 | 838865610 | 0 | 0 | 0 | |
prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_lockup_mechanism_sva.LfsrLockupCheck_A | 0 | 0 | 838865610 | 0 | 0 | 0 | |
prim_lfsr_tb.gen_duts[24].i_prim_lfsr.p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A | 0 | 0 | 0 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
prim_lfsr_tb.gen_duts[24].i_prim_lfsr.NextStateCheck_A | 0 | 0 | 838865610 | 838860750 | 0 | 50 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
prim_lfsr_tb.gen_duts[24].i_prim_lfsr.p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A | 0 | 0 | 0 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |