| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 89.17 | 97.92 | 73.91 | 100.00 | 91.67 | 82.35 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.20 | 86.20 | 97.87 | 97.87 | 59.09 | 59.09 | 100.00 | 100.00 | 91.67 | 91.67 | 82.35 | 82.35 | /workspace/coverage/prim_lfsr_dw_24/11.prim_lfsr_test.1794549237 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24/0.prim_lfsr_test.2606359146 |
| /workspace/coverage/prim_lfsr_dw_24/1.prim_lfsr_test.1876653812 |
| /workspace/coverage/prim_lfsr_dw_24/10.prim_lfsr_test.1915661765 |
| /workspace/coverage/prim_lfsr_dw_24/12.prim_lfsr_test.924117722 |
| /workspace/coverage/prim_lfsr_dw_24/13.prim_lfsr_test.2271076329 |
| /workspace/coverage/prim_lfsr_dw_24/14.prim_lfsr_test.1348638352 |
| /workspace/coverage/prim_lfsr_dw_24/15.prim_lfsr_test.2740625906 |
| /workspace/coverage/prim_lfsr_dw_24/16.prim_lfsr_test.2557450346 |
| /workspace/coverage/prim_lfsr_dw_24/17.prim_lfsr_test.3319841580 |
| /workspace/coverage/prim_lfsr_dw_24/18.prim_lfsr_test.3272254702 |
| /workspace/coverage/prim_lfsr_dw_24/19.prim_lfsr_test.3823523800 |
| /workspace/coverage/prim_lfsr_dw_24/2.prim_lfsr_test.2816541761 |
| /workspace/coverage/prim_lfsr_dw_24/20.prim_lfsr_test.574050671 |
| /workspace/coverage/prim_lfsr_dw_24/21.prim_lfsr_test.1580031289 |
| /workspace/coverage/prim_lfsr_dw_24/22.prim_lfsr_test.726729132 |
| /workspace/coverage/prim_lfsr_dw_24/23.prim_lfsr_test.4122477653 |
| /workspace/coverage/prim_lfsr_dw_24/24.prim_lfsr_test.407305950 |
| /workspace/coverage/prim_lfsr_dw_24/25.prim_lfsr_test.3494672343 |
| /workspace/coverage/prim_lfsr_dw_24/26.prim_lfsr_test.527958552 |
| /workspace/coverage/prim_lfsr_dw_24/27.prim_lfsr_test.2742441409 |
| /workspace/coverage/prim_lfsr_dw_24/28.prim_lfsr_test.520721113 |
| /workspace/coverage/prim_lfsr_dw_24/29.prim_lfsr_test.3242944105 |
| /workspace/coverage/prim_lfsr_dw_24/3.prim_lfsr_test.956858945 |
| /workspace/coverage/prim_lfsr_dw_24/30.prim_lfsr_test.1592227313 |
| /workspace/coverage/prim_lfsr_dw_24/31.prim_lfsr_test.10355366 |
| /workspace/coverage/prim_lfsr_dw_24/32.prim_lfsr_test.2272026033 |
| /workspace/coverage/prim_lfsr_dw_24/33.prim_lfsr_test.1536593742 |
| /workspace/coverage/prim_lfsr_dw_24/34.prim_lfsr_test.1895233812 |
| /workspace/coverage/prim_lfsr_dw_24/35.prim_lfsr_test.2583960634 |
| /workspace/coverage/prim_lfsr_dw_24/36.prim_lfsr_test.29669444 |
| /workspace/coverage/prim_lfsr_dw_24/37.prim_lfsr_test.3926017291 |
| /workspace/coverage/prim_lfsr_dw_24/38.prim_lfsr_test.1895617315 |
| /workspace/coverage/prim_lfsr_dw_24/39.prim_lfsr_test.3780470237 |
| /workspace/coverage/prim_lfsr_dw_24/4.prim_lfsr_test.3203444611 |
| /workspace/coverage/prim_lfsr_dw_24/40.prim_lfsr_test.1921782528 |
| /workspace/coverage/prim_lfsr_dw_24/41.prim_lfsr_test.1238872958 |
| /workspace/coverage/prim_lfsr_dw_24/42.prim_lfsr_test.4242697946 |
| /workspace/coverage/prim_lfsr_dw_24/43.prim_lfsr_test.3873198100 |
| /workspace/coverage/prim_lfsr_dw_24/44.prim_lfsr_test.3636040307 |
| /workspace/coverage/prim_lfsr_dw_24/45.prim_lfsr_test.4266173246 |
| /workspace/coverage/prim_lfsr_dw_24/46.prim_lfsr_test.2123372017 |
| /workspace/coverage/prim_lfsr_dw_24/47.prim_lfsr_test.618347994 |
| /workspace/coverage/prim_lfsr_dw_24/48.prim_lfsr_test.951004171 |
| /workspace/coverage/prim_lfsr_dw_24/49.prim_lfsr_test.3604218157 |
| /workspace/coverage/prim_lfsr_dw_24/5.prim_lfsr_test.3569606178 |
| /workspace/coverage/prim_lfsr_dw_24/6.prim_lfsr_test.838284733 |
| /workspace/coverage/prim_lfsr_dw_24/7.prim_lfsr_test.1427437006 |
| /workspace/coverage/prim_lfsr_dw_24/8.prim_lfsr_test.2019411846 |
| /workspace/coverage/prim_lfsr_dw_24/9.prim_lfsr_test.2905005109 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_24/3.prim_lfsr_test.956858945 | May 28 04:26:37 AM PDT 23 | May 28 05:03:07 AM PDT 23 | 335546490000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_24/12.prim_lfsr_test.924117722 | May 28 04:27:18 AM PDT 23 | May 28 04:54:42 AM PDT 23 | 335546570000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_24/26.prim_lfsr_test.527958552 | May 28 04:27:15 AM PDT 23 | May 28 04:55:00 AM PDT 23 | 335546570000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_24/15.prim_lfsr_test.2740625906 | May 28 04:27:13 AM PDT 23 | May 28 04:55:59 AM PDT 23 | 335545790000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24/16.prim_lfsr_test.2557450346 | May 28 04:27:14 AM PDT 23 | May 28 04:54:57 AM PDT 23 | 335546510000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24/11.prim_lfsr_test.1794549237 | May 28 04:27:15 AM PDT 23 | May 28 04:56:06 AM PDT 23 | 335546730000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_24/33.prim_lfsr_test.1536593742 | May 28 04:27:13 AM PDT 23 | May 28 04:56:18 AM PDT 23 | 335546530000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_24/34.prim_lfsr_test.1895233812 | May 28 04:27:16 AM PDT 23 | May 28 04:54:28 AM PDT 23 | 335546030000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_24/2.prim_lfsr_test.2816541761 | May 28 04:26:41 AM PDT 23 | May 28 04:51:31 AM PDT 23 | 335546190000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_24/8.prim_lfsr_test.2019411846 | May 28 04:27:16 AM PDT 23 | May 28 04:53:23 AM PDT 23 | 335546530000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_24/35.prim_lfsr_test.2583960634 | May 28 04:29:43 AM PDT 23 | May 28 04:58:32 AM PDT 23 | 335546330000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_24/29.prim_lfsr_test.3242944105 | May 28 04:27:17 AM PDT 23 | May 28 04:54:16 AM PDT 23 | 335546170000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_24/13.prim_lfsr_test.2271076329 | May 28 04:27:13 AM PDT 23 | May 28 04:51:26 AM PDT 23 | 335546030000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24/44.prim_lfsr_test.3636040307 | May 28 04:29:57 AM PDT 23 | May 28 04:57:17 AM PDT 23 | 335546750000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24/40.prim_lfsr_test.1921782528 | May 28 04:29:58 AM PDT 23 | May 28 04:57:38 AM PDT 23 | 335546570000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24/32.prim_lfsr_test.2272026033 | May 28 04:27:19 AM PDT 23 | May 28 05:03:32 AM PDT 23 | 335546670000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24/39.prim_lfsr_test.3780470237 | May 28 04:27:52 AM PDT 23 | May 28 04:54:56 AM PDT 23 | 335546470000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24/18.prim_lfsr_test.3272254702 | May 28 04:27:14 AM PDT 23 | May 28 04:52:44 AM PDT 23 | 335546030000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24/20.prim_lfsr_test.574050671 | May 28 04:27:17 AM PDT 23 | May 28 04:54:31 AM PDT 23 | 335546510000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24/5.prim_lfsr_test.3569606178 | May 28 04:26:37 AM PDT 23 | May 28 05:03:16 AM PDT 23 | 335545690000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24/48.prim_lfsr_test.951004171 | May 28 04:29:59 AM PDT 23 | May 28 04:59:00 AM PDT 23 | 335546170000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24/7.prim_lfsr_test.1427437006 | May 28 04:27:14 AM PDT 23 | May 28 04:52:43 AM PDT 23 | 335545990000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24/19.prim_lfsr_test.3823523800 | May 28 04:27:14 AM PDT 23 | May 28 04:52:23 AM PDT 23 | 335546070000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24/23.prim_lfsr_test.4122477653 | May 28 04:27:15 AM PDT 23 | May 28 04:54:34 AM PDT 23 | 335546430000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24/38.prim_lfsr_test.1895617315 | May 28 04:29:44 AM PDT 23 | May 28 04:58:51 AM PDT 23 | 335545830000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24/0.prim_lfsr_test.2606359146 | May 28 04:26:30 AM PDT 23 | May 28 04:54:11 AM PDT 23 | 335546590000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24/30.prim_lfsr_test.1592227313 | May 28 04:27:13 AM PDT 23 | May 28 04:52:21 AM PDT 23 | 335546050000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24/42.prim_lfsr_test.4242697946 | May 28 04:29:57 AM PDT 23 | May 28 04:56:03 AM PDT 23 | 335546170000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24/28.prim_lfsr_test.520721113 | May 28 04:27:15 AM PDT 23 | May 28 04:55:35 AM PDT 23 | 335545770000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24/45.prim_lfsr_test.4266173246 | May 28 04:29:58 AM PDT 23 | May 28 04:56:42 AM PDT 23 | 335546450000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24/9.prim_lfsr_test.2905005109 | May 28 04:27:19 AM PDT 23 | May 28 04:53:43 AM PDT 23 | 335546590000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24/24.prim_lfsr_test.407305950 | May 28 04:27:15 AM PDT 23 | May 28 04:56:00 AM PDT 23 | 335546750000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24/25.prim_lfsr_test.3494672343 | May 28 04:27:13 AM PDT 23 | May 28 04:54:18 AM PDT 23 | 335546090000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24/41.prim_lfsr_test.1238872958 | May 28 04:30:01 AM PDT 23 | May 28 04:54:51 AM PDT 23 | 335545790000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24/6.prim_lfsr_test.838284733 | May 28 04:27:18 AM PDT 23 | May 28 05:03:27 AM PDT 23 | 335546210000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24/49.prim_lfsr_test.3604218157 | May 28 04:30:03 AM PDT 23 | May 28 04:53:25 AM PDT 23 | 335545930000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24/36.prim_lfsr_test.29669444 | May 28 04:29:44 AM PDT 23 | May 28 04:56:05 AM PDT 23 | 335545930000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24/10.prim_lfsr_test.1915661765 | May 28 04:27:15 AM PDT 23 | May 28 04:54:51 AM PDT 23 | 335546070000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24/27.prim_lfsr_test.2742441409 | May 28 04:27:15 AM PDT 23 | May 28 04:55:47 AM PDT 23 | 335546450000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24/4.prim_lfsr_test.3203444611 | May 28 04:26:34 AM PDT 23 | May 28 04:52:12 AM PDT 23 | 335545950000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_24/14.prim_lfsr_test.1348638352 | May 28 04:27:15 AM PDT 23 | May 28 04:54:47 AM PDT 23 | 335546230000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_24/1.prim_lfsr_test.1876653812 | May 28 04:26:35 AM PDT 23 | May 28 04:54:38 AM PDT 23 | 335546430000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_24/43.prim_lfsr_test.3873198100 | May 28 04:30:00 AM PDT 23 | May 28 04:58:41 AM PDT 23 | 335546250000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_24/22.prim_lfsr_test.726729132 | May 28 04:27:13 AM PDT 23 | May 28 04:51:45 AM PDT 23 | 335546710000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_24/47.prim_lfsr_test.618347994 | May 28 04:30:04 AM PDT 23 | May 28 04:57:43 AM PDT 23 | 335545830000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_24/46.prim_lfsr_test.2123372017 | May 28 04:28:39 AM PDT 23 | May 28 04:54:23 AM PDT 23 | 335546070000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_24/31.prim_lfsr_test.10355366 | May 28 04:27:13 AM PDT 23 | May 28 04:53:06 AM PDT 23 | 335545830000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_24/21.prim_lfsr_test.1580031289 | May 28 04:27:14 AM PDT 23 | May 28 04:53:54 AM PDT 23 | 335546830000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_24/17.prim_lfsr_test.3319841580 | May 28 04:27:16 AM PDT 23 | May 28 04:53:45 AM PDT 23 | 335546850000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_24/37.prim_lfsr_test.3926017291 | May 28 04:29:45 AM PDT 23 | May 28 04:56:19 AM PDT 23 | 335546170000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_24/11.prim_lfsr_test.1794549237 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 335546730000 ps |
| CPU time | 717.89 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:56:06 AM PDT 23 |
| Peak memory | 160788 kb |
| Host | smart-a5a1f837-73ce-4517-929c-e71c5b58ce09 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1794549237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_test.1794549237 |
| Directory | /workspace/11.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/0.prim_lfsr_test.2606359146 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 335546590000 ps |
| CPU time | 695.63 seconds |
| Started | May 28 04:26:30 AM PDT 23 |
| Finished | May 28 04:54:11 AM PDT 23 |
| Peak memory | 160908 kb |
| Host | smart-473e1824-fc65-40b4-b3fd-463eb2b274c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2606359146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_test.2606359146 |
| Directory | /workspace/0.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/1.prim_lfsr_test.1876653812 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 335546430000 ps |
| CPU time | 701.24 seconds |
| Started | May 28 04:26:35 AM PDT 23 |
| Finished | May 28 04:54:38 AM PDT 23 |
| Peak memory | 160968 kb |
| Host | smart-4b97771f-58d5-4bed-9a39-f4c510c60ebd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1876653812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_test.1876653812 |
| Directory | /workspace/1.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/10.prim_lfsr_test.1915661765 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 335546070000 ps |
| CPU time | 674.52 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:54:51 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-c32f08b2-86ce-4690-86e1-483f8d90afb9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1915661765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_test.1915661765 |
| Directory | /workspace/10.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/12.prim_lfsr_test.924117722 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 335546570000 ps |
| CPU time | 687.22 seconds |
| Started | May 28 04:27:18 AM PDT 23 |
| Finished | May 28 04:54:42 AM PDT 23 |
| Peak memory | 160872 kb |
| Host | smart-e8d57549-7f1c-48c8-8e61-98d6cbf7de19 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=924117722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_test.924117722 |
| Directory | /workspace/12.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/13.prim_lfsr_test.2271076329 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 335546030000 ps |
| CPU time | 589.72 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:51:26 AM PDT 23 |
| Peak memory | 160836 kb |
| Host | smart-2d91058b-8df3-4e2c-876a-682f6a2f4d3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2271076329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_test.2271076329 |
| Directory | /workspace/13.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/14.prim_lfsr_test.1348638352 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 335546230000 ps |
| CPU time | 681.52 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:54:47 AM PDT 23 |
| Peak memory | 161012 kb |
| Host | smart-f795bc82-178f-4a32-82a0-e3a95edfd4df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1348638352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_test.1348638352 |
| Directory | /workspace/14.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/15.prim_lfsr_test.2740625906 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 335545790000 ps |
| CPU time | 715.87 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:55:59 AM PDT 23 |
| Peak memory | 160888 kb |
| Host | smart-2f03cafe-5287-490b-8fdc-aaac89960e9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2740625906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_test.2740625906 |
| Directory | /workspace/15.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/16.prim_lfsr_test.2557450346 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 335546510000 ps |
| CPU time | 688.54 seconds |
| Started | May 28 04:27:14 AM PDT 23 |
| Finished | May 28 04:54:57 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-681fd02b-3fdb-462a-832f-ae6757c98525 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2557450346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_test.2557450346 |
| Directory | /workspace/16.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/17.prim_lfsr_test.3319841580 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 335546850000 ps |
| CPU time | 649.82 seconds |
| Started | May 28 04:27:16 AM PDT 23 |
| Finished | May 28 04:53:45 AM PDT 23 |
| Peak memory | 160980 kb |
| Host | smart-2a44cee2-87e7-402c-b296-7b1b49c73fde |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3319841580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_test.3319841580 |
| Directory | /workspace/17.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/18.prim_lfsr_test.3272254702 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 335546030000 ps |
| CPU time | 614.35 seconds |
| Started | May 28 04:27:14 AM PDT 23 |
| Finished | May 28 04:52:44 AM PDT 23 |
| Peak memory | 160772 kb |
| Host | smart-f1d85381-757b-4aef-9702-1ce8094110ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3272254702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_test.3272254702 |
| Directory | /workspace/18.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/19.prim_lfsr_test.3823523800 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 335546070000 ps |
| CPU time | 611.43 seconds |
| Started | May 28 04:27:14 AM PDT 23 |
| Finished | May 28 04:52:23 AM PDT 23 |
| Peak memory | 160792 kb |
| Host | smart-5100ea93-b4ed-4bcd-80f1-d4b1d814cf14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3823523800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_test.3823523800 |
| Directory | /workspace/19.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/2.prim_lfsr_test.2816541761 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 335546190000 ps |
| CPU time | 617.21 seconds |
| Started | May 28 04:26:41 AM PDT 23 |
| Finished | May 28 04:51:31 AM PDT 23 |
| Peak memory | 160780 kb |
| Host | smart-89bf190b-e893-4400-9f7a-fe2d22dbbd52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2816541761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_test.2816541761 |
| Directory | /workspace/2.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/20.prim_lfsr_test.574050671 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 335546510000 ps |
| CPU time | 685.83 seconds |
| Started | May 28 04:27:17 AM PDT 23 |
| Finished | May 28 04:54:31 AM PDT 23 |
| Peak memory | 160972 kb |
| Host | smart-f51e83ed-c016-40df-9f63-71a451fe20ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=574050671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_test.574050671 |
| Directory | /workspace/20.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/21.prim_lfsr_test.1580031289 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 335546830000 ps |
| CPU time | 660.88 seconds |
| Started | May 28 04:27:14 AM PDT 23 |
| Finished | May 28 04:53:54 AM PDT 23 |
| Peak memory | 160864 kb |
| Host | smart-5b32fe7f-4dc6-464e-ab8c-98bc60187514 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1580031289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_test.1580031289 |
| Directory | /workspace/21.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/22.prim_lfsr_test.726729132 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 335546710000 ps |
| CPU time | 613.24 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:51:45 AM PDT 23 |
| Peak memory | 160876 kb |
| Host | smart-c595fa5b-06d3-40e2-af92-bc5dce7e79be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=726729132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_test.726729132 |
| Directory | /workspace/22.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/23.prim_lfsr_test.4122477653 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 335546430000 ps |
| CPU time | 683.02 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:54:34 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-600e3bea-434d-4b8e-832e-f10a5c5c8c45 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4122477653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_test.4122477653 |
| Directory | /workspace/23.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/24.prim_lfsr_test.407305950 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 335546750000 ps |
| CPU time | 706.46 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:56:00 AM PDT 23 |
| Peak memory | 160992 kb |
| Host | smart-76359b0b-0e43-4236-88cb-5931f4a2a4f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=407305950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_test.407305950 |
| Directory | /workspace/24.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/25.prim_lfsr_test.3494672343 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 335546090000 ps |
| CPU time | 660.02 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:54:18 AM PDT 23 |
| Peak memory | 160888 kb |
| Host | smart-f41de917-48ae-4d59-8d90-a11d249418ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3494672343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_test.3494672343 |
| Directory | /workspace/25.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/26.prim_lfsr_test.527958552 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 335546570000 ps |
| CPU time | 687.23 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:55:00 AM PDT 23 |
| Peak memory | 160968 kb |
| Host | smart-82d49045-de2a-4a5b-9eb7-1c0419686d01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=527958552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_test.527958552 |
| Directory | /workspace/26.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/27.prim_lfsr_test.2742441409 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 335546450000 ps |
| CPU time | 723.92 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:55:47 AM PDT 23 |
| Peak memory | 160888 kb |
| Host | smart-e51028ca-76da-41b9-809c-979b3f66fabf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2742441409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_test.2742441409 |
| Directory | /workspace/27.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/28.prim_lfsr_test.520721113 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 335545770000 ps |
| CPU time | 711.78 seconds |
| Started | May 28 04:27:15 AM PDT 23 |
| Finished | May 28 04:55:35 AM PDT 23 |
| Peak memory | 160964 kb |
| Host | smart-020a216f-0847-476d-90e4-e99ffa068b00 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=520721113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_test.520721113 |
| Directory | /workspace/28.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/29.prim_lfsr_test.3242944105 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 335546170000 ps |
| CPU time | 673.63 seconds |
| Started | May 28 04:27:17 AM PDT 23 |
| Finished | May 28 04:54:16 AM PDT 23 |
| Peak memory | 160896 kb |
| Host | smart-bd80ace6-dc67-43ae-ae77-20bed4987133 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3242944105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_test.3242944105 |
| Directory | /workspace/29.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/3.prim_lfsr_test.956858945 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 335546490000 ps |
| CPU time | 926.46 seconds |
| Started | May 28 04:26:37 AM PDT 23 |
| Finished | May 28 05:03:07 AM PDT 23 |
| Peak memory | 160976 kb |
| Host | smart-490efa86-aa5b-4139-ba83-e5d9e32f3b98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=956858945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_test.956858945 |
| Directory | /workspace/3.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/30.prim_lfsr_test.1592227313 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 335546050000 ps |
| CPU time | 614.46 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:52:21 AM PDT 23 |
| Peak memory | 160852 kb |
| Host | smart-a3700cda-2b8c-499e-aed5-6da7e688e2d2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1592227313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_test.1592227313 |
| Directory | /workspace/30.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/31.prim_lfsr_test.10355366 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 335545830000 ps |
| CPU time | 628.39 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:53:06 AM PDT 23 |
| Peak memory | 160972 kb |
| Host | smart-a93457d3-65c3-4ca6-aafc-3931892a38f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=10355366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_test.10355366 |
| Directory | /workspace/31.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/32.prim_lfsr_test.2272026033 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 335546670000 ps |
| CPU time | 932.56 seconds |
| Started | May 28 04:27:19 AM PDT 23 |
| Finished | May 28 05:03:32 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-f70b7514-5371-4c9e-9677-cdcf3c5110b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2272026033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_test.2272026033 |
| Directory | /workspace/32.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/33.prim_lfsr_test.1536593742 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 335546530000 ps |
| CPU time | 726.45 seconds |
| Started | May 28 04:27:13 AM PDT 23 |
| Finished | May 28 04:56:18 AM PDT 23 |
| Peak memory | 160808 kb |
| Host | smart-60ce765b-44b6-434c-bd40-8119724366d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1536593742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_test.1536593742 |
| Directory | /workspace/33.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/34.prim_lfsr_test.1895233812 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 335546030000 ps |
| CPU time | 673.45 seconds |
| Started | May 28 04:27:16 AM PDT 23 |
| Finished | May 28 04:54:28 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-2ef0b562-1fac-43d3-836a-199158fcc48e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1895233812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_test.1895233812 |
| Directory | /workspace/34.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/35.prim_lfsr_test.2583960634 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 335546330000 ps |
| CPU time | 716.13 seconds |
| Started | May 28 04:29:43 AM PDT 23 |
| Finished | May 28 04:58:32 AM PDT 23 |
| Peak memory | 160788 kb |
| Host | smart-2a49b755-2051-4deb-a372-a05a8b82f1e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2583960634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_test.2583960634 |
| Directory | /workspace/35.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/36.prim_lfsr_test.29669444 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 335545930000 ps |
| CPU time | 657.63 seconds |
| Started | May 28 04:29:44 AM PDT 23 |
| Finished | May 28 04:56:05 AM PDT 23 |
| Peak memory | 160868 kb |
| Host | smart-4e019404-e9ed-48ec-a9e1-bed8ed13f5ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=29669444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_test.29669444 |
| Directory | /workspace/36.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/37.prim_lfsr_test.3926017291 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 335546170000 ps |
| CPU time | 646.82 seconds |
| Started | May 28 04:29:45 AM PDT 23 |
| Finished | May 28 04:56:19 AM PDT 23 |
| Peak memory | 160936 kb |
| Host | smart-83fbb134-cdd3-4fba-9f2b-a7d602a02e2d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3926017291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_test.3926017291 |
| Directory | /workspace/37.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/38.prim_lfsr_test.1895617315 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 335545830000 ps |
| CPU time | 720.51 seconds |
| Started | May 28 04:29:44 AM PDT 23 |
| Finished | May 28 04:58:51 AM PDT 23 |
| Peak memory | 160808 kb |
| Host | smart-4bbcead5-05cd-44c1-81c4-8f64ebf1af9a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1895617315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_test.1895617315 |
| Directory | /workspace/38.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/39.prim_lfsr_test.3780470237 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 335546470000 ps |
| CPU time | 664.9 seconds |
| Started | May 28 04:27:52 AM PDT 23 |
| Finished | May 28 04:54:56 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-4eea342d-9fcb-4788-8496-8f2b3f93dd6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3780470237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_test.3780470237 |
| Directory | /workspace/39.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/4.prim_lfsr_test.3203444611 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 335545950000 ps |
| CPU time | 637.87 seconds |
| Started | May 28 04:26:34 AM PDT 23 |
| Finished | May 28 04:52:12 AM PDT 23 |
| Peak memory | 160960 kb |
| Host | smart-f3ddbca7-85cf-4eb0-a5e4-45130ab65936 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3203444611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_test.3203444611 |
| Directory | /workspace/4.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/40.prim_lfsr_test.1921782528 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 335546570000 ps |
| CPU time | 678.52 seconds |
| Started | May 28 04:29:58 AM PDT 23 |
| Finished | May 28 04:57:38 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-0579d1ca-1382-49e4-9dd9-5ff19c670915 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1921782528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_test.1921782528 |
| Directory | /workspace/40.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/41.prim_lfsr_test.1238872958 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 335545790000 ps |
| CPU time | 598.67 seconds |
| Started | May 28 04:30:01 AM PDT 23 |
| Finished | May 28 04:54:51 AM PDT 23 |
| Peak memory | 160904 kb |
| Host | smart-020dcf54-d2ea-4f56-8dee-b4ab66dd59f0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1238872958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_test.1238872958 |
| Directory | /workspace/41.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/42.prim_lfsr_test.4242697946 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 335546170000 ps |
| CPU time | 639.36 seconds |
| Started | May 28 04:29:57 AM PDT 23 |
| Finished | May 28 04:56:03 AM PDT 23 |
| Peak memory | 160980 kb |
| Host | smart-42841059-3fcc-424f-85cc-cf0558ce2613 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4242697946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_test.4242697946 |
| Directory | /workspace/42.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/43.prim_lfsr_test.3873198100 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 335546250000 ps |
| CPU time | 713.86 seconds |
| Started | May 28 04:30:00 AM PDT 23 |
| Finished | May 28 04:58:41 AM PDT 23 |
| Peak memory | 160788 kb |
| Host | smart-0b93ff30-7d2e-4b61-ab9d-21f7117a3126 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3873198100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_test.3873198100 |
| Directory | /workspace/43.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/44.prim_lfsr_test.3636040307 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 335546750000 ps |
| CPU time | 673.91 seconds |
| Started | May 28 04:29:57 AM PDT 23 |
| Finished | May 28 04:57:17 AM PDT 23 |
| Peak memory | 160836 kb |
| Host | smart-0ff85fda-b433-471b-a668-331a4842c0dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3636040307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_test.3636040307 |
| Directory | /workspace/44.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/45.prim_lfsr_test.4266173246 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 335546450000 ps |
| CPU time | 652.62 seconds |
| Started | May 28 04:29:58 AM PDT 23 |
| Finished | May 28 04:56:42 AM PDT 23 |
| Peak memory | 160900 kb |
| Host | smart-d4e12428-aeed-44d1-ad22-24d448f1d9dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4266173246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_test.4266173246 |
| Directory | /workspace/45.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/46.prim_lfsr_test.2123372017 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 335546070000 ps |
| CPU time | 631.57 seconds |
| Started | May 28 04:28:39 AM PDT 23 |
| Finished | May 28 04:54:23 AM PDT 23 |
| Peak memory | 160892 kb |
| Host | smart-2a1bd9c6-7ce9-4034-b6d5-7c555f099457 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2123372017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_test.2123372017 |
| Directory | /workspace/46.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/47.prim_lfsr_test.618347994 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 335545830000 ps |
| CPU time | 689.85 seconds |
| Started | May 28 04:30:04 AM PDT 23 |
| Finished | May 28 04:57:43 AM PDT 23 |
| Peak memory | 160964 kb |
| Host | smart-48028c51-70b9-4f79-884e-fabd57993fdc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=618347994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_test.618347994 |
| Directory | /workspace/47.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/48.prim_lfsr_test.951004171 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 335546170000 ps |
| CPU time | 729.48 seconds |
| Started | May 28 04:29:59 AM PDT 23 |
| Finished | May 28 04:59:00 AM PDT 23 |
| Peak memory | 160820 kb |
| Host | smart-c5d31def-2589-4e9b-846b-433d6a88df9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=951004171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_test.951004171 |
| Directory | /workspace/48.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/49.prim_lfsr_test.3604218157 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 335545930000 ps |
| CPU time | 571.87 seconds |
| Started | May 28 04:30:03 AM PDT 23 |
| Finished | May 28 04:53:25 AM PDT 23 |
| Peak memory | 160848 kb |
| Host | smart-5a9c09b2-46dc-4231-a8dd-6025259d6740 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3604218157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_test.3604218157 |
| Directory | /workspace/49.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/5.prim_lfsr_test.3569606178 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 335545690000 ps |
| CPU time | 938 seconds |
| Started | May 28 04:26:37 AM PDT 23 |
| Finished | May 28 05:03:16 AM PDT 23 |
| Peak memory | 160976 kb |
| Host | smart-76fb8048-8152-4f37-96dc-18102f0d3f52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3569606178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_test.3569606178 |
| Directory | /workspace/5.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/6.prim_lfsr_test.838284733 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 335546210000 ps |
| CPU time | 919.78 seconds |
| Started | May 28 04:27:18 AM PDT 23 |
| Finished | May 28 05:03:27 AM PDT 23 |
| Peak memory | 160976 kb |
| Host | smart-a7daf9d9-5c81-46b8-a168-49c7097eacff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=838284733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_test.838284733 |
| Directory | /workspace/6.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/7.prim_lfsr_test.1427437006 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 335545990000 ps |
| CPU time | 622.39 seconds |
| Started | May 28 04:27:14 AM PDT 23 |
| Finished | May 28 04:52:43 AM PDT 23 |
| Peak memory | 160960 kb |
| Host | smart-5719cafb-fb3d-472e-9c9f-2a94fceb441c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1427437006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_test.1427437006 |
| Directory | /workspace/7.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/8.prim_lfsr_test.2019411846 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 335546530000 ps |
| CPU time | 654.43 seconds |
| Started | May 28 04:27:16 AM PDT 23 |
| Finished | May 28 04:53:23 AM PDT 23 |
| Peak memory | 160908 kb |
| Host | smart-6da4657a-06c3-410f-bea0-bedeac1b55c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2019411846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_test.2019411846 |
| Directory | /workspace/8.prim_lfsr_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24/9.prim_lfsr_test.2905005109 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 335546590000 ps |
| CPU time | 655.47 seconds |
| Started | May 28 04:27:19 AM PDT 23 |
| Finished | May 28 04:53:43 AM PDT 23 |
| Peak memory | 160868 kb |
| Host | smart-bdca684d-e6b3-4d5c-a1d8-f643bc4f0def |
| User | root |
| Command | /workspace/prim_lfsr_dw_24/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2905005109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_24.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_test.2905005109 |
| Directory | /workspace/9.prim_lfsr_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |