Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2888304182
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3214763053
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.722899375

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.355254740
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.287123703
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.579908244
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1871622645
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4223657618
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2622242128
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2924257176
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1874223604
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3416961627
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2640761660
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2763235832
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.910731810
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.445764756
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3376219704
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.954210032
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2541799458
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1759578028
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4181025670
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1206649663
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1704340499
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.368790064
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3169682503
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.369574895
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.82328143
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3013821006
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2709313390
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1085911483
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3571622101
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.877312931
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3658437980
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.791100544
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3576784962
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2029864764
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2985480168
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3290805872
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.864963553
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3690702728
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2810936725
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.879740206
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.675561798
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2159902055
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1373545080
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3942968542
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3692253453
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.491771749
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1043202639
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2987419130
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2885848877
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1527770673
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1333516181
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1867459845
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.173632543
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.591269231
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4266223101
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1251996940
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1050303388
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1630754141
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4122133679
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3908938025
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1997587299
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3994017942
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2944614098
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3288355865
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2697826137
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1536250575
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.524892062
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4066592295
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3292862549
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1729520136
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3179169360
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.849729039
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.347061952
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1411528938
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3630473126
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.24200034
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2816994840
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3700307833
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.412000674
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1833975197
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2452277432
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3765482200
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1801526166
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.83568974
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1669690446
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1704586329
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.197845345
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1719807663
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.176512921
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2482050936
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3157464734
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4195983420
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1258478319
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.182535472
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3337057163
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3275218787
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1348455326
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1047063057
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1744782279
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3503211956
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3137728368
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1410031581
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2033979755
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2252338119
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1452885330
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1563067069
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2154701420
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2488126935
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4058579781
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2230577628
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1830249047
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2165213505
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.112398883
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3576298294
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1076187613
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2686320754
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4278952696
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1377353119
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1449946737
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2503974056
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1840356850
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3662307119
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.798273815
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1979439128
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1578903786
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4286567815
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3880139798
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1411943840
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1529023295
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3480515036
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3646045023
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2226212202
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1525376965
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4081897244
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1999719201
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3627770854
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.327243871
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1496988892
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4179665880
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1006149437
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2671978245
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.74744361
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3816954920
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2631850288
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1246695167
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.943944155
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1528813956
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.942158006
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2953732353
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3394327449
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3121174512
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.285596905
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1965078991
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.412478267
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.39466989
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.588229189
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2331359991
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1882200841
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1449672804
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2277411842
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2317927442
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2957331705
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2239829083
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2812907022
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1125518513
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2700730125
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1565901190
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.530938091
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.21418809
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.549409713
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2589937136
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.856593862
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.819421578
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.689413455
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2746987066
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.403429474
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.465198278
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3815678969
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1262624343
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.201011422
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3569478462
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3590899189
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3710432381
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3844348659
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.987730257
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.831060018
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2635526329
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3962425736
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4173224994
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1341263752
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4202084691
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1919007398
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3697230411
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2195819861
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2169419744
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.981143514
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.999167133
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2378705499



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2700730125 Dec 24 12:34:44 PM PST 23 Dec 24 12:35:32 PM PST 23 1536750000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.987730257 Dec 24 12:34:47 PM PST 23 Dec 24 12:35:28 PM PST 23 1487230000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2589937136 Dec 24 12:34:47 PM PST 23 Dec 24 12:35:30 PM PST 23 1463350000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3590899189 Dec 24 12:35:16 PM PST 23 Dec 24 12:35:55 PM PST 23 1496650000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3962425736 Dec 24 12:34:43 PM PST 23 Dec 24 12:35:23 PM PST 23 1202370000 ps
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T140 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2953732353 Dec 24 12:28:04 PM PST 23 Dec 24 12:28:23 PM PST 23 1597090000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4286567815 Dec 24 12:26:27 PM PST 23 Dec 24 12:26:38 PM PST 23 1560030000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3137728368 Dec 24 12:26:39 PM PST 23 Dec 24 12:26:50 PM PST 23 1389630000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.943944155 Dec 24 12:27:36 PM PST 23 Dec 24 12:27:44 PM PST 23 1465350000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1840356850 Dec 24 12:28:22 PM PST 23 Dec 24 12:28:40 PM PST 23 1557530000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3627770854 Dec 24 12:26:36 PM PST 23 Dec 24 12:26:47 PM PST 23 1536530000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1411943840 Dec 24 12:28:53 PM PST 23 Dec 24 12:29:10 PM PST 23 1378510000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1076187613 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:48 PM PST 23 1565850000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2154701420 Dec 24 12:26:23 PM PST 23 Dec 24 12:26:33 PM PST 23 1508190000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1979439128 Dec 24 12:26:45 PM PST 23 Dec 24 12:26:54 PM PST 23 1382950000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1377353119 Dec 24 12:29:19 PM PST 23 Dec 24 12:29:37 PM PST 23 1537790000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3480515036 Dec 24 12:26:36 PM PST 23 Dec 24 12:26:48 PM PST 23 1497550000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1578903786 Dec 24 12:26:29 PM PST 23 Dec 24 12:26:40 PM PST 23 1526650000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2686320754 Dec 24 12:27:59 PM PST 23 Dec 24 12:28:18 PM PST 23 1453390000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3646045023 Dec 24 12:27:53 PM PST 23 Dec 24 12:28:07 PM PST 23 1539790000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2488126935 Dec 24 12:28:04 PM PST 23 Dec 24 12:28:23 PM PST 23 1462110000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1410031581 Dec 24 12:27:41 PM PST 23 Dec 24 12:27:52 PM PST 23 1635830000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1496988892 Dec 24 12:26:38 PM PST 23 Dec 24 12:26:51 PM PST 23 1564890000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.112398883 Dec 24 12:26:33 PM PST 23 Dec 24 12:26:42 PM PST 23 1425450000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1528813956 Dec 24 12:26:58 PM PST 23 Dec 24 12:27:09 PM PST 23 1276630000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3576298294 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:45 PM PST 23 1300790000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.83568974 Dec 24 12:26:43 PM PST 23 Dec 24 12:50:35 PM PST 23 337079510000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3337057163 Dec 24 12:29:31 PM PST 23 Dec 24 12:59:12 PM PST 23 336648650000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.24200034 Dec 24 12:27:05 PM PST 23 Dec 24 12:58:33 PM PST 23 336368730000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1047063057 Dec 24 12:29:33 PM PST 23 Dec 24 12:55:39 PM PST 23 336818590000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3288355865 Dec 24 12:27:08 PM PST 23 Dec 24 12:58:37 PM PST 23 336691710000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1411528938 Dec 24 12:27:05 PM PST 23 Dec 24 01:04:21 PM PST 23 336578250000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2944614098 Dec 24 12:26:55 PM PST 23 Dec 24 12:53:35 PM PST 23 336631930000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1833975197 Dec 24 12:27:54 PM PST 23 Dec 24 12:57:32 PM PST 23 336655090000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.722899375 Dec 24 12:29:48 PM PST 23 Dec 24 12:59:37 PM PST 23 336371070000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3765482200 Dec 24 12:28:33 PM PST 23 Dec 24 12:57:54 PM PST 23 336469070000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.849729039 Dec 24 12:31:13 PM PST 23 Dec 24 12:57:43 PM PST 23 336481190000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4195983420 Dec 24 12:26:59 PM PST 23 Dec 24 12:56:40 PM PST 23 336755990000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1348455326 Dec 24 12:27:06 PM PST 23 Dec 24 12:51:43 PM PST 23 336984870000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3179169360 Dec 24 12:27:09 PM PST 23 Dec 24 12:54:50 PM PST 23 336674650000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1536250575 Dec 24 12:27:09 PM PST 23 Dec 24 01:03:34 PM PST 23 336866090000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1669690446 Dec 24 12:28:05 PM PST 23 Dec 24 01:04:27 PM PST 23 336492390000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.591269231 Dec 24 12:28:46 PM PST 23 Dec 24 12:55:08 PM PST 23 336760890000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3700307833 Dec 24 12:29:47 PM PST 23 Dec 24 01:02:22 PM PST 23 336664710000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.182535472 Dec 24 12:27:00 PM PST 23 Dec 24 12:55:32 PM PST 23 337047830000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.197845345 Dec 24 12:27:07 PM PST 23 Dec 24 12:56:17 PM PST 23 336410370000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1251996940 Dec 24 12:27:01 PM PST 23 Dec 24 12:51:23 PM PST 23 336674310000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1704586329 Dec 24 12:27:05 PM PST 23 Dec 24 12:56:42 PM PST 23 336504350000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1258478319 Dec 24 12:27:09 PM PST 23 Dec 24 12:59:02 PM PST 23 336394550000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1867459845 Dec 24 12:27:09 PM PST 23 Dec 24 12:58:59 PM PST 23 336471450000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4266223101 Dec 24 12:27:09 PM PST 23 Dec 24 01:01:11 PM PST 23 336532590000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3292862549 Dec 24 12:31:13 PM PST 23 Dec 24 12:57:49 PM PST 23 336378950000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4066592295 Dec 24 12:28:21 PM PST 23 Dec 24 12:52:16 PM PST 23 336731990000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3908938025 Dec 24 12:26:55 PM PST 23 Dec 24 12:53:31 PM PST 23 336589110000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3275218787 Dec 24 12:27:01 PM PST 23 Dec 24 01:01:21 PM PST 23 336635750000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3994017942 Dec 24 12:26:26 PM PST 23 Dec 24 12:54:22 PM PST 23 336397210000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3157464734 Dec 24 12:27:04 PM PST 23 Dec 24 12:58:15 PM PST 23 336812710000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2816994840 Dec 24 12:27:22 PM PST 23 Dec 24 12:57:52 PM PST 23 336585350000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4122133679 Dec 24 12:26:50 PM PST 23 Dec 24 12:51:18 PM PST 23 336732170000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1333516181 Dec 24 12:26:37 PM PST 23 Dec 24 12:56:06 PM PST 23 337032390000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.176512921 Dec 24 12:27:10 PM PST 23 Dec 24 12:53:34 PM PST 23 336610770000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.412000674 Dec 24 12:28:43 PM PST 23 Dec 24 12:57:16 PM PST 23 336587890000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1801526166 Dec 24 12:27:22 PM PST 23 Dec 24 12:53:53 PM PST 23 336387610000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1997587299 Dec 24 12:27:04 PM PST 23 Dec 24 01:03:06 PM PST 23 337084990000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1050303388 Dec 24 12:27:14 PM PST 23 Dec 24 12:53:02 PM PST 23 336434850000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.524892062 Dec 24 12:27:04 PM PST 23 Dec 24 01:01:16 PM PST 23 337038010000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2697826137 Dec 24 12:27:10 PM PST 23 Dec 24 01:03:12 PM PST 23 336597010000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1729520136 Dec 24 12:27:10 PM PST 23 Dec 24 01:03:19 PM PST 23 336710450000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.347061952 Dec 24 12:27:58 PM PST 23 Dec 24 12:55:59 PM PST 23 337088130000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.173632543 Dec 24 12:27:27 PM PST 23 Dec 24 01:03:06 PM PST 23 336364950000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2452277432 Dec 24 12:27:05 PM PST 23 Dec 24 01:04:24 PM PST 23 337150070000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3630473126 Dec 24 12:27:06 PM PST 23 Dec 24 01:00:56 PM PST 23 336501970000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1719807663 Dec 24 12:28:00 PM PST 23 Dec 24 12:53:41 PM PST 23 336376570000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1630754141 Dec 24 12:27:57 PM PST 23 Dec 24 01:04:22 PM PST 23 336551950000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2482050936 Dec 24 12:26:58 PM PST 23 Dec 24 12:54:35 PM PST 23 336933810000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1744782279 Dec 24 12:27:57 PM PST 23 Dec 24 12:57:49 PM PST 23 336406750000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2888304182
Short name T11
Test name
Test status
Simulation time 1505650000 ps
CPU time 3.94 seconds
Started Dec 24 12:35:02 PM PST 23
Finished Dec 24 12:35:46 PM PST 23
Peak memory 155720 kb
Host smart-e480bf2d-1d7a-436d-8b72-8ccb6f863893
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2888304182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2888304182
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3214763053
Short name T20
Test name
Test status
Simulation time 336507010000 ps
CPU time 646.92 seconds
Started Dec 24 12:28:29 PM PST 23
Finished Dec 24 12:55:20 PM PST 23
Peak memory 160440 kb
Host smart-a846c1f1-dce3-476f-9bac-b799daa76ac6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3214763053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3214763053
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.722899375
Short name T29
Test name
Test status
Simulation time 336371070000 ps
CPU time 731.83 seconds
Started Dec 24 12:29:48 PM PST 23
Finished Dec 24 12:59:37 PM PST 23
Peak memory 160872 kb
Host smart-8c3009de-9b96-499d-80de-ac26cc5ee456
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=722899375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.722899375
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.355254740
Short name T82
Test name
Test status
Simulation time 336892630000 ps
CPU time 609.15 seconds
Started Dec 24 12:28:28 PM PST 23
Finished Dec 24 12:53:56 PM PST 23
Peak memory 160456 kb
Host smart-64480684-df93-4837-be6a-86f38e0b3e2d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=355254740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.355254740
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.287123703
Short name T102
Test name
Test status
Simulation time 336398550000 ps
CPU time 654.64 seconds
Started Dec 24 12:28:29 PM PST 23
Finished Dec 24 12:55:20 PM PST 23
Peak memory 160580 kb
Host smart-539f386f-3d58-4a01-9105-5e71b13d7bbd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=287123703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.287123703
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.579908244
Short name T105
Test name
Test status
Simulation time 336511550000 ps
CPU time 576.39 seconds
Started Dec 24 12:30:12 PM PST 23
Finished Dec 24 12:54:39 PM PST 23
Peak memory 160552 kb
Host smart-c176699b-9880-453e-8bb3-35fffb27e963
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=579908244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.579908244
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1871622645
Short name T4
Test name
Test status
Simulation time 336849450000 ps
CPU time 791.05 seconds
Started Dec 24 12:29:36 PM PST 23
Finished Dec 24 01:01:59 PM PST 23
Peak memory 160424 kb
Host smart-487a3dd9-1889-4a15-9738-5577699cc7b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1871622645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1871622645
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4223657618
Short name T97
Test name
Test status
Simulation time 336398150000 ps
CPU time 623.41 seconds
Started Dec 24 12:28:28 PM PST 23
Finished Dec 24 12:54:20 PM PST 23
Peak memory 160552 kb
Host smart-1b71b7b8-eeb6-45bb-acc2-5db24d17c9bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4223657618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4223657618
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2622242128
Short name T101
Test name
Test status
Simulation time 336562970000 ps
CPU time 884.83 seconds
Started Dec 24 12:29:31 PM PST 23
Finished Dec 24 01:05:57 PM PST 23
Peak memory 160444 kb
Host smart-d5ff5f46-9cc2-4aad-bd7e-f30996a743e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2622242128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2622242128
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2924257176
Short name T91
Test name
Test status
Simulation time 336534530000 ps
CPU time 883.19 seconds
Started Dec 24 12:29:35 PM PST 23
Finished Dec 24 01:05:35 PM PST 23
Peak memory 160444 kb
Host smart-0fb57bbf-c713-4a86-83e1-7c7888342bad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2924257176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2924257176
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1874223604
Short name T103
Test name
Test status
Simulation time 336803510000 ps
CPU time 683.04 seconds
Started Dec 24 12:29:42 PM PST 23
Finished Dec 24 12:58:04 PM PST 23
Peak memory 160584 kb
Host smart-bfa9670a-b666-4ecc-8406-37c7b1b67246
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1874223604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1874223604
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3416961627
Short name T15
Test name
Test status
Simulation time 336752570000 ps
CPU time 727.95 seconds
Started Dec 24 12:28:44 PM PST 23
Finished Dec 24 12:58:38 PM PST 23
Peak memory 160544 kb
Host smart-3eb0e311-7eac-4229-9606-de0d577ba9e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3416961627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3416961627
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2640761660
Short name T99
Test name
Test status
Simulation time 337100490000 ps
CPU time 948.16 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 01:06:31 PM PST 23
Peak memory 160168 kb
Host smart-94eae6d5-8237-43ef-9ebd-4b2694e0237d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2640761660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2640761660
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2763235832
Short name T96
Test name
Test status
Simulation time 336905410000 ps
CPU time 783.58 seconds
Started Dec 24 12:30:11 PM PST 23
Finished Dec 24 01:02:19 PM PST 23
Peak memory 160484 kb
Host smart-ab7b8ca6-3978-4241-abc4-e292af9f8578
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2763235832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2763235832
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.910731810
Short name T84
Test name
Test status
Simulation time 336812490000 ps
CPU time 631.12 seconds
Started Dec 24 12:30:04 PM PST 23
Finished Dec 24 12:56:27 PM PST 23
Peak memory 160576 kb
Host smart-16f49f4b-579c-4efd-b917-4a818664e4ea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=910731810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.910731810
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.445764756
Short name T81
Test name
Test status
Simulation time 336915570000 ps
CPU time 685.39 seconds
Started Dec 24 12:28:21 PM PST 23
Finished Dec 24 12:56:22 PM PST 23
Peak memory 160328 kb
Host smart-5c1385f7-f28b-49c2-89bf-093263f37352
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=445764756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.445764756
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3376219704
Short name T72
Test name
Test status
Simulation time 336974610000 ps
CPU time 730.82 seconds
Started Dec 24 12:29:21 PM PST 23
Finished Dec 24 12:59:05 PM PST 23
Peak memory 160576 kb
Host smart-beb8dda7-65d0-45af-aa3a-120c5ad6c403
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3376219704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3376219704
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.954210032
Short name T94
Test name
Test status
Simulation time 336669630000 ps
CPU time 586.54 seconds
Started Dec 24 12:28:26 PM PST 23
Finished Dec 24 12:52:59 PM PST 23
Peak memory 160412 kb
Host smart-00ab3807-492a-40da-9394-b246e609e840
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=954210032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.954210032
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2541799458
Short name T92
Test name
Test status
Simulation time 336265210000 ps
CPU time 953.07 seconds
Started Dec 24 12:28:50 PM PST 23
Finished Dec 24 01:06:40 PM PST 23
Peak memory 160144 kb
Host smart-1bcf4ff3-0317-494a-9f0e-19ccd98f2b58
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2541799458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2541799458
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1759578028
Short name T100
Test name
Test status
Simulation time 336914430000 ps
CPU time 809.87 seconds
Started Dec 24 12:29:42 PM PST 23
Finished Dec 24 01:02:23 PM PST 23
Peak memory 160496 kb
Host smart-f8ff74ee-f284-48b0-8e75-fd67fbd88e59
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1759578028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1759578028
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4181025670
Short name T109
Test name
Test status
Simulation time 336408910000 ps
CPU time 687.31 seconds
Started Dec 24 12:28:19 PM PST 23
Finished Dec 24 12:56:24 PM PST 23
Peak memory 160336 kb
Host smart-d3f70708-31c0-4e65-9611-2787ee916377
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4181025670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4181025670
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1206649663
Short name T19
Test name
Test status
Simulation time 337088110000 ps
CPU time 690.53 seconds
Started Dec 24 12:31:09 PM PST 23
Finished Dec 24 12:59:04 PM PST 23
Peak memory 160452 kb
Host smart-9610e31d-f2ba-49d8-8b1b-ea982cf4d401
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1206649663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1206649663
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1704340499
Short name T74
Test name
Test status
Simulation time 336980770000 ps
CPU time 576.22 seconds
Started Dec 24 12:29:23 PM PST 23
Finished Dec 24 12:53:32 PM PST 23
Peak memory 160532 kb
Host smart-be77ca52-965c-444c-9a83-f43c8f612f9d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1704340499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1704340499
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.368790064
Short name T95
Test name
Test status
Simulation time 336607970000 ps
CPU time 785.07 seconds
Started Dec 24 12:28:40 PM PST 23
Finished Dec 24 01:00:30 PM PST 23
Peak memory 160404 kb
Host smart-4d1ccb30-3bb6-47e3-a54d-4f9057df63e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=368790064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.368790064
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3169682503
Short name T88
Test name
Test status
Simulation time 336802350000 ps
CPU time 690.2 seconds
Started Dec 24 12:31:26 PM PST 23
Finished Dec 24 12:59:50 PM PST 23
Peak memory 160452 kb
Host smart-24221fb0-bddd-470a-a308-03bcd70f1443
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3169682503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3169682503
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.369574895
Short name T73
Test name
Test status
Simulation time 336831870000 ps
CPU time 688.45 seconds
Started Dec 24 12:28:10 PM PST 23
Finished Dec 24 12:56:28 PM PST 23
Peak memory 160500 kb
Host smart-d87c65db-a4c7-431b-8cb7-552618bc77d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=369574895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.369574895
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.82328143
Short name T5
Test name
Test status
Simulation time 336948710000 ps
CPU time 566.65 seconds
Started Dec 24 12:29:32 PM PST 23
Finished Dec 24 12:53:28 PM PST 23
Peak memory 160516 kb
Host smart-675b6a41-d3f8-4587-92d3-e4dc71cd803b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=82328143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.82328143
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3013821006
Short name T80
Test name
Test status
Simulation time 336972930000 ps
CPU time 645.5 seconds
Started Dec 24 12:28:28 PM PST 23
Finished Dec 24 12:55:23 PM PST 23
Peak memory 160592 kb
Host smart-d6c8e528-32f2-4660-a1ee-31eae172bb18
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3013821006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3013821006
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2709313390
Short name T75
Test name
Test status
Simulation time 336577030000 ps
CPU time 565.05 seconds
Started Dec 24 12:30:35 PM PST 23
Finished Dec 24 12:54:20 PM PST 23
Peak memory 160164 kb
Host smart-547dba97-0f54-4bfb-b8d4-2da1fc3bdde9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2709313390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2709313390
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1085911483
Short name T98
Test name
Test status
Simulation time 336415770000 ps
CPU time 625.74 seconds
Started Dec 24 12:29:34 PM PST 23
Finished Dec 24 12:55:40 PM PST 23
Peak memory 160440 kb
Host smart-ce307e94-4b3e-4173-aa7d-2b345b224478
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1085911483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1085911483
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3571622101
Short name T17
Test name
Test status
Simulation time 336978330000 ps
CPU time 769.56 seconds
Started Dec 24 12:31:45 PM PST 23
Finished Dec 24 01:03:04 PM PST 23
Peak memory 160168 kb
Host smart-dbf90688-53a5-4985-97e4-d8d088604295
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3571622101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3571622101
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.877312931
Short name T89
Test name
Test status
Simulation time 336460550000 ps
CPU time 659.74 seconds
Started Dec 24 12:29:49 PM PST 23
Finished Dec 24 12:57:29 PM PST 23
Peak memory 160576 kb
Host smart-9d5a1770-07a6-450d-96e6-342a957774d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=877312931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.877312931
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3658437980
Short name T108
Test name
Test status
Simulation time 336482410000 ps
CPU time 653.59 seconds
Started Dec 24 12:29:44 PM PST 23
Finished Dec 24 12:56:46 PM PST 23
Peak memory 160756 kb
Host smart-2b3b0992-298e-4783-a591-d389dba4293d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3658437980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3658437980
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.791100544
Short name T90
Test name
Test status
Simulation time 336730670000 ps
CPU time 792.36 seconds
Started Dec 24 12:29:26 PM PST 23
Finished Dec 24 01:01:28 PM PST 23
Peak memory 160456 kb
Host smart-96bab069-7a80-4e85-82ca-d74fe1f35d12
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=791100544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.791100544
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3576784962
Short name T78
Test name
Test status
Simulation time 336608950000 ps
CPU time 711.38 seconds
Started Dec 24 12:31:50 PM PST 23
Finished Dec 24 01:00:51 PM PST 23
Peak memory 160168 kb
Host smart-b6cef2bb-636b-483e-8178-18510ef8afe2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3576784962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3576784962
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2029864764
Short name T86
Test name
Test status
Simulation time 336490270000 ps
CPU time 746.09 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 01:02:37 PM PST 23
Peak memory 160168 kb
Host smart-67e7943d-86c7-437d-96d4-8da2b5496c2a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2029864764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2029864764
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2985480168
Short name T6
Test name
Test status
Simulation time 337090930000 ps
CPU time 883.05 seconds
Started Dec 24 12:28:22 PM PST 23
Finished Dec 24 01:04:29 PM PST 23
Peak memory 160432 kb
Host smart-8222ee09-6002-4902-9c76-8003579e6802
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2985480168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2985480168
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3290805872
Short name T85
Test name
Test status
Simulation time 336417330000 ps
CPU time 582.7 seconds
Started Dec 24 12:29:08 PM PST 23
Finished Dec 24 12:53:34 PM PST 23
Peak memory 160448 kb
Host smart-a55c00c3-9c87-462d-894c-5c4c7d66f30b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3290805872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3290805872
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.864963553
Short name T76
Test name
Test status
Simulation time 336509030000 ps
CPU time 746.72 seconds
Started Dec 24 12:31:45 PM PST 23
Finished Dec 24 01:02:19 PM PST 23
Peak memory 160160 kb
Host smart-9e879487-49c0-402c-b71a-96c6c76cd728
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=864963553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.864963553
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3690702728
Short name T110
Test name
Test status
Simulation time 337031970000 ps
CPU time 693.86 seconds
Started Dec 24 12:28:25 PM PST 23
Finished Dec 24 12:57:01 PM PST 23
Peak memory 160548 kb
Host smart-d9153cc7-df6a-4806-8232-e99c3c262eee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3690702728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3690702728
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2810936725
Short name T18
Test name
Test status
Simulation time 336904430000 ps
CPU time 597.55 seconds
Started Dec 24 12:29:28 PM PST 23
Finished Dec 24 12:54:34 PM PST 23
Peak memory 160528 kb
Host smart-2a967b73-1bcb-40a1-a16e-6e0a310ef70f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2810936725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2810936725
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.879740206
Short name T77
Test name
Test status
Simulation time 336413210000 ps
CPU time 606.07 seconds
Started Dec 24 12:31:30 PM PST 23
Finished Dec 24 12:56:58 PM PST 23
Peak memory 160444 kb
Host smart-f40ef5ba-68ea-40e7-8ba5-afc19452e6f1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=879740206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.879740206
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.675561798
Short name T106
Test name
Test status
Simulation time 336734250000 ps
CPU time 745.79 seconds
Started Dec 24 12:31:49 PM PST 23
Finished Dec 24 01:02:34 PM PST 23
Peak memory 160160 kb
Host smart-ef34826d-e3c3-4af8-a273-68821f5cf9d1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=675561798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.675561798
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2159902055
Short name T14
Test name
Test status
Simulation time 337035270000 ps
CPU time 895.25 seconds
Started Dec 24 12:28:09 PM PST 23
Finished Dec 24 01:04:37 PM PST 23
Peak memory 160548 kb
Host smart-5b8328cd-082e-4d84-81cd-6f2a9b40efa2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2159902055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2159902055
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1373545080
Short name T104
Test name
Test status
Simulation time 336866970000 ps
CPU time 744.69 seconds
Started Dec 24 12:28:52 PM PST 23
Finished Dec 24 12:59:15 PM PST 23
Peak memory 160444 kb
Host smart-ba02a11a-6615-4029-b626-1ff39fd2709c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1373545080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1373545080
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3942968542
Short name T93
Test name
Test status
Simulation time 337006270000 ps
CPU time 643.25 seconds
Started Dec 24 12:29:10 PM PST 23
Finished Dec 24 12:55:58 PM PST 23
Peak memory 160460 kb
Host smart-696a5317-85fe-49ae-8eea-c1e5ed4253fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3942968542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3942968542
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3692253453
Short name T87
Test name
Test status
Simulation time 336940090000 ps
CPU time 873.16 seconds
Started Dec 24 12:28:33 PM PST 23
Finished Dec 24 01:03:45 PM PST 23
Peak memory 160508 kb
Host smart-791c0e42-da59-43d2-a3c0-19c6afcab154
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3692253453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3692253453
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.491771749
Short name T83
Test name
Test status
Simulation time 336408810000 ps
CPU time 620.4 seconds
Started Dec 24 12:29:32 PM PST 23
Finished Dec 24 12:55:27 PM PST 23
Peak memory 160464 kb
Host smart-7dd5bc4b-47c3-42a7-9592-0ab30c5f3dc6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=491771749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.491771749
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1043202639
Short name T107
Test name
Test status
Simulation time 336823270000 ps
CPU time 748.11 seconds
Started Dec 24 12:28:21 PM PST 23
Finished Dec 24 12:58:39 PM PST 23
Peak memory 160436 kb
Host smart-6fecd547-a6e1-4c8a-9ea9-5100e3d42c7c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1043202639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1043202639
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2987419130
Short name T16
Test name
Test status
Simulation time 336327490000 ps
CPU time 662.15 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:56:04 PM PST 23
Peak memory 160360 kb
Host smart-a07fddec-f12b-4c42-a980-8b2461a5d37a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2987419130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2987419130
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2885848877
Short name T71
Test name
Test status
Simulation time 336771190000 ps
CPU time 889.02 seconds
Started Dec 24 12:29:33 PM PST 23
Finished Dec 24 01:05:53 PM PST 23
Peak memory 160436 kb
Host smart-8298f2b5-2565-4c8f-b88a-fb0a1654cf55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2885848877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2885848877
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1527770673
Short name T79
Test name
Test status
Simulation time 336968790000 ps
CPU time 799.59 seconds
Started Dec 24 12:30:04 PM PST 23
Finished Dec 24 01:02:36 PM PST 23
Peak memory 160488 kb
Host smart-627976d4-102f-43d1-97fe-ca5be1300779
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1527770673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1527770673
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1333516181
Short name T184
Test name
Test status
Simulation time 337032390000 ps
CPU time 717.44 seconds
Started Dec 24 12:26:37 PM PST 23
Finished Dec 24 12:56:06 PM PST 23
Peak memory 160972 kb
Host smart-6b5659a7-9d63-408e-b923-e4892c0e1db9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1333516181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1333516181
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1867459845
Short name T174
Test name
Test status
Simulation time 336471450000 ps
CPU time 791.8 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:58:59 PM PST 23
Peak memory 160672 kb
Host smart-6083274b-8206-46fa-bf8f-ed28c32fcff0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1867459845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1867459845
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.173632543
Short name T194
Test name
Test status
Simulation time 336364950000 ps
CPU time 880.12 seconds
Started Dec 24 12:27:27 PM PST 23
Finished Dec 24 01:03:06 PM PST 23
Peak memory 160932 kb
Host smart-9d4871f9-300e-44ec-865d-6501669f3464
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=173632543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.173632543
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.591269231
Short name T167
Test name
Test status
Simulation time 336760890000 ps
CPU time 624.84 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:55:08 PM PST 23
Peak memory 161000 kb
Host smart-33561c27-aa63-46c2-b773-e1baa8772e63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=591269231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.591269231
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4266223101
Short name T175
Test name
Test status
Simulation time 336532590000 ps
CPU time 842.98 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 01:01:11 PM PST 23
Peak memory 160976 kb
Host smart-47598e38-e089-4b00-b185-b6ebe6f0b087
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4266223101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4266223101
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1251996940
Short name T171
Test name
Test status
Simulation time 336674310000 ps
CPU time 557.53 seconds
Started Dec 24 12:27:01 PM PST 23
Finished Dec 24 12:51:23 PM PST 23
Peak memory 160760 kb
Host smart-c909e0aa-710e-4a6e-a7c2-1449bd1b9dfe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1251996940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1251996940
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1050303388
Short name T189
Test name
Test status
Simulation time 336434850000 ps
CPU time 613.97 seconds
Started Dec 24 12:27:14 PM PST 23
Finished Dec 24 12:53:02 PM PST 23
Peak memory 160956 kb
Host smart-2cb3ed3b-86c6-4eb6-93cd-1b66135bdf2f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1050303388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1050303388
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1630754141
Short name T198
Test name
Test status
Simulation time 336551950000 ps
CPU time 897.93 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 01:04:22 PM PST 23
Peak memory 161032 kb
Host smart-c33f55ac-4cf8-4729-b088-bdfef7a4d144
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1630754141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1630754141
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4122133679
Short name T183
Test name
Test status
Simulation time 336732170000 ps
CPU time 583.57 seconds
Started Dec 24 12:26:50 PM PST 23
Finished Dec 24 12:51:18 PM PST 23
Peak memory 160884 kb
Host smart-9786838c-ced0-430a-9ba4-9c4db2e3b46a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4122133679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4122133679
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3908938025
Short name T178
Test name
Test status
Simulation time 336589110000 ps
CPU time 651.13 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:53:31 PM PST 23
Peak memory 160848 kb
Host smart-628bf5eb-f35b-4ae7-ab0d-274df9271372
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3908938025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3908938025
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1997587299
Short name T188
Test name
Test status
Simulation time 337084990000 ps
CPU time 898.23 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 01:03:06 PM PST 23
Peak memory 161024 kb
Host smart-ce9e01bf-3336-4bbb-8051-c85832e57530
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997587299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1997587299
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3994017942
Short name T180
Test name
Test status
Simulation time 336397210000 ps
CPU time 685.03 seconds
Started Dec 24 12:26:26 PM PST 23
Finished Dec 24 12:54:22 PM PST 23
Peak memory 160892 kb
Host smart-de0259f0-87e7-4db3-a16d-163cf9882838
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3994017942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3994017942
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2944614098
Short name T27
Test name
Test status
Simulation time 336631930000 ps
CPU time 648.68 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:53:35 PM PST 23
Peak memory 160848 kb
Host smart-2edb8b1d-7677-4d29-a59d-beeff72194f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2944614098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2944614098
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3288355865
Short name T25
Test name
Test status
Simulation time 336691710000 ps
CPU time 788.32 seconds
Started Dec 24 12:27:08 PM PST 23
Finished Dec 24 12:58:37 PM PST 23
Peak memory 160904 kb
Host smart-3869c855-0e3b-4970-a558-413ecafba834
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3288355865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3288355865
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2697826137
Short name T191
Test name
Test status
Simulation time 336597010000 ps
CPU time 888.74 seconds
Started Dec 24 12:27:10 PM PST 23
Finished Dec 24 01:03:12 PM PST 23
Peak memory 160944 kb
Host smart-7aab7fe2-42f2-4623-aaac-cb1c3edd44bd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2697826137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2697826137
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1536250575
Short name T165
Test name
Test status
Simulation time 336866090000 ps
CPU time 897.1 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 01:03:34 PM PST 23
Peak memory 160944 kb
Host smart-cba58c57-68f4-4b07-bcd3-9a172e7648a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1536250575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1536250575
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.524892062
Short name T190
Test name
Test status
Simulation time 337038010000 ps
CPU time 845.04 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 01:01:16 PM PST 23
Peak memory 160968 kb
Host smart-eff76f77-d3fc-4b7b-9771-1bb346327c40
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=524892062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.524892062
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4066592295
Short name T177
Test name
Test status
Simulation time 336731990000 ps
CPU time 564.73 seconds
Started Dec 24 12:28:21 PM PST 23
Finished Dec 24 12:52:16 PM PST 23
Peak memory 160980 kb
Host smart-1bebb45b-08ba-4120-8a29-eef5de311937
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4066592295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4066592295
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3292862549
Short name T176
Test name
Test status
Simulation time 336378950000 ps
CPU time 653.28 seconds
Started Dec 24 12:31:13 PM PST 23
Finished Dec 24 12:57:49 PM PST 23
Peak memory 160608 kb
Host smart-1ec4c165-492d-44e1-9d54-e71e94b877b2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3292862549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3292862549
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1729520136
Short name T192
Test name
Test status
Simulation time 336710450000 ps
CPU time 889.21 seconds
Started Dec 24 12:27:10 PM PST 23
Finished Dec 24 01:03:19 PM PST 23
Peak memory 160944 kb
Host smart-d1b8488b-11e3-4e35-96d2-90addf54f26f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1729520136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1729520136
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3179169360
Short name T164
Test name
Test status
Simulation time 336674650000 ps
CPU time 686.03 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:54:50 PM PST 23
Peak memory 160676 kb
Host smart-03e84200-6c2d-4cb6-840f-94ce2e64f8e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3179169360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3179169360
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.849729039
Short name T161
Test name
Test status
Simulation time 336481190000 ps
CPU time 646.66 seconds
Started Dec 24 12:31:13 PM PST 23
Finished Dec 24 12:57:43 PM PST 23
Peak memory 160600 kb
Host smart-a03b19e6-3d2b-4d69-945e-a354a61a80da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=849729039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.849729039
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.347061952
Short name T193
Test name
Test status
Simulation time 337088130000 ps
CPU time 685.14 seconds
Started Dec 24 12:27:58 PM PST 23
Finished Dec 24 12:55:59 PM PST 23
Peak memory 160892 kb
Host smart-d47077aa-53d3-4957-ade7-4e26941ce60a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=347061952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.347061952
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1411528938
Short name T26
Test name
Test status
Simulation time 336578250000 ps
CPU time 932.86 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 01:04:21 PM PST 23
Peak memory 160984 kb
Host smart-99d32d89-56da-4e41-9ae4-3aaedc6c7f1b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1411528938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1411528938
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3630473126
Short name T196
Test name
Test status
Simulation time 336501970000 ps
CPU time 840.7 seconds
Started Dec 24 12:27:06 PM PST 23
Finished Dec 24 01:00:56 PM PST 23
Peak memory 160976 kb
Host smart-ba56aae4-32e5-44be-949a-637c70178a31
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3630473126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3630473126
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.24200034
Short name T23
Test name
Test status
Simulation time 336368730000 ps
CPU time 785.04 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 12:58:33 PM PST 23
Peak memory 160888 kb
Host smart-b0df0e2b-fa34-474a-8c4c-655010c8f808
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=24200034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.24200034
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2816994840
Short name T182
Test name
Test status
Simulation time 336585350000 ps
CPU time 754.78 seconds
Started Dec 24 12:27:22 PM PST 23
Finished Dec 24 12:57:52 PM PST 23
Peak memory 160904 kb
Host smart-f1958d0c-b182-4f6a-bc0d-5e84864d2120
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2816994840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2816994840
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3700307833
Short name T168
Test name
Test status
Simulation time 336664710000 ps
CPU time 792.6 seconds
Started Dec 24 12:29:47 PM PST 23
Finished Dec 24 01:02:22 PM PST 23
Peak memory 160880 kb
Host smart-1f58541e-e325-4512-948b-a786db8f5db1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3700307833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3700307833
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.412000674
Short name T186
Test name
Test status
Simulation time 336587890000 ps
CPU time 688.08 seconds
Started Dec 24 12:28:43 PM PST 23
Finished Dec 24 12:57:16 PM PST 23
Peak memory 160940 kb
Host smart-60c5e6da-f79b-4073-b9f4-0602c2ba5de3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=412000674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.412000674
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1833975197
Short name T28
Test name
Test status
Simulation time 336655090000 ps
CPU time 723.59 seconds
Started Dec 24 12:27:54 PM PST 23
Finished Dec 24 12:57:32 PM PST 23
Peak memory 161016 kb
Host smart-b25e3104-3c89-4a72-9810-bc151d8dc315
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1833975197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1833975197
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2452277432
Short name T195
Test name
Test status
Simulation time 337150070000 ps
CPU time 929.72 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 01:04:24 PM PST 23
Peak memory 160996 kb
Host smart-7040fb07-6a8f-4aa1-9fb6-9bb6d05f720a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2452277432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2452277432
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3765482200
Short name T30
Test name
Test status
Simulation time 336469070000 ps
CPU time 715.09 seconds
Started Dec 24 12:28:33 PM PST 23
Finished Dec 24 12:57:54 PM PST 23
Peak memory 161052 kb
Host smart-866f429b-0c01-41d0-a499-b7d7b021ce20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3765482200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3765482200
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1801526166
Short name T187
Test name
Test status
Simulation time 336387610000 ps
CPU time 650.33 seconds
Started Dec 24 12:27:22 PM PST 23
Finished Dec 24 12:53:53 PM PST 23
Peak memory 160804 kb
Host smart-1a1b3c40-15b6-4bb0-acf3-f7ff919c4b2c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1801526166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1801526166
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.83568974
Short name T21
Test name
Test status
Simulation time 337079510000 ps
CPU time 566.33 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:50:35 PM PST 23
Peak memory 160724 kb
Host smart-c726cd3f-4d42-444f-afb5-508548761a66
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=83568974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.83568974
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1669690446
Short name T166
Test name
Test status
Simulation time 336492390000 ps
CPU time 899.53 seconds
Started Dec 24 12:28:05 PM PST 23
Finished Dec 24 01:04:27 PM PST 23
Peak memory 161032 kb
Host smart-b6716847-0ad6-4ae4-8453-2ebc7157057c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1669690446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1669690446
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1704586329
Short name T172
Test name
Test status
Simulation time 336504350000 ps
CPU time 729.22 seconds
Started Dec 24 12:27:05 PM PST 23
Finished Dec 24 12:56:42 PM PST 23
Peak memory 161016 kb
Host smart-fbc3e2d8-7910-4077-8d92-0a225afd8409
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1704586329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1704586329
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.197845345
Short name T170
Test name
Test status
Simulation time 336410370000 ps
CPU time 725.08 seconds
Started Dec 24 12:27:07 PM PST 23
Finished Dec 24 12:56:17 PM PST 23
Peak memory 160996 kb
Host smart-831d3ce8-d6b9-45cd-82ce-8bb92db7777e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=197845345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.197845345
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1719807663
Short name T197
Test name
Test status
Simulation time 336376570000 ps
CPU time 604.67 seconds
Started Dec 24 12:28:00 PM PST 23
Finished Dec 24 12:53:41 PM PST 23
Peak memory 161008 kb
Host smart-fb165e5f-5ce5-4686-b4ba-aed40bf01bad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1719807663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1719807663
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.176512921
Short name T185
Test name
Test status
Simulation time 336610770000 ps
CPU time 632.54 seconds
Started Dec 24 12:27:10 PM PST 23
Finished Dec 24 12:53:34 PM PST 23
Peak memory 160996 kb
Host smart-5661fbdc-b903-48c6-be7c-c969e523bea7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=176512921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.176512921
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2482050936
Short name T199
Test name
Test status
Simulation time 336933810000 ps
CPU time 678.64 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:54:35 PM PST 23
Peak memory 160988 kb
Host smart-a8abe0dd-98e7-4db6-b09c-91bcf6864328
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2482050936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2482050936
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3157464734
Short name T181
Test name
Test status
Simulation time 336812710000 ps
CPU time 777.58 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 12:58:15 PM PST 23
Peak memory 160916 kb
Host smart-12d29afd-3c00-421d-940d-76d12f1fedb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3157464734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3157464734
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4195983420
Short name T162
Test name
Test status
Simulation time 336755990000 ps
CPU time 734.22 seconds
Started Dec 24 12:26:59 PM PST 23
Finished Dec 24 12:56:40 PM PST 23
Peak memory 160884 kb
Host smart-843824f4-ca8b-4d2f-9d4d-fb16080b6d64
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4195983420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4195983420
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1258478319
Short name T173
Test name
Test status
Simulation time 336394550000 ps
CPU time 795.27 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:59:02 PM PST 23
Peak memory 160640 kb
Host smart-e61f2369-905e-457a-beba-bd589137dca5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1258478319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1258478319
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.182535472
Short name T169
Test name
Test status
Simulation time 337047830000 ps
CPU time 705.29 seconds
Started Dec 24 12:27:00 PM PST 23
Finished Dec 24 12:55:32 PM PST 23
Peak memory 160940 kb
Host smart-ef8240b6-755c-46ac-adf5-97a578a8af6b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=182535472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.182535472
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3337057163
Short name T22
Test name
Test status
Simulation time 336648650000 ps
CPU time 728.94 seconds
Started Dec 24 12:29:31 PM PST 23
Finished Dec 24 12:59:12 PM PST 23
Peak memory 160876 kb
Host smart-7cdaf52a-8dfc-42aa-bf9f-e650a627c8f8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3337057163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3337057163
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3275218787
Short name T179
Test name
Test status
Simulation time 336635750000 ps
CPU time 858.2 seconds
Started Dec 24 12:27:01 PM PST 23
Finished Dec 24 01:01:21 PM PST 23
Peak memory 160968 kb
Host smart-8bcd0a92-865d-4b19-b7be-f63f603e3875
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3275218787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3275218787
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1348455326
Short name T163
Test name
Test status
Simulation time 336984870000 ps
CPU time 583.59 seconds
Started Dec 24 12:27:06 PM PST 23
Finished Dec 24 12:51:43 PM PST 23
Peak memory 160912 kb
Host smart-7a286ebb-5859-4807-8582-521c43f3b1e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1348455326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1348455326
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1047063057
Short name T24
Test name
Test status
Simulation time 336818590000 ps
CPU time 636.66 seconds
Started Dec 24 12:29:33 PM PST 23
Finished Dec 24 12:55:39 PM PST 23
Peak memory 161052 kb
Host smart-96586857-0ed7-474e-baca-a5cf459bed05
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1047063057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1047063057
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1744782279
Short name T200
Test name
Test status
Simulation time 336406750000 ps
CPU time 729.17 seconds
Started Dec 24 12:27:57 PM PST 23
Finished Dec 24 12:57:49 PM PST 23
Peak memory 160924 kb
Host smart-4b86eda3-435e-4fcf-bed5-86c6d6d04b00
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1744782279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1744782279
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3503211956
Short name T126
Test name
Test status
Simulation time 1239530000 ps
CPU time 3.36 seconds
Started Dec 24 12:26:57 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 156144 kb
Host smart-81f3795d-3c0b-4227-aefa-a966899e11e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3503211956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3503211956
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3137728368
Short name T142
Test name
Test status
Simulation time 1389630000 ps
CPU time 3.22 seconds
Started Dec 24 12:26:39 PM PST 23
Finished Dec 24 12:26:50 PM PST 23
Peak memory 156192 kb
Host smart-df2a49fc-e12b-457f-a557-d57ba42f6119
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3137728368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3137728368
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1410031581
Short name T156
Test name
Test status
Simulation time 1635830000 ps
CPU time 3.28 seconds
Started Dec 24 12:27:41 PM PST 23
Finished Dec 24 12:27:52 PM PST 23
Peak memory 156128 kb
Host smart-c264e160-d017-4056-ba3d-e53bb8d96796
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1410031581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1410031581
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2033979755
Short name T127
Test name
Test status
Simulation time 1485470000 ps
CPU time 4.34 seconds
Started Dec 24 12:29:19 PM PST 23
Finished Dec 24 12:29:37 PM PST 23
Peak memory 154664 kb
Host smart-e644bf19-273f-4450-86d1-e876545cf3d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033979755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2033979755
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2252338119
Short name T135
Test name
Test status
Simulation time 1445870000 ps
CPU time 3.77 seconds
Started Dec 24 12:26:32 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 156156 kb
Host smart-4c585495-885b-40cd-9ac6-725cb0033c8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252338119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2252338119
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1452885330
Short name T136
Test name
Test status
Simulation time 1500730000 ps
CPU time 3.73 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:54 PM PST 23
Peak memory 156144 kb
Host smart-21d85d62-1ce4-43b0-a557-73831e2f3839
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452885330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1452885330
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1563067069
Short name T128
Test name
Test status
Simulation time 1442150000 ps
CPU time 4.04 seconds
Started Dec 24 12:27:22 PM PST 23
Finished Dec 24 12:27:35 PM PST 23
Peak memory 156216 kb
Host smart-e80facfa-e7ca-4f39-93f3-5b29eb3837f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1563067069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1563067069
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2154701420
Short name T148
Test name
Test status
Simulation time 1508190000 ps
CPU time 3.24 seconds
Started Dec 24 12:26:23 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 156164 kb
Host smart-ac9ec3a6-27a2-48f1-86fb-49f673274813
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2154701420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2154701420
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2488126935
Short name T155
Test name
Test status
Simulation time 1462110000 ps
CPU time 3.12 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:23 PM PST 23
Peak memory 156072 kb
Host smart-c4963fe8-9093-4717-b1f8-27d7249563de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2488126935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2488126935
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4058579781
Short name T132
Test name
Test status
Simulation time 1603350000 ps
CPU time 4.93 seconds
Started Dec 24 12:26:34 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 156048 kb
Host smart-82819269-e19e-4b13-9cb9-0e772d237fde
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4058579781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4058579781
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2230577628
Short name T116
Test name
Test status
Simulation time 1375150000 ps
CPU time 2.84 seconds
Started Dec 24 12:28:41 PM PST 23
Finished Dec 24 12:28:53 PM PST 23
Peak memory 155804 kb
Host smart-246173c1-996d-4622-8251-2d513a8220f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2230577628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2230577628
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1830249047
Short name T138
Test name
Test status
Simulation time 1351190000 ps
CPU time 3.13 seconds
Started Dec 24 12:26:47 PM PST 23
Finished Dec 24 12:26:55 PM PST 23
Peak memory 156072 kb
Host smart-9d8518da-59c4-436f-aa35-0f39b80540e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1830249047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1830249047
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2165213505
Short name T114
Test name
Test status
Simulation time 1506890000 ps
CPU time 3.68 seconds
Started Dec 24 12:27:44 PM PST 23
Finished Dec 24 12:28:03 PM PST 23
Peak memory 156088 kb
Host smart-6a6f2cd3-b9af-4504-b5b8-668d014fb7a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2165213505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2165213505
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.112398883
Short name T158
Test name
Test status
Simulation time 1425450000 ps
CPU time 3.52 seconds
Started Dec 24 12:26:33 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 155608 kb
Host smart-99024245-00db-42df-a91a-88360769c781
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112398883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.112398883
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3576298294
Short name T160
Test name
Test status
Simulation time 1300790000 ps
CPU time 3.81 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:45 PM PST 23
Peak memory 156048 kb
Host smart-5d22efb6-fd9a-4264-af57-87c746518816
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3576298294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3576298294
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1076187613
Short name T147
Test name
Test status
Simulation time 1565850000 ps
CPU time 4.8 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 156048 kb
Host smart-d3bb081e-4c30-48b9-95b1-e17261907d51
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076187613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1076187613
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2686320754
Short name T153
Test name
Test status
Simulation time 1453390000 ps
CPU time 2.82 seconds
Started Dec 24 12:27:59 PM PST 23
Finished Dec 24 12:28:18 PM PST 23
Peak memory 156172 kb
Host smart-9e9182e9-9493-47cf-a9d8-5c446c02b2af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686320754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2686320754
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4278952696
Short name T111
Test name
Test status
Simulation time 1522890000 ps
CPU time 3.73 seconds
Started Dec 24 12:26:33 PM PST 23
Finished Dec 24 12:26:43 PM PST 23
Peak memory 155792 kb
Host smart-dc8ae25f-e4bf-4a25-b759-646aa36091ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4278952696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4278952696
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1377353119
Short name T150
Test name
Test status
Simulation time 1537790000 ps
CPU time 4.13 seconds
Started Dec 24 12:29:19 PM PST 23
Finished Dec 24 12:29:37 PM PST 23
Peak memory 155180 kb
Host smart-d74f8c07-0de7-4fbe-bfab-33d7d08daa57
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1377353119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1377353119
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1449946737
Short name T120
Test name
Test status
Simulation time 1446270000 ps
CPU time 3.2 seconds
Started Dec 24 12:26:30 PM PST 23
Finished Dec 24 12:26:39 PM PST 23
Peak memory 156164 kb
Host smart-9cc794e4-d1a9-42de-9650-4c1020864fcd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449946737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1449946737
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2503974056
Short name T130
Test name
Test status
Simulation time 1400710000 ps
CPU time 3.92 seconds
Started Dec 24 12:29:30 PM PST 23
Finished Dec 24 12:29:49 PM PST 23
Peak memory 156128 kb
Host smart-8848d891-c7b0-4c47-96b0-9ce4ac1f68e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503974056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2503974056
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1840356850
Short name T144
Test name
Test status
Simulation time 1557530000 ps
CPU time 3.38 seconds
Started Dec 24 12:28:22 PM PST 23
Finished Dec 24 12:28:40 PM PST 23
Peak memory 156080 kb
Host smart-fd64f477-0ae4-48e4-ad52-2539057a702e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1840356850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1840356850
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3662307119
Short name T139
Test name
Test status
Simulation time 1375890000 ps
CPU time 3.96 seconds
Started Dec 24 12:29:29 PM PST 23
Finished Dec 24 12:29:49 PM PST 23
Peak memory 156128 kb
Host smart-c13dc85c-8812-41f2-af89-a54d462781ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662307119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3662307119
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.798273815
Short name T112
Test name
Test status
Simulation time 1435830000 ps
CPU time 2.63 seconds
Started Dec 24 12:30:17 PM PST 23
Finished Dec 24 12:30:45 PM PST 23
Peak memory 156028 kb
Host smart-b4d3455e-5f2f-4933-a23a-91cf774845dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=798273815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.798273815
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1979439128
Short name T149
Test name
Test status
Simulation time 1382950000 ps
CPU time 3.28 seconds
Started Dec 24 12:26:45 PM PST 23
Finished Dec 24 12:26:54 PM PST 23
Peak memory 156072 kb
Host smart-d20a6dc0-19f5-41a5-a937-108ab8e1843a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979439128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1979439128
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1578903786
Short name T152
Test name
Test status
Simulation time 1526650000 ps
CPU time 3.9 seconds
Started Dec 24 12:26:29 PM PST 23
Finished Dec 24 12:26:40 PM PST 23
Peak memory 155796 kb
Host smart-e13d0201-b5c4-4051-9318-c5fea6731ff6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1578903786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1578903786
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4286567815
Short name T141
Test name
Test status
Simulation time 1560030000 ps
CPU time 4.18 seconds
Started Dec 24 12:26:27 PM PST 23
Finished Dec 24 12:26:38 PM PST 23
Peak memory 156324 kb
Host smart-031bb0ef-0424-49d8-8261-bf42681fbdc4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4286567815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4286567815
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3880139798
Short name T118
Test name
Test status
Simulation time 1496890000 ps
CPU time 3.16 seconds
Started Dec 24 12:26:28 PM PST 23
Finished Dec 24 12:26:37 PM PST 23
Peak memory 156084 kb
Host smart-3422b3fc-0585-4a87-8068-d6f21bd2b12d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3880139798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3880139798
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1411943840
Short name T146
Test name
Test status
Simulation time 1378510000 ps
CPU time 2.75 seconds
Started Dec 24 12:28:53 PM PST 23
Finished Dec 24 12:29:10 PM PST 23
Peak memory 154672 kb
Host smart-6c195d60-9711-4384-a57f-2639ce912687
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1411943840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1411943840
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1529023295
Short name T122
Test name
Test status
Simulation time 1565530000 ps
CPU time 3.25 seconds
Started Dec 24 12:26:26 PM PST 23
Finished Dec 24 12:26:35 PM PST 23
Peak memory 156168 kb
Host smart-4337f62e-2e7d-4b5f-90ca-c8e4a20d008f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1529023295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1529023295
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3480515036
Short name T151
Test name
Test status
Simulation time 1497550000 ps
CPU time 4.33 seconds
Started Dec 24 12:26:36 PM PST 23
Finished Dec 24 12:26:48 PM PST 23
Peak memory 156044 kb
Host smart-532472ab-5653-42f6-87d1-0ed74aa4b34e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3480515036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3480515036
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3646045023
Short name T154
Test name
Test status
Simulation time 1539790000 ps
CPU time 3.52 seconds
Started Dec 24 12:27:53 PM PST 23
Finished Dec 24 12:28:07 PM PST 23
Peak memory 156052 kb
Host smart-b1b9db48-3bed-4ce6-b1ab-806eb3bde930
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3646045023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3646045023
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2226212202
Short name T134
Test name
Test status
Simulation time 1175470000 ps
CPU time 3.27 seconds
Started Dec 24 12:26:27 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 155748 kb
Host smart-ff372717-4ec3-452c-8999-b7b8c13f08c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226212202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2226212202
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1525376965
Short name T117
Test name
Test status
Simulation time 1426970000 ps
CPU time 3.77 seconds
Started Dec 24 12:27:56 PM PST 23
Finished Dec 24 12:28:18 PM PST 23
Peak memory 156204 kb
Host smart-44294ceb-4b20-47a1-8a2d-4a04ef857d25
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1525376965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1525376965
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4081897244
Short name T133
Test name
Test status
Simulation time 1178710000 ps
CPU time 3.08 seconds
Started Dec 24 12:29:47 PM PST 23
Finished Dec 24 12:30:15 PM PST 23
Peak memory 155792 kb
Host smart-eff01fa6-e8f0-4048-8ba1-189dd408f85e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4081897244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.4081897244
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1999719201
Short name T137
Test name
Test status
Simulation time 1545430000 ps
CPU time 4.48 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 156068 kb
Host smart-dcdd796c-f7f1-4a21-9fd4-9e633e09f6a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1999719201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1999719201
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3627770854
Short name T145
Test name
Test status
Simulation time 1536530000 ps
CPU time 4.22 seconds
Started Dec 24 12:26:36 PM PST 23
Finished Dec 24 12:26:47 PM PST 23
Peak memory 156044 kb
Host smart-ec50de91-099c-490e-b88e-8ecbfdc99666
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3627770854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3627770854
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.327243871
Short name T115
Test name
Test status
Simulation time 1402050000 ps
CPU time 2.78 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:29:00 PM PST 23
Peak memory 155572 kb
Host smart-5e25e72e-773f-429f-8997-6e0a5eec116b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=327243871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.327243871
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1496988892
Short name T157
Test name
Test status
Simulation time 1564890000 ps
CPU time 4.21 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:51 PM PST 23
Peak memory 156024 kb
Host smart-d9df8256-b1a4-414b-afde-42318687d4d1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496988892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1496988892
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4179665880
Short name T123
Test name
Test status
Simulation time 1403990000 ps
CPU time 3.27 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:27:06 PM PST 23
Peak memory 156128 kb
Host smart-293ac360-1407-4e73-933a-bb6c40aa0008
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4179665880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.4179665880
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1006149437
Short name T124
Test name
Test status
Simulation time 1362050000 ps
CPU time 3.41 seconds
Started Dec 24 12:26:43 PM PST 23
Finished Dec 24 12:26:53 PM PST 23
Peak memory 155896 kb
Host smart-d6153916-13cd-4c3d-bb39-ad10b3a8a8a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1006149437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1006149437
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2671978245
Short name T113
Test name
Test status
Simulation time 1404650000 ps
CPU time 3.07 seconds
Started Dec 24 12:27:21 PM PST 23
Finished Dec 24 12:27:32 PM PST 23
Peak memory 156160 kb
Host smart-0f8215e0-995f-4c0e-8641-68029078d4be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2671978245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2671978245
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.74744361
Short name T131
Test name
Test status
Simulation time 1328910000 ps
CPU time 4.04 seconds
Started Dec 24 12:26:38 PM PST 23
Finished Dec 24 12:26:50 PM PST 23
Peak memory 156032 kb
Host smart-664e36c7-b157-4ec1-b8ac-8a953888f08d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=74744361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.74744361
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3816954920
Short name T125
Test name
Test status
Simulation time 1433410000 ps
CPU time 3.32 seconds
Started Dec 24 12:28:21 PM PST 23
Finished Dec 24 12:28:39 PM PST 23
Peak memory 156228 kb
Host smart-ab8c527c-ee46-4ce1-bdc4-c6a7e072ac84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816954920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3816954920
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2631850288
Short name T129
Test name
Test status
Simulation time 1592830000 ps
CPU time 3.98 seconds
Started Dec 24 12:26:32 PM PST 23
Finished Dec 24 12:26:42 PM PST 23
Peak memory 156164 kb
Host smart-a35a04d2-f753-465a-9db3-2bc850caadaa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631850288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2631850288
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1246695167
Short name T121
Test name
Test status
Simulation time 1563330000 ps
CPU time 4.04 seconds
Started Dec 24 12:28:03 PM PST 23
Finished Dec 24 12:28:24 PM PST 23
Peak memory 156236 kb
Host smart-c2e0b64b-a8d3-4bc8-b78e-bc5a1ffea879
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1246695167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1246695167
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.943944155
Short name T143
Test name
Test status
Simulation time 1465350000 ps
CPU time 3.27 seconds
Started Dec 24 12:27:36 PM PST 23
Finished Dec 24 12:27:44 PM PST 23
Peak memory 156044 kb
Host smart-cafd78fb-5b03-465b-9c2f-7d66a943934a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=943944155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.943944155
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1528813956
Short name T159
Test name
Test status
Simulation time 1276630000 ps
CPU time 3.6 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:09 PM PST 23
Peak memory 156144 kb
Host smart-0b5570da-01ca-4284-8818-673017cd1cc6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1528813956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1528813956
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.942158006
Short name T119
Test name
Test status
Simulation time 1395070000 ps
CPU time 2.89 seconds
Started Dec 24 12:27:53 PM PST 23
Finished Dec 24 12:28:07 PM PST 23
Peak memory 156124 kb
Host smart-a3d2768a-8cb7-4eb6-a120-24e8cb889131
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942158006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.942158006
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2953732353
Short name T140
Test name
Test status
Simulation time 1597090000 ps
CPU time 3.17 seconds
Started Dec 24 12:28:04 PM PST 23
Finished Dec 24 12:28:23 PM PST 23
Peak memory 156192 kb
Host smart-71ff1bfa-a7d3-4e4b-8eb1-7f32d313dd06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953732353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2953732353
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3394327449
Short name T41
Test name
Test status
Simulation time 1474490000 ps
CPU time 4.29 seconds
Started Dec 24 12:34:41 PM PST 23
Finished Dec 24 12:35:24 PM PST 23
Peak memory 155808 kb
Host smart-a3a42307-3feb-4277-b6df-8e03e517227e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394327449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3394327449
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3121174512
Short name T48
Test name
Test status
Simulation time 1484210000 ps
CPU time 4.18 seconds
Started Dec 24 12:35:03 PM PST 23
Finished Dec 24 12:35:46 PM PST 23
Peak memory 155708 kb
Host smart-cd48bf42-0512-40b7-b2c2-538fbce06d93
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3121174512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3121174512
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.285596905
Short name T53
Test name
Test status
Simulation time 1449430000 ps
CPU time 2.88 seconds
Started Dec 24 12:34:58 PM PST 23
Finished Dec 24 12:35:40 PM PST 23
Peak memory 155692 kb
Host smart-551d5060-7d7c-472d-baaf-190259989d6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=285596905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.285596905
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1965078991
Short name T44
Test name
Test status
Simulation time 1369730000 ps
CPU time 2.7 seconds
Started Dec 24 12:35:00 PM PST 23
Finished Dec 24 12:35:41 PM PST 23
Peak memory 155716 kb
Host smart-5a873d34-eacf-4f12-a957-afafd247b741
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1965078991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1965078991
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.412478267
Short name T66
Test name
Test status
Simulation time 1430910000 ps
CPU time 2.66 seconds
Started Dec 24 12:34:42 PM PST 23
Finished Dec 24 12:35:21 PM PST 23
Peak memory 155728 kb
Host smart-eb538ca3-91e0-43f7-812f-3acb7bbcb654
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=412478267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.412478267
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.39466989
Short name T62
Test name
Test status
Simulation time 1448830000 ps
CPU time 2.71 seconds
Started Dec 24 12:35:11 PM PST 23
Finished Dec 24 12:35:48 PM PST 23
Peak memory 155744 kb
Host smart-f9fede60-014a-4076-a857-92cb6c73b8ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39466989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.39466989
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.588229189
Short name T54
Test name
Test status
Simulation time 1333710000 ps
CPU time 3.36 seconds
Started Dec 24 12:35:03 PM PST 23
Finished Dec 24 12:35:45 PM PST 23
Peak memory 155632 kb
Host smart-917184c0-1fee-4afe-83e2-b218a6540be9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=588229189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.588229189
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2331359991
Short name T51
Test name
Test status
Simulation time 1428350000 ps
CPU time 2.78 seconds
Started Dec 24 12:34:36 PM PST 23
Finished Dec 24 12:35:16 PM PST 23
Peak memory 155772 kb
Host smart-a01b05a3-acd3-49ce-859e-0df77e2aed32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331359991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2331359991
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1882200841
Short name T43
Test name
Test status
Simulation time 1513730000 ps
CPU time 2.89 seconds
Started Dec 24 12:34:47 PM PST 23
Finished Dec 24 12:35:26 PM PST 23
Peak memory 155664 kb
Host smart-b0796fef-841c-47a5-b7ee-29710b8d2b43
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1882200841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1882200841
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1449672804
Short name T34
Test name
Test status
Simulation time 1045890000 ps
CPU time 2.91 seconds
Started Dec 24 12:35:03 PM PST 23
Finished Dec 24 12:35:44 PM PST 23
Peak memory 155704 kb
Host smart-0c5795e8-a485-4097-a0fb-27d3e566fedd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449672804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1449672804
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2277411842
Short name T57
Test name
Test status
Simulation time 1558490000 ps
CPU time 3.11 seconds
Started Dec 24 12:34:50 PM PST 23
Finished Dec 24 12:35:33 PM PST 23
Peak memory 155724 kb
Host smart-3ae6f40c-9bf5-43ed-a7a7-5bd7b6ab2807
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2277411842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2277411842
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2317927442
Short name T33
Test name
Test status
Simulation time 1298870000 ps
CPU time 4 seconds
Started Dec 24 12:34:41 PM PST 23
Finished Dec 24 12:35:23 PM PST 23
Peak memory 155756 kb
Host smart-ad13fd16-65d8-40d2-8490-0a72015c2fcf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317927442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2317927442
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2957331705
Short name T67
Test name
Test status
Simulation time 1549010000 ps
CPU time 3.25 seconds
Started Dec 24 12:35:08 PM PST 23
Finished Dec 24 12:35:47 PM PST 23
Peak memory 155772 kb
Host smart-e15576d0-7780-424e-b8ef-19ed7272a5ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2957331705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2957331705
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2239829083
Short name T64
Test name
Test status
Simulation time 1384830000 ps
CPU time 2.98 seconds
Started Dec 24 12:35:17 PM PST 23
Finished Dec 24 12:35:52 PM PST 23
Peak memory 155772 kb
Host smart-a2721010-7382-4e3e-808e-d8f2cfe8883a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2239829083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2239829083
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2812907022
Short name T63
Test name
Test status
Simulation time 1306190000 ps
CPU time 2.56 seconds
Started Dec 24 12:35:07 PM PST 23
Finished Dec 24 12:35:45 PM PST 23
Peak memory 155716 kb
Host smart-f628a8e5-9063-47e9-b763-f5b4b6f680f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2812907022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2812907022
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1125518513
Short name T46
Test name
Test status
Simulation time 1597570000 ps
CPU time 3.18 seconds
Started Dec 24 12:34:58 PM PST 23
Finished Dec 24 12:35:40 PM PST 23
Peak memory 155772 kb
Host smart-60acfd50-672b-42cd-8f83-ae3a3e748e98
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1125518513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1125518513
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2700730125
Short name T1
Test name
Test status
Simulation time 1536750000 ps
CPU time 3.17 seconds
Started Dec 24 12:34:44 PM PST 23
Finished Dec 24 12:35:32 PM PST 23
Peak memory 155732 kb
Host smart-66419463-87fb-45cf-82cb-1f9e7273b63a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2700730125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2700730125
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1565901190
Short name T56
Test name
Test status
Simulation time 1427170000 ps
CPU time 2.82 seconds
Started Dec 24 12:34:42 PM PST 23
Finished Dec 24 12:35:21 PM PST 23
Peak memory 155720 kb
Host smart-fcb9d128-8430-4d2d-89e2-86eeead9888a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1565901190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1565901190
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.530938091
Short name T45
Test name
Test status
Simulation time 1502470000 ps
CPU time 3.31 seconds
Started Dec 24 12:34:56 PM PST 23
Finished Dec 24 12:35:39 PM PST 23
Peak memory 155776 kb
Host smart-cc7d696d-2176-41cc-9b81-db15fd65f3d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=530938091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.530938091
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.21418809
Short name T40
Test name
Test status
Simulation time 1627030000 ps
CPU time 3.94 seconds
Started Dec 24 12:34:49 PM PST 23
Finished Dec 24 12:35:31 PM PST 23
Peak memory 155796 kb
Host smart-879010c2-b977-4bad-aae8-bb0238592e98
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=21418809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.21418809
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.549409713
Short name T70
Test name
Test status
Simulation time 1224270000 ps
CPU time 2.99 seconds
Started Dec 24 12:34:43 PM PST 23
Finished Dec 24 12:35:23 PM PST 23
Peak memory 155784 kb
Host smart-3b856eda-c342-42c3-beec-af70967b6b4e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=549409713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.549409713
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2589937136
Short name T3
Test name
Test status
Simulation time 1463350000 ps
CPU time 4.07 seconds
Started Dec 24 12:34:47 PM PST 23
Finished Dec 24 12:35:30 PM PST 23
Peak memory 155696 kb
Host smart-6b1c1d82-e498-45b5-b2c7-e506007d60fc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2589937136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2589937136
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.856593862
Short name T13
Test name
Test status
Simulation time 1442790000 ps
CPU time 3.21 seconds
Started Dec 24 12:34:49 PM PST 23
Finished Dec 24 12:35:32 PM PST 23
Peak memory 155760 kb
Host smart-e1cf9a8e-9852-41d7-a948-5654d9ff1070
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=856593862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.856593862
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.819421578
Short name T47
Test name
Test status
Simulation time 1510330000 ps
CPU time 2.92 seconds
Started Dec 24 12:34:51 PM PST 23
Finished Dec 24 12:35:33 PM PST 23
Peak memory 155744 kb
Host smart-dbef3f25-22dd-4e7d-a996-c3283c4a350b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=819421578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.819421578
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.689413455
Short name T12
Test name
Test status
Simulation time 1500830000 ps
CPU time 4.02 seconds
Started Dec 24 12:34:50 PM PST 23
Finished Dec 24 12:35:34 PM PST 23
Peak memory 155800 kb
Host smart-53f28d65-4298-4d85-a239-51df1f6cb72f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=689413455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.689413455
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2746987066
Short name T36
Test name
Test status
Simulation time 1457210000 ps
CPU time 2.81 seconds
Started Dec 24 12:34:47 PM PST 23
Finished Dec 24 12:35:26 PM PST 23
Peak memory 155636 kb
Host smart-8a9a408b-f6f0-4b32-b103-4da750af42f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2746987066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2746987066
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.403429474
Short name T69
Test name
Test status
Simulation time 1421790000 ps
CPU time 3.03 seconds
Started Dec 24 12:34:31 PM PST 23
Finished Dec 24 12:35:09 PM PST 23
Peak memory 155724 kb
Host smart-df1ba2b4-7e90-4005-afb5-75b761b99b85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=403429474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.403429474
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.465198278
Short name T52
Test name
Test status
Simulation time 1189270000 ps
CPU time 3.2 seconds
Started Dec 24 12:34:53 PM PST 23
Finished Dec 24 12:35:36 PM PST 23
Peak memory 155636 kb
Host smart-4e1c5951-b764-494e-9507-91b396fad894
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=465198278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.465198278
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3815678969
Short name T60
Test name
Test status
Simulation time 1554750000 ps
CPU time 3.08 seconds
Started Dec 24 12:35:15 PM PST 23
Finished Dec 24 12:35:51 PM PST 23
Peak memory 155724 kb
Host smart-7fd9eed7-d84f-4de4-8935-73f044502436
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3815678969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3815678969
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1262624343
Short name T68
Test name
Test status
Simulation time 1439850000 ps
CPU time 3.1 seconds
Started Dec 24 12:34:47 PM PST 23
Finished Dec 24 12:35:28 PM PST 23
Peak memory 155680 kb
Host smart-71d4aa99-a282-40cf-9966-04edf6e9a72a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1262624343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1262624343
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.201011422
Short name T58
Test name
Test status
Simulation time 1466330000 ps
CPU time 4.51 seconds
Started Dec 24 12:34:43 PM PST 23
Finished Dec 24 12:35:26 PM PST 23
Peak memory 155684 kb
Host smart-9e39f56c-9698-4438-95d5-183111b01156
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=201011422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.201011422
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3569478462
Short name T35
Test name
Test status
Simulation time 1433070000 ps
CPU time 3.27 seconds
Started Dec 24 12:34:50 PM PST 23
Finished Dec 24 12:35:34 PM PST 23
Peak memory 155636 kb
Host smart-2578fb58-fdb1-479a-9f95-574868a3cf2b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569478462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3569478462
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3590899189
Short name T7
Test name
Test status
Simulation time 1496650000 ps
CPU time 4.37 seconds
Started Dec 24 12:35:16 PM PST 23
Finished Dec 24 12:35:55 PM PST 23
Peak memory 155708 kb
Host smart-433fbb87-ff00-4ccf-9a13-2ed63d4bc3b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3590899189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3590899189
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3710432381
Short name T65
Test name
Test status
Simulation time 1314870000 ps
CPU time 2.89 seconds
Started Dec 24 12:34:54 PM PST 23
Finished Dec 24 12:35:36 PM PST 23
Peak memory 155724 kb
Host smart-801527c3-73b8-45d6-a3ed-1c35bd4da915
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3710432381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3710432381
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3844348659
Short name T49
Test name
Test status
Simulation time 1301110000 ps
CPU time 2.52 seconds
Started Dec 24 12:34:53 PM PST 23
Finished Dec 24 12:35:35 PM PST 23
Peak memory 155704 kb
Host smart-56399140-2626-4a9a-a197-19187816b246
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844348659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3844348659
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.987730257
Short name T2
Test name
Test status
Simulation time 1487230000 ps
CPU time 2.74 seconds
Started Dec 24 12:34:47 PM PST 23
Finished Dec 24 12:35:28 PM PST 23
Peak memory 155776 kb
Host smart-fdd203b1-906d-4af9-bad8-a6aeb127ea7b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=987730257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.987730257
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.831060018
Short name T31
Test name
Test status
Simulation time 1528690000 ps
CPU time 3.18 seconds
Started Dec 24 12:34:51 PM PST 23
Finished Dec 24 12:35:34 PM PST 23
Peak memory 155784 kb
Host smart-54d4a32a-09e7-4e72-839f-2eacb8c6e5f0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=831060018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.831060018
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2635526329
Short name T50
Test name
Test status
Simulation time 1550330000 ps
CPU time 2.92 seconds
Started Dec 24 12:34:54 PM PST 23
Finished Dec 24 12:35:37 PM PST 23
Peak memory 155772 kb
Host smart-de846cdf-2d48-401d-a6db-9412f1fe96e1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2635526329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2635526329
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3962425736
Short name T8
Test name
Test status
Simulation time 1202370000 ps
CPU time 2.62 seconds
Started Dec 24 12:34:43 PM PST 23
Finished Dec 24 12:35:23 PM PST 23
Peak memory 155772 kb
Host smart-23e41891-4d33-45ff-a1fb-88df5034ed10
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3962425736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3962425736
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4173224994
Short name T42
Test name
Test status
Simulation time 1514490000 ps
CPU time 3.18 seconds
Started Dec 24 12:35:11 PM PST 23
Finished Dec 24 12:35:49 PM PST 23
Peak memory 155708 kb
Host smart-787dc4ad-1b90-464d-b73e-11666b066109
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173224994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4173224994
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1341263752
Short name T38
Test name
Test status
Simulation time 1323010000 ps
CPU time 2.79 seconds
Started Dec 24 12:34:46 PM PST 23
Finished Dec 24 12:35:25 PM PST 23
Peak memory 155784 kb
Host smart-8e189a9e-a2c1-4584-bfc9-77e935af2e99
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341263752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1341263752
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4202084691
Short name T32
Test name
Test status
Simulation time 1525390000 ps
CPU time 4.74 seconds
Started Dec 24 12:35:20 PM PST 23
Finished Dec 24 12:36:02 PM PST 23
Peak memory 155680 kb
Host smart-f479b410-959a-4831-9cd3-cfd24ad0612b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4202084691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4202084691
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1919007398
Short name T10
Test name
Test status
Simulation time 1533530000 ps
CPU time 2.92 seconds
Started Dec 24 12:34:55 PM PST 23
Finished Dec 24 12:35:38 PM PST 23
Peak memory 155808 kb
Host smart-7daea4bd-7485-4668-8e44-85e50ea1bdef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1919007398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1919007398
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3697230411
Short name T37
Test name
Test status
Simulation time 1280070000 ps
CPU time 2.98 seconds
Started Dec 24 12:35:07 PM PST 23
Finished Dec 24 12:35:46 PM PST 23
Peak memory 155784 kb
Host smart-0b3d4fcb-cff3-4a5c-8ae2-74247c74fda0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3697230411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3697230411
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2195819861
Short name T39
Test name
Test status
Simulation time 1347210000 ps
CPU time 2.92 seconds
Started Dec 24 12:34:46 PM PST 23
Finished Dec 24 12:35:25 PM PST 23
Peak memory 155784 kb
Host smart-f2706a99-1145-4ae6-9939-27862a8f7aeb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2195819861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2195819861
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2169419744
Short name T9
Test name
Test status
Simulation time 1551430000 ps
CPU time 2.86 seconds
Started Dec 24 12:34:47 PM PST 23
Finished Dec 24 12:35:27 PM PST 23
Peak memory 155708 kb
Host smart-dbb5e9c1-710d-4c99-91b0-ebabd09f1fda
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2169419744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2169419744
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.981143514
Short name T61
Test name
Test status
Simulation time 1571170000 ps
CPU time 3.71 seconds
Started Dec 24 12:34:58 PM PST 23
Finished Dec 24 12:35:46 PM PST 23
Peak memory 155944 kb
Host smart-c9d9d3eb-cc06-450b-b5f7-3ae428be4438
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=981143514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.981143514
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.999167133
Short name T59
Test name
Test status
Simulation time 1354890000 ps
CPU time 4.24 seconds
Started Dec 24 12:34:41 PM PST 23
Finished Dec 24 12:35:24 PM PST 23
Peak memory 155756 kb
Host smart-b8e0d5a8-ed43-4bbd-906d-61465577ed2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=999167133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.999167133
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2378705499
Short name T55
Test name
Test status
Simulation time 1385330000 ps
CPU time 2.7 seconds
Started Dec 24 12:34:42 PM PST 23
Finished Dec 24 12:35:21 PM PST 23
Peak memory 155732 kb
Host smart-a172473f-9f5e-4896-bdf8-146140bf8344
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2378705499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2378705499
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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