Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1021081186
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3038428490
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.793288240

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1118265954
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1811713511
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4212949503
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3197511391
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4064588919
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.170246260
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.513744970
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2450032687
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3265246270
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2417123481
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2748384074
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2737897381
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1392487898
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1441259773
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3899683167
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1660017509
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3162233919
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1424793266
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3769144324
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3884373118
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1019969484
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2602100747
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1091502312
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.193965601
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2902160144
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.399645779
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3602856390
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2816642525
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1970183700
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3598950401
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4061480921
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.118417706
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1348409180
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2001626512
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1654168525
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4023720774
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3390525683
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1161348297
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1881725128
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3357622506
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4047541293
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1387183255
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2403972468
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1997069922
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3520381133
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2341555796
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3748247749
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1630105070
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3946229980
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2174916220
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.531149695
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1638487008
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.175956258
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2147165582
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3549577987
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1263754168
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.555668052
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1499421
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2686844397
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.362410333
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3027575969
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.874146675
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1258305149
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3726449572
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1677315972
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.919590914
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.142410852
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3625675539
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1454272686
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2444399981
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.847402511
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2915892586
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1756596378
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1918784717
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.268311418
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2588557663
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1826010330
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2010341271
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3158051931
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.571330336
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2529127647
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.637077559
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.418070959
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1672211309
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2053957442
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2340123412
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.863518405
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3379733598
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1896023203
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3059507510
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4225891851
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3142429549
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1179742914
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2823499146
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1311337199
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.236470048
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.49803296
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1259881546
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2378091977
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.982139163
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2720552400
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2608387221
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3760666848
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2409509788
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2716817386
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1302989774
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4018901673
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1862240843
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1429197677
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1803113682
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3201217730
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.946766817
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3535531149
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.507440227
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2453564696
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3456485713
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3631865587
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2229752059
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1964238189
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4087782679
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.517354002
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2271186790
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.442820762
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2071995199
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1065158988
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1052388337
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.17020441
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2862300087
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2274972954
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3872338118
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1483624091
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.98048042
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.611190049
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1135406373
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2283630931
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.701142087
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1697927485
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1993010869
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3622574199
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.805323206
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.575105719
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2997575069
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1899319449
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1736586476
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3639793342
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4000474732
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.326923742
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3781108666
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3730607183
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4139092645
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3891704436
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2018905052
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3896894104
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3420882458
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.281897300
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1328958663
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.728266335
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.857533246
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.471244533
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1737019054
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2668942019
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.790367537
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3723044294
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1460374090
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2832958445
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4012510092
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2337768583
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3689598176
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3825906734
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.835341687
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4252337190
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3398211559
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1539982838
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1047381046
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.124994399
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1601820374
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1477287405
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2753468841
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1495515027
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.218813659
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3184597925
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2865144511
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.149621446
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1094743176
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3775150656
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.7010029
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3121416893
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1860669365
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2988339571
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2673341557
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.187680464
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4120002347
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3482720563
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1828696097
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1499257976
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2926665353
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2631825149



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3420882458 Dec 27 12:35:39 PM PST 23 Dec 27 12:36:01 PM PST 23 1496530000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1021081186 Dec 27 12:36:27 PM PST 23 Dec 27 12:36:56 PM PST 23 1381190000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1828696097 Dec 27 12:36:16 PM PST 23 Dec 27 12:36:46 PM PST 23 1525190000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.149621446 Dec 27 12:35:25 PM PST 23 Dec 27 12:35:46 PM PST 23 1598390000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2832958445 Dec 27 12:35:39 PM PST 23 Dec 27 12:36:00 PM PST 23 1537670000 ps
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T130 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1454272686 Dec 27 12:41:09 PM PST 23 Dec 27 01:08:47 PM PST 23 336736770000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1179742914 Dec 27 12:40:54 PM PST 23 Dec 27 01:10:09 PM PST 23 336533530000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3726449572 Dec 27 12:40:51 PM PST 23 Dec 27 01:09:08 PM PST 23 336464370000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1259881546 Dec 27 12:40:43 PM PST 23 Dec 27 01:03:51 PM PST 23 337140110000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3625675539 Dec 27 12:41:03 PM PST 23 Dec 27 01:11:50 PM PST 23 336635970000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.142410852 Dec 27 12:40:50 PM PST 23 Dec 27 01:08:31 PM PST 23 336996830000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2147165582 Dec 27 12:40:45 PM PST 23 Dec 27 01:04:56 PM PST 23 336817770000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.847402511 Dec 27 12:41:02 PM PST 23 Dec 27 01:07:12 PM PST 23 337071990000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1672211309 Dec 27 12:40:56 PM PST 23 Dec 27 01:09:47 PM PST 23 337013010000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2823499146 Dec 27 12:40:58 PM PST 23 Dec 27 01:08:47 PM PST 23 336695090000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2588557663 Dec 27 12:40:56 PM PST 23 Dec 27 01:07:53 PM PST 23 336407910000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.362410333 Dec 27 12:41:16 PM PST 23 Dec 27 01:11:34 PM PST 23 336772810000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.49803296 Dec 27 12:40:42 PM PST 23 Dec 27 01:07:35 PM PST 23 336431210000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2053957442 Dec 27 12:40:51 PM PST 23 Dec 27 01:11:34 PM PST 23 336541590000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4225891851 Dec 27 12:40:57 PM PST 23 Dec 27 01:06:07 PM PST 23 336570930000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1258305149 Dec 27 12:40:52 PM PST 23 Dec 27 01:09:11 PM PST 23 336951510000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.236470048 Dec 27 12:40:28 PM PST 23 Dec 27 01:07:11 PM PST 23 336567550000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1896023203 Dec 27 12:41:07 PM PST 23 Dec 27 01:10:58 PM PST 23 336480430000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3142429549 Dec 27 12:41:09 PM PST 23 Dec 27 01:08:31 PM PST 23 336512850000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2174916220 Dec 27 12:40:45 PM PST 23 Dec 27 01:08:16 PM PST 23 336372930000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1638487008 Dec 27 12:41:07 PM PST 23 Dec 27 01:09:42 PM PST 23 336814110000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.701142087 Dec 27 12:41:01 PM PST 23 Dec 27 12:42:13 PM PST 23 1392670000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2997575069 Dec 27 12:41:06 PM PST 23 Dec 27 12:42:17 PM PST 23 1525770000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1803113682 Dec 27 12:41:06 PM PST 23 Dec 27 12:42:15 PM PST 23 1138050000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1899319449 Dec 27 12:41:00 PM PST 23 Dec 27 12:42:12 PM PST 23 1498830000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2608387221 Dec 27 12:41:02 PM PST 23 Dec 27 12:42:12 PM PST 23 1347590000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.442820762 Dec 27 12:41:10 PM PST 23 Dec 27 12:42:20 PM PST 23 1456190000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2274972954 Dec 27 12:41:21 PM PST 23 Dec 27 12:42:29 PM PST 23 1454530000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2720552400 Dec 27 12:41:04 PM PST 23 Dec 27 12:42:14 PM PST 23 1269170000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.611190049 Dec 27 12:41:12 PM PST 23 Dec 27 12:42:23 PM PST 23 1500850000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2378091977 Dec 27 12:40:57 PM PST 23 Dec 27 12:42:10 PM PST 23 1512610000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2283630931 Dec 27 12:40:47 PM PST 23 Dec 27 12:41:54 PM PST 23 1114610000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1964238189 Dec 27 12:40:55 PM PST 23 Dec 27 12:42:05 PM PST 23 1279610000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2409509788 Dec 27 12:40:52 PM PST 23 Dec 27 12:42:04 PM PST 23 1412330000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1135406373 Dec 27 12:40:38 PM PST 23 Dec 27 12:41:44 PM PST 23 1273270000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1065158988 Dec 27 12:41:10 PM PST 23 Dec 27 12:42:21 PM PST 23 1617630000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3201217730 Dec 27 12:40:56 PM PST 23 Dec 27 12:42:06 PM PST 23 1319030000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3631865587 Dec 27 12:41:06 PM PST 23 Dec 27 12:42:16 PM PST 23 1413410000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1429197677 Dec 27 12:41:14 PM PST 23 Dec 27 12:42:25 PM PST 23 1529950000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2071995199 Dec 27 12:40:51 PM PST 23 Dec 27 12:42:00 PM PST 23 1284570000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4000474732 Dec 27 12:40:58 PM PST 23 Dec 27 12:42:09 PM PST 23 1514470000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3872338118 Dec 27 12:41:08 PM PST 23 Dec 27 12:42:21 PM PST 23 1368390000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.98048042 Dec 27 12:40:48 PM PST 23 Dec 27 12:42:02 PM PST 23 1439430000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.17020441 Dec 27 12:41:02 PM PST 23 Dec 27 12:42:16 PM PST 23 1543490000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.805323206 Dec 27 12:41:09 PM PST 23 Dec 27 12:42:19 PM PST 23 1504650000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1697927485 Dec 27 12:41:03 PM PST 23 Dec 27 12:42:16 PM PST 23 1424330000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3639793342 Dec 27 12:41:09 PM PST 23 Dec 27 12:42:21 PM PST 23 1485850000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2862300087 Dec 27 12:41:26 PM PST 23 Dec 27 12:42:34 PM PST 23 1248450000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1483624091 Dec 27 12:41:15 PM PST 23 Dec 27 12:42:25 PM PST 23 1463490000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.946766817 Dec 27 12:41:04 PM PST 23 Dec 27 12:42:14 PM PST 23 1556530000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1993010869 Dec 27 12:41:10 PM PST 23 Dec 27 12:42:21 PM PST 23 1482070000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.575105719 Dec 27 12:41:23 PM PST 23 Dec 27 12:42:30 PM PST 23 1208990000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2453564696 Dec 27 12:40:46 PM PST 23 Dec 27 12:41:53 PM PST 23 1401930000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.517354002 Dec 27 12:41:08 PM PST 23 Dec 27 12:42:18 PM PST 23 1497330000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3622574199 Dec 27 12:41:07 PM PST 23 Dec 27 12:42:21 PM PST 23 1426730000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3456485713 Dec 27 12:41:09 PM PST 23 Dec 27 12:42:20 PM PST 23 1633130000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3535531149 Dec 27 12:41:02 PM PST 23 Dec 27 12:42:14 PM PST 23 1450490000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3760666848 Dec 27 12:41:19 PM PST 23 Dec 27 12:42:29 PM PST 23 1473890000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2271186790 Dec 27 12:40:54 PM PST 23 Dec 27 12:42:04 PM PST 23 1449450000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4018901673 Dec 27 12:41:03 PM PST 23 Dec 27 12:42:14 PM PST 23 1456710000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3781108666 Dec 27 12:40:47 PM PST 23 Dec 27 12:41:54 PM PST 23 1482010000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1736586476 Dec 27 12:41:10 PM PST 23 Dec 27 12:42:20 PM PST 23 1439290000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2716817386 Dec 27 12:41:22 PM PST 23 Dec 27 12:42:29 PM PST 23 1330730000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4087782679 Dec 27 12:40:52 PM PST 23 Dec 27 12:42:03 PM PST 23 1494490000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1052388337 Dec 27 12:41:01 PM PST 23 Dec 27 12:42:11 PM PST 23 1397010000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1302989774 Dec 27 12:41:11 PM PST 23 Dec 27 12:42:22 PM PST 23 1433750000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.982139163 Dec 27 12:40:58 PM PST 23 Dec 27 12:42:09 PM PST 23 1459470000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.326923742 Dec 27 12:41:01 PM PST 23 Dec 27 12:42:12 PM PST 23 1558550000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2229752059 Dec 27 12:41:02 PM PST 23 Dec 27 12:42:12 PM PST 23 1332730000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1862240843 Dec 27 12:40:59 PM PST 23 Dec 27 12:42:11 PM PST 23 1444830000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.507440227 Dec 27 12:41:04 PM PST 23 Dec 27 12:42:15 PM PST 23 1499090000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1021081186
Short name T2
Test name
Test status
Simulation time 1381190000 ps
CPU time 2.98 seconds
Started Dec 27 12:36:27 PM PST 23
Finished Dec 27 12:36:56 PM PST 23
Peak memory 155740 kb
Host smart-385f78ef-5069-4415-98df-0cd877b0f8bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1021081186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1021081186
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3038428490
Short name T17
Test name
Test status
Simulation time 336362510000 ps
CPU time 750.48 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:50:14 PM PST 23
Peak memory 160556 kb
Host smart-315d4a49-50f0-4dd1-84a0-214120780951
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3038428490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3038428490
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.793288240
Short name T22
Test name
Test status
Simulation time 336956790000 ps
CPU time 710.96 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 01:10:35 PM PST 23
Peak memory 160880 kb
Host smart-660556c2-d7e7-4623-a4e0-af7545690dc4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=793288240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.793288240
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1118265954
Short name T73
Test name
Test status
Simulation time 336536270000 ps
CPU time 682.48 seconds
Started Dec 27 12:21:12 PM PST 23
Finished Dec 27 12:48:41 PM PST 23
Peak memory 160276 kb
Host smart-216ce711-fe25-46e6-8f1c-c4979256ecc3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1118265954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1118265954
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1811713511
Short name T79
Test name
Test status
Simulation time 336491490000 ps
CPU time 640.75 seconds
Started Dec 27 12:21:12 PM PST 23
Finished Dec 27 12:47:24 PM PST 23
Peak memory 160276 kb
Host smart-8b5dd654-9224-4bfa-928d-1df7ee7c6393
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811713511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1811713511
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4212949503
Short name T100
Test name
Test status
Simulation time 337040910000 ps
CPU time 933.27 seconds
Started Dec 27 12:19:31 PM PST 23
Finished Dec 27 12:57:39 PM PST 23
Peak memory 160296 kb
Host smart-0cde88e9-88ea-4438-847b-e6774b7c2cdc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4212949503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.4212949503
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3197511391
Short name T91
Test name
Test status
Simulation time 336641290000 ps
CPU time 656.58 seconds
Started Dec 27 12:19:20 PM PST 23
Finished Dec 27 12:45:45 PM PST 23
Peak memory 159512 kb
Host smart-a78a9cba-da61-409d-bd24-dd3446cdb7db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3197511391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3197511391
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4064588919
Short name T101
Test name
Test status
Simulation time 336910270000 ps
CPU time 958.42 seconds
Started Dec 27 12:19:31 PM PST 23
Finished Dec 27 12:58:01 PM PST 23
Peak memory 160296 kb
Host smart-c45d19c1-9226-4e0f-9c17-d941565c10e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4064588919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4064588919
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.170246260
Short name T96
Test name
Test status
Simulation time 336398090000 ps
CPU time 674.52 seconds
Started Dec 27 12:21:12 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 160256 kb
Host smart-0c067256-bfd4-4297-a33e-a5011e8d5fe5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=170246260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.170246260
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.513744970
Short name T81
Test name
Test status
Simulation time 336518070000 ps
CPU time 922.23 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:55:47 PM PST 23
Peak memory 158124 kb
Host smart-3b9e2e0b-b900-4b86-9e34-f5b953ae1ed2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=513744970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.513744970
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2450032687
Short name T20
Test name
Test status
Simulation time 336708130000 ps
CPU time 747.45 seconds
Started Dec 27 12:21:12 PM PST 23
Finished Dec 27 12:50:48 PM PST 23
Peak memory 160156 kb
Host smart-6a15eb42-c9cf-481f-a24a-139a5dc9fa5d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2450032687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2450032687
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3265246270
Short name T16
Test name
Test status
Simulation time 336611770000 ps
CPU time 638.04 seconds
Started Dec 27 12:19:21 PM PST 23
Finished Dec 27 12:45:50 PM PST 23
Peak memory 159892 kb
Host smart-534b3eb1-f83c-4fb8-86ee-cfd8db897111
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3265246270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3265246270
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2417123481
Short name T74
Test name
Test status
Simulation time 336897430000 ps
CPU time 741.71 seconds
Started Dec 27 12:21:12 PM PST 23
Finished Dec 27 12:50:39 PM PST 23
Peak memory 160144 kb
Host smart-c54cec8c-6e09-4391-9cd6-4c120b36aeb5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2417123481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2417123481
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2748384074
Short name T5
Test name
Test status
Simulation time 336489870000 ps
CPU time 722.9 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:57:18 PM PST 23
Peak memory 158832 kb
Host smart-e8ee5aa6-3ffc-455c-8942-6702c5e9a9ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2748384074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2748384074
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2737897381
Short name T14
Test name
Test status
Simulation time 336847470000 ps
CPU time 921.92 seconds
Started Dec 27 12:19:30 PM PST 23
Finished Dec 27 12:57:13 PM PST 23
Peak memory 160200 kb
Host smart-7de8682d-de07-48fd-948a-7eecf200243e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2737897381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2737897381
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1392487898
Short name T103
Test name
Test status
Simulation time 336483690000 ps
CPU time 945.28 seconds
Started Dec 27 12:19:31 PM PST 23
Finished Dec 27 12:58:12 PM PST 23
Peak memory 160296 kb
Host smart-7a07b2d2-4180-44e0-b986-7cb261adb2b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1392487898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1392487898
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1441259773
Short name T98
Test name
Test status
Simulation time 336939030000 ps
CPU time 941.52 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:56:05 PM PST 23
Peak memory 157384 kb
Host smart-c7d5f6cb-de91-4502-8ed7-9e8d99a8179e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1441259773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1441259773
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3899683167
Short name T106
Test name
Test status
Simulation time 336489170000 ps
CPU time 739.09 seconds
Started Dec 27 12:20:59 PM PST 23
Finished Dec 27 12:51:07 PM PST 23
Peak memory 160196 kb
Host smart-d79a617d-2a3e-41e6-a7a6-c4ab7a541f31
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3899683167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3899683167
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1660017509
Short name T94
Test name
Test status
Simulation time 337018010000 ps
CPU time 596.48 seconds
Started Dec 27 12:21:21 PM PST 23
Finished Dec 27 12:46:18 PM PST 23
Peak memory 160468 kb
Host smart-e6b0dedf-d64a-4567-87d2-f3a9f6c122ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1660017509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1660017509
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3162233919
Short name T99
Test name
Test status
Simulation time 337091990000 ps
CPU time 663.85 seconds
Started Dec 27 12:27:33 PM PST 23
Finished Dec 27 12:54:55 PM PST 23
Peak memory 159540 kb
Host smart-9b568351-688d-41e4-aabb-ab53cd419302
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3162233919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3162233919
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1424793266
Short name T107
Test name
Test status
Simulation time 336639550000 ps
CPU time 904.97 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:55:05 PM PST 23
Peak memory 159104 kb
Host smart-9ad39ad7-55eb-4943-9610-7b5cccac91d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1424793266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1424793266
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3769144324
Short name T75
Test name
Test status
Simulation time 336967850000 ps
CPU time 684.23 seconds
Started Dec 27 12:19:28 PM PST 23
Finished Dec 27 12:47:39 PM PST 23
Peak memory 160300 kb
Host smart-f0231f9b-ee9a-42cb-9867-b0f8a7a951eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3769144324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3769144324
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3884373118
Short name T71
Test name
Test status
Simulation time 336729370000 ps
CPU time 606.06 seconds
Started Dec 27 12:20:52 PM PST 23
Finished Dec 27 12:45:57 PM PST 23
Peak memory 160476 kb
Host smart-66a1bf40-7fcb-4cc2-8005-fa7ea5fab8d0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3884373118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3884373118
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1019969484
Short name T90
Test name
Test status
Simulation time 336869130000 ps
CPU time 790.51 seconds
Started Dec 27 12:21:02 PM PST 23
Finished Dec 27 12:52:29 PM PST 23
Peak memory 160272 kb
Host smart-ff04950c-ea74-45ac-9659-e81ea688b11e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1019969484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1019969484
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2602100747
Short name T15
Test name
Test status
Simulation time 336867030000 ps
CPU time 923.68 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:55:46 PM PST 23
Peak memory 158032 kb
Host smart-7c23da0b-19b0-4ae3-862c-56ae9b1c5819
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2602100747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2602100747
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1091502312
Short name T84
Test name
Test status
Simulation time 336799090000 ps
CPU time 677.68 seconds
Started Dec 27 12:21:12 PM PST 23
Finished Dec 27 12:48:25 PM PST 23
Peak memory 160244 kb
Host smart-42735f1e-2582-4464-98c5-a76d824dd242
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1091502312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1091502312
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.193965601
Short name T77
Test name
Test status
Simulation time 336342410000 ps
CPU time 735.32 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:58:47 PM PST 23
Peak memory 160136 kb
Host smart-9d583a0d-fac4-4aa7-bf25-3acad0ad27ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=193965601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.193965601
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2902160144
Short name T83
Test name
Test status
Simulation time 337029730000 ps
CPU time 748.2 seconds
Started Dec 27 12:20:59 PM PST 23
Finished Dec 27 12:51:19 PM PST 23
Peak memory 160180 kb
Host smart-7f2ae9cd-672f-4401-ba9a-5734caa31d93
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2902160144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2902160144
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.399645779
Short name T97
Test name
Test status
Simulation time 336885990000 ps
CPU time 741.6 seconds
Started Dec 27 12:26:29 PM PST 23
Finished Dec 27 12:56:31 PM PST 23
Peak memory 160260 kb
Host smart-7e8bce4a-80a7-4674-b364-73e1c6fe7cfe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399645779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.399645779
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3602856390
Short name T105
Test name
Test status
Simulation time 336536150000 ps
CPU time 926.41 seconds
Started Dec 27 12:19:31 PM PST 23
Finished Dec 27 12:57:08 PM PST 23
Peak memory 160296 kb
Host smart-25f157cb-ff87-4ac2-bb34-8a76bbe97230
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3602856390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3602856390
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2816642525
Short name T110
Test name
Test status
Simulation time 336673710000 ps
CPU time 715.84 seconds
Started Dec 27 12:21:03 PM PST 23
Finished Dec 27 12:49:50 PM PST 23
Peak memory 160272 kb
Host smart-f96ecd46-dc15-4614-b3f0-7406350ebf1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2816642525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2816642525
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1970183700
Short name T72
Test name
Test status
Simulation time 336676210000 ps
CPU time 556.07 seconds
Started Dec 27 12:24:54 PM PST 23
Finished Dec 27 12:48:28 PM PST 23
Peak memory 160416 kb
Host smart-c14395d8-27e8-4f9a-80b0-6d180b02f9b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1970183700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1970183700
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3598950401
Short name T87
Test name
Test status
Simulation time 336691190000 ps
CPU time 557.95 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:53:06 PM PST 23
Peak memory 160168 kb
Host smart-590fc277-4565-430f-bbd6-397498582920
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3598950401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3598950401
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4061480921
Short name T6
Test name
Test status
Simulation time 337087730000 ps
CPU time 708.6 seconds
Started Dec 27 12:29:02 PM PST 23
Finished Dec 27 12:58:43 PM PST 23
Peak memory 160172 kb
Host smart-ba4eb4f3-5489-49ca-a57f-5f219f776898
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4061480921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.4061480921
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.118417706
Short name T78
Test name
Test status
Simulation time 336664250000 ps
CPU time 663.33 seconds
Started Dec 27 12:28:00 PM PST 23
Finished Dec 27 12:55:56 PM PST 23
Peak memory 160116 kb
Host smart-00c642b2-60b1-404a-bd2f-ec94f27a0195
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=118417706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.118417706
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1348409180
Short name T76
Test name
Test status
Simulation time 336584070000 ps
CPU time 880.41 seconds
Started Dec 27 12:20:00 PM PST 23
Finished Dec 27 12:55:20 PM PST 23
Peak memory 160052 kb
Host smart-4097f9a1-6734-4862-ac2f-95bb0eb79402
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1348409180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1348409180
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2001626512
Short name T92
Test name
Test status
Simulation time 336779550000 ps
CPU time 855.83 seconds
Started Dec 27 12:19:27 PM PST 23
Finished Dec 27 12:53:36 PM PST 23
Peak memory 159908 kb
Host smart-157163de-e88b-4f94-8241-ace7a90aeaa8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2001626512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2001626512
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1654168525
Short name T95
Test name
Test status
Simulation time 336757110000 ps
CPU time 725.4 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:55:53 PM PST 23
Peak memory 160340 kb
Host smart-bce69461-32dd-453d-bac3-5cf8c191ed77
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1654168525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1654168525
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4023720774
Short name T86
Test name
Test status
Simulation time 337067570000 ps
CPU time 724.08 seconds
Started Dec 27 12:26:34 PM PST 23
Finished Dec 27 12:56:21 PM PST 23
Peak memory 160340 kb
Host smart-1b3a9c95-0d8f-4fa6-aac9-74e0bfca728f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4023720774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4023720774
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3390525683
Short name T109
Test name
Test status
Simulation time 336741730000 ps
CPU time 565.02 seconds
Started Dec 27 12:22:20 PM PST 23
Finished Dec 27 12:45:53 PM PST 23
Peak memory 160584 kb
Host smart-5c0a55f1-0315-4f3b-9f25-33179b517fa1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3390525683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3390525683
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1161348297
Short name T108
Test name
Test status
Simulation time 337045570000 ps
CPU time 763.54 seconds
Started Dec 27 12:20:17 PM PST 23
Finished Dec 27 12:51:06 PM PST 23
Peak memory 160556 kb
Host smart-48f4c58f-9587-45b7-bfe7-cb1051a5d082
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1161348297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1161348297
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1881725128
Short name T80
Test name
Test status
Simulation time 337013570000 ps
CPU time 638.08 seconds
Started Dec 27 12:28:48 PM PST 23
Finished Dec 27 12:55:54 PM PST 23
Peak memory 160136 kb
Host smart-2d97a16f-ba3d-4b6d-b9da-19501ed7ac7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1881725128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1881725128
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3357622506
Short name T104
Test name
Test status
Simulation time 336821670000 ps
CPU time 958.18 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:56:43 PM PST 23
Peak memory 157460 kb
Host smart-a2f7392f-e8c0-4b4c-a321-16e561a14bcc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3357622506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3357622506
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4047541293
Short name T89
Test name
Test status
Simulation time 336303370000 ps
CPU time 853.32 seconds
Started Dec 27 12:19:30 PM PST 23
Finished Dec 27 12:53:56 PM PST 23
Peak memory 160052 kb
Host smart-eae2b684-9c97-46b6-85b4-c3a1add06ed2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4047541293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.4047541293
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1387183255
Short name T102
Test name
Test status
Simulation time 337155070000 ps
CPU time 782.54 seconds
Started Dec 27 12:21:03 PM PST 23
Finished Dec 27 12:52:29 PM PST 23
Peak memory 160272 kb
Host smart-d534feb5-26af-46c8-b0d3-b375d4eb7f31
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1387183255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1387183255
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2403972468
Short name T93
Test name
Test status
Simulation time 336477930000 ps
CPU time 721.78 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:57:16 PM PST 23
Peak memory 158788 kb
Host smart-f858df68-79c2-4083-848b-22f3a843f1f6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2403972468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2403972468
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1997069922
Short name T82
Test name
Test status
Simulation time 336711190000 ps
CPU time 800.08 seconds
Started Dec 27 12:21:03 PM PST 23
Finished Dec 27 12:52:50 PM PST 23
Peak memory 160272 kb
Host smart-b30e62f2-12f7-4047-bae2-d0f50206caff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997069922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1997069922
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3520381133
Short name T19
Test name
Test status
Simulation time 336444350000 ps
CPU time 933.1 seconds
Started Dec 27 12:19:26 PM PST 23
Finished Dec 27 12:55:57 PM PST 23
Peak memory 158136 kb
Host smart-96791c1e-1536-4281-89e7-6e83ac7f859d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3520381133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3520381133
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2341555796
Short name T18
Test name
Test status
Simulation time 336318570000 ps
CPU time 683.9 seconds
Started Dec 27 12:19:16 PM PST 23
Finished Dec 27 12:46:46 PM PST 23
Peak memory 160216 kb
Host smart-ababe124-0368-45d0-a973-65204e9212fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2341555796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2341555796
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3748247749
Short name T88
Test name
Test status
Simulation time 336984990000 ps
CPU time 944.46 seconds
Started Dec 27 12:19:31 PM PST 23
Finished Dec 27 12:57:53 PM PST 23
Peak memory 160288 kb
Host smart-6cfb6b21-3d29-46f0-ba2c-f0c9d7a7bf7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3748247749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3748247749
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1630105070
Short name T85
Test name
Test status
Simulation time 336671530000 ps
CPU time 892.91 seconds
Started Dec 27 12:19:30 PM PST 23
Finished Dec 27 12:56:08 PM PST 23
Peak memory 160216 kb
Host smart-fe79db5f-a19f-403f-b670-0d2aaee5e65b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1630105070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1630105070
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3946229980
Short name T4
Test name
Test status
Simulation time 336366110000 ps
CPU time 757.09 seconds
Started Dec 27 12:19:18 PM PST 23
Finished Dec 27 12:49:40 PM PST 23
Peak memory 160548 kb
Host smart-25539792-939f-4ac4-8706-9ae914b86ca9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3946229980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3946229980
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2174916220
Short name T149
Test name
Test status
Simulation time 336372930000 ps
CPU time 641.14 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 01:08:16 PM PST 23
Peak memory 160916 kb
Host smart-cb37b6f8-f1be-4060-b1e3-4c9af3ad0897
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2174916220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2174916220
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.531149695
Short name T27
Test name
Test status
Simulation time 337013650000 ps
CPU time 649.45 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 01:08:20 PM PST 23
Peak memory 161052 kb
Host smart-e7dce80a-a080-490e-9d76-ac3440c9cccc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=531149695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.531149695
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1638487008
Short name T150
Test name
Test status
Simulation time 336814110000 ps
CPU time 672.41 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 01:09:42 PM PST 23
Peak memory 160944 kb
Host smart-4656a7fe-66f2-43ae-afd8-827d742453ff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1638487008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1638487008
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.175956258
Short name T129
Test name
Test status
Simulation time 336643910000 ps
CPU time 683.62 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 01:09:43 PM PST 23
Peak memory 160940 kb
Host smart-3b17840f-bd87-41d9-87ca-9ee9b3554344
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=175956258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.175956258
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2147165582
Short name T136
Test name
Test status
Simulation time 336817770000 ps
CPU time 555.34 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 01:04:56 PM PST 23
Peak memory 160968 kb
Host smart-d06fd8c8-3edb-4dda-86f1-49b4d694fc34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2147165582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2147165582
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3549577987
Short name T115
Test name
Test status
Simulation time 336548990000 ps
CPU time 575.43 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 01:06:04 PM PST 23
Peak memory 160968 kb
Host smart-1799db91-3dac-4f38-ac04-3134b8c32ed6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3549577987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3549577987
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1263754168
Short name T118
Test name
Test status
Simulation time 336946650000 ps
CPU time 638.97 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 01:08:20 PM PST 23
Peak memory 160968 kb
Host smart-bd025339-4215-48f3-a5f3-c51d8267afd1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1263754168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1263754168
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.555668052
Short name T113
Test name
Test status
Simulation time 336809410000 ps
CPU time 713.95 seconds
Started Dec 27 12:41:06 PM PST 23
Finished Dec 27 01:11:17 PM PST 23
Peak memory 160916 kb
Host smart-836df115-1954-47da-909e-0a35f790e672
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=555668052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.555668052
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1499421
Short name T125
Test name
Test status
Simulation time 336993850000 ps
CPU time 748.77 seconds
Started Dec 27 12:41:18 PM PST 23
Finished Dec 27 01:12:30 PM PST 23
Peak memory 160944 kb
Host smart-e61a9bb5-909c-4696-b223-610e168058e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1499421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1499421
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2686844397
Short name T25
Test name
Test status
Simulation time 336706230000 ps
CPU time 736.94 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 01:11:36 PM PST 23
Peak memory 160896 kb
Host smart-371227c8-c595-4fba-99c0-cc0649bd547c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2686844397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2686844397
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.362410333
Short name T141
Test name
Test status
Simulation time 336772810000 ps
CPU time 729.02 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 01:11:34 PM PST 23
Peak memory 160936 kb
Host smart-810732dd-ab05-452e-94f5-367d282a8e10
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=362410333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.362410333
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3027575969
Short name T121
Test name
Test status
Simulation time 336765490000 ps
CPU time 611.85 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 01:07:03 PM PST 23
Peak memory 160920 kb
Host smart-7239220c-25cb-40e4-87b6-037751c3f506
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3027575969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3027575969
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.874146675
Short name T112
Test name
Test status
Simulation time 336784890000 ps
CPU time 639.95 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 01:08:15 PM PST 23
Peak memory 160952 kb
Host smart-400d3e38-1e16-49af-97b6-2d734169992d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=874146675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.874146675
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1258305149
Short name T145
Test name
Test status
Simulation time 336951510000 ps
CPU time 654.7 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 01:09:11 PM PST 23
Peak memory 161056 kb
Host smart-bcf2d5b7-50db-4a54-9b5d-a181c3ba898c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1258305149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1258305149
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3726449572
Short name T132
Test name
Test status
Simulation time 336464370000 ps
CPU time 662.22 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 01:09:08 PM PST 23
Peak memory 161040 kb
Host smart-8eb4b544-f74b-42f0-ae36-bfeec897429a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3726449572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3726449572
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1677315972
Short name T126
Test name
Test status
Simulation time 336939050000 ps
CPU time 688.47 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 01:10:03 PM PST 23
Peak memory 161004 kb
Host smart-0a262c36-998a-47d8-8d3e-d4b6500c551b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1677315972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1677315972
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.919590914
Short name T117
Test name
Test status
Simulation time 337102310000 ps
CPU time 625.41 seconds
Started Dec 27 12:40:50 PM PST 23
Finished Dec 27 01:07:42 PM PST 23
Peak memory 160928 kb
Host smart-9147cd55-ea36-48dc-a264-b5a94344e60e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=919590914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.919590914
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.142410852
Short name T135
Test name
Test status
Simulation time 336996830000 ps
CPU time 648.24 seconds
Started Dec 27 12:40:50 PM PST 23
Finished Dec 27 01:08:31 PM PST 23
Peak memory 160980 kb
Host smart-c6224ae2-851a-41a4-b2bc-c78f386ba757
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=142410852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.142410852
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3625675539
Short name T134
Test name
Test status
Simulation time 336635970000 ps
CPU time 742.24 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 01:11:50 PM PST 23
Peak memory 160956 kb
Host smart-af8ba1e3-4330-4494-a236-c46d0e1e6c26
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625675539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3625675539
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1454272686
Short name T130
Test name
Test status
Simulation time 336736770000 ps
CPU time 647.26 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 01:08:47 PM PST 23
Peak memory 161068 kb
Host smart-43abfece-11c6-43e5-b38a-e37cd6ed73c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1454272686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1454272686
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2444399981
Short name T29
Test name
Test status
Simulation time 336398150000 ps
CPU time 683.8 seconds
Started Dec 27 12:40:44 PM PST 23
Finished Dec 27 01:09:37 PM PST 23
Peak memory 161012 kb
Host smart-34d09915-a7bc-4732-81f9-0f6917a59829
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2444399981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2444399981
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.847402511
Short name T137
Test name
Test status
Simulation time 337071990000 ps
CPU time 600.27 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 01:07:12 PM PST 23
Peak memory 160916 kb
Host smart-f03881d4-6325-44fe-bfd6-c2a63690bee9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=847402511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.847402511
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2915892586
Short name T111
Test name
Test status
Simulation time 336445750000 ps
CPU time 717.72 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 01:10:52 PM PST 23
Peak memory 160920 kb
Host smart-76ff0146-819b-419a-a532-bbb315bf0544
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2915892586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2915892586
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1756596378
Short name T114
Test name
Test status
Simulation time 336927370000 ps
CPU time 695.78 seconds
Started Dec 27 12:40:50 PM PST 23
Finished Dec 27 01:10:02 PM PST 23
Peak memory 160896 kb
Host smart-252aa05c-628b-4522-a761-521d6d6e8200
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1756596378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1756596378
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1918784717
Short name T120
Test name
Test status
Simulation time 336542990000 ps
CPU time 647.32 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 01:08:21 PM PST 23
Peak memory 161028 kb
Host smart-a5540ad9-2adc-49a3-9644-c4ae094d04ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1918784717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1918784717
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.268311418
Short name T128
Test name
Test status
Simulation time 336537110000 ps
CPU time 677.37 seconds
Started Dec 27 12:40:54 PM PST 23
Finished Dec 27 01:09:49 PM PST 23
Peak memory 160964 kb
Host smart-f4af7d31-1a4b-4130-a9d1-91b70a9b8b7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=268311418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.268311418
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2588557663
Short name T140
Test name
Test status
Simulation time 336407910000 ps
CPU time 623.46 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 01:07:53 PM PST 23
Peak memory 160900 kb
Host smart-41cf0687-da56-44e3-a77f-4b80ab57147c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2588557663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2588557663
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1826010330
Short name T122
Test name
Test status
Simulation time 336970710000 ps
CPU time 636.05 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 01:08:32 PM PST 23
Peak memory 161052 kb
Host smart-d66f697b-8069-4816-b7da-c3bffcba70a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1826010330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1826010330
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2010341271
Short name T26
Test name
Test status
Simulation time 336998070000 ps
CPU time 622.26 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 01:07:45 PM PST 23
Peak memory 160904 kb
Host smart-63087b7e-db12-4da4-900c-73b6f1e10837
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2010341271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2010341271
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3158051931
Short name T127
Test name
Test status
Simulation time 336987350000 ps
CPU time 637.77 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 01:08:28 PM PST 23
Peak memory 161052 kb
Host smart-758c019f-cefc-4c57-b3d5-adddce9e102e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3158051931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3158051931
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.571330336
Short name T119
Test name
Test status
Simulation time 336852510000 ps
CPU time 669.34 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 01:09:36 PM PST 23
Peak memory 160944 kb
Host smart-73252936-b1b3-478e-ac96-8e7b705fa117
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=571330336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.571330336
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2529127647
Short name T23
Test name
Test status
Simulation time 336864170000 ps
CPU time 614.39 seconds
Started Dec 27 12:40:48 PM PST 23
Finished Dec 27 01:07:08 PM PST 23
Peak memory 160884 kb
Host smart-58c9a155-fa44-4fdd-a2ef-cc27d053c131
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2529127647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2529127647
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.637077559
Short name T21
Test name
Test status
Simulation time 336417730000 ps
CPU time 584.81 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 01:06:09 PM PST 23
Peak memory 160924 kb
Host smart-a4cf1608-5b1b-445d-af55-26556ca77b40
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=637077559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.637077559
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.418070959
Short name T30
Test name
Test status
Simulation time 337122790000 ps
CPU time 635 seconds
Started Dec 27 12:40:44 PM PST 23
Finished Dec 27 01:07:58 PM PST 23
Peak memory 160928 kb
Host smart-8f0f34b5-059e-42f7-bd76-99a9ddc38f91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=418070959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.418070959
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1672211309
Short name T138
Test name
Test status
Simulation time 337013010000 ps
CPU time 665.88 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 01:09:47 PM PST 23
Peak memory 161032 kb
Host smart-17ba5303-c436-4d45-b276-2bbad7d9b14b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1672211309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1672211309
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2053957442
Short name T143
Test name
Test status
Simulation time 336541590000 ps
CPU time 728.67 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 01:11:34 PM PST 23
Peak memory 160904 kb
Host smart-65d646b2-d2c1-4b60-8ea4-264320ccf2a3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2053957442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2053957442
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2340123412
Short name T123
Test name
Test status
Simulation time 337033250000 ps
CPU time 572.49 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 01:05:59 PM PST 23
Peak memory 161056 kb
Host smart-985ac6bb-32f4-4a8f-9d7c-77147030fe57
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2340123412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2340123412
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.863518405
Short name T116
Test name
Test status
Simulation time 336972670000 ps
CPU time 638.14 seconds
Started Dec 27 12:40:58 PM PST 23
Finished Dec 27 01:08:13 PM PST 23
Peak memory 160896 kb
Host smart-65f6f9b8-dce5-49d5-8333-37c6b1f70e45
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=863518405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.863518405
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3379733598
Short name T24
Test name
Test status
Simulation time 336662510000 ps
CPU time 730.28 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 01:11:15 PM PST 23
Peak memory 160904 kb
Host smart-383dd7f5-3122-4304-817e-1f79a3a284d6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3379733598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3379733598
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1896023203
Short name T147
Test name
Test status
Simulation time 336480430000 ps
CPU time 712.52 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 01:10:58 PM PST 23
Peak memory 160896 kb
Host smart-518160c8-0263-4847-a694-660d5f9504a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1896023203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1896023203
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3059507510
Short name T28
Test name
Test status
Simulation time 336737770000 ps
CPU time 610.33 seconds
Started Dec 27 12:40:57 PM PST 23
Finished Dec 27 01:07:21 PM PST 23
Peak memory 161016 kb
Host smart-0a623313-eee0-40fb-9272-c6db417a32ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3059507510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3059507510
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4225891851
Short name T144
Test name
Test status
Simulation time 336570930000 ps
CPU time 586.06 seconds
Started Dec 27 12:40:57 PM PST 23
Finished Dec 27 01:06:07 PM PST 23
Peak memory 160928 kb
Host smart-eeda700d-52cc-4af7-aae4-b1fdfa7fa226
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4225891851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4225891851
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3142429549
Short name T148
Test name
Test status
Simulation time 336512850000 ps
CPU time 640.98 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 01:08:31 PM PST 23
Peak memory 160896 kb
Host smart-14260730-4a81-4447-8a74-489e4df89e83
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3142429549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3142429549
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1179742914
Short name T131
Test name
Test status
Simulation time 336533530000 ps
CPU time 690.73 seconds
Started Dec 27 12:40:54 PM PST 23
Finished Dec 27 01:10:09 PM PST 23
Peak memory 160924 kb
Host smart-ae5c2c91-8059-427d-b21c-667046a00c76
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1179742914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1179742914
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2823499146
Short name T139
Test name
Test status
Simulation time 336695090000 ps
CPU time 646.71 seconds
Started Dec 27 12:40:58 PM PST 23
Finished Dec 27 01:08:47 PM PST 23
Peak memory 161036 kb
Host smart-361b52e2-6b0d-43a5-a183-f18f8b3bad81
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2823499146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2823499146
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1311337199
Short name T124
Test name
Test status
Simulation time 336936030000 ps
CPU time 688.02 seconds
Started Dec 27 12:40:48 PM PST 23
Finished Dec 27 01:09:46 PM PST 23
Peak memory 160888 kb
Host smart-2ace027d-55b7-418c-ae30-2ab58e4ab92c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1311337199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1311337199
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.236470048
Short name T146
Test name
Test status
Simulation time 336567550000 ps
CPU time 633.37 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 01:07:11 PM PST 23
Peak memory 160944 kb
Host smart-6441bc1e-ee28-4db6-9cfb-ea555b5c97a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=236470048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.236470048
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.49803296
Short name T142
Test name
Test status
Simulation time 336431210000 ps
CPU time 626.59 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 01:07:35 PM PST 23
Peak memory 160896 kb
Host smart-68f9d50c-4a60-4b1b-b33f-87fb70d597e8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=49803296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.49803296
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1259881546
Short name T133
Test name
Test status
Simulation time 337140110000 ps
CPU time 515.85 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 01:03:51 PM PST 23
Peak memory 160856 kb
Host smart-808b8293-a6e6-467b-8613-0f8987e5b0ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1259881546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1259881546
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2378091977
Short name T160
Test name
Test status
Simulation time 1512610000 ps
CPU time 3.87 seconds
Started Dec 27 12:40:57 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 156236 kb
Host smart-06ed578b-59e1-4d95-abd1-35eb11d62801
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2378091977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2378091977
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.982139163
Short name T196
Test name
Test status
Simulation time 1459470000 ps
CPU time 2.97 seconds
Started Dec 27 12:40:58 PM PST 23
Finished Dec 27 12:42:09 PM PST 23
Peak memory 156152 kb
Host smart-23651019-679b-4737-ab48-027f9a63dad8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982139163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.982139163
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2720552400
Short name T158
Test name
Test status
Simulation time 1269170000 ps
CPU time 2.92 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 156216 kb
Host smart-8ecd32f3-4c5e-4992-ba2d-c267c5b85b4f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2720552400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2720552400
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2608387221
Short name T155
Test name
Test status
Simulation time 1347590000 ps
CPU time 2.69 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:12 PM PST 23
Peak memory 156140 kb
Host smart-b99e6d9a-7cae-49a1-892a-e513c23591a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2608387221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2608387221
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3760666848
Short name T187
Test name
Test status
Simulation time 1473890000 ps
CPU time 3.02 seconds
Started Dec 27 12:41:19 PM PST 23
Finished Dec 27 12:42:29 PM PST 23
Peak memory 156152 kb
Host smart-07fab69d-b047-4224-89b3-e226d3ee4f5b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3760666848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3760666848
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2409509788
Short name T163
Test name
Test status
Simulation time 1412330000 ps
CPU time 3.49 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 156076 kb
Host smart-c834bee2-adb5-4557-9294-c31351991109
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409509788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2409509788
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2716817386
Short name T192
Test name
Test status
Simulation time 1330730000 ps
CPU time 2.44 seconds
Started Dec 27 12:41:22 PM PST 23
Finished Dec 27 12:42:29 PM PST 23
Peak memory 156192 kb
Host smart-4cdc3eca-b5fe-429d-881e-e07145cb0127
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2716817386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2716817386
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1302989774
Short name T195
Test name
Test status
Simulation time 1433750000 ps
CPU time 3.12 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 12:42:22 PM PST 23
Peak memory 156176 kb
Host smart-62baa945-6fd4-430e-8345-6af7f017e8e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1302989774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1302989774
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4018901673
Short name T189
Test name
Test status
Simulation time 1456710000 ps
CPU time 3.11 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 156136 kb
Host smart-2a7557f3-50e9-4e82-9b61-5bdcea302817
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4018901673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.4018901673
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1862240843
Short name T199
Test name
Test status
Simulation time 1444830000 ps
CPU time 3.75 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 12:42:11 PM PST 23
Peak memory 156240 kb
Host smart-d493338c-4e10-44f9-ae2f-abba2dbd2dab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862240843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1862240843
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1429197677
Short name T168
Test name
Test status
Simulation time 1529950000 ps
CPU time 3.16 seconds
Started Dec 27 12:41:14 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 156152 kb
Host smart-123e4327-811c-4d45-9ecd-a2ee6cd16095
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1429197677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1429197677
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1803113682
Short name T153
Test name
Test status
Simulation time 1138050000 ps
CPU time 2.23 seconds
Started Dec 27 12:41:06 PM PST 23
Finished Dec 27 12:42:15 PM PST 23
Peak memory 156116 kb
Host smart-54862137-5b1e-4676-8bfd-9d049dc8a2fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1803113682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1803113682
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3201217730
Short name T166
Test name
Test status
Simulation time 1319030000 ps
CPU time 2.63 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 12:42:06 PM PST 23
Peak memory 156156 kb
Host smart-ea2a8afe-ee29-4f88-aaa3-d326d7e67d02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3201217730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3201217730
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.946766817
Short name T179
Test name
Test status
Simulation time 1556530000 ps
CPU time 2.96 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 156248 kb
Host smart-4634fdb7-eb0b-4312-a5f0-eab056a98080
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=946766817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.946766817
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3535531149
Short name T186
Test name
Test status
Simulation time 1450490000 ps
CPU time 3.52 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 156112 kb
Host smart-60895718-4dce-4a29-a65b-d4351e9e76f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3535531149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3535531149
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.507440227
Short name T200
Test name
Test status
Simulation time 1499090000 ps
CPU time 3.2 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:15 PM PST 23
Peak memory 156212 kb
Host smart-51cef465-c517-49f9-a9b9-2e3624d6559a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=507440227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.507440227
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2453564696
Short name T182
Test name
Test status
Simulation time 1401930000 ps
CPU time 2.79 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 156144 kb
Host smart-b2ba2d1c-4a1c-48d0-a148-6160e936db2e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453564696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2453564696
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3456485713
Short name T185
Test name
Test status
Simulation time 1633130000 ps
CPU time 3.2 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:20 PM PST 23
Peak memory 156160 kb
Host smart-59994087-34af-463e-9a8e-8d0d5957f5f3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3456485713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3456485713
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3631865587
Short name T167
Test name
Test status
Simulation time 1413410000 ps
CPU time 2.77 seconds
Started Dec 27 12:41:06 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 156152 kb
Host smart-35347c02-6ff2-4e51-9008-30cddd69c71f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631865587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3631865587
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2229752059
Short name T198
Test name
Test status
Simulation time 1332730000 ps
CPU time 2.78 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:12 PM PST 23
Peak memory 156220 kb
Host smart-aceee859-1aeb-4652-83c8-8930dc4915cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2229752059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2229752059
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1964238189
Short name T162
Test name
Test status
Simulation time 1279610000 ps
CPU time 2.56 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:05 PM PST 23
Peak memory 156232 kb
Host smart-f9d379b2-6a69-4317-91b8-7933e2a37fd0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964238189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1964238189
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4087782679
Short name T193
Test name
Test status
Simulation time 1494490000 ps
CPU time 3.06 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:42:03 PM PST 23
Peak memory 156188 kb
Host smart-2812bba4-fa04-4ba7-b99c-e900805b64e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087782679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.4087782679
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.517354002
Short name T183
Test name
Test status
Simulation time 1497330000 ps
CPU time 2.86 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 156136 kb
Host smart-01fa6c63-a20a-43ef-b041-526ea59c65b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=517354002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.517354002
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2271186790
Short name T188
Test name
Test status
Simulation time 1449450000 ps
CPU time 2.9 seconds
Started Dec 27 12:40:54 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 156088 kb
Host smart-82d32581-70a8-4d5b-aa8e-5b18b0691a84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271186790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2271186790
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.442820762
Short name T156
Test name
Test status
Simulation time 1456190000 ps
CPU time 2.78 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:42:20 PM PST 23
Peak memory 156224 kb
Host smart-df0a8b33-e0f4-45dc-928e-9408841fcf71
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=442820762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.442820762
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2071995199
Short name T169
Test name
Test status
Simulation time 1284570000 ps
CPU time 2.68 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 156152 kb
Host smart-acd5a36c-449d-4375-95f3-b3f19beef79e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071995199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2071995199
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1065158988
Short name T165
Test name
Test status
Simulation time 1617630000 ps
CPU time 3.03 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 156192 kb
Host smart-05c509f4-5f60-4451-9734-fb4f386deb66
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1065158988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1065158988
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1052388337
Short name T194
Test name
Test status
Simulation time 1397010000 ps
CPU time 2.68 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:11 PM PST 23
Peak memory 156176 kb
Host smart-a09d215f-e2e5-49b0-b0c9-9c1fba90d8bc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1052388337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1052388337
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.17020441
Short name T173
Test name
Test status
Simulation time 1543490000 ps
CPU time 4.39 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 156128 kb
Host smart-0c22d745-7ede-4fd9-a38a-4b97d1e1e532
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=17020441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.17020441
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2862300087
Short name T177
Test name
Test status
Simulation time 1248450000 ps
CPU time 2.57 seconds
Started Dec 27 12:41:26 PM PST 23
Finished Dec 27 12:42:34 PM PST 23
Peak memory 156124 kb
Host smart-a2fa9f05-90f4-445a-ada2-c9d57b3e047a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2862300087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2862300087
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2274972954
Short name T157
Test name
Test status
Simulation time 1454530000 ps
CPU time 2.98 seconds
Started Dec 27 12:41:21 PM PST 23
Finished Dec 27 12:42:29 PM PST 23
Peak memory 156248 kb
Host smart-5852c88a-fd32-4e1f-b7df-6e1852a15f4d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274972954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2274972954
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3872338118
Short name T171
Test name
Test status
Simulation time 1368390000 ps
CPU time 4.03 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 156172 kb
Host smart-57d42663-5295-4408-a388-2c5d23c3ee87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3872338118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3872338118
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1483624091
Short name T178
Test name
Test status
Simulation time 1463490000 ps
CPU time 2.89 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 156248 kb
Host smart-4a5e086c-d185-4e01-b023-b3bde5a5f6e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1483624091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1483624091
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.98048042
Short name T172
Test name
Test status
Simulation time 1439430000 ps
CPU time 2.69 seconds
Started Dec 27 12:40:48 PM PST 23
Finished Dec 27 12:42:02 PM PST 23
Peak memory 156144 kb
Host smart-6c375ff2-391c-4577-a9d6-cc0576a0de8e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98048042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.98048042
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.611190049
Short name T159
Test name
Test status
Simulation time 1500850000 ps
CPU time 3.07 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:42:23 PM PST 23
Peak memory 156152 kb
Host smart-d1ac573f-cadd-48ad-b4a4-6126b0f7c7f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611190049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.611190049
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1135406373
Short name T164
Test name
Test status
Simulation time 1273270000 ps
CPU time 2.69 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 156148 kb
Host smart-e43c7420-a415-453a-b819-fd29301fe9ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135406373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1135406373
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2283630931
Short name T161
Test name
Test status
Simulation time 1114610000 ps
CPU time 2.4 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:54 PM PST 23
Peak memory 156196 kb
Host smart-890d7b76-dbb1-409e-8711-1ae0883a5451
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2283630931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2283630931
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.701142087
Short name T151
Test name
Test status
Simulation time 1392670000 ps
CPU time 3.41 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:13 PM PST 23
Peak memory 156116 kb
Host smart-4a524047-af99-4975-964f-ae6b99309a3b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=701142087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.701142087
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1697927485
Short name T175
Test name
Test status
Simulation time 1424330000 ps
CPU time 4.24 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 156136 kb
Host smart-94f022b8-ee49-47e9-b476-430ddd476d9d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1697927485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1697927485
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1993010869
Short name T180
Test name
Test status
Simulation time 1482070000 ps
CPU time 3.05 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 156136 kb
Host smart-e79405a8-cb31-478d-906a-6b68d4cd6619
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1993010869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1993010869
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3622574199
Short name T184
Test name
Test status
Simulation time 1426730000 ps
CPU time 4.33 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 156124 kb
Host smart-a9c7b056-e05f-4a99-b172-7be460462f22
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622574199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3622574199
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.805323206
Short name T174
Test name
Test status
Simulation time 1504650000 ps
CPU time 2.82 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:19 PM PST 23
Peak memory 156160 kb
Host smart-b29fbc57-fa35-4586-b9d7-ebd1a29c1483
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=805323206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.805323206
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.575105719
Short name T181
Test name
Test status
Simulation time 1208990000 ps
CPU time 2.62 seconds
Started Dec 27 12:41:23 PM PST 23
Finished Dec 27 12:42:30 PM PST 23
Peak memory 156132 kb
Host smart-5c5d74dd-481b-4797-bb81-2c0bca452eea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=575105719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.575105719
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2997575069
Short name T152
Test name
Test status
Simulation time 1525770000 ps
CPU time 3.4 seconds
Started Dec 27 12:41:06 PM PST 23
Finished Dec 27 12:42:17 PM PST 23
Peak memory 156112 kb
Host smart-bc2b5179-6a24-49eb-a65f-ff413a1bd64c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997575069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2997575069
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1899319449
Short name T154
Test name
Test status
Simulation time 1498830000 ps
CPU time 3.27 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:42:12 PM PST 23
Peak memory 156124 kb
Host smart-fcf6ea45-bb5e-4971-b6df-5a1b7b421abf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1899319449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1899319449
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1736586476
Short name T191
Test name
Test status
Simulation time 1439290000 ps
CPU time 2.78 seconds
Started Dec 27 12:41:10 PM PST 23
Finished Dec 27 12:42:20 PM PST 23
Peak memory 156152 kb
Host smart-b2ca614c-53ed-4eae-9688-ca44b7210d3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1736586476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1736586476
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3639793342
Short name T176
Test name
Test status
Simulation time 1485850000 ps
CPU time 3.75 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 156172 kb
Host smart-d75dbd46-60cf-44be-884a-bbe907247543
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3639793342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3639793342
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4000474732
Short name T170
Test name
Test status
Simulation time 1514470000 ps
CPU time 2.88 seconds
Started Dec 27 12:40:58 PM PST 23
Finished Dec 27 12:42:09 PM PST 23
Peak memory 156152 kb
Host smart-ca39c23c-0674-4f53-b052-21d0c786a011
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4000474732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.4000474732
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.326923742
Short name T197
Test name
Test status
Simulation time 1558550000 ps
CPU time 3.18 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:12 PM PST 23
Peak memory 156152 kb
Host smart-959072d2-ce24-4c9b-9085-948c0ea06d73
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=326923742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.326923742
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3781108666
Short name T190
Test name
Test status
Simulation time 1482010000 ps
CPU time 2.77 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:54 PM PST 23
Peak memory 156220 kb
Host smart-694a0688-2cbf-4553-83a7-56557b1ffde8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3781108666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3781108666
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3730607183
Short name T57
Test name
Test status
Simulation time 1490350000 ps
CPU time 3.98 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:43 PM PST 23
Peak memory 155696 kb
Host smart-e002a53a-88de-43cb-9455-82cf1429419e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3730607183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3730607183
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4139092645
Short name T34
Test name
Test status
Simulation time 1181010000 ps
CPU time 2.32 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:35:52 PM PST 23
Peak memory 155708 kb
Host smart-91700025-59bb-43de-83e2-d880a2967e6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4139092645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4139092645
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3891704436
Short name T65
Test name
Test status
Simulation time 1460010000 ps
CPU time 2.76 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:35:59 PM PST 23
Peak memory 155736 kb
Host smart-9250b28b-a05c-47d5-9b62-3323dcc061b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3891704436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3891704436
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2018905052
Short name T43
Test name
Test status
Simulation time 1241890000 ps
CPU time 3.55 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:57 PM PST 23
Peak memory 155688 kb
Host smart-c2605f66-83bb-4123-8962-42b14ce1a7bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2018905052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2018905052
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3896894104
Short name T9
Test name
Test status
Simulation time 1265510000 ps
CPU time 2.67 seconds
Started Dec 27 12:36:22 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 155708 kb
Host smart-e21f78fd-9728-40b0-be11-be0d39eb6d24
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3896894104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3896894104
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3420882458
Short name T1
Test name
Test status
Simulation time 1496530000 ps
CPU time 3.13 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:36:01 PM PST 23
Peak memory 155688 kb
Host smart-d1b9f46c-28cc-48fc-9ec7-891d49fb6be2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3420882458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3420882458
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.281897300
Short name T64
Test name
Test status
Simulation time 1471410000 ps
CPU time 3.03 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:25 PM PST 23
Peak memory 155692 kb
Host smart-f0d46e7b-595e-4220-b5c7-28a42c9c95f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281897300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.281897300
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1328958663
Short name T37
Test name
Test status
Simulation time 1568970000 ps
CPU time 3.62 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 155704 kb
Host smart-ff801815-17db-41b8-9be4-69c671d81ac5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1328958663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1328958663
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.728266335
Short name T63
Test name
Test status
Simulation time 1453690000 ps
CPU time 2.86 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 155656 kb
Host smart-1c509ece-1ec2-49f9-b67b-b9d2318d3bf7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=728266335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.728266335
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.857533246
Short name T69
Test name
Test status
Simulation time 1239210000 ps
CPU time 2.4 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 155792 kb
Host smart-1f3ae3ef-ba15-475d-bdab-64cd1f052857
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=857533246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.857533246
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.471244533
Short name T10
Test name
Test status
Simulation time 1393710000 ps
CPU time 2.6 seconds
Started Dec 27 12:35:22 PM PST 23
Finished Dec 27 12:35:43 PM PST 23
Peak memory 155652 kb
Host smart-28252a10-57f6-4e77-8e14-c8aaa0102098
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=471244533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.471244533
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1737019054
Short name T11
Test name
Test status
Simulation time 1349150000 ps
CPU time 2.75 seconds
Started Dec 27 12:35:58 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 155792 kb
Host smart-9ea85cfd-b67f-4244-85eb-5bc43d981cbc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1737019054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1737019054
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2668942019
Short name T66
Test name
Test status
Simulation time 1499250000 ps
CPU time 2.94 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 155720 kb
Host smart-7ecee64e-54a0-40b8-a3e4-42ee5a6ead94
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2668942019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2668942019
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.790367537
Short name T67
Test name
Test status
Simulation time 1586730000 ps
CPU time 2.86 seconds
Started Dec 27 12:35:56 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 155792 kb
Host smart-be91c1a9-f2bc-4ddd-afc9-7b1c51022463
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=790367537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.790367537
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3723044294
Short name T52
Test name
Test status
Simulation time 1525490000 ps
CPU time 3.18 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 155712 kb
Host smart-adf4016c-7160-4163-b6a4-654e78e88696
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3723044294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3723044294
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1460374090
Short name T42
Test name
Test status
Simulation time 1397890000 ps
CPU time 2.79 seconds
Started Dec 27 12:36:23 PM PST 23
Finished Dec 27 12:36:50 PM PST 23
Peak memory 155756 kb
Host smart-b4fc59a9-3ae1-4c99-867f-3ffe05495ac2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460374090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1460374090
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2832958445
Short name T8
Test name
Test status
Simulation time 1537670000 ps
CPU time 2.92 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:36:00 PM PST 23
Peak memory 155804 kb
Host smart-8a14c1b0-1297-487c-9eb0-a94d679d98ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832958445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2832958445
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4012510092
Short name T33
Test name
Test status
Simulation time 1489290000 ps
CPU time 3.07 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:45 PM PST 23
Peak memory 155788 kb
Host smart-4545534b-8e41-4a8b-9f1a-ff3e6c5a816f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4012510092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4012510092
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2337768583
Short name T54
Test name
Test status
Simulation time 1358330000 ps
CPU time 2.97 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 155712 kb
Host smart-35596912-f104-4b59-8438-4c5f51aaab1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2337768583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2337768583
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3689598176
Short name T56
Test name
Test status
Simulation time 1405670000 ps
CPU time 2.81 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 155688 kb
Host smart-4e44630e-9bd7-499d-a40e-fe924ed24a97
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3689598176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3689598176
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3825906734
Short name T44
Test name
Test status
Simulation time 1493290000 ps
CPU time 3.12 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 155692 kb
Host smart-4867aac7-3bc2-4272-be51-af044f284d53
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3825906734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3825906734
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.835341687
Short name T38
Test name
Test status
Simulation time 1508970000 ps
CPU time 3.05 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:35:58 PM PST 23
Peak memory 155744 kb
Host smart-0fd75b61-2546-428c-9499-41ecf17e58f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=835341687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.835341687
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4252337190
Short name T62
Test name
Test status
Simulation time 1487530000 ps
CPU time 3.01 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:44 PM PST 23
Peak memory 155736 kb
Host smart-056c6c95-28b8-4b05-a124-d13ab448cdde
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252337190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.4252337190
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3398211559
Short name T70
Test name
Test status
Simulation time 1539130000 ps
CPU time 2.9 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:36:00 PM PST 23
Peak memory 155784 kb
Host smart-642ff807-7ad8-439c-8d24-bfc00724fe24
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3398211559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3398211559
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1539982838
Short name T51
Test name
Test status
Simulation time 1562850000 ps
CPU time 2.93 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 155616 kb
Host smart-24c25fa3-2499-46b4-aeff-683af1ec395d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1539982838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1539982838
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1047381046
Short name T49
Test name
Test status
Simulation time 1394990000 ps
CPU time 3.21 seconds
Started Dec 27 12:36:35 PM PST 23
Finished Dec 27 12:37:10 PM PST 23
Peak memory 155688 kb
Host smart-7d64badc-c6c9-4167-b78f-0ccecbac94e1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1047381046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1047381046
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.124994399
Short name T41
Test name
Test status
Simulation time 1537930000 ps
CPU time 4.99 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:52 PM PST 23
Peak memory 155704 kb
Host smart-7982f52d-fdec-4308-9ac9-d8945de095e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124994399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.124994399
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1601820374
Short name T12
Test name
Test status
Simulation time 1493230000 ps
CPU time 2.96 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:36 PM PST 23
Peak memory 155756 kb
Host smart-5709dc92-51c1-4d67-8809-3f3c251f7269
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1601820374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1601820374
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1477287405
Short name T47
Test name
Test status
Simulation time 1519770000 ps
CPU time 4.68 seconds
Started Dec 27 12:35:49 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 155716 kb
Host smart-e3a8a473-a627-4757-bb29-f8d7ff0ea1e5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1477287405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1477287405
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2753468841
Short name T40
Test name
Test status
Simulation time 1501290000 ps
CPU time 2.86 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:35:50 PM PST 23
Peak memory 155716 kb
Host smart-7863b8b2-8422-4eb0-bcca-923bf66aab92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2753468841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2753468841
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1495515027
Short name T55
Test name
Test status
Simulation time 1452130000 ps
CPU time 2.82 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:35:58 PM PST 23
Peak memory 155684 kb
Host smart-d96e6bc3-6d9c-4992-b4e3-981ff08f906f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495515027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1495515027
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.218813659
Short name T36
Test name
Test status
Simulation time 1420730000 ps
CPU time 2.91 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:56 PM PST 23
Peak memory 155788 kb
Host smart-5be735fb-5eb7-4805-b596-44f42a71cfd9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218813659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.218813659
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3184597925
Short name T39
Test name
Test status
Simulation time 1508290000 ps
CPU time 3.01 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 155712 kb
Host smart-7d65e641-71e7-411b-8e04-17c246e62be9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3184597925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3184597925
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2865144511
Short name T13
Test name
Test status
Simulation time 1261430000 ps
CPU time 2.71 seconds
Started Dec 27 12:35:45 PM PST 23
Finished Dec 27 12:36:10 PM PST 23
Peak memory 155692 kb
Host smart-380598b0-6778-491f-89aa-efaa966b6e42
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2865144511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2865144511
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.149621446
Short name T7
Test name
Test status
Simulation time 1598390000 ps
CPU time 2.86 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:35:46 PM PST 23
Peak memory 155704 kb
Host smart-1d1d4fe7-b51c-49f6-92b9-c5de1183019a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=149621446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.149621446
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1094743176
Short name T35
Test name
Test status
Simulation time 1258750000 ps
CPU time 2.77 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:24 PM PST 23
Peak memory 155680 kb
Host smart-69a4b3e0-7a8c-44d4-b837-403444a1f46c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1094743176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1094743176
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3775150656
Short name T32
Test name
Test status
Simulation time 1550350000 ps
CPU time 4.37 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 155716 kb
Host smart-ecef5f91-a5c8-494f-a11d-d115b0342bb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3775150656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3775150656
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.7010029
Short name T68
Test name
Test status
Simulation time 1391310000 ps
CPU time 2.82 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:36:28 PM PST 23
Peak memory 155780 kb
Host smart-9c3849aa-50cd-4b1e-af56-8ff87fb56821
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=7010029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.7010029
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3121416893
Short name T48
Test name
Test status
Simulation time 1254110000 ps
CPU time 2.49 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 155736 kb
Host smart-ac06c8a3-b933-4d07-9586-bbd3dcd16f63
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3121416893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3121416893
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1860669365
Short name T60
Test name
Test status
Simulation time 1418570000 ps
CPU time 3.21 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:56 PM PST 23
Peak memory 155692 kb
Host smart-be252473-af0c-4217-8cae-d8f5562ebeb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1860669365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1860669365
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2988339571
Short name T50
Test name
Test status
Simulation time 1441330000 ps
CPU time 3.05 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 155784 kb
Host smart-ac0b3369-91c8-4778-a3f4-70aaa7424b19
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2988339571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2988339571
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2673341557
Short name T59
Test name
Test status
Simulation time 1531710000 ps
CPU time 3.17 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:48 PM PST 23
Peak memory 155636 kb
Host smart-f1b0fa65-9747-4d3b-9d00-45a86d09b1d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2673341557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2673341557
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.187680464
Short name T45
Test name
Test status
Simulation time 1468190000 ps
CPU time 2.91 seconds
Started Dec 27 12:36:01 PM PST 23
Finished Dec 27 12:36:25 PM PST 23
Peak memory 155636 kb
Host smart-b3e30734-5fc0-4feb-a240-da61f886ef8c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187680464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.187680464
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4120002347
Short name T58
Test name
Test status
Simulation time 1164050000 ps
CPU time 2.35 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:35:44 PM PST 23
Peak memory 155616 kb
Host smart-2fe3b70c-eae5-4bd9-a069-1224580ce4e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4120002347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4120002347
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3482720563
Short name T61
Test name
Test status
Simulation time 1297030000 ps
CPU time 2.59 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:47 PM PST 23
Peak memory 155672 kb
Host smart-fbb081d4-c454-4058-9db0-0f7a2d21bdf2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482720563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3482720563
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1828696097
Short name T3
Test name
Test status
Simulation time 1525190000 ps
CPU time 4.19 seconds
Started Dec 27 12:36:16 PM PST 23
Finished Dec 27 12:36:46 PM PST 23
Peak memory 155696 kb
Host smart-bc7563ff-f385-4ffa-9162-6dbdf0dfbc3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828696097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1828696097
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1499257976
Short name T31
Test name
Test status
Simulation time 1197150000 ps
CPU time 2.7 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:35:51 PM PST 23
Peak memory 155656 kb
Host smart-4dee439d-0d5e-4af8-88b8-f1ad84a7b865
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1499257976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1499257976
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2926665353
Short name T53
Test name
Test status
Simulation time 1328810000 ps
CPU time 2.6 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:34 PM PST 23
Peak memory 155712 kb
Host smart-acbd1ba5-6e49-403a-aa66-0ae740ca3b9c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2926665353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2926665353
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2631825149
Short name T46
Test name
Test status
Simulation time 1506510000 ps
CPU time 3.04 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 155712 kb
Host smart-b5918480-c831-4005-b62d-f1e346ca7ab5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631825149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2631825149
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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