Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4067951602
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2095758300
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.449952162

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1739289858
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4028286058
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1156365856
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1518254022
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4267144416
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1450586044
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3739965709
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3424426455
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2464795124
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1003548023
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2454518337
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3448767298
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.660028877
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1795613444
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3507062977
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4273296060
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3505774497
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.520018411
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1778668936
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1860981606
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3226176519
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3722886997
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2459853562
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3944522969
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.538119874
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4073062445
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3901972684
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1749333871
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3922428002
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3325696003
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1470853571
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4072219628
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2561114315
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4211126655
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3773102828
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1012529238
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2608167532
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3164408490
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1482007879
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1409262500
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3386337422
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2177163044
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1539538985
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2621529888
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1899076734
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4199319615
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2840713202
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.868724896
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1517987147
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2050591062
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3683966059
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4271319109
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1231755960
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1154429473
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3132765474
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.689836902
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3046985504
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4158845195
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1437300337
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.314591372
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4069949093
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1927862835
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2915957214
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4143620654
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2294707682
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1967616999
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2242023338
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2243637596
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2180474413
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2632440438
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1473875699
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4087009103
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1616569136
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3345663604
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2953847354
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3310055784
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3148903069
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.159231858
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2850080437
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4042625527
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1306242648
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3574354803
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1142822466
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2324538497
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3647393420
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3259775117
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3948237076
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.347842077
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.198512635
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2480558512
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1917330400
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2279651985
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2677951793
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1117325538
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1124309629
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1503958076
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1677247852
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2754757908
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.734567407
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.552927221
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2201750722
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1317774596
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.245417579
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.298944584
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3642940015
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3106371017
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.375380294
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.885025091
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3615263662
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2872807530
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3178371372
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1305151653
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2367005195
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.580383639
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1611101160
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1394372887
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.44917006
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2999947174
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2504398009
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3523998534
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1936797557
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2284677423
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2936004088
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.629417152
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1925566143
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2816675392
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1820272591
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3054461045
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.421923360
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1816392491
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2551918748
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4168263914
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3018524999
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4037690300
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2161595476
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.458367515
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3029093132
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2172425662
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2647296894
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3794164747
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2653775755
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1811414793
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3984815304
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.549889293
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.837118045
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2326929235
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2536151530
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3569348226
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.501645820
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1746430015
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.889618237
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1477609528
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2077642273
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1281390892
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2026087412
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3003024713
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1688158631
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1515908954
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1444310154
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1041969601
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.338985316
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2810822038
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1415888236
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2649656060
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2096222879
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3095395507
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1047743094
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2915443056
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3482879415
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.514366254
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.62738256
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2507606572
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1811594915
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.926580420
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3726941205
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2811658082
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.180020199
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2692835043
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1607539895
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1036928572
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1654418483
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1125516388
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1614157267
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2453962125
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4276689196
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4068378686
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4174446635
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1481133663
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2210013084
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4008474968
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2577077146
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2786809680
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.448712839
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3863132634
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.877217187
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1494856598
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3456025749



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2811658082 Dec 31 12:46:33 PM PST 23 Dec 31 12:46:43 PM PST 23 1425570000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.62738256 Dec 31 12:46:24 PM PST 23 Dec 31 12:46:34 PM PST 23 1509550000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4067951602 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:39 PM PST 23 1525710000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1811594915 Dec 31 12:46:29 PM PST 23 Dec 31 12:46:38 PM PST 23 1495630000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2810822038 Dec 31 12:46:27 PM PST 23 Dec 31 12:46:36 PM PST 23 1467910000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2077642273 Dec 31 12:46:25 PM PST 23 Dec 31 12:46:33 PM PST 23 1542250000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2026087412 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:43 PM PST 23 1370610000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.877217187 Dec 31 12:46:35 PM PST 23 Dec 31 12:46:44 PM PST 23 1434390000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2915443056 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:41 PM PST 23 1431350000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3095395507 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:34 PM PST 23 1296670000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1481133663 Dec 31 12:46:16 PM PST 23 Dec 31 12:46:22 PM PST 23 1098950000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3003024713 Dec 31 12:46:33 PM PST 23 Dec 31 12:46:43 PM PST 23 1362770000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.926580420 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:46 PM PST 23 1500110000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1477609528 Dec 31 12:46:46 PM PST 23 Dec 31 12:46:54 PM PST 23 1384450000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2786809680 Dec 31 12:46:04 PM PST 23 Dec 31 12:46:13 PM PST 23 1526410000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1494856598 Dec 31 12:46:47 PM PST 23 Dec 31 12:46:55 PM PST 23 1237970000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.338985316 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:37 PM PST 23 1601410000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2096222879 Dec 31 12:46:44 PM PST 23 Dec 31 12:46:54 PM PST 23 1324890000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1688158631 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:39 PM PST 23 1403550000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1444310154 Dec 31 12:46:31 PM PST 23 Dec 31 12:46:45 PM PST 23 1537890000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1614157267 Dec 31 12:46:16 PM PST 23 Dec 31 12:46:24 PM PST 23 1340610000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2210013084 Dec 31 12:46:18 PM PST 23 Dec 31 12:46:29 PM PST 23 1555570000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3726941205 Dec 31 12:46:41 PM PST 23 Dec 31 12:46:52 PM PST 23 1527570000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1607539895 Dec 31 12:46:20 PM PST 23 Dec 31 12:46:30 PM PST 23 1530970000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.514366254 Dec 31 12:46:33 PM PST 23 Dec 31 12:46:43 PM PST 23 1509050000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1281390892 Dec 31 12:46:22 PM PST 23 Dec 31 12:46:30 PM PST 23 1440670000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1654418483 Dec 31 12:46:24 PM PST 23 Dec 31 12:46:32 PM PST 23 1371670000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3482879415 Dec 31 12:46:35 PM PST 23 Dec 31 12:46:47 PM PST 23 1649350000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4008474968 Dec 31 12:46:20 PM PST 23 Dec 31 12:46:30 PM PST 23 1440890000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4068378686 Dec 31 12:46:25 PM PST 23 Dec 31 12:46:37 PM PST 23 1599890000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.889618237 Dec 31 12:46:03 PM PST 23 Dec 31 12:46:11 PM PST 23 1349990000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4174446635 Dec 31 12:46:17 PM PST 23 Dec 31 12:46:25 PM PST 23 1545010000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2692835043 Dec 31 12:46:18 PM PST 23 Dec 31 12:46:25 PM PST 23 1259630000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.501645820 Dec 31 12:46:15 PM PST 23 Dec 31 12:46:22 PM PST 23 1479170000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2649656060 Dec 31 12:46:55 PM PST 23 Dec 31 12:47:04 PM PST 23 1363550000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4276689196 Dec 31 12:46:24 PM PST 23 Dec 31 12:46:32 PM PST 23 1326330000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1415888236 Dec 31 12:46:42 PM PST 23 Dec 31 12:46:52 PM PST 23 1407890000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2507606572 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:40 PM PST 23 1531010000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1047743094 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:39 PM PST 23 1494450000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2453962125 Dec 31 12:46:29 PM PST 23 Dec 31 12:46:37 PM PST 23 1138270000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1515908954 Dec 31 12:46:15 PM PST 23 Dec 31 12:46:24 PM PST 23 1401030000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1746430015 Dec 31 12:46:42 PM PST 23 Dec 31 12:46:51 PM PST 23 1473650000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.180020199 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:35 PM PST 23 1572590000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1036928572 Dec 31 12:46:39 PM PST 23 Dec 31 12:46:48 PM PST 23 1449290000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3863132634 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:37 PM PST 23 1518030000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.448712839 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:38 PM PST 23 1431950000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3456025749 Dec 31 12:46:13 PM PST 23 Dec 31 12:46:22 PM PST 23 1584330000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2577077146 Dec 31 12:46:31 PM PST 23 Dec 31 12:46:45 PM PST 23 1512890000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1125516388 Dec 31 12:46:12 PM PST 23 Dec 31 12:46:22 PM PST 23 1534290000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1041969601 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:37 PM PST 23 1196070000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2095758300 Dec 31 12:46:39 PM PST 23 Dec 31 01:12:47 PM PST 23 336809910000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3944522969 Dec 31 12:46:35 PM PST 23 Dec 31 01:11:52 PM PST 23 336546230000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1539538985 Dec 31 12:46:31 PM PST 23 Dec 31 01:15:52 PM PST 23 337063750000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2177163044 Dec 31 12:45:58 PM PST 23 Dec 31 01:13:14 PM PST 23 336882990000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2840713202 Dec 31 12:46:18 PM PST 23 Dec 31 01:10:44 PM PST 23 337049070000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1450586044 Dec 31 12:46:26 PM PST 23 Dec 31 01:12:25 PM PST 23 336625910000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3739965709 Dec 31 12:46:12 PM PST 23 Dec 31 01:15:49 PM PST 23 336882370000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2621529888 Dec 31 12:46:31 PM PST 23 Dec 31 01:13:01 PM PST 23 336617530000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2464795124 Dec 31 12:46:25 PM PST 23 Dec 31 01:14:02 PM PST 23 336678430000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2454518337 Dec 31 12:46:33 PM PST 23 Dec 31 01:10:09 PM PST 23 336402050000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2459853562 Dec 31 12:46:28 PM PST 23 Dec 31 01:15:55 PM PST 23 336659130000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1518254022 Dec 31 12:46:42 PM PST 23 Dec 31 01:12:45 PM PST 23 337013730000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4073062445 Dec 31 12:46:19 PM PST 23 Dec 31 01:14:44 PM PST 23 336814250000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1749333871 Dec 31 12:46:26 PM PST 23 Dec 31 01:13:28 PM PST 23 336749590000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3507062977 Dec 31 12:46:22 PM PST 23 Dec 31 01:12:08 PM PST 23 336807730000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1470853571 Dec 31 12:46:30 PM PST 23 Dec 31 01:17:47 PM PST 23 336701790000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3226176519 Dec 31 12:46:38 PM PST 23 Dec 31 01:09:34 PM PST 23 336954810000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4199319615 Dec 31 12:46:24 PM PST 23 Dec 31 01:14:44 PM PST 23 336453130000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.868724896 Dec 31 12:46:16 PM PST 23 Dec 31 01:10:20 PM PST 23 337025850000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3325696003 Dec 31 12:46:26 PM PST 23 Dec 31 01:12:15 PM PST 23 336913990000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3505774497 Dec 31 12:45:56 PM PST 23 Dec 31 01:15:29 PM PST 23 336873050000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1899076734 Dec 31 12:46:39 PM PST 23 Dec 31 01:12:56 PM PST 23 336432950000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1012529238 Dec 31 12:46:08 PM PST 23 Dec 31 01:12:38 PM PST 23 336371930000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1795613444 Dec 31 12:46:18 PM PST 23 Dec 31 01:11:33 PM PST 23 336875190000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2561114315 Dec 31 12:46:17 PM PST 23 Dec 31 01:10:44 PM PST 23 336688290000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4267144416 Dec 31 12:46:26 PM PST 23 Dec 31 01:11:27 PM PST 23 336574350000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3922428002 Dec 31 12:46:27 PM PST 23 Dec 31 01:13:03 PM PST 23 336597910000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1739289858 Dec 31 12:46:46 PM PST 23 Dec 31 01:12:53 PM PST 23 336421670000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1517987147 Dec 31 12:46:21 PM PST 23 Dec 31 01:11:27 PM PST 23 337007370000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4273296060 Dec 31 12:46:42 PM PST 23 Dec 31 01:12:11 PM PST 23 336450250000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1778668936 Dec 31 12:46:22 PM PST 23 Dec 31 01:11:41 PM PST 23 336969330000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4072219628 Dec 31 12:46:44 PM PST 23 Dec 31 01:16:50 PM PST 23 336507350000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.660028877 Dec 31 12:46:36 PM PST 23 Dec 31 01:12:53 PM PST 23 336630110000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.520018411 Dec 31 12:46:00 PM PST 23 Dec 31 01:10:09 PM PST 23 336547970000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3424426455 Dec 31 12:46:01 PM PST 23 Dec 31 01:13:49 PM PST 23 337017870000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3901972684 Dec 31 12:46:10 PM PST 23 Dec 31 01:13:49 PM PST 23 336364950000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1482007879 Dec 31 12:46:33 PM PST 23 Dec 31 01:13:52 PM PST 23 336628870000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1409262500 Dec 31 12:46:35 PM PST 23 Dec 31 01:17:35 PM PST 23 336472790000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1156365856 Dec 31 12:46:19 PM PST 23 Dec 31 01:15:49 PM PST 23 336625550000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3448767298 Dec 31 12:46:53 PM PST 23 Dec 31 01:15:03 PM PST 23 336928250000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3164408490 Dec 31 12:46:08 PM PST 23 Dec 31 01:09:10 PM PST 23 336714110000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1003548023 Dec 31 12:46:20 PM PST 23 Dec 31 01:13:36 PM PST 23 336724590000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2608167532 Dec 31 12:46:56 PM PST 23 Dec 31 01:12:00 PM PST 23 336813510000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3773102828 Dec 31 12:46:46 PM PST 23 Dec 31 01:12:11 PM PST 23 336565830000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4028286058 Dec 31 12:46:38 PM PST 23 Dec 31 01:12:46 PM PST 23 336584190000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1860981606 Dec 31 12:46:34 PM PST 23 Dec 31 01:11:26 PM PST 23 336972950000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4211126655 Dec 31 12:46:23 PM PST 23 Dec 31 01:13:24 PM PST 23 336292010000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3386337422 Dec 31 12:46:40 PM PST 23 Dec 31 01:14:08 PM PST 23 336478010000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3722886997 Dec 31 12:46:20 PM PST 23 Dec 31 01:10:46 PM PST 23 336601090000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.538119874 Dec 31 12:46:14 PM PST 23 Dec 31 01:13:27 PM PST 23 336830590000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.458367515 Dec 31 12:46:10 PM PST 23 Dec 31 12:46:19 PM PST 23 1495950000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2504398009 Dec 31 12:46:38 PM PST 23 Dec 31 12:46:47 PM PST 23 1534290000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1611101160 Dec 31 12:46:21 PM PST 23 Dec 31 12:46:31 PM PST 23 1597070000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1811414793 Dec 31 12:46:23 PM PST 23 Dec 31 12:46:33 PM PST 23 1520310000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2936004088 Dec 31 12:46:35 PM PST 23 Dec 31 12:46:46 PM PST 23 1437910000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3054461045 Dec 31 12:46:22 PM PST 23 Dec 31 12:46:30 PM PST 23 1331490000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2201750722 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:39 PM PST 23 1386910000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1394372887 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:42 PM PST 23 1000690000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4037690300 Dec 31 12:46:34 PM PST 23 Dec 31 12:46:46 PM PST 23 1486910000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3106371017 Dec 31 12:46:21 PM PST 23 Dec 31 12:46:32 PM PST 23 1480070000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.837118045 Dec 31 12:46:38 PM PST 23 Dec 31 12:46:49 PM PST 23 1472810000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.44917006 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:34 PM PST 23 1445110000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3615263662 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:34 PM PST 23 1575590000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2653775755 Dec 31 12:46:29 PM PST 23 Dec 31 12:46:39 PM PST 23 1503250000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3029093132 Dec 31 12:46:24 PM PST 23 Dec 31 12:46:32 PM PST 23 1260230000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.629417152 Dec 31 12:46:11 PM PST 23 Dec 31 12:46:23 PM PST 23 1463350000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.375380294 Dec 31 12:46:23 PM PST 23 Dec 31 12:46:36 PM PST 23 1367950000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2284677423 Dec 31 12:46:39 PM PST 23 Dec 31 12:46:48 PM PST 23 1563130000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.552927221 Dec 31 12:46:44 PM PST 23 Dec 31 12:46:53 PM PST 23 1413550000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2872807530 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:38 PM PST 23 1528450000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.549889293 Dec 31 12:46:20 PM PST 23 Dec 31 12:46:29 PM PST 23 1560890000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.734567407 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:46 PM PST 23 1417610000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2172425662 Dec 31 12:46:25 PM PST 23 Dec 31 12:46:31 PM PST 23 1117270000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3642940015 Dec 31 12:46:27 PM PST 23 Dec 31 12:46:36 PM PST 23 1290670000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.885025091 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:47 PM PST 23 1556010000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3794164747 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:46 PM PST 23 1494530000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2161595476 Dec 31 12:46:19 PM PST 23 Dec 31 12:46:29 PM PST 23 1564410000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2551918748 Dec 31 12:46:10 PM PST 23 Dec 31 12:46:18 PM PST 23 1167190000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3018524999 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:42 PM PST 23 1403730000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2367005195 Dec 31 12:46:47 PM PST 23 Dec 31 12:46:55 PM PST 23 1355350000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2326929235 Dec 31 12:46:39 PM PST 23 Dec 31 12:46:52 PM PST 23 1404050000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2999947174 Dec 31 12:46:22 PM PST 23 Dec 31 12:46:30 PM PST 23 1184970000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2647296894 Dec 31 12:46:33 PM PST 23 Dec 31 12:46:43 PM PST 23 1552530000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3178371372 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:38 PM PST 23 1206490000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.298944584 Dec 31 12:46:33 PM PST 23 Dec 31 12:46:42 PM PST 23 1325530000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.245417579 Dec 31 12:46:21 PM PST 23 Dec 31 12:46:32 PM PST 23 1413490000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.421923360 Dec 31 12:46:16 PM PST 23 Dec 31 12:46:23 PM PST 23 1345190000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1816392491 Dec 31 12:46:42 PM PST 23 Dec 31 12:46:53 PM PST 23 1583430000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1925566143 Dec 31 12:46:47 PM PST 23 Dec 31 12:46:56 PM PST 23 1569150000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1936797557 Dec 31 12:46:58 PM PST 23 Dec 31 12:47:06 PM PST 23 1438410000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1317774596 Dec 31 12:46:48 PM PST 23 Dec 31 12:47:02 PM PST 23 1442550000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1305151653 Dec 31 12:46:49 PM PST 23 Dec 31 12:46:57 PM PST 23 1339950000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3523998534 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:45 PM PST 23 1441610000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3569348226 Dec 31 12:46:13 PM PST 23 Dec 31 12:46:22 PM PST 23 1519870000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.580383639 Dec 31 12:47:09 PM PST 23 Dec 31 12:47:19 PM PST 23 1421070000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1820272591 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:48 PM PST 23 1253490000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3984815304 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:45 PM PST 23 1383790000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2816675392 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:46 PM PST 23 1485670000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2536151530 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:47 PM PST 23 1424870000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4168263914 Dec 31 12:46:15 PM PST 23 Dec 31 12:46:24 PM PST 23 1588170000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3574354803 Dec 31 12:23:26 PM PST 23 Dec 31 12:57:31 PM PST 23 336629790000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.689836902 Dec 31 12:27:05 PM PST 23 Dec 31 01:01:10 PM PST 23 336508990000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1117325538 Dec 31 12:28:07 PM PST 23 Dec 31 12:50:07 PM PST 23 336904870000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2294707682 Dec 31 12:23:19 PM PST 23 Dec 31 12:54:20 PM PST 23 336897530000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1967616999 Dec 31 12:17:59 PM PST 23 Dec 31 12:44:24 PM PST 23 336862530000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1473875699 Dec 31 12:27:35 PM PST 23 Dec 31 01:01:54 PM PST 23 336583210000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1154429473 Dec 31 12:23:18 PM PST 23 Dec 31 12:54:30 PM PST 23 336567470000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2677951793 Dec 31 12:24:23 PM PST 23 Dec 31 12:57:40 PM PST 23 336851530000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2850080437 Dec 31 12:23:25 PM PST 23 Dec 31 12:56:55 PM PST 23 336887390000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.449952162 Dec 31 12:27:33 PM PST 23 Dec 31 01:01:26 PM PST 23 336449710000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4271319109 Dec 31 12:21:31 PM PST 23 Dec 31 12:58:24 PM PST 23 336984170000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4158845195 Dec 31 12:26:27 PM PST 23 Dec 31 12:52:03 PM PST 23 336356930000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3310055784 Dec 31 12:23:26 PM PST 23 Dec 31 12:58:17 PM PST 23 336980250000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4143620654 Dec 31 12:23:03 PM PST 23 Dec 31 12:49:36 PM PST 23 336479950000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3132765474 Dec 31 12:23:03 PM PST 23 Dec 31 12:49:49 PM PST 23 336913930000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2480558512 Dec 31 12:17:59 PM PST 23 Dec 31 12:44:23 PM PST 23 336567410000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3259775117 Dec 31 12:22:56 PM PST 23 Dec 31 12:57:11 PM PST 23 336801850000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.159231858 Dec 31 12:22:56 PM PST 23 Dec 31 12:56:58 PM PST 23 336863270000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3683966059 Dec 31 12:20:16 PM PST 23 Dec 31 12:46:41 PM PST 23 336980610000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2754757908 Dec 31 12:27:06 PM PST 23 Dec 31 01:00:58 PM PST 23 336733730000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.314591372 Dec 31 12:23:18 PM PST 23 Dec 31 12:55:44 PM PST 23 336459030000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3046985504 Dec 31 12:24:23 PM PST 23 Dec 31 12:57:59 PM PST 23 336512510000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2242023338 Dec 31 12:23:19 PM PST 23 Dec 31 12:54:58 PM PST 23 337078790000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.198512635 Dec 31 12:23:57 PM PST 23 Dec 31 12:54:21 PM PST 23 336990030000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1677247852 Dec 31 12:24:23 PM PST 23 Dec 31 12:58:12 PM PST 23 336947590000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2180474413 Dec 31 12:26:00 PM PST 23 Dec 31 12:50:20 PM PST 23 336827470000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1616569136 Dec 31 12:23:25 PM PST 23 Dec 31 12:58:20 PM PST 23 336823750000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3948237076 Dec 31 12:25:49 PM PST 23 Dec 31 12:48:28 PM PST 23 336996890000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4069949093 Dec 31 12:21:31 PM PST 23 Dec 31 12:58:18 PM PST 23 336582710000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2243637596 Dec 31 12:27:18 PM PST 23 Dec 31 12:51:44 PM PST 23 336505110000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4087009103 Dec 31 12:23:19 PM PST 23 Dec 31 12:55:26 PM PST 23 336968550000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2279651985 Dec 31 12:23:11 PM PST 23 Dec 31 12:57:37 PM PST 23 336579350000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1503958076 Dec 31 12:18:23 PM PST 23 Dec 31 12:43:01 PM PST 23 336987130000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.347842077 Dec 31 12:23:26 PM PST 23 Dec 31 12:58:38 PM PST 23 337087490000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2632440438 Dec 31 12:23:57 PM PST 23 Dec 31 12:57:45 PM PST 23 336964890000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2324538497 Dec 31 12:24:23 PM PST 23 Dec 31 12:48:05 PM PST 23 336616630000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1437300337 Dec 31 12:26:24 PM PST 23 Dec 31 12:50:26 PM PST 23 336419710000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1124309629 Dec 31 12:26:13 PM PST 23 Dec 31 12:59:54 PM PST 23 336406610000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1306242648 Dec 31 12:24:23 PM PST 23 Dec 31 12:48:03 PM PST 23 336521230000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3345663604 Dec 31 12:24:23 PM PST 23 Dec 31 12:58:16 PM PST 23 336703630000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1927862835 Dec 31 12:20:10 PM PST 23 Dec 31 12:46:45 PM PST 23 336315490000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1231755960 Dec 31 12:17:46 PM PST 23 Dec 31 12:55:33 PM PST 23 336608310000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2915957214 Dec 31 12:17:46 PM PST 23 Dec 31 12:56:08 PM PST 23 336432850000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1142822466 Dec 31 12:26:31 PM PST 23 Dec 31 12:52:30 PM PST 23 336613410000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2953847354 Dec 31 12:22:56 PM PST 23 Dec 31 12:57:13 PM PST 23 336773590000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3647393420 Dec 31 12:23:57 PM PST 23 Dec 31 12:54:40 PM PST 23 336940970000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3148903069 Dec 31 12:24:19 PM PST 23 Dec 31 12:55:09 PM PST 23 336948070000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2050591062 Dec 31 12:23:18 PM PST 23 Dec 31 12:55:34 PM PST 23 336810610000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4042625527 Dec 31 12:22:56 PM PST 23 Dec 31 12:57:18 PM PST 23 336479470000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1917330400 Dec 31 12:23:57 PM PST 23 Dec 31 12:54:40 PM PST 23 336596350000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4067951602
Short name T3
Test name
Test status
Simulation time 1525710000 ps
CPU time 3.8 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 155748 kb
Host smart-427ab500-ee93-4297-bc85-9496036a1bfc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4067951602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4067951602
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2095758300
Short name T4
Test name
Test status
Simulation time 336809910000 ps
CPU time 628.96 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 01:12:47 PM PST 23
Peak memory 160552 kb
Host smart-18267a04-5c37-41f9-9df0-5404cabd2cbf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2095758300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2095758300
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.449952162
Short name T30
Test name
Test status
Simulation time 336449710000 ps
CPU time 829.2 seconds
Started Dec 31 12:27:33 PM PST 23
Finished Dec 31 01:01:26 PM PST 23
Peak memory 160808 kb
Host smart-d98c5fe5-aeb3-4c4d-814a-98acf1293a4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=449952162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.449952162
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1739289858
Short name T88
Test name
Test status
Simulation time 336421670000 ps
CPU time 623.62 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 01:12:53 PM PST 23
Peak memory 160428 kb
Host smart-7e9c21e9-100f-4d3d-92e4-2d7663fb8087
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1739289858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1739289858
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4028286058
Short name T105
Test name
Test status
Simulation time 336584190000 ps
CPU time 629.42 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 01:12:46 PM PST 23
Peak memory 160432 kb
Host smart-96411ddf-9945-4ff7-b72a-5f726dc7a6cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4028286058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4028286058
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1156365856
Short name T99
Test name
Test status
Simulation time 336625550000 ps
CPU time 735.84 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 01:15:49 PM PST 23
Peak memory 160444 kb
Host smart-a293fce2-0434-406e-8e98-69ca6699e084
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1156365856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1156365856
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1518254022
Short name T72
Test name
Test status
Simulation time 337013730000 ps
CPU time 624.08 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 01:12:45 PM PST 23
Peak memory 160520 kb
Host smart-95749a31-c45d-4501-8fbe-284e94488a31
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1518254022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1518254022
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4267144416
Short name T86
Test name
Test status
Simulation time 336574350000 ps
CPU time 592.71 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 01:11:27 PM PST 23
Peak memory 160576 kb
Host smart-beface99-586c-4d00-a467-24d80a989dd2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4267144416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4267144416
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1450586044
Short name T16
Test name
Test status
Simulation time 336625910000 ps
CPU time 630.06 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 160548 kb
Host smart-732ff4be-6214-450a-aa7b-94cff9eae5b9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1450586044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1450586044
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3739965709
Short name T17
Test name
Test status
Simulation time 336882370000 ps
CPU time 740.49 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 01:15:49 PM PST 23
Peak memory 160444 kb
Host smart-f68ceda6-76ad-4e70-b53b-055ea8dd008b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3739965709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3739965709
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3424426455
Short name T95
Test name
Test status
Simulation time 337017870000 ps
CPU time 676.08 seconds
Started Dec 31 12:46:01 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 160592 kb
Host smart-e5183a8f-7af6-43a6-8ab4-b3165363bf09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3424426455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3424426455
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2464795124
Short name T19
Test name
Test status
Simulation time 336678430000 ps
CPU time 684.57 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 01:14:02 PM PST 23
Peak memory 160560 kb
Host smart-4c8e7fdb-14c5-4326-a263-444e83d7689e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2464795124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2464795124
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1003548023
Short name T102
Test name
Test status
Simulation time 336724590000 ps
CPU time 660.06 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 160572 kb
Host smart-5b0d5799-41cd-4e2e-bda2-ed8ae97823e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1003548023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1003548023
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2454518337
Short name T20
Test name
Test status
Simulation time 336402050000 ps
CPU time 564.7 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 01:10:09 PM PST 23
Peak memory 160560 kb
Host smart-60d6c5e0-724f-4f52-a5d7-fc68923782d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2454518337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2454518337
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3448767298
Short name T100
Test name
Test status
Simulation time 336928250000 ps
CPU time 690.15 seconds
Started Dec 31 12:46:53 PM PST 23
Finished Dec 31 01:15:03 PM PST 23
Peak memory 160532 kb
Host smart-41499e76-d18d-435d-9936-e2fa44d9e53f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3448767298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3448767298
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.660028877
Short name T93
Test name
Test status
Simulation time 336630110000 ps
CPU time 631.64 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 01:12:53 PM PST 23
Peak memory 160488 kb
Host smart-cfe78076-8265-44cc-b340-2758b8b4f1d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=660028877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.660028877
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1795613444
Short name T84
Test name
Test status
Simulation time 336875190000 ps
CPU time 610.78 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 01:11:33 PM PST 23
Peak memory 160524 kb
Host smart-764fe798-6d7b-43d6-bafb-798a9e29d356
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1795613444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1795613444
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3507062977
Short name T75
Test name
Test status
Simulation time 336807730000 ps
CPU time 619.57 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 160520 kb
Host smart-c68b80e4-b1a3-4442-85a0-76c7c14ce445
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3507062977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3507062977
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.4273296060
Short name T90
Test name
Test status
Simulation time 336450250000 ps
CPU time 612.4 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 01:12:11 PM PST 23
Peak memory 160616 kb
Host smart-06b3d26c-c740-43b6-b0f3-a3633414f210
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4273296060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.4273296060
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3505774497
Short name T81
Test name
Test status
Simulation time 336873050000 ps
CPU time 736.72 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 01:15:29 PM PST 23
Peak memory 160516 kb
Host smart-3481e716-ef6f-40d2-907e-7ed8510610d0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3505774497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3505774497
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.520018411
Short name T94
Test name
Test status
Simulation time 336547970000 ps
CPU time 579.25 seconds
Started Dec 31 12:46:00 PM PST 23
Finished Dec 31 01:10:09 PM PST 23
Peak memory 160520 kb
Host smart-bbc55115-5da7-4a85-9768-a626ab86ecc0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=520018411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.520018411
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1778668936
Short name T91
Test name
Test status
Simulation time 336969330000 ps
CPU time 601.68 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 01:11:41 PM PST 23
Peak memory 160544 kb
Host smart-c0c6cef1-7b48-491f-ba5f-c48653ca4583
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1778668936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1778668936
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1860981606
Short name T106
Test name
Test status
Simulation time 336972950000 ps
CPU time 592.44 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 01:11:26 PM PST 23
Peak memory 160552 kb
Host smart-fefee611-aa33-4950-9e15-5adc32fa47aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1860981606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1860981606
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3226176519
Short name T77
Test name
Test status
Simulation time 336954810000 ps
CPU time 545.89 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 01:09:34 PM PST 23
Peak memory 160636 kb
Host smart-a4be7722-edf6-4ce6-9fd5-4c02b41f6836
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3226176519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3226176519
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3722886997
Short name T109
Test name
Test status
Simulation time 336601090000 ps
CPU time 578.29 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 01:10:46 PM PST 23
Peak memory 160480 kb
Host smart-814af1ba-dcbc-4fd2-a5bd-13b0d5b7b586
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3722886997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3722886997
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2459853562
Short name T71
Test name
Test status
Simulation time 336659130000 ps
CPU time 724 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 01:15:55 PM PST 23
Peak memory 160548 kb
Host smart-7010366a-9431-47fe-aa6a-04e70f324939
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2459853562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2459853562
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3944522969
Short name T5
Test name
Test status
Simulation time 336546230000 ps
CPU time 606.99 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 01:11:52 PM PST 23
Peak memory 160440 kb
Host smart-c4252222-e4c6-49f1-b01a-176d9ed2389f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3944522969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3944522969
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.538119874
Short name T110
Test name
Test status
Simulation time 336830590000 ps
CPU time 667.82 seconds
Started Dec 31 12:46:14 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 160584 kb
Host smart-65042382-d56d-4d3b-8f19-dd0887a07e6e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=538119874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.538119874
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4073062445
Short name T73
Test name
Test status
Simulation time 336814250000 ps
CPU time 706.74 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 160556 kb
Host smart-f2568fce-976f-4b4f-9613-31209262b173
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4073062445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4073062445
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3901972684
Short name T96
Test name
Test status
Simulation time 336364950000 ps
CPU time 672.73 seconds
Started Dec 31 12:46:10 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 160540 kb
Host smart-7ce4602e-212a-4591-bf26-47f9881921aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3901972684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3901972684
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1749333871
Short name T74
Test name
Test status
Simulation time 336749590000 ps
CPU time 646.72 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 01:13:28 PM PST 23
Peak memory 160516 kb
Host smart-f6b5eaf5-edad-4c3c-bf1e-5d08389a7e61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1749333871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1749333871
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3922428002
Short name T87
Test name
Test status
Simulation time 336597910000 ps
CPU time 637.64 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 01:13:03 PM PST 23
Peak memory 160644 kb
Host smart-0da2e440-2ea3-47db-94eb-f0fbc1ef18e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3922428002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3922428002
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3325696003
Short name T80
Test name
Test status
Simulation time 336913990000 ps
CPU time 626.22 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 01:12:15 PM PST 23
Peak memory 160472 kb
Host smart-4700a33d-573b-402c-aa79-c27723d67182
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3325696003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3325696003
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1470853571
Short name T76
Test name
Test status
Simulation time 336701790000 ps
CPU time 777.23 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 01:17:47 PM PST 23
Peak memory 160532 kb
Host smart-5da76083-2c01-4ede-b023-7bbebbcba7ba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1470853571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1470853571
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4072219628
Short name T92
Test name
Test status
Simulation time 336507350000 ps
CPU time 739.6 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 01:16:50 PM PST 23
Peak memory 160516 kb
Host smart-aac6fe28-94d7-4bec-a9dc-07e3b205f1fa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4072219628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4072219628
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2561114315
Short name T85
Test name
Test status
Simulation time 336688290000 ps
CPU time 592.78 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 01:10:44 PM PST 23
Peak memory 160488 kb
Host smart-b30cd249-1c07-4939-a4e6-2d527964f5c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2561114315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2561114315
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4211126655
Short name T107
Test name
Test status
Simulation time 336292010000 ps
CPU time 654.18 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 160636 kb
Host smart-ed4d992d-836a-4e10-a66c-ba048464c09b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4211126655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4211126655
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3773102828
Short name T104
Test name
Test status
Simulation time 336565830000 ps
CPU time 614.55 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 01:12:11 PM PST 23
Peak memory 160572 kb
Host smart-55128dea-d265-47b2-bddf-ebd49dd2d6b5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3773102828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3773102828
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1012529238
Short name T83
Test name
Test status
Simulation time 336371930000 ps
CPU time 633.5 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 01:12:38 PM PST 23
Peak memory 160500 kb
Host smart-3c8e2d35-f65b-4957-a7ba-05a9c7156454
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1012529238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1012529238
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2608167532
Short name T103
Test name
Test status
Simulation time 336813510000 ps
CPU time 593.18 seconds
Started Dec 31 12:46:56 PM PST 23
Finished Dec 31 01:12:00 PM PST 23
Peak memory 160572 kb
Host smart-938b3328-d7c4-438c-8c78-aeb350010d3c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2608167532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2608167532
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3164408490
Short name T101
Test name
Test status
Simulation time 336714110000 ps
CPU time 545.28 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 01:09:10 PM PST 23
Peak memory 160644 kb
Host smart-94e4e679-12f0-4eb8-95bf-3496c126b5e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3164408490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3164408490
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1482007879
Short name T97
Test name
Test status
Simulation time 336628870000 ps
CPU time 659.16 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 160620 kb
Host smart-f803a83e-7cc6-4930-8992-110ed64f4734
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1482007879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1482007879
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1409262500
Short name T98
Test name
Test status
Simulation time 336472790000 ps
CPU time 771.39 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 01:17:35 PM PST 23
Peak memory 160532 kb
Host smart-91b3f2d0-d8ba-4338-8f1e-907daa69ae05
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1409262500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1409262500
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3386337422
Short name T108
Test name
Test status
Simulation time 336478010000 ps
CPU time 676.27 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 01:14:08 PM PST 23
Peak memory 160560 kb
Host smart-faf475a1-1bdc-4cc2-8119-e905bb3952fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3386337422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3386337422
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2177163044
Short name T14
Test name
Test status
Simulation time 336882990000 ps
CPU time 668.24 seconds
Started Dec 31 12:45:58 PM PST 23
Finished Dec 31 01:13:14 PM PST 23
Peak memory 160564 kb
Host smart-b5437c67-2450-4a1b-88bd-00e3c600d9af
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2177163044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2177163044
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1539538985
Short name T6
Test name
Test status
Simulation time 337063750000 ps
CPU time 711.69 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 01:15:52 PM PST 23
Peak memory 160540 kb
Host smart-6bccd232-1be6-4cf6-8504-4f7f6344e268
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1539538985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1539538985
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2621529888
Short name T18
Test name
Test status
Simulation time 336617530000 ps
CPU time 629.61 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 01:13:01 PM PST 23
Peak memory 160516 kb
Host smart-12a324f0-7a5e-4a7e-8d21-e583fdeed9c2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2621529888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2621529888
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1899076734
Short name T82
Test name
Test status
Simulation time 336432950000 ps
CPU time 637.42 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 01:12:56 PM PST 23
Peak memory 160480 kb
Host smart-b59b25e8-d871-402a-8132-bb63decda7d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1899076734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1899076734
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4199319615
Short name T78
Test name
Test status
Simulation time 336453130000 ps
CPU time 686.8 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 160520 kb
Host smart-e9b76b8b-fb9f-4b2b-9711-3d79cfc70db1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4199319615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4199319615
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2840713202
Short name T15
Test name
Test status
Simulation time 337049070000 ps
CPU time 586.04 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 01:10:44 PM PST 23
Peak memory 160544 kb
Host smart-947815b2-a399-4efc-9d57-b5f20e1bb083
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2840713202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2840713202
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.868724896
Short name T79
Test name
Test status
Simulation time 337025850000 ps
CPU time 577.7 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 01:10:20 PM PST 23
Peak memory 160444 kb
Host smart-e5c7cbaa-ed1f-4a89-82c5-310fc8e4e423
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=868724896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.868724896
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1517987147
Short name T89
Test name
Test status
Simulation time 337007370000 ps
CPU time 602.11 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 01:11:27 PM PST 23
Peak memory 160492 kb
Host smart-f044573f-9fa3-4158-ba6b-d73765522e76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1517987147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1517987147
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2050591062
Short name T198
Test name
Test status
Simulation time 336810610000 ps
CPU time 802.64 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 159060 kb
Host smart-6b68706b-ec83-4ec7-8392-53f2f2b5cc33
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2050591062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2050591062
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3683966059
Short name T169
Test name
Test status
Simulation time 336980610000 ps
CPU time 632.67 seconds
Started Dec 31 12:20:16 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 160840 kb
Host smart-3a78cf77-c8f7-49e4-988a-9df2f00f0687
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3683966059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3683966059
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4271319109
Short name T161
Test name
Test status
Simulation time 336984170000 ps
CPU time 917.58 seconds
Started Dec 31 12:21:31 PM PST 23
Finished Dec 31 12:58:24 PM PST 23
Peak memory 160904 kb
Host smart-3d6c4981-44f8-4266-967f-863b4efbee2d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4271319109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.4271319109
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1231755960
Short name T192
Test name
Test status
Simulation time 336608310000 ps
CPU time 946.66 seconds
Started Dec 31 12:17:46 PM PST 23
Finished Dec 31 12:55:33 PM PST 23
Peak memory 159568 kb
Host smart-f7f44439-b967-4073-8fcb-7f67ef1e6055
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1231755960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1231755960
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1154429473
Short name T27
Test name
Test status
Simulation time 336567470000 ps
CPU time 781.8 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 159744 kb
Host smart-61f599e2-3fd2-4465-8590-142348727e38
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1154429473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1154429473
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3132765474
Short name T165
Test name
Test status
Simulation time 336913930000 ps
CPU time 653.81 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:49:49 PM PST 23
Peak memory 160856 kb
Host smart-c863d8f5-5c70-4c14-8ab0-165388283a08
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3132765474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3132765474
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.689836902
Short name T22
Test name
Test status
Simulation time 336508990000 ps
CPU time 841.74 seconds
Started Dec 31 12:27:05 PM PST 23
Finished Dec 31 01:01:10 PM PST 23
Peak memory 160804 kb
Host smart-91b9f38d-d959-4019-81f7-53b10044be56
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=689836902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.689836902
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3046985504
Short name T172
Test name
Test status
Simulation time 336512510000 ps
CPU time 826.62 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:57:59 PM PST 23
Peak memory 160696 kb
Host smart-f8c5d1bb-f19f-4661-8c8a-7aff9400dde1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3046985504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3046985504
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4158845195
Short name T162
Test name
Test status
Simulation time 336356930000 ps
CPU time 647.34 seconds
Started Dec 31 12:26:27 PM PST 23
Finished Dec 31 12:52:03 PM PST 23
Peak memory 160752 kb
Host smart-2114a1a6-570b-4040-9120-3c9480a60442
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4158845195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4158845195
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1437300337
Short name T187
Test name
Test status
Simulation time 336419710000 ps
CPU time 578.69 seconds
Started Dec 31 12:26:24 PM PST 23
Finished Dec 31 12:50:26 PM PST 23
Peak memory 160868 kb
Host smart-65500cea-4edc-490b-aa0e-48829f10203b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1437300337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1437300337
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.314591372
Short name T171
Test name
Test status
Simulation time 336459030000 ps
CPU time 818.82 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:55:44 PM PST 23
Peak memory 159164 kb
Host smart-21af4bf7-c665-481f-a2b4-2610712b1596
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=314591372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.314591372
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4069949093
Short name T179
Test name
Test status
Simulation time 336582710000 ps
CPU time 910.49 seconds
Started Dec 31 12:21:31 PM PST 23
Finished Dec 31 12:58:18 PM PST 23
Peak memory 160892 kb
Host smart-b0fb7e98-2499-41b9-8077-7642a1c19e72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4069949093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.4069949093
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1927862835
Short name T191
Test name
Test status
Simulation time 336315490000 ps
CPU time 642.58 seconds
Started Dec 31 12:20:10 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 161188 kb
Host smart-27c03d1f-3c01-4813-b6aa-ac9b6bfc8989
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1927862835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1927862835
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2915957214
Short name T193
Test name
Test status
Simulation time 336432850000 ps
CPU time 959.27 seconds
Started Dec 31 12:17:46 PM PST 23
Finished Dec 31 12:56:08 PM PST 23
Peak memory 159308 kb
Host smart-71ae1bda-48e3-4eff-b894-8ea644b43b48
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2915957214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2915957214
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4143620654
Short name T164
Test name
Test status
Simulation time 336479950000 ps
CPU time 644.74 seconds
Started Dec 31 12:23:03 PM PST 23
Finished Dec 31 12:49:36 PM PST 23
Peak memory 160856 kb
Host smart-8ad725e2-bcd7-4cde-8adb-e7bbfa972f8b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143620654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4143620654
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2294707682
Short name T24
Test name
Test status
Simulation time 336897530000 ps
CPU time 765.25 seconds
Started Dec 31 12:23:19 PM PST 23
Finished Dec 31 12:54:20 PM PST 23
Peak memory 160524 kb
Host smart-fdcd4cfb-7506-4cf0-b33d-029a9d314fa6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2294707682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2294707682
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1967616999
Short name T25
Test name
Test status
Simulation time 336862530000 ps
CPU time 624.67 seconds
Started Dec 31 12:17:59 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 160912 kb
Host smart-fae2d2bb-952e-42d9-b8b9-cec8144c49a9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1967616999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1967616999
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2242023338
Short name T173
Test name
Test status
Simulation time 337078790000 ps
CPU time 776.04 seconds
Started Dec 31 12:23:19 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 160544 kb
Host smart-a6f3c720-c756-4a17-9f22-22daee38787f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2242023338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2242023338
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2243637596
Short name T180
Test name
Test status
Simulation time 336505110000 ps
CPU time 587.84 seconds
Started Dec 31 12:27:18 PM PST 23
Finished Dec 31 12:51:44 PM PST 23
Peak memory 160876 kb
Host smart-8740597b-239e-4abd-b6e1-07b4a2d87320
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2243637596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2243637596
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2180474413
Short name T176
Test name
Test status
Simulation time 336827470000 ps
CPU time 577.05 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:50:20 PM PST 23
Peak memory 160872 kb
Host smart-b9caf009-30cc-4706-815b-aaf08c757538
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2180474413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2180474413
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2632440438
Short name T185
Test name
Test status
Simulation time 336964890000 ps
CPU time 842 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:57:45 PM PST 23
Peak memory 159936 kb
Host smart-1ef0ce10-b1f3-476d-8225-563068a550bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2632440438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2632440438
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1473875699
Short name T26
Test name
Test status
Simulation time 336583210000 ps
CPU time 845.49 seconds
Started Dec 31 12:27:35 PM PST 23
Finished Dec 31 01:01:54 PM PST 23
Peak memory 160816 kb
Host smart-b56b2f0a-512a-48cf-86bc-0501384e549b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1473875699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1473875699
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4087009103
Short name T181
Test name
Test status
Simulation time 336968550000 ps
CPU time 793.68 seconds
Started Dec 31 12:23:19 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 160544 kb
Host smart-11077dfa-8b59-4a04-8db6-e50efff34174
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4087009103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.4087009103
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1616569136
Short name T177
Test name
Test status
Simulation time 336823750000 ps
CPU time 859.33 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:58:20 PM PST 23
Peak memory 160484 kb
Host smart-a8b66c85-b9c9-457b-b133-4db5fb60b512
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1616569136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1616569136
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3345663604
Short name T190
Test name
Test status
Simulation time 336703630000 ps
CPU time 831.62 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:58:16 PM PST 23
Peak memory 160688 kb
Host smart-76610588-4dfa-4130-9011-5eae737a0fac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3345663604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3345663604
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2953847354
Short name T195
Test name
Test status
Simulation time 336773590000 ps
CPU time 850.44 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:57:13 PM PST 23
Peak memory 160796 kb
Host smart-5fd90dc8-9839-414f-b77a-4d3853499e04
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2953847354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2953847354
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3310055784
Short name T163
Test name
Test status
Simulation time 336980250000 ps
CPU time 867.22 seconds
Started Dec 31 12:23:26 PM PST 23
Finished Dec 31 12:58:17 PM PST 23
Peak memory 160692 kb
Host smart-e9a4b6b9-cbc5-45ed-86b9-a4806e82a7b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3310055784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3310055784
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3148903069
Short name T197
Test name
Test status
Simulation time 336948070000 ps
CPU time 754.64 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:55:09 PM PST 23
Peak memory 160860 kb
Host smart-96335e05-1bff-489f-9745-4c07d2cbc7b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3148903069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3148903069
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.159231858
Short name T168
Test name
Test status
Simulation time 336863270000 ps
CPU time 854.37 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:56:58 PM PST 23
Peak memory 160620 kb
Host smart-8e87b941-72f1-46a0-b838-ba3945d6f2fe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=159231858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.159231858
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2850080437
Short name T29
Test name
Test status
Simulation time 336887390000 ps
CPU time 823.99 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:56:55 PM PST 23
Peak memory 160664 kb
Host smart-d694d596-418d-41b9-8732-4166e67770f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2850080437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2850080437
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4042625527
Short name T199
Test name
Test status
Simulation time 336479470000 ps
CPU time 855.37 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:57:18 PM PST 23
Peak memory 160796 kb
Host smart-ad98f50f-afd4-4d7e-b4e8-41f64870d6cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4042625527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4042625527
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1306242648
Short name T189
Test name
Test status
Simulation time 336521230000 ps
CPU time 569.03 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:48:03 PM PST 23
Peak memory 160140 kb
Host smart-b938942e-022a-4a95-889c-c2f03c77f137
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1306242648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1306242648
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3574354803
Short name T21
Test name
Test status
Simulation time 336629790000 ps
CPU time 848.03 seconds
Started Dec 31 12:23:26 PM PST 23
Finished Dec 31 12:57:31 PM PST 23
Peak memory 160684 kb
Host smart-9f6849b0-e09e-4e24-bb48-cd72b163f2d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3574354803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3574354803
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1142822466
Short name T194
Test name
Test status
Simulation time 336613410000 ps
CPU time 631.78 seconds
Started Dec 31 12:26:31 PM PST 23
Finished Dec 31 12:52:30 PM PST 23
Peak memory 160944 kb
Host smart-f11a3bd8-1765-49df-b587-aeaa4eb75f6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1142822466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1142822466
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2324538497
Short name T186
Test name
Test status
Simulation time 336616630000 ps
CPU time 582.77 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 160060 kb
Host smart-001f0424-acb6-49fb-9496-32bfe954eefe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2324538497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2324538497
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3647393420
Short name T196
Test name
Test status
Simulation time 336940970000 ps
CPU time 751.16 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:54:40 PM PST 23
Peak memory 160520 kb
Host smart-15f44637-9695-4638-88a7-482e112bb982
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3647393420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3647393420
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3259775117
Short name T167
Test name
Test status
Simulation time 336801850000 ps
CPU time 852.49 seconds
Started Dec 31 12:22:56 PM PST 23
Finished Dec 31 12:57:11 PM PST 23
Peak memory 160796 kb
Host smart-92d6721d-dd42-416f-839e-da9ba7fff17d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3259775117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3259775117
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3948237076
Short name T178
Test name
Test status
Simulation time 336996890000 ps
CPU time 538.08 seconds
Started Dec 31 12:25:49 PM PST 23
Finished Dec 31 12:48:28 PM PST 23
Peak memory 159440 kb
Host smart-903489b1-d67f-46c0-a878-8f95349cfba0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3948237076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3948237076
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.347842077
Short name T184
Test name
Test status
Simulation time 337087490000 ps
CPU time 873.29 seconds
Started Dec 31 12:23:26 PM PST 23
Finished Dec 31 12:58:38 PM PST 23
Peak memory 160684 kb
Host smart-977fc945-1ed3-4f4f-9d0e-2b5b4a936456
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=347842077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.347842077
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.198512635
Short name T174
Test name
Test status
Simulation time 336990030000 ps
CPU time 754.16 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:54:21 PM PST 23
Peak memory 160516 kb
Host smart-3327d12f-2d07-4380-86cb-db7bc037e426
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=198512635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.198512635
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2480558512
Short name T166
Test name
Test status
Simulation time 336567410000 ps
CPU time 620.99 seconds
Started Dec 31 12:17:59 PM PST 23
Finished Dec 31 12:44:23 PM PST 23
Peak memory 160912 kb
Host smart-bdf9ba58-a60b-4cdd-b115-6632f0d51d93
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2480558512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2480558512
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1917330400
Short name T200
Test name
Test status
Simulation time 336596350000 ps
CPU time 763.62 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:54:40 PM PST 23
Peak memory 160148 kb
Host smart-4960953e-6647-4b01-93c1-663b8f566b4b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1917330400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1917330400
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2279651985
Short name T182
Test name
Test status
Simulation time 336579350000 ps
CPU time 854.93 seconds
Started Dec 31 12:23:11 PM PST 23
Finished Dec 31 12:57:37 PM PST 23
Peak memory 159928 kb
Host smart-e528f4ec-e937-4d25-9bd0-982acd05b81d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2279651985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2279651985
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2677951793
Short name T28
Test name
Test status
Simulation time 336851530000 ps
CPU time 818.51 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:57:40 PM PST 23
Peak memory 160624 kb
Host smart-b101cac4-428e-40ee-b88b-4f9eae21b04c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2677951793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2677951793
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1117325538
Short name T23
Test name
Test status
Simulation time 336904870000 ps
CPU time 517.38 seconds
Started Dec 31 12:28:07 PM PST 23
Finished Dec 31 12:50:07 PM PST 23
Peak memory 160908 kb
Host smart-5f2f6aee-56c7-4ef5-9e69-74a089d86adf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1117325538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1117325538
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1124309629
Short name T188
Test name
Test status
Simulation time 336406610000 ps
CPU time 846.37 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:59:54 PM PST 23
Peak memory 159736 kb
Host smart-9939044a-5bfb-4ce7-a6e1-31370337ff26
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1124309629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1124309629
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1503958076
Short name T183
Test name
Test status
Simulation time 336987130000 ps
CPU time 591 seconds
Started Dec 31 12:18:23 PM PST 23
Finished Dec 31 12:43:01 PM PST 23
Peak memory 160884 kb
Host smart-05951d08-a1f9-439c-955a-bee6663b06c1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1503958076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1503958076
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1677247852
Short name T175
Test name
Test status
Simulation time 336947590000 ps
CPU time 827.98 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:58:12 PM PST 23
Peak memory 160680 kb
Host smart-a405f847-2416-445a-8619-f271b279e6e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1677247852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1677247852
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2754757908
Short name T170
Test name
Test status
Simulation time 336733730000 ps
CPU time 844.31 seconds
Started Dec 31 12:27:06 PM PST 23
Finished Dec 31 01:00:58 PM PST 23
Peak memory 160808 kb
Host smart-31acdf33-da53-4e9d-a275-5b5a555bbb75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754757908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2754757908
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.734567407
Short name T132
Test name
Test status
Simulation time 1417610000 ps
CPU time 3.14 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 156172 kb
Host smart-27aab6a0-431b-4b76-980b-82d9a6e634ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=734567407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.734567407
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.552927221
Short name T129
Test name
Test status
Simulation time 1413550000 ps
CPU time 2.91 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 156132 kb
Host smart-6d42b7a1-6e13-473d-8d33-8025375fec58
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=552927221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.552927221
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2201750722
Short name T117
Test name
Test status
Simulation time 1386910000 ps
CPU time 2.71 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 156176 kb
Host smart-b275e6df-fee4-40c4-97bf-655724fba606
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2201750722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2201750722
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1317774596
Short name T151
Test name
Test status
Simulation time 1442550000 ps
CPU time 3.39 seconds
Started Dec 31 12:46:48 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 156212 kb
Host smart-225a7371-561c-460e-87ca-8bea0885568a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1317774596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1317774596
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.245417579
Short name T146
Test name
Test status
Simulation time 1413490000 ps
CPU time 4.12 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 156140 kb
Host smart-b2f32a3e-2c48-4381-8313-abcb0dccc164
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=245417579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.245417579
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.298944584
Short name T145
Test name
Test status
Simulation time 1325530000 ps
CPU time 2.54 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 156140 kb
Host smart-ef6a1646-26ee-4aa1-8a77-8f4b1f780ba4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298944584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.298944584
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3642940015
Short name T134
Test name
Test status
Simulation time 1290670000 ps
CPU time 3.32 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 156400 kb
Host smart-ea16fa6d-596c-4f3b-a553-c065a751d78b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3642940015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3642940015
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3106371017
Short name T120
Test name
Test status
Simulation time 1480070000 ps
CPU time 4.19 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 156128 kb
Host smart-437c4d3b-2526-483b-98e8-fdee6a88eacc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106371017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3106371017
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.375380294
Short name T127
Test name
Test status
Simulation time 1367950000 ps
CPU time 3.16 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 156108 kb
Host smart-e25e9654-ca36-4b17-a7d1-a0b30061bcf8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=375380294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.375380294
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.885025091
Short name T135
Test name
Test status
Simulation time 1556010000 ps
CPU time 3.63 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 156172 kb
Host smart-9ea6d79d-ba66-4193-8740-65cd5010e8f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=885025091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.885025091
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3615263662
Short name T123
Test name
Test status
Simulation time 1575590000 ps
CPU time 3.17 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 156148 kb
Host smart-ad7a4f2b-ee7b-46a7-b2ff-5d93b23635e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3615263662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3615263662
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2872807530
Short name T130
Test name
Test status
Simulation time 1528450000 ps
CPU time 3.59 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 156232 kb
Host smart-59b02c61-8dbf-489d-b5c0-6c7b189b7e7b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2872807530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2872807530
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3178371372
Short name T144
Test name
Test status
Simulation time 1206490000 ps
CPU time 2.44 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 156168 kb
Host smart-69e74cad-15be-46d8-a36a-70450a80189e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178371372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3178371372
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1305151653
Short name T152
Test name
Test status
Simulation time 1339950000 ps
CPU time 2.71 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:57 PM PST 23
Peak memory 156148 kb
Host smart-31fb8dc9-36ed-476c-b889-55bf8750d281
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1305151653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1305151653
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2367005195
Short name T140
Test name
Test status
Simulation time 1355350000 ps
CPU time 2.88 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:46:55 PM PST 23
Peak memory 156088 kb
Host smart-0d990c1b-d94b-4769-a376-2b93aba6311a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2367005195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2367005195
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.580383639
Short name T155
Test name
Test status
Simulation time 1421070000 ps
CPU time 2.97 seconds
Started Dec 31 12:47:09 PM PST 23
Finished Dec 31 12:47:19 PM PST 23
Peak memory 156164 kb
Host smart-7e308297-239d-45aa-b8f9-999e8d8bbeab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=580383639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.580383639
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1611101160
Short name T113
Test name
Test status
Simulation time 1597070000 ps
CPU time 3.16 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:31 PM PST 23
Peak memory 156164 kb
Host smart-0fcbb4a5-7802-4393-97b7-c3abec8277df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611101160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1611101160
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1394372887
Short name T118
Test name
Test status
Simulation time 1000690000 ps
CPU time 2.72 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 156168 kb
Host smart-d304eb8d-c04c-4a09-86d5-3dd325574d60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394372887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1394372887
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.44917006
Short name T122
Test name
Test status
Simulation time 1445110000 ps
CPU time 3.07 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 156080 kb
Host smart-acf7dc3d-7e74-4994-91d2-2741a3154dce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=44917006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.44917006
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2999947174
Short name T142
Test name
Test status
Simulation time 1184970000 ps
CPU time 2.47 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 156164 kb
Host smart-e1e80cfa-0fda-4213-bf64-3a8bcaf62b04
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2999947174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2999947174
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2504398009
Short name T112
Test name
Test status
Simulation time 1534290000 ps
CPU time 3.23 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 156220 kb
Host smart-4476db09-7543-446b-a585-84cbd08f6db4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2504398009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2504398009
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3523998534
Short name T153
Test name
Test status
Simulation time 1441610000 ps
CPU time 2.88 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 156180 kb
Host smart-adcace16-8db2-4b98-921d-929f5ef4be87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3523998534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3523998534
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1936797557
Short name T150
Test name
Test status
Simulation time 1438410000 ps
CPU time 3 seconds
Started Dec 31 12:46:58 PM PST 23
Finished Dec 31 12:47:06 PM PST 23
Peak memory 156180 kb
Host smart-7cf3b9f6-78fc-4317-8ce4-3dee15b29590
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936797557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1936797557
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2284677423
Short name T128
Test name
Test status
Simulation time 1563130000 ps
CPU time 3.2 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 156180 kb
Host smart-c5a2b4e4-b72f-4f97-bb52-a8ca93e87785
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2284677423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2284677423
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2936004088
Short name T115
Test name
Test status
Simulation time 1437910000 ps
CPU time 3.91 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 156144 kb
Host smart-21c3d6a0-5bd4-4413-afa5-1f40e08b6a5d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936004088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2936004088
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.629417152
Short name T126
Test name
Test status
Simulation time 1463350000 ps
CPU time 2.95 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:46:23 PM PST 23
Peak memory 156244 kb
Host smart-a9b01d1b-271d-494c-910a-8fd0a7881208
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=629417152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.629417152
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1925566143
Short name T149
Test name
Test status
Simulation time 1569150000 ps
CPU time 3.31 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:46:56 PM PST 23
Peak memory 156224 kb
Host smart-36bdfc06-4a20-4c3c-8d3f-05397d0b0067
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1925566143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1925566143
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2816675392
Short name T158
Test name
Test status
Simulation time 1485670000 ps
CPU time 4.42 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 156100 kb
Host smart-068da8f7-4c14-4b5c-91d4-436f6e42288b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816675392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2816675392
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1820272591
Short name T156
Test name
Test status
Simulation time 1253490000 ps
CPU time 2.9 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 156104 kb
Host smart-fa65f34a-cc5f-4407-a5b2-133f1e3cb2ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1820272591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1820272591
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3054461045
Short name T116
Test name
Test status
Simulation time 1331490000 ps
CPU time 2.64 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 156176 kb
Host smart-e100183c-1967-4ed8-910a-3a25a097bfc9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054461045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3054461045
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.421923360
Short name T147
Test name
Test status
Simulation time 1345190000 ps
CPU time 2.95 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 12:46:23 PM PST 23
Peak memory 156088 kb
Host smart-415be0b6-ade6-4da7-bfb7-fb2ba9c5c240
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421923360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.421923360
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1816392491
Short name T148
Test name
Test status
Simulation time 1583430000 ps
CPU time 4.09 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 156156 kb
Host smart-2d74acd4-d3e3-4635-be35-5605bfbbf85a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1816392491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1816392491
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2551918748
Short name T138
Test name
Test status
Simulation time 1167190000 ps
CPU time 2.7 seconds
Started Dec 31 12:46:10 PM PST 23
Finished Dec 31 12:46:18 PM PST 23
Peak memory 156128 kb
Host smart-9f2d676b-17b5-4e9d-a870-4f32ac0d077e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2551918748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2551918748
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4168263914
Short name T160
Test name
Test status
Simulation time 1588170000 ps
CPU time 3.56 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 156136 kb
Host smart-0c4d15c4-59c9-45a9-a57d-d2a140ad1e79
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4168263914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.4168263914
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3018524999
Short name T139
Test name
Test status
Simulation time 1403730000 ps
CPU time 2.9 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 156180 kb
Host smart-ef52eceb-f607-4f39-b2c2-dff4d94dff1b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3018524999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3018524999
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4037690300
Short name T119
Test name
Test status
Simulation time 1486910000 ps
CPU time 3.92 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 156160 kb
Host smart-c74662b8-44b8-4de9-bb85-a5ae7f73a76e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4037690300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.4037690300
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2161595476
Short name T137
Test name
Test status
Simulation time 1564410000 ps
CPU time 3.31 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 156180 kb
Host smart-f6951a71-5257-4133-a5ed-0eb934c071a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2161595476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2161595476
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.458367515
Short name T111
Test name
Test status
Simulation time 1495950000 ps
CPU time 2.98 seconds
Started Dec 31 12:46:10 PM PST 23
Finished Dec 31 12:46:19 PM PST 23
Peak memory 156124 kb
Host smart-c0e927b8-de37-41ec-abe4-a067646c10fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=458367515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.458367515
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3029093132
Short name T125
Test name
Test status
Simulation time 1260230000 ps
CPU time 3.12 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 156148 kb
Host smart-f9408582-10ec-4f7d-9d89-62491ede7ca9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3029093132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3029093132
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2172425662
Short name T133
Test name
Test status
Simulation time 1117270000 ps
CPU time 2.36 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 12:46:31 PM PST 23
Peak memory 156152 kb
Host smart-39c98e2e-dd48-4a0e-b359-997893141356
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172425662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2172425662
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2647296894
Short name T143
Test name
Test status
Simulation time 1552530000 ps
CPU time 2.98 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 156148 kb
Host smart-910dd9de-fc8f-4b29-8b66-8f0336d557a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2647296894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2647296894
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3794164747
Short name T136
Test name
Test status
Simulation time 1494530000 ps
CPU time 4.39 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 156140 kb
Host smart-44d79eb2-1c76-4e9f-8650-8be916e04082
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3794164747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3794164747
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2653775755
Short name T124
Test name
Test status
Simulation time 1503250000 ps
CPU time 3.44 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 156168 kb
Host smart-a85bd50d-6b0f-4326-af8f-656941e09247
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2653775755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2653775755
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1811414793
Short name T114
Test name
Test status
Simulation time 1520310000 ps
CPU time 3.48 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 156092 kb
Host smart-a6db7223-0eca-4ca8-9dd9-5dd623b1c3c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811414793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1811414793
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3984815304
Short name T157
Test name
Test status
Simulation time 1383790000 ps
CPU time 2.78 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 156164 kb
Host smart-a9ea6f06-7237-43cd-9f01-a3ba2963ba56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3984815304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3984815304
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.549889293
Short name T131
Test name
Test status
Simulation time 1560890000 ps
CPU time 2.96 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 156152 kb
Host smart-761d4b3a-e898-4239-bc43-630bec630dff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=549889293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.549889293
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.837118045
Short name T121
Test name
Test status
Simulation time 1472810000 ps
CPU time 3.7 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 156164 kb
Host smart-1840cdf3-ce4e-4c72-adab-ee6ad2251a97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=837118045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.837118045
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2326929235
Short name T141
Test name
Test status
Simulation time 1404050000 ps
CPU time 3.95 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 156156 kb
Host smart-ecfea30d-8b25-4de0-9c72-97e58c8fe890
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2326929235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2326929235
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2536151530
Short name T159
Test name
Test status
Simulation time 1424870000 ps
CPU time 3.51 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 156212 kb
Host smart-4195eef1-ba5b-4f44-b963-907c7a38de06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2536151530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2536151530
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3569348226
Short name T154
Test name
Test status
Simulation time 1519870000 ps
CPU time 3.14 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 156168 kb
Host smart-ca19dd7f-bb2e-482e-88c3-4df70b56e868
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569348226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3569348226
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.501645820
Short name T54
Test name
Test status
Simulation time 1479170000 ps
CPU time 3.05 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 155728 kb
Host smart-89d8ceed-72b6-44eb-ae52-d4912f628704
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=501645820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.501645820
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1746430015
Short name T62
Test name
Test status
Simulation time 1473650000 ps
CPU time 3.22 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 155744 kb
Host smart-9869b2ce-c89d-4333-b4a7-e89aecf5f15e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1746430015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1746430015
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.889618237
Short name T51
Test name
Test status
Simulation time 1349990000 ps
CPU time 2.93 seconds
Started Dec 31 12:46:03 PM PST 23
Finished Dec 31 12:46:11 PM PST 23
Peak memory 155732 kb
Host smart-5f89b911-8643-489a-8617-704adbaade88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889618237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.889618237
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1477609528
Short name T34
Test name
Test status
Simulation time 1384450000 ps
CPU time 2.91 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 155696 kb
Host smart-7bb71cf8-2368-41ff-9f44-496097865023
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1477609528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1477609528
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2077642273
Short name T9
Test name
Test status
Simulation time 1542250000 ps
CPU time 3 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 155696 kb
Host smart-22db8dc5-e0f7-4fec-a1c4-d52a7510aac6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077642273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2077642273
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1281390892
Short name T46
Test name
Test status
Simulation time 1440670000 ps
CPU time 3.17 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 155800 kb
Host smart-0231bb60-1dd5-436c-876c-56fa76f8a66b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1281390892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1281390892
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2026087412
Short name T10
Test name
Test status
Simulation time 1370610000 ps
CPU time 2.86 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 155696 kb
Host smart-3d87f05e-8905-4db0-b7e0-64c1c1eef62b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2026087412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2026087412
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3003024713
Short name T32
Test name
Test status
Simulation time 1362770000 ps
CPU time 2.85 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 155800 kb
Host smart-b40d646f-1e96-4088-9048-bb773af1e996
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3003024713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3003024713
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1688158631
Short name T39
Test name
Test status
Simulation time 1403550000 ps
CPU time 3.14 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 155744 kb
Host smart-c5900c55-3954-4701-9f91-ac6ad2c79326
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1688158631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1688158631
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1515908954
Short name T61
Test name
Test status
Simulation time 1401030000 ps
CPU time 3.8 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 155676 kb
Host smart-c83901c4-9ff8-4f9a-80ac-802ec93e25ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1515908954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1515908954
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1444310154
Short name T40
Test name
Test status
Simulation time 1537890000 ps
CPU time 4.09 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 155740 kb
Host smart-193752fb-d45f-4887-958d-47c04496aafa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1444310154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1444310154
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1041969601
Short name T70
Test name
Test status
Simulation time 1196070000 ps
CPU time 2.46 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 155704 kb
Host smart-3ae40843-9d65-444e-a6c9-673bb8dc3c35
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1041969601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1041969601
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.338985316
Short name T37
Test name
Test status
Simulation time 1601410000 ps
CPU time 3.23 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 155728 kb
Host smart-86927f75-5b4a-4d59-8b5f-ad9848ed1a95
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=338985316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.338985316
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2810822038
Short name T8
Test name
Test status
Simulation time 1467910000 ps
CPU time 2.95 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 155720 kb
Host smart-82c2f5a9-7d18-41b2-ad52-9fe19ec26ebc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810822038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2810822038
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1415888236
Short name T57
Test name
Test status
Simulation time 1407890000 ps
CPU time 3.68 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 155732 kb
Host smart-177ca707-dfa5-46cc-8264-88eef3415f5d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1415888236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1415888236
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2649656060
Short name T55
Test name
Test status
Simulation time 1363550000 ps
CPU time 3.71 seconds
Started Dec 31 12:46:55 PM PST 23
Finished Dec 31 12:47:04 PM PST 23
Peak memory 155708 kb
Host smart-5d47e514-5fd5-4c71-bbd0-ab830950716f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2649656060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2649656060
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2096222879
Short name T38
Test name
Test status
Simulation time 1324890000 ps
CPU time 3.55 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 155732 kb
Host smart-fa544db7-61b1-49d1-9d0a-96f25c5cce7c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2096222879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2096222879
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3095395507
Short name T13
Test name
Test status
Simulation time 1296670000 ps
CPU time 3.23 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 155792 kb
Host smart-99aae253-7879-4462-a782-87af11771c05
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095395507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3095395507
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1047743094
Short name T59
Test name
Test status
Simulation time 1494450000 ps
CPU time 4.53 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 155704 kb
Host smart-109b1a58-af3e-4458-a8b4-29100939fb3b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1047743094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1047743094
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2915443056
Short name T12
Test name
Test status
Simulation time 1431350000 ps
CPU time 3.51 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 155724 kb
Host smart-6dde8e0a-fe0f-4727-8f00-ffe6effe2be4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2915443056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2915443056
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3482879415
Short name T48
Test name
Test status
Simulation time 1649350000 ps
CPU time 4.05 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 155744 kb
Host smart-3570fdb9-4494-4123-ba6f-767bdbf0a427
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482879415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3482879415
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.514366254
Short name T45
Test name
Test status
Simulation time 1509050000 ps
CPU time 3.01 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 155724 kb
Host smart-062fba05-ee31-42ad-b45e-02eeef933911
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=514366254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.514366254
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.62738256
Short name T2
Test name
Test status
Simulation time 1509550000 ps
CPU time 3.64 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 155724 kb
Host smart-51e9b7e0-bac9-4413-9ef1-858c8fb2fee8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=62738256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.62738256
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2507606572
Short name T58
Test name
Test status
Simulation time 1531010000 ps
CPU time 3.07 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:40 PM PST 23
Peak memory 155736 kb
Host smart-cdb30fd7-75e8-41c3-88d9-6062cbd17a86
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507606572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2507606572
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1811594915
Short name T7
Test name
Test status
Simulation time 1495630000 ps
CPU time 2.84 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 155652 kb
Host smart-b3846c50-13c2-4a46-a73a-cf5ca690b6fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811594915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1811594915
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.926580420
Short name T33
Test name
Test status
Simulation time 1500110000 ps
CPU time 3.37 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 155716 kb
Host smart-9a1e6ae8-3765-4cd4-ab6b-c422186c37a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=926580420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.926580420
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3726941205
Short name T43
Test name
Test status
Simulation time 1527570000 ps
CPU time 4.03 seconds
Started Dec 31 12:46:41 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 155704 kb
Host smart-1ef78f03-7fb7-4b2f-89cc-515e71c646ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3726941205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3726941205
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2811658082
Short name T1
Test name
Test status
Simulation time 1425570000 ps
CPU time 3.18 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 155692 kb
Host smart-1eb6ba1f-aedc-4069-9a37-121e2126f97f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2811658082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2811658082
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.180020199
Short name T63
Test name
Test status
Simulation time 1572590000 ps
CPU time 3.63 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:35 PM PST 23
Peak memory 155736 kb
Host smart-3e73fe91-8ca6-45b7-980c-99157a1bee0f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=180020199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.180020199
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2692835043
Short name T53
Test name
Test status
Simulation time 1259630000 ps
CPU time 2.6 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 155748 kb
Host smart-b3328565-fdfe-41d4-ac40-3c3e400923ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692835043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2692835043
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1607539895
Short name T44
Test name
Test status
Simulation time 1530970000 ps
CPU time 3.6 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 155784 kb
Host smart-b0ae8293-a266-4fc3-8d4b-bfe1f05dffb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1607539895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1607539895
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1036928572
Short name T64
Test name
Test status
Simulation time 1449290000 ps
CPU time 2.76 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 155740 kb
Host smart-8b1e7192-0b07-455d-aefd-4e22621c40de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1036928572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1036928572
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1654418483
Short name T47
Test name
Test status
Simulation time 1371670000 ps
CPU time 2.82 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 155696 kb
Host smart-b557aad9-7881-4a95-a8c7-c7e579c4101d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1654418483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1654418483
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1125516388
Short name T69
Test name
Test status
Simulation time 1534290000 ps
CPU time 3.29 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 155800 kb
Host smart-0c92dcba-4481-4714-b09a-3faa97571584
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1125516388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1125516388
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1614157267
Short name T41
Test name
Test status
Simulation time 1340610000 ps
CPU time 3.25 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 155732 kb
Host smart-ac874868-75d4-4bb5-aeb1-2e2e3f228f58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1614157267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1614157267
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2453962125
Short name T60
Test name
Test status
Simulation time 1138270000 ps
CPU time 2.52 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 155800 kb
Host smart-22440d70-fe00-450e-9083-1837aa07fe50
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453962125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2453962125
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4276689196
Short name T56
Test name
Test status
Simulation time 1326330000 ps
CPU time 2.74 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 155708 kb
Host smart-06ea1af1-a84b-4094-8ade-b2750c9cc967
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276689196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.4276689196
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4068378686
Short name T50
Test name
Test status
Simulation time 1599890000 ps
CPU time 4.52 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 155708 kb
Host smart-ec79f655-b31a-4ac7-bd5c-ce4937f5ba55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4068378686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4068378686
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4174446635
Short name T52
Test name
Test status
Simulation time 1545010000 ps
CPU time 3.23 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 155724 kb
Host smart-fa83db8b-2783-4576-bce6-66409e8be062
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4174446635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4174446635
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1481133663
Short name T31
Test name
Test status
Simulation time 1098950000 ps
CPU time 2.36 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 155724 kb
Host smart-25483a2e-83ec-49db-a70a-eb0ba472dbb5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1481133663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1481133663
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2210013084
Short name T42
Test name
Test status
Simulation time 1555570000 ps
CPU time 4.41 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 155704 kb
Host smart-6d5796f9-1edf-4b25-aabf-c97aef27344d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2210013084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2210013084
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4008474968
Short name T49
Test name
Test status
Simulation time 1440890000 ps
CPU time 3.52 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 155704 kb
Host smart-2b080baf-5ca7-4590-b309-cf5e3b889bb9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4008474968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4008474968
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2577077146
Short name T68
Test name
Test status
Simulation time 1512890000 ps
CPU time 5.18 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 155748 kb
Host smart-055f694a-f5e6-43a2-9746-b65f2193ac5b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2577077146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2577077146
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2786809680
Short name T35
Test name
Test status
Simulation time 1526410000 ps
CPU time 3.32 seconds
Started Dec 31 12:46:04 PM PST 23
Finished Dec 31 12:46:13 PM PST 23
Peak memory 155748 kb
Host smart-65cd5052-0701-4389-bd25-3be186b8ccc4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2786809680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2786809680
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.448712839
Short name T66
Test name
Test status
Simulation time 1431950000 ps
CPU time 3.6 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 155740 kb
Host smart-3f4cd2c4-69de-4523-8f9d-3cafc8a9e3bc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=448712839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.448712839
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3863132634
Short name T65
Test name
Test status
Simulation time 1518030000 ps
CPU time 4.26 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 155708 kb
Host smart-dab893d4-f276-425c-91d3-d8a47a6868e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3863132634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3863132634
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.877217187
Short name T11
Test name
Test status
Simulation time 1434390000 ps
CPU time 2.84 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:46:44 PM PST 23
Peak memory 155736 kb
Host smart-e22fb31d-5975-4154-b252-46dfdc0de40f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=877217187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.877217187
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1494856598
Short name T36
Test name
Test status
Simulation time 1237970000 ps
CPU time 2.55 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:46:55 PM PST 23
Peak memory 155772 kb
Host smart-b0ce50a1-e968-4da8-82ee-0859184633bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1494856598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1494856598
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3456025749
Short name T67
Test name
Test status
Simulation time 1584330000 ps
CPU time 3.11 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 155740 kb
Host smart-59e243db-74ac-442e-a626-b68dfc856fd7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3456025749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3456025749
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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