Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2084757192
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2188293868
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3953840494
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1678691736

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2760710059
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.9842124
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1535175845
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.978559745
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2487365756
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2125789412
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3809150576
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.124242714
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.146557739
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.683235830
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.504817201
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2961889560
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.627340326
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1334182868
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3411395181
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2955842591
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2120355288
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2151396864
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.342849909
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1353066692
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3133056306
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3012908261
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1441045147
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4045675225
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2643154351
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3571465318
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4083558120
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4277467963
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3678960583
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1986087880
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1029546168
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.996608555
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3647285315
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2721703833
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1443159495
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4230970700
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2479888270
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3222579624
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1214682637
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1831897135
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3750817753
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1653756241
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.252544020
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.177897688
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3673288492
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3480281642
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1077575037
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3061425137
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.734857414
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.672707470
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2686287365
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2067208922
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3259308062
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.647907793
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.774264110
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3612547764
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2008501574
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2912452646
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1226735285
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3657200783
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3219697086
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1781542715
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2905541731
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3922391940
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3320336447
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4034280839
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2453374537
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2621171760
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4106003557
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.89359782
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.40754935
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.811088650
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4193157333
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2770447754
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2928843691
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2072199281
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.743331911
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2831416223
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1171107169
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.153416478
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3760199401
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3382378087
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1865505241
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2640632895
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.813553424
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2937020451
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.88675807
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.593790541
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1052691407
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.565211049
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1420122694
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.375965302
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2431310046
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3336924502
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3255598467
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1526494923
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.390664901
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1046567681
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.528234331
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3460101786
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.141042170
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1011171362
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4169964496
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.808968832
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.553661176
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1918946599
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.933554101
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1596021115
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2190681589
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2285673666
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.531037874
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3451584454
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1747081802
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.801434913
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.533548794
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.511185432
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3229969382
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3961855391
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1565902276
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2010368268
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1059407931
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1629695451
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1888733634
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3002868013
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3823181227
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2512502694
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.627692421
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1582228888
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3239811409
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2858326546
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1108834954
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3436773293
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3773383976
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3243451288
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.578991956
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.55314505
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.840433827
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3269521307
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1394859480
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2757753392
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3054754009
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2175264848
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1008323224
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.952162425
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1332555330
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4032122314
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1796889696
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2437690382
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1138072270
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1465886922
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2586708724
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3156543390
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2330598523
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1919377959
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3938302085
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.477466442
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2672222548
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2567560364
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1979392028
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.456043639
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.374223297
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3226658481
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3275254333
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2987031838
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.138290688
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.461559693
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1718809652
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1874038196
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2796551732
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2950293040
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2163702213
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.320411278
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1299636794
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3982765535
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.867453220
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.648056372
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.452043773
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2662588506
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3244996560
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1074832449
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2444196462
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1532970170
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2727465717
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.794745455
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3220249901
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1196655982
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2842067646
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2327197206
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1698307508
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.733119340
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.672928748
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1175279974
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1924876570
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1928359471
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2390513748
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.461902275



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2327197206 Jan 14 12:57:56 PM PST 24 Jan 14 12:58:07 PM PST 24 1441770000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1924876570 Jan 14 12:57:00 PM PST 24 Jan 14 12:57:09 PM PST 24 1455730000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2444196462 Jan 14 12:57:01 PM PST 24 Jan 14 12:57:10 PM PST 24 1595190000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2084757192 Jan 14 12:57:03 PM PST 24 Jan 14 12:57:14 PM PST 24 1570090000 ps
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T139 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1747081802 Jan 14 12:55:19 PM PST 24 Jan 14 12:55:26 PM PST 24 1104270000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2285673666 Jan 14 12:55:00 PM PST 24 Jan 14 12:55:09 PM PST 24 1410190000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2010368268 Jan 14 12:55:39 PM PST 24 Jan 14 12:55:47 PM PST 24 1401070000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1582228888 Jan 14 12:55:54 PM PST 24 Jan 14 12:56:05 PM PST 24 1359030000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.933554101 Jan 14 12:55:10 PM PST 24 Jan 14 12:55:19 PM PST 24 1538150000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2757753392 Jan 14 12:56:07 PM PST 24 Jan 14 12:56:15 PM PST 24 1295770000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1596021115 Jan 14 12:55:19 PM PST 24 Jan 14 12:55:30 PM PST 24 1546170000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3773383976 Jan 14 12:56:15 PM PST 24 Jan 14 12:56:26 PM PST 24 1562190000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1918946599 Jan 14 12:55:12 PM PST 24 Jan 14 12:55:22 PM PST 24 1422570000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1332555330 Jan 14 12:55:02 PM PST 24 Jan 14 12:55:15 PM PST 24 1489330000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.528234331 Jan 14 12:55:02 PM PST 24 Jan 14 12:55:12 PM PST 24 1374110000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1059407931 Jan 14 12:55:06 PM PST 24 Jan 14 12:55:17 PM PST 24 1486850000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.55314505 Jan 14 12:56:07 PM PST 24 Jan 14 12:56:14 PM PST 24 1260650000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.578991956 Jan 14 12:56:08 PM PST 24 Jan 14 12:56:18 PM PST 24 1504310000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.531037874 Jan 14 12:55:19 PM PST 24 Jan 14 12:55:28 PM PST 24 1247810000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.627692421 Jan 14 12:55:45 PM PST 24 Jan 14 12:55:55 PM PST 24 1530410000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2190681589 Jan 14 12:55:20 PM PST 24 Jan 14 12:55:28 PM PST 24 1357010000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3823181227 Jan 14 12:55:36 PM PST 24 Jan 14 12:55:43 PM PST 24 1496130000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3054754009 Jan 14 12:56:18 PM PST 24 Jan 14 12:56:29 PM PST 24 1555090000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1008323224 Jan 14 12:55:02 PM PST 24 Jan 14 12:55:12 PM PST 24 1545950000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3436773293 Jan 14 12:55:03 PM PST 24 Jan 14 12:55:15 PM PST 24 1588770000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.808968832 Jan 14 12:55:10 PM PST 24 Jan 14 12:55:22 PM PST 24 1343830000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3953840494 Jan 14 12:56:10 PM PST 24 Jan 14 01:28:52 PM PST 24 336881190000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1334182868 Jan 14 12:56:30 PM PST 24 Jan 14 01:37:15 PM PST 24 336497850000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1029546168 Jan 14 12:56:48 PM PST 24 Jan 14 01:37:42 PM PST 24 336957330000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1653756241 Jan 14 12:56:54 PM PST 24 Jan 14 01:23:32 PM PST 24 336790430000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2721703833 Jan 14 12:56:12 PM PST 24 Jan 14 01:25:34 PM PST 24 336992970000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1353066692 Jan 14 12:56:32 PM PST 24 Jan 14 01:37:54 PM PST 24 336905890000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.734857414 Jan 14 12:56:20 PM PST 24 Jan 14 01:33:36 PM PST 24 336749050000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.124242714 Jan 14 12:56:15 PM PST 24 Jan 14 01:26:13 PM PST 24 336868090000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4045675225 Jan 14 12:56:29 PM PST 24 Jan 14 01:33:02 PM PST 24 337072790000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.252544020 Jan 14 12:56:56 PM PST 24 Jan 14 01:37:38 PM PST 24 336722730000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1535175845 Jan 14 12:56:18 PM PST 24 Jan 14 01:34:14 PM PST 24 336375790000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.146557739 Jan 14 12:56:15 PM PST 24 Jan 14 01:29:46 PM PST 24 336706330000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2961889560 Jan 14 12:56:10 PM PST 24 Jan 14 01:28:44 PM PST 24 336527070000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3222579624 Jan 14 12:56:50 PM PST 24 Jan 14 01:27:20 PM PST 24 336690130000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3411395181 Jan 14 12:56:30 PM PST 24 Jan 14 01:37:24 PM PST 24 336432470000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1214682637 Jan 14 12:56:51 PM PST 24 Jan 14 01:29:44 PM PST 24 336898410000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.177897688 Jan 14 12:57:00 PM PST 24 Jan 14 01:28:47 PM PST 24 336860090000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2479888270 Jan 14 12:56:49 PM PST 24 Jan 14 01:24:10 PM PST 24 336476670000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3061425137 Jan 14 12:56:14 PM PST 24 Jan 14 01:22:51 PM PST 24 336359010000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2643154351 Jan 14 12:56:31 PM PST 24 Jan 14 01:36:52 PM PST 24 336498510000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3133056306 Jan 14 12:56:30 PM PST 24 Jan 14 01:23:45 PM PST 24 336384850000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2151396864 Jan 14 12:56:31 PM PST 24 Jan 14 01:29:15 PM PST 24 337146230000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3571465318 Jan 14 12:56:30 PM PST 24 Jan 14 01:25:59 PM PST 24 336455010000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3480281642 Jan 14 12:56:10 PM PST 24 Jan 14 01:26:25 PM PST 24 336770470000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.627340326 Jan 14 12:56:20 PM PST 24 Jan 14 01:32:30 PM PST 24 336507810000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3809150576 Jan 14 12:56:15 PM PST 24 Jan 14 01:22:52 PM PST 24 336701970000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.996608555 Jan 14 12:56:40 PM PST 24 Jan 14 01:30:08 PM PST 24 336474230000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4230970700 Jan 14 12:56:49 PM PST 24 Jan 14 01:25:48 PM PST 24 336443370000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3647285315 Jan 14 12:56:48 PM PST 24 Jan 14 01:37:26 PM PST 24 336557350000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.683235830 Jan 14 12:56:20 PM PST 24 Jan 14 01:32:51 PM PST 24 336925030000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1077575037 Jan 14 12:56:11 PM PST 24 Jan 14 01:31:02 PM PST 24 336897830000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1986087880 Jan 14 12:56:38 PM PST 24 Jan 14 01:30:20 PM PST 24 336413770000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1443159495 Jan 14 12:56:38 PM PST 24 Jan 14 01:30:15 PM PST 24 336727970000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.504817201 Jan 14 12:56:14 PM PST 24 Jan 14 01:26:40 PM PST 24 336449530000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2760710059 Jan 14 12:56:14 PM PST 24 Jan 14 01:26:02 PM PST 24 336623370000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3750817753 Jan 14 12:56:55 PM PST 24 Jan 14 01:23:40 PM PST 24 336628390000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2487365756 Jan 14 12:56:16 PM PST 24 Jan 14 01:28:31 PM PST 24 337016930000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4083558120 Jan 14 12:56:36 PM PST 24 Jan 14 01:25:08 PM PST 24 336376130000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4277467963 Jan 14 12:56:42 PM PST 24 Jan 14 01:34:20 PM PST 24 336368110000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.9842124 Jan 14 12:56:21 PM PST 24 Jan 14 01:33:40 PM PST 24 336786370000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1441045147 Jan 14 12:56:11 PM PST 24 Jan 14 01:26:22 PM PST 24 336775310000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2120355288 Jan 14 12:56:31 PM PST 24 Jan 14 01:31:32 PM PST 24 336525250000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3012908261 Jan 14 12:56:31 PM PST 24 Jan 14 01:37:54 PM PST 24 336987990000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1831897135 Jan 14 12:56:55 PM PST 24 Jan 14 01:28:34 PM PST 24 337087610000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2955842591 Jan 14 12:56:29 PM PST 24 Jan 14 01:38:01 PM PST 24 336561230000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.978559745 Jan 14 12:56:18 PM PST 24 Jan 14 01:33:51 PM PST 24 336573630000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3673288492 Jan 14 12:56:10 PM PST 24 Jan 14 01:24:51 PM PST 24 336479170000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.342849909 Jan 14 12:56:30 PM PST 24 Jan 14 01:24:28 PM PST 24 336795490000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3678960583 Jan 14 12:56:41 PM PST 24 Jan 14 01:28:45 PM PST 24 336423450000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2125789412 Jan 14 12:56:19 PM PST 24 Jan 14 01:33:41 PM PST 24 336464230000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2084757192
Short name T7
Test name
Test status
Simulation time 1570090000 ps
CPU time 4.51 seconds
Started Jan 14 12:57:03 PM PST 24
Finished Jan 14 12:57:14 PM PST 24
Peak memory 155796 kb
Host smart-8d6028d7-1ee9-48b7-9f20-44d2d30dd218
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2084757192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2084757192
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2188293868
Short name T23
Test name
Test status
Simulation time 336959510000 ps
CPU time 762.04 seconds
Started Jan 14 12:54:29 PM PST 24
Finished Jan 14 01:25:11 PM PST 24
Peak memory 160908 kb
Host smart-27e02edd-8711-45c5-91ca-54977ef3a265
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2188293868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2188293868
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3953840494
Short name T31
Test name
Test status
Simulation time 336881190000 ps
CPU time 816.89 seconds
Started Jan 14 12:56:10 PM PST 24
Finished Jan 14 01:28:52 PM PST 24
Peak memory 160472 kb
Host smart-8b6111a3-1e8c-44c3-9a95-cc62e11e177f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3953840494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3953840494
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1678691736
Short name T27
Test name
Test status
Simulation time 1295050000 ps
CPU time 4.44 seconds
Started Jan 14 12:55:03 PM PST 24
Finished Jan 14 12:55:14 PM PST 24
Peak memory 156216 kb
Host smart-5d0fb928-13f1-4bda-9a82-58ee23a4ecc6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1678691736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1678691736
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2760710059
Short name T185
Test name
Test status
Simulation time 336623370000 ps
CPU time 736.65 seconds
Started Jan 14 12:56:14 PM PST 24
Finished Jan 14 01:26:02 PM PST 24
Peak memory 160504 kb
Host smart-e08be256-7e9c-49fd-9906-e9d452a0bcad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2760710059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2760710059
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.9842124
Short name T190
Test name
Test status
Simulation time 336786370000 ps
CPU time 912.58 seconds
Started Jan 14 12:56:21 PM PST 24
Finished Jan 14 01:33:40 PM PST 24
Peak memory 160512 kb
Host smart-8984694e-0cee-413e-a5f2-96ddd42b5425
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=9842124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.9842124
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1535175845
Short name T161
Test name
Test status
Simulation time 336375790000 ps
CPU time 946.79 seconds
Started Jan 14 12:56:18 PM PST 24
Finished Jan 14 01:34:14 PM PST 24
Peak memory 160504 kb
Host smart-2fa5a7ec-7123-426a-ba6b-b52dbb18dbdf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1535175845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1535175845
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.978559745
Short name T196
Test name
Test status
Simulation time 336573630000 ps
CPU time 938.43 seconds
Started Jan 14 12:56:18 PM PST 24
Finished Jan 14 01:33:51 PM PST 24
Peak memory 160496 kb
Host smart-a00ccd22-cdf1-43db-b5e7-b19a856e29ec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=978559745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.978559745
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2487365756
Short name T187
Test name
Test status
Simulation time 337016930000 ps
CPU time 814.41 seconds
Started Jan 14 12:56:16 PM PST 24
Finished Jan 14 01:28:31 PM PST 24
Peak memory 160480 kb
Host smart-ee0da7b0-a581-415d-9626-243d0348b987
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2487365756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2487365756
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2125789412
Short name T200
Test name
Test status
Simulation time 336464230000 ps
CPU time 919.4 seconds
Started Jan 14 12:56:19 PM PST 24
Finished Jan 14 01:33:41 PM PST 24
Peak memory 160504 kb
Host smart-b3d01286-e118-464d-9b73-fc45519df071
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2125789412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2125789412
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3809150576
Short name T176
Test name
Test status
Simulation time 336701970000 ps
CPU time 641.54 seconds
Started Jan 14 12:56:15 PM PST 24
Finished Jan 14 01:22:52 PM PST 24
Peak memory 160496 kb
Host smart-af415b12-ce27-4fb2-9d89-37d4ba3ac0e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3809150576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3809150576
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.124242714
Short name T38
Test name
Test status
Simulation time 336868090000 ps
CPU time 740.54 seconds
Started Jan 14 12:56:15 PM PST 24
Finished Jan 14 01:26:13 PM PST 24
Peak memory 160492 kb
Host smart-754e7f60-462e-4d8a-b495-d00ec3f7d7dd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=124242714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.124242714
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.146557739
Short name T162
Test name
Test status
Simulation time 336706330000 ps
CPU time 822.11 seconds
Started Jan 14 12:56:15 PM PST 24
Finished Jan 14 01:29:46 PM PST 24
Peak memory 160552 kb
Host smart-ee7e7c4c-53a7-4685-958f-67f67e3a33d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=146557739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.146557739
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.683235830
Short name T180
Test name
Test status
Simulation time 336925030000 ps
CPU time 891.72 seconds
Started Jan 14 12:56:20 PM PST 24
Finished Jan 14 01:32:51 PM PST 24
Peak memory 160496 kb
Host smart-c0c269ea-9d1b-4aee-9b9b-c5154eeb3705
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=683235830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.683235830
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.504817201
Short name T184
Test name
Test status
Simulation time 336449530000 ps
CPU time 754.18 seconds
Started Jan 14 12:56:14 PM PST 24
Finished Jan 14 01:26:40 PM PST 24
Peak memory 160520 kb
Host smart-507806bf-eb2e-4abf-bc5f-93647fb6124e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=504817201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.504817201
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2961889560
Short name T163
Test name
Test status
Simulation time 336527070000 ps
CPU time 817.66 seconds
Started Jan 14 12:56:10 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 160472 kb
Host smart-7838dec0-c00c-49bb-9088-286bd4e33bad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2961889560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2961889560
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.627340326
Short name T175
Test name
Test status
Simulation time 336507810000 ps
CPU time 888.98 seconds
Started Jan 14 12:56:20 PM PST 24
Finished Jan 14 01:32:30 PM PST 24
Peak memory 160496 kb
Host smart-840319f2-7efb-443a-ae14-7ae84dd37114
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=627340326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.627340326
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1334182868
Short name T32
Test name
Test status
Simulation time 336497850000 ps
CPU time 989.73 seconds
Started Jan 14 12:56:30 PM PST 24
Finished Jan 14 01:37:15 PM PST 24
Peak memory 160468 kb
Host smart-b6d3ecb4-d8a2-4664-a5c3-71ebb7443c61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1334182868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1334182868
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3411395181
Short name T165
Test name
Test status
Simulation time 336432470000 ps
CPU time 1009.93 seconds
Started Jan 14 12:56:30 PM PST 24
Finished Jan 14 01:37:24 PM PST 24
Peak memory 160468 kb
Host smart-95ff1075-ec81-4b38-8e0d-4fa0e347c187
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3411395181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3411395181
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2955842591
Short name T195
Test name
Test status
Simulation time 336561230000 ps
CPU time 1027.02 seconds
Started Jan 14 12:56:29 PM PST 24
Finished Jan 14 01:38:01 PM PST 24
Peak memory 160468 kb
Host smart-4cc59ea0-f18f-42d1-ab1e-131f763bb081
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2955842591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2955842591
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2120355288
Short name T192
Test name
Test status
Simulation time 336525250000 ps
CPU time 872.05 seconds
Started Jan 14 12:56:31 PM PST 24
Finished Jan 14 01:31:32 PM PST 24
Peak memory 160496 kb
Host smart-53674fda-439c-4de2-bb5c-c2dd068db7c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2120355288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2120355288
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2151396864
Short name T172
Test name
Test status
Simulation time 337146230000 ps
CPU time 808.03 seconds
Started Jan 14 12:56:31 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 160440 kb
Host smart-c4ebda01-77bc-41b2-b546-96b590393742
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2151396864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2151396864
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.342849909
Short name T198
Test name
Test status
Simulation time 336795490000 ps
CPU time 677.29 seconds
Started Jan 14 12:56:30 PM PST 24
Finished Jan 14 01:24:28 PM PST 24
Peak memory 160484 kb
Host smart-682db6a6-6e6c-4a90-b519-958f04a100fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=342849909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.342849909
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1353066692
Short name T36
Test name
Test status
Simulation time 336905890000 ps
CPU time 1007.49 seconds
Started Jan 14 12:56:32 PM PST 24
Finished Jan 14 01:37:54 PM PST 24
Peak memory 160468 kb
Host smart-c91f4f75-ec54-4ad5-a0df-333f6cb42b11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1353066692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1353066692
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3133056306
Short name T171
Test name
Test status
Simulation time 336384850000 ps
CPU time 671.09 seconds
Started Jan 14 12:56:30 PM PST 24
Finished Jan 14 01:23:45 PM PST 24
Peak memory 160532 kb
Host smart-e759aba6-7215-4cab-9d7e-e1801a356bdd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3133056306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3133056306
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3012908261
Short name T193
Test name
Test status
Simulation time 336987990000 ps
CPU time 1010.66 seconds
Started Jan 14 12:56:31 PM PST 24
Finished Jan 14 01:37:54 PM PST 24
Peak memory 160460 kb
Host smart-397c425f-821c-4297-87c6-667a7cdb5d1b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3012908261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3012908261
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1441045147
Short name T191
Test name
Test status
Simulation time 336775310000 ps
CPU time 752.95 seconds
Started Jan 14 12:56:11 PM PST 24
Finished Jan 14 01:26:22 PM PST 24
Peak memory 160484 kb
Host smart-e3c1551f-6ef1-4bd8-9464-ae598f11d78f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1441045147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1441045147
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4045675225
Short name T39
Test name
Test status
Simulation time 337072790000 ps
CPU time 898.01 seconds
Started Jan 14 12:56:29 PM PST 24
Finished Jan 14 01:33:02 PM PST 24
Peak memory 160504 kb
Host smart-4d170898-78c5-4827-a972-326f5442664c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4045675225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4045675225
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2643154351
Short name T170
Test name
Test status
Simulation time 336498510000 ps
CPU time 981.58 seconds
Started Jan 14 12:56:31 PM PST 24
Finished Jan 14 01:36:52 PM PST 24
Peak memory 160464 kb
Host smart-348d0646-33d0-48d5-aefd-5bca0b77c0b5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2643154351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2643154351
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3571465318
Short name T173
Test name
Test status
Simulation time 336455010000 ps
CPU time 745.05 seconds
Started Jan 14 12:56:30 PM PST 24
Finished Jan 14 01:25:59 PM PST 24
Peak memory 160528 kb
Host smart-629ad169-d64a-4548-a25a-96089540ec7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3571465318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3571465318
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4083558120
Short name T188
Test name
Test status
Simulation time 336376130000 ps
CPU time 701.34 seconds
Started Jan 14 12:56:36 PM PST 24
Finished Jan 14 01:25:08 PM PST 24
Peak memory 160472 kb
Host smart-aeb74f26-858f-4da5-8131-e87e5c3d22b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4083558120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.4083558120
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4277467963
Short name T189
Test name
Test status
Simulation time 336368110000 ps
CPU time 935.69 seconds
Started Jan 14 12:56:42 PM PST 24
Finished Jan 14 01:34:20 PM PST 24
Peak memory 160504 kb
Host smart-274e40c1-a32a-4b14-99ca-75c81e7d0ce0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4277467963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4277467963
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3678960583
Short name T199
Test name
Test status
Simulation time 336423450000 ps
CPU time 796.24 seconds
Started Jan 14 12:56:41 PM PST 24
Finished Jan 14 01:28:45 PM PST 24
Peak memory 160480 kb
Host smart-5ca439bd-def3-4698-a24d-80bda6fdf4e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3678960583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3678960583
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1986087880
Short name T182
Test name
Test status
Simulation time 336413770000 ps
CPU time 829.76 seconds
Started Jan 14 12:56:38 PM PST 24
Finished Jan 14 01:30:20 PM PST 24
Peak memory 160584 kb
Host smart-2a96e540-526b-43a2-8a4f-a6a695d729f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1986087880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1986087880
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1029546168
Short name T33
Test name
Test status
Simulation time 336957330000 ps
CPU time 993.26 seconds
Started Jan 14 12:56:48 PM PST 24
Finished Jan 14 01:37:42 PM PST 24
Peak memory 160468 kb
Host smart-41aea690-80cc-45a1-b55f-ccddbb36fd01
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1029546168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1029546168
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.996608555
Short name T177
Test name
Test status
Simulation time 336474230000 ps
CPU time 824.97 seconds
Started Jan 14 12:56:40 PM PST 24
Finished Jan 14 01:30:08 PM PST 24
Peak memory 160492 kb
Host smart-7132fd24-d6de-4000-acea-0d728c3ab691
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=996608555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.996608555
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3647285315
Short name T179
Test name
Test status
Simulation time 336557350000 ps
CPU time 979.08 seconds
Started Jan 14 12:56:48 PM PST 24
Finished Jan 14 01:37:26 PM PST 24
Peak memory 160468 kb
Host smart-94860c8f-8981-401d-9067-4087fa5975e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3647285315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3647285315
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2721703833
Short name T35
Test name
Test status
Simulation time 336992970000 ps
CPU time 725.6 seconds
Started Jan 14 12:56:12 PM PST 24
Finished Jan 14 01:25:34 PM PST 24
Peak memory 160520 kb
Host smart-cfdcd7f5-bcb1-4a30-b278-9e9e81b9fa7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2721703833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2721703833
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1443159495
Short name T183
Test name
Test status
Simulation time 336727970000 ps
CPU time 844.51 seconds
Started Jan 14 12:56:38 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 160452 kb
Host smart-1bbf196f-8665-4a72-872e-091072229edf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1443159495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1443159495
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4230970700
Short name T178
Test name
Test status
Simulation time 336443370000 ps
CPU time 721.93 seconds
Started Jan 14 12:56:49 PM PST 24
Finished Jan 14 01:25:48 PM PST 24
Peak memory 160524 kb
Host smart-89a57e92-ed10-4936-a489-8314a9c1948b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4230970700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4230970700
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2479888270
Short name T168
Test name
Test status
Simulation time 336476670000 ps
CPU time 663.28 seconds
Started Jan 14 12:56:49 PM PST 24
Finished Jan 14 01:24:10 PM PST 24
Peak memory 160524 kb
Host smart-05804020-3d91-4eb7-9627-0baface8fc7c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2479888270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2479888270
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3222579624
Short name T164
Test name
Test status
Simulation time 336690130000 ps
CPU time 755.34 seconds
Started Jan 14 12:56:50 PM PST 24
Finished Jan 14 01:27:20 PM PST 24
Peak memory 160568 kb
Host smart-76f7bc2b-1e85-44db-8837-796c08db20fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3222579624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3222579624
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1214682637
Short name T166
Test name
Test status
Simulation time 336898410000 ps
CPU time 826.52 seconds
Started Jan 14 12:56:51 PM PST 24
Finished Jan 14 01:29:44 PM PST 24
Peak memory 160452 kb
Host smart-e65eab2c-868c-442e-8a72-739fcf494744
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1214682637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1214682637
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1831897135
Short name T194
Test name
Test status
Simulation time 337087610000 ps
CPU time 793.71 seconds
Started Jan 14 12:56:55 PM PST 24
Finished Jan 14 01:28:34 PM PST 24
Peak memory 160480 kb
Host smart-2f39d9fb-2926-4e5e-b043-ccf102d7eee0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1831897135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1831897135
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3750817753
Short name T186
Test name
Test status
Simulation time 336628390000 ps
CPU time 648.31 seconds
Started Jan 14 12:56:55 PM PST 24
Finished Jan 14 01:23:40 PM PST 24
Peak memory 160472 kb
Host smart-6eda8c9a-b440-449c-9d47-3f571a0e6724
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3750817753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3750817753
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1653756241
Short name T34
Test name
Test status
Simulation time 336790430000 ps
CPU time 634.72 seconds
Started Jan 14 12:56:54 PM PST 24
Finished Jan 14 01:23:32 PM PST 24
Peak memory 160408 kb
Host smart-1e159d4f-df1f-4312-ac0b-6f5901b8890b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1653756241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1653756241
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.252544020
Short name T40
Test name
Test status
Simulation time 336722730000 ps
CPU time 986.73 seconds
Started Jan 14 12:56:56 PM PST 24
Finished Jan 14 01:37:38 PM PST 24
Peak memory 160460 kb
Host smart-fcb7735d-28dc-4a2b-8e0e-48f11c745648
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=252544020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.252544020
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.177897688
Short name T167
Test name
Test status
Simulation time 336860090000 ps
CPU time 796.78 seconds
Started Jan 14 12:57:00 PM PST 24
Finished Jan 14 01:28:47 PM PST 24
Peak memory 160432 kb
Host smart-0b17016f-d340-418b-8e1d-3e3d9ae8b797
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=177897688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.177897688
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3673288492
Short name T197
Test name
Test status
Simulation time 336479170000 ps
CPU time 706.88 seconds
Started Jan 14 12:56:10 PM PST 24
Finished Jan 14 01:24:51 PM PST 24
Peak memory 160584 kb
Host smart-2165ffb7-4a74-433e-a091-dc0a2229aaa7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3673288492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3673288492
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3480281642
Short name T174
Test name
Test status
Simulation time 336770470000 ps
CPU time 762.38 seconds
Started Jan 14 12:56:10 PM PST 24
Finished Jan 14 01:26:25 PM PST 24
Peak memory 160484 kb
Host smart-58dc1b80-dabf-4de7-a5ef-0b6cdad64baa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3480281642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3480281642
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1077575037
Short name T181
Test name
Test status
Simulation time 336897830000 ps
CPU time 877.31 seconds
Started Jan 14 12:56:11 PM PST 24
Finished Jan 14 01:31:02 PM PST 24
Peak memory 160484 kb
Host smart-0d86f23e-9027-43c9-85de-6660248425f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1077575037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1077575037
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3061425137
Short name T169
Test name
Test status
Simulation time 336359010000 ps
CPU time 645.99 seconds
Started Jan 14 12:56:14 PM PST 24
Finished Jan 14 01:22:51 PM PST 24
Peak memory 160580 kb
Host smart-7a972a08-7672-44a2-9c1c-afdbf8dc9fe1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3061425137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3061425137
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.734857414
Short name T37
Test name
Test status
Simulation time 336749050000 ps
CPU time 915.21 seconds
Started Jan 14 12:56:20 PM PST 24
Finished Jan 14 01:33:36 PM PST 24
Peak memory 160512 kb
Host smart-fb8d0dc4-2c14-4c37-851d-ec53e58cfe11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=734857414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.734857414
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.672707470
Short name T109
Test name
Test status
Simulation time 336368190000 ps
CPU time 725.97 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 01:23:52 PM PST 24
Peak memory 160988 kb
Host smart-fc0ca4d2-de99-4276-b466-297b40411cb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=672707470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.672707470
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2686287365
Short name T17
Test name
Test status
Simulation time 336357630000 ps
CPU time 745.95 seconds
Started Jan 14 12:54:28 PM PST 24
Finished Jan 14 01:24:38 PM PST 24
Peak memory 160984 kb
Host smart-4eaa69ed-def4-46ea-a4be-1a554152eff6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2686287365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2686287365
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2067208922
Short name T108
Test name
Test status
Simulation time 336393590000 ps
CPU time 754.24 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 01:25:11 PM PST 24
Peak memory 160960 kb
Host smart-7f3654cc-5b0f-459a-ba38-dcc9b1eff097
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2067208922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2067208922
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3259308062
Short name T98
Test name
Test status
Simulation time 336557330000 ps
CPU time 927.84 seconds
Started Jan 14 12:54:32 PM PST 24
Finished Jan 14 01:31:54 PM PST 24
Peak memory 160976 kb
Host smart-aac3372a-ba6c-4828-9d15-275374bbf1bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3259308062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3259308062
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.647907793
Short name T21
Test name
Test status
Simulation time 336617510000 ps
CPU time 930.77 seconds
Started Jan 14 12:54:32 PM PST 24
Finished Jan 14 01:32:08 PM PST 24
Peak memory 160972 kb
Host smart-c92a7311-d60a-4d75-b3dd-ee0917f9fcc6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=647907793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.647907793
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.774264110
Short name T97
Test name
Test status
Simulation time 336535350000 ps
CPU time 704.29 seconds
Started Jan 14 12:54:38 PM PST 24
Finished Jan 14 01:23:22 PM PST 24
Peak memory 161052 kb
Host smart-2b61d3fd-8ec7-4ded-aee6-26c7ac0b6fac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=774264110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.774264110
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3612547764
Short name T118
Test name
Test status
Simulation time 336529010000 ps
CPU time 583.78 seconds
Started Jan 14 12:54:39 PM PST 24
Finished Jan 14 01:19:27 PM PST 24
Peak memory 161048 kb
Host smart-54ca818b-f77b-419a-a6c3-cc4ea0dc30e2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3612547764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3612547764
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2008501574
Short name T115
Test name
Test status
Simulation time 336530190000 ps
CPU time 603.66 seconds
Started Jan 14 12:54:36 PM PST 24
Finished Jan 14 01:19:53 PM PST 24
Peak memory 160928 kb
Host smart-143cc6d0-36b2-42f0-9430-9baf6b96a87e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2008501574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2008501574
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2912452646
Short name T106
Test name
Test status
Simulation time 337014990000 ps
CPU time 633.41 seconds
Started Jan 14 12:54:37 PM PST 24
Finished Jan 14 01:21:02 PM PST 24
Peak memory 160952 kb
Host smart-543f8235-1b6f-4eb5-babb-2ec3b1c49127
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2912452646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2912452646
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1226735285
Short name T105
Test name
Test status
Simulation time 336351370000 ps
CPU time 702.44 seconds
Started Jan 14 12:54:38 PM PST 24
Finished Jan 14 01:23:05 PM PST 24
Peak memory 160964 kb
Host smart-a503cd99-0965-456e-ac5f-bc58e63c0b4d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1226735285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1226735285
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3657200783
Short name T116
Test name
Test status
Simulation time 336714730000 ps
CPU time 802.75 seconds
Started Jan 14 12:54:37 PM PST 24
Finished Jan 14 01:26:53 PM PST 24
Peak memory 160900 kb
Host smart-a29eb50a-0dc2-4cc9-840c-43ab17a2942b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3657200783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3657200783
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3219697086
Short name T88
Test name
Test status
Simulation time 336520950000 ps
CPU time 622.08 seconds
Started Jan 14 12:54:28 PM PST 24
Finished Jan 14 01:20:27 PM PST 24
Peak memory 161016 kb
Host smart-a8a6b0de-51e4-4fd6-b58d-882160cd7ebc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3219697086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3219697086
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1781542715
Short name T112
Test name
Test status
Simulation time 336478490000 ps
CPU time 694.32 seconds
Started Jan 14 12:54:52 PM PST 24
Finished Jan 14 01:22:34 PM PST 24
Peak memory 161016 kb
Host smart-9deac211-94d6-4c85-8c60-19f79e0b66cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1781542715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1781542715
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2905541731
Short name T107
Test name
Test status
Simulation time 336976910000 ps
CPU time 739.01 seconds
Started Jan 14 12:54:53 PM PST 24
Finished Jan 14 01:24:34 PM PST 24
Peak memory 160984 kb
Host smart-134fa3a6-434d-4773-9974-2b6553fb590d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2905541731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2905541731
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3922391940
Short name T20
Test name
Test status
Simulation time 336736190000 ps
CPU time 743.38 seconds
Started Jan 14 12:54:53 PM PST 24
Finished Jan 14 01:25:08 PM PST 24
Peak memory 160920 kb
Host smart-a4bda7ed-ee40-40d7-b335-07980e75eff0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3922391940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3922391940
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3320336447
Short name T81
Test name
Test status
Simulation time 337067950000 ps
CPU time 817.35 seconds
Started Jan 14 12:54:52 PM PST 24
Finished Jan 14 01:27:54 PM PST 24
Peak memory 161020 kb
Host smart-4bf1adc9-4a6a-4b2b-b9ba-737282c2de58
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3320336447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3320336447
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4034280839
Short name T119
Test name
Test status
Simulation time 337012590000 ps
CPU time 670.37 seconds
Started Jan 14 12:54:52 PM PST 24
Finished Jan 14 01:22:20 PM PST 24
Peak memory 160980 kb
Host smart-eaef0bce-514f-4313-9ef4-efe9a82c3fc9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4034280839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.4034280839
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2453374537
Short name T82
Test name
Test status
Simulation time 336712370000 ps
CPU time 625.88 seconds
Started Jan 14 12:54:51 PM PST 24
Finished Jan 14 01:20:44 PM PST 24
Peak memory 161048 kb
Host smart-d9b70cd8-27ce-4ddf-bee9-a611fb94bbe8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2453374537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2453374537
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2621171760
Short name T103
Test name
Test status
Simulation time 336331490000 ps
CPU time 805.54 seconds
Started Jan 14 12:54:53 PM PST 24
Finished Jan 14 01:27:18 PM PST 24
Peak memory 160948 kb
Host smart-6f362974-a635-41ec-8538-36a74e677129
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2621171760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2621171760
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4106003557
Short name T93
Test name
Test status
Simulation time 336992010000 ps
CPU time 737.08 seconds
Started Jan 14 12:54:49 PM PST 24
Finished Jan 14 01:24:23 PM PST 24
Peak memory 160956 kb
Host smart-4ed2c465-b124-43cd-b12e-c9bc163e9df0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4106003557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4106003557
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.89359782
Short name T102
Test name
Test status
Simulation time 336869170000 ps
CPU time 667.79 seconds
Started Jan 14 12:54:52 PM PST 24
Finished Jan 14 01:22:30 PM PST 24
Peak memory 160940 kb
Host smart-69ca9ae2-164c-4012-9a06-db6af3819228
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=89359782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.89359782
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.40754935
Short name T89
Test name
Test status
Simulation time 336424450000 ps
CPU time 672.97 seconds
Started Jan 14 12:54:54 PM PST 24
Finished Jan 14 01:21:58 PM PST 24
Peak memory 160948 kb
Host smart-0302b967-a988-479a-a1f4-a11e48c75d6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=40754935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.40754935
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.811088650
Short name T96
Test name
Test status
Simulation time 336520890000 ps
CPU time 716.45 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 01:23:52 PM PST 24
Peak memory 161036 kb
Host smart-8f55901a-0fe7-4a34-8c20-e1e2b3e90ca0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=811088650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.811088650
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4193157333
Short name T95
Test name
Test status
Simulation time 336727710000 ps
CPU time 642.7 seconds
Started Jan 14 12:54:51 PM PST 24
Finished Jan 14 01:21:35 PM PST 24
Peak memory 160968 kb
Host smart-784f4f25-7f4f-499b-a8d5-59ede6c90c2f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4193157333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.4193157333
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2770447754
Short name T91
Test name
Test status
Simulation time 336993730000 ps
CPU time 676.08 seconds
Started Jan 14 12:54:55 PM PST 24
Finished Jan 14 01:22:44 PM PST 24
Peak memory 161068 kb
Host smart-2986eb5e-3067-4166-90c9-b15423c1cdac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2770447754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2770447754
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2928843691
Short name T18
Test name
Test status
Simulation time 336445910000 ps
CPU time 864.06 seconds
Started Jan 14 12:54:56 PM PST 24
Finished Jan 14 01:29:13 PM PST 24
Peak memory 161036 kb
Host smart-5e2638e6-f24e-4cd9-9149-b9e0939f3b69
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928843691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2928843691
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2072199281
Short name T101
Test name
Test status
Simulation time 336941730000 ps
CPU time 779.35 seconds
Started Jan 14 12:54:51 PM PST 24
Finished Jan 14 01:26:14 PM PST 24
Peak memory 161020 kb
Host smart-f8b21f7d-a6c2-4801-9d51-84b8f62cda95
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2072199281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2072199281
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.743331911
Short name T90
Test name
Test status
Simulation time 337060970000 ps
CPU time 725.53 seconds
Started Jan 14 12:54:52 PM PST 24
Finished Jan 14 01:24:13 PM PST 24
Peak memory 160968 kb
Host smart-687093cc-1dc3-43d4-b229-f0c62e8fe22a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=743331911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.743331911
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2831416223
Short name T120
Test name
Test status
Simulation time 336946750000 ps
CPU time 739.44 seconds
Started Jan 14 12:54:54 PM PST 24
Finished Jan 14 01:24:56 PM PST 24
Peak memory 161096 kb
Host smart-a5317744-7afd-4a21-bd58-9fe6921c533b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2831416223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2831416223
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1171107169
Short name T83
Test name
Test status
Simulation time 336656530000 ps
CPU time 559.91 seconds
Started Jan 14 12:54:54 PM PST 24
Finished Jan 14 01:18:07 PM PST 24
Peak memory 160944 kb
Host smart-9d0e5a1c-9fa6-4c2c-949c-5ec3ea14f719
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1171107169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1171107169
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.153416478
Short name T16
Test name
Test status
Simulation time 336797510000 ps
CPU time 821.05 seconds
Started Jan 14 12:54:54 PM PST 24
Finished Jan 14 01:28:12 PM PST 24
Peak memory 160936 kb
Host smart-4d437eaa-0b99-4940-9a45-575c98afcae2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=153416478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.153416478
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3760199401
Short name T94
Test name
Test status
Simulation time 336497950000 ps
CPU time 755.57 seconds
Started Jan 14 12:54:56 PM PST 24
Finished Jan 14 01:25:58 PM PST 24
Peak memory 160984 kb
Host smart-3cf94cdc-42c4-4cdb-ae43-9ec85cda257d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3760199401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3760199401
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3382378087
Short name T86
Test name
Test status
Simulation time 336685270000 ps
CPU time 693.37 seconds
Started Jan 14 12:54:53 PM PST 24
Finished Jan 14 01:22:31 PM PST 24
Peak memory 161016 kb
Host smart-f96bc872-1b4a-464e-a0d7-21ddfc617640
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3382378087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3382378087
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1865505241
Short name T22
Test name
Test status
Simulation time 336919910000 ps
CPU time 727.2 seconds
Started Jan 14 12:54:30 PM PST 24
Finished Jan 14 01:23:52 PM PST 24
Peak memory 160944 kb
Host smart-cf12f5c0-6f79-42b8-ab59-83696ee66fe2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1865505241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1865505241
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2640632895
Short name T92
Test name
Test status
Simulation time 336929690000 ps
CPU time 899.8 seconds
Started Jan 14 12:54:55 PM PST 24
Finished Jan 14 01:29:49 PM PST 24
Peak memory 160952 kb
Host smart-475ed351-4e10-4891-91ab-3ecd90b4d06a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2640632895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2640632895
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.813553424
Short name T117
Test name
Test status
Simulation time 336534990000 ps
CPU time 851.89 seconds
Started Jan 14 12:54:56 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 161028 kb
Host smart-0a2b68a1-76a7-4aeb-a127-3225094b921c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=813553424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.813553424
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2937020451
Short name T14
Test name
Test status
Simulation time 336624710000 ps
CPU time 571.16 seconds
Started Jan 14 12:54:53 PM PST 24
Finished Jan 14 01:19:09 PM PST 24
Peak memory 160944 kb
Host smart-426e4712-079b-41b5-bf69-ba6d91422041
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2937020451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2937020451
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.88675807
Short name T19
Test name
Test status
Simulation time 336473470000 ps
CPU time 831.43 seconds
Started Jan 14 12:54:53 PM PST 24
Finished Jan 14 01:28:24 PM PST 24
Peak memory 160920 kb
Host smart-67f99ba0-f89d-4511-81c9-45bb714906af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=88675807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.88675807
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.593790541
Short name T87
Test name
Test status
Simulation time 336390190000 ps
CPU time 758.64 seconds
Started Jan 14 12:55:01 PM PST 24
Finished Jan 14 01:25:46 PM PST 24
Peak memory 160976 kb
Host smart-3f1a92f4-ae1b-4ee2-9de4-4c7f6cb99ea7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=593790541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.593790541
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1052691407
Short name T84
Test name
Test status
Simulation time 336828570000 ps
CPU time 722.41 seconds
Started Jan 14 12:55:01 PM PST 24
Finished Jan 14 01:24:10 PM PST 24
Peak memory 161020 kb
Host smart-d5e5a618-df20-4ee0-9776-8f74d49710c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1052691407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1052691407
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.565211049
Short name T99
Test name
Test status
Simulation time 336929850000 ps
CPU time 686.16 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 01:23:10 PM PST 24
Peak memory 161024 kb
Host smart-a8be8e5b-872a-495c-8b7e-b99abc7626bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=565211049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.565211049
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1420122694
Short name T104
Test name
Test status
Simulation time 336456490000 ps
CPU time 705.89 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 01:23:45 PM PST 24
Peak memory 161028 kb
Host smart-8735c556-5f43-4a5f-93aa-22198dcea08a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1420122694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1420122694
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.375965302
Short name T110
Test name
Test status
Simulation time 336921790000 ps
CPU time 955.11 seconds
Started Jan 14 12:55:07 PM PST 24
Finished Jan 14 01:33:31 PM PST 24
Peak memory 160940 kb
Host smart-91d923b6-2a83-4a47-94b2-979d8ed22fb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=375965302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.375965302
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2431310046
Short name T113
Test name
Test status
Simulation time 336725950000 ps
CPU time 709.11 seconds
Started Jan 14 12:55:04 PM PST 24
Finished Jan 14 01:23:45 PM PST 24
Peak memory 160964 kb
Host smart-1da94b24-1e03-435b-9660-f198310c7dbd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2431310046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2431310046
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3336924502
Short name T85
Test name
Test status
Simulation time 336997410000 ps
CPU time 780.81 seconds
Started Jan 14 12:54:28 PM PST 24
Finished Jan 14 01:25:51 PM PST 24
Peak memory 160972 kb
Host smart-483e693a-4b55-4c36-bcae-c1e0d18c7740
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3336924502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3336924502
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3255598467
Short name T100
Test name
Test status
Simulation time 336486190000 ps
CPU time 672.59 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 01:21:46 PM PST 24
Peak memory 161004 kb
Host smart-c3ca24ba-a81e-4b91-9857-fb9452aa6225
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3255598467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3255598467
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1526494923
Short name T111
Test name
Test status
Simulation time 336454150000 ps
CPU time 831.96 seconds
Started Jan 14 12:54:28 PM PST 24
Finished Jan 14 01:28:00 PM PST 24
Peak memory 161008 kb
Host smart-e12ea6b3-b200-46a5-8fbc-35777bb9c1f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526494923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1526494923
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.390664901
Short name T15
Test name
Test status
Simulation time 336962470000 ps
CPU time 768.97 seconds
Started Jan 14 12:54:27 PM PST 24
Finished Jan 14 01:25:41 PM PST 24
Peak memory 161052 kb
Host smart-812b6423-bb45-47e8-ae87-cacd5659fc8e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=390664901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.390664901
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1046567681
Short name T114
Test name
Test status
Simulation time 336951770000 ps
CPU time 628.65 seconds
Started Jan 14 12:54:26 PM PST 24
Finished Jan 14 01:20:36 PM PST 24
Peak memory 161044 kb
Host smart-db4f6c0e-2303-4142-a5f2-915e09229923
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1046567681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1046567681
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.528234331
Short name T149
Test name
Test status
Simulation time 1374110000 ps
CPU time 4.11 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 12:55:12 PM PST 24
Peak memory 156168 kb
Host smart-788fd127-9faa-4e19-bab2-5af8c188bd68
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=528234331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.528234331
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3460101786
Short name T4
Test name
Test status
Simulation time 1361650000 ps
CPU time 3.88 seconds
Started Jan 14 12:55:05 PM PST 24
Finished Jan 14 12:55:14 PM PST 24
Peak memory 156188 kb
Host smart-1646e534-a95e-47b8-a745-b469dad3a43e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3460101786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3460101786
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.141042170
Short name T6
Test name
Test status
Simulation time 1398310000 ps
CPU time 4.92 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 12:55:15 PM PST 24
Peak memory 156220 kb
Host smart-7ba3da1a-ace3-44a2-9202-6b40a57560c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=141042170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.141042170
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1011171362
Short name T5
Test name
Test status
Simulation time 1338150000 ps
CPU time 4.62 seconds
Started Jan 14 12:55:07 PM PST 24
Finished Jan 14 12:55:17 PM PST 24
Peak memory 156180 kb
Host smart-61dc7153-fbb7-49c9-a4cb-9890c5b3959a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1011171362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1011171362
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4169964496
Short name T28
Test name
Test status
Simulation time 1409710000 ps
CPU time 3.32 seconds
Started Jan 14 12:55:04 PM PST 24
Finished Jan 14 12:55:12 PM PST 24
Peak memory 156212 kb
Host smart-56407300-92f7-4d85-a5cc-e37a7ef22bee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4169964496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4169964496
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.808968832
Short name T160
Test name
Test status
Simulation time 1343830000 ps
CPU time 4.8 seconds
Started Jan 14 12:55:10 PM PST 24
Finished Jan 14 12:55:22 PM PST 24
Peak memory 156172 kb
Host smart-03cf2dcd-e383-4218-b1a0-a9d5b113c018
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=808968832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.808968832
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.553661176
Short name T124
Test name
Test status
Simulation time 1480010000 ps
CPU time 3.57 seconds
Started Jan 14 12:55:10 PM PST 24
Finished Jan 14 12:55:18 PM PST 24
Peak memory 156264 kb
Host smart-ac756807-e2ec-405e-8888-34296a15bcdc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553661176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.553661176
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1918946599
Short name T147
Test name
Test status
Simulation time 1422570000 ps
CPU time 4.28 seconds
Started Jan 14 12:55:12 PM PST 24
Finished Jan 14 12:55:22 PM PST 24
Peak memory 156188 kb
Host smart-f51abede-7d95-4516-8c8c-0f30ed27e633
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1918946599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1918946599
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.933554101
Short name T143
Test name
Test status
Simulation time 1538150000 ps
CPU time 3.95 seconds
Started Jan 14 12:55:10 PM PST 24
Finished Jan 14 12:55:19 PM PST 24
Peak memory 156164 kb
Host smart-ecfba76d-de79-4f0e-973b-5767bac37450
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933554101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.933554101
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1596021115
Short name T145
Test name
Test status
Simulation time 1546170000 ps
CPU time 4.84 seconds
Started Jan 14 12:55:19 PM PST 24
Finished Jan 14 12:55:30 PM PST 24
Peak memory 156188 kb
Host smart-780aeb80-f245-47d5-b1f3-0d802a80bd0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1596021115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1596021115
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2190681589
Short name T155
Test name
Test status
Simulation time 1357010000 ps
CPU time 3.57 seconds
Started Jan 14 12:55:20 PM PST 24
Finished Jan 14 12:55:28 PM PST 24
Peak memory 156196 kb
Host smart-e4faa235-30e3-472a-b2af-73afc9e62d91
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2190681589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2190681589
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2285673666
Short name T140
Test name
Test status
Simulation time 1410190000 ps
CPU time 3.43 seconds
Started Jan 14 12:55:00 PM PST 24
Finished Jan 14 12:55:09 PM PST 24
Peak memory 156272 kb
Host smart-90a9ee25-24a2-4e4f-b940-25285ce2409a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2285673666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2285673666
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.531037874
Short name T153
Test name
Test status
Simulation time 1247810000 ps
CPU time 3.95 seconds
Started Jan 14 12:55:19 PM PST 24
Finished Jan 14 12:55:28 PM PST 24
Peak memory 156256 kb
Host smart-f2e4ead6-8987-4ad7-a11b-4a9331dce70c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=531037874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.531037874
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3451584454
Short name T127
Test name
Test status
Simulation time 1501590000 ps
CPU time 3.71 seconds
Started Jan 14 12:55:17 PM PST 24
Finished Jan 14 12:55:26 PM PST 24
Peak memory 156160 kb
Host smart-b8d70381-74f8-4590-b569-b80e3811e239
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3451584454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3451584454
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1747081802
Short name T139
Test name
Test status
Simulation time 1104270000 ps
CPU time 3.1 seconds
Started Jan 14 12:55:19 PM PST 24
Finished Jan 14 12:55:26 PM PST 24
Peak memory 156236 kb
Host smart-13c8c435-5d22-400d-a8be-693e2d545f43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747081802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1747081802
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.801434913
Short name T26
Test name
Test status
Simulation time 1494810000 ps
CPU time 3.71 seconds
Started Jan 14 12:55:19 PM PST 24
Finished Jan 14 12:55:27 PM PST 24
Peak memory 156168 kb
Host smart-b86d4eb0-5d43-40de-bd96-2682136957eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=801434913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.801434913
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.533548794
Short name T128
Test name
Test status
Simulation time 1388010000 ps
CPU time 3.89 seconds
Started Jan 14 12:55:29 PM PST 24
Finished Jan 14 12:55:38 PM PST 24
Peak memory 156228 kb
Host smart-474e35ce-35be-4643-8767-f6824ef5304d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=533548794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.533548794
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.511185432
Short name T131
Test name
Test status
Simulation time 1370270000 ps
CPU time 3.68 seconds
Started Jan 14 12:55:30 PM PST 24
Finished Jan 14 12:55:39 PM PST 24
Peak memory 156204 kb
Host smart-a4721705-fde5-41a9-aae2-f08e6d747329
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=511185432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.511185432
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3229969382
Short name T30
Test name
Test status
Simulation time 1444930000 ps
CPU time 3.7 seconds
Started Jan 14 12:55:31 PM PST 24
Finished Jan 14 12:55:40 PM PST 24
Peak memory 156168 kb
Host smart-373845b9-b4be-4c76-a00b-7d1f365c9fea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3229969382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3229969382
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3961855391
Short name T29
Test name
Test status
Simulation time 1568950000 ps
CPU time 5.26 seconds
Started Jan 14 12:55:31 PM PST 24
Finished Jan 14 12:55:43 PM PST 24
Peak memory 156136 kb
Host smart-1a38fa58-2173-4d2d-98fe-0fdab29517fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3961855391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3961855391
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1565902276
Short name T132
Test name
Test status
Simulation time 1390670000 ps
CPU time 3.66 seconds
Started Jan 14 12:55:31 PM PST 24
Finished Jan 14 12:55:39 PM PST 24
Peak memory 156152 kb
Host smart-cc0b5f49-7e29-44b4-838d-13d3d47926d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1565902276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1565902276
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2010368268
Short name T141
Test name
Test status
Simulation time 1401070000 ps
CPU time 3.65 seconds
Started Jan 14 12:55:39 PM PST 24
Finished Jan 14 12:55:47 PM PST 24
Peak memory 156156 kb
Host smart-8980aa7f-86c3-4847-a925-3ae4e15b3280
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2010368268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2010368268
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1059407931
Short name T150
Test name
Test status
Simulation time 1486850000 ps
CPU time 4.69 seconds
Started Jan 14 12:55:06 PM PST 24
Finished Jan 14 12:55:17 PM PST 24
Peak memory 156240 kb
Host smart-8ec33c42-c26d-410a-9305-fc69d302b96a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1059407931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1059407931
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1629695451
Short name T123
Test name
Test status
Simulation time 1408710000 ps
CPU time 3.52 seconds
Started Jan 14 12:55:37 PM PST 24
Finished Jan 14 12:55:45 PM PST 24
Peak memory 156160 kb
Host smart-1cbbae97-d453-4924-8a61-eb050dc2426e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1629695451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1629695451
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1888733634
Short name T121
Test name
Test status
Simulation time 1457570000 ps
CPU time 3.36 seconds
Started Jan 14 12:55:36 PM PST 24
Finished Jan 14 12:55:44 PM PST 24
Peak memory 156244 kb
Host smart-1d1c9b19-720b-4422-9c6a-9a006f73710f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1888733634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1888733634
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3002868013
Short name T130
Test name
Test status
Simulation time 1487670000 ps
CPU time 5.72 seconds
Started Jan 14 12:55:36 PM PST 24
Finished Jan 14 12:55:48 PM PST 24
Peak memory 156220 kb
Host smart-26dc14bc-87bc-40c9-9067-1256c6ca45a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3002868013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3002868013
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3823181227
Short name T156
Test name
Test status
Simulation time 1496130000 ps
CPU time 3.11 seconds
Started Jan 14 12:55:36 PM PST 24
Finished Jan 14 12:55:43 PM PST 24
Peak memory 156176 kb
Host smart-c149f5f0-a63a-4c59-8703-edf1218afdb7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3823181227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3823181227
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2512502694
Short name T125
Test name
Test status
Simulation time 1501030000 ps
CPU time 4.1 seconds
Started Jan 14 12:55:44 PM PST 24
Finished Jan 14 12:55:54 PM PST 24
Peak memory 156144 kb
Host smart-84706fe7-0c6d-4c13-9fef-63040d748c28
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512502694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2512502694
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.627692421
Short name T154
Test name
Test status
Simulation time 1530410000 ps
CPU time 3.68 seconds
Started Jan 14 12:55:45 PM PST 24
Finished Jan 14 12:55:55 PM PST 24
Peak memory 156256 kb
Host smart-9212bd64-2ace-4c83-9667-9e6bafdecee6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=627692421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.627692421
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1582228888
Short name T142
Test name
Test status
Simulation time 1359030000 ps
CPU time 5.1 seconds
Started Jan 14 12:55:54 PM PST 24
Finished Jan 14 12:56:05 PM PST 24
Peak memory 156188 kb
Host smart-1c600961-527a-4cd2-8fe8-75d4d9f2f891
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1582228888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1582228888
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3239811409
Short name T126
Test name
Test status
Simulation time 1321970000 ps
CPU time 3.78 seconds
Started Jan 14 12:55:55 PM PST 24
Finished Jan 14 12:56:04 PM PST 24
Peak memory 156188 kb
Host smart-abc17654-d118-439d-ac02-12998128310c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3239811409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3239811409
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2858326546
Short name T122
Test name
Test status
Simulation time 1393550000 ps
CPU time 3.12 seconds
Started Jan 14 12:56:11 PM PST 24
Finished Jan 14 12:56:18 PM PST 24
Peak memory 156232 kb
Host smart-824d5391-0baf-4034-b963-d6c3c509f35f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2858326546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2858326546
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1108834954
Short name T136
Test name
Test status
Simulation time 1553230000 ps
CPU time 4.17 seconds
Started Jan 14 12:56:07 PM PST 24
Finished Jan 14 12:56:17 PM PST 24
Peak memory 156236 kb
Host smart-e2379365-81b5-46e7-b3ff-14e68f2d3532
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1108834954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1108834954
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3436773293
Short name T159
Test name
Test status
Simulation time 1588770000 ps
CPU time 4.58 seconds
Started Jan 14 12:55:03 PM PST 24
Finished Jan 14 12:55:15 PM PST 24
Peak memory 156192 kb
Host smart-8089d6db-73b5-45aa-8c1c-d363360effe9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3436773293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3436773293
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3773383976
Short name T146
Test name
Test status
Simulation time 1562190000 ps
CPU time 4.92 seconds
Started Jan 14 12:56:15 PM PST 24
Finished Jan 14 12:56:26 PM PST 24
Peak memory 156220 kb
Host smart-958abf8d-d8ec-42fb-9370-7e317c493c8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773383976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3773383976
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3243451288
Short name T24
Test name
Test status
Simulation time 1203930000 ps
CPU time 3.13 seconds
Started Jan 14 12:56:10 PM PST 24
Finished Jan 14 12:56:17 PM PST 24
Peak memory 156136 kb
Host smart-e2a9e28e-8908-48c1-8e25-26bc67b5e584
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3243451288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3243451288
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.578991956
Short name T152
Test name
Test status
Simulation time 1504310000 ps
CPU time 4.38 seconds
Started Jan 14 12:56:08 PM PST 24
Finished Jan 14 12:56:18 PM PST 24
Peak memory 156196 kb
Host smart-acfc0cec-191b-4238-9a40-76870ac35a35
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=578991956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.578991956
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.55314505
Short name T151
Test name
Test status
Simulation time 1260650000 ps
CPU time 3.19 seconds
Started Jan 14 12:56:07 PM PST 24
Finished Jan 14 12:56:14 PM PST 24
Peak memory 156160 kb
Host smart-7174c686-20fc-410b-b1fb-e29741e10ae5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=55314505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.55314505
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.840433827
Short name T135
Test name
Test status
Simulation time 1337550000 ps
CPU time 3.77 seconds
Started Jan 14 12:56:07 PM PST 24
Finished Jan 14 12:56:16 PM PST 24
Peak memory 156172 kb
Host smart-0c825128-5a62-49f6-b82d-a8708025bbda
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840433827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.840433827
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3269521307
Short name T129
Test name
Test status
Simulation time 1572190000 ps
CPU time 3.84 seconds
Started Jan 14 12:56:07 PM PST 24
Finished Jan 14 12:56:16 PM PST 24
Peak memory 156224 kb
Host smart-2a2de017-9cc3-4957-aa86-6d0e6e20d4b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3269521307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3269521307
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1394859480
Short name T134
Test name
Test status
Simulation time 1465270000 ps
CPU time 3.14 seconds
Started Jan 14 12:56:06 PM PST 24
Finished Jan 14 12:56:14 PM PST 24
Peak memory 156220 kb
Host smart-ebe6e935-c2e0-4ea6-96dd-9b3363e8fc87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394859480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1394859480
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2757753392
Short name T144
Test name
Test status
Simulation time 1295770000 ps
CPU time 3.28 seconds
Started Jan 14 12:56:07 PM PST 24
Finished Jan 14 12:56:15 PM PST 24
Peak memory 156212 kb
Host smart-f85ec7cf-4176-45a9-be4e-4ca2e4752bef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757753392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2757753392
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3054754009
Short name T157
Test name
Test status
Simulation time 1555090000 ps
CPU time 4.68 seconds
Started Jan 14 12:56:18 PM PST 24
Finished Jan 14 12:56:29 PM PST 24
Peak memory 156200 kb
Host smart-5f9cc067-de52-418c-a408-a70d706a69d1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054754009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3054754009
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2175264848
Short name T133
Test name
Test status
Simulation time 1460370000 ps
CPU time 3.76 seconds
Started Jan 14 12:56:09 PM PST 24
Finished Jan 14 12:56:18 PM PST 24
Peak memory 156236 kb
Host smart-88bef775-af1b-4214-9ce1-f107f3e697f3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2175264848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2175264848
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1008323224
Short name T158
Test name
Test status
Simulation time 1545950000 ps
CPU time 4.15 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 12:55:12 PM PST 24
Peak memory 156252 kb
Host smart-e03cc7a4-165d-4ee4-908f-9d3e4cd0ceff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008323224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1008323224
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.952162425
Short name T137
Test name
Test status
Simulation time 1475110000 ps
CPU time 3.24 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 12:55:11 PM PST 24
Peak memory 156172 kb
Host smart-f005e515-9742-4ae5-9e70-9931040e6951
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=952162425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.952162425
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1332555330
Short name T148
Test name
Test status
Simulation time 1489330000 ps
CPU time 4.9 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 12:55:15 PM PST 24
Peak memory 156192 kb
Host smart-beaa0d2e-0d12-4161-9d44-ca5e552310b9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332555330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1332555330
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4032122314
Short name T138
Test name
Test status
Simulation time 1538890000 ps
CPU time 3.83 seconds
Started Jan 14 12:55:03 PM PST 24
Finished Jan 14 12:55:13 PM PST 24
Peak memory 156256 kb
Host smart-21c67485-bace-47f6-b1d7-73760ce0c37b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4032122314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.4032122314
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1796889696
Short name T25
Test name
Test status
Simulation time 1417910000 ps
CPU time 3.94 seconds
Started Jan 14 12:55:02 PM PST 24
Finished Jan 14 12:55:12 PM PST 24
Peak memory 156212 kb
Host smart-4ff657cb-a644-4b52-87db-87aa3ded5e4c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1796889696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1796889696
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2437690382
Short name T54
Test name
Test status
Simulation time 1401530000 ps
CPU time 3.39 seconds
Started Jan 14 12:57:01 PM PST 24
Finished Jan 14 12:57:09 PM PST 24
Peak memory 155848 kb
Host smart-2be69eb4-1a94-46db-ade0-2f2ded423777
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2437690382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2437690382
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1138072270
Short name T73
Test name
Test status
Simulation time 1439650000 ps
CPU time 3.58 seconds
Started Jan 14 12:57:02 PM PST 24
Finished Jan 14 12:57:11 PM PST 24
Peak memory 155792 kb
Host smart-d7d2ae19-c4ec-416c-b15d-a56f37657f8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138072270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1138072270
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1465886922
Short name T70
Test name
Test status
Simulation time 1316530000 ps
CPU time 4.06 seconds
Started Jan 14 12:57:01 PM PST 24
Finished Jan 14 12:57:11 PM PST 24
Peak memory 155796 kb
Host smart-ea4f6c34-d150-49eb-82b3-bd1fe4763016
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1465886922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1465886922
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2586708724
Short name T64
Test name
Test status
Simulation time 1295170000 ps
CPU time 3.17 seconds
Started Jan 14 12:57:01 PM PST 24
Finished Jan 14 12:57:08 PM PST 24
Peak memory 155812 kb
Host smart-ef908f89-ca4a-49b8-8b40-8321349fa363
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2586708724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2586708724
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3156543390
Short name T43
Test name
Test status
Simulation time 1458030000 ps
CPU time 4.23 seconds
Started Jan 14 12:57:03 PM PST 24
Finished Jan 14 12:57:13 PM PST 24
Peak memory 155796 kb
Host smart-95815fc8-bad5-466e-832c-9c9f407def97
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3156543390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3156543390
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2330598523
Short name T60
Test name
Test status
Simulation time 1559530000 ps
CPU time 4.02 seconds
Started Jan 14 12:57:01 PM PST 24
Finished Jan 14 12:57:11 PM PST 24
Peak memory 155808 kb
Host smart-4faffc36-af5a-4892-aad0-71f4657f47d1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2330598523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2330598523
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1919377959
Short name T46
Test name
Test status
Simulation time 1484610000 ps
CPU time 3.99 seconds
Started Jan 14 12:57:10 PM PST 24
Finished Jan 14 12:57:28 PM PST 24
Peak memory 155680 kb
Host smart-4956837a-3ab4-4a53-b99f-280c75f2ce31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1919377959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1919377959
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3938302085
Short name T78
Test name
Test status
Simulation time 1442670000 ps
CPU time 3.72 seconds
Started Jan 14 12:57:08 PM PST 24
Finished Jan 14 12:57:17 PM PST 24
Peak memory 155652 kb
Host smart-cd141d1a-aed9-485c-8e1b-15b511fa16d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3938302085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3938302085
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.477466442
Short name T74
Test name
Test status
Simulation time 1313710000 ps
CPU time 3.82 seconds
Started Jan 14 12:57:08 PM PST 24
Finished Jan 14 12:57:25 PM PST 24
Peak memory 155692 kb
Host smart-c476f293-fae0-47f5-a9f3-0994ee693156
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477466442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.477466442
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2672222548
Short name T59
Test name
Test status
Simulation time 1525310000 ps
CPU time 3.46 seconds
Started Jan 14 12:57:07 PM PST 24
Finished Jan 14 12:57:15 PM PST 24
Peak memory 155716 kb
Host smart-8a639fb2-b414-48ce-9149-2c788c8a7e9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2672222548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2672222548
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2567560364
Short name T58
Test name
Test status
Simulation time 1306030000 ps
CPU time 4.53 seconds
Started Jan 14 12:57:08 PM PST 24
Finished Jan 14 12:57:19 PM PST 24
Peak memory 155744 kb
Host smart-0276ba3c-68a1-4faf-aa9b-269c166c4593
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2567560364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2567560364
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1979392028
Short name T79
Test name
Test status
Simulation time 1530450000 ps
CPU time 3.84 seconds
Started Jan 14 12:57:00 PM PST 24
Finished Jan 14 12:57:09 PM PST 24
Peak memory 155804 kb
Host smart-763107ef-6e46-4096-82aa-bac7787efed7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979392028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1979392028
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.456043639
Short name T42
Test name
Test status
Simulation time 1573670000 ps
CPU time 4.31 seconds
Started Jan 14 12:57:25 PM PST 24
Finished Jan 14 12:57:39 PM PST 24
Peak memory 155768 kb
Host smart-a6fc6d78-bc6d-44e8-bda9-a7fbba401e9d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=456043639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.456043639
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.374223297
Short name T77
Test name
Test status
Simulation time 1601430000 ps
CPU time 5.4 seconds
Started Jan 14 12:57:31 PM PST 24
Finished Jan 14 12:57:44 PM PST 24
Peak memory 155696 kb
Host smart-ac96ef43-fe05-4d47-94fd-d31bf340b996
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=374223297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.374223297
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3226658481
Short name T75
Test name
Test status
Simulation time 1569170000 ps
CPU time 4.18 seconds
Started Jan 14 12:57:25 PM PST 24
Finished Jan 14 12:57:38 PM PST 24
Peak memory 155740 kb
Host smart-cc5b9923-4c8a-4b04-a771-cc663a1a8d61
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226658481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3226658481
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3275254333
Short name T9
Test name
Test status
Simulation time 1420310000 ps
CPU time 3.44 seconds
Started Jan 14 12:57:29 PM PST 24
Finished Jan 14 12:57:37 PM PST 24
Peak memory 155728 kb
Host smart-509a50a1-aafd-4efe-bb0a-9001b995bb0c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275254333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3275254333
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2987031838
Short name T12
Test name
Test status
Simulation time 1389910000 ps
CPU time 4.59 seconds
Started Jan 14 12:57:28 PM PST 24
Finished Jan 14 12:57:40 PM PST 24
Peak memory 155784 kb
Host smart-c9cbbe49-aeab-4901-8a29-77ae04f36025
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2987031838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2987031838
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.138290688
Short name T80
Test name
Test status
Simulation time 1462710000 ps
CPU time 4.31 seconds
Started Jan 14 12:57:30 PM PST 24
Finished Jan 14 12:57:40 PM PST 24
Peak memory 155764 kb
Host smart-be12f81d-e8e8-40d9-8c42-e1594b6d3f7c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=138290688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.138290688
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.461559693
Short name T61
Test name
Test status
Simulation time 1587790000 ps
CPU time 5.4 seconds
Started Jan 14 12:57:30 PM PST 24
Finished Jan 14 12:57:43 PM PST 24
Peak memory 155732 kb
Host smart-42ba8240-6474-468f-bc40-ed3704b9e0b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461559693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.461559693
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1718809652
Short name T66
Test name
Test status
Simulation time 1567910000 ps
CPU time 5.28 seconds
Started Jan 14 12:57:31 PM PST 24
Finished Jan 14 12:57:43 PM PST 24
Peak memory 155756 kb
Host smart-49f88020-9c51-468a-83e9-7877761f3107
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1718809652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1718809652
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1874038196
Short name T41
Test name
Test status
Simulation time 1150510000 ps
CPU time 2.69 seconds
Started Jan 14 12:57:30 PM PST 24
Finished Jan 14 12:57:36 PM PST 24
Peak memory 155724 kb
Host smart-8365daa6-5ef3-4fef-9be3-af2c427c5c73
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1874038196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1874038196
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2796551732
Short name T44
Test name
Test status
Simulation time 1536210000 ps
CPU time 5.4 seconds
Started Jan 14 12:57:27 PM PST 24
Finished Jan 14 12:57:41 PM PST 24
Peak memory 155708 kb
Host smart-d6c2392c-d4d1-4435-9a6e-bddb72581ff6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2796551732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2796551732
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2950293040
Short name T50
Test name
Test status
Simulation time 1549290000 ps
CPU time 4.14 seconds
Started Jan 14 12:57:00 PM PST 24
Finished Jan 14 12:57:10 PM PST 24
Peak memory 155788 kb
Host smart-7ab3d53f-df69-4da4-8019-4fedfac041bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2950293040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2950293040
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2163702213
Short name T49
Test name
Test status
Simulation time 1588390000 ps
CPU time 3.98 seconds
Started Jan 14 12:57:34 PM PST 24
Finished Jan 14 12:57:43 PM PST 24
Peak memory 155792 kb
Host smart-d32bc8d0-b58f-45a9-8b15-1887580df447
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2163702213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2163702213
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.320411278
Short name T56
Test name
Test status
Simulation time 1483530000 ps
CPU time 3.77 seconds
Started Jan 14 12:57:33 PM PST 24
Finished Jan 14 12:57:42 PM PST 24
Peak memory 155748 kb
Host smart-0df94ffa-9e43-401c-a1e0-99768bc17567
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=320411278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.320411278
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1299636794
Short name T63
Test name
Test status
Simulation time 1631470000 ps
CPU time 4.43 seconds
Started Jan 14 12:57:33 PM PST 24
Finished Jan 14 12:57:43 PM PST 24
Peak memory 155792 kb
Host smart-8e2163a0-8213-42d2-b3ee-d15133113bdd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1299636794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1299636794
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3982765535
Short name T10
Test name
Test status
Simulation time 1468410000 ps
CPU time 4.55 seconds
Started Jan 14 12:57:40 PM PST 24
Finished Jan 14 12:57:50 PM PST 24
Peak memory 155728 kb
Host smart-6a07d53b-2d48-4ae1-9904-67e0716ff356
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3982765535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3982765535
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.867453220
Short name T55
Test name
Test status
Simulation time 1415130000 ps
CPU time 4.46 seconds
Started Jan 14 12:57:40 PM PST 24
Finished Jan 14 12:57:51 PM PST 24
Peak memory 155768 kb
Host smart-85c0a0af-3b7d-43f2-82f4-56effb3d16d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=867453220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.867453220
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.648056372
Short name T76
Test name
Test status
Simulation time 1480750000 ps
CPU time 3.91 seconds
Started Jan 14 12:57:41 PM PST 24
Finished Jan 14 12:57:50 PM PST 24
Peak memory 155736 kb
Host smart-6edc66ac-dd01-4d57-9b69-8b21551fc422
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=648056372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.648056372
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.452043773
Short name T68
Test name
Test status
Simulation time 1504830000 ps
CPU time 3.51 seconds
Started Jan 14 12:57:40 PM PST 24
Finished Jan 14 12:57:48 PM PST 24
Peak memory 155808 kb
Host smart-2429ab57-8e88-427c-bcf6-44c9c04b2275
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=452043773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.452043773
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2662588506
Short name T53
Test name
Test status
Simulation time 1455470000 ps
CPU time 3.64 seconds
Started Jan 14 12:57:41 PM PST 24
Finished Jan 14 12:57:49 PM PST 24
Peak memory 155808 kb
Host smart-71c34423-f955-4723-a5b8-fe9611b30f56
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2662588506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2662588506
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3244996560
Short name T45
Test name
Test status
Simulation time 1496830000 ps
CPU time 4.68 seconds
Started Jan 14 12:57:52 PM PST 24
Finished Jan 14 12:58:02 PM PST 24
Peak memory 155732 kb
Host smart-f60c85dd-1423-45a0-b2ed-4f4faaf33138
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3244996560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3244996560
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1074832449
Short name T52
Test name
Test status
Simulation time 1476810000 ps
CPU time 4.92 seconds
Started Jan 14 12:57:51 PM PST 24
Finished Jan 14 12:58:02 PM PST 24
Peak memory 155756 kb
Host smart-41455449-ada0-4e6f-840a-b30f3ccd1ceb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074832449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1074832449
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2444196462
Short name T3
Test name
Test status
Simulation time 1595190000 ps
CPU time 3.85 seconds
Started Jan 14 12:57:01 PM PST 24
Finished Jan 14 12:57:10 PM PST 24
Peak memory 155840 kb
Host smart-80df45fa-5235-46c5-8ce2-8be0fe40d422
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2444196462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2444196462
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1532970170
Short name T48
Test name
Test status
Simulation time 1556310000 ps
CPU time 3.73 seconds
Started Jan 14 12:57:50 PM PST 24
Finished Jan 14 12:57:59 PM PST 24
Peak memory 155764 kb
Host smart-bb34f1e5-94df-40b6-8cf2-ba619d318595
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532970170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1532970170
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2727465717
Short name T65
Test name
Test status
Simulation time 1490370000 ps
CPU time 5.49 seconds
Started Jan 14 12:57:50 PM PST 24
Finished Jan 14 12:58:03 PM PST 24
Peak memory 155732 kb
Host smart-9ca5f40b-e606-43f3-81ad-96008d647c1c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2727465717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2727465717
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.794745455
Short name T62
Test name
Test status
Simulation time 1550850000 ps
CPU time 5.78 seconds
Started Jan 14 12:57:50 PM PST 24
Finished Jan 14 12:58:03 PM PST 24
Peak memory 155808 kb
Host smart-81abb027-9698-42f5-afc9-31e1cba59f2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=794745455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.794745455
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3220249901
Short name T51
Test name
Test status
Simulation time 1586390000 ps
CPU time 3.81 seconds
Started Jan 14 12:57:56 PM PST 24
Finished Jan 14 12:58:05 PM PST 24
Peak memory 155812 kb
Host smart-ad2b593e-4a3b-43d8-b9ac-821e5f66d979
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3220249901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3220249901
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1196655982
Short name T47
Test name
Test status
Simulation time 1367170000 ps
CPU time 5.15 seconds
Started Jan 14 12:57:55 PM PST 24
Finished Jan 14 12:58:07 PM PST 24
Peak memory 155656 kb
Host smart-eaaa6e6e-c552-4792-bdf0-484e9e0fdceb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1196655982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1196655982
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2842067646
Short name T69
Test name
Test status
Simulation time 1536550000 ps
CPU time 4.56 seconds
Started Jan 14 12:57:57 PM PST 24
Finished Jan 14 12:58:08 PM PST 24
Peak memory 155760 kb
Host smart-5f4bd55a-7431-416a-b808-31c4ad7ef829
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2842067646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2842067646
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2327197206
Short name T1
Test name
Test status
Simulation time 1441770000 ps
CPU time 4.51 seconds
Started Jan 14 12:57:56 PM PST 24
Finished Jan 14 12:58:07 PM PST 24
Peak memory 155656 kb
Host smart-c51a89cd-b6e1-42f4-a243-540011c565b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2327197206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2327197206
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1698307508
Short name T72
Test name
Test status
Simulation time 1365710000 ps
CPU time 4.98 seconds
Started Jan 14 12:58:07 PM PST 24
Finished Jan 14 12:58:18 PM PST 24
Peak memory 155688 kb
Host smart-bf006354-b7db-410a-8e9b-7d46937d5ef2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1698307508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1698307508
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.733119340
Short name T8
Test name
Test status
Simulation time 1517990000 ps
CPU time 3.54 seconds
Started Jan 14 12:58:08 PM PST 24
Finished Jan 14 12:58:16 PM PST 24
Peak memory 155716 kb
Host smart-e057d75d-5687-4d1b-86ba-c98b31cb0768
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=733119340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.733119340
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.672928748
Short name T67
Test name
Test status
Simulation time 1323610000 ps
CPU time 4.38 seconds
Started Jan 14 12:58:09 PM PST 24
Finished Jan 14 12:58:19 PM PST 24
Peak memory 155748 kb
Host smart-3699a408-2e36-4dd6-a881-667267de2e8f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=672928748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.672928748
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1175279974
Short name T71
Test name
Test status
Simulation time 1340770000 ps
CPU time 4.32 seconds
Started Jan 14 12:57:01 PM PST 24
Finished Jan 14 12:57:11 PM PST 24
Peak memory 155768 kb
Host smart-c7894b7a-d245-476f-b56d-8bb35296d3ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175279974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1175279974
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1924876570
Short name T2
Test name
Test status
Simulation time 1455730000 ps
CPU time 3.94 seconds
Started Jan 14 12:57:00 PM PST 24
Finished Jan 14 12:57:09 PM PST 24
Peak memory 155788 kb
Host smart-d4934a1e-c740-4dd2-8d6f-402c0000a3cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1924876570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1924876570
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1928359471
Short name T11
Test name
Test status
Simulation time 1374910000 ps
CPU time 3.91 seconds
Started Jan 14 12:57:02 PM PST 24
Finished Jan 14 12:57:12 PM PST 24
Peak memory 155836 kb
Host smart-2c3d28d1-b2f3-43b4-b917-29fdb0728525
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1928359471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1928359471
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2390513748
Short name T57
Test name
Test status
Simulation time 1354330000 ps
CPU time 3.85 seconds
Started Jan 14 12:57:02 PM PST 24
Finished Jan 14 12:57:11 PM PST 24
Peak memory 155792 kb
Host smart-f04ba393-c061-4f42-b1c0-f31a4e6524d9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2390513748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2390513748
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.461902275
Short name T13
Test name
Test status
Simulation time 1443870000 ps
CPU time 3.95 seconds
Started Jan 14 12:57:00 PM PST 24
Finished Jan 14 12:57:10 PM PST 24
Peak memory 155788 kb
Host smart-f534fff6-f918-4f15-bc39-ab3b91e7f0c7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461902275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.461902275
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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