Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.90950758
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3741408505
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1677957232
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3388770485

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.745133800
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.611989485
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2168331738
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.235572330
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2449375161
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.109162247
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4124497218
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2762089192
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2593464139
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3022283672
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3320311428
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3626270573
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4158616034
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3328982552
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.673601250
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.656245663
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.177123556
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4048967652
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1710347198
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3475903443
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2680944390
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1792125233
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2957889574
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1066420196
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.79931377
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2531753240
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.962449090
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2491098612
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1708678338
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2743381612
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3320307776
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1344705325
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1077492472
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.458505770
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3440961514
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4262037789
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4188303303
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2674537701
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2093024056
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.390832798
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2149420114
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.98446298
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1521415357
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2511114468
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4091396039
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2831885370
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2936811713
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1876580475
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3053787515
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1625889529
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3561664629
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3210767882
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2563008316
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2139395082
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1425342270
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1382590480
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1284373185
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3631068437
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4143524406
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.543852845
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3673144995
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2313141288
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.855196465
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1061670547
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3568936876
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3056761025
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3388462904
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3271997668
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1500642919
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3571992128
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.165748338
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2778229471
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2707184024
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2367149920
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.936802297
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2067791034
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3329711066
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2287930839
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.453505065
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1457616203
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3447440649
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2693204491
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.153559974
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2236068227
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.460063069
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4167780955
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2796745080
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.173534479
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.385997395
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1418779642
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.752216652
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3606924629
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.703466712
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2424015616
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1912010297
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.784408871
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.326538506
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1198704706
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2606328880
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3699808391
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.858038025
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3174753377
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.361210212
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3271251773
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1428332468
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3812913695
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2822247188
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1818685628
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.246112068
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3092805266
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.880941157
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3133581602
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3524276999
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2737524581
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3877055871
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1766170643
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1696192460
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1241134837
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2827591841
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2036136336
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2266072165
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2873735792
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.942860898
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.497094470
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3430634578
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2161773318
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.135159857
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1883022436
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.894487121
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2949366001
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.826851316
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.929049774
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2564420593
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.719799095
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4044944293
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1281743360
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3153470731
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3860733609
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1301723975
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.595504378
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2339932694
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3492647723
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1903652754
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1650616658
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.231544855
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3569995900
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.439866708
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3857903019
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4201828075
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1954287385
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2936483769
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.809537685
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3334553086
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1372787419
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1335863736
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2390311250
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1765639405
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.208502292
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3606221132
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2311952818
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1335531892
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1907173489
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1567685882
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2867945089
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.894717476
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.28912590
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.793881391
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4013514126
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.325197733
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2208481690
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2781057018
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1231056929
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3575581009
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.525645276
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3958375984
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.987695080
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2757910666
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2168363185
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1758979150
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3617226822
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.643548527
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1573037068
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3530125649
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.864806768
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.267987821
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1408267993
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.285772324
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1659801567
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4053992086
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1069137179
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2594075617
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1314704670
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2383138276
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.768947733
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3897959591
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2930064159



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.643548527 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:42 PM PST 24 1169530000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1758979150 Feb 21 02:51:42 PM PST 24 Feb 21 02:51:55 PM PST 24 1450930000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1372787419 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:49 PM PST 24 1435810000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1573037068 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:55 PM PST 24 1518650000 ps
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T138 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.784408871 Feb 21 02:52:09 PM PST 24 Feb 21 03:28:13 PM PST 24 336931250000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2313141288 Feb 21 02:52:03 PM PST 24 Feb 21 03:25:39 PM PST 24 336898890000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.326538506 Feb 21 02:52:12 PM PST 24 Feb 21 03:26:37 PM PST 24 336510370000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3568936876 Feb 21 02:52:06 PM PST 24 Feb 21 03:30:42 PM PST 24 336802150000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2424015616 Feb 21 02:52:12 PM PST 24 Feb 21 03:26:39 PM PST 24 336457350000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3329711066 Feb 21 02:52:10 PM PST 24 Feb 21 03:35:13 PM PST 24 336848630000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1912010297 Feb 21 02:52:12 PM PST 24 Feb 21 03:37:02 PM PST 24 336846170000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1198704706 Feb 21 02:52:15 PM PST 24 Feb 21 03:36:00 PM PST 24 336865170000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4143524406 Feb 21 02:52:12 PM PST 24 Feb 21 03:31:57 PM PST 24 336678030000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1500642919 Feb 21 02:52:03 PM PST 24 Feb 21 03:27:59 PM PST 24 336340150000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.543852845 Feb 21 02:52:03 PM PST 24 Feb 21 03:28:20 PM PST 24 336410370000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3561664629 Feb 21 02:52:07 PM PST 24 Feb 21 03:26:53 PM PST 24 336431450000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2563008316 Feb 21 02:52:22 PM PST 24 Feb 21 03:22:18 PM PST 24 336386310000 ps
T151 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2796745080 Feb 21 02:52:14 PM PST 24 Feb 21 03:31:27 PM PST 24 336644370000 ps
T152 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2067791034 Feb 21 02:52:11 PM PST 24 Feb 21 03:31:48 PM PST 24 336885350000 ps
T153 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3447440649 Feb 21 02:52:12 PM PST 24 Feb 21 03:35:00 PM PST 24 336366550000 ps
T154 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.855196465 Feb 21 02:52:12 PM PST 24 Feb 21 03:33:19 PM PST 24 336405050000 ps
T155 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2367149920 Feb 21 02:52:17 PM PST 24 Feb 21 03:25:52 PM PST 24 336947790000 ps
T156 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.173534479 Feb 21 02:52:17 PM PST 24 Feb 21 03:35:54 PM PST 24 336805930000 ps
T157 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.936802297 Feb 21 02:52:19 PM PST 24 Feb 21 03:23:18 PM PST 24 337048170000 ps
T158 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1418779642 Feb 21 02:52:40 PM PST 24 Feb 21 03:23:25 PM PST 24 336472510000 ps
T159 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3571992128 Feb 21 02:52:09 PM PST 24 Feb 21 03:26:35 PM PST 24 336920310000 ps
T160 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1457616203 Feb 21 02:52:09 PM PST 24 Feb 21 03:28:06 PM PST 24 336614410000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2531753240 Feb 21 02:52:41 PM PST 24 Feb 21 03:23:39 PM PST 24 336304630000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2093024056 Feb 21 02:52:31 PM PST 24 Feb 21 03:28:32 PM PST 24 337025090000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2680944390 Feb 21 02:52:22 PM PST 24 Feb 21 03:26:54 PM PST 24 336702150000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4091396039 Feb 21 02:52:16 PM PST 24 Feb 21 03:30:51 PM PST 24 337030410000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1677957232 Feb 21 02:52:50 PM PST 24 Feb 21 03:25:49 PM PST 24 336952870000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3475903443 Feb 21 02:52:45 PM PST 24 Feb 21 03:26:00 PM PST 24 336869090000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3053787515 Feb 21 02:52:14 PM PST 24 Feb 21 03:31:44 PM PST 24 336563430000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3022283672 Feb 21 02:52:12 PM PST 24 Feb 21 03:23:40 PM PST 24 336856730000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2491098612 Feb 21 02:52:39 PM PST 24 Feb 21 03:26:56 PM PST 24 336413130000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1708678338 Feb 21 02:52:33 PM PST 24 Feb 21 03:28:17 PM PST 24 336370830000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2674537701 Feb 21 02:52:32 PM PST 24 Feb 21 03:27:47 PM PST 24 337152070000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3320311428 Feb 21 02:52:13 PM PST 24 Feb 21 03:26:35 PM PST 24 336997890000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2762089192 Feb 21 02:52:50 PM PST 24 Feb 21 03:28:02 PM PST 24 336722630000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4124497218 Feb 21 02:52:41 PM PST 24 Feb 21 03:24:12 PM PST 24 336902050000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.656245663 Feb 21 02:52:30 PM PST 24 Feb 21 03:35:14 PM PST 24 336664390000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.611989485 Feb 21 02:52:35 PM PST 24 Feb 21 03:25:38 PM PST 24 336969590000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4188303303 Feb 21 02:52:32 PM PST 24 Feb 21 03:36:00 PM PST 24 337107090000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2168331738 Feb 21 02:52:46 PM PST 24 Feb 21 03:26:42 PM PST 24 336489350000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4048967652 Feb 21 02:52:30 PM PST 24 Feb 21 03:19:27 PM PST 24 336992090000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3328982552 Feb 21 02:52:28 PM PST 24 Feb 21 03:26:21 PM PST 24 336463490000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3320307776 Feb 21 02:52:42 PM PST 24 Feb 21 03:27:35 PM PST 24 336589390000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2593464139 Feb 21 02:52:34 PM PST 24 Feb 21 03:24:45 PM PST 24 336680530000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.109162247 Feb 21 02:52:31 PM PST 24 Feb 21 03:22:59 PM PST 24 336640530000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1077492472 Feb 21 02:52:33 PM PST 24 Feb 21 03:32:35 PM PST 24 336739110000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.98446298 Feb 21 02:52:40 PM PST 24 Feb 21 03:25:42 PM PST 24 336644510000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3440961514 Feb 21 02:52:30 PM PST 24 Feb 21 03:26:31 PM PST 24 336370290000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2743381612 Feb 21 02:52:28 PM PST 24 Feb 21 03:31:36 PM PST 24 336780490000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3626270573 Feb 21 02:52:15 PM PST 24 Feb 21 03:25:31 PM PST 24 336448570000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.745133800 Feb 21 02:52:32 PM PST 24 Feb 21 03:32:41 PM PST 24 337040350000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2511114468 Feb 21 02:52:34 PM PST 24 Feb 21 03:28:17 PM PST 24 336933510000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1521415357 Feb 21 02:52:39 PM PST 24 Feb 21 03:25:54 PM PST 24 336668250000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2831885370 Feb 21 02:52:45 PM PST 24 Feb 21 03:27:31 PM PST 24 336356470000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2449375161 Feb 21 02:52:34 PM PST 24 Feb 21 03:32:28 PM PST 24 336604490000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1710347198 Feb 21 02:52:39 PM PST 24 Feb 21 03:21:32 PM PST 24 336497150000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.673601250 Feb 21 02:52:36 PM PST 24 Feb 21 03:22:59 PM PST 24 336999530000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1344705325 Feb 21 02:52:31 PM PST 24 Feb 21 03:34:58 PM PST 24 336396410000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.235572330 Feb 21 02:52:45 PM PST 24 Feb 21 03:27:33 PM PST 24 336873790000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1876580475 Feb 21 02:52:41 PM PST 24 Feb 21 03:21:33 PM PST 24 336857130000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.458505770 Feb 21 02:52:18 PM PST 24 Feb 21 03:24:36 PM PST 24 337028910000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.390832798 Feb 21 02:52:31 PM PST 24 Feb 21 03:34:05 PM PST 24 336440410000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1792125233 Feb 21 02:52:34 PM PST 24 Feb 21 03:27:10 PM PST 24 336969870000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.962449090 Feb 21 02:52:32 PM PST 24 Feb 21 03:30:23 PM PST 24 336469250000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4262037789 Feb 21 02:52:32 PM PST 24 Feb 21 03:35:58 PM PST 24 336840010000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.79931377 Feb 21 02:52:45 PM PST 24 Feb 21 03:24:10 PM PST 24 336600690000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.177123556 Feb 21 02:52:28 PM PST 24 Feb 21 03:26:10 PM PST 24 336932570000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1066420196 Feb 21 02:52:28 PM PST 24 Feb 21 03:36:03 PM PST 24 336561790000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4158616034 Feb 21 02:52:15 PM PST 24 Feb 21 03:28:08 PM PST 24 336671330000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2149420114 Feb 21 02:52:34 PM PST 24 Feb 21 03:33:42 PM PST 24 337066890000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2957889574 Feb 21 02:52:13 PM PST 24 Feb 21 03:24:10 PM PST 24 336374230000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2936811713 Feb 21 02:52:48 PM PST 24 Feb 21 03:24:16 PM PST 24 337048770000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.90950758
Short name T13
Test name
Test status
Simulation time 1479930000 ps
CPU time 4.65 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 02:52:14 PM PST 24
Peak memory 164588 kb
Host smart-9f05fda2-7983-43af-ae4f-9cc69fcfedae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90950758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.90950758
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3741408505
Short name T15
Test name
Test status
Simulation time 336703810000 ps
CPU time 714.22 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 03:21:47 PM PST 24
Peak memory 160644 kb
Host smart-4b656861-17c0-4c1b-98ca-99115e7b602b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3741408505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3741408505
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1677957232
Short name T35
Test name
Test status
Simulation time 336952870000 ps
CPU time 808.67 seconds
Started Feb 21 02:52:50 PM PST 24
Finished Feb 21 03:25:49 PM PST 24
Peak memory 160792 kb
Host smart-84124416-965e-401a-9872-69edf1c6cd22
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1677957232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1677957232
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3388770485
Short name T25
Test name
Test status
Simulation time 1468990000 ps
CPU time 3.48 seconds
Started Feb 21 02:52:14 PM PST 24
Finished Feb 21 02:52:27 PM PST 24
Peak memory 164680 kb
Host smart-03b84f02-208f-4a05-957f-3c82c73d6795
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3388770485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3388770485
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.745133800
Short name T179
Test name
Test status
Simulation time 337040350000 ps
CPU time 955.43 seconds
Started Feb 21 02:52:32 PM PST 24
Finished Feb 21 03:32:41 PM PST 24
Peak memory 160784 kb
Host smart-a483df55-8be1-4c5f-b2d8-24b03142d7b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=745133800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.745133800
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.611989485
Short name T166
Test name
Test status
Simulation time 336969590000 ps
CPU time 815.12 seconds
Started Feb 21 02:52:35 PM PST 24
Finished Feb 21 03:25:38 PM PST 24
Peak memory 160780 kb
Host smart-260eaba9-1604-46b8-910b-bc0dca1fa368
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=611989485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.611989485
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2168331738
Short name T168
Test name
Test status
Simulation time 336489350000 ps
CPU time 830.25 seconds
Started Feb 21 02:52:46 PM PST 24
Finished Feb 21 03:26:42 PM PST 24
Peak memory 160816 kb
Host smart-96b94c58-bdb0-411d-a69a-dad2d69ebc4a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2168331738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2168331738
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.235572330
Short name T187
Test name
Test status
Simulation time 336873790000 ps
CPU time 852.52 seconds
Started Feb 21 02:52:45 PM PST 24
Finished Feb 21 03:27:33 PM PST 24
Peak memory 160780 kb
Host smart-da191239-b263-4205-a51a-3b871a3b48a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=235572330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.235572330
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2449375161
Short name T183
Test name
Test status
Simulation time 336604490000 ps
CPU time 948.04 seconds
Started Feb 21 02:52:34 PM PST 24
Finished Feb 21 03:32:28 PM PST 24
Peak memory 160792 kb
Host smart-ad195ccf-d93d-43a2-b00b-7c7a959d06d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2449375161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2449375161
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.109162247
Short name T173
Test name
Test status
Simulation time 336640530000 ps
CPU time 752.12 seconds
Started Feb 21 02:52:31 PM PST 24
Finished Feb 21 03:22:59 PM PST 24
Peak memory 160804 kb
Host smart-f9ce1b46-e172-4ab3-b278-bd97d3cabf7c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=109162247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.109162247
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4124497218
Short name T164
Test name
Test status
Simulation time 336902050000 ps
CPU time 779.59 seconds
Started Feb 21 02:52:41 PM PST 24
Finished Feb 21 03:24:12 PM PST 24
Peak memory 160820 kb
Host smart-3da26325-6d10-4781-a4ab-4a7ce6ead94a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4124497218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.4124497218
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2762089192
Short name T163
Test name
Test status
Simulation time 336722630000 ps
CPU time 865.48 seconds
Started Feb 21 02:52:50 PM PST 24
Finished Feb 21 03:28:02 PM PST 24
Peak memory 160788 kb
Host smart-9179d601-15b1-4eae-851a-7d56b76085b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2762089192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2762089192
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2593464139
Short name T172
Test name
Test status
Simulation time 336680530000 ps
CPU time 795.33 seconds
Started Feb 21 02:52:34 PM PST 24
Finished Feb 21 03:24:45 PM PST 24
Peak memory 160780 kb
Host smart-8e64a0c0-b853-4520-92b3-5511b1e85050
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2593464139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2593464139
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3022283672
Short name T38
Test name
Test status
Simulation time 336856730000 ps
CPU time 762.92 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:23:40 PM PST 24
Peak memory 160824 kb
Host smart-475419e5-9996-4bb8-9e3c-a2d8bc071318
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3022283672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3022283672
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3320311428
Short name T162
Test name
Test status
Simulation time 336997890000 ps
CPU time 834.38 seconds
Started Feb 21 02:52:13 PM PST 24
Finished Feb 21 03:26:35 PM PST 24
Peak memory 160876 kb
Host smart-7433567f-e712-4bfb-997c-d99fc0db0251
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3320311428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3320311428
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3626270573
Short name T178
Test name
Test status
Simulation time 336448570000 ps
CPU time 812.86 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:25:31 PM PST 24
Peak memory 160788 kb
Host smart-b84b7fe7-9bab-44fa-a270-af35357e06aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3626270573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3626270573
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.4158616034
Short name T197
Test name
Test status
Simulation time 336671330000 ps
CPU time 878.73 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:28:08 PM PST 24
Peak memory 160780 kb
Host smart-acdae6b5-7c27-421b-98a6-5d926ae39b16
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4158616034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.4158616034
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3328982552
Short name T170
Test name
Test status
Simulation time 336463490000 ps
CPU time 788.09 seconds
Started Feb 21 02:52:28 PM PST 24
Finished Feb 21 03:26:21 PM PST 24
Peak memory 160712 kb
Host smart-7f0c9f26-b235-427c-8ce9-6beeafbde4ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328982552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3328982552
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.673601250
Short name T185
Test name
Test status
Simulation time 336999530000 ps
CPU time 743.03 seconds
Started Feb 21 02:52:36 PM PST 24
Finished Feb 21 03:22:59 PM PST 24
Peak memory 160784 kb
Host smart-01d94688-aebd-4ada-8ea9-b1e7805d241e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=673601250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.673601250
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.656245663
Short name T165
Test name
Test status
Simulation time 336664390000 ps
CPU time 1027.04 seconds
Started Feb 21 02:52:30 PM PST 24
Finished Feb 21 03:35:14 PM PST 24
Peak memory 160776 kb
Host smart-7350df55-fc83-4d93-93ce-e51888d14eab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=656245663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.656245663
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.177123556
Short name T195
Test name
Test status
Simulation time 336932570000 ps
CPU time 820.07 seconds
Started Feb 21 02:52:28 PM PST 24
Finished Feb 21 03:26:10 PM PST 24
Peak memory 160784 kb
Host smart-d6611a4b-4e6c-45e9-9489-fb94dc0a662c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=177123556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.177123556
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4048967652
Short name T169
Test name
Test status
Simulation time 336992090000 ps
CPU time 663.77 seconds
Started Feb 21 02:52:30 PM PST 24
Finished Feb 21 03:19:27 PM PST 24
Peak memory 160756 kb
Host smart-de04d930-2016-4c14-bfbe-5341518566a7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4048967652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4048967652
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1710347198
Short name T184
Test name
Test status
Simulation time 336497150000 ps
CPU time 703.46 seconds
Started Feb 21 02:52:39 PM PST 24
Finished Feb 21 03:21:32 PM PST 24
Peak memory 160800 kb
Host smart-6a8f13d1-288c-4ac0-93d7-c2e50ff2c8e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1710347198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1710347198
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3475903443
Short name T36
Test name
Test status
Simulation time 336869090000 ps
CPU time 808.84 seconds
Started Feb 21 02:52:45 PM PST 24
Finished Feb 21 03:26:00 PM PST 24
Peak memory 160876 kb
Host smart-e211ad15-a328-44a0-bbee-78d41681025b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3475903443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3475903443
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2680944390
Short name T33
Test name
Test status
Simulation time 336702150000 ps
CPU time 835.32 seconds
Started Feb 21 02:52:22 PM PST 24
Finished Feb 21 03:26:54 PM PST 24
Peak memory 160824 kb
Host smart-d1c983d2-b3a5-4615-a1c0-2812475777ff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2680944390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2680944390
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1792125233
Short name T191
Test name
Test status
Simulation time 336969870000 ps
CPU time 839.74 seconds
Started Feb 21 02:52:34 PM PST 24
Finished Feb 21 03:27:10 PM PST 24
Peak memory 160776 kb
Host smart-af1ccdc8-b3f7-47e4-8585-be05691eb545
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1792125233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1792125233
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2957889574
Short name T199
Test name
Test status
Simulation time 336374230000 ps
CPU time 792.24 seconds
Started Feb 21 02:52:13 PM PST 24
Finished Feb 21 03:24:10 PM PST 24
Peak memory 160776 kb
Host smart-e3c028a4-1385-4a64-b75f-4a7f6b9153b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2957889574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2957889574
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1066420196
Short name T196
Test name
Test status
Simulation time 336561790000 ps
CPU time 1043.8 seconds
Started Feb 21 02:52:28 PM PST 24
Finished Feb 21 03:36:03 PM PST 24
Peak memory 160920 kb
Host smart-c64e5a19-8da1-42aa-b36b-96f3f1b45542
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1066420196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1066420196
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.79931377
Short name T194
Test name
Test status
Simulation time 336600690000 ps
CPU time 780.18 seconds
Started Feb 21 02:52:45 PM PST 24
Finished Feb 21 03:24:10 PM PST 24
Peak memory 160804 kb
Host smart-1f4c1206-cbd6-43e6-8114-5c12b0677ff4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=79931377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.79931377
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2531753240
Short name T31
Test name
Test status
Simulation time 336304630000 ps
CPU time 770.03 seconds
Started Feb 21 02:52:41 PM PST 24
Finished Feb 21 03:23:39 PM PST 24
Peak memory 160820 kb
Host smart-e2bad7b8-87d4-4b67-bc42-524a4804f97c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2531753240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2531753240
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.962449090
Short name T192
Test name
Test status
Simulation time 336469250000 ps
CPU time 921.76 seconds
Started Feb 21 02:52:32 PM PST 24
Finished Feb 21 03:30:23 PM PST 24
Peak memory 160784 kb
Host smart-95307c3a-5678-433d-959e-4f8c33367a97
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=962449090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.962449090
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2491098612
Short name T39
Test name
Test status
Simulation time 336413130000 ps
CPU time 848.83 seconds
Started Feb 21 02:52:39 PM PST 24
Finished Feb 21 03:26:56 PM PST 24
Peak memory 160784 kb
Host smart-027f899a-5678-40c5-a7a6-def2ad5fc081
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2491098612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2491098612
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1708678338
Short name T40
Test name
Test status
Simulation time 336370830000 ps
CPU time 875.5 seconds
Started Feb 21 02:52:33 PM PST 24
Finished Feb 21 03:28:17 PM PST 24
Peak memory 160780 kb
Host smart-33e25f1a-cb1d-4ef9-8870-926f40d2324b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1708678338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1708678338
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2743381612
Short name T177
Test name
Test status
Simulation time 336780490000 ps
CPU time 914.29 seconds
Started Feb 21 02:52:28 PM PST 24
Finished Feb 21 03:31:36 PM PST 24
Peak memory 160804 kb
Host smart-de39d21c-8b5b-4263-9d5a-75daeff446b5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2743381612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2743381612
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3320307776
Short name T171
Test name
Test status
Simulation time 336589390000 ps
CPU time 847.3 seconds
Started Feb 21 02:52:42 PM PST 24
Finished Feb 21 03:27:35 PM PST 24
Peak memory 160748 kb
Host smart-4c2db307-334d-49ee-904d-53270f7ac884
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3320307776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3320307776
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1344705325
Short name T186
Test name
Test status
Simulation time 336396410000 ps
CPU time 1015.8 seconds
Started Feb 21 02:52:31 PM PST 24
Finished Feb 21 03:34:58 PM PST 24
Peak memory 160784 kb
Host smart-b7dfd39c-4835-4f6f-9bd8-05aa37257a03
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1344705325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1344705325
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1077492472
Short name T174
Test name
Test status
Simulation time 336739110000 ps
CPU time 953.53 seconds
Started Feb 21 02:52:33 PM PST 24
Finished Feb 21 03:32:35 PM PST 24
Peak memory 160792 kb
Host smart-90de9a78-3199-4cc7-8605-e853fa678c6c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1077492472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1077492472
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.458505770
Short name T189
Test name
Test status
Simulation time 337028910000 ps
CPU time 802.66 seconds
Started Feb 21 02:52:18 PM PST 24
Finished Feb 21 03:24:36 PM PST 24
Peak memory 160792 kb
Host smart-cb014be7-e568-49a0-bbb1-ebf5fc6343fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=458505770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.458505770
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3440961514
Short name T176
Test name
Test status
Simulation time 336370290000 ps
CPU time 825.74 seconds
Started Feb 21 02:52:30 PM PST 24
Finished Feb 21 03:26:31 PM PST 24
Peak memory 160796 kb
Host smart-9f5d0428-ad6e-464d-96bf-03ef46b1548b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3440961514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3440961514
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4262037789
Short name T193
Test name
Test status
Simulation time 336840010000 ps
CPU time 1040.28 seconds
Started Feb 21 02:52:32 PM PST 24
Finished Feb 21 03:35:58 PM PST 24
Peak memory 160816 kb
Host smart-322e0f97-1766-4073-a701-dcd24fcf06fb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4262037789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4262037789
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4188303303
Short name T167
Test name
Test status
Simulation time 337107090000 ps
CPU time 1043.25 seconds
Started Feb 21 02:52:32 PM PST 24
Finished Feb 21 03:36:00 PM PST 24
Peak memory 160816 kb
Host smart-f0ff8f64-fe86-4bfa-a7ad-5d4e41366add
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4188303303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.4188303303
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2674537701
Short name T161
Test name
Test status
Simulation time 337152070000 ps
CPU time 873.59 seconds
Started Feb 21 02:52:32 PM PST 24
Finished Feb 21 03:27:47 PM PST 24
Peak memory 160924 kb
Host smart-0dbd3e09-a82e-4461-a050-d5bf7cd3916e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2674537701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2674537701
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2093024056
Short name T32
Test name
Test status
Simulation time 337025090000 ps
CPU time 862.84 seconds
Started Feb 21 02:52:31 PM PST 24
Finished Feb 21 03:28:32 PM PST 24
Peak memory 160792 kb
Host smart-27691889-2192-493e-9f3e-0a9512c09a4d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2093024056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2093024056
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.390832798
Short name T190
Test name
Test status
Simulation time 336440410000 ps
CPU time 954.26 seconds
Started Feb 21 02:52:31 PM PST 24
Finished Feb 21 03:34:05 PM PST 24
Peak memory 160772 kb
Host smart-eac72e09-5937-42e7-b624-40a7a7068343
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=390832798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.390832798
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2149420114
Short name T198
Test name
Test status
Simulation time 337066890000 ps
CPU time 995.84 seconds
Started Feb 21 02:52:34 PM PST 24
Finished Feb 21 03:33:42 PM PST 24
Peak memory 160800 kb
Host smart-e097246f-d3c9-4fa6-b996-ff17b7473010
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2149420114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2149420114
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.98446298
Short name T175
Test name
Test status
Simulation time 336644510000 ps
CPU time 814.61 seconds
Started Feb 21 02:52:40 PM PST 24
Finished Feb 21 03:25:42 PM PST 24
Peak memory 160792 kb
Host smart-ee29045d-b442-495a-8eef-d34fc3056e4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=98446298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.98446298
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1521415357
Short name T181
Test name
Test status
Simulation time 336668250000 ps
CPU time 800.51 seconds
Started Feb 21 02:52:39 PM PST 24
Finished Feb 21 03:25:54 PM PST 24
Peak memory 160876 kb
Host smart-9bdb3209-d195-4011-ad51-6ed37b367117
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1521415357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1521415357
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2511114468
Short name T180
Test name
Test status
Simulation time 336933510000 ps
CPU time 875.85 seconds
Started Feb 21 02:52:34 PM PST 24
Finished Feb 21 03:28:17 PM PST 24
Peak memory 160780 kb
Host smart-a6b3b783-9622-4e3a-9a78-44aa34ee221e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2511114468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2511114468
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.4091396039
Short name T34
Test name
Test status
Simulation time 337030410000 ps
CPU time 946.69 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 03:30:51 PM PST 24
Peak memory 160788 kb
Host smart-f6e6ac26-ea3f-4af2-aeaa-5eb97537f8ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4091396039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.4091396039
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2831885370
Short name T182
Test name
Test status
Simulation time 336356470000 ps
CPU time 839.84 seconds
Started Feb 21 02:52:45 PM PST 24
Finished Feb 21 03:27:31 PM PST 24
Peak memory 160740 kb
Host smart-a7a5b2c8-e860-4f41-aae7-635b398b38d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2831885370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2831885370
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2936811713
Short name T200
Test name
Test status
Simulation time 337048770000 ps
CPU time 780.01 seconds
Started Feb 21 02:52:48 PM PST 24
Finished Feb 21 03:24:16 PM PST 24
Peak memory 160848 kb
Host smart-0b8a02e4-f120-4d86-b5b2-5245950ad843
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2936811713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2936811713
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1876580475
Short name T188
Test name
Test status
Simulation time 336857130000 ps
CPU time 707.75 seconds
Started Feb 21 02:52:41 PM PST 24
Finished Feb 21 03:21:33 PM PST 24
Peak memory 160808 kb
Host smart-d7eca35f-1058-4270-af8b-61135aa4d578
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1876580475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1876580475
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3053787515
Short name T37
Test name
Test status
Simulation time 336563430000 ps
CPU time 933.24 seconds
Started Feb 21 02:52:14 PM PST 24
Finished Feb 21 03:31:44 PM PST 24
Peak memory 160796 kb
Host smart-cdafb10b-ea53-4b96-8b51-ed97c4a5e130
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3053787515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3053787515
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1625889529
Short name T20
Test name
Test status
Simulation time 336984190000 ps
CPU time 737.53 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 03:22:26 PM PST 24
Peak memory 160708 kb
Host smart-16fc4b7e-d9e9-4d6a-83b5-77924a9481cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1625889529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1625889529
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3561664629
Short name T149
Test name
Test status
Simulation time 336431450000 ps
CPU time 832 seconds
Started Feb 21 02:52:07 PM PST 24
Finished Feb 21 03:26:53 PM PST 24
Peak memory 160708 kb
Host smart-8f1613b3-a585-43f0-8aa0-2535af9a1f54
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3561664629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3561664629
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3210767882
Short name T128
Test name
Test status
Simulation time 336828290000 ps
CPU time 597.99 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 160652 kb
Host smart-8a9c8b92-a77b-4f92-af7a-3defec2ebaee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3210767882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3210767882
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2563008316
Short name T150
Test name
Test status
Simulation time 336386310000 ps
CPU time 735.99 seconds
Started Feb 21 02:52:22 PM PST 24
Finished Feb 21 03:22:18 PM PST 24
Peak memory 160680 kb
Host smart-32d9cfc1-f694-4bc9-88e2-780bb1f048cf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2563008316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2563008316
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2139395082
Short name T16
Test name
Test status
Simulation time 336963830000 ps
CPU time 824.89 seconds
Started Feb 21 02:52:06 PM PST 24
Finished Feb 21 03:25:45 PM PST 24
Peak memory 160632 kb
Host smart-01bd251e-0f4a-4781-8914-365032f85c86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2139395082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2139395082
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1425342270
Short name T19
Test name
Test status
Simulation time 336595590000 ps
CPU time 1059.84 seconds
Started Feb 21 02:52:11 PM PST 24
Finished Feb 21 03:36:26 PM PST 24
Peak memory 160800 kb
Host smart-05ec0d53-3705-4cc4-b883-db968b5f368a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1425342270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1425342270
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1382590480
Short name T136
Test name
Test status
Simulation time 336501230000 ps
CPU time 731.11 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 03:21:58 PM PST 24
Peak memory 160680 kb
Host smart-e9c40971-8e8d-4bf1-b8be-d9ca6f952eee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1382590480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1382590480
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1284373185
Short name T22
Test name
Test status
Simulation time 336667610000 ps
CPU time 768.33 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:23:31 PM PST 24
Peak memory 160676 kb
Host smart-af0195bc-e3a7-4905-9b9f-3d064ce2a23d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1284373185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1284373185
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3631068437
Short name T23
Test name
Test status
Simulation time 336919810000 ps
CPU time 841.49 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:26:08 PM PST 24
Peak memory 160724 kb
Host smart-722d0e31-c7b7-43af-ad4d-db18515b5b29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3631068437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3631068437
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4143524406
Short name T146
Test name
Test status
Simulation time 336678030000 ps
CPU time 962.56 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:31:57 PM PST 24
Peak memory 160656 kb
Host smart-ff12a839-6a44-4199-ba85-c53108b6eb27
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143524406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4143524406
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.543852845
Short name T148
Test name
Test status
Simulation time 336410370000 ps
CPU time 874.67 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 03:28:20 PM PST 24
Peak memory 160572 kb
Host smart-102fe18e-2c14-4e30-bab2-ef1689b793e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=543852845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.543852845
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3673144995
Short name T129
Test name
Test status
Simulation time 336891130000 ps
CPU time 822.11 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 03:25:11 PM PST 24
Peak memory 160632 kb
Host smart-bf9c1cdc-ba9b-408c-adff-763620ea8757
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3673144995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3673144995
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2313141288
Short name T139
Test name
Test status
Simulation time 336898890000 ps
CPU time 834.69 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 03:25:39 PM PST 24
Peak memory 160676 kb
Host smart-0d2cd99f-e27d-4568-9c57-e460f14b55b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2313141288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2313141288
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.855196465
Short name T154
Test name
Test status
Simulation time 336405050000 ps
CPU time 1005.33 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:33:19 PM PST 24
Peak memory 160664 kb
Host smart-6bf96a15-4ba0-48a0-9333-dcccca422dc7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=855196465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.855196465
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1061670547
Short name T122
Test name
Test status
Simulation time 336680170000 ps
CPU time 1066.4 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:36:51 PM PST 24
Peak memory 160800 kb
Host smart-86938232-4818-4ed4-a163-09e633cdea14
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1061670547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1061670547
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3568936876
Short name T141
Test name
Test status
Simulation time 336802150000 ps
CPU time 924.13 seconds
Started Feb 21 02:52:06 PM PST 24
Finished Feb 21 03:30:42 PM PST 24
Peak memory 160676 kb
Host smart-830f3920-bb6a-4135-9dbc-3b9da82e3446
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3568936876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3568936876
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3056761025
Short name T130
Test name
Test status
Simulation time 336527770000 ps
CPU time 842.84 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 03:26:37 PM PST 24
Peak memory 160684 kb
Host smart-0286b2f6-3850-41dd-a11a-876fad07a7e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3056761025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3056761025
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3388462904
Short name T126
Test name
Test status
Simulation time 336524250000 ps
CPU time 810.69 seconds
Started Feb 21 02:52:10 PM PST 24
Finished Feb 21 03:25:06 PM PST 24
Peak memory 160684 kb
Host smart-15959bdd-8e41-48bb-bd2f-bb6b44152340
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3388462904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3388462904
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3271997668
Short name T137
Test name
Test status
Simulation time 336673090000 ps
CPU time 790.25 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:24:15 PM PST 24
Peak memory 160648 kb
Host smart-82381459-627c-4df5-a0df-f28f4048572e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3271997668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3271997668
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1500642919
Short name T147
Test name
Test status
Simulation time 336340150000 ps
CPU time 884.17 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 03:27:59 PM PST 24
Peak memory 160696 kb
Host smart-8fb5828c-001a-4c5d-a081-a0dd1e023f11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1500642919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1500642919
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3571992128
Short name T159
Test name
Test status
Simulation time 336920310000 ps
CPU time 822.24 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 03:26:35 PM PST 24
Peak memory 160708 kb
Host smart-52f5bf92-7b6e-4e67-a6b7-4307fbdc22ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3571992128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3571992128
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.165748338
Short name T132
Test name
Test status
Simulation time 336317210000 ps
CPU time 778.97 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 03:24:01 PM PST 24
Peak memory 160672 kb
Host smart-26ff784a-7a11-4795-af9a-05d89afd4948
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=165748338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.165748338
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2778229471
Short name T135
Test name
Test status
Simulation time 336651390000 ps
CPU time 823.78 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 03:25:41 PM PST 24
Peak memory 160632 kb
Host smart-bb44860c-0c7d-4996-8d43-06d4ddaf0224
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2778229471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2778229471
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2707184024
Short name T127
Test name
Test status
Simulation time 336383510000 ps
CPU time 931.64 seconds
Started Feb 21 02:52:06 PM PST 24
Finished Feb 21 03:30:47 PM PST 24
Peak memory 160676 kb
Host smart-e28a862a-3452-42c5-90e3-9301e7e471e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2707184024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2707184024
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2367149920
Short name T155
Test name
Test status
Simulation time 336947790000 ps
CPU time 820.32 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 03:25:52 PM PST 24
Peak memory 160672 kb
Host smart-df23d3c2-b25e-49c6-bd93-662cc35a31bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2367149920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2367149920
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.936802297
Short name T157
Test name
Test status
Simulation time 337048170000 ps
CPU time 766.4 seconds
Started Feb 21 02:52:19 PM PST 24
Finished Feb 21 03:23:18 PM PST 24
Peak memory 160736 kb
Host smart-a33b3362-16d1-4a01-9c3c-cb8b5f219fe9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=936802297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.936802297
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2067791034
Short name T152
Test name
Test status
Simulation time 336885350000 ps
CPU time 932.19 seconds
Started Feb 21 02:52:11 PM PST 24
Finished Feb 21 03:31:48 PM PST 24
Peak memory 160680 kb
Host smart-4cb9cc6f-58eb-4e1e-9336-a04c05253f38
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2067791034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2067791034
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3329711066
Short name T143
Test name
Test status
Simulation time 336848630000 ps
CPU time 1028.72 seconds
Started Feb 21 02:52:10 PM PST 24
Finished Feb 21 03:35:13 PM PST 24
Peak memory 160692 kb
Host smart-d8e8d36d-5363-40cc-b647-fd6b7c60a37f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3329711066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3329711066
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2287930839
Short name T134
Test name
Test status
Simulation time 337043030000 ps
CPU time 789.31 seconds
Started Feb 21 02:52:19 PM PST 24
Finished Feb 21 03:24:16 PM PST 24
Peak memory 160648 kb
Host smart-e8731459-cc57-4f07-86cc-f30b1a70b1e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2287930839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2287930839
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.453505065
Short name T18
Test name
Test status
Simulation time 336716990000 ps
CPU time 1036.33 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 03:35:25 PM PST 24
Peak memory 160684 kb
Host smart-4d7f23c1-ae18-4430-855d-4e16299d44bd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=453505065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.453505065
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1457616203
Short name T160
Test name
Test status
Simulation time 336614410000 ps
CPU time 895.64 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 03:28:06 PM PST 24
Peak memory 160812 kb
Host smart-ec78d2b1-e5b6-4fe5-bbb1-8b24c0b5c2dd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1457616203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1457616203
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3447440649
Short name T153
Test name
Test status
Simulation time 336366550000 ps
CPU time 1021.46 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:35:00 PM PST 24
Peak memory 160652 kb
Host smart-56a55ad1-593b-4d1a-921f-98aeac3dccd8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3447440649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3447440649
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2693204491
Short name T123
Test name
Test status
Simulation time 336830570000 ps
CPU time 881.01 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:28:30 PM PST 24
Peak memory 160624 kb
Host smart-43f44fa7-bb34-4b47-b5c5-ece19e067474
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2693204491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2693204491
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.153559974
Short name T131
Test name
Test status
Simulation time 336909830000 ps
CPU time 831.51 seconds
Started Feb 21 02:52:10 PM PST 24
Finished Feb 21 03:25:54 PM PST 24
Peak memory 160676 kb
Host smart-13fdf297-ad51-454b-bd18-01c8b304ca49
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=153559974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.153559974
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2236068227
Short name T125
Test name
Test status
Simulation time 336751050000 ps
CPU time 814.07 seconds
Started Feb 21 02:52:19 PM PST 24
Finished Feb 21 03:25:21 PM PST 24
Peak memory 160668 kb
Host smart-5c415b34-0c18-4d0e-9b41-55e770b83f25
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2236068227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2236068227
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.460063069
Short name T21
Test name
Test status
Simulation time 336430430000 ps
CPU time 733.19 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:22:22 PM PST 24
Peak memory 160672 kb
Host smart-71d44380-9bca-447f-971a-7eb721d4f460
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=460063069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.460063069
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4167780955
Short name T14
Test name
Test status
Simulation time 337058010000 ps
CPU time 832.92 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 03:26:06 PM PST 24
Peak memory 160684 kb
Host smart-36cf2e07-b19e-44dc-88d1-5a71aedfc04e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4167780955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.4167780955
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2796745080
Short name T151
Test name
Test status
Simulation time 336644370000 ps
CPU time 918.69 seconds
Started Feb 21 02:52:14 PM PST 24
Finished Feb 21 03:31:27 PM PST 24
Peak memory 160684 kb
Host smart-42598e57-dd8a-4bc4-9dfb-1ccd2471ea58
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2796745080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2796745080
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.173534479
Short name T156
Test name
Test status
Simulation time 336805930000 ps
CPU time 1049.68 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 03:35:54 PM PST 24
Peak memory 160640 kb
Host smart-fbad2417-87fc-43b3-bcaa-328383d9fe92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=173534479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.173534479
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.385997395
Short name T124
Test name
Test status
Simulation time 337059530000 ps
CPU time 832.97 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 03:26:06 PM PST 24
Peak memory 160672 kb
Host smart-5646ed0c-b9ab-48d0-8d68-ee0b9c555f11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=385997395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.385997395
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1418779642
Short name T158
Test name
Test status
Simulation time 336472510000 ps
CPU time 745.59 seconds
Started Feb 21 02:52:40 PM PST 24
Finished Feb 21 03:23:25 PM PST 24
Peak memory 160672 kb
Host smart-2f3dfbfe-5ab3-4950-896a-c77d4d56bf12
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1418779642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1418779642
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.752216652
Short name T17
Test name
Test status
Simulation time 336637970000 ps
CPU time 815.94 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:25:50 PM PST 24
Peak memory 160660 kb
Host smart-e1c1be3c-34bc-4aae-ba3c-6fc0914f7fef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=752216652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.752216652
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3606924629
Short name T121
Test name
Test status
Simulation time 336910910000 ps
CPU time 900.76 seconds
Started Feb 21 02:52:11 PM PST 24
Finished Feb 21 03:28:40 PM PST 24
Peak memory 160696 kb
Host smart-9e526594-311c-48dd-954d-79d3a9fa6937
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3606924629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3606924629
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.703466712
Short name T133
Test name
Test status
Simulation time 336834210000 ps
CPU time 1050.79 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 03:35:57 PM PST 24
Peak memory 160640 kb
Host smart-9eaa3982-3476-4f7d-bee7-4effc83a9a83
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=703466712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.703466712
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2424015616
Short name T142
Test name
Test status
Simulation time 336457350000 ps
CPU time 837.26 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:26:39 PM PST 24
Peak memory 160624 kb
Host smart-d21e1d0e-9b3f-4f07-b89f-cc022527014b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2424015616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2424015616
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1912010297
Short name T144
Test name
Test status
Simulation time 336846170000 ps
CPU time 1076.21 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:37:02 PM PST 24
Peak memory 160800 kb
Host smart-c1466bab-8d0b-4767-b448-25967d586587
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1912010297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1912010297
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.784408871
Short name T138
Test name
Test status
Simulation time 336931250000 ps
CPU time 865.81 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 03:28:13 PM PST 24
Peak memory 160576 kb
Host smart-1f069768-c00f-42b3-951c-ae6defd99670
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=784408871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.784408871
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.326538506
Short name T140
Test name
Test status
Simulation time 336510370000 ps
CPU time 833.68 seconds
Started Feb 21 02:52:12 PM PST 24
Finished Feb 21 03:26:37 PM PST 24
Peak memory 160700 kb
Host smart-73626a5a-7c49-4837-a0bb-ec73af109024
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=326538506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.326538506
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1198704706
Short name T145
Test name
Test status
Simulation time 336865170000 ps
CPU time 1057.78 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 03:36:00 PM PST 24
Peak memory 160644 kb
Host smart-5db56784-5cde-4748-adb3-92e6c3876d4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1198704706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1198704706
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2606328880
Short name T84
Test name
Test status
Simulation time 1488850000 ps
CPU time 3.41 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 164676 kb
Host smart-e6f7d4bc-2cb3-42ec-a09a-b46ab6c0d844
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2606328880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2606328880
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3699808391
Short name T82
Test name
Test status
Simulation time 1308950000 ps
CPU time 3.79 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 164648 kb
Host smart-51456f78-b98d-4bbd-ac49-09fd1f4cd7a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699808391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3699808391
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.858038025
Short name T93
Test name
Test status
Simulation time 1461930000 ps
CPU time 2.92 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 02:52:23 PM PST 24
Peak memory 164612 kb
Host smart-8eada23c-8d41-4518-b8ef-c3f693db4d5e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=858038025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.858038025
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3174753377
Short name T105
Test name
Test status
Simulation time 1435390000 ps
CPU time 3.86 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 02:52:19 PM PST 24
Peak memory 164684 kb
Host smart-2da7f3f0-13fd-4053-8db6-42fe27f6f8fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3174753377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3174753377
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.361210212
Short name T108
Test name
Test status
Simulation time 1375010000 ps
CPU time 4 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 164612 kb
Host smart-119545f6-80bc-4c84-9895-83525327add3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=361210212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.361210212
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3271251773
Short name T96
Test name
Test status
Simulation time 1422550000 ps
CPU time 4.23 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:10 PM PST 24
Peak memory 164652 kb
Host smart-63ca3423-ff69-452c-b14d-f30a01ff9c5a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3271251773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3271251773
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1428332468
Short name T87
Test name
Test status
Simulation time 1481090000 ps
CPU time 3.64 seconds
Started Feb 21 02:51:58 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 164684 kb
Host smart-eaddcdcb-f98b-4621-9aff-b5649128a0d4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1428332468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1428332468
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3812913695
Short name T103
Test name
Test status
Simulation time 1517610000 ps
CPU time 3.14 seconds
Started Feb 21 02:51:52 PM PST 24
Finished Feb 21 02:51:59 PM PST 24
Peak memory 164688 kb
Host smart-39ee3f63-35f2-490b-9a39-aa64cc054a84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3812913695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3812913695
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2822247188
Short name T29
Test name
Test status
Simulation time 1143570000 ps
CPU time 2.69 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:56 PM PST 24
Peak memory 164628 kb
Host smart-f7fdf9d1-ea6b-495b-bb9e-70af314f92a9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2822247188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2822247188
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1818685628
Short name T120
Test name
Test status
Simulation time 1549310000 ps
CPU time 3.41 seconds
Started Feb 21 02:52:13 PM PST 24
Finished Feb 21 02:52:22 PM PST 24
Peak memory 164680 kb
Host smart-9d29b3a3-73c5-4911-a53a-1f228e260ff0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1818685628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1818685628
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.246112068
Short name T81
Test name
Test status
Simulation time 1399090000 ps
CPU time 2.84 seconds
Started Feb 21 02:52:13 PM PST 24
Finished Feb 21 02:52:20 PM PST 24
Peak memory 164612 kb
Host smart-7719fe20-50b6-461e-8ce8-51b529bbf888
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=246112068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.246112068
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3092805266
Short name T116
Test name
Test status
Simulation time 1553330000 ps
CPU time 3.39 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 02:52:11 PM PST 24
Peak memory 164680 kb
Host smart-6d7a0bb2-2135-40d8-b430-3dc684ded8c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3092805266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3092805266
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.880941157
Short name T99
Test name
Test status
Simulation time 1402310000 ps
CPU time 3.87 seconds
Started Feb 21 02:51:51 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 164588 kb
Host smart-36e0304d-4f5d-4500-94e0-d33d48d7f410
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=880941157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.880941157
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3133581602
Short name T101
Test name
Test status
Simulation time 1478610000 ps
CPU time 4.62 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 164680 kb
Host smart-479e56e3-4512-4c7e-b31e-4052756489be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133581602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3133581602
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3524276999
Short name T98
Test name
Test status
Simulation time 1370250000 ps
CPU time 5.33 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 02:52:22 PM PST 24
Peak memory 164656 kb
Host smart-a6bebc9f-bc8b-4e8b-83a8-014d606258b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3524276999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3524276999
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2737524581
Short name T94
Test name
Test status
Simulation time 1353290000 ps
CPU time 5.25 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:13 PM PST 24
Peak memory 164680 kb
Host smart-be6d39fa-6bab-4121-8a7b-4dfb0aa5fea1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2737524581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2737524581
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3877055871
Short name T106
Test name
Test status
Simulation time 1447190000 ps
CPU time 5.55 seconds
Started Feb 21 02:52:04 PM PST 24
Finished Feb 21 02:52:17 PM PST 24
Peak memory 164656 kb
Host smart-3f7a1128-3d01-4bcf-88f5-9993bbdda937
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3877055871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3877055871
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1766170643
Short name T97
Test name
Test status
Simulation time 1528010000 ps
CPU time 4.27 seconds
Started Feb 21 02:52:14 PM PST 24
Finished Feb 21 02:52:25 PM PST 24
Peak memory 164636 kb
Host smart-66aa1f71-f897-4b58-a9fc-04cad10d389c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1766170643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1766170643
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1696192460
Short name T109
Test name
Test status
Simulation time 1484790000 ps
CPU time 5.98 seconds
Started Feb 21 02:52:07 PM PST 24
Finished Feb 21 02:52:21 PM PST 24
Peak memory 164656 kb
Host smart-eed02b2d-ce03-473d-bdfc-5a8e4b19e9d8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1696192460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1696192460
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1241134837
Short name T119
Test name
Test status
Simulation time 1502830000 ps
CPU time 3.91 seconds
Started Feb 21 02:52:19 PM PST 24
Finished Feb 21 02:52:28 PM PST 24
Peak memory 164636 kb
Host smart-5464730f-c77d-490e-9f1f-cdb57e4d133a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1241134837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1241134837
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2827591841
Short name T7
Test name
Test status
Simulation time 1567110000 ps
CPU time 6 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 02:52:17 PM PST 24
Peak memory 164680 kb
Host smart-289bdcf8-efe9-4362-a316-c9cfe8b21688
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2827591841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2827591841
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2036136336
Short name T117
Test name
Test status
Simulation time 1234250000 ps
CPU time 3.71 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 02:52:25 PM PST 24
Peak memory 164636 kb
Host smart-83da7710-4d8e-4d76-bc1c-253b063fa7a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2036136336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2036136336
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2266072165
Short name T110
Test name
Test status
Simulation time 1490190000 ps
CPU time 4.13 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:52:04 PM PST 24
Peak memory 164588 kb
Host smart-39c45cc3-08e8-454b-bd88-aea06d8c3ea3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2266072165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2266072165
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2873735792
Short name T5
Test name
Test status
Simulation time 1282130000 ps
CPU time 5.05 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:13 PM PST 24
Peak memory 164680 kb
Host smart-770e0df7-5af8-491a-8f12-e6a8ef68dcb7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2873735792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2873735792
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.942860898
Short name T107
Test name
Test status
Simulation time 1508110000 ps
CPU time 3.08 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 164580 kb
Host smart-d0c7102a-0f93-4a64-96b2-bb1468c6c746
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=942860898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.942860898
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.497094470
Short name T91
Test name
Test status
Simulation time 1531310000 ps
CPU time 3.04 seconds
Started Feb 21 02:51:49 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 164612 kb
Host smart-cf9f107b-30e4-4fef-b0b9-437239203468
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=497094470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.497094470
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3430634578
Short name T89
Test name
Test status
Simulation time 1138430000 ps
CPU time 4.03 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:12 PM PST 24
Peak memory 164656 kb
Host smart-bc36b94c-5c37-460f-8c82-50e9267af573
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430634578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3430634578
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2161773318
Short name T113
Test name
Test status
Simulation time 1566510000 ps
CPU time 5.82 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:16 PM PST 24
Peak memory 164680 kb
Host smart-1a43a5bc-b75e-4c9c-a408-e631d6c79a40
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2161773318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2161773318
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.135159857
Short name T102
Test name
Test status
Simulation time 1503310000 ps
CPU time 5.9 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 02:52:23 PM PST 24
Peak memory 164588 kb
Host smart-ff6313da-dd9d-468d-805d-2ff7992eac16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=135159857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.135159857
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1883022436
Short name T27
Test name
Test status
Simulation time 1211570000 ps
CPU time 5.27 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 02:52:20 PM PST 24
Peak memory 164656 kb
Host smart-fdc29ee3-d031-4a2f-9273-801c5324cbe9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1883022436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1883022436
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.894487121
Short name T112
Test name
Test status
Simulation time 1583110000 ps
CPU time 5.74 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 02:52:23 PM PST 24
Peak memory 164588 kb
Host smart-4857181f-7e40-46e1-8723-cd617a71dfcd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=894487121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.894487121
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2949366001
Short name T114
Test name
Test status
Simulation time 1463790000 ps
CPU time 5.62 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:14 PM PST 24
Peak memory 164680 kb
Host smart-13c7b290-6059-40ea-b972-5c5cb756ef3a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2949366001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2949366001
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.826851316
Short name T83
Test name
Test status
Simulation time 1478650000 ps
CPU time 4.74 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 02:52:27 PM PST 24
Peak memory 164644 kb
Host smart-35bc7527-825a-482f-b0e8-a7201dc65b1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=826851316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.826851316
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.929049774
Short name T111
Test name
Test status
Simulation time 1409050000 ps
CPU time 4.61 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 164588 kb
Host smart-635b999f-a0a8-42b1-b52c-1149ed5ece3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=929049774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.929049774
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2564420593
Short name T115
Test name
Test status
Simulation time 1598550000 ps
CPU time 5.96 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:52:11 PM PST 24
Peak memory 164680 kb
Host smart-4c2dd4ad-fff1-4375-a5df-a53aba954635
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2564420593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2564420593
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.719799095
Short name T118
Test name
Test status
Simulation time 1408750000 ps
CPU time 5.43 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:13 PM PST 24
Peak memory 164700 kb
Host smart-763c9e01-f610-42be-9fe0-b8186cdee31f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=719799095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.719799095
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4044944293
Short name T24
Test name
Test status
Simulation time 1440790000 ps
CPU time 5.84 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 02:52:22 PM PST 24
Peak memory 164656 kb
Host smart-26734ee4-77a5-4e23-b896-e730bf50816c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044944293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.4044944293
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1281743360
Short name T6
Test name
Test status
Simulation time 1456850000 ps
CPU time 3.68 seconds
Started Feb 21 02:52:05 PM PST 24
Finished Feb 21 02:52:13 PM PST 24
Peak memory 164680 kb
Host smart-03f0a89f-e31f-4933-a6cf-36e6f4949049
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1281743360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1281743360
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3153470731
Short name T30
Test name
Test status
Simulation time 1500750000 ps
CPU time 5.77 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:15 PM PST 24
Peak memory 164680 kb
Host smart-37fe86c2-b4df-4fa4-8bbc-a4a64770f535
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3153470731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3153470731
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3860733609
Short name T86
Test name
Test status
Simulation time 1408910000 ps
CPU time 2.8 seconds
Started Feb 21 02:51:45 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 164672 kb
Host smart-0caeca5d-556f-42ff-b958-e14aa1b76d16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3860733609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3860733609
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1301723975
Short name T88
Test name
Test status
Simulation time 1544950000 ps
CPU time 5.07 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 02:52:08 PM PST 24
Peak memory 164648 kb
Host smart-17f828a0-0da2-46fd-8549-96cf475fbd00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1301723975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1301723975
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.595504378
Short name T26
Test name
Test status
Simulation time 1500850000 ps
CPU time 4.7 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 02:52:06 PM PST 24
Peak memory 164580 kb
Host smart-b22afb0e-a173-415b-a9fe-0f5eef28e39a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=595504378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.595504378
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2339932694
Short name T104
Test name
Test status
Simulation time 1387350000 ps
CPU time 5.71 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:15 PM PST 24
Peak memory 164680 kb
Host smart-0afdb9c2-20e7-400f-bf22-2244138e32a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2339932694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2339932694
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3492647723
Short name T85
Test name
Test status
Simulation time 1248030000 ps
CPU time 4 seconds
Started Feb 21 02:52:00 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 164656 kb
Host smart-b2fa9266-499e-4640-b477-624b51a639f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3492647723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3492647723
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1903652754
Short name T95
Test name
Test status
Simulation time 1294890000 ps
CPU time 2.94 seconds
Started Feb 21 02:51:45 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 164608 kb
Host smart-d982f039-346f-44ff-bb9c-97d8fb037d39
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1903652754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1903652754
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1650616658
Short name T90
Test name
Test status
Simulation time 1543390000 ps
CPU time 4.45 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:10 PM PST 24
Peak memory 164664 kb
Host smart-49889a7f-53a2-4b41-9be6-5ca80621ae50
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1650616658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1650616658
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.231544855
Short name T28
Test name
Test status
Simulation time 1370970000 ps
CPU time 4.57 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 02:52:05 PM PST 24
Peak memory 164564 kb
Host smart-ca7637cf-6e2e-41c0-9582-97dfea1e8d19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231544855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.231544855
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3569995900
Short name T92
Test name
Test status
Simulation time 1420750000 ps
CPU time 3.89 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:51 PM PST 24
Peak memory 164672 kb
Host smart-d51a2062-14b5-44ec-b5aa-ce277301734b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3569995900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3569995900
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.439866708
Short name T100
Test name
Test status
Simulation time 1297050000 ps
CPU time 3.44 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:52:06 PM PST 24
Peak memory 164580 kb
Host smart-37dd9376-352a-4d82-a87e-ee42a48ab518
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439866708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.439866708
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3857903019
Short name T46
Test name
Test status
Simulation time 1408610000 ps
CPU time 4.15 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 164664 kb
Host smart-0ee2dc60-fb38-4e20-9e5a-ad897a5e8603
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3857903019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3857903019
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4201828075
Short name T72
Test name
Test status
Simulation time 1405330000 ps
CPU time 4.03 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 164664 kb
Host smart-f5457a5e-1210-4ece-9f83-b8bf94e6e356
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201828075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4201828075
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1954287385
Short name T60
Test name
Test status
Simulation time 1539810000 ps
CPU time 4.15 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 164696 kb
Host smart-d38936ec-9185-4f49-88d3-f3964a14080d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1954287385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1954287385
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2936483769
Short name T56
Test name
Test status
Simulation time 1467350000 ps
CPU time 5.93 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 164680 kb
Host smart-3692b4ed-480c-4f1e-a5cc-aad5810957cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936483769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2936483769
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.809537685
Short name T66
Test name
Test status
Simulation time 1257690000 ps
CPU time 3.11 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 164608 kb
Host smart-481acad3-64ac-40e4-a8cb-e127629e41a8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809537685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.809537685
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3334553086
Short name T52
Test name
Test status
Simulation time 1526430000 ps
CPU time 3.32 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:48 PM PST 24
Peak memory 164648 kb
Host smart-a5287f51-3488-49c6-b29f-91e37cb788f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3334553086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3334553086
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1372787419
Short name T3
Test name
Test status
Simulation time 1435810000 ps
CPU time 3.53 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 164680 kb
Host smart-647a5810-4e91-4b92-b852-82a22505f2d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372787419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1372787419
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1335863736
Short name T42
Test name
Test status
Simulation time 1432490000 ps
CPU time 4.3 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:10 PM PST 24
Peak memory 164652 kb
Host smart-60b5a5f1-500a-4af8-811d-8ed2a99caadd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1335863736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1335863736
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2390311250
Short name T80
Test name
Test status
Simulation time 1511610000 ps
CPU time 3.73 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:59 PM PST 24
Peak memory 164524 kb
Host smart-f9de3de1-fa7f-47bb-9d5d-2d850a32af75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2390311250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2390311250
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1765639405
Short name T10
Test name
Test status
Simulation time 1469710000 ps
CPU time 3.85 seconds
Started Feb 21 02:52:09 PM PST 24
Finished Feb 21 02:52:18 PM PST 24
Peak memory 164684 kb
Host smart-4d36000e-2eff-4d6c-800b-3f9b3e97a3fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765639405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1765639405
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.208502292
Short name T65
Test name
Test status
Simulation time 1534310000 ps
CPU time 4.1 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 164588 kb
Host smart-39bf13e1-adde-4afc-b173-ece9e34ee773
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=208502292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.208502292
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3606221132
Short name T47
Test name
Test status
Simulation time 1407330000 ps
CPU time 4.19 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 164644 kb
Host smart-6f85ff6e-2fe5-4fa0-a2ab-ad14b2b266b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3606221132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3606221132
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2311952818
Short name T41
Test name
Test status
Simulation time 1586010000 ps
CPU time 5.78 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:55 PM PST 24
Peak memory 164664 kb
Host smart-7c58b689-4d11-43ac-abe2-43892fc1c4f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2311952818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2311952818
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1335531892
Short name T79
Test name
Test status
Simulation time 1522510000 ps
CPU time 5.63 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:55 PM PST 24
Peak memory 164592 kb
Host smart-f28b42a4-7445-43db-b304-11e83d17652a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1335531892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1335531892
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1907173489
Short name T74
Test name
Test status
Simulation time 1468290000 ps
CPU time 5.41 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 164600 kb
Host smart-b7ea20c2-abd7-414a-bcef-6beb4ddcf8a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907173489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1907173489
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1567685882
Short name T64
Test name
Test status
Simulation time 1484090000 ps
CPU time 3.44 seconds
Started Feb 21 02:51:27 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 164672 kb
Host smart-599b99f3-68e7-48dc-9b3d-96bb18550857
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1567685882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1567685882
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2867945089
Short name T68
Test name
Test status
Simulation time 1495070000 ps
CPU time 5.25 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:53 PM PST 24
Peak memory 164680 kb
Host smart-05b5073e-f571-4e1a-aee7-34da90dfb787
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2867945089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2867945089
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.894717476
Short name T62
Test name
Test status
Simulation time 1364850000 ps
CPU time 5.24 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 164612 kb
Host smart-cba2882a-fb4f-4ac9-96e5-381b028b94ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=894717476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.894717476
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.28912590
Short name T44
Test name
Test status
Simulation time 1513070000 ps
CPU time 6.03 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 164704 kb
Host smart-73052f6b-0c03-4e91-8a6b-322f262a1117
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=28912590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.28912590
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.793881391
Short name T49
Test name
Test status
Simulation time 1389170000 ps
CPU time 5.08 seconds
Started Feb 21 02:51:44 PM PST 24
Finished Feb 21 02:51:56 PM PST 24
Peak memory 164612 kb
Host smart-34e0788e-d734-44a5-9d95-920f93f6e3ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793881391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.793881391
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4013514126
Short name T73
Test name
Test status
Simulation time 1438050000 ps
CPU time 4.45 seconds
Started Feb 21 02:51:48 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 164676 kb
Host smart-cde54f20-48b4-4c24-a622-50afb505fa9d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4013514126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4013514126
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.325197733
Short name T75
Test name
Test status
Simulation time 1528230000 ps
CPU time 4.1 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:52:04 PM PST 24
Peak memory 164608 kb
Host smart-e4e7df4a-2320-4d7b-a4e6-1c610b5f9da0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=325197733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.325197733
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2208481690
Short name T53
Test name
Test status
Simulation time 1388690000 ps
CPU time 4.63 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 164624 kb
Host smart-cfd6ef40-ce7c-41ef-b961-a01270e003d4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208481690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2208481690
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2781057018
Short name T58
Test name
Test status
Simulation time 1395110000 ps
CPU time 4.61 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:10 PM PST 24
Peak memory 164696 kb
Host smart-938c0395-cddc-46b3-8610-f7a5ff2f8554
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2781057018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2781057018
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1231056929
Short name T57
Test name
Test status
Simulation time 1550290000 ps
CPU time 3.2 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 164656 kb
Host smart-4073a7b3-378a-4770-9f21-b8388bac6992
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231056929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1231056929
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3575581009
Short name T4
Test name
Test status
Simulation time 1409050000 ps
CPU time 3.11 seconds
Started Feb 21 02:52:05 PM PST 24
Finished Feb 21 02:52:12 PM PST 24
Peak memory 164660 kb
Host smart-99cc92c2-767c-4a69-916a-a790cf63b154
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3575581009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3575581009
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.525645276
Short name T50
Test name
Test status
Simulation time 1511110000 ps
CPU time 6.23 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 164716 kb
Host smart-7e45a873-b72e-4daa-9030-bb3f8077a296
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=525645276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.525645276
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3958375984
Short name T78
Test name
Test status
Simulation time 1259270000 ps
CPU time 5.28 seconds
Started Feb 21 02:52:04 PM PST 24
Finished Feb 21 02:52:17 PM PST 24
Peak memory 164676 kb
Host smart-27602d24-de98-48a6-bf9b-941cf9e62024
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3958375984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3958375984
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.987695080
Short name T45
Test name
Test status
Simulation time 1445670000 ps
CPU time 4.97 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:14 PM PST 24
Peak memory 164608 kb
Host smart-377bfcdf-4d6f-4d75-9376-ba384c3e94df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=987695080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.987695080
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2757910666
Short name T69
Test name
Test status
Simulation time 1447770000 ps
CPU time 4.16 seconds
Started Feb 21 02:52:07 PM PST 24
Finished Feb 21 02:52:16 PM PST 24
Peak memory 164676 kb
Host smart-45412b44-94ed-4860-a061-b20478438b3f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2757910666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2757910666
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2168363185
Short name T77
Test name
Test status
Simulation time 1543690000 ps
CPU time 4.05 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:47 PM PST 24
Peak memory 164656 kb
Host smart-4bb82526-540c-4549-8489-911fc29a03d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2168363185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2168363185
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1758979150
Short name T2
Test name
Test status
Simulation time 1450930000 ps
CPU time 5.38 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:55 PM PST 24
Peak memory 164680 kb
Host smart-aa593824-08dc-4062-9a65-2e121b9203ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1758979150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1758979150
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3617226822
Short name T51
Test name
Test status
Simulation time 1342530000 ps
CPU time 5.8 seconds
Started Feb 21 02:52:04 PM PST 24
Finished Feb 21 02:52:17 PM PST 24
Peak memory 164676 kb
Host smart-4dd90bea-dd90-4773-a587-40db14a28fc7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3617226822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3617226822
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.643548527
Short name T1
Test name
Test status
Simulation time 1169530000 ps
CPU time 4.16 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 164536 kb
Host smart-cfa688a1-32f0-4145-8b05-8e18d961780c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=643548527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.643548527
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1573037068
Short name T8
Test name
Test status
Simulation time 1518650000 ps
CPU time 5.56 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:55 PM PST 24
Peak memory 164664 kb
Host smart-f13a17ca-fc67-4555-a557-657c54e01a58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573037068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1573037068
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3530125649
Short name T67
Test name
Test status
Simulation time 1197470000 ps
CPU time 4.69 seconds
Started Feb 21 02:51:45 PM PST 24
Finished Feb 21 02:51:56 PM PST 24
Peak memory 164680 kb
Host smart-85d07985-c4e4-4d79-9851-54394cb97343
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3530125649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3530125649
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.864806768
Short name T55
Test name
Test status
Simulation time 1329270000 ps
CPU time 5.19 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 164572 kb
Host smart-c300b430-1961-426a-b1b0-0577c809133f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=864806768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.864806768
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.267987821
Short name T11
Test name
Test status
Simulation time 1407190000 ps
CPU time 5.23 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 164472 kb
Host smart-72a1831d-97ea-4098-832a-c765f17a8413
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=267987821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.267987821
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1408267993
Short name T71
Test name
Test status
Simulation time 1532670000 ps
CPU time 3.55 seconds
Started Feb 21 02:51:52 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 164676 kb
Host smart-4934848d-c93e-4394-97ae-e04204a29f52
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1408267993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1408267993
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.285772324
Short name T9
Test name
Test status
Simulation time 1305270000 ps
CPU time 5.38 seconds
Started Feb 21 02:51:48 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 164608 kb
Host smart-8cc9d506-e10e-4b38-9869-5a8264119ece
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=285772324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.285772324
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1659801567
Short name T48
Test name
Test status
Simulation time 1457170000 ps
CPU time 5.41 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 164564 kb
Host smart-cf289bb7-109b-42a5-a5bd-f4c317c27ad0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1659801567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1659801567
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4053992086
Short name T61
Test name
Test status
Simulation time 1520090000 ps
CPU time 3.38 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:10 PM PST 24
Peak memory 164660 kb
Host smart-f6aac811-4553-4b0f-af43-165d3465a71b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4053992086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4053992086
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1069137179
Short name T76
Test name
Test status
Simulation time 1175770000 ps
CPU time 4.41 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 164556 kb
Host smart-57def2ca-4974-4e2c-b920-84085f923132
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1069137179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1069137179
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2594075617
Short name T59
Test name
Test status
Simulation time 1326690000 ps
CPU time 3.29 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 164676 kb
Host smart-c19beab8-177a-4003-840d-313f0064f87f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2594075617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2594075617
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1314704670
Short name T63
Test name
Test status
Simulation time 1402770000 ps
CPU time 5.25 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:54 PM PST 24
Peak memory 164616 kb
Host smart-84a6296a-5334-4b88-bd81-705aae5dc9b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1314704670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1314704670
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2383138276
Short name T43
Test name
Test status
Simulation time 1565230000 ps
CPU time 3.96 seconds
Started Feb 21 02:51:49 PM PST 24
Finished Feb 21 02:51:59 PM PST 24
Peak memory 164644 kb
Host smart-a04dec0d-232a-47cf-bcbe-9c5e2885c4f9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383138276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2383138276
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.768947733
Short name T54
Test name
Test status
Simulation time 1519730000 ps
CPU time 4.6 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 164536 kb
Host smart-5fae1508-fd6d-47ca-b1df-4af081b3177c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=768947733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.768947733
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3897959591
Short name T70
Test name
Test status
Simulation time 1565810000 ps
CPU time 5.57 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:52:06 PM PST 24
Peak memory 164716 kb
Host smart-9b270689-6d78-4bfa-a609-1ffd6c6fb3a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3897959591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3897959591
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2930064159
Short name T12
Test name
Test status
Simulation time 1505230000 ps
CPU time 3.6 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 164636 kb
Host smart-d1958d65-3ca4-4b0a-b1b9-953689a7a94d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2930064159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2930064159
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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