Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1451974702
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1147133167
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3625539090

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1721962882
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2918866010
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1728259052
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1451219645
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1038999417
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3469005427
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1604418022
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2762631638
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3341447903
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3612454584
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.211503439
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3493462720
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.191041428
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2784868924
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3912574144
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2903889261
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3314257463
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1526967859
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1405616638
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1025700080
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3548905276
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3118932754
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3541783864
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4232147024
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2589355344
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1009749055
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3787430931
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.872155027
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.778261647
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1250585007
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1851103511
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1228006105
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4243691572
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2235100592
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3399572145
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.833475447
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.251547111
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3467516157
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2219460100
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1435016839
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2300832242
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3296485527
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1136913889
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3362483185
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2241383806
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1336974572
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4146962729
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2333132491
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3841148423
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.279428098
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1690421376
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3492477166
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2982004250
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4028786273
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.698843092
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1231287098
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3623263713
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2685294128
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1538647574
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.209420873
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2455491270
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3328084022
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1248034610
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1176202467
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.343370559
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.453854270
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.209342771
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1752883224
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4239743745
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3969712846
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3354619995
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.518347129
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2223849436
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2982737984
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1898084798
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2500935952
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2620436089
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.873369683
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2473928184
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3330898507
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3343041441
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2211856060
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1594775098
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.340280901
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1875799906
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2292287302
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3887731589
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4060411283
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2150243371
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1952327487
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1428597185
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1125742794
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3581377943
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1745544925
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3391727511
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1169976713
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1878294608
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4105057864
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.30265693
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4124388358
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2947201936
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1508790621
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2699666988
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4105148897
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3269267243
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3434356340
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2518065887
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.923848
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1616741606
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3966406429
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2078609671
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1411348192
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1536003153
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.238303150
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.116995156
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1147396906
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.690867781
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1275140321
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.351157238
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1071184722
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1385994336
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.891049198
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2885430984
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4190216687
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3459953146
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.964859429
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2048961254
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3330078918
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2133054468
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1769186503
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.396800732
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.122747350
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3471164274
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.770247574
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2409954785
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2895194059
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1322290777
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1176739515
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1457453484
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1953380224
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.522939181
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2966624973
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.200903796
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.881312275
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3154033202
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2914210184
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3438252676
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4052561386
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2349921082
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3791207379
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.592501277
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3311962576
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3429239002
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.711232173
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.37080419
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2198978915
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.111889421
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3060745687
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2919826454
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3434888364
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2171882916
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.158689904
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.982623613
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.768277059
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3290138591
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1749946198
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1902593069
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1022944975
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1137652119
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2383760783
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4192264020
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3323564492
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.39761874
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.433368917
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.377383805
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2595128005
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3271919718
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1215836721
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1087587459
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1690153172
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1473876769
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4149441122
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3902796267
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.325518056
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.455154404
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.943415633
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3144821470
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2321788029
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4284810102
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1658505321
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.298268313
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1981060572
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1273172759
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.359478434
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.644333269
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4252748133
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.998790644



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.982623613 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:12 PM PST 24 1462270000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1451974702 Mar 05 01:17:53 PM PST 24 Mar 05 01:18:03 PM PST 24 1357730000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1902593069 Mar 05 01:18:00 PM PST 24 Mar 05 01:18:13 PM PST 24 1519490000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1215836721 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:09 PM PST 24 1091450000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3311962576 Mar 05 01:17:56 PM PST 24 Mar 05 01:18:07 PM PST 24 1463170000 ps
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T130 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1875799906 Mar 05 12:25:29 PM PST 24 Mar 05 01:03:01 PM PST 24 337011010000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1745544925 Mar 05 12:19:12 PM PST 24 Mar 05 12:53:21 PM PST 24 336665850000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1428597185 Mar 05 12:25:28 PM PST 24 Mar 05 01:03:16 PM PST 24 336774630000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.518347129 Mar 05 12:24:25 PM PST 24 Mar 05 12:54:53 PM PST 24 336564290000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1125742794 Mar 05 12:25:18 PM PST 24 Mar 05 01:00:51 PM PST 24 336605770000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3343041441 Mar 05 12:23:17 PM PST 24 Mar 05 12:56:21 PM PST 24 336795230000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3328084022 Mar 05 12:25:17 PM PST 24 Mar 05 12:59:44 PM PST 24 336798310000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3623263713 Mar 05 12:23:36 PM PST 24 Mar 05 12:52:24 PM PST 24 336876670000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.453854270 Mar 05 12:25:23 PM PST 24 Mar 05 12:51:05 PM PST 24 336639510000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.279428098 Mar 05 12:25:25 PM PST 24 Mar 05 01:01:26 PM PST 24 336747530000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1231287098 Mar 05 12:24:24 PM PST 24 Mar 05 12:55:21 PM PST 24 336482290000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2685294128 Mar 05 12:18:51 PM PST 24 Mar 05 12:52:46 PM PST 24 336318870000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1169976713 Mar 05 12:24:36 PM PST 24 Mar 05 12:51:26 PM PST 24 336449450000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1248034610 Mar 05 12:25:17 PM PST 24 Mar 05 12:58:49 PM PST 24 336489690000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2292287302 Mar 05 12:25:29 PM PST 24 Mar 05 01:03:13 PM PST 24 336701010000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1538647574 Mar 05 12:23:09 PM PST 24 Mar 05 12:54:38 PM PST 24 336397990000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3887731589 Mar 05 12:25:29 PM PST 24 Mar 05 12:56:24 PM PST 24 336919610000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1690421376 Mar 05 12:25:26 PM PST 24 Mar 05 01:00:58 PM PST 24 336686150000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2500935952 Mar 05 12:19:14 PM PST 24 Mar 05 12:49:19 PM PST 24 336758310000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2211856060 Mar 05 12:20:33 PM PST 24 Mar 05 12:54:55 PM PST 24 336272030000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3581377943 Mar 05 12:25:18 PM PST 24 Mar 05 01:00:15 PM PST 24 337000970000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3459953146 Mar 05 01:18:07 PM PST 24 Mar 05 01:18:15 PM PST 24 1127710000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1322290777 Mar 05 01:18:07 PM PST 24 Mar 05 01:18:16 PM PST 24 1279770000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2409954785 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:16 PM PST 24 1444410000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3438252676 Mar 05 01:18:02 PM PST 24 Mar 05 01:18:14 PM PST 24 1457210000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.964859429 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:14 PM PST 24 1492610000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2048961254 Mar 05 01:18:07 PM PST 24 Mar 05 01:18:17 PM PST 24 1522850000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1071184722 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:11 PM PST 24 1421830000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3966406429 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:13 PM PST 24 1314370000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.522939181 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:14 PM PST 24 1484930000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.770247574 Mar 05 01:18:14 PM PST 24 Mar 05 01:18:24 PM PST 24 1565510000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1508790621 Mar 05 01:18:08 PM PST 24 Mar 05 01:18:17 PM PST 24 1523150000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4190216687 Mar 05 01:18:21 PM PST 24 Mar 05 01:18:29 PM PST 24 1406490000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2947201936 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:13 PM PST 24 1542290000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1385994336 Mar 05 01:18:12 PM PST 24 Mar 05 01:18:20 PM PST 24 1151390000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.351157238 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:13 PM PST 24 1402230000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2914210184 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:12 PM PST 24 1392070000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.923848 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:14 PM PST 24 1481450000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2966624973 Mar 05 01:18:05 PM PST 24 Mar 05 01:18:16 PM PST 24 1573730000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1953380224 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:11 PM PST 24 1344190000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3154033202 Mar 05 01:17:58 PM PST 24 Mar 05 01:18:06 PM PST 24 1399910000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1176739515 Mar 05 01:18:13 PM PST 24 Mar 05 01:18:24 PM PST 24 1188270000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4124388358 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:12 PM PST 24 1314750000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2518065887 Mar 05 01:18:02 PM PST 24 Mar 05 01:18:15 PM PST 24 1543930000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.200903796 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:14 PM PST 24 1609270000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.881312275 Mar 05 01:18:00 PM PST 24 Mar 05 01:18:10 PM PST 24 1300550000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2699666988 Mar 05 01:18:05 PM PST 24 Mar 05 01:18:14 PM PST 24 1319450000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.116995156 Mar 05 01:18:02 PM PST 24 Mar 05 01:18:11 PM PST 24 1403990000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1275140321 Mar 05 01:18:06 PM PST 24 Mar 05 01:18:16 PM PST 24 1551550000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1769186503 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:15 PM PST 24 1345470000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2133054468 Mar 05 01:18:07 PM PST 24 Mar 05 01:18:18 PM PST 24 1367110000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1147396906 Mar 05 01:18:05 PM PST 24 Mar 05 01:18:19 PM PST 24 1587750000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1616741606 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:16 PM PST 24 1526490000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.891049198 Mar 05 01:18:05 PM PST 24 Mar 05 01:18:16 PM PST 24 1499910000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4052561386 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:14 PM PST 24 1531750000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2895194059 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:14 PM PST 24 1396950000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4105148897 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:16 PM PST 24 1514550000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.238303150 Mar 05 01:18:08 PM PST 24 Mar 05 01:18:18 PM PST 24 1536130000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2885430984 Mar 05 01:18:05 PM PST 24 Mar 05 01:18:19 PM PST 24 1525450000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.690867781 Mar 05 01:18:06 PM PST 24 Mar 05 01:18:17 PM PST 24 1368350000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3269267243 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:15 PM PST 24 1564930000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3330078918 Mar 05 01:18:05 PM PST 24 Mar 05 01:18:13 PM PST 24 1474370000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.30265693 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:11 PM PST 24 1345970000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2078609671 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:11 PM PST 24 1303470000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.122747350 Mar 05 01:18:01 PM PST 24 Mar 05 01:18:16 PM PST 24 1543850000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1411348192 Mar 05 01:18:04 PM PST 24 Mar 05 01:18:15 PM PST 24 1560670000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3471164274 Mar 05 01:18:00 PM PST 24 Mar 05 01:18:12 PM PST 24 1321150000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.396800732 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:14 PM PST 24 1394470000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3434356340 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:16 PM PST 24 1521130000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1536003153 Mar 05 01:18:03 PM PST 24 Mar 05 01:18:14 PM PST 24 1548710000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1457453484 Mar 05 01:18:06 PM PST 24 Mar 05 01:18:16 PM PST 24 1316230000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1451974702
Short name T2
Test name
Test status
Simulation time 1357730000 ps
CPU time 4.64 seconds
Started Mar 05 01:17:53 PM PST 24
Finished Mar 05 01:18:03 PM PST 24
Peak memory 164620 kb
Host smart-fc186b4b-6f79-493d-83b2-21c22cfff1cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1451974702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1451974702
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1147133167
Short name T18
Test name
Test status
Simulation time 336959390000 ps
CPU time 991.33 seconds
Started Mar 05 12:44:57 PM PST 24
Finished Mar 05 01:25:47 PM PST 24
Peak memory 160772 kb
Host smart-ab978c64-70b4-4a05-9e5e-e1b67e619334
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1147133167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1147133167
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3625539090
Short name T25
Test name
Test status
Simulation time 336653790000 ps
CPU time 841.7 seconds
Started Mar 05 12:25:25 PM PST 24
Finished Mar 05 01:00:02 PM PST 24
Peak memory 160064 kb
Host smart-5e2e7083-9a8d-435e-af3e-8f01e819ed28
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625539090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3625539090
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1721962882
Short name T81
Test name
Test status
Simulation time 336344670000 ps
CPU time 680.12 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 01:12:58 PM PST 24
Peak memory 160684 kb
Host smart-3527594b-6fa5-4d80-a67e-04783f50bc16
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1721962882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1721962882
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2918866010
Short name T78
Test name
Test status
Simulation time 336283990000 ps
CPU time 1085.67 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 01:31:30 PM PST 24
Peak memory 160684 kb
Host smart-1a710c9d-e215-4617-8015-088dc754a020
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2918866010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2918866010
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1728259052
Short name T72
Test name
Test status
Simulation time 336405590000 ps
CPU time 930.63 seconds
Started Mar 05 12:44:45 PM PST 24
Finished Mar 05 01:22:57 PM PST 24
Peak memory 160692 kb
Host smart-c8911538-c3da-4463-9c7d-e42cb0afa89a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1728259052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1728259052
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1451219645
Short name T88
Test name
Test status
Simulation time 336747930000 ps
CPU time 1117.51 seconds
Started Mar 05 12:44:56 PM PST 24
Finished Mar 05 01:31:58 PM PST 24
Peak memory 160776 kb
Host smart-e03dccfe-fae5-4701-9dc4-aeb3524affa0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1451219645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1451219645
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1038999417
Short name T82
Test name
Test status
Simulation time 336398550000 ps
CPU time 1105.58 seconds
Started Mar 05 12:44:42 PM PST 24
Finished Mar 05 01:31:49 PM PST 24
Peak memory 160776 kb
Host smart-5a28edee-726f-40f8-a7b4-e3c86fa12fc0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1038999417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1038999417
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3469005427
Short name T99
Test name
Test status
Simulation time 336671730000 ps
CPU time 1043.08 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:30:13 PM PST 24
Peak memory 160692 kb
Host smart-cb43889b-f878-46d6-8521-ad40b12a8ac5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3469005427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3469005427
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1604418022
Short name T107
Test name
Test status
Simulation time 336557650000 ps
CPU time 1118.17 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 01:31:55 PM PST 24
Peak memory 160776 kb
Host smart-35094a9e-150c-4594-a719-56cdd8342a60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1604418022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1604418022
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2762631638
Short name T98
Test name
Test status
Simulation time 336803590000 ps
CPU time 950.3 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 01:23:16 PM PST 24
Peak memory 160692 kb
Host smart-7380aa89-019a-41aa-8f5d-11ac28b28e42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2762631638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2762631638
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3341447903
Short name T84
Test name
Test status
Simulation time 336629610000 ps
CPU time 993.86 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 01:28:06 PM PST 24
Peak memory 160692 kb
Host smart-48b224df-9f44-4b2f-b416-34dfc518569a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3341447903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3341447903
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3612454584
Short name T85
Test name
Test status
Simulation time 336846530000 ps
CPU time 1035.77 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:30:05 PM PST 24
Peak memory 160692 kb
Host smart-58b7c6d3-f0b9-4c94-9cc4-74861d55c8f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3612454584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3612454584
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.211503439
Short name T19
Test name
Test status
Simulation time 336417210000 ps
CPU time 1079.98 seconds
Started Mar 05 12:44:34 PM PST 24
Finished Mar 05 01:29:59 PM PST 24
Peak memory 160764 kb
Host smart-95f6788a-ad1f-4e31-a166-099ac53859f5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=211503439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.211503439
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3493462720
Short name T5
Test name
Test status
Simulation time 336850210000 ps
CPU time 1089.27 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 01:31:35 PM PST 24
Peak memory 160684 kb
Host smart-eef930d7-73e3-4e83-8b94-befda8dc5e2f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3493462720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3493462720
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.191041428
Short name T109
Test name
Test status
Simulation time 336746510000 ps
CPU time 1044.79 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:30:15 PM PST 24
Peak memory 160660 kb
Host smart-dd9296c5-14ef-4322-b434-4aa3277fbb82
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=191041428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.191041428
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2784868924
Short name T77
Test name
Test status
Simulation time 336713290000 ps
CPU time 1066.62 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 01:31:20 PM PST 24
Peak memory 160692 kb
Host smart-19873fef-468b-4569-96fe-1747d4bf8c59
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2784868924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2784868924
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3912574144
Short name T92
Test name
Test status
Simulation time 336798470000 ps
CPU time 1050.84 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:31:11 PM PST 24
Peak memory 160692 kb
Host smart-157109e3-ba3d-4604-9f62-579b93ebe408
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3912574144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3912574144
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2903889261
Short name T80
Test name
Test status
Simulation time 336807490000 ps
CPU time 1044.72 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 01:30:25 PM PST 24
Peak memory 160692 kb
Host smart-0d3b58fc-7f5f-43a0-a133-9855c70aad4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2903889261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2903889261
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3314257463
Short name T93
Test name
Test status
Simulation time 336858270000 ps
CPU time 1116.32 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:31:54 PM PST 24
Peak memory 160692 kb
Host smart-69ca4bac-8746-477d-abab-206fe94a8d02
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3314257463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3314257463
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1526967859
Short name T101
Test name
Test status
Simulation time 336384850000 ps
CPU time 761.37 seconds
Started Mar 05 12:44:29 PM PST 24
Finished Mar 05 01:15:16 PM PST 24
Peak memory 160772 kb
Host smart-887be6b1-e2be-48b2-8282-20f7b0adb1d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526967859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1526967859
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1405616638
Short name T86
Test name
Test status
Simulation time 336715130000 ps
CPU time 1097.85 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 01:31:28 PM PST 24
Peak memory 160692 kb
Host smart-3b4bd06d-c2ac-4bdb-87e2-0b30619fbcfb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1405616638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1405616638
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1025700080
Short name T83
Test name
Test status
Simulation time 336649670000 ps
CPU time 1056.78 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:30:13 PM PST 24
Peak memory 160692 kb
Host smart-8223dadc-ee4d-4ea5-9902-5da154b6ce26
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1025700080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1025700080
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3548905276
Short name T97
Test name
Test status
Simulation time 336782510000 ps
CPU time 968.06 seconds
Started Mar 05 12:45:00 PM PST 24
Finished Mar 05 01:27:39 PM PST 24
Peak memory 160692 kb
Host smart-8536113b-8ba5-4d9b-88e5-c2f3fa6f4bda
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3548905276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3548905276
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3118932754
Short name T94
Test name
Test status
Simulation time 336874510000 ps
CPU time 1021.52 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:27:43 PM PST 24
Peak memory 160692 kb
Host smart-0be11c85-2c7b-4807-b6c2-f47878725595
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3118932754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3118932754
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3541783864
Short name T95
Test name
Test status
Simulation time 336990170000 ps
CPU time 1115.3 seconds
Started Mar 05 12:44:43 PM PST 24
Finished Mar 05 01:31:48 PM PST 24
Peak memory 160768 kb
Host smart-3a07e019-f9fd-48b9-a0db-c81f255c821c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3541783864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3541783864
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4232147024
Short name T73
Test name
Test status
Simulation time 336629570000 ps
CPU time 985.13 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 01:27:38 PM PST 24
Peak memory 160692 kb
Host smart-782927eb-ae6a-4344-94f3-504f57cfbc1d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4232147024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4232147024
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2589355344
Short name T108
Test name
Test status
Simulation time 336447690000 ps
CPU time 923.93 seconds
Started Mar 05 12:44:42 PM PST 24
Finished Mar 05 01:23:27 PM PST 24
Peak memory 160768 kb
Host smart-e3d8250d-abe0-4f51-bac9-75284b143f68
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2589355344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2589355344
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1009749055
Short name T103
Test name
Test status
Simulation time 336607790000 ps
CPU time 1022.58 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:26:52 PM PST 24
Peak memory 160772 kb
Host smart-cfb74149-de00-4cdc-9893-bb56ec4fd3d0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1009749055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1009749055
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3787430931
Short name T6
Test name
Test status
Simulation time 336775410000 ps
CPU time 997.42 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:28:07 PM PST 24
Peak memory 160692 kb
Host smart-a823701f-bfc1-4bb8-b719-2371dfbd6ad9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3787430931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3787430931
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.872155027
Short name T14
Test name
Test status
Simulation time 336963910000 ps
CPU time 1105.65 seconds
Started Mar 05 12:44:42 PM PST 24
Finished Mar 05 01:31:34 PM PST 24
Peak memory 160764 kb
Host smart-7d1d9316-14c5-4231-a0a2-60f59f229b93
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=872155027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.872155027
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.778261647
Short name T90
Test name
Test status
Simulation time 336869250000 ps
CPU time 1114.34 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:31:53 PM PST 24
Peak memory 160680 kb
Host smart-712749d2-cb12-443b-b5fe-d7a73b4bc3cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=778261647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.778261647
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1250585007
Short name T16
Test name
Test status
Simulation time 336514050000 ps
CPU time 991.42 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 01:27:45 PM PST 24
Peak memory 160692 kb
Host smart-4fcae910-6dcf-4ad9-990b-bbd1db950a24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1250585007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1250585007
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1851103511
Short name T104
Test name
Test status
Simulation time 336985990000 ps
CPU time 1022.03 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 01:27:49 PM PST 24
Peak memory 160692 kb
Host smart-59cc7927-0b00-4b22-a626-b5a87a240734
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1851103511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1851103511
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1228006105
Short name T75
Test name
Test status
Simulation time 336720430000 ps
CPU time 1020.76 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:29:42 PM PST 24
Peak memory 160692 kb
Host smart-18db874d-6c2d-4cad-a2b9-ff3672650599
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1228006105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1228006105
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4243691572
Short name T71
Test name
Test status
Simulation time 336372610000 ps
CPU time 795.05 seconds
Started Mar 05 12:44:43 PM PST 24
Finished Mar 05 01:18:24 PM PST 24
Peak memory 160768 kb
Host smart-33838370-8389-4083-a19f-11df1a93148e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4243691572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4243691572
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2235100592
Short name T7
Test name
Test status
Simulation time 336736310000 ps
CPU time 1106.63 seconds
Started Mar 05 12:44:47 PM PST 24
Finished Mar 05 01:31:54 PM PST 24
Peak memory 160768 kb
Host smart-5c10fd67-fb41-4ba6-819b-37f85d846351
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2235100592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2235100592
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3399572145
Short name T79
Test name
Test status
Simulation time 336693270000 ps
CPU time 915.22 seconds
Started Mar 05 12:44:46 PM PST 24
Finished Mar 05 01:23:10 PM PST 24
Peak memory 160768 kb
Host smart-70737b06-9f7f-49f3-8e04-3a80282dbc22
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3399572145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3399572145
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.833475447
Short name T100
Test name
Test status
Simulation time 336509470000 ps
CPU time 1051.07 seconds
Started Mar 05 12:44:46 PM PST 24
Finished Mar 05 01:30:00 PM PST 24
Peak memory 160680 kb
Host smart-d3c4a143-a8b8-4e51-9d9e-e4d370633b6e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=833475447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.833475447
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.251547111
Short name T91
Test name
Test status
Simulation time 336376350000 ps
CPU time 743.83 seconds
Started Mar 05 12:44:57 PM PST 24
Finished Mar 05 01:17:25 PM PST 24
Peak memory 160756 kb
Host smart-0779b9c4-b2e1-4881-84af-d9f7293d77bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=251547111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.251547111
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3467516157
Short name T96
Test name
Test status
Simulation time 336986750000 ps
CPU time 999.11 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:25:45 PM PST 24
Peak memory 160772 kb
Host smart-ee8ac70a-f22a-45f9-99dc-d9a3c4441980
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3467516157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3467516157
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2219460100
Short name T87
Test name
Test status
Simulation time 336902950000 ps
CPU time 765.6 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:17:59 PM PST 24
Peak memory 160768 kb
Host smart-eb075fef-e896-47b4-8832-d4ed31168c1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2219460100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2219460100
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1435016839
Short name T74
Test name
Test status
Simulation time 336468150000 ps
CPU time 1032.51 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 01:27:13 PM PST 24
Peak memory 160772 kb
Host smart-131e7b95-429b-40e3-a314-a5bc737f8302
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1435016839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1435016839
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2300832242
Short name T102
Test name
Test status
Simulation time 336985850000 ps
CPU time 744.14 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 01:17:45 PM PST 24
Peak memory 160772 kb
Host smart-1680c180-e2cc-43ab-9a86-f421f5ae2a42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2300832242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2300832242
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3296485527
Short name T89
Test name
Test status
Simulation time 336482130000 ps
CPU time 1043.87 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:27:17 PM PST 24
Peak memory 160768 kb
Host smart-48f118db-8f15-4343-aa0d-68ace6f239da
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3296485527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3296485527
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1136913889
Short name T106
Test name
Test status
Simulation time 336644930000 ps
CPU time 733.21 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 01:15:18 PM PST 24
Peak memory 160788 kb
Host smart-87ce1ff6-45d4-4357-912c-8bf46c380ad6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1136913889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1136913889
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3362483185
Short name T17
Test name
Test status
Simulation time 336980450000 ps
CPU time 719.61 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 01:14:25 PM PST 24
Peak memory 160776 kb
Host smart-7c1dc748-5beb-4ccc-a177-3e64c3fc90e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3362483185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3362483185
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2241383806
Short name T20
Test name
Test status
Simulation time 336963770000 ps
CPU time 927.86 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 160684 kb
Host smart-92670800-b953-40c7-95f8-730892aa70c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2241383806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2241383806
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1336974572
Short name T15
Test name
Test status
Simulation time 336273130000 ps
CPU time 964 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:27:37 PM PST 24
Peak memory 160684 kb
Host smart-4b3e1b2c-3148-4247-95c1-813fa6c1bf37
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1336974572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1336974572
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4146962729
Short name T110
Test name
Test status
Simulation time 336919570000 ps
CPU time 706.64 seconds
Started Mar 05 12:44:46 PM PST 24
Finished Mar 05 01:13:35 PM PST 24
Peak memory 160780 kb
Host smart-303f8812-21e9-4b7f-9df3-9701ad22f4b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4146962729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4146962729
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2333132491
Short name T105
Test name
Test status
Simulation time 336668790000 ps
CPU time 1004 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:26:15 PM PST 24
Peak memory 160764 kb
Host smart-18fadbf0-dc71-42ec-ab67-74eb7180d3c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2333132491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2333132491
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3841148423
Short name T76
Test name
Test status
Simulation time 337079550000 ps
CPU time 985.8 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:30:27 PM PST 24
Peak memory 160684 kb
Host smart-63ed52b0-7f46-4ec3-80fe-084c1aa6edb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3841148423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3841148423
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.279428098
Short name T139
Test name
Test status
Simulation time 336747530000 ps
CPU time 892.4 seconds
Started Mar 05 12:25:25 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 160064 kb
Host smart-bc181c9e-5f76-405f-8a71-c2ead6e6141d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=279428098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.279428098
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1690421376
Short name T147
Test name
Test status
Simulation time 336686150000 ps
CPU time 866.29 seconds
Started Mar 05 12:25:26 PM PST 24
Finished Mar 05 01:00:58 PM PST 24
Peak memory 160076 kb
Host smart-9d941810-3a03-4562-89ce-360764cbb13d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1690421376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1690421376
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3492477166
Short name T23
Test name
Test status
Simulation time 336875870000 ps
CPU time 873.57 seconds
Started Mar 05 12:25:25 PM PST 24
Finished Mar 05 01:00:57 PM PST 24
Peak memory 160076 kb
Host smart-0429421f-3f07-470e-96c5-9909ae516cd6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3492477166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3492477166
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2982004250
Short name T122
Test name
Test status
Simulation time 336536330000 ps
CPU time 752.42 seconds
Started Mar 05 12:23:17 PM PST 24
Finished Mar 05 12:54:49 PM PST 24
Peak memory 160020 kb
Host smart-dff46daf-4c4a-4022-99d7-1389ad54ce30
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2982004250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2982004250
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4028786273
Short name T117
Test name
Test status
Simulation time 336391010000 ps
CPU time 613.33 seconds
Started Mar 05 12:23:34 PM PST 24
Finished Mar 05 12:49:41 PM PST 24
Peak memory 159472 kb
Host smart-020b75c4-80e9-4ca3-9f11-840d80acc825
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4028786273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4028786273
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.698843092
Short name T26
Test name
Test status
Simulation time 336655630000 ps
CPU time 738.89 seconds
Started Mar 05 12:24:16 PM PST 24
Finished Mar 05 12:55:06 PM PST 24
Peak memory 159024 kb
Host smart-1076c085-1c6d-44fe-af83-0c362d9fb1e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=698843092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.698843092
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1231287098
Short name T140
Test name
Test status
Simulation time 336482290000 ps
CPU time 746.47 seconds
Started Mar 05 12:24:24 PM PST 24
Finished Mar 05 12:55:21 PM PST 24
Peak memory 160072 kb
Host smart-99e9034d-2bc7-48f6-8bb1-5815b2cf0d0e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1231287098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1231287098
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3623263713
Short name T137
Test name
Test status
Simulation time 336876670000 ps
CPU time 691.73 seconds
Started Mar 05 12:23:36 PM PST 24
Finished Mar 05 12:52:24 PM PST 24
Peak memory 159472 kb
Host smart-767df1cb-a36b-45a3-857f-5293e3eaebdc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3623263713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3623263713
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2685294128
Short name T141
Test name
Test status
Simulation time 336318870000 ps
CPU time 830.49 seconds
Started Mar 05 12:18:51 PM PST 24
Finished Mar 05 12:52:46 PM PST 24
Peak memory 160636 kb
Host smart-29a999ba-a3b3-4c97-8a21-dbb694dfa4f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2685294128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2685294128
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1538647574
Short name T145
Test name
Test status
Simulation time 336397990000 ps
CPU time 748.2 seconds
Started Mar 05 12:23:09 PM PST 24
Finished Mar 05 12:54:38 PM PST 24
Peak memory 159048 kb
Host smart-bd1122a5-3560-47d8-8ff4-636fc3e90aa2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1538647574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1538647574
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.209420873
Short name T128
Test name
Test status
Simulation time 336347170000 ps
CPU time 680.02 seconds
Started Mar 05 12:20:56 PM PST 24
Finished Mar 05 12:49:00 PM PST 24
Peak memory 160628 kb
Host smart-273f934a-c662-4b19-b951-58da2e15cdab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=209420873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.209420873
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2455491270
Short name T114
Test name
Test status
Simulation time 336780670000 ps
CPU time 738.73 seconds
Started Mar 05 12:24:25 PM PST 24
Finished Mar 05 12:55:01 PM PST 24
Peak memory 160068 kb
Host smart-62e18ad7-ca83-4153-99d2-fc103ae87c01
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2455491270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2455491270
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3328084022
Short name T136
Test name
Test status
Simulation time 336798310000 ps
CPU time 840.15 seconds
Started Mar 05 12:25:17 PM PST 24
Finished Mar 05 12:59:44 PM PST 24
Peak memory 158372 kb
Host smart-7bd49b45-030d-4399-bfe9-71f65f155d42
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328084022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3328084022
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1248034610
Short name T143
Test name
Test status
Simulation time 336489690000 ps
CPU time 809.25 seconds
Started Mar 05 12:25:17 PM PST 24
Finished Mar 05 12:58:49 PM PST 24
Peak memory 158808 kb
Host smart-6a01c542-313b-424e-baca-7a85b4618934
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1248034610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1248034610
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1176202467
Short name T125
Test name
Test status
Simulation time 336911990000 ps
CPU time 616.54 seconds
Started Mar 05 12:24:36 PM PST 24
Finished Mar 05 12:50:00 PM PST 24
Peak memory 160100 kb
Host smart-02719888-bcb2-4480-b2fa-657b0fe6b2cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1176202467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1176202467
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.343370559
Short name T113
Test name
Test status
Simulation time 336413810000 ps
CPU time 664.68 seconds
Started Mar 05 12:24:46 PM PST 24
Finished Mar 05 12:52:52 PM PST 24
Peak memory 158944 kb
Host smart-c1803a19-c001-4edb-99ab-3c2478d52867
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=343370559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.343370559
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.453854270
Short name T138
Test name
Test status
Simulation time 336639510000 ps
CPU time 621.9 seconds
Started Mar 05 12:25:23 PM PST 24
Finished Mar 05 12:51:05 PM PST 24
Peak memory 160040 kb
Host smart-dee93d6b-40e5-451b-9f61-0775f3b6a811
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=453854270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.453854270
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.209342771
Short name T119
Test name
Test status
Simulation time 336663090000 ps
CPU time 621.61 seconds
Started Mar 05 12:25:24 PM PST 24
Finished Mar 05 12:51:03 PM PST 24
Peak memory 160092 kb
Host smart-e3b626db-3663-446f-95c2-1988d991856d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=209342771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.209342771
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1752883224
Short name T115
Test name
Test status
Simulation time 337023730000 ps
CPU time 740.08 seconds
Started Mar 05 12:19:14 PM PST 24
Finished Mar 05 12:49:38 PM PST 24
Peak memory 160668 kb
Host smart-a68b6c35-76fb-4245-9557-3b1ed2fb955d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1752883224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1752883224
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4239743745
Short name T127
Test name
Test status
Simulation time 336575670000 ps
CPU time 685.84 seconds
Started Mar 05 12:23:56 PM PST 24
Finished Mar 05 12:52:08 PM PST 24
Peak memory 160748 kb
Host smart-cab743d3-168e-499a-8b57-5d6f7b09094d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4239743745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4239743745
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3969712846
Short name T126
Test name
Test status
Simulation time 337018790000 ps
CPU time 549.82 seconds
Started Mar 05 12:25:33 PM PST 24
Finished Mar 05 12:48:41 PM PST 24
Peak memory 159472 kb
Host smart-e167cd11-8a40-452d-bbe5-58567334c6ad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3969712846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3969712846
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3354619995
Short name T24
Test name
Test status
Simulation time 336900970000 ps
CPU time 686.51 seconds
Started Mar 05 12:24:46 PM PST 24
Finished Mar 05 12:53:18 PM PST 24
Peak memory 158372 kb
Host smart-3f638998-f97f-46a1-8877-f2f363cb17c5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3354619995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3354619995
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.518347129
Short name T133
Test name
Test status
Simulation time 336564290000 ps
CPU time 729.39 seconds
Started Mar 05 12:24:25 PM PST 24
Finished Mar 05 12:54:53 PM PST 24
Peak memory 160068 kb
Host smart-cbfd2278-ee52-4a91-8a1b-98eaea2b26f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=518347129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.518347129
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2223849436
Short name T116
Test name
Test status
Simulation time 337111310000 ps
CPU time 673.47 seconds
Started Mar 05 12:24:46 PM PST 24
Finished Mar 05 12:53:01 PM PST 24
Peak memory 158784 kb
Host smart-f9ae823e-cb05-4579-9bc6-e1cf28311f56
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2223849436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2223849436
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2982737984
Short name T120
Test name
Test status
Simulation time 336917010000 ps
CPU time 676.08 seconds
Started Mar 05 12:24:46 PM PST 24
Finished Mar 05 12:53:11 PM PST 24
Peak memory 158448 kb
Host smart-eda9401b-4a92-4932-8d15-302c5088c132
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2982737984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2982737984
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1898084798
Short name T29
Test name
Test status
Simulation time 336542910000 ps
CPU time 559.72 seconds
Started Mar 05 12:28:10 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 159472 kb
Host smart-8a10d51b-dee7-4bcf-8bf3-7c6e60e5b000
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1898084798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1898084798
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2500935952
Short name T148
Test name
Test status
Simulation time 336758310000 ps
CPU time 732.61 seconds
Started Mar 05 12:19:14 PM PST 24
Finished Mar 05 12:49:19 PM PST 24
Peak memory 160668 kb
Host smart-acb00522-17eb-471c-9819-6d5224249f19
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2500935952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2500935952
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2620436089
Short name T27
Test name
Test status
Simulation time 336495770000 ps
CPU time 825.96 seconds
Started Mar 05 12:25:17 PM PST 24
Finished Mar 05 12:59:31 PM PST 24
Peak memory 158504 kb
Host smart-2edf25a8-322e-4bcc-81e6-87a5cc2fcedf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2620436089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2620436089
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.873369683
Short name T123
Test name
Test status
Simulation time 336429950000 ps
CPU time 738.14 seconds
Started Mar 05 12:23:18 PM PST 24
Finished Mar 05 12:54:10 PM PST 24
Peak memory 160008 kb
Host smart-26d5761e-4847-451a-baf9-4b1e15eb04b1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=873369683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.873369683
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2473928184
Short name T30
Test name
Test status
Simulation time 336600970000 ps
CPU time 794.37 seconds
Started Mar 05 12:23:17 PM PST 24
Finished Mar 05 12:55:50 PM PST 24
Peak memory 160020 kb
Host smart-ba76dab4-eefb-42d9-a132-b420982fecc0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2473928184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2473928184
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3330898507
Short name T112
Test name
Test status
Simulation time 337013550000 ps
CPU time 736.16 seconds
Started Mar 05 12:23:09 PM PST 24
Finished Mar 05 12:54:17 PM PST 24
Peak memory 159076 kb
Host smart-ac1c29ef-3f94-47a8-a192-a50877cb9066
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3330898507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3330898507
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3343041441
Short name T135
Test name
Test status
Simulation time 336795230000 ps
CPU time 809.03 seconds
Started Mar 05 12:23:17 PM PST 24
Finished Mar 05 12:56:21 PM PST 24
Peak memory 160020 kb
Host smart-dd8b0b56-f5b7-4efb-a54c-ad23e9bf5ece
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3343041441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3343041441
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2211856060
Short name T149
Test name
Test status
Simulation time 336272030000 ps
CPU time 835.24 seconds
Started Mar 05 12:20:33 PM PST 24
Finished Mar 05 12:54:55 PM PST 24
Peak memory 160636 kb
Host smart-ef4d79e5-4fae-4cac-bcb9-703eed41feed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2211856060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2211856060
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1594775098
Short name T124
Test name
Test status
Simulation time 337020350000 ps
CPU time 699.7 seconds
Started Mar 05 12:24:16 PM PST 24
Finished Mar 05 12:53:35 PM PST 24
Peak memory 159040 kb
Host smart-ce357e7a-6691-4de1-a636-268d2b4717b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1594775098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1594775098
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.340280901
Short name T129
Test name
Test status
Simulation time 336818710000 ps
CPU time 590.86 seconds
Started Mar 05 12:24:59 PM PST 24
Finished Mar 05 12:49:46 PM PST 24
Peak memory 159460 kb
Host smart-d7804e4d-80f5-41f6-b5d5-a008a4c6e555
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=340280901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.340280901
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1875799906
Short name T130
Test name
Test status
Simulation time 337011010000 ps
CPU time 895.49 seconds
Started Mar 05 12:25:29 PM PST 24
Finished Mar 05 01:03:01 PM PST 24
Peak memory 159900 kb
Host smart-a9cc5a50-1346-4e6b-95cd-7887e161e810
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1875799906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1875799906
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2292287302
Short name T144
Test name
Test status
Simulation time 336701010000 ps
CPU time 903.25 seconds
Started Mar 05 12:25:29 PM PST 24
Finished Mar 05 01:03:13 PM PST 24
Peak memory 159924 kb
Host smart-0ec57acb-fefd-4d65-a96d-ed9a1a0937bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292287302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2292287302
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3887731589
Short name T146
Test name
Test status
Simulation time 336919610000 ps
CPU time 730.51 seconds
Started Mar 05 12:25:29 PM PST 24
Finished Mar 05 12:56:24 PM PST 24
Peak memory 159472 kb
Host smart-931a2c5c-f8c7-4eb0-8105-3600106fd0dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3887731589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3887731589
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4060411283
Short name T28
Test name
Test status
Simulation time 336616550000 ps
CPU time 851.46 seconds
Started Mar 05 12:25:18 PM PST 24
Finished Mar 05 01:00:41 PM PST 24
Peak memory 158376 kb
Host smart-ae2999a2-a81c-4994-89f6-b08384a12a97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4060411283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4060411283
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2150243371
Short name T21
Test name
Test status
Simulation time 337055310000 ps
CPU time 895.89 seconds
Started Mar 05 12:25:28 PM PST 24
Finished Mar 05 01:02:59 PM PST 24
Peak memory 158352 kb
Host smart-134ee601-6ee5-40ed-840d-115bd01468ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2150243371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2150243371
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1952327487
Short name T111
Test name
Test status
Simulation time 336670770000 ps
CPU time 897.93 seconds
Started Mar 05 12:25:28 PM PST 24
Finished Mar 05 01:03:05 PM PST 24
Peak memory 158380 kb
Host smart-049c411a-e525-4ce4-a684-6ff9855723c6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1952327487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1952327487
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1428597185
Short name T132
Test name
Test status
Simulation time 336774630000 ps
CPU time 905.96 seconds
Started Mar 05 12:25:28 PM PST 24
Finished Mar 05 01:03:16 PM PST 24
Peak memory 158388 kb
Host smart-495bb8ec-1c73-427c-8e05-6f8b46ada667
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1428597185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1428597185
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1125742794
Short name T134
Test name
Test status
Simulation time 336605770000 ps
CPU time 858.06 seconds
Started Mar 05 12:25:18 PM PST 24
Finished Mar 05 01:00:51 PM PST 24
Peak memory 158556 kb
Host smart-80a65889-0238-4625-947a-fdf46a0b039f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1125742794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1125742794
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3581377943
Short name T150
Test name
Test status
Simulation time 337000970000 ps
CPU time 833.48 seconds
Started Mar 05 12:25:18 PM PST 24
Finished Mar 05 01:00:15 PM PST 24
Peak memory 158688 kb
Host smart-666a114e-d133-4a3d-8b12-686bed55a978
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3581377943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3581377943
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1745544925
Short name T131
Test name
Test status
Simulation time 336665850000 ps
CPU time 833.72 seconds
Started Mar 05 12:19:12 PM PST 24
Finished Mar 05 12:53:21 PM PST 24
Peak memory 160628 kb
Host smart-c7805d3e-744c-4757-9be8-737676b066d3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1745544925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1745544925
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3391727511
Short name T118
Test name
Test status
Simulation time 336796210000 ps
CPU time 702.45 seconds
Started Mar 05 12:21:08 PM PST 24
Finished Mar 05 12:49:49 PM PST 24
Peak memory 160428 kb
Host smart-65ee3e69-a11f-43c8-8295-e5dfb4cfa258
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3391727511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3391727511
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1169976713
Short name T142
Test name
Test status
Simulation time 336449450000 ps
CPU time 648.82 seconds
Started Mar 05 12:24:36 PM PST 24
Finished Mar 05 12:51:26 PM PST 24
Peak memory 160044 kb
Host smart-19465c6c-f501-40ef-aa3b-d533bb29e136
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1169976713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1169976713
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1878294608
Short name T121
Test name
Test status
Simulation time 336423070000 ps
CPU time 854.52 seconds
Started Mar 05 12:25:26 PM PST 24
Finished Mar 05 01:00:44 PM PST 24
Peak memory 160068 kb
Host smart-5c5b742d-f9c5-47db-bace-d25ca92696b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1878294608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1878294608
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.4105057864
Short name T22
Test name
Test status
Simulation time 336521850000 ps
CPU time 839.04 seconds
Started Mar 05 12:25:25 PM PST 24
Finished Mar 05 12:59:54 PM PST 24
Peak memory 160004 kb
Host smart-f6900b4d-1014-4a46-a61b-7620b14a26e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4105057864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.4105057864
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.30265693
Short name T192
Test name
Test status
Simulation time 1345970000 ps
CPU time 4.2 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164636 kb
Host smart-fc557c02-ca3f-4d15-8ace-52a5294cc856
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30265693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.30265693
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4124388358
Short name T172
Test name
Test status
Simulation time 1314750000 ps
CPU time 4.71 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164640 kb
Host smart-417ce638-9bc3-4dec-9e5f-a0e8d6fbb90e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4124388358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.4124388358
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2947201936
Short name T163
Test name
Test status
Simulation time 1542290000 ps
CPU time 4.91 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164656 kb
Host smart-a19f32a3-29ac-49fc-9c37-1ff7ee8dc8da
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2947201936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2947201936
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1508790621
Short name T161
Test name
Test status
Simulation time 1523150000 ps
CPU time 4.03 seconds
Started Mar 05 01:18:08 PM PST 24
Finished Mar 05 01:18:17 PM PST 24
Peak memory 164652 kb
Host smart-2a4cc08f-8edd-4773-980d-572930c2cb7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1508790621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1508790621
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2699666988
Short name T176
Test name
Test status
Simulation time 1319450000 ps
CPU time 3.83 seconds
Started Mar 05 01:18:05 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164556 kb
Host smart-7cf7a746-3ae3-4e7d-ac72-579fd9fba669
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2699666988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2699666988
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4105148897
Short name T186
Test name
Test status
Simulation time 1514550000 ps
CPU time 5.43 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164644 kb
Host smart-dddb6312-2855-49fb-b0cc-5096c5ab47ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4105148897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4105148897
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3269267243
Short name T190
Test name
Test status
Simulation time 1564930000 ps
CPU time 5.05 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:15 PM PST 24
Peak memory 164644 kb
Host smart-7efa403c-48fd-4d5a-923f-6438c4d0f4de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3269267243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3269267243
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3434356340
Short name T198
Test name
Test status
Simulation time 1521130000 ps
CPU time 6.04 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164660 kb
Host smart-c422be80-954b-4adb-b62b-481282081991
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3434356340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3434356340
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2518065887
Short name T173
Test name
Test status
Simulation time 1543930000 ps
CPU time 5.32 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:15 PM PST 24
Peak memory 164552 kb
Host smart-77ddb070-6ab5-44dc-8592-c63ecee7e454
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2518065887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2518065887
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.923848
Short name T167
Test name
Test status
Simulation time 1481450000 ps
CPU time 4.88 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164648 kb
Host smart-63a929cf-2b50-4b6f-b32a-ec16ba354587
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=923848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.923848
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1616741606
Short name T182
Test name
Test status
Simulation time 1526490000 ps
CPU time 4.87 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164644 kb
Host smart-7a005f1e-e2d8-4267-9ad7-d53473ebbae8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1616741606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1616741606
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3966406429
Short name T158
Test name
Test status
Simulation time 1314370000 ps
CPU time 4.38 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164660 kb
Host smart-614b0ee5-661a-49e5-aa56-560a15a466be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3966406429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3966406429
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2078609671
Short name T193
Test name
Test status
Simulation time 1303470000 ps
CPU time 4.32 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164656 kb
Host smart-1a2e194e-d6da-4465-a1fe-d6992d1d225b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2078609671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2078609671
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1411348192
Short name T195
Test name
Test status
Simulation time 1560670000 ps
CPU time 4.83 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:15 PM PST 24
Peak memory 164648 kb
Host smart-9def9408-2eea-4c5f-bf65-bdd4c8c168fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1411348192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1411348192
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1536003153
Short name T199
Test name
Test status
Simulation time 1548710000 ps
CPU time 4.79 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164644 kb
Host smart-cb0548cd-3086-443c-8f21-a66af6537484
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1536003153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1536003153
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.238303150
Short name T187
Test name
Test status
Simulation time 1536130000 ps
CPU time 4.3 seconds
Started Mar 05 01:18:08 PM PST 24
Finished Mar 05 01:18:18 PM PST 24
Peak memory 164580 kb
Host smart-12648394-30b3-496b-83fb-3159a4aca5ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=238303150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.238303150
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.116995156
Short name T177
Test name
Test status
Simulation time 1403990000 ps
CPU time 3.94 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164656 kb
Host smart-0a7dc166-647b-431c-8f8e-8ceb4bcd7054
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=116995156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.116995156
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1147396906
Short name T181
Test name
Test status
Simulation time 1587750000 ps
CPU time 5.43 seconds
Started Mar 05 01:18:05 PM PST 24
Finished Mar 05 01:18:19 PM PST 24
Peak memory 164584 kb
Host smart-7657c7dd-1488-4142-9cc3-c29447d562b7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147396906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1147396906
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.690867781
Short name T189
Test name
Test status
Simulation time 1368350000 ps
CPU time 4.86 seconds
Started Mar 05 01:18:06 PM PST 24
Finished Mar 05 01:18:17 PM PST 24
Peak memory 164516 kb
Host smart-4742ee03-eb00-44c7-9f76-cebc3d5eae3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=690867781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.690867781
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1275140321
Short name T178
Test name
Test status
Simulation time 1551550000 ps
CPU time 4.31 seconds
Started Mar 05 01:18:06 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164688 kb
Host smart-6ac575cc-28e0-4d29-b692-7534117d8776
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1275140321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1275140321
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.351157238
Short name T165
Test name
Test status
Simulation time 1402230000 ps
CPU time 3.47 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164552 kb
Host smart-94701134-ee1a-48cc-bedc-96538a3dad13
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351157238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.351157238
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1071184722
Short name T157
Test name
Test status
Simulation time 1421830000 ps
CPU time 4.6 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164712 kb
Host smart-df48a35c-ff3a-4786-a308-fa937a29ac06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1071184722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1071184722
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1385994336
Short name T164
Test name
Test status
Simulation time 1151390000 ps
CPU time 3.64 seconds
Started Mar 05 01:18:12 PM PST 24
Finished Mar 05 01:18:20 PM PST 24
Peak memory 164712 kb
Host smart-5c5313ef-9817-4c8b-9789-e0469f337a97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1385994336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1385994336
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.891049198
Short name T183
Test name
Test status
Simulation time 1499910000 ps
CPU time 4.93 seconds
Started Mar 05 01:18:05 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164644 kb
Host smart-57aa4ff9-f2ea-45cc-b33c-2982588f8976
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=891049198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.891049198
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2885430984
Short name T188
Test name
Test status
Simulation time 1525450000 ps
CPU time 5.55 seconds
Started Mar 05 01:18:05 PM PST 24
Finished Mar 05 01:18:19 PM PST 24
Peak memory 164584 kb
Host smart-dba7bff4-6257-42d0-bf29-66f2951d1d8b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2885430984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2885430984
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4190216687
Short name T162
Test name
Test status
Simulation time 1406490000 ps
CPU time 3.57 seconds
Started Mar 05 01:18:21 PM PST 24
Finished Mar 05 01:18:29 PM PST 24
Peak memory 164584 kb
Host smart-be6e1b35-d026-42d5-af1c-39ca8f41dfba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4190216687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4190216687
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3459953146
Short name T151
Test name
Test status
Simulation time 1127710000 ps
CPU time 3.62 seconds
Started Mar 05 01:18:07 PM PST 24
Finished Mar 05 01:18:15 PM PST 24
Peak memory 164644 kb
Host smart-eb3636c9-0b34-4b80-ac17-c69cdb994564
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459953146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3459953146
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.964859429
Short name T155
Test name
Test status
Simulation time 1492610000 ps
CPU time 5.47 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164604 kb
Host smart-3f923a91-7d37-4c9d-9482-686eae700591
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=964859429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.964859429
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2048961254
Short name T156
Test name
Test status
Simulation time 1522850000 ps
CPU time 4.45 seconds
Started Mar 05 01:18:07 PM PST 24
Finished Mar 05 01:18:17 PM PST 24
Peak memory 164644 kb
Host smart-5f778f0e-bddf-4e8e-9b4d-fb6e21d700de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2048961254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2048961254
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3330078918
Short name T191
Test name
Test status
Simulation time 1474370000 ps
CPU time 3.6 seconds
Started Mar 05 01:18:05 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164620 kb
Host smart-cf5a8e4e-7812-4b53-90a2-14122057d2d1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3330078918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3330078918
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2133054468
Short name T180
Test name
Test status
Simulation time 1367110000 ps
CPU time 4.9 seconds
Started Mar 05 01:18:07 PM PST 24
Finished Mar 05 01:18:18 PM PST 24
Peak memory 164512 kb
Host smart-447fddc9-097b-437c-93f9-801342359053
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2133054468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2133054468
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1769186503
Short name T179
Test name
Test status
Simulation time 1345470000 ps
CPU time 4.81 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:15 PM PST 24
Peak memory 164644 kb
Host smart-87718344-27ee-4bb3-a815-8b470301070c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769186503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1769186503
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.396800732
Short name T197
Test name
Test status
Simulation time 1394470000 ps
CPU time 4.63 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164600 kb
Host smart-7e80a079-77b2-4024-8d3b-8b6da4e69cda
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396800732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.396800732
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.122747350
Short name T194
Test name
Test status
Simulation time 1543850000 ps
CPU time 6.05 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164420 kb
Host smart-03ef063c-ca96-4c52-8c1d-ecbc4f377a5c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122747350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.122747350
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3471164274
Short name T196
Test name
Test status
Simulation time 1321150000 ps
CPU time 5.12 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164580 kb
Host smart-cd5183ca-cda5-4709-9856-74457dc3191c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3471164274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3471164274
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.770247574
Short name T160
Test name
Test status
Simulation time 1565510000 ps
CPU time 4.12 seconds
Started Mar 05 01:18:14 PM PST 24
Finished Mar 05 01:18:24 PM PST 24
Peak memory 164516 kb
Host smart-175c7fb2-18c7-448c-80d9-d8791f89f2e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=770247574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.770247574
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2409954785
Short name T153
Test name
Test status
Simulation time 1444410000 ps
CPU time 5.52 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164644 kb
Host smart-9359c108-800a-4010-abf8-6141bb384124
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409954785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2409954785
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2895194059
Short name T185
Test name
Test status
Simulation time 1396950000 ps
CPU time 4.1 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164648 kb
Host smart-535f56dd-a113-43df-93e4-b93920ad6469
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895194059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2895194059
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1322290777
Short name T152
Test name
Test status
Simulation time 1279770000 ps
CPU time 4.09 seconds
Started Mar 05 01:18:07 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164644 kb
Host smart-f3c00932-3758-4153-b923-796d5aaabad4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322290777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1322290777
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1176739515
Short name T171
Test name
Test status
Simulation time 1188270000 ps
CPU time 4.3 seconds
Started Mar 05 01:18:13 PM PST 24
Finished Mar 05 01:18:24 PM PST 24
Peak memory 164584 kb
Host smart-4a47a1dd-764b-4fc9-8471-ac0a2d525c23
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1176739515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1176739515
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1457453484
Short name T200
Test name
Test status
Simulation time 1316230000 ps
CPU time 4.5 seconds
Started Mar 05 01:18:06 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164644 kb
Host smart-a76c8aa6-b4e3-4c2c-88f5-31576f2adae1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457453484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1457453484
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1953380224
Short name T169
Test name
Test status
Simulation time 1344190000 ps
CPU time 3.97 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164584 kb
Host smart-1d8398cb-88d3-48f2-ba32-8473f20655b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1953380224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1953380224
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.522939181
Short name T159
Test name
Test status
Simulation time 1484930000 ps
CPU time 4.24 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164608 kb
Host smart-abc4edf1-b840-4a64-9897-0d768c4e256a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=522939181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.522939181
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2966624973
Short name T168
Test name
Test status
Simulation time 1573730000 ps
CPU time 4.54 seconds
Started Mar 05 01:18:05 PM PST 24
Finished Mar 05 01:18:16 PM PST 24
Peak memory 164648 kb
Host smart-9833c9ab-7b90-4a5a-8d1e-5dd95a91ff35
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2966624973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2966624973
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.200903796
Short name T174
Test name
Test status
Simulation time 1609270000 ps
CPU time 4.23 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164568 kb
Host smart-a391a2e5-8604-4853-bb5f-2a5a466e546c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=200903796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.200903796
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.881312275
Short name T175
Test name
Test status
Simulation time 1300550000 ps
CPU time 4.44 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:10 PM PST 24
Peak memory 164696 kb
Host smart-02f451ee-ba23-46a2-831f-5c21fdf54ce0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881312275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.881312275
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3154033202
Short name T170
Test name
Test status
Simulation time 1399910000 ps
CPU time 3.68 seconds
Started Mar 05 01:17:58 PM PST 24
Finished Mar 05 01:18:06 PM PST 24
Peak memory 164708 kb
Host smart-c7ae98e6-7606-4738-871b-b7c3457d38e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3154033202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3154033202
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2914210184
Short name T166
Test name
Test status
Simulation time 1392070000 ps
CPU time 4.77 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164672 kb
Host smart-f206be90-002f-4347-95aa-8c869c3391fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2914210184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2914210184
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3438252676
Short name T154
Test name
Test status
Simulation time 1457210000 ps
CPU time 4.72 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164640 kb
Host smart-2122d257-70f9-4bb9-b083-25b55885d8e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3438252676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3438252676
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4052561386
Short name T184
Test name
Test status
Simulation time 1531750000 ps
CPU time 4.36 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164648 kb
Host smart-0a01fd46-6115-4697-8a18-ac33c4220951
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4052561386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.4052561386
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2349921082
Short name T54
Test name
Test status
Simulation time 1304410000 ps
CPU time 3.84 seconds
Started Mar 05 01:17:53 PM PST 24
Finished Mar 05 01:18:02 PM PST 24
Peak memory 164564 kb
Host smart-23163367-00ef-4ddd-9daf-12b4dcd40f13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349921082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2349921082
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3791207379
Short name T68
Test name
Test status
Simulation time 1459130000 ps
CPU time 3.61 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164632 kb
Host smart-bf788d32-7a6f-457d-bf5f-97b7609a1256
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3791207379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3791207379
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.592501277
Short name T60
Test name
Test status
Simulation time 1499710000 ps
CPU time 4.91 seconds
Started Mar 05 01:17:58 PM PST 24
Finished Mar 05 01:18:10 PM PST 24
Peak memory 164484 kb
Host smart-727ea05f-67e7-4ba3-970c-9b4e5ce1b330
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=592501277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.592501277
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3311962576
Short name T8
Test name
Test status
Simulation time 1463170000 ps
CPU time 4.91 seconds
Started Mar 05 01:17:56 PM PST 24
Finished Mar 05 01:18:07 PM PST 24
Peak memory 164672 kb
Host smart-4fce9216-46c8-42c6-8436-daf54c026b82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3311962576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3311962576
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3429239002
Short name T41
Test name
Test status
Simulation time 1342430000 ps
CPU time 4.57 seconds
Started Mar 05 01:17:58 PM PST 24
Finished Mar 05 01:18:08 PM PST 24
Peak memory 164620 kb
Host smart-ec8bdadf-b2e2-49f5-b01b-b558427c3848
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429239002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3429239002
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.711232173
Short name T12
Test name
Test status
Simulation time 1492890000 ps
CPU time 5.21 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164536 kb
Host smart-c09abeaa-0112-4a81-b57d-fe5c74d96e54
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711232173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.711232173
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.37080419
Short name T62
Test name
Test status
Simulation time 1443210000 ps
CPU time 5.06 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164560 kb
Host smart-acff5643-309d-45af-a56e-e4535ec0ec1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=37080419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.37080419
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2198978915
Short name T64
Test name
Test status
Simulation time 1406110000 ps
CPU time 4.75 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:10 PM PST 24
Peak memory 164672 kb
Host smart-b15a5ebb-b26a-4865-92c5-29bc74e3eb2c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2198978915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2198978915
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.111889421
Short name T9
Test name
Test status
Simulation time 1259170000 ps
CPU time 3.86 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:08 PM PST 24
Peak memory 164568 kb
Host smart-302bb5cb-1134-4afd-b381-241b06316566
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111889421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.111889421
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3060745687
Short name T11
Test name
Test status
Simulation time 1622510000 ps
CPU time 4.57 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:10 PM PST 24
Peak memory 164620 kb
Host smart-c739515f-bbe8-40f7-a0d0-a00155d00921
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060745687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3060745687
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2919826454
Short name T31
Test name
Test status
Simulation time 1541230000 ps
CPU time 4.16 seconds
Started Mar 05 01:17:58 PM PST 24
Finished Mar 05 01:18:07 PM PST 24
Peak memory 164568 kb
Host smart-4ffd393e-a50f-4090-8a32-b6dceac3f30f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2919826454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2919826454
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3434888364
Short name T67
Test name
Test status
Simulation time 1520690000 ps
CPU time 4.37 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:09 PM PST 24
Peak memory 164632 kb
Host smart-dd1b5882-fea7-4a5a-b3f8-967e18332350
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3434888364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3434888364
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2171882916
Short name T50
Test name
Test status
Simulation time 1301690000 ps
CPU time 4.94 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164584 kb
Host smart-232dfa77-5b87-4e47-8ca4-ecfe73898508
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2171882916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2171882916
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.158689904
Short name T33
Test name
Test status
Simulation time 1492370000 ps
CPU time 5.47 seconds
Started Mar 05 01:17:58 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164516 kb
Host smart-f246abfc-b45b-4a99-8902-a90c7140b5f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=158689904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.158689904
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.982623613
Short name T1
Test name
Test status
Simulation time 1462270000 ps
CPU time 4.69 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164596 kb
Host smart-a9858fec-17ae-419d-b1ab-e16a12a6f051
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982623613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.982623613
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.768277059
Short name T40
Test name
Test status
Simulation time 1557150000 ps
CPU time 4.07 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164496 kb
Host smart-38422edd-83fb-49d6-9dcf-ab3a01c8bc4f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=768277059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.768277059
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3290138591
Short name T46
Test name
Test status
Simulation time 1441790000 ps
CPU time 4.98 seconds
Started Mar 05 01:17:57 PM PST 24
Finished Mar 05 01:18:08 PM PST 24
Peak memory 164616 kb
Host smart-a6374e9e-a730-4e28-8f6b-46505e040df9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3290138591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3290138591
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1749946198
Short name T38
Test name
Test status
Simulation time 1166710000 ps
CPU time 3.99 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164700 kb
Host smart-24b864ca-ff02-49ee-a791-6b719d11e8b6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1749946198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1749946198
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1902593069
Short name T3
Test name
Test status
Simulation time 1519490000 ps
CPU time 5.64 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164584 kb
Host smart-53515c7c-1dbf-4134-b079-d20096496a4d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1902593069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1902593069
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1022944975
Short name T52
Test name
Test status
Simulation time 1441850000 ps
CPU time 4.14 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164664 kb
Host smart-8a3be93e-92e7-462e-9125-8c94c5f0bb60
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1022944975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1022944975
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1137652119
Short name T36
Test name
Test status
Simulation time 1501630000 ps
CPU time 4.15 seconds
Started Mar 05 01:18:03 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164564 kb
Host smart-0c72bb5b-d628-4b0e-ba44-2c23325c9344
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1137652119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1137652119
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2383760783
Short name T13
Test name
Test status
Simulation time 1444490000 ps
CPU time 5.69 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164672 kb
Host smart-b6ad8581-86b2-402e-bedc-4b8d03cb1aed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383760783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2383760783
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4192264020
Short name T69
Test name
Test status
Simulation time 1511510000 ps
CPU time 5.63 seconds
Started Mar 05 01:17:57 PM PST 24
Finished Mar 05 01:18:10 PM PST 24
Peak memory 164580 kb
Host smart-94ddfef2-f5ff-4b56-ab13-16aa80b98c8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192264020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.4192264020
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3323564492
Short name T59
Test name
Test status
Simulation time 1425630000 ps
CPU time 4.29 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:09 PM PST 24
Peak memory 164548 kb
Host smart-6b5bfbbd-e9d7-4051-a2cc-f84084943d00
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3323564492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3323564492
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.39761874
Short name T37
Test name
Test status
Simulation time 1561310000 ps
CPU time 4.99 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164712 kb
Host smart-0dc513e9-ec85-46b2-8ed2-da1eacb06fe1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39761874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.39761874
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.433368917
Short name T48
Test name
Test status
Simulation time 1536150000 ps
CPU time 5.43 seconds
Started Mar 05 01:17:58 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164420 kb
Host smart-fc0819df-3771-4a55-af76-ef26d1820a5f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433368917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.433368917
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.377383805
Short name T63
Test name
Test status
Simulation time 1276850000 ps
CPU time 4.98 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164608 kb
Host smart-4e75c92d-65da-4754-95ce-96d27eeda8a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=377383805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.377383805
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2595128005
Short name T65
Test name
Test status
Simulation time 1456490000 ps
CPU time 5.34 seconds
Started Mar 05 01:17:55 PM PST 24
Finished Mar 05 01:18:07 PM PST 24
Peak memory 164664 kb
Host smart-3b2a3b4c-459c-45bc-a1c6-40a3187596a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595128005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2595128005
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3271919718
Short name T42
Test name
Test status
Simulation time 1492550000 ps
CPU time 4.72 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:10 PM PST 24
Peak memory 164688 kb
Host smart-99f1d288-7122-4a9a-ac3e-5b7bbcf83610
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3271919718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3271919718
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1215836721
Short name T4
Test name
Test status
Simulation time 1091450000 ps
CPU time 3.84 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:09 PM PST 24
Peak memory 164644 kb
Host smart-c8b8f64b-25a9-4875-880d-d4fd1748a584
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1215836721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1215836721
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1087587459
Short name T57
Test name
Test status
Simulation time 1482090000 ps
CPU time 5.02 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164668 kb
Host smart-e0e5bf08-15cb-4169-b4b1-5d40ecffd755
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087587459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1087587459
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1690153172
Short name T49
Test name
Test status
Simulation time 1461250000 ps
CPU time 4.64 seconds
Started Mar 05 01:17:57 PM PST 24
Finished Mar 05 01:18:07 PM PST 24
Peak memory 164644 kb
Host smart-0e2a6ea1-d50d-4af7-af61-00ff056aae17
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1690153172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1690153172
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1473876769
Short name T10
Test name
Test status
Simulation time 1173490000 ps
CPU time 3.49 seconds
Started Mar 05 01:18:04 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164564 kb
Host smart-536cd873-9565-4fcf-a4f2-44be9830d3b3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1473876769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1473876769
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4149441122
Short name T66
Test name
Test status
Simulation time 1385650000 ps
CPU time 4.96 seconds
Started Mar 05 01:17:56 PM PST 24
Finished Mar 05 01:18:06 PM PST 24
Peak memory 164616 kb
Host smart-e41d578c-e6df-4aae-a8fc-cc810f595a57
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149441122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.4149441122
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3902796267
Short name T56
Test name
Test status
Simulation time 1547670000 ps
CPU time 5.24 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164644 kb
Host smart-aea621be-dde4-46c9-a9e2-86cc36a3438d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3902796267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3902796267
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.325518056
Short name T58
Test name
Test status
Simulation time 1447890000 ps
CPU time 5.18 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164536 kb
Host smart-2e5a89d0-5dcb-48b4-ad83-e56cfd926469
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=325518056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.325518056
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.455154404
Short name T55
Test name
Test status
Simulation time 1387550000 ps
CPU time 5.21 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164516 kb
Host smart-96925e44-859a-4a45-861e-441d5390e709
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=455154404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.455154404
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.943415633
Short name T61
Test name
Test status
Simulation time 1571570000 ps
CPU time 5.1 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164600 kb
Host smart-bbb1b83a-6c1b-4265-9705-1ff25b1c9b6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=943415633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.943415633
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3144821470
Short name T53
Test name
Test status
Simulation time 1510870000 ps
CPU time 5.23 seconds
Started Mar 05 01:18:01 PM PST 24
Finished Mar 05 01:18:13 PM PST 24
Peak memory 164676 kb
Host smart-3afed2fd-8ce3-4469-9f0d-dc543663d097
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3144821470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3144821470
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2321788029
Short name T70
Test name
Test status
Simulation time 1538810000 ps
CPU time 4.62 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164644 kb
Host smart-3628af62-adcb-4e7b-8fa1-a0448b4bc80a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2321788029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2321788029
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4284810102
Short name T34
Test name
Test status
Simulation time 1642130000 ps
CPU time 4.55 seconds
Started Mar 05 01:18:06 PM PST 24
Finished Mar 05 01:18:17 PM PST 24
Peak memory 164712 kb
Host smart-ee50e769-ceed-47c6-9330-8ac893f8799f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284810102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4284810102
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1658505321
Short name T35
Test name
Test status
Simulation time 1586190000 ps
CPU time 5.81 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:12 PM PST 24
Peak memory 164676 kb
Host smart-32236e30-7555-47a6-85e9-d445339b00d5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658505321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1658505321
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.298268313
Short name T39
Test name
Test status
Simulation time 1491370000 ps
CPU time 5.17 seconds
Started Mar 05 01:18:02 PM PST 24
Finished Mar 05 01:18:14 PM PST 24
Peak memory 164576 kb
Host smart-a673cbdf-8e8e-4604-b48f-63f00c9226ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298268313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.298268313
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1981060572
Short name T47
Test name
Test status
Simulation time 1555790000 ps
CPU time 4.79 seconds
Started Mar 05 01:18:00 PM PST 24
Finished Mar 05 01:18:11 PM PST 24
Peak memory 164688 kb
Host smart-04eea66d-9968-4a77-97ac-51545bd68b74
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981060572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1981060572
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1273172759
Short name T43
Test name
Test status
Simulation time 1238890000 ps
CPU time 3.83 seconds
Started Mar 05 01:17:59 PM PST 24
Finished Mar 05 01:18:08 PM PST 24
Peak memory 164632 kb
Host smart-8230dd46-d543-4091-bf59-02ec8d211c21
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273172759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1273172759
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.359478434
Short name T32
Test name
Test status
Simulation time 1247270000 ps
CPU time 3.25 seconds
Started Mar 05 01:17:53 PM PST 24
Finished Mar 05 01:18:01 PM PST 24
Peak memory 164680 kb
Host smart-820d0933-b10c-47b3-8c02-4c302e8d9321
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=359478434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.359478434
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.644333269
Short name T44
Test name
Test status
Simulation time 1430510000 ps
CPU time 4.62 seconds
Started Mar 05 01:17:57 PM PST 24
Finished Mar 05 01:18:08 PM PST 24
Peak memory 164684 kb
Host smart-637a23dc-d6ed-4be4-89a4-e1dd4ce7175c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=644333269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.644333269
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4252748133
Short name T45
Test name
Test status
Simulation time 1541510000 ps
CPU time 5.65 seconds
Started Mar 05 01:17:55 PM PST 24
Finished Mar 05 01:18:07 PM PST 24
Peak memory 164616 kb
Host smart-abfe5ab4-be00-49be-92e0-364380ec9728
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252748133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.4252748133
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.998790644
Short name T51
Test name
Test status
Simulation time 1472330000 ps
CPU time 4.88 seconds
Started Mar 05 01:17:57 PM PST 24
Finished Mar 05 01:18:08 PM PST 24
Peak memory 164680 kb
Host smart-b287d9fa-3817-4143-829b-b1fd4f73e01f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=998790644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.998790644
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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