Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4117595737
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1369030539
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4104433254

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2162584452
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1843037693
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.731751367
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1520783905
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3848386353
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3374236704
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1670746233
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3721496623
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1326509084
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1771499063
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3318423085
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.836442143
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1657723620
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.820771638
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2547380748
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2948987803
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3789129672
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.299296139
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2580364262
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3238665494
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1150254397
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2595688883
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4291619159
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3778200382
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2594761486
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.392882020
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1186723555
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.356026773
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1686410675
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2924495656
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3989209240
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2703764451
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1753597813
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3721708738
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3508138429
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2072557963
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.99521482
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1199791249
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3276283511
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4155758085
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1164396641
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.771248906
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3252611546
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.778078682
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2521977670
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1072314687
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1568263741
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1118365891
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1946400273
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.534168576
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1881484721
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4102428145
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4002692194
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1598611988
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1278181687
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3405403489
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3213808685
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3781291222
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3614656614
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2184164520
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3159195436
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.403489962
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.867149199
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2664220867
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1617266827
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1586354737
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.767439205
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.652943672
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1909038943
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3190565457
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3814792672
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4249719402
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1081811770
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3889938
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1269732120
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3293847064
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1767987809
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1332971710
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1964856584
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2871746336
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2006174731
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.271759344
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3776345780
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.572266614
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1583555104
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1529354782
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1182574172
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2141549809
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1160044041
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.962407549
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1482245733
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.896319245
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3546488231
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.920157254
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.485253259
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2175716140
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2783088616
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.466410843
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4229632263
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3151041574
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3432006070
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1558374019
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1730403096
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2772598512
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3972938778
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.220280444
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.923810130
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3694459517
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1136396902
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.739041808
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.584460601
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4288499210
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3996756907
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3950730498
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1964070697
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3967116500
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2234516503
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4120944803
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2396763
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3387198325
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3077397128
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1436140196
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1962314483
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3005100048
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3730816189
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1886993746
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1721771137
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2837047763
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3568862729
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1725566711
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.931427835
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1721356239
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.502264983
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3368187866
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.970022853
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.192211939
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3556844589
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4137980482
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2817744230
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2881726758
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3769645232
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3047883665
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3552760531
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2819502188
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1209931715
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.988697240
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.124479551
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1423901008
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3364992442
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1407680625
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3814899959
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.178512548
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1160914074
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.268780028
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2873155208
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1208424690
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1410917817
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3069244504
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2231691116
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1720299929
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1002551839
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2391289742
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2241192822
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.265632637
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3259182028
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3123715995
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1304421979
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3594517047
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3529314768
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2104260940
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3661670897
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1083822836
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2282836132
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3151423180
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4098373940
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3422461166
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3533144151
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3671586270
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2575764910
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2115118902
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.298036988
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.398375905
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1586779286
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1901148530
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2481922006
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1568684209
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1000441371
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2385032349
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3825728413
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3972681091
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2262750136
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1701549322
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.303319056
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.553469159
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2401219874
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1764519899
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4097856733



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1002551839 Mar 10 01:12:05 PM PDT 24 Mar 10 01:12:13 PM PDT 24 1513450000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1701549322 Mar 10 01:12:11 PM PDT 24 Mar 10 01:12:24 PM PDT 24 1587290000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2385032349 Mar 10 01:12:09 PM PDT 24 Mar 10 01:12:20 PM PDT 24 1472850000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.303319056 Mar 10 01:12:00 PM PDT 24 Mar 10 01:12:10 PM PDT 24 1332910000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4117595737 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:11 PM PDT 24 1564630000 ps
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T34 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3529314768 Mar 10 01:12:06 PM PDT 24 Mar 10 01:12:15 PM PDT 24 1401590000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2231691116 Mar 10 01:11:58 PM PDT 24 Mar 10 01:12:09 PM PDT 24 1525070000 ps
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T45 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4097856733 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:10 PM PDT 24 1367190000 ps
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T59 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3069244504 Mar 10 01:12:04 PM PDT 24 Mar 10 01:12:17 PM PDT 24 1542410000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1083822836 Mar 10 01:12:06 PM PDT 24 Mar 10 01:12:17 PM PDT 24 1496650000 ps
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T63 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3259182028 Mar 10 01:12:04 PM PDT 24 Mar 10 01:12:14 PM PDT 24 1466930000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1410917817 Mar 10 01:12:01 PM PDT 24 Mar 10 01:12:12 PM PDT 24 1463870000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2282836132 Mar 10 01:12:05 PM PDT 24 Mar 10 01:12:12 PM PDT 24 1153970000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3364992442 Mar 10 01:12:02 PM PDT 24 Mar 10 01:12:10 PM PDT 24 1366930000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1304421979 Mar 10 01:12:07 PM PDT 24 Mar 10 01:12:18 PM PDT 24 1605770000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3825728413 Mar 10 01:12:14 PM PDT 24 Mar 10 01:12:23 PM PDT 24 1386070000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2391289742 Mar 10 01:12:05 PM PDT 24 Mar 10 01:12:15 PM PDT 24 1413390000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1000441371 Mar 10 01:12:12 PM PDT 24 Mar 10 01:12:24 PM PDT 24 1625710000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.485253259 Mar 10 01:00:02 PM PDT 24 Mar 10 01:28:38 PM PDT 24 336559630000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.867149199 Mar 10 01:00:06 PM PDT 24 Mar 10 01:35:34 PM PDT 24 336334090000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1369030539 Mar 10 12:59:58 PM PDT 24 Mar 10 01:33:20 PM PDT 24 336354990000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4002692194 Mar 10 01:00:04 PM PDT 24 Mar 10 01:39:16 PM PDT 24 336768630000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1081811770 Mar 10 01:00:12 PM PDT 24 Mar 10 01:31:20 PM PDT 24 337036850000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1332971710 Mar 10 01:00:17 PM PDT 24 Mar 10 01:30:37 PM PDT 24 336547250000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4249719402 Mar 10 12:59:58 PM PDT 24 Mar 10 01:33:33 PM PDT 24 336676390000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1583555104 Mar 10 01:00:21 PM PDT 24 Mar 10 01:31:16 PM PDT 24 336765510000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1482245733 Mar 10 01:00:21 PM PDT 24 Mar 10 01:36:27 PM PDT 24 336781830000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3776345780 Mar 10 12:59:57 PM PDT 24 Mar 10 01:31:04 PM PDT 24 336533750000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3213808685 Mar 10 01:00:05 PM PDT 24 Mar 10 01:39:05 PM PDT 24 336309610000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4102428145 Mar 10 01:00:02 PM PDT 24 Mar 10 01:31:43 PM PDT 24 337070470000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.767439205 Mar 10 01:00:06 PM PDT 24 Mar 10 01:35:02 PM PDT 24 336520430000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1586354737 Mar 10 01:00:07 PM PDT 24 Mar 10 01:33:34 PM PDT 24 336449050000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3405403489 Mar 10 01:00:02 PM PDT 24 Mar 10 01:34:05 PM PDT 24 336727850000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3814792672 Mar 10 01:00:15 PM PDT 24 Mar 10 01:35:12 PM PDT 24 337129270000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1598611988 Mar 10 01:00:02 PM PDT 24 Mar 10 01:29:56 PM PDT 24 336883910000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.962407549 Mar 10 01:00:22 PM PDT 24 Mar 10 01:29:58 PM PDT 24 336526870000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2175716140 Mar 10 01:00:02 PM PDT 24 Mar 10 01:35:09 PM PDT 24 336924870000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2006174731 Mar 10 01:00:23 PM PDT 24 Mar 10 01:37:35 PM PDT 24 336670350000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.534168576 Mar 10 12:59:58 PM PDT 24 Mar 10 01:34:49 PM PDT 24 336918930000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1278181687 Mar 10 01:00:05 PM PDT 24 Mar 10 01:39:12 PM PDT 24 336735110000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1964856584 Mar 10 01:00:17 PM PDT 24 Mar 10 01:30:38 PM PDT 24 336948850000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.466410843 Mar 10 01:00:00 PM PDT 24 Mar 10 01:36:24 PM PDT 24 336378470000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3781291222 Mar 10 01:00:02 PM PDT 24 Mar 10 01:33:44 PM PDT 24 337068250000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2871746336 Mar 10 01:00:22 PM PDT 24 Mar 10 01:34:18 PM PDT 24 336423430000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3190565457 Mar 10 01:00:13 PM PDT 24 Mar 10 01:32:56 PM PDT 24 337108890000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.271759344 Mar 10 01:00:22 PM PDT 24 Mar 10 01:42:15 PM PDT 24 336608250000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3546488231 Mar 10 01:00:27 PM PDT 24 Mar 10 01:31:40 PM PDT 24 336933110000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1617266827 Mar 10 01:00:08 PM PDT 24 Mar 10 01:33:08 PM PDT 24 336317210000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3293847064 Mar 10 01:00:17 PM PDT 24 Mar 10 01:36:32 PM PDT 24 336635750000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1909038943 Mar 10 01:00:12 PM PDT 24 Mar 10 01:30:56 PM PDT 24 336967150000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1767987809 Mar 10 01:00:15 PM PDT 24 Mar 10 01:28:13 PM PDT 24 336394590000 ps
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T95 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3889938 Mar 10 01:00:17 PM PDT 24 Mar 10 01:39:23 PM PDT 24 336511450000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1182574172 Mar 10 01:00:22 PM PDT 24 Mar 10 01:33:23 PM PDT 24 336714010000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1160044041 Mar 10 01:00:22 PM PDT 24 Mar 10 01:33:33 PM PDT 24 336758030000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1529354782 Mar 10 01:00:24 PM PDT 24 Mar 10 01:34:17 PM PDT 24 336590270000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2783088616 Mar 10 01:00:01 PM PDT 24 Mar 10 01:35:17 PM PDT 24 336619810000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3159195436 Mar 10 12:59:59 PM PDT 24 Mar 10 01:33:36 PM PDT 24 336688530000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1269732120 Mar 10 01:00:17 PM PDT 24 Mar 10 01:36:36 PM PDT 24 336342210000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.403489962 Mar 10 01:00:05 PM PDT 24 Mar 10 01:30:10 PM PDT 24 336714410000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.572266614 Mar 10 01:00:22 PM PDT 24 Mar 10 01:32:46 PM PDT 24 336594850000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.896319245 Mar 10 01:00:22 PM PDT 24 Mar 10 01:33:53 PM PDT 24 336722290000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2184164520 Mar 10 01:00:07 PM PDT 24 Mar 10 01:35:26 PM PDT 24 336913010000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2664220867 Mar 10 01:00:08 PM PDT 24 Mar 10 01:42:28 PM PDT 24 336988310000 ps
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T109 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.652943672 Mar 10 01:00:15 PM PDT 24 Mar 10 01:39:25 PM PDT 24 336394310000 ps
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T4 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3989209240 Mar 10 01:01:53 PM PDT 24 Mar 10 01:35:31 PM PDT 24 336530290000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1150254397 Mar 10 01:01:53 PM PDT 24 Mar 10 01:37:14 PM PDT 24 336843030000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4155758085 Mar 10 01:02:00 PM PDT 24 Mar 10 01:37:23 PM PDT 24 336440530000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.392882020 Mar 10 01:01:56 PM PDT 24 Mar 10 01:40:31 PM PDT 24 336766070000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3238665494 Mar 10 01:01:54 PM PDT 24 Mar 10 01:35:29 PM PDT 24 336556610000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3508138429 Mar 10 01:01:59 PM PDT 24 Mar 10 01:35:48 PM PDT 24 336767430000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2072557963 Mar 10 01:02:02 PM PDT 24 Mar 10 01:40:28 PM PDT 24 336536210000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4291619159 Mar 10 01:01:44 PM PDT 24 Mar 10 01:35:39 PM PDT 24 336841390000 ps
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T30 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1072314687 Mar 10 01:01:48 PM PDT 24 Mar 10 01:38:38 PM PDT 24 336644170000 ps
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T114 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1946400273 Mar 10 01:01:48 PM PDT 24 Mar 10 01:37:07 PM PDT 24 336311890000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1326509084 Mar 10 01:01:51 PM PDT 24 Mar 10 01:35:06 PM PDT 24 336397230000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3318423085 Mar 10 01:01:48 PM PDT 24 Mar 10 01:32:19 PM PDT 24 336818730000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2594761486 Mar 10 01:01:54 PM PDT 24 Mar 10 01:43:33 PM PDT 24 336922210000 ps
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T120 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2580364262 Mar 10 01:01:53 PM PDT 24 Mar 10 01:34:25 PM PDT 24 336412130000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2924495656 Mar 10 01:01:54 PM PDT 24 Mar 10 01:34:59 PM PDT 24 336956530000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1186723555 Mar 10 01:01:53 PM PDT 24 Mar 10 01:33:01 PM PDT 24 336766190000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.356026773 Mar 10 01:01:54 PM PDT 24 Mar 10 01:34:48 PM PDT 24 336752050000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2595688883 Mar 10 01:01:55 PM PDT 24 Mar 10 01:36:52 PM PDT 24 336935910000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3276283511 Mar 10 01:02:02 PM PDT 24 Mar 10 01:34:15 PM PDT 24 336621110000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1164396641 Mar 10 01:02:01 PM PDT 24 Mar 10 01:36:36 PM PDT 24 337043510000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1199791249 Mar 10 01:02:00 PM PDT 24 Mar 10 01:39:36 PM PDT 24 336926930000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2521977670 Mar 10 01:01:49 PM PDT 24 Mar 10 01:40:19 PM PDT 24 336845610000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2948987803 Mar 10 01:01:48 PM PDT 24 Mar 10 01:43:29 PM PDT 24 336455370000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2162584452 Mar 10 01:01:42 PM PDT 24 Mar 10 01:35:03 PM PDT 24 336454450000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2547380748 Mar 10 01:01:47 PM PDT 24 Mar 10 01:41:04 PM PDT 24 336376850000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1118365891 Mar 10 01:01:49 PM PDT 24 Mar 10 01:36:28 PM PDT 24 336459950000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1753597813 Mar 10 01:01:53 PM PDT 24 Mar 10 01:28:39 PM PDT 24 336946010000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1657723620 Mar 10 01:01:48 PM PDT 24 Mar 10 01:36:15 PM PDT 24 336420970000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.299296139 Mar 10 01:01:54 PM PDT 24 Mar 10 01:40:58 PM PDT 24 336865230000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.778078682 Mar 10 01:02:02 PM PDT 24 Mar 10 01:35:19 PM PDT 24 336854030000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1670746233 Mar 10 01:01:49 PM PDT 24 Mar 10 01:40:41 PM PDT 24 337157490000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1568263741 Mar 10 01:01:48 PM PDT 24 Mar 10 01:35:02 PM PDT 24 336421670000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1520783905 Mar 10 01:01:48 PM PDT 24 Mar 10 01:29:28 PM PDT 24 336999410000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1686410675 Mar 10 01:01:55 PM PDT 24 Mar 10 01:32:48 PM PDT 24 336835070000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3721496623 Mar 10 01:01:49 PM PDT 24 Mar 10 01:35:46 PM PDT 24 336601930000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3252611546 Mar 10 01:02:01 PM PDT 24 Mar 10 01:35:08 PM PDT 24 336686450000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2703764451 Mar 10 01:01:53 PM PDT 24 Mar 10 01:35:50 PM PDT 24 337086770000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.820771638 Mar 10 01:01:48 PM PDT 24 Mar 10 01:36:11 PM PDT 24 337091030000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.731751367 Mar 10 01:01:52 PM PDT 24 Mar 10 01:36:53 PM PDT 24 337068030000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3789129672 Mar 10 01:01:53 PM PDT 24 Mar 10 01:40:09 PM PDT 24 336624490000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3848386353 Mar 10 01:01:47 PM PDT 24 Mar 10 01:35:24 PM PDT 24 336956130000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1843037693 Mar 10 01:01:44 PM PDT 24 Mar 10 01:36:00 PM PDT 24 336735230000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.771248906 Mar 10 01:01:59 PM PDT 24 Mar 10 01:34:57 PM PDT 24 336969070000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.99521482 Mar 10 01:02:02 PM PDT 24 Mar 10 01:35:15 PM PDT 24 336338530000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.502264983 Mar 10 12:24:06 PM PDT 24 Mar 10 12:24:13 PM PDT 24 1349450000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3769645232 Mar 10 12:23:44 PM PDT 24 Mar 10 12:23:52 PM PDT 24 1292190000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.988697240 Mar 10 12:19:52 PM PDT 24 Mar 10 12:20:01 PM PDT 24 1542970000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3556844589 Mar 10 12:32:50 PM PDT 24 Mar 10 12:32:58 PM PDT 24 1444870000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1721771137 Mar 10 12:20:42 PM PDT 24 Mar 10 12:20:52 PM PDT 24 1614130000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4120944803 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:17 PM PDT 24 1524170000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1436140196 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:10 PM PDT 24 1522270000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3967116500 Mar 10 12:24:10 PM PDT 24 Mar 10 12:24:20 PM PDT 24 1447010000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4137980482 Mar 10 12:21:26 PM PDT 24 Mar 10 12:21:35 PM PDT 24 1573250000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1721356239 Mar 10 12:18:22 PM PDT 24 Mar 10 12:18:31 PM PDT 24 1529810000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2396763 Mar 10 12:24:00 PM PDT 24 Mar 10 12:24:08 PM PDT 24 1463730000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2837047763 Mar 10 12:23:18 PM PDT 24 Mar 10 12:23:27 PM PDT 24 1566750000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3151041574 Mar 10 12:20:33 PM PDT 24 Mar 10 12:20:42 PM PDT 24 1356150000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.931427835 Mar 10 12:21:26 PM PDT 24 Mar 10 12:21:35 PM PDT 24 1556230000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3387198325 Mar 10 12:27:01 PM PDT 24 Mar 10 12:27:08 PM PDT 24 1407190000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1423901008 Mar 10 12:24:30 PM PDT 24 Mar 10 12:24:36 PM PDT 24 1305970000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4288499210 Mar 10 12:23:50 PM PDT 24 Mar 10 12:24:00 PM PDT 24 1446490000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3568862729 Mar 10 12:24:38 PM PDT 24 Mar 10 12:24:47 PM PDT 24 1609210000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.739041808 Mar 10 12:23:21 PM PDT 24 Mar 10 12:23:29 PM PDT 24 1586770000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.584460601 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:09 PM PDT 24 1353590000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3077397128 Mar 10 12:23:37 PM PDT 24 Mar 10 12:23:43 PM PDT 24 1315030000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1886993746 Mar 10 12:23:19 PM PDT 24 Mar 10 12:23:27 PM PDT 24 1287610000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3552760531 Mar 10 12:19:06 PM PDT 24 Mar 10 12:19:13 PM PDT 24 1341830000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2772598512 Mar 10 12:24:09 PM PDT 24 Mar 10 12:24:19 PM PDT 24 1560790000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.970022853 Mar 10 12:23:29 PM PDT 24 Mar 10 12:23:36 PM PDT 24 1489470000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1136396902 Mar 10 12:23:05 PM PDT 24 Mar 10 12:23:12 PM PDT 24 1518030000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1964070697 Mar 10 12:20:06 PM PDT 24 Mar 10 12:20:14 PM PDT 24 1188170000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.220280444 Mar 10 12:24:05 PM PDT 24 Mar 10 12:24:13 PM PDT 24 1423070000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3730816189 Mar 10 12:22:53 PM PDT 24 Mar 10 12:23:01 PM PDT 24 1550810000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.124479551 Mar 10 12:20:11 PM PDT 24 Mar 10 12:20:19 PM PDT 24 1474310000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.192211939 Mar 10 12:24:19 PM PDT 24 Mar 10 12:24:26 PM PDT 24 1421790000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3950730498 Mar 10 12:20:17 PM PDT 24 Mar 10 12:20:26 PM PDT 24 1421150000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2819502188 Mar 10 12:21:04 PM PDT 24 Mar 10 12:21:14 PM PDT 24 1560450000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1962314483 Mar 10 12:21:03 PM PDT 24 Mar 10 12:21:14 PM PDT 24 1474510000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2881726758 Mar 10 12:20:41 PM PDT 24 Mar 10 12:20:49 PM PDT 24 1459710000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3368187866 Mar 10 12:24:38 PM PDT 24 Mar 10 12:24:46 PM PDT 24 1430550000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1209931715 Mar 10 12:23:54 PM PDT 24 Mar 10 12:24:03 PM PDT 24 1604350000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4229632263 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:10 PM PDT 24 1632210000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1725566711 Mar 10 12:21:24 PM PDT 24 Mar 10 12:21:33 PM PDT 24 1486290000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.923810130 Mar 10 12:24:13 PM PDT 24 Mar 10 12:24:20 PM PDT 24 1512510000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3005100048 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:10 PM PDT 24 1562590000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3432006070 Mar 10 12:24:29 PM PDT 24 Mar 10 12:24:37 PM PDT 24 1533290000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3694459517 Mar 10 12:23:50 PM PDT 24 Mar 10 12:23:59 PM PDT 24 1262190000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2234516503 Mar 10 12:19:21 PM PDT 24 Mar 10 12:19:31 PM PDT 24 1562910000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3996756907 Mar 10 12:23:54 PM PDT 24 Mar 10 12:24:02 PM PDT 24 1533770000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3047883665 Mar 10 12:33:05 PM PDT 24 Mar 10 12:33:11 PM PDT 24 1279690000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3972938778 Mar 10 12:18:16 PM PDT 24 Mar 10 12:18:23 PM PDT 24 1284370000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2817744230 Mar 10 12:23:29 PM PDT 24 Mar 10 12:23:37 PM PDT 24 1511610000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1558374019 Mar 10 12:24:05 PM PDT 24 Mar 10 12:24:13 PM PDT 24 1395970000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1730403096 Mar 10 12:21:46 PM PDT 24 Mar 10 12:21:55 PM PDT 24 1329090000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4117595737
Short name T8
Test name
Test status
Simulation time 1564630000 ps
CPU time 4.49 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 164580 kb
Host smart-58268179-d9cd-4856-ba1b-13b0f840dfdc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4117595737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4117595737
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1369030539
Short name T16
Test name
Test status
Simulation time 336354990000 ps
CPU time 818.09 seconds
Started Mar 10 12:59:58 PM PDT 24
Finished Mar 10 01:33:20 PM PDT 24
Peak memory 160612 kb
Host smart-77695171-b1bc-41ee-8242-ed62b45f737d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1369030539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1369030539
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4104433254
Short name T29
Test name
Test status
Simulation time 336475110000 ps
CPU time 859.74 seconds
Started Mar 10 01:01:50 PM PDT 24
Finished Mar 10 01:36:50 PM PDT 24
Peak memory 160720 kb
Host smart-9edf9cb1-74ca-4092-bfeb-718e3e4229b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4104433254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.4104433254
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2162584452
Short name T130
Test name
Test status
Simulation time 336454450000 ps
CPU time 813.26 seconds
Started Mar 10 01:01:42 PM PDT 24
Finished Mar 10 01:35:03 PM PDT 24
Peak memory 160636 kb
Host smart-ca1f26dd-eb0c-46d5-8280-3782efd8b055
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2162584452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2162584452
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1843037693
Short name T148
Test name
Test status
Simulation time 336735230000 ps
CPU time 845.16 seconds
Started Mar 10 01:01:44 PM PDT 24
Finished Mar 10 01:36:00 PM PDT 24
Peak memory 160704 kb
Host smart-ce0bc4e0-c9ac-44c0-9903-5677e0ce5f61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1843037693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1843037693
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.731751367
Short name T145
Test name
Test status
Simulation time 337068030000 ps
CPU time 861.88 seconds
Started Mar 10 01:01:52 PM PDT 24
Finished Mar 10 01:36:53 PM PDT 24
Peak memory 160708 kb
Host smart-643e87ea-1fb7-47b8-8f29-2baa1d804d9d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=731751367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.731751367
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1520783905
Short name T139
Test name
Test status
Simulation time 336999410000 ps
CPU time 671.53 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:29:28 PM PDT 24
Peak memory 160748 kb
Host smart-647bebba-2242-47f2-8323-048536dd592c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1520783905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1520783905
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3848386353
Short name T147
Test name
Test status
Simulation time 336956130000 ps
CPU time 828.63 seconds
Started Mar 10 01:01:47 PM PDT 24
Finished Mar 10 01:35:24 PM PDT 24
Peak memory 160712 kb
Host smart-0248dfd5-280d-42fb-b882-220b9ba6dae0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3848386353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3848386353
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3374236704
Short name T112
Test name
Test status
Simulation time 336613510000 ps
CPU time 850.75 seconds
Started Mar 10 01:01:46 PM PDT 24
Finished Mar 10 01:35:30 PM PDT 24
Peak memory 160752 kb
Host smart-5bf46316-4a38-40f2-b0ad-2d17e26d75de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3374236704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3374236704
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1670746233
Short name T137
Test name
Test status
Simulation time 337157490000 ps
CPU time 956.84 seconds
Started Mar 10 01:01:49 PM PDT 24
Finished Mar 10 01:40:41 PM PDT 24
Peak memory 160744 kb
Host smart-8fd1018c-cb47-4733-b66a-7bf10e1b3076
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1670746233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1670746233
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3721496623
Short name T141
Test name
Test status
Simulation time 336601930000 ps
CPU time 843.8 seconds
Started Mar 10 01:01:49 PM PDT 24
Finished Mar 10 01:35:46 PM PDT 24
Peak memory 160652 kb
Host smart-dab21ba4-ce61-4b53-94a2-ea915a7e36b8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3721496623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3721496623
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1326509084
Short name T115
Test name
Test status
Simulation time 336397230000 ps
CPU time 811.79 seconds
Started Mar 10 01:01:51 PM PDT 24
Finished Mar 10 01:35:06 PM PDT 24
Peak memory 160720 kb
Host smart-91dc2897-105e-4b8b-b0f2-16c7cb6153c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1326509084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1326509084
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1771499063
Short name T111
Test name
Test status
Simulation time 336673190000 ps
CPU time 787.88 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:34:14 PM PDT 24
Peak memory 160704 kb
Host smart-7b97bf67-f914-4f4f-a08c-f2ac98a8a872
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1771499063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1771499063
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3318423085
Short name T116
Test name
Test status
Simulation time 336818730000 ps
CPU time 744.4 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:32:19 PM PDT 24
Peak memory 160740 kb
Host smart-1e5a828f-4a7f-47be-bbae-ef77a071722f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3318423085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3318423085
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.836442143
Short name T118
Test name
Test status
Simulation time 336753030000 ps
CPU time 855.73 seconds
Started Mar 10 01:01:44 PM PDT 24
Finished Mar 10 01:36:40 PM PDT 24
Peak memory 160796 kb
Host smart-b25779eb-bfb7-4ef2-a2cd-9408b47565b9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=836442143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.836442143
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1657723620
Short name T134
Test name
Test status
Simulation time 336420970000 ps
CPU time 867.46 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:36:15 PM PDT 24
Peak memory 160716 kb
Host smart-a35400b6-1a83-4cb0-9d4f-e3dbf12419f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1657723620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1657723620
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.820771638
Short name T144
Test name
Test status
Simulation time 337091030000 ps
CPU time 853.98 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:36:11 PM PDT 24
Peak memory 160756 kb
Host smart-96eab11f-23da-4a83-adf2-7134a6bc341d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=820771638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.820771638
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2547380748
Short name T131
Test name
Test status
Simulation time 336376850000 ps
CPU time 963.52 seconds
Started Mar 10 01:01:47 PM PDT 24
Finished Mar 10 01:41:04 PM PDT 24
Peak memory 160752 kb
Host smart-1b41dffe-67bd-4227-8c6a-0d024f3e224a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2547380748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2547380748
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2948987803
Short name T129
Test name
Test status
Simulation time 336455370000 ps
CPU time 983.41 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:43:29 PM PDT 24
Peak memory 160736 kb
Host smart-662c9b07-05a5-4294-87dd-311c84e597d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2948987803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2948987803
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3789129672
Short name T146
Test name
Test status
Simulation time 336624490000 ps
CPU time 933.28 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:40:09 PM PDT 24
Peak memory 160748 kb
Host smart-7d906b44-65fe-42f1-a7c4-13578f6adbbd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3789129672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3789129672
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.299296139
Short name T135
Test name
Test status
Simulation time 336865230000 ps
CPU time 954.8 seconds
Started Mar 10 01:01:54 PM PDT 24
Finished Mar 10 01:40:58 PM PDT 24
Peak memory 160740 kb
Host smart-52175c0e-e882-4cbc-ad23-0e079c641f72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=299296139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.299296139
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2580364262
Short name T120
Test name
Test status
Simulation time 336412130000 ps
CPU time 788.52 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:34:25 PM PDT 24
Peak memory 160704 kb
Host smart-890c07bd-ec3b-49f5-be64-0ee1ef348fa7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2580364262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2580364262
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3238665494
Short name T25
Test name
Test status
Simulation time 336556610000 ps
CPU time 828.06 seconds
Started Mar 10 01:01:54 PM PDT 24
Finished Mar 10 01:35:29 PM PDT 24
Peak memory 160752 kb
Host smart-6e47a8e6-1c34-4668-adf2-0fc1fc45c4dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3238665494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3238665494
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1150254397
Short name T5
Test name
Test status
Simulation time 336843030000 ps
CPU time 868.7 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:37:14 PM PDT 24
Peak memory 160720 kb
Host smart-7a580697-6bda-4ac2-80a3-1d3ee4365f98
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1150254397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1150254397
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2595688883
Short name T124
Test name
Test status
Simulation time 336935910000 ps
CPU time 852.36 seconds
Started Mar 10 01:01:55 PM PDT 24
Finished Mar 10 01:36:52 PM PDT 24
Peak memory 160700 kb
Host smart-7124d24b-0cc1-4b46-b512-c27d18e49ebf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2595688883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2595688883
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4291619159
Short name T28
Test name
Test status
Simulation time 336841390000 ps
CPU time 829.11 seconds
Started Mar 10 01:01:44 PM PDT 24
Finished Mar 10 01:35:39 PM PDT 24
Peak memory 160704 kb
Host smart-20b22c4a-a478-4639-906e-5e775b156037
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4291619159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4291619159
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3778200382
Short name T113
Test name
Test status
Simulation time 336653970000 ps
CPU time 765.02 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:32:36 PM PDT 24
Peak memory 160748 kb
Host smart-89c85b46-87dc-4232-adf3-f639d8f9c80f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3778200382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3778200382
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2594761486
Short name T117
Test name
Test status
Simulation time 336922210000 ps
CPU time 983.36 seconds
Started Mar 10 01:01:54 PM PDT 24
Finished Mar 10 01:43:33 PM PDT 24
Peak memory 160736 kb
Host smart-2ec43b01-5016-4e99-a463-648e7bce3633
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2594761486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2594761486
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.392882020
Short name T24
Test name
Test status
Simulation time 336766070000 ps
CPU time 940.96 seconds
Started Mar 10 01:01:56 PM PDT 24
Finished Mar 10 01:40:31 PM PDT 24
Peak memory 160736 kb
Host smart-dec16342-bef2-4fd9-b698-d9ca727adb3f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=392882020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.392882020
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1186723555
Short name T122
Test name
Test status
Simulation time 336766190000 ps
CPU time 770.63 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:33:01 PM PDT 24
Peak memory 160720 kb
Host smart-b1695d1b-3e67-49fe-a1cc-f440af3b9f2d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1186723555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1186723555
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.356026773
Short name T123
Test name
Test status
Simulation time 336752050000 ps
CPU time 807.53 seconds
Started Mar 10 01:01:54 PM PDT 24
Finished Mar 10 01:34:48 PM PDT 24
Peak memory 160728 kb
Host smart-8472969f-1c17-43ce-aac3-d6037d424352
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=356026773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.356026773
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1686410675
Short name T140
Test name
Test status
Simulation time 336835070000 ps
CPU time 746.87 seconds
Started Mar 10 01:01:55 PM PDT 24
Finished Mar 10 01:32:48 PM PDT 24
Peak memory 160728 kb
Host smart-64c046c7-d5cf-4450-96ca-6fe4b430d835
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1686410675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1686410675
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2924495656
Short name T121
Test name
Test status
Simulation time 336956530000 ps
CPU time 801.76 seconds
Started Mar 10 01:01:54 PM PDT 24
Finished Mar 10 01:34:59 PM PDT 24
Peak memory 160644 kb
Host smart-e4db3ec0-0b06-4f12-8815-f41c3db249ff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2924495656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2924495656
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3989209240
Short name T4
Test name
Test status
Simulation time 336530290000 ps
CPU time 833.95 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:35:31 PM PDT 24
Peak memory 160724 kb
Host smart-3d8649a9-bf7b-45d8-8c72-7894ec50a7b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3989209240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3989209240
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2703764451
Short name T143
Test name
Test status
Simulation time 337086770000 ps
CPU time 825.12 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:35:50 PM PDT 24
Peak memory 160720 kb
Host smart-3700094d-0982-4bf6-9b58-8b3625d98a9d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2703764451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2703764451
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1753597813
Short name T133
Test name
Test status
Simulation time 336946010000 ps
CPU time 650.56 seconds
Started Mar 10 01:01:53 PM PDT 24
Finished Mar 10 01:28:39 PM PDT 24
Peak memory 160776 kb
Host smart-fcdb5b1e-ae3c-4f76-819f-8e074b745327
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1753597813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1753597813
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3721708738
Short name T119
Test name
Test status
Simulation time 336477210000 ps
CPU time 809.11 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:34:58 PM PDT 24
Peak memory 160772 kb
Host smart-12bb5ae6-7d2a-47df-85e1-eaabb6ff6624
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3721708738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3721708738
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3508138429
Short name T26
Test name
Test status
Simulation time 336767430000 ps
CPU time 830.22 seconds
Started Mar 10 01:01:59 PM PDT 24
Finished Mar 10 01:35:48 PM PDT 24
Peak memory 160784 kb
Host smart-55fd4617-b792-4b4f-91d5-6bfa8423714d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3508138429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3508138429
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2072557963
Short name T27
Test name
Test status
Simulation time 336536210000 ps
CPU time 938.47 seconds
Started Mar 10 01:02:02 PM PDT 24
Finished Mar 10 01:40:28 PM PDT 24
Peak memory 160748 kb
Host smart-938d5670-9c7d-4ea5-a6c8-ff7536ad4503
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2072557963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2072557963
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.99521482
Short name T150
Test name
Test status
Simulation time 336338530000 ps
CPU time 810.39 seconds
Started Mar 10 01:02:02 PM PDT 24
Finished Mar 10 01:35:15 PM PDT 24
Peak memory 160696 kb
Host smart-c7b536ca-163b-414f-a766-5f3058748773
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=99521482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.99521482
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1199791249
Short name T127
Test name
Test status
Simulation time 336926930000 ps
CPU time 938.23 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:39:36 PM PDT 24
Peak memory 160656 kb
Host smart-7efea965-3382-42b7-aada-e5c9d0953487
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1199791249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1199791249
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3276283511
Short name T125
Test name
Test status
Simulation time 336621110000 ps
CPU time 801.48 seconds
Started Mar 10 01:02:02 PM PDT 24
Finished Mar 10 01:34:15 PM PDT 24
Peak memory 160752 kb
Host smart-088306e4-d62b-4a6a-8c8b-80c4bea9a180
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3276283511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3276283511
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4155758085
Short name T6
Test name
Test status
Simulation time 336440530000 ps
CPU time 860.83 seconds
Started Mar 10 01:02:00 PM PDT 24
Finished Mar 10 01:37:23 PM PDT 24
Peak memory 160700 kb
Host smart-0478c125-72de-4e4d-b057-426d6e5266de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4155758085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4155758085
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1164396641
Short name T126
Test name
Test status
Simulation time 337043510000 ps
CPU time 856.15 seconds
Started Mar 10 01:02:01 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 160796 kb
Host smart-a0e0ac2d-e22d-454e-ac61-e7c70a34d98b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1164396641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1164396641
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.771248906
Short name T149
Test name
Test status
Simulation time 336969070000 ps
CPU time 799.47 seconds
Started Mar 10 01:01:59 PM PDT 24
Finished Mar 10 01:34:57 PM PDT 24
Peak memory 160628 kb
Host smart-a54df447-3d7c-46f9-a281-e522508480cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=771248906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.771248906
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3252611546
Short name T142
Test name
Test status
Simulation time 336686450000 ps
CPU time 825.01 seconds
Started Mar 10 01:02:01 PM PDT 24
Finished Mar 10 01:35:08 PM PDT 24
Peak memory 160872 kb
Host smart-67b1757d-d79e-4201-95a2-3ed68b079e21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3252611546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3252611546
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.778078682
Short name T136
Test name
Test status
Simulation time 336854030000 ps
CPU time 812.65 seconds
Started Mar 10 01:02:02 PM PDT 24
Finished Mar 10 01:35:19 PM PDT 24
Peak memory 160680 kb
Host smart-8e08363e-bc4a-4c08-962f-dbccfde8992d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=778078682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.778078682
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2521977670
Short name T128
Test name
Test status
Simulation time 336845610000 ps
CPU time 935.87 seconds
Started Mar 10 01:01:49 PM PDT 24
Finished Mar 10 01:40:19 PM PDT 24
Peak memory 160736 kb
Host smart-4070e68e-5cb5-4051-8e72-9514edf2952b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2521977670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2521977670
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1072314687
Short name T30
Test name
Test status
Simulation time 336644170000 ps
CPU time 917.57 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:38:38 PM PDT 24
Peak memory 160792 kb
Host smart-53ac0a3f-ea37-40db-aedd-0d37b62f4b13
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1072314687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1072314687
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1568263741
Short name T138
Test name
Test status
Simulation time 336421670000 ps
CPU time 820.05 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:35:02 PM PDT 24
Peak memory 160744 kb
Host smart-30040d88-0daa-417e-8be7-b787566584db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1568263741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1568263741
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1118365891
Short name T132
Test name
Test status
Simulation time 336459950000 ps
CPU time 849.34 seconds
Started Mar 10 01:01:49 PM PDT 24
Finished Mar 10 01:36:28 PM PDT 24
Peak memory 160740 kb
Host smart-c218c57d-946e-4c37-b4cc-b144e1b73d54
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1118365891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1118365891
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1946400273
Short name T114
Test name
Test status
Simulation time 336311890000 ps
CPU time 862.78 seconds
Started Mar 10 01:01:48 PM PDT 24
Finished Mar 10 01:37:07 PM PDT 24
Peak memory 160696 kb
Host smart-9b1dd04f-caf6-4cad-a4b4-aeda92eacffc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1946400273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1946400273
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.534168576
Short name T81
Test name
Test status
Simulation time 336918930000 ps
CPU time 842.53 seconds
Started Mar 10 12:59:58 PM PDT 24
Finished Mar 10 01:34:49 PM PDT 24
Peak memory 160632 kb
Host smart-6642e3fe-e96e-4f3d-bec9-cfcd2e8ec1b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=534168576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.534168576
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1881484721
Short name T94
Test name
Test status
Simulation time 337066490000 ps
CPU time 697.52 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:28:50 PM PDT 24
Peak memory 160664 kb
Host smart-3661748d-538a-4081-b398-6fa21bf54084
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1881484721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1881484721
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4102428145
Short name T72
Test name
Test status
Simulation time 337070470000 ps
CPU time 783.5 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:31:43 PM PDT 24
Peak memory 160624 kb
Host smart-559a6cf5-6f8a-48b0-ac8f-d25c1bec4368
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4102428145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.4102428145
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4002692194
Short name T17
Test name
Test status
Simulation time 336768630000 ps
CPU time 947.55 seconds
Started Mar 10 01:00:04 PM PDT 24
Finished Mar 10 01:39:16 PM PDT 24
Peak memory 160624 kb
Host smart-b3c4ef70-afe1-4dc8-8e11-066d318e2f15
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4002692194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4002692194
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1598611988
Short name T77
Test name
Test status
Simulation time 336883910000 ps
CPU time 737.77 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:29:56 PM PDT 24
Peak memory 160672 kb
Host smart-251b8e78-631d-447a-be18-9a1b7e622a90
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1598611988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1598611988
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1278181687
Short name T82
Test name
Test status
Simulation time 336735110000 ps
CPU time 939.63 seconds
Started Mar 10 01:00:05 PM PDT 24
Finished Mar 10 01:39:12 PM PDT 24
Peak memory 160624 kb
Host smart-715474a1-3c84-4440-9c81-8e5f04a0c3ea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1278181687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1278181687
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3405403489
Short name T75
Test name
Test status
Simulation time 336727850000 ps
CPU time 838.67 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:34:05 PM PDT 24
Peak memory 160612 kb
Host smart-26c1a541-0c38-40e5-8654-9e67bba9535f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3405403489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3405403489
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3213808685
Short name T71
Test name
Test status
Simulation time 336309610000 ps
CPU time 938.69 seconds
Started Mar 10 01:00:05 PM PDT 24
Finished Mar 10 01:39:05 PM PDT 24
Peak memory 160624 kb
Host smart-4fb1ac33-c8cc-426a-bda2-6e22f0424608
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3213808685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3213808685
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3781291222
Short name T85
Test name
Test status
Simulation time 337068250000 ps
CPU time 827.53 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:33:44 PM PDT 24
Peak memory 160680 kb
Host smart-7878ef66-00ae-47fa-af10-ff1e897fe330
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3781291222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3781291222
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3614656614
Short name T108
Test name
Test status
Simulation time 337034870000 ps
CPU time 821.14 seconds
Started Mar 10 01:00:01 PM PDT 24
Finished Mar 10 01:33:34 PM PDT 24
Peak memory 160628 kb
Host smart-dfc7e1b6-e686-4c42-a603-0b418be1f362
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3614656614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3614656614
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2184164520
Short name T105
Test name
Test status
Simulation time 336913010000 ps
CPU time 866.03 seconds
Started Mar 10 01:00:07 PM PDT 24
Finished Mar 10 01:35:26 PM PDT 24
Peak memory 160656 kb
Host smart-b0dc2837-34d5-4562-972f-b52357be7d0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2184164520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2184164520
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3159195436
Short name T100
Test name
Test status
Simulation time 336688530000 ps
CPU time 825.45 seconds
Started Mar 10 12:59:59 PM PDT 24
Finished Mar 10 01:33:36 PM PDT 24
Peak memory 160672 kb
Host smart-dce08cab-2a76-4e55-9d27-a9ce6a49617d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3159195436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3159195436
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.403489962
Short name T102
Test name
Test status
Simulation time 336714410000 ps
CPU time 742.3 seconds
Started Mar 10 01:00:05 PM PDT 24
Finished Mar 10 01:30:10 PM PDT 24
Peak memory 160660 kb
Host smart-66fa00f0-2fe4-40a7-9fdd-c3e9cd5db609
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=403489962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.403489962
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.867149199
Short name T15
Test name
Test status
Simulation time 336334090000 ps
CPU time 865.43 seconds
Started Mar 10 01:00:06 PM PDT 24
Finished Mar 10 01:35:34 PM PDT 24
Peak memory 160592 kb
Host smart-cda55b98-c689-46ca-9afa-8e6f0c7613a5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=867149199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.867149199
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2664220867
Short name T106
Test name
Test status
Simulation time 336988310000 ps
CPU time 988.84 seconds
Started Mar 10 01:00:08 PM PDT 24
Finished Mar 10 01:42:28 PM PDT 24
Peak memory 160612 kb
Host smart-269403cb-a7d3-409f-8126-9ac85be3eaa1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2664220867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2664220867
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1617266827
Short name T90
Test name
Test status
Simulation time 336317210000 ps
CPU time 809.2 seconds
Started Mar 10 01:00:08 PM PDT 24
Finished Mar 10 01:33:08 PM PDT 24
Peak memory 160680 kb
Host smart-636caada-e19f-46d2-afbe-b96424663601
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1617266827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1617266827
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1586354737
Short name T74
Test name
Test status
Simulation time 336449050000 ps
CPU time 828.05 seconds
Started Mar 10 01:00:07 PM PDT 24
Finished Mar 10 01:33:34 PM PDT 24
Peak memory 160592 kb
Host smart-eb81c6f1-0a19-4f5c-b1ce-30e914d34154
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1586354737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1586354737
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.767439205
Short name T73
Test name
Test status
Simulation time 336520430000 ps
CPU time 865.44 seconds
Started Mar 10 01:00:06 PM PDT 24
Finished Mar 10 01:35:02 PM PDT 24
Peak memory 160660 kb
Host smart-ecba69ca-121a-4f5b-b82d-e79625004ef0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=767439205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.767439205
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.652943672
Short name T109
Test name
Test status
Simulation time 336394310000 ps
CPU time 941.75 seconds
Started Mar 10 01:00:15 PM PDT 24
Finished Mar 10 01:39:25 PM PDT 24
Peak memory 160612 kb
Host smart-e189ca80-fe73-4fb6-905c-4eeca8697e53
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=652943672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.652943672
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1909038943
Short name T92
Test name
Test status
Simulation time 336967150000 ps
CPU time 764.6 seconds
Started Mar 10 01:00:12 PM PDT 24
Finished Mar 10 01:30:56 PM PDT 24
Peak memory 160596 kb
Host smart-8e305949-b5e9-40d5-8f12-3221432410a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1909038943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1909038943
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3190565457
Short name T87
Test name
Test status
Simulation time 337108890000 ps
CPU time 799.87 seconds
Started Mar 10 01:00:13 PM PDT 24
Finished Mar 10 01:32:56 PM PDT 24
Peak memory 160580 kb
Host smart-0a09f7dd-fab0-45a9-b60c-c51bbae80a5e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3190565457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3190565457
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3814792672
Short name T76
Test name
Test status
Simulation time 337129270000 ps
CPU time 852.68 seconds
Started Mar 10 01:00:15 PM PDT 24
Finished Mar 10 01:35:12 PM PDT 24
Peak memory 160640 kb
Host smart-5d03c0ff-8eff-4c00-89a6-89c74019f9c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3814792672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3814792672
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.4249719402
Short name T20
Test name
Test status
Simulation time 336676390000 ps
CPU time 818.7 seconds
Started Mar 10 12:59:58 PM PDT 24
Finished Mar 10 01:33:33 PM PDT 24
Peak memory 160612 kb
Host smart-e4ebe22a-3129-4b4e-869d-e44c1d34e667
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4249719402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.4249719402
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1081811770
Short name T18
Test name
Test status
Simulation time 337036850000 ps
CPU time 767.1 seconds
Started Mar 10 01:00:12 PM PDT 24
Finished Mar 10 01:31:20 PM PDT 24
Peak memory 160564 kb
Host smart-c74f5ebc-9fd5-4eff-b4ef-b2adf1b42324
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1081811770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1081811770
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3889938
Short name T95
Test name
Test status
Simulation time 336511450000 ps
CPU time 937.92 seconds
Started Mar 10 01:00:17 PM PDT 24
Finished Mar 10 01:39:23 PM PDT 24
Peak memory 160616 kb
Host smart-0fa4b7fe-58ce-4f42-a79c-b6f974b219e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3889938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3889938
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1269732120
Short name T101
Test name
Test status
Simulation time 336342210000 ps
CPU time 904.86 seconds
Started Mar 10 01:00:17 PM PDT 24
Finished Mar 10 01:36:36 PM PDT 24
Peak memory 160692 kb
Host smart-79711645-9812-4042-99f4-2e3c1ad18b3d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1269732120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1269732120
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3293847064
Short name T91
Test name
Test status
Simulation time 336635750000 ps
CPU time 868.09 seconds
Started Mar 10 01:00:17 PM PDT 24
Finished Mar 10 01:36:32 PM PDT 24
Peak memory 160620 kb
Host smart-95f1aa41-13c7-4faa-a348-53a7a0729c00
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3293847064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3293847064
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1767987809
Short name T93
Test name
Test status
Simulation time 336394590000 ps
CPU time 684.82 seconds
Started Mar 10 01:00:15 PM PDT 24
Finished Mar 10 01:28:13 PM PDT 24
Peak memory 160676 kb
Host smart-3bc0052d-75e1-46a0-8364-7800ce8ebbd8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1767987809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1767987809
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1332971710
Short name T19
Test name
Test status
Simulation time 336547250000 ps
CPU time 744.68 seconds
Started Mar 10 01:00:17 PM PDT 24
Finished Mar 10 01:30:37 PM PDT 24
Peak memory 160664 kb
Host smart-c7e1cf82-85c3-4030-af63-fe44d6d13255
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1332971710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1332971710
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1964856584
Short name T83
Test name
Test status
Simulation time 336948850000 ps
CPU time 750.42 seconds
Started Mar 10 01:00:17 PM PDT 24
Finished Mar 10 01:30:38 PM PDT 24
Peak memory 160584 kb
Host smart-bf39c6e6-444b-40fa-a49a-3d672414e525
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1964856584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1964856584
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2871746336
Short name T86
Test name
Test status
Simulation time 336423430000 ps
CPU time 850.55 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:34:18 PM PDT 24
Peak memory 160596 kb
Host smart-ea723b32-3b51-4d31-a494-0211574fe42e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2871746336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2871746336
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2006174731
Short name T80
Test name
Test status
Simulation time 336670350000 ps
CPU time 899.06 seconds
Started Mar 10 01:00:23 PM PDT 24
Finished Mar 10 01:37:35 PM PDT 24
Peak memory 160620 kb
Host smart-c4810709-659c-4d40-bef4-bf8619aa26dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2006174731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2006174731
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.271759344
Short name T88
Test name
Test status
Simulation time 336608250000 ps
CPU time 995.88 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:42:15 PM PDT 24
Peak memory 160608 kb
Host smart-839d4cc8-8732-46c1-8b73-2de0b2c57680
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=271759344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.271759344
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3776345780
Short name T23
Test name
Test status
Simulation time 336533750000 ps
CPU time 762.86 seconds
Started Mar 10 12:59:57 PM PDT 24
Finished Mar 10 01:31:04 PM PDT 24
Peak memory 160656 kb
Host smart-d098b538-12e9-43ee-9f80-a67c3dbd9d81
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3776345780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3776345780
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.572266614
Short name T103
Test name
Test status
Simulation time 336594850000 ps
CPU time 784.62 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:32:46 PM PDT 24
Peak memory 160564 kb
Host smart-ad65fa11-4d4e-4410-ad34-7c9f916936dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=572266614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.572266614
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1583555104
Short name T21
Test name
Test status
Simulation time 336765510000 ps
CPU time 752.62 seconds
Started Mar 10 01:00:21 PM PDT 24
Finished Mar 10 01:31:16 PM PDT 24
Peak memory 160664 kb
Host smart-0cf12101-ee49-4489-9de4-3e37e966f583
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1583555104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1583555104
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1529354782
Short name T98
Test name
Test status
Simulation time 336590270000 ps
CPU time 837.63 seconds
Started Mar 10 01:00:24 PM PDT 24
Finished Mar 10 01:34:17 PM PDT 24
Peak memory 160508 kb
Host smart-6c689c71-b3e0-4b8b-9a8f-d67fcc35a139
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529354782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1529354782
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1182574172
Short name T96
Test name
Test status
Simulation time 336714010000 ps
CPU time 811.28 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:33:23 PM PDT 24
Peak memory 160616 kb
Host smart-bbf666b5-18de-4281-ad02-76c868f5cd16
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1182574172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1182574172
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2141549809
Short name T107
Test name
Test status
Simulation time 337003230000 ps
CPU time 722.08 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:29:40 PM PDT 24
Peak memory 160596 kb
Host smart-d95f80d9-3c04-4d1a-99bc-00fed7a2da57
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2141549809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2141549809
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1160044041
Short name T97
Test name
Test status
Simulation time 336758030000 ps
CPU time 812.66 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:33:33 PM PDT 24
Peak memory 160632 kb
Host smart-690d3312-d650-4d64-aa6d-c19b593200fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1160044041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1160044041
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.962407549
Short name T78
Test name
Test status
Simulation time 336526870000 ps
CPU time 729.66 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:29:58 PM PDT 24
Peak memory 160612 kb
Host smart-66fa3c83-fbb4-4b3f-af87-da1e43c96c0d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=962407549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.962407549
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1482245733
Short name T22
Test name
Test status
Simulation time 336781830000 ps
CPU time 894.35 seconds
Started Mar 10 01:00:21 PM PDT 24
Finished Mar 10 01:36:27 PM PDT 24
Peak memory 160572 kb
Host smart-28be8f4e-c167-4738-be4a-c11704ad7b03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1482245733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1482245733
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.896319245
Short name T104
Test name
Test status
Simulation time 336722290000 ps
CPU time 836.48 seconds
Started Mar 10 01:00:22 PM PDT 24
Finished Mar 10 01:33:53 PM PDT 24
Peak memory 160612 kb
Host smart-02739a03-6abd-4c22-88a7-a9acf4355664
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=896319245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.896319245
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3546488231
Short name T89
Test name
Test status
Simulation time 336933110000 ps
CPU time 772.48 seconds
Started Mar 10 01:00:27 PM PDT 24
Finished Mar 10 01:31:40 PM PDT 24
Peak memory 160624 kb
Host smart-069488a1-3e77-437f-bc41-8094025d59fd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3546488231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3546488231
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.920157254
Short name T110
Test name
Test status
Simulation time 336441710000 ps
CPU time 816.28 seconds
Started Mar 10 12:59:58 PM PDT 24
Finished Mar 10 01:33:12 PM PDT 24
Peak memory 160604 kb
Host smart-a5b868b4-9285-4b8f-9854-ee15ab7ec400
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=920157254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.920157254
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.485253259
Short name T14
Test name
Test status
Simulation time 336559630000 ps
CPU time 702.47 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:28:38 PM PDT 24
Peak memory 160656 kb
Host smart-0a45765b-9573-451c-afbd-863731dd01e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=485253259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.485253259
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2175716140
Short name T79
Test name
Test status
Simulation time 336924870000 ps
CPU time 856.35 seconds
Started Mar 10 01:00:02 PM PDT 24
Finished Mar 10 01:35:09 PM PDT 24
Peak memory 160616 kb
Host smart-ac39bdac-768a-4e88-8419-d18ce59df20d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175716140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2175716140
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2783088616
Short name T99
Test name
Test status
Simulation time 336619810000 ps
CPU time 855.33 seconds
Started Mar 10 01:00:01 PM PDT 24
Finished Mar 10 01:35:17 PM PDT 24
Peak memory 160632 kb
Host smart-480e2ea9-40be-4348-9e5f-23e3065712a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2783088616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2783088616
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.466410843
Short name T84
Test name
Test status
Simulation time 336378470000 ps
CPU time 895.19 seconds
Started Mar 10 01:00:00 PM PDT 24
Finished Mar 10 01:36:24 PM PDT 24
Peak memory 160680 kb
Host smart-5b336f51-2f02-4a01-b0e2-401ee6f314b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=466410843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.466410843
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4229632263
Short name T188
Test name
Test status
Simulation time 1632210000 ps
CPU time 4.31 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:10 PM PDT 24
Peak memory 164424 kb
Host smart-c75ab00e-c61e-4827-a3d8-28b16882366e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4229632263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4229632263
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3151041574
Short name T163
Test name
Test status
Simulation time 1356150000 ps
CPU time 3.83 seconds
Started Mar 10 12:20:33 PM PDT 24
Finished Mar 10 12:20:42 PM PDT 24
Peak memory 164444 kb
Host smart-cfc94ded-3aa6-4018-9d74-baf47f723ccc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3151041574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3151041574
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3432006070
Short name T192
Test name
Test status
Simulation time 1533290000 ps
CPU time 3.49 seconds
Started Mar 10 12:24:29 PM PDT 24
Finished Mar 10 12:24:37 PM PDT 24
Peak memory 164380 kb
Host smart-9c92f4d7-6836-462f-a004-0e6f3d4fd368
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3432006070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3432006070
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1558374019
Short name T199
Test name
Test status
Simulation time 1395970000 ps
CPU time 3.29 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:13 PM PDT 24
Peak memory 164300 kb
Host smart-c4b9698c-2579-4db9-b5dd-8533286cb527
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1558374019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1558374019
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1730403096
Short name T200
Test name
Test status
Simulation time 1329090000 ps
CPU time 4.18 seconds
Started Mar 10 12:21:46 PM PDT 24
Finished Mar 10 12:21:55 PM PDT 24
Peak memory 164512 kb
Host smart-654f41a0-31ea-4ead-96b2-c0cefac1adef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1730403096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1730403096
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2772598512
Short name T174
Test name
Test status
Simulation time 1560790000 ps
CPU time 4.57 seconds
Started Mar 10 12:24:09 PM PDT 24
Finished Mar 10 12:24:19 PM PDT 24
Peak memory 164356 kb
Host smart-0098083a-bdb4-4abe-8fe7-e7920ddd3e92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2772598512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2772598512
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3972938778
Short name T197
Test name
Test status
Simulation time 1284370000 ps
CPU time 3.26 seconds
Started Mar 10 12:18:16 PM PDT 24
Finished Mar 10 12:18:23 PM PDT 24
Peak memory 164496 kb
Host smart-03dcaee5-7eaa-4272-8ad6-6f913bf9f262
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3972938778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3972938778
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.220280444
Short name T178
Test name
Test status
Simulation time 1423070000 ps
CPU time 3.45 seconds
Started Mar 10 12:24:05 PM PDT 24
Finished Mar 10 12:24:13 PM PDT 24
Peak memory 164368 kb
Host smart-6cea6bef-8fb1-4381-b23a-4939fae55f16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220280444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.220280444
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.923810130
Short name T190
Test name
Test status
Simulation time 1512510000 ps
CPU time 3 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:20 PM PDT 24
Peak memory 164216 kb
Host smart-97d825a9-8803-4189-929b-c7372c0ed6a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=923810130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.923810130
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3694459517
Short name T193
Test name
Test status
Simulation time 1262190000 ps
CPU time 3.77 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:23:59 PM PDT 24
Peak memory 162536 kb
Host smart-eac952f5-0555-4c1a-8afa-c545989da47e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3694459517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3694459517
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1136396902
Short name T176
Test name
Test status
Simulation time 1518030000 ps
CPU time 3.04 seconds
Started Mar 10 12:23:05 PM PDT 24
Finished Mar 10 12:23:12 PM PDT 24
Peak memory 163096 kb
Host smart-d4a5f04e-84a7-47c0-9a17-be635b3cf5af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136396902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1136396902
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.739041808
Short name T169
Test name
Test status
Simulation time 1586770000 ps
CPU time 3.86 seconds
Started Mar 10 12:23:21 PM PDT 24
Finished Mar 10 12:23:29 PM PDT 24
Peak memory 164432 kb
Host smart-74639aeb-e783-4a42-b636-f28f7229d606
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=739041808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.739041808
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.584460601
Short name T170
Test name
Test status
Simulation time 1353590000 ps
CPU time 3.9 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:09 PM PDT 24
Peak memory 164436 kb
Host smart-577ec9aa-33f2-4fe5-b907-6e2d7abee9f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=584460601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.584460601
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4288499210
Short name T167
Test name
Test status
Simulation time 1446490000 ps
CPU time 4.02 seconds
Started Mar 10 12:23:50 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 162488 kb
Host smart-e7fd5bf3-914b-4cce-9539-f25d6b5cc3a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288499210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4288499210
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3996756907
Short name T195
Test name
Test status
Simulation time 1533770000 ps
CPU time 3.21 seconds
Started Mar 10 12:23:54 PM PDT 24
Finished Mar 10 12:24:02 PM PDT 24
Peak memory 164016 kb
Host smart-d8e9dc52-1c44-42ea-8b37-e72672ec30cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996756907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3996756907
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3950730498
Short name T182
Test name
Test status
Simulation time 1421150000 ps
CPU time 3.75 seconds
Started Mar 10 12:20:17 PM PDT 24
Finished Mar 10 12:20:26 PM PDT 24
Peak memory 164536 kb
Host smart-99bf890b-20d8-48ea-b080-69cafecb09b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3950730498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3950730498
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1964070697
Short name T177
Test name
Test status
Simulation time 1188170000 ps
CPU time 3.53 seconds
Started Mar 10 12:20:06 PM PDT 24
Finished Mar 10 12:20:14 PM PDT 24
Peak memory 164520 kb
Host smart-3437c524-cb65-4c34-8d01-727b7026d8e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964070697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1964070697
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3967116500
Short name T158
Test name
Test status
Simulation time 1447010000 ps
CPU time 4.47 seconds
Started Mar 10 12:24:10 PM PDT 24
Finished Mar 10 12:24:20 PM PDT 24
Peak memory 164420 kb
Host smart-a07670f4-6dd1-4350-b90c-0728b3cdeaca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967116500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3967116500
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2234516503
Short name T194
Test name
Test status
Simulation time 1562910000 ps
CPU time 4.6 seconds
Started Mar 10 12:19:21 PM PDT 24
Finished Mar 10 12:19:31 PM PDT 24
Peak memory 164492 kb
Host smart-80bef3c4-0db7-4cb0-8af1-26d84da644ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2234516503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2234516503
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4120944803
Short name T156
Test name
Test status
Simulation time 1524170000 ps
CPU time 3.61 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:17 PM PDT 24
Peak memory 164348 kb
Host smart-d03a5518-ff46-4b7e-8994-dc684920436d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4120944803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4120944803
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2396763
Short name T161
Test name
Test status
Simulation time 1463730000 ps
CPU time 3.7 seconds
Started Mar 10 12:24:00 PM PDT 24
Finished Mar 10 12:24:08 PM PDT 24
Peak memory 164488 kb
Host smart-6ae0ac2d-8fef-4a65-a0d7-0cef4adbb987
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2396763
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3387198325
Short name T165
Test name
Test status
Simulation time 1407190000 ps
CPU time 2.95 seconds
Started Mar 10 12:27:01 PM PDT 24
Finished Mar 10 12:27:08 PM PDT 24
Peak memory 163212 kb
Host smart-c62834df-ecf9-4bc3-a336-0b2740d1b2bc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3387198325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3387198325
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3077397128
Short name T171
Test name
Test status
Simulation time 1315030000 ps
CPU time 3.08 seconds
Started Mar 10 12:23:37 PM PDT 24
Finished Mar 10 12:23:43 PM PDT 24
Peak memory 164344 kb
Host smart-004341b3-2a09-4d56-ac20-4ded24d2b5b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3077397128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3077397128
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1436140196
Short name T157
Test name
Test status
Simulation time 1522270000 ps
CPU time 4.14 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:10 PM PDT 24
Peak memory 164424 kb
Host smart-68312867-4c36-4fec-a433-235c7ae15fc0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1436140196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1436140196
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1962314483
Short name T184
Test name
Test status
Simulation time 1474510000 ps
CPU time 4.92 seconds
Started Mar 10 12:21:03 PM PDT 24
Finished Mar 10 12:21:14 PM PDT 24
Peak memory 164536 kb
Host smart-c0378549-02ff-425e-9bcd-293110bf11ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1962314483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1962314483
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3005100048
Short name T191
Test name
Test status
Simulation time 1562590000 ps
CPU time 3.81 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:10 PM PDT 24
Peak memory 164444 kb
Host smart-7d545052-0a4c-4898-a702-597f98145c80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3005100048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3005100048
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3730816189
Short name T179
Test name
Test status
Simulation time 1550810000 ps
CPU time 3.41 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:23:01 PM PDT 24
Peak memory 164360 kb
Host smart-77ef58a2-5127-4baa-a89c-e100d23c652b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3730816189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3730816189
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1886993746
Short name T172
Test name
Test status
Simulation time 1287610000 ps
CPU time 3.39 seconds
Started Mar 10 12:23:19 PM PDT 24
Finished Mar 10 12:23:27 PM PDT 24
Peak memory 164324 kb
Host smart-47b51827-153d-4a7d-a4f5-db995469b1bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1886993746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1886993746
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1721771137
Short name T155
Test name
Test status
Simulation time 1614130000 ps
CPU time 4.31 seconds
Started Mar 10 12:20:42 PM PDT 24
Finished Mar 10 12:20:52 PM PDT 24
Peak memory 164536 kb
Host smart-a8c6cf95-e089-40e2-ac9b-54eeb1547273
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1721771137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1721771137
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2837047763
Short name T162
Test name
Test status
Simulation time 1566750000 ps
CPU time 3.71 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:27 PM PDT 24
Peak memory 164340 kb
Host smart-cc2a9898-a7f0-4f3c-b7ee-b883b1fd5af8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837047763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2837047763
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3568862729
Short name T168
Test name
Test status
Simulation time 1609210000 ps
CPU time 3.94 seconds
Started Mar 10 12:24:38 PM PDT 24
Finished Mar 10 12:24:47 PM PDT 24
Peak memory 164332 kb
Host smart-0d10c769-204d-4cad-8fb1-6c6906bddd45
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3568862729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3568862729
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1725566711
Short name T189
Test name
Test status
Simulation time 1486290000 ps
CPU time 3.97 seconds
Started Mar 10 12:21:24 PM PDT 24
Finished Mar 10 12:21:33 PM PDT 24
Peak memory 164512 kb
Host smart-37832f82-1354-44d9-9e1b-85c92bcf5ccb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1725566711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1725566711
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.931427835
Short name T164
Test name
Test status
Simulation time 1556230000 ps
CPU time 4.1 seconds
Started Mar 10 12:21:26 PM PDT 24
Finished Mar 10 12:21:35 PM PDT 24
Peak memory 164532 kb
Host smart-0dede228-c0de-46e0-b302-fdf3e243549b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931427835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.931427835
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1721356239
Short name T160
Test name
Test status
Simulation time 1529810000 ps
CPU time 3.74 seconds
Started Mar 10 12:18:22 PM PDT 24
Finished Mar 10 12:18:31 PM PDT 24
Peak memory 164492 kb
Host smart-a0c8990a-1486-40f5-aac3-44d045a20e92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1721356239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1721356239
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.502264983
Short name T151
Test name
Test status
Simulation time 1349450000 ps
CPU time 3.19 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:13 PM PDT 24
Peak memory 164388 kb
Host smart-ddc6a5fb-d9b6-4c6a-b5a7-73b4e232af54
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=502264983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.502264983
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3368187866
Short name T186
Test name
Test status
Simulation time 1430550000 ps
CPU time 3.33 seconds
Started Mar 10 12:24:38 PM PDT 24
Finished Mar 10 12:24:46 PM PDT 24
Peak memory 164328 kb
Host smart-3a363b67-958d-4dfe-ab05-4cbeaa500fb5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3368187866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3368187866
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.970022853
Short name T175
Test name
Test status
Simulation time 1489470000 ps
CPU time 3.38 seconds
Started Mar 10 12:23:29 PM PDT 24
Finished Mar 10 12:23:36 PM PDT 24
Peak memory 164428 kb
Host smart-be9dff73-759c-4cd0-a5c4-92c0d43640cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=970022853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.970022853
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.192211939
Short name T181
Test name
Test status
Simulation time 1421790000 ps
CPU time 2.91 seconds
Started Mar 10 12:24:19 PM PDT 24
Finished Mar 10 12:24:26 PM PDT 24
Peak memory 163324 kb
Host smart-0857b972-5ace-475a-a831-0b6a315b74b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192211939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.192211939
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3556844589
Short name T154
Test name
Test status
Simulation time 1444870000 ps
CPU time 3.42 seconds
Started Mar 10 12:32:50 PM PDT 24
Finished Mar 10 12:32:58 PM PDT 24
Peak memory 164584 kb
Host smart-7ea8e955-8773-4cf6-9f1a-fd0847eda0df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3556844589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3556844589
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4137980482
Short name T159
Test name
Test status
Simulation time 1573250000 ps
CPU time 4.12 seconds
Started Mar 10 12:21:26 PM PDT 24
Finished Mar 10 12:21:35 PM PDT 24
Peak memory 164536 kb
Host smart-09099c1d-8ddb-429c-9084-be550f8a788f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4137980482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.4137980482
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2817744230
Short name T198
Test name
Test status
Simulation time 1511610000 ps
CPU time 3.51 seconds
Started Mar 10 12:23:29 PM PDT 24
Finished Mar 10 12:23:37 PM PDT 24
Peak memory 164360 kb
Host smart-e9c62967-78e8-48be-937a-f10176d0f6be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2817744230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2817744230
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2881726758
Short name T185
Test name
Test status
Simulation time 1459710000 ps
CPU time 3.59 seconds
Started Mar 10 12:20:41 PM PDT 24
Finished Mar 10 12:20:49 PM PDT 24
Peak memory 164540 kb
Host smart-1a2c8dad-4e73-46e8-b6a6-da2ed980f1c2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881726758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2881726758
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3769645232
Short name T152
Test name
Test status
Simulation time 1292190000 ps
CPU time 2.73 seconds
Started Mar 10 12:23:44 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 163068 kb
Host smart-639e4a6c-43e4-4e1a-a9ac-cc08687c8653
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3769645232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3769645232
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3047883665
Short name T196
Test name
Test status
Simulation time 1279690000 ps
CPU time 2.97 seconds
Started Mar 10 12:33:05 PM PDT 24
Finished Mar 10 12:33:11 PM PDT 24
Peak memory 164328 kb
Host smart-ffc01481-1e00-4cf4-ac26-ed3bb1a2d7be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3047883665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3047883665
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3552760531
Short name T173
Test name
Test status
Simulation time 1341830000 ps
CPU time 3.06 seconds
Started Mar 10 12:19:06 PM PDT 24
Finished Mar 10 12:19:13 PM PDT 24
Peak memory 164536 kb
Host smart-d4cbb79e-3f11-4eb2-94b7-ed7b6ed3443e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3552760531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3552760531
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2819502188
Short name T183
Test name
Test status
Simulation time 1560450000 ps
CPU time 4.68 seconds
Started Mar 10 12:21:04 PM PDT 24
Finished Mar 10 12:21:14 PM PDT 24
Peak memory 164532 kb
Host smart-80b39bb4-7992-42a2-aa17-22ad44aa10df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2819502188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2819502188
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1209931715
Short name T187
Test name
Test status
Simulation time 1604350000 ps
CPU time 3.65 seconds
Started Mar 10 12:23:54 PM PDT 24
Finished Mar 10 12:24:03 PM PDT 24
Peak memory 163232 kb
Host smart-ec02308b-5050-4534-8cdc-16d621e8b7f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1209931715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1209931715
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.988697240
Short name T153
Test name
Test status
Simulation time 1542970000 ps
CPU time 3.89 seconds
Started Mar 10 12:19:52 PM PDT 24
Finished Mar 10 12:20:01 PM PDT 24
Peak memory 164516 kb
Host smart-7f884927-6ffe-47d7-b634-42390d5814ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=988697240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.988697240
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.124479551
Short name T180
Test name
Test status
Simulation time 1474310000 ps
CPU time 3.1 seconds
Started Mar 10 12:20:11 PM PDT 24
Finished Mar 10 12:20:19 PM PDT 24
Peak memory 162512 kb
Host smart-3f97cbf4-c29e-4ab0-bdac-4a830374ecc9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124479551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.124479551
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1423901008
Short name T166
Test name
Test status
Simulation time 1305970000 ps
CPU time 3.06 seconds
Started Mar 10 12:24:30 PM PDT 24
Finished Mar 10 12:24:36 PM PDT 24
Peak memory 164452 kb
Host smart-fbd6c9c6-6d6c-44a1-b49c-ab1963770d15
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423901008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1423901008
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3364992442
Short name T66
Test name
Test status
Simulation time 1366930000 ps
CPU time 3.65 seconds
Started Mar 10 01:12:02 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 164584 kb
Host smart-f6a17742-5c8c-466a-a226-dec304c6d13d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3364992442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3364992442
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1407680625
Short name T36
Test name
Test status
Simulation time 1276010000 ps
CPU time 5.02 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 164580 kb
Host smart-bf18b1cb-ad7e-431d-bccf-8a773a53ab01
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1407680625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1407680625
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3814899959
Short name T62
Test name
Test status
Simulation time 1500170000 ps
CPU time 5.22 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 164572 kb
Host smart-276d5361-b7a4-4e7f-b33e-f22786c865cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3814899959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3814899959
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.178512548
Short name T37
Test name
Test status
Simulation time 1427430000 ps
CPU time 4.97 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 164504 kb
Host smart-d5f38a31-74b8-4ae5-8401-60750f33d3d0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=178512548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.178512548
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1160914074
Short name T46
Test name
Test status
Simulation time 1501870000 ps
CPU time 4.81 seconds
Started Mar 10 01:11:59 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 164588 kb
Host smart-5be13ee4-def0-4881-9f53-33293dff1ed6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1160914074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1160914074
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.268780028
Short name T11
Test name
Test status
Simulation time 1590370000 ps
CPU time 4.97 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 164560 kb
Host smart-2b3db477-13b9-4f36-b067-345aef96ccfb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=268780028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.268780028
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2873155208
Short name T12
Test name
Test status
Simulation time 1486470000 ps
CPU time 5.19 seconds
Started Mar 10 01:11:59 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 164552 kb
Host smart-ebf0f08c-abd0-4a65-be93-0e6391283132
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2873155208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2873155208
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1208424690
Short name T33
Test name
Test status
Simulation time 1555850000 ps
CPU time 5.76 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 164580 kb
Host smart-ffedcce1-d97f-4e31-8cd5-f19fa5c4b86e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1208424690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1208424690
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1410917817
Short name T64
Test name
Test status
Simulation time 1463870000 ps
CPU time 5.14 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:12 PM PDT 24
Peak memory 164548 kb
Host smart-fd22e534-0b1c-40fb-a451-8ae9cf7e4ef3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1410917817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1410917817
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3069244504
Short name T59
Test name
Test status
Simulation time 1542410000 ps
CPU time 6.03 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 164580 kb
Host smart-06489f5f-27f9-4e42-8939-36e45c6fdfcf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069244504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3069244504
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2231691116
Short name T35
Test name
Test status
Simulation time 1525070000 ps
CPU time 4.78 seconds
Started Mar 10 01:11:58 PM PDT 24
Finished Mar 10 01:12:09 PM PDT 24
Peak memory 164624 kb
Host smart-f757bccf-da75-4b83-a66b-349b3d88cbb3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2231691116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2231691116
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1720299929
Short name T57
Test name
Test status
Simulation time 1543350000 ps
CPU time 5.03 seconds
Started Mar 10 01:11:58 PM PDT 24
Finished Mar 10 01:12:09 PM PDT 24
Peak memory 164628 kb
Host smart-8efa7d80-713f-4320-8005-a6dcd0343087
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1720299929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1720299929
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1002551839
Short name T1
Test name
Test status
Simulation time 1513450000 ps
CPU time 3.68 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:13 PM PDT 24
Peak memory 164600 kb
Host smart-b3d7b921-0485-4042-8051-b15f02fe386c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002551839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1002551839
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2391289742
Short name T69
Test name
Test status
Simulation time 1413390000 ps
CPU time 4.64 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 164560 kb
Host smart-59e2b171-9de4-4543-a740-4cafc88b2c19
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2391289742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2391289742
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2241192822
Short name T41
Test name
Test status
Simulation time 1485810000 ps
CPU time 4.72 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 164656 kb
Host smart-cd7c9461-03a8-44e9-a142-82025eb58701
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2241192822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2241192822
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.265632637
Short name T53
Test name
Test status
Simulation time 1517970000 ps
CPU time 4.42 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:14 PM PDT 24
Peak memory 164520 kb
Host smart-8083e4b7-01e5-450e-bb3d-760aeaffe3ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=265632637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.265632637
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3259182028
Short name T63
Test name
Test status
Simulation time 1466930000 ps
CPU time 4.77 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:14 PM PDT 24
Peak memory 164548 kb
Host smart-6b555325-cc35-4bd9-af3b-2c25f0a4e2cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259182028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3259182028
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3123715995
Short name T50
Test name
Test status
Simulation time 1429790000 ps
CPU time 4.52 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:14 PM PDT 24
Peak memory 164632 kb
Host smart-9b89044d-907e-490f-93ff-f9cd0ae94b13
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3123715995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3123715995
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1304421979
Short name T67
Test name
Test status
Simulation time 1605770000 ps
CPU time 5.11 seconds
Started Mar 10 01:12:07 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 164568 kb
Host smart-01f150f4-b5c4-45e6-b5ad-9daa7a2d8ace
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1304421979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1304421979
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3594517047
Short name T40
Test name
Test status
Simulation time 1346630000 ps
CPU time 5.79 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 164604 kb
Host smart-bd7fa4b2-134a-40ae-a3fa-5101d4405b22
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3594517047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3594517047
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3529314768
Short name T34
Test name
Test status
Simulation time 1401590000 ps
CPU time 4.33 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 164656 kb
Host smart-eb433ece-3337-4ce5-bcbe-cf20903eaa9c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3529314768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3529314768
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2104260940
Short name T42
Test name
Test status
Simulation time 1446410000 ps
CPU time 3.56 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:12 PM PDT 24
Peak memory 164600 kb
Host smart-32725671-5b18-4794-984d-fdf2b65d1095
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2104260940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2104260940
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3661670897
Short name T31
Test name
Test status
Simulation time 1413330000 ps
CPU time 4.8 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:12 PM PDT 24
Peak memory 164484 kb
Host smart-94722f91-87dc-4ecc-8ab8-42bfad4bac84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3661670897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3661670897
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1083822836
Short name T60
Test name
Test status
Simulation time 1496650000 ps
CPU time 4.99 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 164652 kb
Host smart-79911121-54d7-485a-b9f6-988bbf2123d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1083822836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1083822836
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2282836132
Short name T65
Test name
Test status
Simulation time 1153970000 ps
CPU time 3.42 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:12 PM PDT 24
Peak memory 164580 kb
Host smart-dccc23df-7fee-423f-8f1d-4ce3296cd845
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2282836132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2282836132
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3151423180
Short name T52
Test name
Test status
Simulation time 1343150000 ps
CPU time 3.79 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:13 PM PDT 24
Peak memory 164588 kb
Host smart-300f5c47-a56a-4d80-baac-ef2760c1b322
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3151423180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3151423180
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4098373940
Short name T48
Test name
Test status
Simulation time 1493850000 ps
CPU time 4.57 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 164592 kb
Host smart-bbe49f47-7730-4210-9caf-467750abe5a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4098373940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4098373940
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3422461166
Short name T51
Test name
Test status
Simulation time 1416130000 ps
CPU time 4.79 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 164628 kb
Host smart-f6881843-3078-4609-93ad-730c66a886c0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3422461166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3422461166
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3533144151
Short name T55
Test name
Test status
Simulation time 1547070000 ps
CPU time 4.75 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 164652 kb
Host smart-c62c5a30-d1a4-4771-a13b-fc436163c9c0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3533144151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3533144151
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3671586270
Short name T54
Test name
Test status
Simulation time 1547030000 ps
CPU time 4.92 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 164588 kb
Host smart-01793ae2-cf5c-4780-959f-468b7c0d94f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3671586270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3671586270
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2575764910
Short name T61
Test name
Test status
Simulation time 1573810000 ps
CPU time 4.91 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 164584 kb
Host smart-6c775e64-76ea-4ce9-ac5f-598a8f7e79c8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2575764910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2575764910
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2115118902
Short name T44
Test name
Test status
Simulation time 1490690000 ps
CPU time 4.73 seconds
Started Mar 10 01:12:05 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 164660 kb
Host smart-7bb59306-e3f3-4fbf-8efb-7d5680c88826
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2115118902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2115118902
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.298036988
Short name T49
Test name
Test status
Simulation time 1255790000 ps
CPU time 3.62 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 164588 kb
Host smart-c5522130-e8b0-489b-abfc-11b714a06bd2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298036988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.298036988
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.398375905
Short name T32
Test name
Test status
Simulation time 1421990000 ps
CPU time 4.18 seconds
Started Mar 10 01:12:02 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 164592 kb
Host smart-1c53e962-a5d7-4bb9-8109-c26d7414406c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398375905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.398375905
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1586779286
Short name T39
Test name
Test status
Simulation time 1340150000 ps
CPU time 4.68 seconds
Started Mar 10 01:12:09 PM PDT 24
Finished Mar 10 01:12:19 PM PDT 24
Peak memory 164584 kb
Host smart-2a6f439b-8699-493b-99ed-900af39c7007
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586779286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1586779286
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1901148530
Short name T9
Test name
Test status
Simulation time 1424690000 ps
CPU time 4.37 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:20 PM PDT 24
Peak memory 164584 kb
Host smart-7ce290b8-0ba6-4a19-b3b3-4a1ad798bbfd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1901148530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1901148530
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2481922006
Short name T13
Test name
Test status
Simulation time 1390650000 ps
CPU time 4.84 seconds
Started Mar 10 01:12:08 PM PDT 24
Finished Mar 10 01:12:19 PM PDT 24
Peak memory 164644 kb
Host smart-d1a35af0-6b32-431c-b614-276e0a4229e2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481922006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2481922006
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1568684209
Short name T43
Test name
Test status
Simulation time 1460490000 ps
CPU time 4.14 seconds
Started Mar 10 01:12:12 PM PDT 24
Finished Mar 10 01:12:21 PM PDT 24
Peak memory 164588 kb
Host smart-f09c53d6-4bd8-47e6-bb6f-3f82089ed351
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1568684209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1568684209
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1000441371
Short name T70
Test name
Test status
Simulation time 1625710000 ps
CPU time 5.3 seconds
Started Mar 10 01:12:12 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 164624 kb
Host smart-eca8b67f-4f7d-4d0c-8833-ce193e0395f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1000441371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1000441371
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2385032349
Short name T3
Test name
Test status
Simulation time 1472850000 ps
CPU time 4.63 seconds
Started Mar 10 01:12:09 PM PDT 24
Finished Mar 10 01:12:20 PM PDT 24
Peak memory 164560 kb
Host smart-f256b82f-8cf8-472d-85ac-80e1c8422b6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385032349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2385032349
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3825728413
Short name T68
Test name
Test status
Simulation time 1386070000 ps
CPU time 3.72 seconds
Started Mar 10 01:12:14 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 164660 kb
Host smart-3f30273a-9004-42a9-95f2-731a842a5fa3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3825728413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3825728413
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3972681091
Short name T10
Test name
Test status
Simulation time 1564730000 ps
CPU time 4.09 seconds
Started Mar 10 01:12:09 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 164600 kb
Host smart-f60a976b-da38-435a-8661-ca211bd55fb1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3972681091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3972681091
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2262750136
Short name T56
Test name
Test status
Simulation time 1573950000 ps
CPU time 5.79 seconds
Started Mar 10 01:12:11 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 164588 kb
Host smart-0e84e40e-4a51-4357-8371-e6408f2d3da3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262750136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2262750136
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1701549322
Short name T2
Test name
Test status
Simulation time 1587290000 ps
CPU time 5.72 seconds
Started Mar 10 01:12:11 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 164632 kb
Host smart-1d82029f-a4f4-4849-b1e8-5f8a809cbee2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701549322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1701549322
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.303319056
Short name T7
Test name
Test status
Simulation time 1332910000 ps
CPU time 4.26 seconds
Started Mar 10 01:12:00 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 164632 kb
Host smart-8188dbd6-8537-4254-b67a-8f1f58cd3975
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=303319056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.303319056
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.553469159
Short name T38
Test name
Test status
Simulation time 1535930000 ps
CPU time 5.8 seconds
Started Mar 10 01:12:04 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 164588 kb
Host smart-ce7b06b5-231a-400d-808d-aed18f51770d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=553469159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.553469159
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2401219874
Short name T47
Test name
Test status
Simulation time 1587390000 ps
CPU time 5.5 seconds
Started Mar 10 01:12:06 PM PDT 24
Finished Mar 10 01:12:19 PM PDT 24
Peak memory 164568 kb
Host smart-5cebd8c0-ac43-40e5-b724-235acc38e2af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2401219874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2401219874
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1764519899
Short name T58
Test name
Test status
Simulation time 1272010000 ps
CPU time 3.97 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 164596 kb
Host smart-acadfd98-2d20-46bc-80e6-1eaf847db9c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1764519899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1764519899
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4097856733
Short name T45
Test name
Test status
Simulation time 1367190000 ps
CPU time 3.93 seconds
Started Mar 10 01:12:01 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 164532 kb
Host smart-0744d499-99ed-449c-8260-16182bd41ec0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4097856733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4097856733
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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