| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1097105454 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2453588287 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1534109005 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3965604765 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.105847130 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1660847858 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2715296321 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2842458142 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1492253149 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2948152452 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3496547169 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.139578421 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2757581190 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.917806129 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2257454284 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.19510764 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.700540289 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2014917507 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1517864418 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.367617622 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2855364352 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1214894144 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2854738050 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2300726098 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2042642387 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2712919369 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4161122186 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1151792183 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2396447191 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.173642236 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.933754969 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2605575527 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2479487824 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2232641695 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3646046270 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2937141132 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.104497735 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3645775916 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1392109863 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3844834554 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3407013321 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1476163749 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.55850643 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.549834430 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3881530954 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3917832778 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3231337785 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3023696631 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2357164889 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3790850930 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1721729581 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3291831983 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3677904962 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2023820868 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.459323341 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3917047817 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2255888271 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1752611597 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3586780130 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3044668719 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3093955673 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.90279577 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1471570018 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3853937803 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1307739239 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1688185084 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1905423410 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1169573973 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.67104774 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.454274752 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3089385985 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.827255871 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3451297385 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.518205472 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2101293946 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.865341814 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2655228661 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4255663335 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1814035453 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3031016131 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2042072404 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4021409608 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2868725914 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3577020697 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.708694903 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2609490974 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3660441312 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1756076314 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2970736043 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.971120397 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.736256980 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2725594665 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1365072345 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.566698880 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3303764 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.250208359 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3175354119 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1157641252 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1168321383 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1601906347 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3410179792 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1844429644 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4181422536 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.537157725 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.601563210 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4172955366 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1451242781 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1594987687 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1474199154 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.836407223 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2277080440 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.874983023 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1343481251 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.407541315 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2703093574 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2600113 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2611148300 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2242537983 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1439643555 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3143855437 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.228740584 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2504602696 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3276473910 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2456828751 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2846327082 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1500981817 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3182155193 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3449808138 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1433153443 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2437336205 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1104072598 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1424434893 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1319551388 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2999505106 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1790553899 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.33564396 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1187181795 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1551587059 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1810142232 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.288038463 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2346263867 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2649128976 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2984708963 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3835262418 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1479998447 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4132314062 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3829778873 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4110224285 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2299154058 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.664356355 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1732777233 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3100118416 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2467690903 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4016025196 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3035795515 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.742329238 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3724357331 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3633800229 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3916744929 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2557130310 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4072766605 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.33063739 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1203909763 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.242201126 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3540133159 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.632940390 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4108101288 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2479745084 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.780303652 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4216968319 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.768036071 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3653399594 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1721183514 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.345879767 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2698659506 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3038784560 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3164201275 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3598825588 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3965802864 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2266987283 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3622425937 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2885672251 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2105947551 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4194014367 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.178749072 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1451868755 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1099660212 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1193850188 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2084555800 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.75209034 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1031535199 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.602929774 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2992540691 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.10262848 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2983749808 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1397985495 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.266464293 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.913014626 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2904219855 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4275139965 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.33063739 | Mar 12 12:24:54 PM PDT 24 | Mar 12 12:25:04 PM PDT 24 | 1500030000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3035795515 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:16:48 PM PDT 24 | 1246910000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.780303652 | Mar 12 12:25:00 PM PDT 24 | Mar 12 12:25:07 PM PDT 24 | 1407110000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2904219855 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:16:53 PM PDT 24 | 1493690000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1193850188 | Mar 12 12:22:27 PM PDT 24 | Mar 12 12:22:36 PM PDT 24 | 1512750000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1097105454 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:16:55 PM PDT 24 | 1480470000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.602929774 | Mar 12 12:22:27 PM PDT 24 | Mar 12 12:22:35 PM PDT 24 | 1326830000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1031535199 | Mar 12 12:22:26 PM PDT 24 | Mar 12 12:22:34 PM PDT 24 | 1305890000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3622425937 | Mar 12 12:27:41 PM PDT 24 | Mar 12 12:27:51 PM PDT 24 | 1527470000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2698659506 | Mar 12 12:22:52 PM PDT 24 | Mar 12 12:23:05 PM PDT 24 | 1545750000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3100118416 | Mar 12 12:23:17 PM PDT 24 | Mar 12 12:23:26 PM PDT 24 | 1460410000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3724357331 | Mar 12 12:25:05 PM PDT 24 | Mar 12 12:25:16 PM PDT 24 | 1471470000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4016025196 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:16:48 PM PDT 24 | 1451090000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2084555800 | Mar 12 12:23:27 PM PDT 24 | Mar 12 12:23:40 PM PDT 24 | 1553690000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.75209034 | Mar 12 12:22:35 PM PDT 24 | Mar 12 12:22:42 PM PDT 24 | 1185490000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.10262848 | Mar 12 12:23:28 PM PDT 24 | Mar 12 12:23:39 PM PDT 24 | 1317430000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2266987283 | Mar 12 12:24:39 PM PDT 24 | Mar 12 12:24:49 PM PDT 24 | 1458490000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3540133159 | Mar 12 12:24:52 PM PDT 24 | Mar 12 12:25:01 PM PDT 24 | 1396990000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2885672251 | Mar 12 12:24:36 PM PDT 24 | Mar 12 12:24:45 PM PDT 24 | 1448390000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3916744929 | Mar 12 12:17:26 PM PDT 24 | Mar 12 12:17:35 PM PDT 24 | 1206630000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1099660212 | Mar 12 12:27:39 PM PDT 24 | Mar 12 12:27:48 PM PDT 24 | 1379910000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4108101288 | Mar 12 12:23:44 PM PDT 24 | Mar 12 12:23:53 PM PDT 24 | 1260450000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3965802864 | Mar 12 12:24:35 PM PDT 24 | Mar 12 12:24:43 PM PDT 24 | 1280430000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1203909763 | Mar 12 12:23:16 PM PDT 24 | Mar 12 12:23:27 PM PDT 24 | 1497010000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1721183514 | Mar 12 12:25:53 PM PDT 24 | Mar 12 12:26:02 PM PDT 24 | 1590810000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3653399594 | Mar 12 12:23:48 PM PDT 24 | Mar 12 12:23:58 PM PDT 24 | 1550070000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3598825588 | Mar 12 12:26:02 PM PDT 24 | Mar 12 12:26:12 PM PDT 24 | 1550490000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2479745084 | Mar 12 12:25:58 PM PDT 24 | Mar 12 12:26:05 PM PDT 24 | 1372170000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3038784560 | Mar 12 12:24:14 PM PDT 24 | Mar 12 12:24:22 PM PDT 24 | 1311870000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1397985495 | Mar 12 12:16:41 PM PDT 24 | Mar 12 12:16:53 PM PDT 24 | 1601390000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.768036071 | Mar 12 12:22:15 PM PDT 24 | Mar 12 12:22:22 PM PDT 24 | 1426750000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2992540691 | Mar 12 12:25:07 PM PDT 24 | Mar 12 12:25:16 PM PDT 24 | 1517130000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3164201275 | Mar 12 12:24:21 PM PDT 24 | Mar 12 12:24:30 PM PDT 24 | 1609670000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4216968319 | Mar 12 12:22:26 PM PDT 24 | Mar 12 12:22:34 PM PDT 24 | 1529870000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2467690903 | Mar 12 12:21:10 PM PDT 24 | Mar 12 12:21:23 PM PDT 24 | 1518150000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.178749072 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:16:54 PM PDT 24 | 1381250000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.913014626 | Mar 12 12:16:41 PM PDT 24 | Mar 12 12:16:53 PM PDT 24 | 1525810000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2983749808 | Mar 12 12:17:53 PM PDT 24 | Mar 12 12:18:00 PM PDT 24 | 1433750000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.742329238 | Mar 12 12:20:22 PM PDT 24 | Mar 12 12:20:34 PM PDT 24 | 1596450000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1451868755 | Mar 12 12:24:20 PM PDT 24 | Mar 12 12:24:29 PM PDT 24 | 1601170000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.242201126 | Mar 12 12:24:54 PM PDT 24 | Mar 12 12:25:04 PM PDT 24 | 1567630000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2557130310 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:27:50 PM PDT 24 | 1450170000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4275139965 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:16:50 PM PDT 24 | 1539910000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.266464293 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:16:51 PM PDT 24 | 1274690000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.345879767 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:16:50 PM PDT 24 | 1401950000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2105947551 | Mar 12 12:24:33 PM PDT 24 | Mar 12 12:24:42 PM PDT 24 | 1567650000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.632940390 | Mar 12 12:23:32 PM PDT 24 | Mar 12 12:23:43 PM PDT 24 | 1405170000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4194014367 | Mar 12 12:24:20 PM PDT 24 | Mar 12 12:24:29 PM PDT 24 | 1545430000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4072766605 | Mar 12 12:23:42 PM PDT 24 | Mar 12 12:23:50 PM PDT 24 | 1463230000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3633800229 | Mar 12 12:17:26 PM PDT 24 | Mar 12 12:17:36 PM PDT 24 | 1447750000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3451297385 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:51:20 PM PDT 24 | 336580110000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2453588287 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:58:07 PM PDT 24 | 336822710000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.67104774 | Mar 12 12:16:28 PM PDT 24 | Mar 12 12:50:53 PM PDT 24 | 336806570000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3303764 | Mar 12 12:16:42 PM PDT 24 | Mar 12 01:00:27 PM PDT 24 | 336771070000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1688185084 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:53:04 PM PDT 24 | 336790810000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.708694903 | Mar 12 12:16:38 PM PDT 24 | Mar 12 12:49:08 PM PDT 24 | 336387250000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3044668719 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:49:38 PM PDT 24 | 336758030000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3093955673 | Mar 12 12:16:36 PM PDT 24 | Mar 12 12:59:52 PM PDT 24 | 336706270000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.454274752 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:57:28 PM PDT 24 | 336331750000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2970736043 | Mar 12 12:16:37 PM PDT 24 | Mar 12 12:59:58 PM PDT 24 | 337073870000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1471570018 | Mar 12 12:16:41 PM PDT 24 | Mar 12 01:00:16 PM PDT 24 | 336395570000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1905423410 | Mar 12 12:16:42 PM PDT 24 | Mar 12 01:00:20 PM PDT 24 | 336656490000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.971120397 | Mar 12 12:16:36 PM PDT 24 | Mar 12 12:59:53 PM PDT 24 | 336688010000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1168321383 | Mar 12 12:16:41 PM PDT 24 | Mar 12 12:50:38 PM PDT 24 | 336502570000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3175354119 | Mar 12 12:25:07 PM PDT 24 | Mar 12 12:50:40 PM PDT 24 | 336994630000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2868725914 | Mar 12 12:16:36 PM PDT 24 | Mar 12 12:59:48 PM PDT 24 | 336541210000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1844429644 | Mar 12 12:16:43 PM PDT 24 | Mar 12 01:00:14 PM PDT 24 | 336506130000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1601906347 | Mar 12 12:16:28 PM PDT 24 | Mar 12 12:51:58 PM PDT 24 | 336526210000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2023820868 | Mar 12 12:16:41 PM PDT 24 | Mar 12 01:00:19 PM PDT 24 | 337167550000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2609490974 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:52:29 PM PDT 24 | 336639830000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.90279577 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:59:00 PM PDT 24 | 336339470000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3089385985 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:58:51 PM PDT 24 | 337130130000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4255663335 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:49:35 PM PDT 24 | 337026150000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1157641252 | Mar 12 12:16:28 PM PDT 24 | Mar 12 12:51:47 PM PDT 24 | 336860350000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1756076314 | Mar 12 12:16:31 PM PDT 24 | Mar 12 12:41:54 PM PDT 24 | 337000310000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.250208359 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:52:39 PM PDT 24 | 336699250000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.865341814 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:52:49 PM PDT 24 | 336686210000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2042072404 | Mar 12 12:16:37 PM PDT 24 | Mar 12 12:59:59 PM PDT 24 | 336466290000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1365072345 | Mar 12 12:22:17 PM PDT 24 | Mar 12 12:49:27 PM PDT 24 | 336983030000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3410179792 | Mar 12 12:16:38 PM PDT 24 | Mar 12 12:50:15 PM PDT 24 | 336398210000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.518205472 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:50:18 PM PDT 24 | 336760290000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4021409608 | Mar 12 12:16:37 PM PDT 24 | Mar 12 01:00:00 PM PDT 24 | 336428210000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3660441312 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:58:47 PM PDT 24 | 336659710000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3577020697 | Mar 12 12:16:36 PM PDT 24 | Mar 12 01:00:01 PM PDT 24 | 336576010000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.827255871 | Mar 12 12:16:42 PM PDT 24 | Mar 12 01:00:16 PM PDT 24 | 336389030000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2725594665 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:53:35 PM PDT 24 | 336835990000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2101293946 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:51:45 PM PDT 24 | 336406670000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3917047817 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:58:54 PM PDT 24 | 336423970000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2255888271 | Mar 12 12:16:43 PM PDT 24 | Mar 12 01:00:19 PM PDT 24 | 336571510000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3031016131 | Mar 12 12:16:42 PM PDT 24 | Mar 12 01:00:34 PM PDT 24 | 336584290000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3586780130 | Mar 12 12:16:42 PM PDT 24 | Mar 12 01:00:27 PM PDT 24 | 336687690000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1752611597 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:52:47 PM PDT 24 | 336532930000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.566698880 | Mar 12 12:16:41 PM PDT 24 | Mar 12 12:59:36 PM PDT 24 | 336455170000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.459323341 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:55:24 PM PDT 24 | 337128090000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1307739239 | Mar 12 12:16:41 PM PDT 24 | Mar 12 12:59:15 PM PDT 24 | 336386510000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1169573973 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:51:21 PM PDT 24 | 337068770000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1814035453 | Mar 12 12:16:31 PM PDT 24 | Mar 12 12:41:50 PM PDT 24 | 336951210000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2655228661 | Mar 12 12:16:37 PM PDT 24 | Mar 12 12:59:55 PM PDT 24 | 336963210000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3853937803 | Mar 12 12:16:37 PM PDT 24 | Mar 12 12:59:52 PM PDT 24 | 337035630000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.736256980 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:51:47 PM PDT 24 | 336955790000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1424434893 | Mar 12 12:24:33 PM PDT 24 | Mar 12 12:24:42 PM PDT 24 | 1580190000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2299154058 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:27:50 PM PDT 24 | 1365970000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1810142232 | Mar 12 12:27:23 PM PDT 24 | Mar 12 12:27:30 PM PDT 24 | 1523330000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.33564396 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:16:55 PM PDT 24 | 1578470000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2504602696 | Mar 12 12:23:44 PM PDT 24 | Mar 12 12:23:54 PM PDT 24 | 1527510000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3965604765 | Mar 12 12:22:27 PM PDT 24 | Mar 12 12:22:36 PM PDT 24 | 1589370000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1439643555 | Mar 12 12:18:06 PM PDT 24 | Mar 12 12:18:17 PM PDT 24 | 1280130000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.228740584 | Mar 12 12:18:02 PM PDT 24 | Mar 12 12:18:12 PM PDT 24 | 1388190000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1732777233 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:16:54 PM PDT 24 | 1506470000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1594987687 | Mar 12 12:25:05 PM PDT 24 | Mar 12 12:25:17 PM PDT 24 | 1662610000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.407541315 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:16:56 PM PDT 24 | 1509590000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.288038463 | Mar 12 12:23:32 PM PDT 24 | Mar 12 12:23:42 PM PDT 24 | 1460390000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4110224285 | Mar 12 12:16:31 PM PDT 24 | Mar 12 12:16:39 PM PDT 24 | 1418770000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2437336205 | Mar 12 12:24:14 PM PDT 24 | Mar 12 12:24:21 PM PDT 24 | 1140370000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4181422536 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:16:48 PM PDT 24 | 1348390000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1500981817 | Mar 12 12:22:52 PM PDT 24 | Mar 12 12:23:03 PM PDT 24 | 1344550000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1551587059 | Mar 12 12:24:39 PM PDT 24 | Mar 12 12:24:50 PM PDT 24 | 1518210000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2999505106 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:27:48 PM PDT 24 | 1424130000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3182155193 | Mar 12 12:22:52 PM PDT 24 | Mar 12 12:23:05 PM PDT 24 | 1602950000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2846327082 | Mar 12 12:16:41 PM PDT 24 | Mar 12 12:16:50 PM PDT 24 | 1543910000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3829778873 | Mar 12 12:16:31 PM PDT 24 | Mar 12 12:16:39 PM PDT 24 | 1338510000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2984708963 | Mar 12 12:23:16 PM PDT 24 | Mar 12 12:23:26 PM PDT 24 | 1439770000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1433153443 | Mar 12 12:24:07 PM PDT 24 | Mar 12 12:24:15 PM PDT 24 | 1499970000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3276473910 | Mar 12 12:22:26 PM PDT 24 | Mar 12 12:22:34 PM PDT 24 | 1585470000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2703093574 | Mar 12 12:24:49 PM PDT 24 | Mar 12 12:24:56 PM PDT 24 | 1431450000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2277080440 | Mar 12 12:25:15 PM PDT 24 | Mar 12 12:25:24 PM PDT 24 | 1390290000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1104072598 | Mar 12 12:24:39 PM PDT 24 | Mar 12 12:24:48 PM PDT 24 | 1278710000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3835262418 | Mar 12 12:25:07 PM PDT 24 | Mar 12 12:25:17 PM PDT 24 | 1577910000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1479998447 | Mar 12 12:23:16 PM PDT 24 | Mar 12 12:23:27 PM PDT 24 | 1540130000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1187181795 | Mar 12 12:24:29 PM PDT 24 | Mar 12 12:24:36 PM PDT 24 | 1427210000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.537157725 | Mar 12 12:16:37 PM PDT 24 | Mar 12 12:16:48 PM PDT 24 | 1532450000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2600113 | Mar 12 12:27:21 PM PDT 24 | Mar 12 12:27:28 PM PDT 24 | 1379210000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2456828751 | Mar 12 12:23:43 PM PDT 24 | Mar 12 12:23:53 PM PDT 24 | 1374750000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.874983023 | Mar 12 12:25:02 PM PDT 24 | Mar 12 12:25:10 PM PDT 24 | 1241770000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4132314062 | Mar 12 12:22:35 PM PDT 24 | Mar 12 12:22:44 PM PDT 24 | 1580390000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1790553899 | Mar 12 12:27:41 PM PDT 24 | Mar 12 12:27:51 PM PDT 24 | 1469510000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2649128976 | Mar 12 12:17:31 PM PDT 24 | Mar 12 12:17:43 PM PDT 24 | 1380130000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2346263867 | Mar 12 12:23:26 PM PDT 24 | Mar 12 12:23:37 PM PDT 24 | 1219370000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2611148300 | Mar 12 12:25:01 PM PDT 24 | Mar 12 12:25:08 PM PDT 24 | 1366930000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4172955366 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:16:48 PM PDT 24 | 1532310000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1343481251 | Mar 12 12:20:23 PM PDT 24 | Mar 12 12:20:36 PM PDT 24 | 1500710000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2242537983 | Mar 12 12:22:52 PM PDT 24 | Mar 12 12:23:04 PM PDT 24 | 1444690000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3449808138 | Mar 12 12:25:54 PM PDT 24 | Mar 12 12:26:03 PM PDT 24 | 1512250000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1319551388 | Mar 12 12:24:39 PM PDT 24 | Mar 12 12:24:50 PM PDT 24 | 1528830000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1451242781 | Mar 12 12:25:03 PM PDT 24 | Mar 12 12:25:11 PM PDT 24 | 1372370000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.836407223 | Mar 12 12:25:05 PM PDT 24 | Mar 12 12:25:16 PM PDT 24 | 1333110000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1474199154 | Mar 12 12:30:39 PM PDT 24 | Mar 12 12:30:49 PM PDT 24 | 1218330000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.664356355 | Mar 12 12:27:39 PM PDT 24 | Mar 12 12:27:48 PM PDT 24 | 1207330000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3143855437 | Mar 12 12:26:17 PM PDT 24 | Mar 12 12:26:27 PM PDT 24 | 1288550000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.601563210 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:16:57 PM PDT 24 | 1618810000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1151792183 | Mar 12 12:24:14 PM PDT 24 | Mar 12 12:52:19 PM PDT 24 | 336845770000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2605575527 | Mar 12 12:24:39 PM PDT 24 | Mar 12 12:49:11 PM PDT 24 | 336995370000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2937141132 | Mar 12 12:23:53 PM PDT 24 | Mar 12 12:48:55 PM PDT 24 | 337006570000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4161122186 | Mar 12 12:23:15 PM PDT 24 | Mar 12 12:51:39 PM PDT 24 | 336480510000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1517864418 | Mar 12 12:24:52 PM PDT 24 | Mar 12 12:52:36 PM PDT 24 | 336457230000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2300726098 | Mar 12 12:25:54 PM PDT 24 | Mar 12 12:52:25 PM PDT 24 | 336881430000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.19510764 | Mar 12 12:18:27 PM PDT 24 | Mar 12 12:53:58 PM PDT 24 | 336479670000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1534109005 | Mar 12 12:23:32 PM PDT 24 | Mar 12 12:51:16 PM PDT 24 | 336781790000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3844834554 | Mar 12 12:22:26 PM PDT 24 | Mar 12 12:49:14 PM PDT 24 | 336792350000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3496547169 | Mar 12 12:23:21 PM PDT 24 | Mar 12 12:53:28 PM PDT 24 | 336515430000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3231337785 | Mar 12 12:22:46 PM PDT 24 | Mar 12 12:52:17 PM PDT 24 | 336927830000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3677904962 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:52:48 PM PDT 24 | 337059670000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1392109863 | Mar 12 12:22:27 PM PDT 24 | Mar 12 12:48:20 PM PDT 24 | 336621290000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2842458142 | Mar 12 12:20:20 PM PDT 24 | Mar 12 12:55:41 PM PDT 24 | 336630790000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3407013321 | Mar 12 12:22:26 PM PDT 24 | Mar 12 12:49:18 PM PDT 24 | 336456150000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.139578421 | Mar 12 12:24:54 PM PDT 24 | Mar 12 12:53:42 PM PDT 24 | 337147850000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.917806129 | Mar 12 12:23:31 PM PDT 24 | Mar 12 12:53:13 PM PDT 24 | 336549630000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.549834430 | Mar 12 12:22:47 PM PDT 24 | Mar 12 12:54:06 PM PDT 24 | 336568090000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1492253149 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:55:27 PM PDT 24 | 336841150000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2757581190 | Mar 12 12:24:57 PM PDT 24 | Mar 12 12:49:37 PM PDT 24 | 336763770000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2712919369 | Mar 12 12:22:52 PM PDT 24 | Mar 12 12:56:08 PM PDT 24 | 336474190000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.933754969 | Mar 12 12:23:21 PM PDT 24 | Mar 12 12:53:17 PM PDT 24 | 336499630000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1476163749 | Mar 12 12:23:26 PM PDT 24 | Mar 12 12:55:38 PM PDT 24 | 337101070000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3917832778 | Mar 12 12:23:16 PM PDT 24 | Mar 12 12:50:13 PM PDT 24 | 336525750000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.700540289 | Mar 12 12:23:31 PM PDT 24 | Mar 12 12:53:18 PM PDT 24 | 336325470000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3790850930 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:53:25 PM PDT 24 | 337005090000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2854738050 | Mar 12 12:20:25 PM PDT 24 | Mar 12 12:56:55 PM PDT 24 | 336558830000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2855364352 | Mar 12 12:26:15 PM PDT 24 | Mar 12 12:58:34 PM PDT 24 | 337095650000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2357164889 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:53:42 PM PDT 24 | 336584330000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2042642387 | Mar 12 12:22:52 PM PDT 24 | Mar 12 12:56:01 PM PDT 24 | 336922970000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.367617622 | Mar 12 12:26:17 PM PDT 24 | Mar 12 12:58:32 PM PDT 24 | 336597910000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1214894144 | Mar 12 12:24:21 PM PDT 24 | Mar 12 12:53:47 PM PDT 24 | 336490850000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3646046270 | Mar 12 12:23:26 PM PDT 24 | Mar 12 12:55:40 PM PDT 24 | 336722070000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1660847858 | Mar 12 12:16:39 PM PDT 24 | Mar 12 12:49:10 PM PDT 24 | 336743870000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.105847130 | Mar 12 12:22:46 PM PDT 24 | Mar 12 12:53:24 PM PDT 24 | 336868810000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2014917507 | Mar 12 12:16:40 PM PDT 24 | Mar 12 12:52:24 PM PDT 24 | 336989730000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2257454284 | Mar 12 12:16:42 PM PDT 24 | Mar 12 12:52:53 PM PDT 24 | 336777690000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2715296321 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:53:03 PM PDT 24 | 336613650000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3291831983 | Mar 12 12:16:43 PM PDT 24 | Mar 12 12:53:16 PM PDT 24 | 337088990000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.104497735 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:55:14 PM PDT 24 | 336774570000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.173642236 | Mar 12 12:23:56 PM PDT 24 | Mar 12 12:49:30 PM PDT 24 | 336585970000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2232641695 | Mar 12 12:27:41 PM PDT 24 | Mar 12 12:56:43 PM PDT 24 | 336486170000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3881530954 | Mar 12 12:22:35 PM PDT 24 | Mar 12 12:52:32 PM PDT 24 | 336902290000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2479487824 | Mar 12 12:24:21 PM PDT 24 | Mar 12 12:53:23 PM PDT 24 | 336863390000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2396447191 | Mar 12 12:26:02 PM PDT 24 | Mar 12 12:51:24 PM PDT 24 | 336675150000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2948152452 | Mar 12 12:17:35 PM PDT 24 | Mar 12 01:01:06 PM PDT 24 | 337059330000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3023696631 | Mar 12 12:23:17 PM PDT 24 | Mar 12 12:50:09 PM PDT 24 | 336769190000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3645775916 | Mar 12 12:16:38 PM PDT 24 | Mar 12 12:47:52 PM PDT 24 | 336605290000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.55850643 | Mar 12 12:20:49 PM PDT 24 | Mar 12 12:57:30 PM PDT 24 | 336962450000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1721729581 | Mar 12 12:23:47 PM PDT 24 | Mar 12 12:51:43 PM PDT 24 | 336317270000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1097105454 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1480470000 ps |
| CPU time | 5.32 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:16:55 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-268e2912-36f2-4e32-b786-57f5c1c192a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1097105454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1097105454 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2453588287 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336822710000 ps |
| CPU time | 998.31 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:58:07 PM PDT 24 |
| Peak memory | 160248 kb |
| Host | smart-c3344e22-690d-4d27-965f-b3ef18feb527 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2453588287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2453588287 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1534109005 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336781790000 ps |
| CPU time | 670.38 seconds |
| Started | Mar 12 12:23:32 PM PDT 24 |
| Finished | Mar 12 12:51:16 PM PDT 24 |
| Peak memory | 159796 kb |
| Host | smart-73c482bd-af7f-4d0c-87d3-e54adf9c3fc7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1534109005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1534109005 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3965604765 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1589370000 ps |
| CPU time | 4.19 seconds |
| Started | Mar 12 12:22:27 PM PDT 24 |
| Finished | Mar 12 12:22:36 PM PDT 24 |
| Peak memory | 164192 kb |
| Host | smart-79feb0a7-83c4-41f8-a340-5603f5a746a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3965604765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3965604765 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.105847130 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336868810000 ps |
| CPU time | 728.84 seconds |
| Started | Mar 12 12:22:46 PM PDT 24 |
| Finished | Mar 12 12:53:24 PM PDT 24 |
| Peak memory | 160496 kb |
| Host | smart-d20b4339-5c46-4f4a-879b-e3c4204d4e12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=105847130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.105847130 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1660847858 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336743870000 ps |
| CPU time | 776.5 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:49:10 PM PDT 24 |
| Peak memory | 160216 kb |
| Host | smart-3d58ebaa-52d8-40ef-921d-cc58ec9e2cfb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1660847858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1660847858 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2715296321 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336613650000 ps |
| CPU time | 877.6 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:53:03 PM PDT 24 |
| Peak memory | 160136 kb |
| Host | smart-6d4c661c-f61d-44e1-ad77-525f348264c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2715296321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2715296321 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2842458142 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336630790000 ps |
| CPU time | 869.94 seconds |
| Started | Mar 12 12:20:20 PM PDT 24 |
| Finished | Mar 12 12:55:41 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-a44ff297-b0c6-4c6c-8ed0-f3587aadd954 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2842458142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2842458142 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1492253149 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336841150000 ps |
| CPU time | 675.15 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:55:27 PM PDT 24 |
| Peak memory | 160444 kb |
| Host | smart-9c28dd76-6ee3-4619-a63e-d63370ba4ba2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1492253149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1492253149 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2948152452 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 337059330000 ps |
| CPU time | 1052.41 seconds |
| Started | Mar 12 12:17:35 PM PDT 24 |
| Finished | Mar 12 01:01:06 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-709b4911-19b1-4862-9c85-95b8d1d27277 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2948152452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2948152452 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3496547169 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336515430000 ps |
| CPU time | 717.26 seconds |
| Started | Mar 12 12:23:21 PM PDT 24 |
| Finished | Mar 12 12:53:28 PM PDT 24 |
| Peak memory | 159344 kb |
| Host | smart-4aeea4e5-f160-4c64-9f35-e29d2503d330 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3496547169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3496547169 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.139578421 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 337147850000 ps |
| CPU time | 701.48 seconds |
| Started | Mar 12 12:24:54 PM PDT 24 |
| Finished | Mar 12 12:53:42 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-7af422c8-faf7-4e6c-8ba1-03bbd14a8c14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=139578421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.139578421 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2757581190 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336763770000 ps |
| CPU time | 607.87 seconds |
| Started | Mar 12 12:24:57 PM PDT 24 |
| Finished | Mar 12 12:49:37 PM PDT 24 |
| Peak memory | 160452 kb |
| Host | smart-6541aed9-f620-4a36-a4e4-c52f9841a6b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2757581190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2757581190 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.917806129 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336549630000 ps |
| CPU time | 700.89 seconds |
| Started | Mar 12 12:23:31 PM PDT 24 |
| Finished | Mar 12 12:53:13 PM PDT 24 |
| Peak memory | 160344 kb |
| Host | smart-b8cb0e76-cc41-4049-a5c7-ec00e6d5d71f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=917806129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.917806129 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2257454284 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336777690000 ps |
| CPU time | 884.74 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:52:53 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-f9965f7f-1993-401e-bcfe-a6ae9519325c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2257454284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2257454284 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.19510764 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336479670000 ps |
| CPU time | 873.51 seconds |
| Started | Mar 12 12:18:27 PM PDT 24 |
| Finished | Mar 12 12:53:58 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-20ec358d-0b16-4234-9ad3-6ade1f1c2aa4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=19510764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.19510764 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.700540289 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336325470000 ps |
| CPU time | 700.36 seconds |
| Started | Mar 12 12:23:31 PM PDT 24 |
| Finished | Mar 12 12:53:18 PM PDT 24 |
| Peak memory | 160344 kb |
| Host | smart-3c11d085-8ad1-4993-aa73-3d5cb9efdbb3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=700540289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.700540289 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2014917507 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336989730000 ps |
| CPU time | 882.8 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:52:24 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-c6fcaf67-edc8-4be6-8486-937fccf7d482 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2014917507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2014917507 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1517864418 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336457230000 ps |
| CPU time | 681 seconds |
| Started | Mar 12 12:24:52 PM PDT 24 |
| Finished | Mar 12 12:52:36 PM PDT 24 |
| Peak memory | 159252 kb |
| Host | smart-3a6f090b-b031-4ea8-bd5f-45ddaebb96d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1517864418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1517864418 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.367617622 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336597910000 ps |
| CPU time | 784.61 seconds |
| Started | Mar 12 12:26:17 PM PDT 24 |
| Finished | Mar 12 12:58:32 PM PDT 24 |
| Peak memory | 160504 kb |
| Host | smart-e12404a2-2fb7-4f89-ae5b-e8c41b5eecce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=367617622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.367617622 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2855364352 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 337095650000 ps |
| CPU time | 785.85 seconds |
| Started | Mar 12 12:26:15 PM PDT 24 |
| Finished | Mar 12 12:58:34 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-e77b198b-a310-46c5-8a27-467c7ed5399e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2855364352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2855364352 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1214894144 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336490850000 ps |
| CPU time | 711.18 seconds |
| Started | Mar 12 12:24:21 PM PDT 24 |
| Finished | Mar 12 12:53:47 PM PDT 24 |
| Peak memory | 160448 kb |
| Host | smart-b412fe2c-b155-4fe3-b99b-8f843ea82b92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1214894144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1214894144 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2854738050 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336558830000 ps |
| CPU time | 894.73 seconds |
| Started | Mar 12 12:20:25 PM PDT 24 |
| Finished | Mar 12 12:56:55 PM PDT 24 |
| Peak memory | 160568 kb |
| Host | smart-7c0de3ec-3865-48a7-876d-0babfa2f066f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2854738050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2854738050 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2300726098 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336881430000 ps |
| CPU time | 651.1 seconds |
| Started | Mar 12 12:25:54 PM PDT 24 |
| Finished | Mar 12 12:52:25 PM PDT 24 |
| Peak memory | 160348 kb |
| Host | smart-c9336b53-5106-46b7-b57b-86048d98f081 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2300726098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2300726098 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2042642387 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336922970000 ps |
| CPU time | 809.42 seconds |
| Started | Mar 12 12:22:52 PM PDT 24 |
| Finished | Mar 12 12:56:01 PM PDT 24 |
| Peak memory | 159276 kb |
| Host | smart-9080201a-553b-4c2f-83ee-0b0e9d1722a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2042642387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2042642387 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2712919369 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336474190000 ps |
| CPU time | 809.51 seconds |
| Started | Mar 12 12:22:52 PM PDT 24 |
| Finished | Mar 12 12:56:08 PM PDT 24 |
| Peak memory | 158488 kb |
| Host | smart-d10d4fec-81f1-46e8-9a86-3ad33ff8e2d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2712919369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2712919369 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4161122186 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336480510000 ps |
| CPU time | 677.33 seconds |
| Started | Mar 12 12:23:15 PM PDT 24 |
| Finished | Mar 12 12:51:39 PM PDT 24 |
| Peak memory | 159136 kb |
| Host | smart-a276163b-e90c-4fba-ab8c-6d20bf3c1753 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4161122186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4161122186 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1151792183 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336845770000 ps |
| CPU time | 683.82 seconds |
| Started | Mar 12 12:24:14 PM PDT 24 |
| Finished | Mar 12 12:52:19 PM PDT 24 |
| Peak memory | 160292 kb |
| Host | smart-16975431-9753-4109-9487-23cddfd85977 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1151792183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1151792183 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2396447191 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336675150000 ps |
| CPU time | 612.67 seconds |
| Started | Mar 12 12:26:02 PM PDT 24 |
| Finished | Mar 12 12:51:24 PM PDT 24 |
| Peak memory | 159524 kb |
| Host | smart-e68ba20e-9fae-446c-bf01-28a43c9386dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2396447191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2396447191 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.173642236 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336585970000 ps |
| CPU time | 629.44 seconds |
| Started | Mar 12 12:23:56 PM PDT 24 |
| Finished | Mar 12 12:49:30 PM PDT 24 |
| Peak memory | 160228 kb |
| Host | smart-54cabebb-638c-4bd4-87c6-4810ca8a70c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=173642236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.173642236 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.933754969 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336499630000 ps |
| CPU time | 711.48 seconds |
| Started | Mar 12 12:23:21 PM PDT 24 |
| Finished | Mar 12 12:53:17 PM PDT 24 |
| Peak memory | 159312 kb |
| Host | smart-476d856c-a143-4cb6-8d72-883593462cb6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=933754969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.933754969 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2605575527 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336995370000 ps |
| CPU time | 591.33 seconds |
| Started | Mar 12 12:24:39 PM PDT 24 |
| Finished | Mar 12 12:49:11 PM PDT 24 |
| Peak memory | 159468 kb |
| Host | smart-4e6933cc-72bc-49c4-9b26-0de687cf1363 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2605575527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2605575527 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2479487824 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336863390000 ps |
| CPU time | 700.45 seconds |
| Started | Mar 12 12:24:21 PM PDT 24 |
| Finished | Mar 12 12:53:23 PM PDT 24 |
| Peak memory | 160448 kb |
| Host | smart-48dcfed2-2e90-412c-a428-5e0f8613b772 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2479487824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2479487824 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2232641695 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336486170000 ps |
| CPU time | 703.06 seconds |
| Started | Mar 12 12:27:41 PM PDT 24 |
| Finished | Mar 12 12:56:43 PM PDT 24 |
| Peak memory | 160484 kb |
| Host | smart-4899ef7a-638e-4584-a73a-b64c94a41d40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2232641695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2232641695 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3646046270 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336722070000 ps |
| CPU time | 781.01 seconds |
| Started | Mar 12 12:23:26 PM PDT 24 |
| Finished | Mar 12 12:55:40 PM PDT 24 |
| Peak memory | 159052 kb |
| Host | smart-26e586c4-9a04-4c2d-a61e-c0b6f7764c6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3646046270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3646046270 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2937141132 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 337006570000 ps |
| CPU time | 612.66 seconds |
| Started | Mar 12 12:23:53 PM PDT 24 |
| Finished | Mar 12 12:48:55 PM PDT 24 |
| Peak memory | 159184 kb |
| Host | smart-5a23153c-a8ec-4530-a723-5459575e73e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2937141132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2937141132 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.104497735 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336774570000 ps |
| CPU time | 672.13 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:55:14 PM PDT 24 |
| Peak memory | 160480 kb |
| Host | smart-1fd2a223-0137-439d-9c2a-f6038005eebb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=104497735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.104497735 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3645775916 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336605290000 ps |
| CPU time | 744.89 seconds |
| Started | Mar 12 12:16:38 PM PDT 24 |
| Finished | Mar 12 12:47:52 PM PDT 24 |
| Peak memory | 160188 kb |
| Host | smart-69bdf986-7ddd-4e79-874e-f322d9fa6036 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3645775916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3645775916 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1392109863 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336621290000 ps |
| CPU time | 624.22 seconds |
| Started | Mar 12 12:22:27 PM PDT 24 |
| Finished | Mar 12 12:48:20 PM PDT 24 |
| Peak memory | 160156 kb |
| Host | smart-387e3502-c19a-4cec-a8ce-70af1d6255a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1392109863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1392109863 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3844834554 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336792350000 ps |
| CPU time | 650.79 seconds |
| Started | Mar 12 12:22:26 PM PDT 24 |
| Finished | Mar 12 12:49:14 PM PDT 24 |
| Peak memory | 159784 kb |
| Host | smart-a0aac028-2873-4775-a33e-7c174365078b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3844834554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3844834554 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3407013321 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336456150000 ps |
| CPU time | 645.93 seconds |
| Started | Mar 12 12:22:26 PM PDT 24 |
| Finished | Mar 12 12:49:18 PM PDT 24 |
| Peak memory | 159460 kb |
| Host | smart-5d1297f7-b80a-46fe-a3fb-5c42681790a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3407013321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3407013321 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1476163749 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 337101070000 ps |
| CPU time | 780.3 seconds |
| Started | Mar 12 12:23:26 PM PDT 24 |
| Finished | Mar 12 12:55:38 PM PDT 24 |
| Peak memory | 159116 kb |
| Host | smart-9c508354-a699-4391-80b3-f9fe038b1072 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1476163749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1476163749 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.55850643 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336962450000 ps |
| CPU time | 903.99 seconds |
| Started | Mar 12 12:20:49 PM PDT 24 |
| Finished | Mar 12 12:57:30 PM PDT 24 |
| Peak memory | 160556 kb |
| Host | smart-96ed2ec1-ede5-485c-8503-aab3bdc01495 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=55850643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.55850643 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.549834430 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336568090000 ps |
| CPU time | 748.31 seconds |
| Started | Mar 12 12:22:47 PM PDT 24 |
| Finished | Mar 12 12:54:06 PM PDT 24 |
| Peak memory | 160484 kb |
| Host | smart-de7f0d69-e408-4c1b-b78d-d071c48630ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=549834430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.549834430 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3881530954 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336902290000 ps |
| CPU time | 706.64 seconds |
| Started | Mar 12 12:22:35 PM PDT 24 |
| Finished | Mar 12 12:52:32 PM PDT 24 |
| Peak memory | 159388 kb |
| Host | smart-fc42f940-cf0a-4ddd-8288-9535cc3c077a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3881530954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3881530954 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3917832778 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336525750000 ps |
| CPU time | 655.1 seconds |
| Started | Mar 12 12:23:16 PM PDT 24 |
| Finished | Mar 12 12:50:13 PM PDT 24 |
| Peak memory | 160044 kb |
| Host | smart-cd1dcf97-5025-48d8-aced-41da07d25626 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3917832778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3917832778 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3231337785 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336927830000 ps |
| CPU time | 700.94 seconds |
| Started | Mar 12 12:22:46 PM PDT 24 |
| Finished | Mar 12 12:52:17 PM PDT 24 |
| Peak memory | 160488 kb |
| Host | smart-9529bcb8-22ec-46fa-ba90-c0e6b419944d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3231337785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3231337785 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3023696631 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336769190000 ps |
| CPU time | 653.09 seconds |
| Started | Mar 12 12:23:17 PM PDT 24 |
| Finished | Mar 12 12:50:09 PM PDT 24 |
| Peak memory | 160212 kb |
| Host | smart-68154f5c-14cb-4a7c-89da-fdbee4d4cf6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3023696631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3023696631 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2357164889 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336584330000 ps |
| CPU time | 898.42 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:53:42 PM PDT 24 |
| Peak memory | 159132 kb |
| Host | smart-909592e9-c435-4abe-8eed-94d0fd6364ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2357164889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2357164889 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3790850930 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337005090000 ps |
| CPU time | 886.42 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:53:25 PM PDT 24 |
| Peak memory | 159052 kb |
| Host | smart-72e83885-8eb9-4ebb-bc4e-7dbc8dd0916b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3790850930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3790850930 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1721729581 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336317270000 ps |
| CPU time | 682.59 seconds |
| Started | Mar 12 12:23:47 PM PDT 24 |
| Finished | Mar 12 12:51:43 PM PDT 24 |
| Peak memory | 159492 kb |
| Host | smart-1de4dfe3-1299-4beb-83b8-2654e999ce29 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1721729581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1721729581 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3291831983 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 337088990000 ps |
| CPU time | 879.17 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:53:16 PM PDT 24 |
| Peak memory | 160132 kb |
| Host | smart-0dccd249-784b-4f77-8060-478be6029645 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3291831983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3291831983 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3677904962 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 337059670000 ps |
| CPU time | 867.78 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:52:48 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-57946052-67c1-41d3-beb7-301ac1f2ca90 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3677904962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3677904962 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2023820868 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 337167550000 ps |
| CPU time | 1077.79 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 01:00:19 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-a5758e86-c255-44ea-8e64-8926f956c05e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2023820868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2023820868 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.459323341 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 337128090000 ps |
| CPU time | 674.25 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:55:24 PM PDT 24 |
| Peak memory | 160464 kb |
| Host | smart-dc216f55-647a-4aaf-864b-f2949eb9aa2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=459323341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.459323341 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3917047817 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336423970000 ps |
| CPU time | 1012.17 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:58:54 PM PDT 24 |
| Peak memory | 160060 kb |
| Host | smart-45a6d136-1020-4d32-a1cf-2c9f2b27ee80 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3917047817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3917047817 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2255888271 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336571510000 ps |
| CPU time | 1045.77 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 01:00:19 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-c50abb00-0555-44db-8140-5515b55255af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2255888271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2255888271 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1752611597 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336532930000 ps |
| CPU time | 867.38 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:52:47 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-9675a740-d213-4901-acb8-e2cb6f30bd13 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1752611597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1752611597 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3586780130 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336687690000 ps |
| CPU time | 1055.93 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 01:00:27 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-e9d17926-e0e4-4a4d-8e24-a823eabce8a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3586780130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3586780130 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3044668719 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336758030000 ps |
| CPU time | 793.64 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:49:38 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-f5933b6f-3afd-43bb-8c39-e8bcd9c4e8c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3044668719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3044668719 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3093955673 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336706270000 ps |
| CPU time | 1010.65 seconds |
| Started | Mar 12 12:16:36 PM PDT 24 |
| Finished | Mar 12 12:59:52 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-c2620d74-0bf7-45c0-996e-7301f5f8955b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3093955673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3093955673 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.90279577 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336339470000 ps |
| CPU time | 1031.31 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:59:00 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-58199fd7-9401-4609-ae41-bf6981e1cf82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=90279577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.90279577 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1471570018 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336395570000 ps |
| CPU time | 1078.33 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 01:00:16 PM PDT 24 |
| Peak memory | 160632 kb |
| Host | smart-450e5d0b-196b-4d56-9c80-4d2136b8db97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1471570018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1471570018 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3853937803 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 337035630000 ps |
| CPU time | 1032.06 seconds |
| Started | Mar 12 12:16:37 PM PDT 24 |
| Finished | Mar 12 12:59:52 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-1a8feb3b-00a2-4bf9-b3c7-9f08cc1ca43e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3853937803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3853937803 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1307739239 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336386510000 ps |
| CPU time | 1045.36 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 12:59:15 PM PDT 24 |
| Peak memory | 159160 kb |
| Host | smart-1b8a1eed-5377-4902-aed1-af9b151958a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1307739239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1307739239 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1688185084 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336790810000 ps |
| CPU time | 877.08 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:53:04 PM PDT 24 |
| Peak memory | 159528 kb |
| Host | smart-9b54022c-1990-4b8c-805f-8244007467e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1688185084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1688185084 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1905423410 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336656490000 ps |
| CPU time | 1061.15 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 01:00:20 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-98c66300-cae6-43a6-a1b0-76b9250af575 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1905423410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1905423410 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1169573973 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 337068770000 ps |
| CPU time | 847.6 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:51:21 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-ee0b3794-0046-489b-8698-2c5db3e6fbe2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1169573973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1169573973 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.67104774 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336806570000 ps |
| CPU time | 854.53 seconds |
| Started | Mar 12 12:16:28 PM PDT 24 |
| Finished | Mar 12 12:50:53 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-0950a8f0-2b67-4a4c-bede-72c66400de2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=67104774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.67104774 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.454274752 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336331750000 ps |
| CPU time | 973.17 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:57:28 PM PDT 24 |
| Peak memory | 160232 kb |
| Host | smart-96438561-8645-450b-8c7f-12568fb9acc3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=454274752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.454274752 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3089385985 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 337130130000 ps |
| CPU time | 1011.96 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:58:51 PM PDT 24 |
| Peak memory | 160260 kb |
| Host | smart-cc08e556-b5e6-43ac-b790-6616acfd9aee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3089385985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3089385985 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.827255871 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336389030000 ps |
| CPU time | 1076.36 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 01:00:16 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-51e78890-4f61-4701-8e41-45b5b62b957a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=827255871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.827255871 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3451297385 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336580110000 ps |
| CPU time | 846.63 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:51:20 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-c7be6a9a-7712-4628-af43-2fbb098bc5b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3451297385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3451297385 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.518205472 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336760290000 ps |
| CPU time | 813.53 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:50:18 PM PDT 24 |
| Peak memory | 160192 kb |
| Host | smart-0e2197e6-ed63-4c86-9956-ba08c8c23c67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=518205472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.518205472 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2101293946 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336406670000 ps |
| CPU time | 859.89 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:51:45 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-960c48e8-d402-4a4e-be99-68d79e34bf32 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2101293946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2101293946 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.865341814 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336686210000 ps |
| CPU time | 857.35 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:52:49 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-ecf4ff6e-d29d-415d-8a75-446cacdc8a49 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=865341814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.865341814 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2655228661 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 336963210000 ps |
| CPU time | 1041.33 seconds |
| Started | Mar 12 12:16:37 PM PDT 24 |
| Finished | Mar 12 12:59:55 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-9c81864a-3b2e-4a99-bf4e-e03b5787fb72 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2655228661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2655228661 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4255663335 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 337026150000 ps |
| CPU time | 790.33 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:49:35 PM PDT 24 |
| Peak memory | 160220 kb |
| Host | smart-15594483-ed1c-4c31-baaa-27ed08be2b26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4255663335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4255663335 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1814035453 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 336951210000 ps |
| CPU time | 602.03 seconds |
| Started | Mar 12 12:16:31 PM PDT 24 |
| Finished | Mar 12 12:41:50 PM PDT 24 |
| Peak memory | 160952 kb |
| Host | smart-e66e3899-279e-41c3-8627-65d9ef9949a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1814035453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1814035453 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3031016131 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336584290000 ps |
| CPU time | 1069.67 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 01:00:34 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-da6d0e7f-2853-4ec8-853b-75f59c544a46 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3031016131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3031016131 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2042072404 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336466290000 ps |
| CPU time | 1018.81 seconds |
| Started | Mar 12 12:16:37 PM PDT 24 |
| Finished | Mar 12 12:59:59 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-65210bc2-6698-418f-93ab-12d5202073f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2042072404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2042072404 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4021409608 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336428210000 ps |
| CPU time | 1009.25 seconds |
| Started | Mar 12 12:16:37 PM PDT 24 |
| Finished | Mar 12 01:00:00 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-ac332532-e9de-4b94-b248-4e383979157c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4021409608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.4021409608 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2868725914 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336541210000 ps |
| CPU time | 1007.25 seconds |
| Started | Mar 12 12:16:36 PM PDT 24 |
| Finished | Mar 12 12:59:48 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-3b206481-eb78-4d32-a3f7-093c4389f0af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2868725914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2868725914 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3577020697 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336576010000 ps |
| CPU time | 1016.93 seconds |
| Started | Mar 12 12:16:36 PM PDT 24 |
| Finished | Mar 12 01:00:01 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-f687ec1b-29e4-4ee8-97a5-9f897503a91a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3577020697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3577020697 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.708694903 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336387250000 ps |
| CPU time | 791.2 seconds |
| Started | Mar 12 12:16:38 PM PDT 24 |
| Finished | Mar 12 12:49:08 PM PDT 24 |
| Peak memory | 160192 kb |
| Host | smart-43f18d0a-8c40-437e-922c-3ae49c379074 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=708694903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.708694903 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2609490974 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336639830000 ps |
| CPU time | 852.74 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:52:29 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-f3c41898-0e36-43a0-8ae9-bb7a7495a83d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2609490974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2609490974 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3660441312 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336659710000 ps |
| CPU time | 1008.77 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:58:47 PM PDT 24 |
| Peak memory | 160080 kb |
| Host | smart-52afce79-997d-4175-a662-1ab767799894 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3660441312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3660441312 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1756076314 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 337000310000 ps |
| CPU time | 602.07 seconds |
| Started | Mar 12 12:16:31 PM PDT 24 |
| Finished | Mar 12 12:41:54 PM PDT 24 |
| Peak memory | 160968 kb |
| Host | smart-c029d940-e7b7-478c-9e5d-0baad9f9c60b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1756076314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1756076314 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2970736043 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337073870000 ps |
| CPU time | 1011.93 seconds |
| Started | Mar 12 12:16:37 PM PDT 24 |
| Finished | Mar 12 12:59:58 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-78b92937-b2e6-4f17-917f-5158ea704734 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2970736043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2970736043 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.971120397 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336688010000 ps |
| CPU time | 995.39 seconds |
| Started | Mar 12 12:16:36 PM PDT 24 |
| Finished | Mar 12 12:59:53 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-1a590029-8f4e-47dd-ab35-eb0bbc2ef0ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=971120397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.971120397 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.736256980 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336955790000 ps |
| CPU time | 861.21 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:51:47 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-572022b1-9f0d-4252-8fb9-8680ed52e1cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=736256980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.736256980 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2725594665 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336835990000 ps |
| CPU time | 886.12 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:53:35 PM PDT 24 |
| Peak memory | 159108 kb |
| Host | smart-9100cf6b-ee32-4f19-a161-84ee02f14e9b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2725594665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2725594665 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1365072345 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336983030000 ps |
| CPU time | 666.81 seconds |
| Started | Mar 12 12:22:17 PM PDT 24 |
| Finished | Mar 12 12:49:27 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-cb6b4a50-98d8-4328-b101-234492e3aed5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1365072345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1365072345 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.566698880 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336455170000 ps |
| CPU time | 1051.73 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 12:59:36 PM PDT 24 |
| Peak memory | 159176 kb |
| Host | smart-b58679f3-0301-4799-951b-0bcad2199196 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=566698880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.566698880 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3303764 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336771070000 ps |
| CPU time | 1068.56 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 01:00:27 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-d201e6c2-dbb7-4b9e-9ff9-b9b7a9327ca8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3303764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3303764 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.250208359 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336699250000 ps |
| CPU time | 876.74 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:52:39 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-3badeb78-05fc-4b18-8585-5fbae16f9b74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=250208359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.250208359 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3175354119 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336994630000 ps |
| CPU time | 620.5 seconds |
| Started | Mar 12 12:25:07 PM PDT 24 |
| Finished | Mar 12 12:50:40 PM PDT 24 |
| Peak memory | 160360 kb |
| Host | smart-efdc2a7a-5bb8-4230-a1f1-2e6a7ecdef64 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3175354119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3175354119 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1157641252 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336860350000 ps |
| CPU time | 872.94 seconds |
| Started | Mar 12 12:16:28 PM PDT 24 |
| Finished | Mar 12 12:51:47 PM PDT 24 |
| Peak memory | 160600 kb |
| Host | smart-9bf0d867-858c-414b-ad6b-723282fafc37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1157641252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1157641252 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1168321383 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336502570000 ps |
| CPU time | 824.32 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 12:50:38 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-0c078b64-cbb7-4f2b-b13a-5bd545adfd66 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1168321383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1168321383 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1601906347 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336526210000 ps |
| CPU time | 875.18 seconds |
| Started | Mar 12 12:16:28 PM PDT 24 |
| Finished | Mar 12 12:51:58 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-da2d39da-129e-46d1-80ff-2b0cc7b779f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1601906347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1601906347 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3410179792 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336398210000 ps |
| CPU time | 806.23 seconds |
| Started | Mar 12 12:16:38 PM PDT 24 |
| Finished | Mar 12 12:50:15 PM PDT 24 |
| Peak memory | 160604 kb |
| Host | smart-6e1d6f72-e4a2-4e1d-aedd-80091522ade7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3410179792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3410179792 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1844429644 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336506130000 ps |
| CPU time | 1049.01 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 01:00:14 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-9ac97a00-e62b-41c3-a967-1131ee5e6655 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1844429644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1844429644 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4181422536 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1348390000 ps |
| CPU time | 4.17 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:16:48 PM PDT 24 |
| Peak memory | 164328 kb |
| Host | smart-32305e37-df5f-4141-bec8-e5af4e510c31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4181422536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4181422536 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.537157725 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1532450000 ps |
| CPU time | 4.67 seconds |
| Started | Mar 12 12:16:37 PM PDT 24 |
| Finished | Mar 12 12:16:48 PM PDT 24 |
| Peak memory | 163704 kb |
| Host | smart-5a7d6c51-e965-4aba-85ef-9d749b2f62a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=537157725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.537157725 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.601563210 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1618810000 ps |
| CPU time | 6.44 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:16:57 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-d01a337e-7b28-40b1-a8cd-fde18c704e01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=601563210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.601563210 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4172955366 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1532310000 ps |
| CPU time | 4.17 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:16:48 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-af394834-1894-4236-90c2-06e0b4dece75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4172955366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4172955366 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1451242781 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1372370000 ps |
| CPU time | 3.42 seconds |
| Started | Mar 12 12:25:03 PM PDT 24 |
| Finished | Mar 12 12:25:11 PM PDT 24 |
| Peak memory | 164256 kb |
| Host | smart-d8cb88c1-9850-4afa-bd14-c7fac5092e09 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1451242781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1451242781 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1594987687 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1662610000 ps |
| CPU time | 4.89 seconds |
| Started | Mar 12 12:25:05 PM PDT 24 |
| Finished | Mar 12 12:25:17 PM PDT 24 |
| Peak memory | 162452 kb |
| Host | smart-436b3312-c8f8-4265-8869-e4eb8f05893e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1594987687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1594987687 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1474199154 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1218330000 ps |
| CPU time | 4.45 seconds |
| Started | Mar 12 12:30:39 PM PDT 24 |
| Finished | Mar 12 12:30:49 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-05243a1f-94c8-4216-b93c-63fed459f292 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1474199154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1474199154 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.836407223 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1333110000 ps |
| CPU time | 4.64 seconds |
| Started | Mar 12 12:25:05 PM PDT 24 |
| Finished | Mar 12 12:25:16 PM PDT 24 |
| Peak memory | 163056 kb |
| Host | smart-42ed3e13-78e1-4259-ac16-df5e2fbc0b86 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=836407223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.836407223 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2277080440 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1390290000 ps |
| CPU time | 3.95 seconds |
| Started | Mar 12 12:25:15 PM PDT 24 |
| Finished | Mar 12 12:25:24 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-54fb8eb6-eea4-414d-9ae8-455ad208e414 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2277080440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2277080440 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.874983023 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1241770000 ps |
| CPU time | 3.37 seconds |
| Started | Mar 12 12:25:02 PM PDT 24 |
| Finished | Mar 12 12:25:10 PM PDT 24 |
| Peak memory | 164200 kb |
| Host | smart-55bc0307-e052-4727-b643-0f5fbaee41c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=874983023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.874983023 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1343481251 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1500710000 ps |
| CPU time | 5.78 seconds |
| Started | Mar 12 12:20:23 PM PDT 24 |
| Finished | Mar 12 12:20:36 PM PDT 24 |
| Peak memory | 164548 kb |
| Host | smart-5fe18179-3a58-43b3-a45a-fdea780fe1c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1343481251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1343481251 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.407541315 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1509590000 ps |
| CPU time | 6.12 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:16:56 PM PDT 24 |
| Peak memory | 164700 kb |
| Host | smart-b121ba4c-03d1-48ee-8f2e-3896c39db559 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=407541315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.407541315 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2703093574 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1431450000 ps |
| CPU time | 3.13 seconds |
| Started | Mar 12 12:24:49 PM PDT 24 |
| Finished | Mar 12 12:24:56 PM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-1832dc9e-6590-4ba6-a2ce-e40a5ee64ea6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2703093574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2703093574 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2600113 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1379210000 ps |
| CPU time | 3.13 seconds |
| Started | Mar 12 12:27:21 PM PDT 24 |
| Finished | Mar 12 12:27:28 PM PDT 24 |
| Peak memory | 164380 kb |
| Host | smart-d2526d08-6cb1-46e9-8356-2b40b0a03f25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2600113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2600113 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2611148300 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1366930000 ps |
| CPU time | 3.41 seconds |
| Started | Mar 12 12:25:01 PM PDT 24 |
| Finished | Mar 12 12:25:08 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-eaddbe78-8d0e-4449-9324-7d2fcdd4bf37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2611148300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2611148300 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2242537983 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1444690000 ps |
| CPU time | 5.34 seconds |
| Started | Mar 12 12:22:52 PM PDT 24 |
| Finished | Mar 12 12:23:04 PM PDT 24 |
| Peak memory | 161448 kb |
| Host | smart-dfdf53ec-885d-4d44-a6ee-6d2a9a1e732a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2242537983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2242537983 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1439643555 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1280130000 ps |
| CPU time | 4.53 seconds |
| Started | Mar 12 12:18:06 PM PDT 24 |
| Finished | Mar 12 12:18:17 PM PDT 24 |
| Peak memory | 164544 kb |
| Host | smart-7a1be81a-4aa4-4052-96b1-0912f7fec12f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1439643555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1439643555 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3143855437 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1288550000 ps |
| CPU time | 4.82 seconds |
| Started | Mar 12 12:26:17 PM PDT 24 |
| Finished | Mar 12 12:26:27 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-acdf2a25-770f-4773-ba6a-78d60e6d6f31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3143855437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3143855437 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.228740584 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1388190000 ps |
| CPU time | 4.38 seconds |
| Started | Mar 12 12:18:02 PM PDT 24 |
| Finished | Mar 12 12:18:12 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-29adae8a-4c90-4d28-bf37-f5952e4132e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=228740584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.228740584 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2504602696 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1527510000 ps |
| CPU time | 4.5 seconds |
| Started | Mar 12 12:23:44 PM PDT 24 |
| Finished | Mar 12 12:23:54 PM PDT 24 |
| Peak memory | 164244 kb |
| Host | smart-ce92e01c-24c9-4af9-b818-64e296236c15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2504602696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2504602696 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3276473910 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1585470000 ps |
| CPU time | 3.65 seconds |
| Started | Mar 12 12:22:26 PM PDT 24 |
| Finished | Mar 12 12:22:34 PM PDT 24 |
| Peak memory | 166012 kb |
| Host | smart-9dfb4726-a26a-4a82-b49d-30454ef9c6b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3276473910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3276473910 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2456828751 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1374750000 ps |
| CPU time | 4.29 seconds |
| Started | Mar 12 12:23:43 PM PDT 24 |
| Finished | Mar 12 12:23:53 PM PDT 24 |
| Peak memory | 163972 kb |
| Host | smart-ed4d20c5-3acd-40e8-8b12-88a03d81e609 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2456828751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2456828751 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2846327082 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1543910000 ps |
| CPU time | 4.45 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 12:16:50 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-f62132d1-92d6-4688-9ae4-07bb4bcd2074 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2846327082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2846327082 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1500981817 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1344550000 ps |
| CPU time | 4.76 seconds |
| Started | Mar 12 12:22:52 PM PDT 24 |
| Finished | Mar 12 12:23:03 PM PDT 24 |
| Peak memory | 162864 kb |
| Host | smart-464e060e-b4f5-4aff-9769-eb9f065f4334 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1500981817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1500981817 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3182155193 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1602950000 ps |
| CPU time | 5.68 seconds |
| Started | Mar 12 12:22:52 PM PDT 24 |
| Finished | Mar 12 12:23:05 PM PDT 24 |
| Peak memory | 162428 kb |
| Host | smart-62dda155-ff27-4bcb-9888-7e807636b4df |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3182155193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3182155193 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3449808138 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1512250000 ps |
| CPU time | 4.01 seconds |
| Started | Mar 12 12:25:54 PM PDT 24 |
| Finished | Mar 12 12:26:03 PM PDT 24 |
| Peak memory | 164288 kb |
| Host | smart-93f042e8-a3aa-446f-bdf4-a90773929f21 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3449808138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3449808138 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1433153443 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1499970000 ps |
| CPU time | 3.21 seconds |
| Started | Mar 12 12:24:07 PM PDT 24 |
| Finished | Mar 12 12:24:15 PM PDT 24 |
| Peak memory | 164328 kb |
| Host | smart-9268f83e-b7f1-44f4-8ab9-16f6ccf2623f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1433153443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1433153443 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2437336205 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1140370000 ps |
| CPU time | 2.81 seconds |
| Started | Mar 12 12:24:14 PM PDT 24 |
| Finished | Mar 12 12:24:21 PM PDT 24 |
| Peak memory | 164308 kb |
| Host | smart-b19ee838-1eeb-4f36-aee1-dda5bf72d7f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2437336205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2437336205 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1104072598 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1278710000 ps |
| CPU time | 3.89 seconds |
| Started | Mar 12 12:24:39 PM PDT 24 |
| Finished | Mar 12 12:24:48 PM PDT 24 |
| Peak memory | 163232 kb |
| Host | smart-37f1cb02-c7c6-4338-a4d8-f2fc8b435b50 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1104072598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1104072598 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1424434893 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1580190000 ps |
| CPU time | 3.88 seconds |
| Started | Mar 12 12:24:33 PM PDT 24 |
| Finished | Mar 12 12:24:42 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-48ff80ac-09ac-442c-bcf1-8d0cb441ce9c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1424434893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1424434893 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1319551388 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1528830000 ps |
| CPU time | 4.75 seconds |
| Started | Mar 12 12:24:39 PM PDT 24 |
| Finished | Mar 12 12:24:50 PM PDT 24 |
| Peak memory | 162780 kb |
| Host | smart-b7a938ca-ccfb-4be7-9d80-ed74309b7154 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1319551388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1319551388 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2999505106 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1424130000 ps |
| CPU time | 3.85 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:27:48 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-de130cfe-e686-4b2e-80de-f66d11a7340d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2999505106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2999505106 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1790553899 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1469510000 ps |
| CPU time | 4.46 seconds |
| Started | Mar 12 12:27:41 PM PDT 24 |
| Finished | Mar 12 12:27:51 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-02834593-860e-4ea1-afaa-cb2abee71509 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1790553899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1790553899 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.33564396 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1578470000 ps |
| CPU time | 5.49 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:16:55 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-7c84c234-3841-4057-90c2-ed80c635a601 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=33564396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.33564396 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1187181795 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1427210000 ps |
| CPU time | 3.57 seconds |
| Started | Mar 12 12:24:29 PM PDT 24 |
| Finished | Mar 12 12:24:36 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-8a520dc0-ea2d-4c9b-92f9-1cbb5aea06e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1187181795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1187181795 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1551587059 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1518210000 ps |
| CPU time | 4.61 seconds |
| Started | Mar 12 12:24:39 PM PDT 24 |
| Finished | Mar 12 12:24:50 PM PDT 24 |
| Peak memory | 162844 kb |
| Host | smart-17e61d60-addc-48eb-977f-b702f8b6f16e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1551587059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1551587059 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1810142232 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1523330000 ps |
| CPU time | 2.92 seconds |
| Started | Mar 12 12:27:23 PM PDT 24 |
| Finished | Mar 12 12:27:30 PM PDT 24 |
| Peak memory | 164036 kb |
| Host | smart-734bc194-6c81-4b48-a72a-6ef4a05da664 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1810142232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1810142232 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.288038463 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1460390000 ps |
| CPU time | 4.11 seconds |
| Started | Mar 12 12:23:32 PM PDT 24 |
| Finished | Mar 12 12:23:42 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-285b9f5b-2003-423b-b301-86341f1f381d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=288038463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.288038463 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2346263867 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1219370000 ps |
| CPU time | 4.77 seconds |
| Started | Mar 12 12:23:26 PM PDT 24 |
| Finished | Mar 12 12:23:37 PM PDT 24 |
| Peak memory | 163560 kb |
| Host | smart-01cd2aae-9e91-4170-af61-e837bd2241d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2346263867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2346263867 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2649128976 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1380130000 ps |
| CPU time | 5.5 seconds |
| Started | Mar 12 12:17:31 PM PDT 24 |
| Finished | Mar 12 12:17:43 PM PDT 24 |
| Peak memory | 164548 kb |
| Host | smart-30c140fa-be7e-47dd-b0ed-a00b52b33ff6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2649128976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2649128976 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2984708963 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1439770000 ps |
| CPU time | 4.41 seconds |
| Started | Mar 12 12:23:16 PM PDT 24 |
| Finished | Mar 12 12:23:26 PM PDT 24 |
| Peak memory | 163648 kb |
| Host | smart-e6bd0b33-6d5d-4bdc-a5cb-90ca461853d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2984708963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2984708963 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3835262418 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1577910000 ps |
| CPU time | 4.01 seconds |
| Started | Mar 12 12:25:07 PM PDT 24 |
| Finished | Mar 12 12:25:17 PM PDT 24 |
| Peak memory | 164296 kb |
| Host | smart-81c1aeb0-ecbc-47ae-a038-c85ecebdde40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3835262418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3835262418 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1479998447 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1540130000 ps |
| CPU time | 4.76 seconds |
| Started | Mar 12 12:23:16 PM PDT 24 |
| Finished | Mar 12 12:23:27 PM PDT 24 |
| Peak memory | 162664 kb |
| Host | smart-7be4ce4d-d840-4425-a9d1-c7bcd5cd7146 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1479998447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1479998447 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4132314062 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1580390000 ps |
| CPU time | 3.88 seconds |
| Started | Mar 12 12:22:35 PM PDT 24 |
| Finished | Mar 12 12:22:44 PM PDT 24 |
| Peak memory | 163680 kb |
| Host | smart-0b21077b-4208-421f-bf9e-c85d56b29164 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4132314062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4132314062 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3829778873 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1338510000 ps |
| CPU time | 3.24 seconds |
| Started | Mar 12 12:16:31 PM PDT 24 |
| Finished | Mar 12 12:16:39 PM PDT 24 |
| Peak memory | 166640 kb |
| Host | smart-bca1255f-81d9-4830-a2ec-f93633d0e6b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3829778873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3829778873 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4110224285 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1418770000 ps |
| CPU time | 3.42 seconds |
| Started | Mar 12 12:16:31 PM PDT 24 |
| Finished | Mar 12 12:16:39 PM PDT 24 |
| Peak memory | 166640 kb |
| Host | smart-c037894e-25e9-4808-a837-e1e7257e4757 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4110224285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4110224285 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2299154058 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1365970000 ps |
| CPU time | 4.76 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:27:50 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-30d1c0cd-40d8-45e2-a7e5-d1748397328b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2299154058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2299154058 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.664356355 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1207330000 ps |
| CPU time | 3.87 seconds |
| Started | Mar 12 12:27:39 PM PDT 24 |
| Finished | Mar 12 12:27:48 PM PDT 24 |
| Peak memory | 164464 kb |
| Host | smart-6b70ceef-6cde-454d-a8c7-baaa36730a1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=664356355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.664356355 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1732777233 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1506470000 ps |
| CPU time | 4.98 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:16:54 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-c1e0509a-8c6d-4083-9cf4-84cff193a5bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1732777233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1732777233 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3100118416 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1460410000 ps |
| CPU time | 4.39 seconds |
| Started | Mar 12 12:23:17 PM PDT 24 |
| Finished | Mar 12 12:23:26 PM PDT 24 |
| Peak memory | 164256 kb |
| Host | smart-5d60607d-ea40-421f-9b5d-938bc4bdc60c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3100118416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3100118416 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2467690903 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1518150000 ps |
| CPU time | 6.08 seconds |
| Started | Mar 12 12:21:10 PM PDT 24 |
| Finished | Mar 12 12:21:23 PM PDT 24 |
| Peak memory | 164548 kb |
| Host | smart-d2444305-cafe-4f83-b614-1f6f5b7e479a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2467690903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2467690903 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4016025196 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1451090000 ps |
| CPU time | 4.37 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:16:48 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-4367a2d3-ada5-4ea9-b79f-accbc51f4eaa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4016025196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.4016025196 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3035795515 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1246910000 ps |
| CPU time | 3.9 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:16:48 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-599a59e5-287f-4561-8aa9-2f7db5462959 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3035795515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3035795515 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.742329238 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1596450000 ps |
| CPU time | 5.29 seconds |
| Started | Mar 12 12:20:22 PM PDT 24 |
| Finished | Mar 12 12:20:34 PM PDT 24 |
| Peak memory | 164580 kb |
| Host | smart-4eca9dcb-2925-494b-8d6a-a3500cf7b73e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=742329238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.742329238 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3724357331 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1471470000 ps |
| CPU time | 4.84 seconds |
| Started | Mar 12 12:25:05 PM PDT 24 |
| Finished | Mar 12 12:25:16 PM PDT 24 |
| Peak memory | 162092 kb |
| Host | smart-b159a479-8965-4fa9-b916-52793d354c11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3724357331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3724357331 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3633800229 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1447750000 ps |
| CPU time | 4.62 seconds |
| Started | Mar 12 12:17:26 PM PDT 24 |
| Finished | Mar 12 12:17:36 PM PDT 24 |
| Peak memory | 164544 kb |
| Host | smart-98666beb-15bb-4a9b-bdac-b00350ff7804 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3633800229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3633800229 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3916744929 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1206630000 ps |
| CPU time | 4.2 seconds |
| Started | Mar 12 12:17:26 PM PDT 24 |
| Finished | Mar 12 12:17:35 PM PDT 24 |
| Peak memory | 164544 kb |
| Host | smart-c4796c6b-72a9-4027-848e-18fc31fdcab5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3916744929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3916744929 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2557130310 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1450170000 ps |
| CPU time | 4.84 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:27:50 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-737a3dba-6c5e-4c3b-9c0a-3995c6427fcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2557130310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2557130310 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4072766605 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1463230000 ps |
| CPU time | 3.41 seconds |
| Started | Mar 12 12:23:42 PM PDT 24 |
| Finished | Mar 12 12:23:50 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-b23e3c04-ffad-4a60-9115-6af4f2d1ff2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4072766605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4072766605 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.33063739 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1500030000 ps |
| CPU time | 4.57 seconds |
| Started | Mar 12 12:24:54 PM PDT 24 |
| Finished | Mar 12 12:25:04 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-2a1e2b35-a910-4b65-bf9c-8eb7e920e0ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=33063739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.33063739 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1203909763 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1497010000 ps |
| CPU time | 4.92 seconds |
| Started | Mar 12 12:23:16 PM PDT 24 |
| Finished | Mar 12 12:23:27 PM PDT 24 |
| Peak memory | 162860 kb |
| Host | smart-36f90cf5-b6c3-4ba6-961a-5dd0bfe2349d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1203909763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1203909763 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.242201126 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1567630000 ps |
| CPU time | 4.5 seconds |
| Started | Mar 12 12:24:54 PM PDT 24 |
| Finished | Mar 12 12:25:04 PM PDT 24 |
| Peak memory | 164256 kb |
| Host | smart-25a8f1a0-141b-4f96-b362-f9901c4c2995 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=242201126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.242201126 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3540133159 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1396990000 ps |
| CPU time | 3.85 seconds |
| Started | Mar 12 12:24:52 PM PDT 24 |
| Finished | Mar 12 12:25:01 PM PDT 24 |
| Peak memory | 163908 kb |
| Host | smart-83859fbb-3afe-4e97-bf5a-d37f8c241a6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3540133159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3540133159 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.632940390 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1405170000 ps |
| CPU time | 4.17 seconds |
| Started | Mar 12 12:23:32 PM PDT 24 |
| Finished | Mar 12 12:23:43 PM PDT 24 |
| Peak memory | 164980 kb |
| Host | smart-e8bead43-638d-4162-8ea5-fda279a80b55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=632940390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.632940390 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4108101288 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1260450000 ps |
| CPU time | 4.5 seconds |
| Started | Mar 12 12:23:44 PM PDT 24 |
| Finished | Mar 12 12:23:53 PM PDT 24 |
| Peak memory | 164244 kb |
| Host | smart-5fb55b66-f056-466d-bd93-255f20425e0e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4108101288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4108101288 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2479745084 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1372170000 ps |
| CPU time | 3.18 seconds |
| Started | Mar 12 12:25:58 PM PDT 24 |
| Finished | Mar 12 12:26:05 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-b292da26-d484-484c-be20-4953e9ff7441 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2479745084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2479745084 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.780303652 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1407110000 ps |
| CPU time | 3.24 seconds |
| Started | Mar 12 12:25:00 PM PDT 24 |
| Finished | Mar 12 12:25:07 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-1ddcb8db-4a63-458a-9d3c-159ee80de0ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=780303652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.780303652 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4216968319 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1529870000 ps |
| CPU time | 3.56 seconds |
| Started | Mar 12 12:22:26 PM PDT 24 |
| Finished | Mar 12 12:22:34 PM PDT 24 |
| Peak memory | 166012 kb |
| Host | smart-447683d9-a8f4-4719-bf6a-ef229633912d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4216968319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4216968319 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.768036071 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1426750000 ps |
| CPU time | 3.25 seconds |
| Started | Mar 12 12:22:15 PM PDT 24 |
| Finished | Mar 12 12:22:22 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-b7ecac85-b07d-4da9-91cd-328dccd365d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=768036071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.768036071 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3653399594 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1550070000 ps |
| CPU time | 4.23 seconds |
| Started | Mar 12 12:23:48 PM PDT 24 |
| Finished | Mar 12 12:23:58 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-2c34efab-c650-4f39-8a60-dcd65fb9f121 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3653399594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3653399594 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1721183514 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1590810000 ps |
| CPU time | 4.2 seconds |
| Started | Mar 12 12:25:53 PM PDT 24 |
| Finished | Mar 12 12:26:02 PM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-480e87d4-7165-4393-8bf1-17d27922762e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1721183514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1721183514 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.345879767 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1401950000 ps |
| CPU time | 4.28 seconds |
| Started | Mar 12 12:16:40 PM PDT 24 |
| Finished | Mar 12 12:16:50 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-b5569913-036e-4647-90ce-53781b3e229f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=345879767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.345879767 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2698659506 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1545750000 ps |
| CPU time | 5.65 seconds |
| Started | Mar 12 12:22:52 PM PDT 24 |
| Finished | Mar 12 12:23:05 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-d7eed9da-5c81-4833-8dfe-adb68f0568fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2698659506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2698659506 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3038784560 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1311870000 ps |
| CPU time | 3.21 seconds |
| Started | Mar 12 12:24:14 PM PDT 24 |
| Finished | Mar 12 12:24:22 PM PDT 24 |
| Peak memory | 164312 kb |
| Host | smart-82eaff3c-f3cc-4430-b76e-51cb16bce38f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3038784560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3038784560 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3164201275 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1609670000 ps |
| CPU time | 4.01 seconds |
| Started | Mar 12 12:24:21 PM PDT 24 |
| Finished | Mar 12 12:24:30 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-58c335bc-a31f-4797-b1f0-9c3494155780 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3164201275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3164201275 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3598825588 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1550490000 ps |
| CPU time | 4.38 seconds |
| Started | Mar 12 12:26:02 PM PDT 24 |
| Finished | Mar 12 12:26:12 PM PDT 24 |
| Peak memory | 164144 kb |
| Host | smart-ca908bc1-c26b-4053-865c-571ca545be9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3598825588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3598825588 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3965802864 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1280430000 ps |
| CPU time | 3.7 seconds |
| Started | Mar 12 12:24:35 PM PDT 24 |
| Finished | Mar 12 12:24:43 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-f58815ea-05a2-4ec0-93bf-05648f2764a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3965802864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3965802864 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2266987283 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1458490000 ps |
| CPU time | 4.54 seconds |
| Started | Mar 12 12:24:39 PM PDT 24 |
| Finished | Mar 12 12:24:49 PM PDT 24 |
| Peak memory | 162320 kb |
| Host | smart-0cfb73ba-4418-424b-bc52-cfed1b1c29a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2266987283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2266987283 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3622425937 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1527470000 ps |
| CPU time | 4.39 seconds |
| Started | Mar 12 12:27:41 PM PDT 24 |
| Finished | Mar 12 12:27:51 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-5232a268-c7a3-4855-ae51-f648d8a94901 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3622425937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3622425937 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2885672251 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1448390000 ps |
| CPU time | 3.88 seconds |
| Started | Mar 12 12:24:36 PM PDT 24 |
| Finished | Mar 12 12:24:45 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-5a53627d-49d2-44e9-a256-6c70686f2f0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2885672251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2885672251 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2105947551 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1567650000 ps |
| CPU time | 3.7 seconds |
| Started | Mar 12 12:24:33 PM PDT 24 |
| Finished | Mar 12 12:24:42 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-2d8ff78d-a34b-4c6c-8fc9-6fb52156cdd6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2105947551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2105947551 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.4194014367 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1545430000 ps |
| CPU time | 3.99 seconds |
| Started | Mar 12 12:24:20 PM PDT 24 |
| Finished | Mar 12 12:24:29 PM PDT 24 |
| Peak memory | 163404 kb |
| Host | smart-89e348a1-1b82-46da-b218-a013fd8ebf6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4194014367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.4194014367 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.178749072 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1381250000 ps |
| CPU time | 4.82 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:16:54 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-b77a27f2-8bd0-48b5-a5f9-da0d64b3ab4e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=178749072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.178749072 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1451868755 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1601170000 ps |
| CPU time | 3.87 seconds |
| Started | Mar 12 12:24:20 PM PDT 24 |
| Finished | Mar 12 12:24:29 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-04d898f0-3faf-490a-9f92-2fd6318680a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1451868755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1451868755 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1099660212 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1379910000 ps |
| CPU time | 3.96 seconds |
| Started | Mar 12 12:27:39 PM PDT 24 |
| Finished | Mar 12 12:27:48 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-83ae58c1-14fd-45a8-9b11-1c25933b6a92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1099660212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1099660212 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1193850188 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1512750000 ps |
| CPU time | 4.06 seconds |
| Started | Mar 12 12:22:27 PM PDT 24 |
| Finished | Mar 12 12:22:36 PM PDT 24 |
| Peak memory | 164168 kb |
| Host | smart-dd0548b3-2023-4c6b-8800-a395aa8bcb42 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1193850188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1193850188 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2084555800 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1553690000 ps |
| CPU time | 5.63 seconds |
| Started | Mar 12 12:23:27 PM PDT 24 |
| Finished | Mar 12 12:23:40 PM PDT 24 |
| Peak memory | 164116 kb |
| Host | smart-c8ea0d39-83ef-4ab1-9903-4518a75e48bc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2084555800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2084555800 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.75209034 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1185490000 ps |
| CPU time | 2.96 seconds |
| Started | Mar 12 12:22:35 PM PDT 24 |
| Finished | Mar 12 12:22:42 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-f92d507f-aca5-4d3c-ad49-72762d496508 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=75209034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.75209034 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1031535199 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1305890000 ps |
| CPU time | 3.32 seconds |
| Started | Mar 12 12:22:26 PM PDT 24 |
| Finished | Mar 12 12:22:34 PM PDT 24 |
| Peak memory | 163980 kb |
| Host | smart-4a64baeb-27de-4c1b-a996-9eb3f6566370 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1031535199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1031535199 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.602929774 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1326830000 ps |
| CPU time | 3.43 seconds |
| Started | Mar 12 12:22:27 PM PDT 24 |
| Finished | Mar 12 12:22:35 PM PDT 24 |
| Peak memory | 164252 kb |
| Host | smart-19c22884-d699-4893-9a1d-a69e50add5c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=602929774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.602929774 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2992540691 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1517130000 ps |
| CPU time | 4.15 seconds |
| Started | Mar 12 12:25:07 PM PDT 24 |
| Finished | Mar 12 12:25:16 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-39d39315-13e4-489a-8673-412f97ddd989 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2992540691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2992540691 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.10262848 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1317430000 ps |
| CPU time | 4.98 seconds |
| Started | Mar 12 12:23:28 PM PDT 24 |
| Finished | Mar 12 12:23:39 PM PDT 24 |
| Peak memory | 164264 kb |
| Host | smart-b40a8b4d-036a-499f-a88f-7fa56f1cea4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=10262848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.10262848 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2983749808 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1433750000 ps |
| CPU time | 3.04 seconds |
| Started | Mar 12 12:17:53 PM PDT 24 |
| Finished | Mar 12 12:18:00 PM PDT 24 |
| Peak memory | 165024 kb |
| Host | smart-4161e51f-cef7-4bc3-bc2c-f95f29a4707a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2983749808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2983749808 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1397985495 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1601390000 ps |
| CPU time | 5.39 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 12:16:53 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-b3f37f05-4744-4d2a-969e-364bb2e294ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1397985495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1397985495 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.266464293 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1274690000 ps |
| CPU time | 3.71 seconds |
| Started | Mar 12 12:16:43 PM PDT 24 |
| Finished | Mar 12 12:16:51 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-2a203d54-81e9-4daa-b24a-58679a771d5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=266464293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.266464293 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.913014626 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1525810000 ps |
| CPU time | 5.32 seconds |
| Started | Mar 12 12:16:41 PM PDT 24 |
| Finished | Mar 12 12:16:53 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-e88d1355-ed86-4e77-9142-6b62c25db1bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=913014626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.913014626 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2904219855 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1493690000 ps |
| CPU time | 5.11 seconds |
| Started | Mar 12 12:16:42 PM PDT 24 |
| Finished | Mar 12 12:16:53 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-1ed39402-6112-4a40-aecc-7b967a29d410 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2904219855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2904219855 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4275139965 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1539910000 ps |
| CPU time | 4.7 seconds |
| Started | Mar 12 12:16:39 PM PDT 24 |
| Finished | Mar 12 12:16:50 PM PDT 24 |
| Peak memory | 164328 kb |
| Host | smart-b5c25821-0a3d-47d8-bf20-a06d0769e84b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4275139965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4275139965 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |