Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2456382749
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1976020575
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1291455137

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.675434888
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2565595594
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2771474476
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.106054869
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1812817508
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.612420083
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1920278337
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1811652397
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1352797903
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2506397922
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3143347880
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.297645691
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.993359180
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.807124309
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2933236902
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1690674347
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2759861499
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3444524621
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2083629042
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3297202215
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3485774526
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3367413259
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.932824823
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3370804787
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1095732626
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1327211150
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.259295400
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.930172052
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.692924205
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1197380230
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1682054717
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3604954628
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1822071945
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1855446867
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.939657981
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.946601183
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4104256119
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3361423431
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.796247380
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3407212606
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2898407685
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3196877632
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3589009315
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3068268937
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3750120402
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2102591843
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.268569429
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.841945759
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1812270061
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2555494783
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2679525954
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1202404389
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.528146055
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.184524295
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.395522809
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.58425441
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1959100358
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.690828482
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2001395849
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1961566785
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1886418823
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3104812544
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1602923791
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.295693636
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2432206690
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.988666220
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.770102640
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1405686735
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.419368843
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2228524839
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.838430867
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.730976602
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3642730656
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1147812042
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3667519079
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4131175231
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1292193108
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.927115421
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.21315638
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1526059062
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3914187503
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3858957347
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3880668011
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2514680187
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1623408980
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2721183182
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3410526121
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1219913164
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2509430937
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.331921394
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1471109399
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2696094197
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.62570937
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3997304806
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.868828034
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1350365377
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1089812174
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2700869538
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3653918750
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3478294288
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.515942159
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4238333452
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3348850827
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3283437533
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1427926592
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2269918552
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1158069303
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1058536676
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3579384788
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3263138160
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2376988862
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1388277504
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1988240950
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1345082163
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1341768835
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3482545237
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.382319059
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2961251935
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1926811717
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.490824562
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2692138425
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1267815351
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.442498713
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3900017517
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3415178689
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3872255130
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2174837271
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3878629332
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1478864866
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2265563173
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2238940263
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1550839698
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2710904238
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3104453327
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3708483739
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3030653257
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1680008129
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3232311002
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1212965664
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1591903662
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2627598027
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4257767694
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.59257222
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1451645016
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4249156468
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2206598928
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.935050742
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3155865549
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3710768869
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1980391821
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3679326621
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.161736582
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.981001595
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2487517207
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3991935430
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1684202761
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3619262908
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1031911889
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.142359405
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3259176415
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.388094233
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1800111439
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2923819918
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2344878883
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1016860171
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3500129209
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3431868142
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1314905560
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.728485425
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2605423680
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.845740407
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2206833700
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1457684830
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2236283630
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3300245640
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2019648775
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2317829224
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1410165907
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3620007438
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.390115080
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1490286767
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1729647177
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.117969163
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3192259295
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3625552871
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.219637378
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3966803079
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3825756119
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1859049379
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3924758079
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2422999806
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1352386813
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.461932047
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.779760004
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1933049216
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2201636630
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3072426531



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2317829224 Mar 17 02:59:03 PM PDT 24 Mar 17 02:59:16 PM PDT 24 1526490000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.779760004 Mar 17 02:59:01 PM PDT 24 Mar 17 02:59:10 PM PDT 24 1569810000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1684202761 Mar 17 02:58:59 PM PDT 24 Mar 17 02:59:08 PM PDT 24 1548970000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3991935430 Mar 17 02:58:59 PM PDT 24 Mar 17 02:59:10 PM PDT 24 1407130000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3619262908 Mar 17 02:58:59 PM PDT 24 Mar 17 02:59:10 PM PDT 24 1576290000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1682054717 Mar 17 02:41:17 PM PDT 24 Mar 17 03:12:33 PM PDT 24 336653230000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.841945759 Mar 17 02:41:11 PM PDT 24 Mar 17 03:10:45 PM PDT 24 337033750000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.796247380 Mar 17 02:41:20 PM PDT 24 Mar 17 03:15:10 PM PDT 24 336400390000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.675434888 Mar 17 02:41:05 PM PDT 24 Mar 17 03:11:15 PM PDT 24 336743330000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1822071945 Mar 17 02:41:17 PM PDT 24 Mar 17 03:12:18 PM PDT 24 336767950000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.106054869 Mar 17 02:41:11 PM PDT 24 Mar 17 03:10:08 PM PDT 24 336587870000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3196877632 Mar 17 02:41:16 PM PDT 24 Mar 17 03:13:12 PM PDT 24 336888610000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.612420083 Mar 17 02:41:10 PM PDT 24 Mar 17 03:10:49 PM PDT 24 336758710000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1855446867 Mar 17 02:41:11 PM PDT 24 Mar 17 03:14:54 PM PDT 24 336556830000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.993359180 Mar 17 02:41:16 PM PDT 24 Mar 17 03:13:47 PM PDT 24 336325090000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3407212606 Mar 17 02:41:24 PM PDT 24 Mar 17 03:16:08 PM PDT 24 336420370000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1197380230 Mar 17 02:41:15 PM PDT 24 Mar 17 03:10:51 PM PDT 24 336625870000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3143347880 Mar 17 02:41:11 PM PDT 24 Mar 17 03:11:58 PM PDT 24 336409370000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1920278337 Mar 17 02:41:11 PM PDT 24 Mar 17 03:13:10 PM PDT 24 336978290000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.692924205 Mar 17 02:41:16 PM PDT 24 Mar 17 03:12:21 PM PDT 24 336401750000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2102591843 Mar 17 02:41:13 PM PDT 24 Mar 17 03:16:09 PM PDT 24 337050210000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3604954628 Mar 17 02:41:25 PM PDT 24 Mar 17 03:16:17 PM PDT 24 337000250000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.930172052 Mar 17 02:41:18 PM PDT 24 Mar 17 03:14:52 PM PDT 24 336338150000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3485774526 Mar 17 02:41:25 PM PDT 24 Mar 17 03:16:09 PM PDT 24 336850590000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3589009315 Mar 17 02:41:16 PM PDT 24 Mar 17 03:16:27 PM PDT 24 336849110000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.932824823 Mar 17 02:41:11 PM PDT 24 Mar 17 03:13:00 PM PDT 24 336721890000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1352797903 Mar 17 02:41:16 PM PDT 24 Mar 17 03:14:32 PM PDT 24 336908130000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1095732626 Mar 17 02:41:17 PM PDT 24 Mar 17 03:10:51 PM PDT 24 336514430000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3232311002 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:33 PM PDT 24 1571530000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2174837271 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:36 PM PDT 24 1610070000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3263138160 Mar 17 12:58:28 PM PDT 24 Mar 17 12:58:38 PM PDT 24 1624170000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3872255130 Mar 17 12:58:21 PM PDT 24 Mar 17 12:58:29 PM PDT 24 1141110000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2206598928 Mar 17 12:58:16 PM PDT 24 Mar 17 12:58:27 PM PDT 24 1538290000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2627598027 Mar 17 12:58:18 PM PDT 24 Mar 17 12:58:26 PM PDT 24 1251870000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2961251935 Mar 17 12:58:19 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1452950000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3104453327 Mar 17 12:58:19 PM PDT 24 Mar 17 12:58:29 PM PDT 24 1331890000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3348850827 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:27 PM PDT 24 1520470000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2710904238 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1418490000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.59257222 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:23 PM PDT 24 1304350000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1591903662 Mar 17 12:58:21 PM PDT 24 Mar 17 12:58:33 PM PDT 24 1580830000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3283437533 Mar 17 12:58:15 PM PDT 24 Mar 17 12:58:23 PM PDT 24 1372350000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3900017517 Mar 17 12:58:18 PM PDT 24 Mar 17 12:58:25 PM PDT 24 1360230000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2376988862 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1520310000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1345082163 Mar 17 12:58:19 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1568210000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1680008129 Mar 17 12:58:21 PM PDT 24 Mar 17 12:58:32 PM PDT 24 1514450000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.490824562 Mar 17 12:58:21 PM PDT 24 Mar 17 12:58:33 PM PDT 24 1429530000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1267815351 Mar 17 12:58:13 PM PDT 24 Mar 17 12:58:21 PM PDT 24 1434210000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3482545237 Mar 17 12:58:20 PM PDT 24 Mar 17 12:58:31 PM PDT 24 1543150000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2269918552 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:35 PM PDT 24 1450530000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4257767694 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:36 PM PDT 24 1401650000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1427926592 Mar 17 12:58:12 PM PDT 24 Mar 17 12:58:22 PM PDT 24 1547430000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3708483739 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:35 PM PDT 24 1551110000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3579384788 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:26 PM PDT 24 1471350000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3478294288 Mar 17 12:58:15 PM PDT 24 Mar 17 12:58:25 PM PDT 24 1273270000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.442498713 Mar 17 12:58:19 PM PDT 24 Mar 17 12:58:29 PM PDT 24 1402790000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2265563173 Mar 17 12:58:27 PM PDT 24 Mar 17 12:58:38 PM PDT 24 1566990000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1926811717 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:35 PM PDT 24 1616390000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.515942159 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1524890000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1478864866 Mar 17 12:58:23 PM PDT 24 Mar 17 12:58:32 PM PDT 24 1520790000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3030653257 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:35 PM PDT 24 1460070000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1550839698 Mar 17 12:58:20 PM PDT 24 Mar 17 12:58:33 PM PDT 24 1544030000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1158069303 Mar 17 12:58:16 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1530030000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3653918750 Mar 17 12:58:14 PM PDT 24 Mar 17 12:58:24 PM PDT 24 1454930000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4238333452 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:26 PM PDT 24 1199990000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1341768835 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:35 PM PDT 24 1453430000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3415178689 Mar 17 12:58:27 PM PDT 24 Mar 17 12:58:38 PM PDT 24 1554930000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2692138425 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:30 PM PDT 24 1538810000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.382319059 Mar 17 12:58:22 PM PDT 24 Mar 17 12:58:33 PM PDT 24 1372050000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.935050742 Mar 17 12:58:16 PM PDT 24 Mar 17 12:58:26 PM PDT 24 1198870000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1388277504 Mar 17 12:58:20 PM PDT 24 Mar 17 12:58:31 PM PDT 24 1480450000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3878629332 Mar 17 12:58:20 PM PDT 24 Mar 17 12:58:29 PM PDT 24 1506750000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1212965664 Mar 17 12:58:18 PM PDT 24 Mar 17 12:58:25 PM PDT 24 1425150000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3155865549 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1538990000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4249156468 Mar 17 12:58:15 PM PDT 24 Mar 17 12:58:22 PM PDT 24 1188450000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2238940263 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:25 PM PDT 24 1272370000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1451645016 Mar 17 12:58:13 PM PDT 24 Mar 17 12:58:23 PM PDT 24 1396790000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1988240950 Mar 17 12:58:18 PM PDT 24 Mar 17 12:58:28 PM PDT 24 1581210000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1058536676 Mar 17 12:58:21 PM PDT 24 Mar 17 12:58:32 PM PDT 24 1451270000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2456382749
Short name T12
Test name
Test status
Simulation time 1562110000 ps
CPU time 4.98 seconds
Started Mar 17 02:59:00 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 164896 kb
Host smart-0706ee17-3e0f-4d5c-9b62-11267695953e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2456382749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2456382749
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1976020575
Short name T23
Test name
Test status
Simulation time 336345370000 ps
CPU time 731.65 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 01:28:11 PM PDT 24
Peak memory 160744 kb
Host smart-348e1394-82b2-42d5-8e16-86d61de37ddd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976020575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1976020575
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1291455137
Short name T25
Test name
Test status
Simulation time 337102050000 ps
CPU time 828.36 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:14:44 PM PDT 24
Peak memory 160840 kb
Host smart-2081a717-8463-4aea-abc2-d02fb2889125
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1291455137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1291455137
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.675434888
Short name T131
Test name
Test status
Simulation time 336743330000 ps
CPU time 747.44 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 03:11:15 PM PDT 24
Peak memory 160752 kb
Host smart-9d01b11a-fde6-4716-bd78-b7417f60ca9c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=675434888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.675434888
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2565595594
Short name T120
Test name
Test status
Simulation time 336709450000 ps
CPU time 837.73 seconds
Started Mar 17 02:41:05 PM PDT 24
Finished Mar 17 03:15:34 PM PDT 24
Peak memory 160804 kb
Host smart-005a81e4-f276-4166-8881-16c76c07aa12
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2565595594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2565595594
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2771474476
Short name T111
Test name
Test status
Simulation time 336748010000 ps
CPU time 636.58 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:07:32 PM PDT 24
Peak memory 160848 kb
Host smart-ff4e3f38-4c71-482c-9bfb-d4adcca0b2ab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2771474476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2771474476
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.106054869
Short name T133
Test name
Test status
Simulation time 336587870000 ps
CPU time 710.66 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:10:08 PM PDT 24
Peak memory 160800 kb
Host smart-ca5e158a-9989-4d18-83b6-4673ba932d72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=106054869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.106054869
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1812817508
Short name T122
Test name
Test status
Simulation time 336758010000 ps
CPU time 791.76 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:13:13 PM PDT 24
Peak memory 160776 kb
Host smart-2cae1cc4-3b6c-48fb-8f1b-3430881a1290
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1812817508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1812817508
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.612420083
Short name T135
Test name
Test status
Simulation time 336758710000 ps
CPU time 715.52 seconds
Started Mar 17 02:41:10 PM PDT 24
Finished Mar 17 03:10:49 PM PDT 24
Peak memory 160808 kb
Host smart-2d8ea1df-cfa0-49a5-86f5-3c7969eb080a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=612420083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.612420083
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1920278337
Short name T141
Test name
Test status
Simulation time 336978290000 ps
CPU time 779.39 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:13:10 PM PDT 24
Peak memory 160784 kb
Host smart-ebd3bd83-2d15-4e47-bdd4-00bd1e93e660
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1920278337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1920278337
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1811652397
Short name T27
Test name
Test status
Simulation time 336720250000 ps
CPU time 789.66 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:13:59 PM PDT 24
Peak memory 160796 kb
Host smart-f1f11107-9426-462d-91b7-c965a5e8b113
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811652397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1811652397
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1352797903
Short name T149
Test name
Test status
Simulation time 336908130000 ps
CPU time 797.43 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:14:32 PM PDT 24
Peak memory 160796 kb
Host smart-2a5f4137-ac10-4205-8302-486c1cbc7a01
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1352797903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1352797903
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2506397922
Short name T118
Test name
Test status
Simulation time 336758850000 ps
CPU time 798.62 seconds
Started Mar 17 02:41:14 PM PDT 24
Finished Mar 17 03:13:46 PM PDT 24
Peak memory 160844 kb
Host smart-12780c0e-2fdb-4fb7-bbc9-0d76e01a5f6d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2506397922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2506397922
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3143347880
Short name T140
Test name
Test status
Simulation time 336409370000 ps
CPU time 764.58 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:11:58 PM PDT 24
Peak memory 160808 kb
Host smart-b2a95738-e3af-4ac1-b469-cc3d0029284f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3143347880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3143347880
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.297645691
Short name T5
Test name
Test status
Simulation time 336816050000 ps
CPU time 716.54 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:10:01 PM PDT 24
Peak memory 160800 kb
Host smart-b7191a81-99c0-4064-a7d9-f23b586d47fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=297645691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.297645691
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.993359180
Short name T137
Test name
Test status
Simulation time 336325090000 ps
CPU time 779.42 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:13:47 PM PDT 24
Peak memory 160792 kb
Host smart-6a9d6787-2e9a-4968-83ed-7d41716c5fba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=993359180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.993359180
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.807124309
Short name T4
Test name
Test status
Simulation time 336921750000 ps
CPU time 845 seconds
Started Mar 17 02:41:12 PM PDT 24
Finished Mar 17 03:15:25 PM PDT 24
Peak memory 160796 kb
Host smart-4557b12d-b294-44fc-bd54-9d35496b2d7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=807124309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.807124309
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2933236902
Short name T125
Test name
Test status
Simulation time 336760490000 ps
CPU time 751.96 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:11:44 PM PDT 24
Peak memory 160748 kb
Host smart-e0ba5abd-4d16-438f-ba5b-0bd5790c8e84
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933236902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2933236902
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1690674347
Short name T127
Test name
Test status
Simulation time 336615150000 ps
CPU time 746.78 seconds
Started Mar 17 02:41:15 PM PDT 24
Finished Mar 17 03:12:03 PM PDT 24
Peak memory 160776 kb
Host smart-9e3a0dd0-d88c-4c66-8bfe-e471fdda5115
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1690674347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1690674347
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2759861499
Short name T117
Test name
Test status
Simulation time 336659090000 ps
CPU time 746.36 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:11:51 PM PDT 24
Peak memory 160776 kb
Host smart-94200395-1938-4a4c-ba12-d16cf5c9e9c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2759861499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2759861499
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3444524621
Short name T123
Test name
Test status
Simulation time 336674130000 ps
CPU time 816.13 seconds
Started Mar 17 02:41:20 PM PDT 24
Finished Mar 17 03:15:19 PM PDT 24
Peak memory 160772 kb
Host smart-d4720973-8ce1-4ba7-93df-626e8721bc2c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3444524621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3444524621
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2083629042
Short name T26
Test name
Test status
Simulation time 336870070000 ps
CPU time 830.75 seconds
Started Mar 17 02:41:19 PM PDT 24
Finished Mar 17 03:15:44 PM PDT 24
Peak memory 160772 kb
Host smart-88a33bb6-218a-4144-bca2-b5cf47143b61
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2083629042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2083629042
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3297202215
Short name T116
Test name
Test status
Simulation time 337002690000 ps
CPU time 579.76 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:05:46 PM PDT 24
Peak memory 160744 kb
Host smart-39083793-ae11-445f-b905-5608e66bc2fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3297202215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3297202215
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3485774526
Short name T146
Test name
Test status
Simulation time 336850590000 ps
CPU time 837.45 seconds
Started Mar 17 02:41:25 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 160784 kb
Host smart-e92f5572-bff0-4cd7-9958-b41225b687e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3485774526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3485774526
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3367413259
Short name T124
Test name
Test status
Simulation time 336682230000 ps
CPU time 789.72 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:13:11 PM PDT 24
Peak memory 160796 kb
Host smart-a135462c-f469-4880-b396-adc34c408eec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3367413259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3367413259
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.932824823
Short name T148
Test name
Test status
Simulation time 336721890000 ps
CPU time 775.79 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:13:00 PM PDT 24
Peak memory 160796 kb
Host smart-3141f577-b3db-45bb-b657-7f3f354f4a05
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=932824823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.932824823
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3370804787
Short name T126
Test name
Test status
Simulation time 336969730000 ps
CPU time 734.8 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:11:07 PM PDT 24
Peak memory 160760 kb
Host smart-d6c06a1c-96e9-4d3d-898b-76bf76aef8a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3370804787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3370804787
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1095732626
Short name T150
Test name
Test status
Simulation time 336514430000 ps
CPU time 721.93 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:10:51 PM PDT 24
Peak memory 160832 kb
Host smart-2738cf9b-7d55-484b-8733-57a9ae35d8e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1095732626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1095732626
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1327211150
Short name T114
Test name
Test status
Simulation time 336391370000 ps
CPU time 735.83 seconds
Started Mar 17 02:41:15 PM PDT 24
Finished Mar 17 03:11:14 PM PDT 24
Peak memory 160812 kb
Host smart-741037fc-2fd2-434f-adab-6bb15a053d99
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1327211150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1327211150
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.259295400
Short name T113
Test name
Test status
Simulation time 336618830000 ps
CPU time 823.56 seconds
Started Mar 17 02:41:18 PM PDT 24
Finished Mar 17 03:14:52 PM PDT 24
Peak memory 160820 kb
Host smart-d431294e-9c0c-48fa-8710-50a53c743872
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=259295400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.259295400
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.930172052
Short name T145
Test name
Test status
Simulation time 336338150000 ps
CPU time 799.72 seconds
Started Mar 17 02:41:18 PM PDT 24
Finished Mar 17 03:14:52 PM PDT 24
Peak memory 160792 kb
Host smart-97c84dd3-1f50-42a2-a892-0e257d52ceb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=930172052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.930172052
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.692924205
Short name T142
Test name
Test status
Simulation time 336401750000 ps
CPU time 775.44 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:12:21 PM PDT 24
Peak memory 160808 kb
Host smart-5a635ab0-ae38-4c1e-9cdc-3ead36c174e0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=692924205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.692924205
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1197380230
Short name T139
Test name
Test status
Simulation time 336625870000 ps
CPU time 722.17 seconds
Started Mar 17 02:41:15 PM PDT 24
Finished Mar 17 03:10:51 PM PDT 24
Peak memory 160848 kb
Host smart-32a88400-2ff4-4f24-8210-89597889501c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1197380230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1197380230
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1682054717
Short name T128
Test name
Test status
Simulation time 336653230000 ps
CPU time 779.48 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:12:33 PM PDT 24
Peak memory 160796 kb
Host smart-a983bf83-1714-40f2-8073-afe7507cd7f1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1682054717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1682054717
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3604954628
Short name T144
Test name
Test status
Simulation time 337000250000 ps
CPU time 842.54 seconds
Started Mar 17 02:41:25 PM PDT 24
Finished Mar 17 03:16:17 PM PDT 24
Peak memory 160784 kb
Host smart-65eaea43-501e-4565-9310-96765c8899de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3604954628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3604954628
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1822071945
Short name T132
Test name
Test status
Simulation time 336767950000 ps
CPU time 751.78 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:12:18 PM PDT 24
Peak memory 160776 kb
Host smart-6f86286d-9343-4cd1-a665-37dc249e2034
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1822071945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1822071945
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1855446867
Short name T136
Test name
Test status
Simulation time 336556830000 ps
CPU time 825.57 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:14:54 PM PDT 24
Peak memory 160796 kb
Host smart-b0d50f75-588e-4f0a-b452-ff009694645f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1855446867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1855446867
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.939657981
Short name T115
Test name
Test status
Simulation time 337014830000 ps
CPU time 842.14 seconds
Started Mar 17 02:41:19 PM PDT 24
Finished Mar 17 03:16:03 PM PDT 24
Peak memory 160760 kb
Host smart-5b0f99c0-042e-4ed7-9ff8-8d0ae3629046
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=939657981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.939657981
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.946601183
Short name T28
Test name
Test status
Simulation time 336322730000 ps
CPU time 870.16 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:16:56 PM PDT 24
Peak memory 160800 kb
Host smart-d3795bfa-0435-4d6c-8e18-1749ce141985
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=946601183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.946601183
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4104256119
Short name T112
Test name
Test status
Simulation time 337002370000 ps
CPU time 828.64 seconds
Started Mar 17 02:41:19 PM PDT 24
Finished Mar 17 03:15:44 PM PDT 24
Peak memory 160772 kb
Host smart-ab11c17e-39ea-4ea8-86af-0b7c42153a4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4104256119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.4104256119
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3361423431
Short name T24
Test name
Test status
Simulation time 336495510000 ps
CPU time 803.26 seconds
Started Mar 17 02:41:17 PM PDT 24
Finished Mar 17 03:13:47 PM PDT 24
Peak memory 160792 kb
Host smart-f0d2a0ab-88fb-4b24-8b01-4d08d57ff860
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3361423431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3361423431
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.796247380
Short name T130
Test name
Test status
Simulation time 336400390000 ps
CPU time 808.93 seconds
Started Mar 17 02:41:20 PM PDT 24
Finished Mar 17 03:15:10 PM PDT 24
Peak memory 160760 kb
Host smart-370ba428-40a7-46b1-9d96-793b8b155b68
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=796247380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.796247380
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3407212606
Short name T138
Test name
Test status
Simulation time 336420370000 ps
CPU time 841.07 seconds
Started Mar 17 02:41:24 PM PDT 24
Finished Mar 17 03:16:08 PM PDT 24
Peak memory 160784 kb
Host smart-8971f583-b413-42e9-b564-7c6e8cc01f33
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3407212606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3407212606
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2898407685
Short name T6
Test name
Test status
Simulation time 337061730000 ps
CPU time 729.22 seconds
Started Mar 17 02:41:15 PM PDT 24
Finished Mar 17 03:10:59 PM PDT 24
Peak memory 160716 kb
Host smart-44dcde86-0dae-4e0f-b437-09a8a112ed03
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2898407685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2898407685
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3196877632
Short name T134
Test name
Test status
Simulation time 336888610000 ps
CPU time 779.32 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:13:12 PM PDT 24
Peak memory 160832 kb
Host smart-31a9f16f-d664-4773-a228-3eb49e4276e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3196877632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3196877632
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3589009315
Short name T147
Test name
Test status
Simulation time 336849110000 ps
CPU time 856.59 seconds
Started Mar 17 02:41:16 PM PDT 24
Finished Mar 17 03:16:27 PM PDT 24
Peak memory 160800 kb
Host smart-53c123c1-af68-4e75-8208-cf637fdd50de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3589009315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3589009315
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3068268937
Short name T30
Test name
Test status
Simulation time 336818750000 ps
CPU time 844.6 seconds
Started Mar 17 02:41:24 PM PDT 24
Finished Mar 17 03:16:21 PM PDT 24
Peak memory 160784 kb
Host smart-0271d7ae-8c99-487d-9682-7297f6333d5c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3068268937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3068268937
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3750120402
Short name T121
Test name
Test status
Simulation time 336968990000 ps
CPU time 773.27 seconds
Started Mar 17 02:41:10 PM PDT 24
Finished Mar 17 03:12:29 PM PDT 24
Peak memory 160776 kb
Host smart-bd828713-cd38-4249-a43a-adac5a11b1a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3750120402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3750120402
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2102591843
Short name T143
Test name
Test status
Simulation time 337050210000 ps
CPU time 860.31 seconds
Started Mar 17 02:41:13 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 160824 kb
Host smart-98ef01d8-a106-4756-9146-38563d002792
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2102591843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2102591843
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.268569429
Short name T119
Test name
Test status
Simulation time 337028610000 ps
CPU time 866.77 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:16:49 PM PDT 24
Peak memory 160792 kb
Host smart-350f0616-3a46-48fc-a03b-677bc6d0b8f7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=268569429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.268569429
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.841945759
Short name T129
Test name
Test status
Simulation time 337033750000 ps
CPU time 726.09 seconds
Started Mar 17 02:41:11 PM PDT 24
Finished Mar 17 03:10:45 PM PDT 24
Peak memory 160836 kb
Host smart-a57eb850-d102-447b-b2b8-3989f7440e46
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=841945759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.841945759
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1812270061
Short name T29
Test name
Test status
Simulation time 336521810000 ps
CPU time 758.95 seconds
Started Mar 17 02:41:10 PM PDT 24
Finished Mar 17 03:12:00 PM PDT 24
Peak memory 160784 kb
Host smart-a4d98e98-49de-4d3f-848a-99b7a3ebecc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1812270061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1812270061
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2555494783
Short name T90
Test name
Test status
Simulation time 336368310000 ps
CPU time 856.45 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 01:33:12 PM PDT 24
Peak memory 160436 kb
Host smart-f00cd03f-0d47-44de-845a-58fef5c86a21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2555494783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2555494783
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2679525954
Short name T92
Test name
Test status
Simulation time 336901650000 ps
CPU time 825.68 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:39 PM PDT 24
Peak memory 160756 kb
Host smart-8eb7afe4-2a62-46a5-ad59-15278834626c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2679525954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2679525954
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1202404389
Short name T108
Test name
Test status
Simulation time 337001430000 ps
CPU time 759.36 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:29:17 PM PDT 24
Peak memory 160732 kb
Host smart-c06eaa34-f376-4b47-8be2-9c91dbffec70
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1202404389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1202404389
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.528146055
Short name T96
Test name
Test status
Simulation time 336488790000 ps
CPU time 527.36 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:20:55 PM PDT 24
Peak memory 160968 kb
Host smart-507428a5-a0c4-4ad3-9e06-5835905a7905
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=528146055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.528146055
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.184524295
Short name T74
Test name
Test status
Simulation time 336892830000 ps
CPU time 765.56 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 01:29:51 PM PDT 24
Peak memory 160720 kb
Host smart-0643a8db-a1e1-4f37-bb75-e7da4673c3d8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=184524295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.184524295
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.395522809
Short name T71
Test name
Test status
Simulation time 336488170000 ps
CPU time 758.04 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:28:55 PM PDT 24
Peak memory 160732 kb
Host smart-6fd4b2c8-d436-4bcc-b794-5ed78fe40463
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395522809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.395522809
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.58425441
Short name T72
Test name
Test status
Simulation time 336748850000 ps
CPU time 735.53 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:28:25 PM PDT 24
Peak memory 160708 kb
Host smart-1ab7fa8f-4acd-479a-bf41-e431c2d20362
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=58425441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.58425441
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1959100358
Short name T88
Test name
Test status
Simulation time 336662450000 ps
CPU time 699.09 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:27:05 PM PDT 24
Peak memory 160668 kb
Host smart-fa71d4fd-ae4e-4952-965c-f3e46df2c4af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1959100358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1959100358
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.690828482
Short name T93
Test name
Test status
Simulation time 336641190000 ps
CPU time 779.08 seconds
Started Mar 17 12:58:10 PM PDT 24
Finished Mar 17 01:29:42 PM PDT 24
Peak memory 160712 kb
Host smart-8b1289e7-0a2d-4186-89cc-66cf84f0aea7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=690828482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.690828482
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2001395849
Short name T106
Test name
Test status
Simulation time 336578030000 ps
CPU time 808.14 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 01:32:09 PM PDT 24
Peak memory 160724 kb
Host smart-2a270e87-e288-4012-b06c-1154a6e3fc66
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2001395849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2001395849
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1961566785
Short name T102
Test name
Test status
Simulation time 336660070000 ps
CPU time 811.88 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 01:32:15 PM PDT 24
Peak memory 160724 kb
Host smart-babaf9b7-9bdb-4937-b822-22c6987b3455
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1961566785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1961566785
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1886418823
Short name T80
Test name
Test status
Simulation time 336816850000 ps
CPU time 553.6 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:21:45 PM PDT 24
Peak memory 160688 kb
Host smart-3346b240-f07c-40aa-83fc-c6781dbd6702
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1886418823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1886418823
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3104812544
Short name T82
Test name
Test status
Simulation time 336536650000 ps
CPU time 678.99 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:25:47 PM PDT 24
Peak memory 160712 kb
Host smart-4e874d33-8120-4488-ab4e-adbeced09c43
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3104812544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3104812544
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1602923791
Short name T84
Test name
Test status
Simulation time 336474710000 ps
CPU time 739.22 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:28:29 PM PDT 24
Peak memory 160692 kb
Host smart-043c5bef-742c-48f5-8cea-8fa21ff7050c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1602923791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1602923791
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.295693636
Short name T73
Test name
Test status
Simulation time 336944670000 ps
CPU time 797.53 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:41 PM PDT 24
Peak memory 160672 kb
Host smart-785559a3-6ad6-489a-bb7e-e28a04af6bcd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=295693636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.295693636
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2432206690
Short name T18
Test name
Test status
Simulation time 336667290000 ps
CPU time 801.79 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:30:54 PM PDT 24
Peak memory 160764 kb
Host smart-c08bcc5f-dba5-48ca-8a54-5ee3dcc0bef5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2432206690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2432206690
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.988666220
Short name T79
Test name
Test status
Simulation time 337077830000 ps
CPU time 798.68 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:30:39 PM PDT 24
Peak memory 160720 kb
Host smart-d830fa44-649d-4a16-b45b-7b9e6dcbcb43
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=988666220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.988666220
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.770102640
Short name T103
Test name
Test status
Simulation time 336885990000 ps
CPU time 829.87 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:52 PM PDT 24
Peak memory 160752 kb
Host smart-1d2d30fe-58c9-4e9f-a807-13e060df2708
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=770102640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.770102640
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1405686735
Short name T98
Test name
Test status
Simulation time 336571590000 ps
CPU time 891.29 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:34:45 PM PDT 24
Peak memory 160732 kb
Host smart-9b30b2f4-03ec-4115-964e-1a7b95669faf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1405686735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1405686735
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.419368843
Short name T19
Test name
Test status
Simulation time 336425450000 ps
CPU time 787.62 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:12 PM PDT 24
Peak memory 160672 kb
Host smart-263344bf-9d0f-4de7-b04c-c782f9382727
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=419368843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.419368843
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2228524839
Short name T89
Test name
Test status
Simulation time 337015910000 ps
CPU time 825.47 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 01:32:32 PM PDT 24
Peak memory 160772 kb
Host smart-1fadff8c-d1f9-4b1c-b26e-6f23f45a2e0b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2228524839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2228524839
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.838430867
Short name T77
Test name
Test status
Simulation time 336353170000 ps
CPU time 787.02 seconds
Started Mar 17 12:58:10 PM PDT 24
Finished Mar 17 01:29:47 PM PDT 24
Peak memory 160772 kb
Host smart-47034b1a-4d9c-4b0d-a363-5ac86d118001
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=838430867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.838430867
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.730976602
Short name T107
Test name
Test status
Simulation time 336483450000 ps
CPU time 777.52 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:29:37 PM PDT 24
Peak memory 160812 kb
Host smart-bd5f42d8-8554-4bf8-b2d7-f082137aa434
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=730976602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.730976602
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3642730656
Short name T78
Test name
Test status
Simulation time 337042850000 ps
CPU time 891.35 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:34:30 PM PDT 24
Peak memory 160732 kb
Host smart-5932efea-060f-43fb-87f5-5b80fe14c7a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3642730656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3642730656
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1147812042
Short name T17
Test name
Test status
Simulation time 336293810000 ps
CPU time 699.42 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:27:01 PM PDT 24
Peak memory 160668 kb
Host smart-6caa1f28-9470-4d5b-829f-001d13f76e9e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1147812042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1147812042
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3667519079
Short name T20
Test name
Test status
Simulation time 336559770000 ps
CPU time 857.28 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 01:33:10 PM PDT 24
Peak memory 160452 kb
Host smart-aafe28c0-9ecc-4062-b96c-b1addeb95844
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3667519079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3667519079
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4131175231
Short name T110
Test name
Test status
Simulation time 336519210000 ps
CPU time 768.76 seconds
Started Mar 17 12:58:09 PM PDT 24
Finished Mar 17 01:29:03 PM PDT 24
Peak memory 160728 kb
Host smart-e3b70748-cbb6-4eb8-ad48-1f9032bf3865
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4131175231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4131175231
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1292193108
Short name T21
Test name
Test status
Simulation time 336618650000 ps
CPU time 752.53 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:29:22 PM PDT 24
Peak memory 160728 kb
Host smart-2b5f2a43-4bd2-4efb-a8b6-21c87c0fcd9f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1292193108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1292193108
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.927115421
Short name T101
Test name
Test status
Simulation time 336901270000 ps
CPU time 796.55 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:30:42 PM PDT 24
Peak memory 160720 kb
Host smart-84c74a7c-9bc9-4057-a983-5888744be815
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=927115421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.927115421
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.21315638
Short name T16
Test name
Test status
Simulation time 337019730000 ps
CPU time 833.56 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 160792 kb
Host smart-ef5b8d97-c4c3-4871-b4d3-121580b8b80b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=21315638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.21315638
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1526059062
Short name T75
Test name
Test status
Simulation time 336886330000 ps
CPU time 783.33 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 160764 kb
Host smart-aff0d952-4f0b-418a-929d-5cb7dc13e487
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1526059062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1526059062
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3914187503
Short name T94
Test name
Test status
Simulation time 336568990000 ps
CPU time 767.11 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:29:15 PM PDT 24
Peak memory 160732 kb
Host smart-9805b07f-de7c-4cf3-9ec0-179371fe5b71
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3914187503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3914187503
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3858957347
Short name T81
Test name
Test status
Simulation time 337078270000 ps
CPU time 698.53 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 01:26:55 PM PDT 24
Peak memory 160756 kb
Host smart-82fc39c4-6424-46bf-87d6-a20861e6c3be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3858957347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3858957347
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3880668011
Short name T14
Test name
Test status
Simulation time 337127350000 ps
CPU time 807.41 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 160680 kb
Host smart-3e59a4ae-863d-48d5-b385-8f43d46e14e6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3880668011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3880668011
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2514680187
Short name T105
Test name
Test status
Simulation time 336670790000 ps
CPU time 693.75 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:26:31 PM PDT 24
Peak memory 160760 kb
Host smart-2480f093-e6fc-4631-920d-e7e6af7fadf5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2514680187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2514680187
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1623408980
Short name T100
Test name
Test status
Simulation time 336764710000 ps
CPU time 799.98 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:44 PM PDT 24
Peak memory 160676 kb
Host smart-aa5f49ee-2ee3-472b-b126-4ab2cae3daec
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1623408980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1623408980
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2721183182
Short name T109
Test name
Test status
Simulation time 337012990000 ps
CPU time 831.35 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 01:32:35 PM PDT 24
Peak memory 160780 kb
Host smart-41abd3da-fbac-4585-a367-6cd4fc28b717
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2721183182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2721183182
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3410526121
Short name T83
Test name
Test status
Simulation time 336394630000 ps
CPU time 815.94 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:31:50 PM PDT 24
Peak memory 160688 kb
Host smart-a7010987-f0f1-416f-90dd-f4c5634d7403
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3410526121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3410526121
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1219913164
Short name T15
Test name
Test status
Simulation time 337103070000 ps
CPU time 761.57 seconds
Started Mar 17 12:58:09 PM PDT 24
Finished Mar 17 01:29:05 PM PDT 24
Peak memory 160708 kb
Host smart-b4fae036-73b0-4a69-84d8-d6f5b616a9c7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219913164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1219913164
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2509430937
Short name T85
Test name
Test status
Simulation time 336899750000 ps
CPU time 734.95 seconds
Started Mar 17 12:58:10 PM PDT 24
Finished Mar 17 01:28:00 PM PDT 24
Peak memory 160728 kb
Host smart-cf99ce61-828e-41ff-95d6-43af749d04cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509430937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2509430937
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.331921394
Short name T86
Test name
Test status
Simulation time 336727090000 ps
CPU time 757.88 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 01:29:40 PM PDT 24
Peak memory 160700 kb
Host smart-02062719-341f-42ef-b80a-a9589677a1c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=331921394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.331921394
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1471109399
Short name T99
Test name
Test status
Simulation time 337009250000 ps
CPU time 789.7 seconds
Started Mar 17 12:58:10 PM PDT 24
Finished Mar 17 01:30:22 PM PDT 24
Peak memory 160816 kb
Host smart-3a6543e8-4a6c-4723-be7f-13f82263de1b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1471109399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1471109399
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2696094197
Short name T97
Test name
Test status
Simulation time 336696030000 ps
CPU time 771.84 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 01:29:57 PM PDT 24
Peak memory 160724 kb
Host smart-2dbf2c7e-0899-4f37-a08b-e92c7233372e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2696094197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2696094197
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.62570937
Short name T104
Test name
Test status
Simulation time 336319250000 ps
CPU time 748.98 seconds
Started Mar 17 12:58:10 PM PDT 24
Finished Mar 17 01:28:13 PM PDT 24
Peak memory 160708 kb
Host smart-38c4fbc9-f03c-4491-acd7-efbfb18c2919
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=62570937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.62570937
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3997304806
Short name T76
Test name
Test status
Simulation time 336303050000 ps
CPU time 762.44 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 01:29:00 PM PDT 24
Peak memory 160720 kb
Host smart-38b99825-e19b-487d-9328-7c5bd783c0d6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3997304806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3997304806
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.868828034
Short name T95
Test name
Test status
Simulation time 336485150000 ps
CPU time 828.19 seconds
Started Mar 17 12:58:11 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 160712 kb
Host smart-64f69697-d5b0-4f04-9a12-fe1040fddd71
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=868828034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.868828034
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1350365377
Short name T87
Test name
Test status
Simulation time 336660390000 ps
CPU time 734.97 seconds
Started Mar 17 12:58:10 PM PDT 24
Finished Mar 17 01:28:09 PM PDT 24
Peak memory 160636 kb
Host smart-ab6f0d8a-346a-40bb-b0f6-4b39a7015040
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1350365377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1350365377
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1089812174
Short name T91
Test name
Test status
Simulation time 336316730000 ps
CPU time 695.26 seconds
Started Mar 17 12:58:09 PM PDT 24
Finished Mar 17 01:26:32 PM PDT 24
Peak memory 160768 kb
Host smart-ec4a13f7-dcca-47be-8e8e-7c74eb76cf5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1089812174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1089812174
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2700869538
Short name T22
Test name
Test status
Simulation time 336704650000 ps
CPU time 786.64 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 01:31:16 PM PDT 24
Peak memory 160720 kb
Host smart-ac10f207-dfc0-4d50-932c-bf4c6de91359
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2700869538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2700869538
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3653918750
Short name T185
Test name
Test status
Simulation time 1454930000 ps
CPU time 4.77 seconds
Started Mar 17 12:58:14 PM PDT 24
Finished Mar 17 12:58:24 PM PDT 24
Peak memory 164772 kb
Host smart-40b9ac60-5ea5-4a58-9847-e4cdb4c6470f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3653918750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3653918750
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3478294288
Short name T176
Test name
Test status
Simulation time 1273270000 ps
CPU time 4.6 seconds
Started Mar 17 12:58:15 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 164836 kb
Host smart-f4f4bd0b-771d-4e4e-8e72-468cddc7d49f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3478294288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3478294288
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.515942159
Short name T180
Test name
Test status
Simulation time 1524890000 ps
CPU time 4.66 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164812 kb
Host smart-be427103-b564-4097-82a7-62b65c4265cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=515942159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.515942159
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4238333452
Short name T186
Test name
Test status
Simulation time 1199990000 ps
CPU time 4.16 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 164804 kb
Host smart-558b86b9-ad6a-4144-b185-88beb167b2f4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4238333452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4238333452
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3348850827
Short name T159
Test name
Test status
Simulation time 1520470000 ps
CPU time 4.43 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 164868 kb
Host smart-68c84b41-d3d0-480d-89c6-abd8c59189c2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3348850827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3348850827
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3283437533
Short name T163
Test name
Test status
Simulation time 1372350000 ps
CPU time 3.59 seconds
Started Mar 17 12:58:15 PM PDT 24
Finished Mar 17 12:58:23 PM PDT 24
Peak memory 164836 kb
Host smart-b9e5eed5-56a1-424c-a435-f344ea0dd62b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3283437533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3283437533
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1427926592
Short name T173
Test name
Test status
Simulation time 1547430000 ps
CPU time 4.3 seconds
Started Mar 17 12:58:12 PM PDT 24
Finished Mar 17 12:58:22 PM PDT 24
Peak memory 164912 kb
Host smart-caec9458-6f71-454d-83fb-b88178e92f96
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1427926592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1427926592
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2269918552
Short name T171
Test name
Test status
Simulation time 1450530000 ps
CPU time 4.16 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 164816 kb
Host smart-1beb877a-b40f-41f4-b302-af9c8912b5b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2269918552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2269918552
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1158069303
Short name T184
Test name
Test status
Simulation time 1530030000 ps
CPU time 5.85 seconds
Started Mar 17 12:58:16 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164852 kb
Host smart-31dc6d10-babe-4d93-81af-c8c18e9ba612
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1158069303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1158069303
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1058536676
Short name T200
Test name
Test status
Simulation time 1451270000 ps
CPU time 4.83 seconds
Started Mar 17 12:58:21 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 164900 kb
Host smart-545ce603-767c-443a-bceb-37ad23099e8f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1058536676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1058536676
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3579384788
Short name T175
Test name
Test status
Simulation time 1471350000 ps
CPU time 3.68 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 164840 kb
Host smart-ddf589e6-f0d8-4f33-a093-15f554879436
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3579384788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3579384788
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3263138160
Short name T153
Test name
Test status
Simulation time 1624170000 ps
CPU time 4.41 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 164860 kb
Host smart-bc2e6757-7a9c-4ec5-8310-46b10ad47f29
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3263138160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3263138160
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2376988862
Short name T165
Test name
Test status
Simulation time 1520310000 ps
CPU time 5.01 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164804 kb
Host smart-c17cd694-f458-47ac-aaa5-3fc5b492f4b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2376988862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2376988862
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1388277504
Short name T192
Test name
Test status
Simulation time 1480450000 ps
CPU time 4.76 seconds
Started Mar 17 12:58:20 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 164856 kb
Host smart-96ff02f1-2332-46ff-899f-f02a9fa2e5f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1388277504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1388277504
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1988240950
Short name T199
Test name
Test status
Simulation time 1581210000 ps
CPU time 4.27 seconds
Started Mar 17 12:58:18 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164744 kb
Host smart-9e9b2072-1c73-4b1c-b0a2-683ea6e42c51
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988240950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1988240950
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1345082163
Short name T166
Test name
Test status
Simulation time 1568210000 ps
CPU time 3.91 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164808 kb
Host smart-e8c7fc59-3755-450f-8b15-d0944362936f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1345082163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1345082163
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1341768835
Short name T187
Test name
Test status
Simulation time 1453430000 ps
CPU time 4.85 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 164764 kb
Host smart-35ab5799-e5c2-461b-996e-b9c50d9699ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341768835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1341768835
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3482545237
Short name T170
Test name
Test status
Simulation time 1543150000 ps
CPU time 4.81 seconds
Started Mar 17 12:58:20 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 164856 kb
Host smart-e2015570-ebaf-4d7a-875f-43b7a33a5b86
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482545237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3482545237
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.382319059
Short name T190
Test name
Test status
Simulation time 1372050000 ps
CPU time 4.64 seconds
Started Mar 17 12:58:22 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 164780 kb
Host smart-0a3b91bd-f75f-4d49-ad7f-875ecc4616c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=382319059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.382319059
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2961251935
Short name T157
Test name
Test status
Simulation time 1452950000 ps
CPU time 4.45 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164844 kb
Host smart-0f80acba-e63e-423b-9b85-17594a46c32a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2961251935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2961251935
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1926811717
Short name T179
Test name
Test status
Simulation time 1616390000 ps
CPU time 4.87 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 164868 kb
Host smart-714935d7-1918-4563-af40-35665ebef0e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1926811717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1926811717
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.490824562
Short name T168
Test name
Test status
Simulation time 1429530000 ps
CPU time 5.01 seconds
Started Mar 17 12:58:21 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 164800 kb
Host smart-42a79c7a-f790-4366-ac3f-60d9f6985c9e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=490824562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.490824562
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2692138425
Short name T189
Test name
Test status
Simulation time 1538810000 ps
CPU time 6.11 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:30 PM PDT 24
Peak memory 164832 kb
Host smart-02856c52-2e96-4185-a684-db2aba5d6ea3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692138425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2692138425
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1267815351
Short name T169
Test name
Test status
Simulation time 1434210000 ps
CPU time 3.63 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 12:58:21 PM PDT 24
Peak memory 164812 kb
Host smart-40213e4f-3308-4a35-9d23-cf56a956b62a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267815351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1267815351
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.442498713
Short name T177
Test name
Test status
Simulation time 1402790000 ps
CPU time 4.37 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 164780 kb
Host smart-e5bad762-e67e-4929-bef6-6e7bb8d0d614
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=442498713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.442498713
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3900017517
Short name T164
Test name
Test status
Simulation time 1360230000 ps
CPU time 3.2 seconds
Started Mar 17 12:58:18 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 164840 kb
Host smart-89530e44-31a7-4e2b-8ded-2b2845ece9cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900017517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3900017517
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3415178689
Short name T188
Test name
Test status
Simulation time 1554930000 ps
CPU time 4.52 seconds
Started Mar 17 12:58:27 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 164808 kb
Host smart-83fae6be-8b8f-4091-9dc6-3c8cb3ed4786
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3415178689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3415178689
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3872255130
Short name T154
Test name
Test status
Simulation time 1141110000 ps
CPU time 3.63 seconds
Started Mar 17 12:58:21 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 164900 kb
Host smart-bd681ad1-0f63-48f7-956a-2dabe9a2be08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3872255130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3872255130
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2174837271
Short name T152
Test name
Test status
Simulation time 1610070000 ps
CPU time 5.08 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:36 PM PDT 24
Peak memory 164796 kb
Host smart-f4936403-3625-4fe3-be1e-e2b30adffb3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2174837271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2174837271
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3878629332
Short name T193
Test name
Test status
Simulation time 1506750000 ps
CPU time 3.97 seconds
Started Mar 17 12:58:20 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 164912 kb
Host smart-9ebe758f-4225-4b61-83e9-fea5eae4648c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3878629332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3878629332
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1478864866
Short name T181
Test name
Test status
Simulation time 1520790000 ps
CPU time 4.1 seconds
Started Mar 17 12:58:23 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 164800 kb
Host smart-3e47332f-a99b-4be4-a34d-49d8a1c7c405
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1478864866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1478864866
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2265563173
Short name T178
Test name
Test status
Simulation time 1566990000 ps
CPU time 4.74 seconds
Started Mar 17 12:58:27 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 164860 kb
Host smart-ac233d1f-98ed-4a7c-b423-095a88d9e166
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265563173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2265563173
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2238940263
Short name T197
Test name
Test status
Simulation time 1272370000 ps
CPU time 3.84 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 164784 kb
Host smart-de090d1b-8609-49c8-81ef-afe75587fcc4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2238940263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2238940263
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1550839698
Short name T183
Test name
Test status
Simulation time 1544030000 ps
CPU time 5.7 seconds
Started Mar 17 12:58:20 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 164896 kb
Host smart-0208e176-0eeb-4139-832f-a476eaf68bc6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1550839698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1550839698
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2710904238
Short name T160
Test name
Test status
Simulation time 1418490000 ps
CPU time 4.44 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164812 kb
Host smart-2bcae712-6af4-46ae-a7a9-73aa13e36df7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710904238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2710904238
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3104453327
Short name T158
Test name
Test status
Simulation time 1331890000 ps
CPU time 4.02 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 164840 kb
Host smart-4acad8ac-2214-4984-beec-3dd1875e06f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104453327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3104453327
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3708483739
Short name T174
Test name
Test status
Simulation time 1551110000 ps
CPU time 4.84 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 164896 kb
Host smart-bea68b1e-3d89-41b0-b996-2f3c944e1b0b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3708483739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3708483739
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3030653257
Short name T182
Test name
Test status
Simulation time 1460070000 ps
CPU time 4.35 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 164860 kb
Host smart-9e4ea727-39ca-4e3c-b611-080642cbe6c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3030653257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3030653257
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1680008129
Short name T167
Test name
Test status
Simulation time 1514450000 ps
CPU time 5.16 seconds
Started Mar 17 12:58:21 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 164796 kb
Host smart-f97b4fb3-b12b-47e1-80a8-387ea17c0d80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1680008129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1680008129
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3232311002
Short name T151
Test name
Test status
Simulation time 1571530000 ps
CPU time 3.33 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 164808 kb
Host smart-a7c873cb-fb61-4c52-8fe3-d38fe7503f8f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3232311002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3232311002
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1212965664
Short name T194
Test name
Test status
Simulation time 1425150000 ps
CPU time 3.22 seconds
Started Mar 17 12:58:18 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 164844 kb
Host smart-ac544250-6258-46e0-b735-72a73fe519d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1212965664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1212965664
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1591903662
Short name T162
Test name
Test status
Simulation time 1580830000 ps
CPU time 4.83 seconds
Started Mar 17 12:58:21 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 164828 kb
Host smart-fe39cd29-35dd-4f10-a77f-f7aacf5d3dc2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1591903662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1591903662
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2627598027
Short name T156
Test name
Test status
Simulation time 1251870000 ps
CPU time 3.47 seconds
Started Mar 17 12:58:18 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 164812 kb
Host smart-d41be63b-4f07-4c3e-8c61-d85c739cc410
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2627598027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2627598027
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4257767694
Short name T172
Test name
Test status
Simulation time 1401650000 ps
CPU time 4.82 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:36 PM PDT 24
Peak memory 164896 kb
Host smart-001c8a49-8843-4c49-9ffa-3a3cb04b9987
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257767694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4257767694
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.59257222
Short name T161
Test name
Test status
Simulation time 1304350000 ps
CPU time 2.89 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:23 PM PDT 24
Peak memory 164756 kb
Host smart-5cc24d2d-3faa-4222-99bd-f0690f7e3f06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=59257222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.59257222
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1451645016
Short name T198
Test name
Test status
Simulation time 1396790000 ps
CPU time 4.38 seconds
Started Mar 17 12:58:13 PM PDT 24
Finished Mar 17 12:58:23 PM PDT 24
Peak memory 164832 kb
Host smart-d0e251e8-18f5-46bc-8e82-0b441863b944
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1451645016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1451645016
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.4249156468
Short name T196
Test name
Test status
Simulation time 1188450000 ps
CPU time 3.09 seconds
Started Mar 17 12:58:15 PM PDT 24
Finished Mar 17 12:58:22 PM PDT 24
Peak memory 164836 kb
Host smart-fef9c503-4746-4ab2-92cf-1be426612e16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4249156468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.4249156468
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2206598928
Short name T155
Test name
Test status
Simulation time 1538290000 ps
CPU time 4.9 seconds
Started Mar 17 12:58:16 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 164804 kb
Host smart-29162a2e-26cf-4ab2-a7cf-67e862b147c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206598928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2206598928
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.935050742
Short name T191
Test name
Test status
Simulation time 1198870000 ps
CPU time 4.24 seconds
Started Mar 17 12:58:16 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 164856 kb
Host smart-90860839-f8aa-4ed4-8074-64bd6def25e4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=935050742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.935050742
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3155865549
Short name T195
Test name
Test status
Simulation time 1538990000 ps
CPU time 4.6 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 164812 kb
Host smart-36f84607-a8c9-4844-96d5-18c1bfbaa6ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3155865549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3155865549
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3710768869
Short name T32
Test name
Test status
Simulation time 1441510000 ps
CPU time 4.45 seconds
Started Mar 17 02:58:58 PM PDT 24
Finished Mar 17 02:59:08 PM PDT 24
Peak memory 164904 kb
Host smart-0defb744-a27c-4c40-bfd1-d3b964975f68
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3710768869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3710768869
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1980391821
Short name T58
Test name
Test status
Simulation time 1506390000 ps
CPU time 4.38 seconds
Started Mar 17 02:58:53 PM PDT 24
Finished Mar 17 02:59:02 PM PDT 24
Peak memory 164896 kb
Host smart-a0e425a9-9c7d-4834-8c97-96af25f3ece4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980391821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1980391821
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3679326621
Short name T46
Test name
Test status
Simulation time 1539850000 ps
CPU time 4.12 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:08 PM PDT 24
Peak memory 164868 kb
Host smart-dc8be3fb-cc06-4769-9062-a3ce33ed7cd1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3679326621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3679326621
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.161736582
Short name T63
Test name
Test status
Simulation time 1354770000 ps
CPU time 4.69 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 164860 kb
Host smart-27e2104f-7bb6-48bb-95fa-c96e9ead9f83
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161736582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.161736582
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.981001595
Short name T64
Test name
Test status
Simulation time 1316910000 ps
CPU time 3.41 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:07 PM PDT 24
Peak memory 164920 kb
Host smart-5a83e5be-099a-4a36-b49e-a808b4f7e162
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=981001595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.981001595
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2487517207
Short name T31
Test name
Test status
Simulation time 1467890000 ps
CPU time 4.89 seconds
Started Mar 17 02:59:00 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 164840 kb
Host smart-95fb909b-9284-4dcb-bc5a-8f9ff4ed94ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2487517207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2487517207
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3991935430
Short name T7
Test name
Test status
Simulation time 1407130000 ps
CPU time 5.26 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 164888 kb
Host smart-074ccbec-d5cc-4ebe-be6b-d849d5bbda26
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3991935430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3991935430
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1684202761
Short name T3
Test name
Test status
Simulation time 1548970000 ps
CPU time 4.28 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:08 PM PDT 24
Peak memory 164920 kb
Host smart-24f7ebef-ade0-4e03-8517-4ed6ae85dae7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1684202761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1684202761
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3619262908
Short name T8
Test name
Test status
Simulation time 1576290000 ps
CPU time 4.82 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 164880 kb
Host smart-b9ab791f-4882-4607-9e27-0fcecb354c2b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3619262908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3619262908
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1031911889
Short name T13
Test name
Test status
Simulation time 1567490000 ps
CPU time 5.34 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 164256 kb
Host smart-5b0316c5-c199-4c75-a1d8-adeb06f56ede
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1031911889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1031911889
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.142359405
Short name T49
Test name
Test status
Simulation time 1482250000 ps
CPU time 5.61 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 164888 kb
Host smart-3e95360e-14f9-4749-8079-241342650dfc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=142359405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.142359405
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3259176415
Short name T36
Test name
Test status
Simulation time 1246570000 ps
CPU time 4.12 seconds
Started Mar 17 02:58:55 PM PDT 24
Finished Mar 17 02:59:04 PM PDT 24
Peak memory 164844 kb
Host smart-9bb783be-9dea-4acf-8167-fb5413a82596
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3259176415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3259176415
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.388094233
Short name T35
Test name
Test status
Simulation time 1299290000 ps
CPU time 3.4 seconds
Started Mar 17 02:59:05 PM PDT 24
Finished Mar 17 02:59:12 PM PDT 24
Peak memory 164888 kb
Host smart-434bee00-1a74-48f4-81e4-8fb143e6f654
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388094233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.388094233
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1800111439
Short name T43
Test name
Test status
Simulation time 1316290000 ps
CPU time 3.74 seconds
Started Mar 17 02:59:03 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 164804 kb
Host smart-cafab973-f5ea-466f-a030-86f94f42e1e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1800111439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1800111439
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2923819918
Short name T53
Test name
Test status
Simulation time 1537930000 ps
CPU time 3.33 seconds
Started Mar 17 02:59:03 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 164844 kb
Host smart-ba49a8b5-862e-4b53-ad6f-123af715efe3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2923819918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2923819918
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2344878883
Short name T54
Test name
Test status
Simulation time 1476330000 ps
CPU time 5.53 seconds
Started Mar 17 02:59:02 PM PDT 24
Finished Mar 17 02:59:14 PM PDT 24
Peak memory 164892 kb
Host smart-98df6799-4287-4b55-b884-a25f386372bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2344878883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2344878883
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1016860171
Short name T70
Test name
Test status
Simulation time 1447390000 ps
CPU time 5.05 seconds
Started Mar 17 02:59:03 PM PDT 24
Finished Mar 17 02:59:14 PM PDT 24
Peak memory 164888 kb
Host smart-d654fb91-57ce-4833-9060-64f32d393d8c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1016860171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1016860171
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3500129209
Short name T59
Test name
Test status
Simulation time 1363690000 ps
CPU time 4.36 seconds
Started Mar 17 02:59:02 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 164948 kb
Host smart-cd3a8077-e2b5-4095-ae35-3ee2dafe1411
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3500129209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3500129209
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3431868142
Short name T51
Test name
Test status
Simulation time 1462350000 ps
CPU time 4.22 seconds
Started Mar 17 02:59:02 PM PDT 24
Finished Mar 17 02:59:12 PM PDT 24
Peak memory 164900 kb
Host smart-1831d03a-e1e7-4afb-8e7b-720a866984a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3431868142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3431868142
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1314905560
Short name T52
Test name
Test status
Simulation time 1398910000 ps
CPU time 3.77 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:13 PM PDT 24
Peak memory 164888 kb
Host smart-6961fb8c-5a65-489c-aa6b-dbb0b5b74607
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1314905560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1314905560
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.728485425
Short name T37
Test name
Test status
Simulation time 1499550000 ps
CPU time 4.85 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 164856 kb
Host smart-3f38a0b7-87b7-44e8-89d3-0cb6c4194eae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=728485425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.728485425
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2605423680
Short name T61
Test name
Test status
Simulation time 1396530000 ps
CPU time 4.76 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 164160 kb
Host smart-38fe23b2-009d-45f8-8eea-22f7a88280b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2605423680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2605423680
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.845740407
Short name T57
Test name
Test status
Simulation time 1509390000 ps
CPU time 4.75 seconds
Started Mar 17 02:58:54 PM PDT 24
Finished Mar 17 02:59:05 PM PDT 24
Peak memory 164916 kb
Host smart-2f6caa86-bf02-433b-912a-03077696f71f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=845740407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.845740407
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2206833700
Short name T55
Test name
Test status
Simulation time 1414990000 ps
CPU time 3.83 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:12 PM PDT 24
Peak memory 164888 kb
Host smart-c2783a9e-8464-48e5-b993-aab8dfed80c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206833700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2206833700
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1457684830
Short name T66
Test name
Test status
Simulation time 1542290000 ps
CPU time 4.91 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 164864 kb
Host smart-0b578750-06a1-4b80-b48e-60bae49debff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457684830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1457684830
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2236283630
Short name T33
Test name
Test status
Simulation time 1603150000 ps
CPU time 3.8 seconds
Started Mar 17 02:59:02 PM PDT 24
Finished Mar 17 02:59:11 PM PDT 24
Peak memory 164904 kb
Host smart-4a7bb921-b4a4-400b-a2f1-191c56b70c3e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236283630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2236283630
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3300245640
Short name T68
Test name
Test status
Simulation time 1387570000 ps
CPU time 3.51 seconds
Started Mar 17 02:59:03 PM PDT 24
Finished Mar 17 02:59:12 PM PDT 24
Peak memory 164940 kb
Host smart-94243823-3d76-4ad3-86ec-8c0adcac92de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3300245640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3300245640
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2019648775
Short name T10
Test name
Test status
Simulation time 1413790000 ps
CPU time 4.09 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:13 PM PDT 24
Peak memory 164892 kb
Host smart-f8a653ee-c34e-4072-8b17-cca3172659bc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2019648775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2019648775
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2317829224
Short name T1
Test name
Test status
Simulation time 1526490000 ps
CPU time 5.7 seconds
Started Mar 17 02:59:03 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 164884 kb
Host smart-3eb97d60-3131-4b8e-923c-7488986d180d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2317829224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2317829224
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1410165907
Short name T44
Test name
Test status
Simulation time 1284570000 ps
CPU time 3.09 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 164896 kb
Host smart-51caa01f-291d-46a3-9868-b74c5aa4bc83
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1410165907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1410165907
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3620007438
Short name T41
Test name
Test status
Simulation time 1226290000 ps
CPU time 4.03 seconds
Started Mar 17 02:59:04 PM PDT 24
Finished Mar 17 02:59:13 PM PDT 24
Peak memory 164864 kb
Host smart-d6a24606-55ef-481e-b8f7-e1feddd2718c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620007438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3620007438
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.390115080
Short name T45
Test name
Test status
Simulation time 1488370000 ps
CPU time 4.2 seconds
Started Mar 17 02:59:07 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 164888 kb
Host smart-4cd92014-2bfa-4026-a5d7-fa01df8de42b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=390115080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.390115080
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1490286767
Short name T40
Test name
Test status
Simulation time 1321210000 ps
CPU time 4.6 seconds
Started Mar 17 02:59:08 PM PDT 24
Finished Mar 17 02:59:18 PM PDT 24
Peak memory 164896 kb
Host smart-cbd15552-d879-412d-9157-246ffd4ff1ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490286767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1490286767
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1729647177
Short name T69
Test name
Test status
Simulation time 1368210000 ps
CPU time 4.47 seconds
Started Mar 17 02:58:56 PM PDT 24
Finished Mar 17 02:59:06 PM PDT 24
Peak memory 164904 kb
Host smart-cde1656a-4d51-48c2-8fed-7e7c4a6448d9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1729647177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1729647177
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.117969163
Short name T62
Test name
Test status
Simulation time 1568930000 ps
CPU time 4.89 seconds
Started Mar 17 02:59:08 PM PDT 24
Finished Mar 17 02:59:19 PM PDT 24
Peak memory 164880 kb
Host smart-3e196f11-2854-4384-9058-56acd948cc88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=117969163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.117969163
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3192259295
Short name T56
Test name
Test status
Simulation time 1579250000 ps
CPU time 4.41 seconds
Started Mar 17 02:59:08 PM PDT 24
Finished Mar 17 02:59:18 PM PDT 24
Peak memory 164944 kb
Host smart-755b7ca4-e2cb-49b1-ad33-6ab0d1109d06
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3192259295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3192259295
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3625552871
Short name T34
Test name
Test status
Simulation time 1482530000 ps
CPU time 4.54 seconds
Started Mar 17 02:59:08 PM PDT 24
Finished Mar 17 02:59:18 PM PDT 24
Peak memory 164956 kb
Host smart-a9b74f90-3c2b-411a-9ea0-30b41c46236f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3625552871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3625552871
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.219637378
Short name T9
Test name
Test status
Simulation time 1608570000 ps
CPU time 4.56 seconds
Started Mar 17 02:59:07 PM PDT 24
Finished Mar 17 02:59:18 PM PDT 24
Peak memory 164876 kb
Host smart-58aba263-5192-44ff-a132-a4b4357a218a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=219637378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.219637378
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3966803079
Short name T39
Test name
Test status
Simulation time 1496330000 ps
CPU time 5.41 seconds
Started Mar 17 02:59:07 PM PDT 24
Finished Mar 17 02:59:19 PM PDT 24
Peak memory 164884 kb
Host smart-300a094b-6409-40c9-88bb-920b0a1c3f1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3966803079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3966803079
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3825756119
Short name T65
Test name
Test status
Simulation time 1231970000 ps
CPU time 4.03 seconds
Started Mar 17 02:59:07 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 164844 kb
Host smart-e1c4d3b5-12df-4219-b519-263873ee350f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3825756119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3825756119
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1859049379
Short name T11
Test name
Test status
Simulation time 1443530000 ps
CPU time 3.43 seconds
Started Mar 17 02:59:09 PM PDT 24
Finished Mar 17 02:59:16 PM PDT 24
Peak memory 164876 kb
Host smart-407b9545-9c36-4cc6-8f61-a541d39b01b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1859049379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1859049379
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3924758079
Short name T67
Test name
Test status
Simulation time 1459310000 ps
CPU time 3.73 seconds
Started Mar 17 02:59:05 PM PDT 24
Finished Mar 17 02:59:14 PM PDT 24
Peak memory 164940 kb
Host smart-d7c8ea9d-253b-4e36-977d-58fcb73f891c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3924758079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3924758079
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2422999806
Short name T60
Test name
Test status
Simulation time 1223390000 ps
CPU time 3.43 seconds
Started Mar 17 02:59:07 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 164900 kb
Host smart-a24833ab-bf01-4817-9a8b-fbc41c358ffe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2422999806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2422999806
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1352386813
Short name T42
Test name
Test status
Simulation time 1449090000 ps
CPU time 3.39 seconds
Started Mar 17 02:59:07 PM PDT 24
Finished Mar 17 02:59:15 PM PDT 24
Peak memory 164896 kb
Host smart-a396ec76-2332-4562-a337-cba1d3812c6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1352386813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1352386813
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.461932047
Short name T50
Test name
Test status
Simulation time 1531670000 ps
CPU time 4.06 seconds
Started Mar 17 02:58:54 PM PDT 24
Finished Mar 17 02:59:03 PM PDT 24
Peak memory 164952 kb
Host smart-a58887c8-db83-4655-a88f-c5bafb5bba91
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461932047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.461932047
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.779760004
Short name T2
Test name
Test status
Simulation time 1569810000 ps
CPU time 3.99 seconds
Started Mar 17 02:59:01 PM PDT 24
Finished Mar 17 02:59:10 PM PDT 24
Peak memory 164864 kb
Host smart-bdcaa86a-93d7-4ae5-beff-d50926917038
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=779760004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.779760004
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1933049216
Short name T48
Test name
Test status
Simulation time 1309190000 ps
CPU time 4.41 seconds
Started Mar 17 02:58:57 PM PDT 24
Finished Mar 17 02:59:08 PM PDT 24
Peak memory 164908 kb
Host smart-0e7d4219-5c82-451f-9e00-2eb2aafded03
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1933049216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1933049216
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2201636630
Short name T47
Test name
Test status
Simulation time 1382710000 ps
CPU time 4.69 seconds
Started Mar 17 02:58:58 PM PDT 24
Finished Mar 17 02:59:09 PM PDT 24
Peak memory 164816 kb
Host smart-3a5576f4-1048-47f5-bed3-d8c2963635cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2201636630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2201636630
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3072426531
Short name T38
Test name
Test status
Simulation time 1526290000 ps
CPU time 5.55 seconds
Started Mar 17 02:58:59 PM PDT 24
Finished Mar 17 02:59:13 PM PDT 24
Peak memory 164864 kb
Host smart-794939cb-4cb3-4439-9d5f-1f5cc44c4870
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3072426531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3072426531
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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