Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.325683411
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.74473736
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3191840143

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4044816283
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3979982879
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3657493931
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.104648652
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.399406009
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1691405619
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.555143314
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2292028358
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2350918492
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2784678686
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2760502065
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2295447651
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3166042849
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.271067605
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3236527523
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1922452689
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3611452729
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.334869830
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2636932986
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1211988645
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1636373616
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1482123687
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1604800115
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4262606557
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2172079520
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.215633326
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1649932398
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2652926141
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.690715144
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.325232749
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1976901643
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2653159766
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2711590344
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1100127139
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1219348976
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3128953016
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2772858410
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1106893568
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3195771044
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.513996037
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3546250304
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.803592155
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2253005470
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4116817859
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.352836447
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2473592376
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1742556595
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1866877678
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2820196275
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.76898527
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3823290029
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2997532889
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3284277693
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1010237099
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2631456810
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3812243204
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3952768801
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2192368549
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3271813750
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1065800382
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2257571094
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.71670292
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4033699010
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2249503041
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4201807827
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.118608183
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1531773310
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.928128449
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2139694853
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1861413145
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2040690647
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.487596405
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1185317839
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2085955442
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.993178584
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1777794809
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2568734945
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3541562288
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4090028460
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.150289217
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3824545792
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1941813873
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.384273138
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2703813339
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2719836746
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2282797065
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2997757176
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1857799454
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3043866
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1448669897
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.815017349
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.171549135
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3098077086
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3090015437
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3790911238
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.892997319
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4264823682
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3218016468
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.351854105
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1229571732
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1600040616
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1554239006
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4076173850
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.514904385
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3040015039
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.382416803
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2433417375
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2816340481
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1883320851
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1447545909
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3196457975
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4126815878
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3761945207
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.101534185
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.718787467
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2968591873
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.918180013
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2467349080
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1522436156
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1049084459
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.905177841
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1831428779
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4276902076
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2634118197
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.612451439
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1487767833
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2277857305
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4169408789
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2296886849
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3918763897
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2523390829
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.878506570
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1013392939
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3493535564
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.321410457
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2315761810
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3649144845
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3678808405
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4248652016
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3023071376
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4068677424
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2562509269
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3865508746
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2972222162
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2085530060
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2071423018
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2453392679
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.633888525
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3271240971
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1768216661
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.915694300
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.641561617
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3175018407
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1570135421
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3829590446
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2895163118
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3741584550
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2008500609
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1873768532
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2797342727
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1606309994
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.726988207
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.536195562
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3998339576
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.960126011
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1150132977
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1457441485
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1247666386
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3338768703
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3434134223
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1385731039
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2671669805
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2026233427
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1712182069
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2816457802
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3066388930
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2216827737
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1050075908
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1807943117
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1987205105
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.225676664
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.882215468
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3635979400
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2988118990
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1964329232
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1144061839
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2369178011
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2723215716
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1655687993
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1600980991
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2953513893
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2525187676
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1317625899
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.396072287
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.893321498
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1247308460
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1692004688



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1570135421 Mar 21 12:22:28 PM PDT 24 Mar 21 12:22:43 PM PDT 24 1613330000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2369178011 Mar 21 12:17:32 PM PDT 24 Mar 21 12:17:42 PM PDT 24 1562510000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1247308460 Mar 21 12:16:34 PM PDT 24 Mar 21 12:16:48 PM PDT 24 1506370000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2816457802 Mar 21 12:20:50 PM PDT 24 Mar 21 12:21:00 PM PDT 24 1524330000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1964329232 Mar 21 12:23:12 PM PDT 24 Mar 21 12:23:23 PM PDT 24 1544130000 ps
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T128 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.399406009 Mar 21 12:16:33 PM PDT 24 Mar 21 12:44:18 PM PDT 24 336445330000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1922452689 Mar 21 12:22:28 PM PDT 24 Mar 21 12:54:18 PM PDT 24 336681030000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2253005470 Mar 21 12:22:24 PM PDT 24 Mar 21 12:50:08 PM PDT 24 336939610000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3979982879 Mar 21 12:16:24 PM PDT 24 Mar 21 12:42:17 PM PDT 24 336353330000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1866877678 Mar 21 12:21:48 PM PDT 24 Mar 21 12:51:12 PM PDT 24 336877210000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1106893568 Mar 21 12:21:42 PM PDT 24 Mar 21 12:56:08 PM PDT 24 337074910000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1604800115 Mar 21 12:23:00 PM PDT 24 Mar 21 12:47:17 PM PDT 24 336533310000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2652926141 Mar 21 12:23:58 PM PDT 24 Mar 21 12:52:22 PM PDT 24 336388610000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1100127139 Mar 21 12:21:29 PM PDT 24 Mar 21 12:49:19 PM PDT 24 337120910000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4044816283 Mar 21 12:19:47 PM PDT 24 Mar 21 12:57:26 PM PDT 24 337014850000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1211988645 Mar 21 12:22:59 PM PDT 24 Mar 21 12:49:50 PM PDT 24 336450110000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1482123687 Mar 21 12:23:03 PM PDT 24 Mar 21 12:50:43 PM PDT 24 336649450000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1976901643 Mar 21 12:22:36 PM PDT 24 Mar 21 12:49:42 PM PDT 24 336393790000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2653159766 Mar 21 12:22:51 PM PDT 24 Mar 21 12:53:12 PM PDT 24 336630750000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3236527523 Mar 21 12:18:15 PM PDT 24 Mar 21 01:00:37 PM PDT 24 336713590000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4262606557 Mar 21 12:23:30 PM PDT 24 Mar 21 12:53:59 PM PDT 24 336946350000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.803592155 Mar 21 12:23:07 PM PDT 24 Mar 21 12:51:01 PM PDT 24 336395730000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1742556595 Mar 21 12:21:48 PM PDT 24 Mar 21 12:51:13 PM PDT 24 336480590000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1219348976 Mar 21 12:21:41 PM PDT 24 Mar 21 12:56:10 PM PDT 24 336714730000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.104648652 Mar 21 12:16:23 PM PDT 24 Mar 21 12:42:21 PM PDT 24 336315270000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.690715144 Mar 21 12:23:29 PM PDT 24 Mar 21 12:54:17 PM PDT 24 336321670000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3166042849 Mar 21 12:16:35 PM PDT 24 Mar 21 12:59:01 PM PDT 24 336508350000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2711590344 Mar 21 12:22:18 PM PDT 24 Mar 21 12:45:24 PM PDT 24 336543110000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1522436156 Mar 21 12:16:30 PM PDT 24 Mar 21 12:16:41 PM PDT 24 1243090000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2296886849 Mar 21 12:22:31 PM PDT 24 Mar 21 12:22:42 PM PDT 24 1387550000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1600040616 Mar 21 12:23:00 PM PDT 24 Mar 21 12:23:08 PM PDT 24 1399930000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.382416803 Mar 21 12:23:08 PM PDT 24 Mar 21 12:23:15 PM PDT 24 1524370000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2467349080 Mar 21 12:16:24 PM PDT 24 Mar 21 12:16:32 PM PDT 24 1535110000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4276902076 Mar 21 12:17:29 PM PDT 24 Mar 21 12:17:37 PM PDT 24 1493390000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1049084459 Mar 21 12:16:34 PM PDT 24 Mar 21 12:16:47 PM PDT 24 1613430000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4126815878 Mar 21 12:22:23 PM PDT 24 Mar 21 12:22:32 PM PDT 24 1421850000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1229571732 Mar 21 12:22:26 PM PDT 24 Mar 21 12:22:34 PM PDT 24 1528350000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3678808405 Mar 21 12:22:16 PM PDT 24 Mar 21 12:22:27 PM PDT 24 1324150000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2071423018 Mar 21 12:20:16 PM PDT 24 Mar 21 12:20:27 PM PDT 24 1358030000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3493535564 Mar 21 12:22:08 PM PDT 24 Mar 21 12:22:21 PM PDT 24 1515410000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.633888525 Mar 21 12:22:49 PM PDT 24 Mar 21 12:22:56 PM PDT 24 1441890000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2968591873 Mar 21 12:22:23 PM PDT 24 Mar 21 12:22:32 PM PDT 24 1423270000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3918763897 Mar 21 12:22:28 PM PDT 24 Mar 21 12:22:42 PM PDT 24 1489050000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3761945207 Mar 21 12:16:30 PM PDT 24 Mar 21 12:16:40 PM PDT 24 1350070000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2562509269 Mar 21 12:23:23 PM PDT 24 Mar 21 12:23:30 PM PDT 24 1401530000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4248652016 Mar 21 12:22:08 PM PDT 24 Mar 21 12:22:21 PM PDT 24 1509930000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1487767833 Mar 21 12:19:13 PM PDT 24 Mar 21 12:19:24 PM PDT 24 1624990000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2277857305 Mar 21 12:22:23 PM PDT 24 Mar 21 12:22:33 PM PDT 24 1505250000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1883320851 Mar 21 12:21:59 PM PDT 24 Mar 21 12:22:07 PM PDT 24 1146570000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3040015039 Mar 21 12:21:36 PM PDT 24 Mar 21 12:21:46 PM PDT 24 1381150000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4068677424 Mar 21 12:22:27 PM PDT 24 Mar 21 12:22:35 PM PDT 24 1586450000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.612451439 Mar 21 12:17:36 PM PDT 24 Mar 21 12:17:44 PM PDT 24 1549510000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1554239006 Mar 21 12:18:48 PM PDT 24 Mar 21 12:18:59 PM PDT 24 1179170000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.351854105 Mar 21 12:22:53 PM PDT 24 Mar 21 12:23:00 PM PDT 24 1250030000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2634118197 Mar 21 12:17:09 PM PDT 24 Mar 21 12:17:16 PM PDT 24 1114870000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3023071376 Mar 21 12:22:16 PM PDT 24 Mar 21 12:22:27 PM PDT 24 1460590000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2816340481 Mar 21 12:21:28 PM PDT 24 Mar 21 12:21:37 PM PDT 24 1492050000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1831428779 Mar 21 12:22:26 PM PDT 24 Mar 21 12:22:34 PM PDT 24 1443870000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2972222162 Mar 21 12:19:41 PM PDT 24 Mar 21 12:19:52 PM PDT 24 1522490000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2433417375 Mar 21 12:21:37 PM PDT 24 Mar 21 12:21:48 PM PDT 24 1575670000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.878506570 Mar 21 12:20:41 PM PDT 24 Mar 21 12:20:49 PM PDT 24 1519750000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4169408789 Mar 21 12:22:23 PM PDT 24 Mar 21 12:22:33 PM PDT 24 1521570000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4076173850 Mar 21 12:18:47 PM PDT 24 Mar 21 12:18:59 PM PDT 24 1250990000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2085530060 Mar 21 12:19:37 PM PDT 24 Mar 21 12:19:49 PM PDT 24 1441590000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2315761810 Mar 21 12:18:22 PM PDT 24 Mar 21 12:18:32 PM PDT 24 1489010000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3649144845 Mar 21 12:22:47 PM PDT 24 Mar 21 12:22:56 PM PDT 24 1251070000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.321410457 Mar 21 12:22:47 PM PDT 24 Mar 21 12:23:00 PM PDT 24 1547510000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2453392679 Mar 21 12:22:36 PM PDT 24 Mar 21 12:22:44 PM PDT 24 1479690000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3865508746 Mar 21 12:23:09 PM PDT 24 Mar 21 12:23:17 PM PDT 24 1484690000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.918180013 Mar 21 12:16:29 PM PDT 24 Mar 21 12:16:41 PM PDT 24 1434630000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.718787467 Mar 21 12:17:36 PM PDT 24 Mar 21 12:17:44 PM PDT 24 1455790000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.905177841 Mar 21 12:16:33 PM PDT 24 Mar 21 12:16:44 PM PDT 24 1236030000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3196457975 Mar 21 12:22:34 PM PDT 24 Mar 21 12:22:44 PM PDT 24 1276170000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2523390829 Mar 21 12:22:28 PM PDT 24 Mar 21 12:22:43 PM PDT 24 1524370000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1447545909 Mar 21 12:16:33 PM PDT 24 Mar 21 12:16:44 PM PDT 24 1171750000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.514904385 Mar 21 12:23:07 PM PDT 24 Mar 21 12:23:15 PM PDT 24 1519170000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1013392939 Mar 21 12:22:53 PM PDT 24 Mar 21 12:23:01 PM PDT 24 1592230000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.101534185 Mar 21 12:16:33 PM PDT 24 Mar 21 12:16:42 PM PDT 24 1396530000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.325683411
Short name T13
Test name
Test status
Simulation time 1414130000 ps
CPU time 4.74 seconds
Started Mar 21 12:22:32 PM PDT 24
Finished Mar 21 12:22:43 PM PDT 24
Peak memory 163060 kb
Host smart-87e6a4e1-a187-49fa-b2a7-0a73098d8b55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=325683411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.325683411
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.74473736
Short name T17
Test name
Test status
Simulation time 336526310000 ps
CPU time 904.47 seconds
Started Mar 21 12:37:36 PM PDT 24
Finished Mar 21 01:15:39 PM PDT 24
Peak memory 160636 kb
Host smart-40d76a90-214f-4527-a82f-9edb8ba86ef8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=74473736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.74473736
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3191840143
Short name T25
Test name
Test status
Simulation time 336995870000 ps
CPU time 769.6 seconds
Started Mar 21 12:20:16 PM PDT 24
Finished Mar 21 12:51:21 PM PDT 24
Peak memory 160716 kb
Host smart-47b9add9-3f4f-41ea-b4e2-32585c3c9196
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3191840143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3191840143
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4044816283
Short name T137
Test name
Test status
Simulation time 337014850000 ps
CPU time 930.8 seconds
Started Mar 21 12:19:47 PM PDT 24
Finished Mar 21 12:57:26 PM PDT 24
Peak memory 160704 kb
Host smart-75de7230-ab0e-47ca-beca-5da107cd649e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4044816283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4044816283
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3979982879
Short name T131
Test name
Test status
Simulation time 336353330000 ps
CPU time 619.14 seconds
Started Mar 21 12:16:24 PM PDT 24
Finished Mar 21 12:42:17 PM PDT 24
Peak memory 161028 kb
Host smart-3561ff9c-9e4a-4d3e-9d49-b22ead7ad552
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3979982879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3979982879
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3657493931
Short name T29
Test name
Test status
Simulation time 336374310000 ps
CPU time 615.5 seconds
Started Mar 21 12:17:08 PM PDT 24
Finished Mar 21 12:43:06 PM PDT 24
Peak memory 161028 kb
Host smart-20e3c925-757c-4065-8d19-d7f9f2803291
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3657493931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3657493931
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.104648652
Short name T147
Test name
Test status
Simulation time 336315270000 ps
CPU time 618.81 seconds
Started Mar 21 12:16:23 PM PDT 24
Finished Mar 21 12:42:21 PM PDT 24
Peak memory 161028 kb
Host smart-d7293f22-28df-4943-b164-e788067f0688
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=104648652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.104648652
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.399406009
Short name T128
Test name
Test status
Simulation time 336445330000 ps
CPU time 685.09 seconds
Started Mar 21 12:16:33 PM PDT 24
Finished Mar 21 12:44:18 PM PDT 24
Peak memory 160508 kb
Host smart-6115d791-d370-454e-adc5-55ca1de9b3c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399406009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.399406009
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1691405619
Short name T30
Test name
Test status
Simulation time 336529110000 ps
CPU time 830.44 seconds
Started Mar 21 12:17:34 PM PDT 24
Finished Mar 21 12:51:32 PM PDT 24
Peak memory 160684 kb
Host smart-6bb0c1a5-6e8f-4e35-883a-8703f0194a47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1691405619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1691405619
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.555143314
Short name T27
Test name
Test status
Simulation time 337011990000 ps
CPU time 797.33 seconds
Started Mar 21 12:16:30 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 160752 kb
Host smart-3a2a6407-a5a9-4a55-a26e-359e55a9f79e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=555143314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.555143314
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2292028358
Short name T121
Test name
Test status
Simulation time 336473830000 ps
CPU time 604.12 seconds
Started Mar 21 12:22:23 PM PDT 24
Finished Mar 21 12:47:11 PM PDT 24
Peak memory 160224 kb
Host smart-81bd283a-3e1e-423c-a864-b799202a58b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292028358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2292028358
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2350918492
Short name T126
Test name
Test status
Simulation time 336473890000 ps
CPU time 1012.53 seconds
Started Mar 21 12:16:34 PM PDT 24
Finished Mar 21 12:59:05 PM PDT 24
Peak memory 160892 kb
Host smart-2a69ecc9-0ad5-426b-8eb6-081a1a23e661
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2350918492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2350918492
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2784678686
Short name T117
Test name
Test status
Simulation time 336907510000 ps
CPU time 1002.91 seconds
Started Mar 21 12:16:34 PM PDT 24
Finished Mar 21 12:59:10 PM PDT 24
Peak memory 160892 kb
Host smart-16df8416-8004-485d-b324-19c67d14f115
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2784678686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2784678686
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2760502065
Short name T116
Test name
Test status
Simulation time 336711250000 ps
CPU time 741.72 seconds
Started Mar 21 12:23:29 PM PDT 24
Finished Mar 21 12:54:15 PM PDT 24
Peak memory 160224 kb
Host smart-32c68cef-8243-40e3-8d52-433ae5d2ff2a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2760502065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2760502065
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2295447651
Short name T115
Test name
Test status
Simulation time 337073990000 ps
CPU time 641.11 seconds
Started Mar 21 12:23:07 PM PDT 24
Finished Mar 21 12:49:33 PM PDT 24
Peak memory 160444 kb
Host smart-76204fbc-cf96-48da-b188-2003c064b0e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2295447651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2295447651
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3166042849
Short name T149
Test name
Test status
Simulation time 336508350000 ps
CPU time 1000.54 seconds
Started Mar 21 12:16:35 PM PDT 24
Finished Mar 21 12:59:01 PM PDT 24
Peak memory 160892 kb
Host smart-e64d78fc-6774-42e1-b1c4-8590b21e1ca8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3166042849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3166042849
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.271067605
Short name T6
Test name
Test status
Simulation time 336716990000 ps
CPU time 773.19 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:54:11 PM PDT 24
Peak memory 158276 kb
Host smart-d14e0af9-8543-4e3e-84cc-7fb8d23cfc63
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=271067605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.271067605
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3236527523
Short name T142
Test name
Test status
Simulation time 336713590000 ps
CPU time 1011.59 seconds
Started Mar 21 12:18:15 PM PDT 24
Finished Mar 21 01:00:37 PM PDT 24
Peak memory 160892 kb
Host smart-9954dc5f-e235-4c2d-b4e9-9463ceda36e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3236527523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3236527523
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1922452689
Short name T129
Test name
Test status
Simulation time 336681030000 ps
CPU time 771.97 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:54:18 PM PDT 24
Peak memory 158424 kb
Host smart-d9f6d8d4-40ae-4882-bb1c-1ce4825db8be
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1922452689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1922452689
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3611452729
Short name T120
Test name
Test status
Simulation time 336617730000 ps
CPU time 666.76 seconds
Started Mar 21 12:21:28 PM PDT 24
Finished Mar 21 12:49:08 PM PDT 24
Peak memory 159300 kb
Host smart-3e314cd6-c698-4b71-886f-36b68e8c3122
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3611452729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3611452729
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.334869830
Short name T124
Test name
Test status
Simulation time 336886710000 ps
CPU time 804.5 seconds
Started Mar 21 12:18:21 PM PDT 24
Finished Mar 21 12:50:51 PM PDT 24
Peak memory 160796 kb
Host smart-823beee6-8c9d-4293-ba11-0abf9b5aebe3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=334869830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.334869830
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2636932986
Short name T112
Test name
Test status
Simulation time 336936450000 ps
CPU time 1009.29 seconds
Started Mar 21 12:17:28 PM PDT 24
Finished Mar 21 12:59:53 PM PDT 24
Peak memory 160892 kb
Host smart-896ab242-a030-46dd-a253-118283fe5f64
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2636932986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2636932986
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1211988645
Short name T138
Test name
Test status
Simulation time 336450110000 ps
CPU time 654.53 seconds
Started Mar 21 12:22:59 PM PDT 24
Finished Mar 21 12:49:50 PM PDT 24
Peak memory 159736 kb
Host smart-a0ed3861-eb7a-4f99-8ce9-507cc10ebedc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1211988645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1211988645
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1636373616
Short name T28
Test name
Test status
Simulation time 336366510000 ps
CPU time 640.95 seconds
Started Mar 21 12:23:27 PM PDT 24
Finished Mar 21 12:50:14 PM PDT 24
Peak memory 159736 kb
Host smart-01b786fc-cabb-4908-b915-b4bfd95e1ffb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1636373616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1636373616
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1482123687
Short name T139
Test name
Test status
Simulation time 336649450000 ps
CPU time 670.37 seconds
Started Mar 21 12:23:03 PM PDT 24
Finished Mar 21 12:50:43 PM PDT 24
Peak memory 160232 kb
Host smart-ce1c0813-7b87-4e33-bf9b-649cf9823828
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1482123687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1482123687
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1604800115
Short name T134
Test name
Test status
Simulation time 336533310000 ps
CPU time 595.79 seconds
Started Mar 21 12:23:00 PM PDT 24
Finished Mar 21 12:47:17 PM PDT 24
Peak memory 159208 kb
Host smart-236dce63-f2d9-4aaa-b059-7006d76a95b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1604800115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1604800115
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4262606557
Short name T143
Test name
Test status
Simulation time 336946350000 ps
CPU time 737.56 seconds
Started Mar 21 12:23:30 PM PDT 24
Finished Mar 21 12:53:59 PM PDT 24
Peak memory 160220 kb
Host smart-95b9dccc-401a-4069-ab15-98662d61322b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4262606557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4262606557
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2172079520
Short name T122
Test name
Test status
Simulation time 337024110000 ps
CPU time 736.97 seconds
Started Mar 21 12:23:20 PM PDT 24
Finished Mar 21 12:53:51 PM PDT 24
Peak memory 159252 kb
Host smart-fe0ebddd-e35a-4098-a81b-4e42dc6e9317
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2172079520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2172079520
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.215633326
Short name T119
Test name
Test status
Simulation time 336574730000 ps
CPU time 888.02 seconds
Started Mar 21 12:19:33 PM PDT 24
Finished Mar 21 12:55:52 PM PDT 24
Peak memory 160700 kb
Host smart-bfff2dbf-84fd-4acc-9800-fe4d37206505
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=215633326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.215633326
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1649932398
Short name T114
Test name
Test status
Simulation time 336556650000 ps
CPU time 740.64 seconds
Started Mar 21 12:23:29 PM PDT 24
Finished Mar 21 12:54:08 PM PDT 24
Peak memory 160224 kb
Host smart-e243ea44-c7f4-4a4f-8747-a25b3f824336
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1649932398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1649932398
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2652926141
Short name T135
Test name
Test status
Simulation time 336388610000 ps
CPU time 682.48 seconds
Started Mar 21 12:23:58 PM PDT 24
Finished Mar 21 12:52:22 PM PDT 24
Peak memory 159488 kb
Host smart-dfe97237-2f0a-43d5-a931-e45f8b032e57
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2652926141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2652926141
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.690715144
Short name T148
Test name
Test status
Simulation time 336321670000 ps
CPU time 743.46 seconds
Started Mar 21 12:23:29 PM PDT 24
Finished Mar 21 12:54:17 PM PDT 24
Peak memory 160212 kb
Host smart-57e6ba0b-d5a7-437b-bd3f-8e4108a97d08
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=690715144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.690715144
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.325232749
Short name T111
Test name
Test status
Simulation time 336531250000 ps
CPU time 727.12 seconds
Started Mar 21 12:23:20 PM PDT 24
Finished Mar 21 12:53:28 PM PDT 24
Peak memory 159304 kb
Host smart-94a203e4-2957-41d8-905f-433dab0cc0f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=325232749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.325232749
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1976901643
Short name T140
Test name
Test status
Simulation time 336393790000 ps
CPU time 654.25 seconds
Started Mar 21 12:22:36 PM PDT 24
Finished Mar 21 12:49:42 PM PDT 24
Peak memory 159780 kb
Host smart-2f79860d-34c1-414b-90c3-beb396ceeba5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976901643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1976901643
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2653159766
Short name T141
Test name
Test status
Simulation time 336630750000 ps
CPU time 742.97 seconds
Started Mar 21 12:22:51 PM PDT 24
Finished Mar 21 12:53:12 PM PDT 24
Peak memory 160448 kb
Host smart-3c2e0de0-1340-4d51-92b2-2c9eb08edee7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2653159766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2653159766
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2711590344
Short name T150
Test name
Test status
Simulation time 336543110000 ps
CPU time 553.79 seconds
Started Mar 21 12:22:18 PM PDT 24
Finished Mar 21 12:45:24 PM PDT 24
Peak memory 159496 kb
Host smart-f7fbd651-0d22-4430-9e43-4194c9863dff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2711590344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2711590344
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1100127139
Short name T136
Test name
Test status
Simulation time 337120910000 ps
CPU time 675.99 seconds
Started Mar 21 12:21:29 PM PDT 24
Finished Mar 21 12:49:19 PM PDT 24
Peak memory 159420 kb
Host smart-744ceb51-01ff-412b-8120-428e6f11bcbe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1100127139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1100127139
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1219348976
Short name T146
Test name
Test status
Simulation time 336714730000 ps
CPU time 837.84 seconds
Started Mar 21 12:21:41 PM PDT 24
Finished Mar 21 12:56:10 PM PDT 24
Peak memory 159544 kb
Host smart-06a13fa5-29cc-4da4-818e-28b0e7be8f9e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219348976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1219348976
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3128953016
Short name T24
Test name
Test status
Simulation time 336818310000 ps
CPU time 665.17 seconds
Started Mar 21 12:23:14 PM PDT 24
Finished Mar 21 12:51:10 PM PDT 24
Peak memory 160224 kb
Host smart-15097600-edd9-4671-8501-a69aed010a89
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3128953016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3128953016
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2772858410
Short name T123
Test name
Test status
Simulation time 336675670000 ps
CPU time 785.77 seconds
Started Mar 21 12:17:32 PM PDT 24
Finished Mar 21 12:49:03 PM PDT 24
Peak memory 160688 kb
Host smart-99bc9e9c-7ba0-4a42-ad5e-9b4fc64ca58e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2772858410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2772858410
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1106893568
Short name T133
Test name
Test status
Simulation time 337074910000 ps
CPU time 841.29 seconds
Started Mar 21 12:21:42 PM PDT 24
Finished Mar 21 12:56:08 PM PDT 24
Peak memory 159568 kb
Host smart-c7cba2c3-2a36-476b-90cf-81eabb10aec1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1106893568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1106893568
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3195771044
Short name T113
Test name
Test status
Simulation time 336394570000 ps
CPU time 665.41 seconds
Started Mar 21 12:23:14 PM PDT 24
Finished Mar 21 12:51:13 PM PDT 24
Peak memory 160224 kb
Host smart-1f76e1c0-27e9-4a42-aef9-6dc7c5eeed45
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3195771044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3195771044
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.513996037
Short name T118
Test name
Test status
Simulation time 337041790000 ps
CPU time 681.73 seconds
Started Mar 21 12:22:24 PM PDT 24
Finished Mar 21 12:50:05 PM PDT 24
Peak memory 159216 kb
Host smart-31b7272e-5024-4266-bfc5-b49336c8f4ff
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=513996037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.513996037
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3546250304
Short name T127
Test name
Test status
Simulation time 336366010000 ps
CPU time 1017.48 seconds
Started Mar 21 12:18:22 PM PDT 24
Finished Mar 21 01:00:53 PM PDT 24
Peak memory 160892 kb
Host smart-f8d83b41-46da-4418-b86f-57310449bc32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3546250304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3546250304
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.803592155
Short name T144
Test name
Test status
Simulation time 336395730000 ps
CPU time 670.67 seconds
Started Mar 21 12:23:07 PM PDT 24
Finished Mar 21 12:51:01 PM PDT 24
Peak memory 159724 kb
Host smart-203ac298-a409-430f-9cd1-4b214268c04c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=803592155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.803592155
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2253005470
Short name T130
Test name
Test status
Simulation time 336939610000 ps
CPU time 680.39 seconds
Started Mar 21 12:22:24 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 159236 kb
Host smart-0201d148-880a-4cb4-a484-65d6ef042c15
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2253005470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2253005470
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4116817859
Short name T5
Test name
Test status
Simulation time 337076790000 ps
CPU time 718.2 seconds
Started Mar 21 12:26:08 PM PDT 24
Finished Mar 21 12:55:53 PM PDT 24
Peak memory 159736 kb
Host smart-f3062f7f-bf53-489e-bb22-25843898047b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4116817859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4116817859
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.352836447
Short name T125
Test name
Test status
Simulation time 336584110000 ps
CPU time 717.36 seconds
Started Mar 21 12:21:48 PM PDT 24
Finished Mar 21 12:51:40 PM PDT 24
Peak memory 159208 kb
Host smart-12bb3e05-eee6-4b99-806a-e511ff673b1f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=352836447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.352836447
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2473592376
Short name T26
Test name
Test status
Simulation time 337045010000 ps
CPU time 717.96 seconds
Started Mar 21 12:20:04 PM PDT 24
Finished Mar 21 12:49:14 PM PDT 24
Peak memory 160696 kb
Host smart-05072180-c821-4394-8588-93e9d87bacfc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2473592376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2473592376
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1742556595
Short name T145
Test name
Test status
Simulation time 336480590000 ps
CPU time 708.03 seconds
Started Mar 21 12:21:48 PM PDT 24
Finished Mar 21 12:51:13 PM PDT 24
Peak memory 158748 kb
Host smart-865970c9-d260-43e2-9075-0aa8e8620e50
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1742556595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1742556595
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1866877678
Short name T132
Test name
Test status
Simulation time 336877210000 ps
CPU time 706.64 seconds
Started Mar 21 12:21:48 PM PDT 24
Finished Mar 21 12:51:12 PM PDT 24
Peak memory 158792 kb
Host smart-cf66e764-d67c-45c4-97ed-298a214bc3a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1866877678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1866877678
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2820196275
Short name T4
Test name
Test status
Simulation time 336639110000 ps
CPU time 795.16 seconds
Started Mar 21 12:16:31 PM PDT 24
Finished Mar 21 12:48:44 PM PDT 24
Peak memory 160760 kb
Host smart-927bd722-9c86-4896-b397-5e0b22f754d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2820196275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2820196275
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.76898527
Short name T75
Test name
Test status
Simulation time 337064130000 ps
CPU time 902.6 seconds
Started Mar 21 12:37:40 PM PDT 24
Finished Mar 21 01:15:37 PM PDT 24
Peak memory 160636 kb
Host smart-92658636-526f-4373-8b10-f24e7e735358
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=76898527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.76898527
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3823290029
Short name T78
Test name
Test status
Simulation time 336882310000 ps
CPU time 729.08 seconds
Started Mar 21 12:37:13 PM PDT 24
Finished Mar 21 01:07:24 PM PDT 24
Peak memory 160656 kb
Host smart-db82cdf6-3eb0-4288-8572-8768656dd383
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3823290029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3823290029
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2997532889
Short name T95
Test name
Test status
Simulation time 336996090000 ps
CPU time 1020.52 seconds
Started Mar 21 12:37:30 PM PDT 24
Finished Mar 21 01:20:38 PM PDT 24
Peak memory 160580 kb
Host smart-93132777-94ca-4e01-ad39-80887a21ac6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2997532889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2997532889
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3284277693
Short name T90
Test name
Test status
Simulation time 336696030000 ps
CPU time 1012.66 seconds
Started Mar 21 12:37:26 PM PDT 24
Finished Mar 21 01:19:46 PM PDT 24
Peak memory 160580 kb
Host smart-41c83554-da89-49c0-bfc2-d81f1eebee43
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3284277693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3284277693
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1010237099
Short name T16
Test name
Test status
Simulation time 336872010000 ps
CPU time 921.11 seconds
Started Mar 21 12:37:22 PM PDT 24
Finished Mar 21 01:14:52 PM PDT 24
Peak memory 160788 kb
Host smart-caece5c3-3020-4dae-b29e-20b6bf0ed6da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1010237099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1010237099
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2631456810
Short name T88
Test name
Test status
Simulation time 336509930000 ps
CPU time 754.32 seconds
Started Mar 21 12:37:35 PM PDT 24
Finished Mar 21 01:08:42 PM PDT 24
Peak memory 160656 kb
Host smart-96060886-8055-415c-ac3d-06046a43266d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2631456810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2631456810
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3812243204
Short name T97
Test name
Test status
Simulation time 336777330000 ps
CPU time 1013.14 seconds
Started Mar 21 12:37:34 PM PDT 24
Finished Mar 21 01:20:21 PM PDT 24
Peak memory 160580 kb
Host smart-4f0aefb6-77ab-4123-ae26-1a6dcad927c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3812243204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3812243204
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3952768801
Short name T81
Test name
Test status
Simulation time 336598670000 ps
CPU time 789.08 seconds
Started Mar 21 12:37:18 PM PDT 24
Finished Mar 21 01:09:29 PM PDT 24
Peak memory 160604 kb
Host smart-7b578b26-da10-4f63-9a1b-b59d2c73bd4c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3952768801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3952768801
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2192368549
Short name T92
Test name
Test status
Simulation time 336511990000 ps
CPU time 791.55 seconds
Started Mar 21 12:37:44 PM PDT 24
Finished Mar 21 01:09:57 PM PDT 24
Peak memory 160568 kb
Host smart-0ec15bac-2ab2-4dc8-8b97-58411b086ad4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2192368549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2192368549
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3271813750
Short name T101
Test name
Test status
Simulation time 336608210000 ps
CPU time 1002.81 seconds
Started Mar 21 12:37:18 PM PDT 24
Finished Mar 21 01:18:45 PM PDT 24
Peak memory 160652 kb
Host smart-2b9b9207-bf95-4e93-8b4c-55483a3c7c91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3271813750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3271813750
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1065800382
Short name T83
Test name
Test status
Simulation time 336475030000 ps
CPU time 898.03 seconds
Started Mar 21 12:37:21 PM PDT 24
Finished Mar 21 01:14:20 PM PDT 24
Peak memory 160608 kb
Host smart-dbc51e59-cd98-4a6e-b591-5ff67d96e38e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1065800382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1065800382
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2257571094
Short name T77
Test name
Test status
Simulation time 336774910000 ps
CPU time 718.93 seconds
Started Mar 21 12:37:41 PM PDT 24
Finished Mar 21 01:07:28 PM PDT 24
Peak memory 160656 kb
Host smart-becea9f9-61f7-4284-b882-3deb0c949cd3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2257571094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2257571094
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.71670292
Short name T102
Test name
Test status
Simulation time 336447890000 ps
CPU time 753.2 seconds
Started Mar 21 12:37:23 PM PDT 24
Finished Mar 21 01:08:04 PM PDT 24
Peak memory 160668 kb
Host smart-9db1d093-cd30-40c1-94cb-526430f402f6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=71670292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.71670292
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4033699010
Short name T73
Test name
Test status
Simulation time 336897430000 ps
CPU time 1010.89 seconds
Started Mar 21 12:37:28 PM PDT 24
Finished Mar 21 01:18:30 PM PDT 24
Peak memory 160652 kb
Host smart-05be0341-18be-4f1c-9414-a9a69402da8f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4033699010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4033699010
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2249503041
Short name T79
Test name
Test status
Simulation time 336821930000 ps
CPU time 908.38 seconds
Started Mar 21 12:37:21 PM PDT 24
Finished Mar 21 01:14:54 PM PDT 24
Peak memory 160600 kb
Host smart-ef5d3035-cde4-4a85-949a-3d9855d22235
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2249503041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2249503041
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4201807827
Short name T14
Test name
Test status
Simulation time 336855770000 ps
CPU time 923.93 seconds
Started Mar 21 12:37:25 PM PDT 24
Finished Mar 21 01:15:25 PM PDT 24
Peak memory 160608 kb
Host smart-26663652-47b7-4e42-b416-fee6df815d15
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4201807827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.4201807827
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.118608183
Short name T106
Test name
Test status
Simulation time 336917070000 ps
CPU time 1013.28 seconds
Started Mar 21 12:37:14 PM PDT 24
Finished Mar 21 01:18:49 PM PDT 24
Peak memory 160648 kb
Host smart-4463c257-6883-4b3c-934d-f1b8d315b794
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=118608183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.118608183
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1531773310
Short name T85
Test name
Test status
Simulation time 336847210000 ps
CPU time 1010.57 seconds
Started Mar 21 12:37:17 PM PDT 24
Finished Mar 21 01:18:43 PM PDT 24
Peak memory 160652 kb
Host smart-1ed237bf-fa7b-4157-a61c-e14a31d351aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1531773310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1531773310
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.928128449
Short name T89
Test name
Test status
Simulation time 336923390000 ps
CPU time 811.36 seconds
Started Mar 21 12:37:21 PM PDT 24
Finished Mar 21 01:10:20 PM PDT 24
Peak memory 160832 kb
Host smart-68fb6eef-5694-43aa-b741-ddc5290347c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=928128449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.928128449
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2139694853
Short name T108
Test name
Test status
Simulation time 337159370000 ps
CPU time 754.67 seconds
Started Mar 21 12:37:16 PM PDT 24
Finished Mar 21 01:08:18 PM PDT 24
Peak memory 160632 kb
Host smart-0d77cac1-761e-4ab5-92ed-8564ff6c9443
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2139694853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2139694853
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1861413145
Short name T23
Test name
Test status
Simulation time 337076070000 ps
CPU time 849.69 seconds
Started Mar 21 12:37:30 PM PDT 24
Finished Mar 21 01:12:48 PM PDT 24
Peak memory 160656 kb
Host smart-175bbaaa-377c-421c-a724-a9bda3b5bfea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1861413145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1861413145
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2040690647
Short name T84
Test name
Test status
Simulation time 337059310000 ps
CPU time 996.28 seconds
Started Mar 21 12:37:32 PM PDT 24
Finished Mar 21 01:19:32 PM PDT 24
Peak memory 160604 kb
Host smart-dd5ef3a3-a375-48fe-9c1f-b55599007fa6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2040690647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2040690647
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.487596405
Short name T80
Test name
Test status
Simulation time 336384690000 ps
CPU time 757.9 seconds
Started Mar 21 12:37:36 PM PDT 24
Finished Mar 21 01:08:55 PM PDT 24
Peak memory 160656 kb
Host smart-11508b75-e155-4720-a232-8aaf25e2d849
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=487596405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.487596405
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1185317839
Short name T74
Test name
Test status
Simulation time 336920750000 ps
CPU time 845.85 seconds
Started Mar 21 12:37:29 PM PDT 24
Finished Mar 21 01:12:41 PM PDT 24
Peak memory 160656 kb
Host smart-7ae7718a-85ee-4900-8e30-436f9427e770
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1185317839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1185317839
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2085955442
Short name T109
Test name
Test status
Simulation time 336386810000 ps
CPU time 784.97 seconds
Started Mar 21 12:37:19 PM PDT 24
Finished Mar 21 01:09:39 PM PDT 24
Peak memory 160660 kb
Host smart-715dd102-3d41-47bd-8c0d-9585358b4dad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2085955442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2085955442
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.993178584
Short name T21
Test name
Test status
Simulation time 336682370000 ps
CPU time 996.13 seconds
Started Mar 21 12:37:17 PM PDT 24
Finished Mar 21 01:18:54 PM PDT 24
Peak memory 160592 kb
Host smart-191a715e-9444-4ca0-a120-e3e5915382de
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=993178584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.993178584
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1777794809
Short name T20
Test name
Test status
Simulation time 336795070000 ps
CPU time 843.35 seconds
Started Mar 21 12:37:26 PM PDT 24
Finished Mar 21 01:12:25 PM PDT 24
Peak memory 160656 kb
Host smart-20c81de6-59d0-4bbf-b337-e1bf7568bc16
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1777794809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1777794809
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2568734945
Short name T71
Test name
Test status
Simulation time 337027230000 ps
CPU time 739.28 seconds
Started Mar 21 12:37:11 PM PDT 24
Finished Mar 21 01:07:02 PM PDT 24
Peak memory 160592 kb
Host smart-078caa8c-d774-4e91-a919-055918b67bf1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2568734945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2568734945
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3541562288
Short name T105
Test name
Test status
Simulation time 336812970000 ps
CPU time 762.85 seconds
Started Mar 21 12:37:38 PM PDT 24
Finished Mar 21 01:08:59 PM PDT 24
Peak memory 160660 kb
Host smart-8588125d-1493-44b0-9545-3bd2c83bf167
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3541562288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3541562288
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4090028460
Short name T99
Test name
Test status
Simulation time 336971970000 ps
CPU time 542.27 seconds
Started Mar 21 12:37:27 PM PDT 24
Finished Mar 21 01:00:47 PM PDT 24
Peak memory 161032 kb
Host smart-dd75be02-dfd5-41c5-9c8a-ebe55b191139
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4090028460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.4090028460
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.150289217
Short name T91
Test name
Test status
Simulation time 336640810000 ps
CPU time 692.52 seconds
Started Mar 21 12:37:22 PM PDT 24
Finished Mar 21 01:05:32 PM PDT 24
Peak memory 160620 kb
Host smart-06191ac4-ae3e-4ed6-bb59-b24c786e8a4a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=150289217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.150289217
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3824545792
Short name T104
Test name
Test status
Simulation time 336692110000 ps
CPU time 780.67 seconds
Started Mar 21 12:37:31 PM PDT 24
Finished Mar 21 01:09:46 PM PDT 24
Peak memory 160668 kb
Host smart-d93464c4-f52c-46b6-a1f5-db89cc628fc9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3824545792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3824545792
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1941813873
Short name T86
Test name
Test status
Simulation time 336778610000 ps
CPU time 788.19 seconds
Started Mar 21 12:37:19 PM PDT 24
Finished Mar 21 01:08:53 PM PDT 24
Peak memory 160760 kb
Host smart-82f8c98c-f0a2-4e0a-b2b6-b73aefa8f632
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1941813873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1941813873
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.384273138
Short name T18
Test name
Test status
Simulation time 336780430000 ps
CPU time 744.39 seconds
Started Mar 21 12:37:36 PM PDT 24
Finished Mar 21 01:08:36 PM PDT 24
Peak memory 160656 kb
Host smart-190bf30b-526d-4b43-b6af-bafcc29c27dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=384273138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.384273138
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2703813339
Short name T82
Test name
Test status
Simulation time 336816470000 ps
CPU time 790.51 seconds
Started Mar 21 12:37:37 PM PDT 24
Finished Mar 21 01:10:12 PM PDT 24
Peak memory 160668 kb
Host smart-9fda1db6-1ef3-4b84-8c22-fde999bbee44
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2703813339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2703813339
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2719836746
Short name T100
Test name
Test status
Simulation time 336407770000 ps
CPU time 768.4 seconds
Started Mar 21 12:37:32 PM PDT 24
Finished Mar 21 01:09:22 PM PDT 24
Peak memory 160668 kb
Host smart-2647560a-a0b3-4f6c-9e20-04b0d4be499f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2719836746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2719836746
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2282797065
Short name T19
Test name
Test status
Simulation time 336454470000 ps
CPU time 782.15 seconds
Started Mar 21 12:37:37 PM PDT 24
Finished Mar 21 01:09:34 PM PDT 24
Peak memory 160668 kb
Host smart-54ff0a59-2259-4534-b037-b4355ab5c57c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2282797065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2282797065
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2997757176
Short name T76
Test name
Test status
Simulation time 336671510000 ps
CPU time 892.96 seconds
Started Mar 21 12:37:13 PM PDT 24
Finished Mar 21 01:14:38 PM PDT 24
Peak memory 160644 kb
Host smart-294d6748-3f5f-44d4-9c2c-a4404712aa98
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2997757176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2997757176
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1857799454
Short name T93
Test name
Test status
Simulation time 336807010000 ps
CPU time 668.32 seconds
Started Mar 21 12:37:53 PM PDT 24
Finished Mar 21 01:05:53 PM PDT 24
Peak memory 160660 kb
Host smart-a7eca94e-5cb3-4eb4-b227-66cd51bba57e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1857799454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1857799454
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3043866
Short name T22
Test name
Test status
Simulation time 337074110000 ps
CPU time 999.33 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 01:19:34 PM PDT 24
Peak memory 160592 kb
Host smart-af8d8543-76e0-45c9-8907-5fef4a747902
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3043866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3043866
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1448669897
Short name T96
Test name
Test status
Simulation time 336537790000 ps
CPU time 739.37 seconds
Started Mar 21 12:37:43 PM PDT 24
Finished Mar 21 01:08:05 PM PDT 24
Peak memory 160664 kb
Host smart-0f290abe-9634-4dee-8020-292b3631d449
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1448669897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1448669897
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.815017349
Short name T107
Test name
Test status
Simulation time 336579610000 ps
CPU time 717.65 seconds
Started Mar 21 12:37:21 PM PDT 24
Finished Mar 21 01:06:39 PM PDT 24
Peak memory 160604 kb
Host smart-62892941-b75a-4e23-91b9-e815c92d7112
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=815017349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.815017349
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.171549135
Short name T15
Test name
Test status
Simulation time 336482210000 ps
CPU time 807.33 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 01:10:27 PM PDT 24
Peak memory 160832 kb
Host smart-a4d7e24b-0747-4236-a4fa-dab37e2cae0f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=171549135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.171549135
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3098077086
Short name T98
Test name
Test status
Simulation time 336753290000 ps
CPU time 771.63 seconds
Started Mar 21 12:37:48 PM PDT 24
Finished Mar 21 01:09:35 PM PDT 24
Peak memory 160656 kb
Host smart-8c318273-6cc9-4531-9340-783f9786fe1d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3098077086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3098077086
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3090015437
Short name T103
Test name
Test status
Simulation time 336737490000 ps
CPU time 735.79 seconds
Started Mar 21 12:37:11 PM PDT 24
Finished Mar 21 01:07:15 PM PDT 24
Peak memory 160616 kb
Host smart-a1afb660-1278-4270-995e-959ba53bd099
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3090015437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3090015437
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3790911238
Short name T110
Test name
Test status
Simulation time 336938830000 ps
CPU time 624.14 seconds
Started Mar 21 12:37:39 PM PDT 24
Finished Mar 21 01:03:54 PM PDT 24
Peak memory 160648 kb
Host smart-7e7d179e-5831-4384-bbc3-7a547503b659
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3790911238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3790911238
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.892997319
Short name T72
Test name
Test status
Simulation time 336413650000 ps
CPU time 907.09 seconds
Started Mar 21 12:37:22 PM PDT 24
Finished Mar 21 01:14:48 PM PDT 24
Peak memory 160784 kb
Host smart-93a1e720-2e33-4206-aeb5-d48c6e17a002
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=892997319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.892997319
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4264823682
Short name T87
Test name
Test status
Simulation time 336577230000 ps
CPU time 1012.78 seconds
Started Mar 21 12:37:45 PM PDT 24
Finished Mar 21 01:20:34 PM PDT 24
Peak memory 160576 kb
Host smart-8bedbd1d-be11-4b99-ac06-44d3eafe7afb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4264823682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.4264823682
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3218016468
Short name T94
Test name
Test status
Simulation time 336313330000 ps
CPU time 990.04 seconds
Started Mar 21 12:37:27 PM PDT 24
Finished Mar 21 01:19:20 PM PDT 24
Peak memory 160596 kb
Host smart-f03e8cf9-b9a9-4080-81b8-b7d0d15b1e80
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3218016468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3218016468
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.351854105
Short name T176
Test name
Test status
Simulation time 1250030000 ps
CPU time 3.21 seconds
Started Mar 21 12:22:53 PM PDT 24
Finished Mar 21 12:23:00 PM PDT 24
Peak memory 164464 kb
Host smart-4aa4049f-72c8-4d97-9228-0382fcc89e46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351854105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.351854105
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1229571732
Short name T159
Test name
Test status
Simulation time 1528350000 ps
CPU time 3.42 seconds
Started Mar 21 12:22:26 PM PDT 24
Finished Mar 21 12:22:34 PM PDT 24
Peak memory 164272 kb
Host smart-f7acfe02-dbb8-46d5-89b8-457b2189c6fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1229571732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1229571732
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1600040616
Short name T153
Test name
Test status
Simulation time 1399930000 ps
CPU time 3.54 seconds
Started Mar 21 12:23:00 PM PDT 24
Finished Mar 21 12:23:08 PM PDT 24
Peak memory 163892 kb
Host smart-d1361af2-0cdf-499a-af85-f9775b3ddcf8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1600040616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1600040616
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1554239006
Short name T175
Test name
Test status
Simulation time 1179170000 ps
CPU time 5.12 seconds
Started Mar 21 12:18:48 PM PDT 24
Finished Mar 21 12:18:59 PM PDT 24
Peak memory 164828 kb
Host smart-fec9e3b9-19eb-49e3-a2c5-924ab8ef7e99
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1554239006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1554239006
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4076173850
Short name T185
Test name
Test status
Simulation time 1250990000 ps
CPU time 5.35 seconds
Started Mar 21 12:18:47 PM PDT 24
Finished Mar 21 12:18:59 PM PDT 24
Peak memory 164828 kb
Host smart-385a2cde-5df9-41a4-a5dc-15bf2dc859e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4076173850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.4076173850
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.514904385
Short name T198
Test name
Test status
Simulation time 1519170000 ps
CPU time 3.53 seconds
Started Mar 21 12:23:07 PM PDT 24
Finished Mar 21 12:23:15 PM PDT 24
Peak memory 164476 kb
Host smart-be48c1b6-fe59-468c-9288-c1ad6fec06e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=514904385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.514904385
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3040015039
Short name T172
Test name
Test status
Simulation time 1381150000 ps
CPU time 3.29 seconds
Started Mar 21 12:21:36 PM PDT 24
Finished Mar 21 12:21:46 PM PDT 24
Peak memory 164312 kb
Host smart-fb0734f3-e07b-4b7c-9e69-c3e843537c68
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3040015039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3040015039
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.382416803
Short name T154
Test name
Test status
Simulation time 1524370000 ps
CPU time 2.94 seconds
Started Mar 21 12:23:08 PM PDT 24
Finished Mar 21 12:23:15 PM PDT 24
Peak memory 164396 kb
Host smart-4b197509-4193-4e8d-adac-8b45e750ab6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=382416803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.382416803
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2433417375
Short name T182
Test name
Test status
Simulation time 1575670000 ps
CPU time 4.1 seconds
Started Mar 21 12:21:37 PM PDT 24
Finished Mar 21 12:21:48 PM PDT 24
Peak memory 164312 kb
Host smart-e11c2ccf-507a-4883-9518-5e48b5717aec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2433417375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2433417375
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2816340481
Short name T179
Test name
Test status
Simulation time 1492050000 ps
CPU time 4.11 seconds
Started Mar 21 12:21:28 PM PDT 24
Finished Mar 21 12:21:37 PM PDT 24
Peak memory 164008 kb
Host smart-ec7cfadb-7982-48e5-a07e-e019622cbd6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816340481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2816340481
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1883320851
Short name T171
Test name
Test status
Simulation time 1146570000 ps
CPU time 3.64 seconds
Started Mar 21 12:21:59 PM PDT 24
Finished Mar 21 12:22:07 PM PDT 24
Peak memory 164896 kb
Host smart-774119a3-a8e5-47b1-bc11-e6a61a5b1650
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1883320851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1883320851
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1447545909
Short name T197
Test name
Test status
Simulation time 1171750000 ps
CPU time 4.59 seconds
Started Mar 21 12:16:33 PM PDT 24
Finished Mar 21 12:16:44 PM PDT 24
Peak memory 165012 kb
Host smart-d00ca086-f62c-427d-8a4b-a9de51c819ba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1447545909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1447545909
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3196457975
Short name T195
Test name
Test status
Simulation time 1276170000 ps
CPU time 4.56 seconds
Started Mar 21 12:22:34 PM PDT 24
Finished Mar 21 12:22:44 PM PDT 24
Peak memory 164332 kb
Host smart-e447e841-938b-4a47-9865-31a8dd0f6f4d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3196457975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3196457975
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4126815878
Short name T158
Test name
Test status
Simulation time 1421850000 ps
CPU time 4.08 seconds
Started Mar 21 12:22:23 PM PDT 24
Finished Mar 21 12:22:32 PM PDT 24
Peak memory 163620 kb
Host smart-4fdc463d-8946-41c4-9fd6-fc3c5116c19e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4126815878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4126815878
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3761945207
Short name T166
Test name
Test status
Simulation time 1350070000 ps
CPU time 4.14 seconds
Started Mar 21 12:16:30 PM PDT 24
Finished Mar 21 12:16:40 PM PDT 24
Peak memory 164872 kb
Host smart-cd8cb47e-0dac-482f-a62b-9b8bed4a9041
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3761945207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3761945207
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.101534185
Short name T200
Test name
Test status
Simulation time 1396530000 ps
CPU time 3.73 seconds
Started Mar 21 12:16:33 PM PDT 24
Finished Mar 21 12:16:42 PM PDT 24
Peak memory 164772 kb
Host smart-1a8e7e72-5879-4a9c-bbc7-135efab57c97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=101534185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.101534185
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.718787467
Short name T193
Test name
Test status
Simulation time 1455790000 ps
CPU time 3.57 seconds
Started Mar 21 12:17:36 PM PDT 24
Finished Mar 21 12:17:44 PM PDT 24
Peak memory 164880 kb
Host smart-5d4f9bc0-415a-44ce-8026-ecbbe5f460f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718787467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.718787467
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2968591873
Short name T164
Test name
Test status
Simulation time 1423270000 ps
CPU time 3.96 seconds
Started Mar 21 12:22:23 PM PDT 24
Finished Mar 21 12:22:32 PM PDT 24
Peak memory 164240 kb
Host smart-a1164c98-690c-42e8-83dc-8659528bd4fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2968591873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2968591873
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.918180013
Short name T192
Test name
Test status
Simulation time 1434630000 ps
CPU time 5.04 seconds
Started Mar 21 12:16:29 PM PDT 24
Finished Mar 21 12:16:41 PM PDT 24
Peak memory 164748 kb
Host smart-277d677f-d377-43d7-bee3-d0714f73fb67
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=918180013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.918180013
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2467349080
Short name T155
Test name
Test status
Simulation time 1535110000 ps
CPU time 3.82 seconds
Started Mar 21 12:16:24 PM PDT 24
Finished Mar 21 12:16:32 PM PDT 24
Peak memory 165160 kb
Host smart-be51c5ae-d296-4f77-a875-4771a9749024
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2467349080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2467349080
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1522436156
Short name T151
Test name
Test status
Simulation time 1243090000 ps
CPU time 4.8 seconds
Started Mar 21 12:16:30 PM PDT 24
Finished Mar 21 12:16:41 PM PDT 24
Peak memory 164856 kb
Host smart-0db53bc5-6fbc-44f1-be2d-793193cdae21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522436156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1522436156
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1049084459
Short name T157
Test name
Test status
Simulation time 1613430000 ps
CPU time 5.9 seconds
Started Mar 21 12:16:34 PM PDT 24
Finished Mar 21 12:16:47 PM PDT 24
Peak memory 165012 kb
Host smart-97301c33-1cc3-4464-bb1c-fe628c96919d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1049084459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1049084459
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.905177841
Short name T194
Test name
Test status
Simulation time 1236030000 ps
CPU time 4.84 seconds
Started Mar 21 12:16:33 PM PDT 24
Finished Mar 21 12:16:44 PM PDT 24
Peak memory 165012 kb
Host smart-6153ad8d-b26a-4df3-bd11-6e01e3715e3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905177841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.905177841
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1831428779
Short name T180
Test name
Test status
Simulation time 1443870000 ps
CPU time 3.31 seconds
Started Mar 21 12:22:26 PM PDT 24
Finished Mar 21 12:22:34 PM PDT 24
Peak memory 164272 kb
Host smart-153a3775-6808-4a83-aed9-08550d3fffc6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831428779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1831428779
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4276902076
Short name T156
Test name
Test status
Simulation time 1493390000 ps
CPU time 3.58 seconds
Started Mar 21 12:17:29 PM PDT 24
Finished Mar 21 12:17:37 PM PDT 24
Peak memory 164824 kb
Host smart-81bd206f-8c6a-4b53-88af-f1e3f717efc4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276902076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.4276902076
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2634118197
Short name T177
Test name
Test status
Simulation time 1114870000 ps
CPU time 3.49 seconds
Started Mar 21 12:17:09 PM PDT 24
Finished Mar 21 12:17:16 PM PDT 24
Peak memory 164672 kb
Host smart-968956c6-1b37-4d80-8e26-6040d687ff64
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634118197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2634118197
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.612451439
Short name T174
Test name
Test status
Simulation time 1549510000 ps
CPU time 3.5 seconds
Started Mar 21 12:17:36 PM PDT 24
Finished Mar 21 12:17:44 PM PDT 24
Peak memory 164884 kb
Host smart-96d93b93-2434-4027-a14a-d7f5fc215b71
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=612451439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.612451439
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1487767833
Short name T169
Test name
Test status
Simulation time 1624990000 ps
CPU time 4.95 seconds
Started Mar 21 12:19:13 PM PDT 24
Finished Mar 21 12:19:24 PM PDT 24
Peak memory 164820 kb
Host smart-8dafa0fe-e534-45cc-b396-5002abb290b0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1487767833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1487767833
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2277857305
Short name T170
Test name
Test status
Simulation time 1505250000 ps
CPU time 4.26 seconds
Started Mar 21 12:22:23 PM PDT 24
Finished Mar 21 12:22:33 PM PDT 24
Peak memory 164212 kb
Host smart-818e4aa3-c2ca-4404-8406-5265e7ceb2b1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2277857305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2277857305
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.4169408789
Short name T184
Test name
Test status
Simulation time 1521570000 ps
CPU time 4.18 seconds
Started Mar 21 12:22:23 PM PDT 24
Finished Mar 21 12:22:33 PM PDT 24
Peak memory 164216 kb
Host smart-790df2c7-8e61-4b03-96b4-b4bf2fe4f5b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4169408789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.4169408789
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2296886849
Short name T152
Test name
Test status
Simulation time 1387550000 ps
CPU time 4.73 seconds
Started Mar 21 12:22:31 PM PDT 24
Finished Mar 21 12:22:42 PM PDT 24
Peak memory 162968 kb
Host smart-0324c86d-39a8-43c4-976e-8a589f6663a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2296886849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2296886849
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3918763897
Short name T165
Test name
Test status
Simulation time 1489050000 ps
CPU time 5.94 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:22:42 PM PDT 24
Peak memory 161432 kb
Host smart-1f0edd3b-ca47-4566-a219-4f41383ea286
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3918763897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3918763897
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2523390829
Short name T196
Test name
Test status
Simulation time 1524370000 ps
CPU time 6.08 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:22:43 PM PDT 24
Peak memory 161484 kb
Host smart-a0c2aaa6-1ca3-42f6-a3ad-0151ffd9f8cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2523390829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2523390829
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.878506570
Short name T183
Test name
Test status
Simulation time 1519750000 ps
CPU time 3.62 seconds
Started Mar 21 12:20:41 PM PDT 24
Finished Mar 21 12:20:49 PM PDT 24
Peak memory 165104 kb
Host smart-5ed4d2af-e6b7-49b6-8887-7971887eab3f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878506570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.878506570
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1013392939
Short name T199
Test name
Test status
Simulation time 1592230000 ps
CPU time 3.72 seconds
Started Mar 21 12:22:53 PM PDT 24
Finished Mar 21 12:23:01 PM PDT 24
Peak memory 164468 kb
Host smart-e7a5041f-c8ff-4dc9-ae13-945fddeb7dbc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1013392939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1013392939
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3493535564
Short name T162
Test name
Test status
Simulation time 1515410000 ps
CPU time 4.8 seconds
Started Mar 21 12:22:08 PM PDT 24
Finished Mar 21 12:22:21 PM PDT 24
Peak memory 163024 kb
Host smart-fb84bdf7-127a-43a5-8421-879eb466a284
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493535564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3493535564
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.321410457
Short name T189
Test name
Test status
Simulation time 1547510000 ps
CPU time 5.69 seconds
Started Mar 21 12:22:47 PM PDT 24
Finished Mar 21 12:23:00 PM PDT 24
Peak memory 162900 kb
Host smart-0b9d24b6-93a4-4731-9fc5-2fe579d01c15
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=321410457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.321410457
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2315761810
Short name T187
Test name
Test status
Simulation time 1489010000 ps
CPU time 4.59 seconds
Started Mar 21 12:18:22 PM PDT 24
Finished Mar 21 12:18:32 PM PDT 24
Peak memory 164944 kb
Host smart-976fe5d3-24a5-4e13-b2b7-9194a70ba9bc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2315761810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2315761810
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3649144845
Short name T188
Test name
Test status
Simulation time 1251070000 ps
CPU time 4.18 seconds
Started Mar 21 12:22:47 PM PDT 24
Finished Mar 21 12:22:56 PM PDT 24
Peak memory 163616 kb
Host smart-60b3030c-33dd-4a21-8050-b9820c64956b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3649144845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3649144845
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3678808405
Short name T160
Test name
Test status
Simulation time 1324150000 ps
CPU time 4.7 seconds
Started Mar 21 12:22:16 PM PDT 24
Finished Mar 21 12:22:27 PM PDT 24
Peak memory 163108 kb
Host smart-ade4a77a-d9c7-48fc-a393-4badb840d3c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3678808405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3678808405
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4248652016
Short name T168
Test name
Test status
Simulation time 1509930000 ps
CPU time 4.82 seconds
Started Mar 21 12:22:08 PM PDT 24
Finished Mar 21 12:22:21 PM PDT 24
Peak memory 163528 kb
Host smart-fdb6ddf7-3cbb-4f7f-8abd-e44f840d7dd6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248652016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.4248652016
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3023071376
Short name T178
Test name
Test status
Simulation time 1460590000 ps
CPU time 4.82 seconds
Started Mar 21 12:22:16 PM PDT 24
Finished Mar 21 12:22:27 PM PDT 24
Peak memory 162692 kb
Host smart-b51d1aec-cd56-4ed5-b368-73d15005af4f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3023071376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3023071376
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4068677424
Short name T173
Test name
Test status
Simulation time 1586450000 ps
CPU time 3.67 seconds
Started Mar 21 12:22:27 PM PDT 24
Finished Mar 21 12:22:35 PM PDT 24
Peak memory 164320 kb
Host smart-32f96072-0f74-4abd-8c86-2991fcae7230
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4068677424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.4068677424
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2562509269
Short name T167
Test name
Test status
Simulation time 1401530000 ps
CPU time 2.92 seconds
Started Mar 21 12:23:23 PM PDT 24
Finished Mar 21 12:23:30 PM PDT 24
Peak memory 164336 kb
Host smart-23d1f57c-05e0-425e-9d45-a66f30ce6ef9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2562509269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2562509269
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3865508746
Short name T191
Test name
Test status
Simulation time 1484690000 ps
CPU time 3.18 seconds
Started Mar 21 12:23:09 PM PDT 24
Finished Mar 21 12:23:17 PM PDT 24
Peak memory 164320 kb
Host smart-1035b9b2-1605-4426-93ff-29bdb5c917af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3865508746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3865508746
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2972222162
Short name T181
Test name
Test status
Simulation time 1522490000 ps
CPU time 5.06 seconds
Started Mar 21 12:19:41 PM PDT 24
Finished Mar 21 12:19:52 PM PDT 24
Peak memory 164888 kb
Host smart-8177e87c-f5c2-4a47-82b0-5ae7072df7ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2972222162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2972222162
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2085530060
Short name T186
Test name
Test status
Simulation time 1441590000 ps
CPU time 5.33 seconds
Started Mar 21 12:19:37 PM PDT 24
Finished Mar 21 12:19:49 PM PDT 24
Peak memory 164824 kb
Host smart-7d66eb04-811e-4f2c-a8fb-646b8daa551b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2085530060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2085530060
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2071423018
Short name T161
Test name
Test status
Simulation time 1358030000 ps
CPU time 4.97 seconds
Started Mar 21 12:20:16 PM PDT 24
Finished Mar 21 12:20:27 PM PDT 24
Peak memory 164872 kb
Host smart-2bf2d865-6a64-4d8b-aa58-9d469608574d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071423018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2071423018
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2453392679
Short name T190
Test name
Test status
Simulation time 1479690000 ps
CPU time 3.62 seconds
Started Mar 21 12:22:36 PM PDT 24
Finished Mar 21 12:22:44 PM PDT 24
Peak memory 164232 kb
Host smart-1b09dcdb-7d49-4840-b233-2e7171ee1050
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453392679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2453392679
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.633888525
Short name T163
Test name
Test status
Simulation time 1441890000 ps
CPU time 2.97 seconds
Started Mar 21 12:22:49 PM PDT 24
Finished Mar 21 12:22:56 PM PDT 24
Peak memory 164296 kb
Host smart-3869fa47-5799-494f-abcc-1d049a1ecd9c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=633888525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.633888525
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3271240971
Short name T38
Test name
Test status
Simulation time 1513650000 ps
CPU time 3.72 seconds
Started Mar 21 12:16:22 PM PDT 24
Finished Mar 21 12:16:31 PM PDT 24
Peak memory 165104 kb
Host smart-3e5373e2-2b48-4a9b-8cb1-a97036f6e870
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3271240971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3271240971
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1768216661
Short name T32
Test name
Test status
Simulation time 1577150000 ps
CPU time 4.82 seconds
Started Mar 21 12:16:31 PM PDT 24
Finished Mar 21 12:16:42 PM PDT 24
Peak memory 164876 kb
Host smart-d6a79591-2039-4eb0-aeb7-bd94d7ab435a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1768216661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1768216661
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.915694300
Short name T60
Test name
Test status
Simulation time 1313350000 ps
CPU time 3.3 seconds
Started Mar 21 12:17:29 PM PDT 24
Finished Mar 21 12:17:36 PM PDT 24
Peak memory 164888 kb
Host smart-356da676-c5cd-477b-992f-90079282fe45
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=915694300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.915694300
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.641561617
Short name T70
Test name
Test status
Simulation time 1367430000 ps
CPU time 5.63 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:22:42 PM PDT 24
Peak memory 162324 kb
Host smart-9eb90d29-f22e-4b68-87e8-ff27fca372b3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=641561617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.641561617
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3175018407
Short name T56
Test name
Test status
Simulation time 1254270000 ps
CPU time 4.29 seconds
Started Mar 21 12:22:32 PM PDT 24
Finished Mar 21 12:22:41 PM PDT 24
Peak memory 163752 kb
Host smart-54497774-2191-496c-a2ef-0516e642054e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3175018407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3175018407
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1570135421
Short name T1
Test name
Test status
Simulation time 1613330000 ps
CPU time 6.14 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:22:43 PM PDT 24
Peak memory 161076 kb
Host smart-e7203dce-5ff9-404c-8488-5203675f2767
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1570135421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1570135421
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3829590446
Short name T35
Test name
Test status
Simulation time 1496030000 ps
CPU time 3.79 seconds
Started Mar 21 12:17:11 PM PDT 24
Finished Mar 21 12:17:19 PM PDT 24
Peak memory 165160 kb
Host smart-cc6a724e-39c0-4b88-ab5b-ce38b591c59d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3829590446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3829590446
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2895163118
Short name T55
Test name
Test status
Simulation time 1146150000 ps
CPU time 3.85 seconds
Started Mar 21 12:17:30 PM PDT 24
Finished Mar 21 12:17:38 PM PDT 24
Peak memory 164944 kb
Host smart-aa099adb-2e3e-4849-80a3-fdc55afeab58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895163118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2895163118
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3741584550
Short name T46
Test name
Test status
Simulation time 1091390000 ps
CPU time 3.79 seconds
Started Mar 21 12:17:29 PM PDT 24
Finished Mar 21 12:17:37 PM PDT 24
Peak memory 165012 kb
Host smart-06f60735-d1a2-4ac0-beea-afba3ea1896b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3741584550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3741584550
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2008500609
Short name T49
Test name
Test status
Simulation time 1624310000 ps
CPU time 4.43 seconds
Started Mar 21 12:17:33 PM PDT 24
Finished Mar 21 12:17:43 PM PDT 24
Peak memory 164756 kb
Host smart-3f9aae1f-8f9c-4baf-823a-e0b900cb183c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008500609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2008500609
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1873768532
Short name T12
Test name
Test status
Simulation time 1484950000 ps
CPU time 4.18 seconds
Started Mar 21 12:23:28 PM PDT 24
Finished Mar 21 12:23:37 PM PDT 24
Peak memory 164588 kb
Host smart-6f62cddf-1d11-4bef-adca-2596d8b73c67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873768532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1873768532
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2797342727
Short name T48
Test name
Test status
Simulation time 1443990000 ps
CPU time 4.33 seconds
Started Mar 21 12:16:30 PM PDT 24
Finished Mar 21 12:16:39 PM PDT 24
Peak memory 164796 kb
Host smart-2114b405-98f3-4d61-84b2-c887ee9387a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2797342727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2797342727
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1606309994
Short name T45
Test name
Test status
Simulation time 1424710000 ps
CPU time 5.88 seconds
Started Mar 21 12:22:28 PM PDT 24
Finished Mar 21 12:22:42 PM PDT 24
Peak memory 161680 kb
Host smart-8f0c2085-3535-4d31-9937-05e28d16aa23
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1606309994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1606309994
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.726988207
Short name T58
Test name
Test status
Simulation time 1555810000 ps
CPU time 4.22 seconds
Started Mar 21 12:23:28 PM PDT 24
Finished Mar 21 12:23:37 PM PDT 24
Peak memory 163852 kb
Host smart-b35daaf2-2a27-4f8a-bded-e44fcd994454
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726988207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.726988207
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.536195562
Short name T44
Test name
Test status
Simulation time 1532610000 ps
CPU time 3.58 seconds
Started Mar 21 12:23:03 PM PDT 24
Finished Mar 21 12:23:11 PM PDT 24
Peak memory 164280 kb
Host smart-acd66eca-5b90-4349-ac10-f80617a2d51b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=536195562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.536195562
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3998339576
Short name T68
Test name
Test status
Simulation time 1484030000 ps
CPU time 3.6 seconds
Started Mar 21 12:22:35 PM PDT 24
Finished Mar 21 12:22:44 PM PDT 24
Peak memory 163632 kb
Host smart-945d194d-f4f7-4c3e-a6cb-9f955233be8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3998339576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3998339576
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.960126011
Short name T53
Test name
Test status
Simulation time 1435170000 ps
CPU time 4.5 seconds
Started Mar 21 12:17:33 PM PDT 24
Finished Mar 21 12:17:42 PM PDT 24
Peak memory 164740 kb
Host smart-e8258af7-1a3f-4f36-b9c0-f62a8538ae2e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=960126011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.960126011
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1150132977
Short name T37
Test name
Test status
Simulation time 1395930000 ps
CPU time 4.03 seconds
Started Mar 21 12:23:29 PM PDT 24
Finished Mar 21 12:23:37 PM PDT 24
Peak memory 164272 kb
Host smart-0021530c-40d7-4cd6-b481-f813f8aa91a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1150132977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1150132977
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1457441485
Short name T40
Test name
Test status
Simulation time 1228470000 ps
CPU time 3.54 seconds
Started Mar 21 12:23:03 PM PDT 24
Finished Mar 21 12:23:11 PM PDT 24
Peak memory 164336 kb
Host smart-4ac2a557-5b54-4072-af0d-28ef0042b1e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457441485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1457441485
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1247666386
Short name T10
Test name
Test status
Simulation time 1378250000 ps
CPU time 4.49 seconds
Started Mar 21 12:19:13 PM PDT 24
Finished Mar 21 12:19:23 PM PDT 24
Peak memory 164820 kb
Host smart-d0781b8e-c1c4-4074-a5d7-9c8c3d1d05eb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1247666386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1247666386
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3338768703
Short name T9
Test name
Test status
Simulation time 1614590000 ps
CPU time 4.27 seconds
Started Mar 21 12:23:01 PM PDT 24
Finished Mar 21 12:23:11 PM PDT 24
Peak memory 164936 kb
Host smart-46c56cee-efb9-4a61-9df7-da303ad2479c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338768703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3338768703
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3434134223
Short name T11
Test name
Test status
Simulation time 1443490000 ps
CPU time 3.31 seconds
Started Mar 21 12:17:35 PM PDT 24
Finished Mar 21 12:17:43 PM PDT 24
Peak memory 164908 kb
Host smart-6bf12910-c09c-4352-9c3c-537d14a08625
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3434134223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3434134223
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1385731039
Short name T52
Test name
Test status
Simulation time 1543530000 ps
CPU time 3.6 seconds
Started Mar 21 12:16:23 PM PDT 24
Finished Mar 21 12:16:31 PM PDT 24
Peak memory 165104 kb
Host smart-e4ba62ec-f1c4-47cc-aed4-2b1c2e022095
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1385731039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1385731039
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2671669805
Short name T69
Test name
Test status
Simulation time 1413370000 ps
CPU time 3.9 seconds
Started Mar 21 12:23:58 PM PDT 24
Finished Mar 21 12:24:07 PM PDT 24
Peak memory 164244 kb
Host smart-44726d8c-4de8-45a6-a570-ea363663870b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2671669805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2671669805
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2026233427
Short name T64
Test name
Test status
Simulation time 1516370000 ps
CPU time 4.13 seconds
Started Mar 21 12:17:35 PM PDT 24
Finished Mar 21 12:17:44 PM PDT 24
Peak memory 164756 kb
Host smart-258a1d01-ac81-4b1c-ae4d-a05739fa4d4e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2026233427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2026233427
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1712182069
Short name T36
Test name
Test status
Simulation time 1381690000 ps
CPU time 3.22 seconds
Started Mar 21 12:22:36 PM PDT 24
Finished Mar 21 12:22:43 PM PDT 24
Peak memory 164844 kb
Host smart-92b59e40-eefa-424d-8f50-7c2049cf7c4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1712182069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1712182069
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2816457802
Short name T7
Test name
Test status
Simulation time 1524330000 ps
CPU time 4.23 seconds
Started Mar 21 12:20:50 PM PDT 24
Finished Mar 21 12:21:00 PM PDT 24
Peak memory 164824 kb
Host smart-22e072b4-73a3-405e-9d9e-18c6b89ed233
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816457802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2816457802
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3066388930
Short name T34
Test name
Test status
Simulation time 1593070000 ps
CPU time 6.22 seconds
Started Mar 21 12:19:33 PM PDT 24
Finished Mar 21 12:19:47 PM PDT 24
Peak memory 164828 kb
Host smart-8fda5d3a-adee-434d-98f9-40dbfbaac479
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066388930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3066388930
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2216827737
Short name T41
Test name
Test status
Simulation time 1515490000 ps
CPU time 3.77 seconds
Started Mar 21 12:22:18 PM PDT 24
Finished Mar 21 12:22:27 PM PDT 24
Peak memory 164024 kb
Host smart-2b8d2530-6dc4-4c42-a879-192a65b719e8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216827737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2216827737
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1050075908
Short name T61
Test name
Test status
Simulation time 1385130000 ps
CPU time 5.88 seconds
Started Mar 21 12:19:59 PM PDT 24
Finished Mar 21 12:20:11 PM PDT 24
Peak memory 164908 kb
Host smart-689104c3-ab37-46f5-824b-17b476f62507
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1050075908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1050075908
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1807943117
Short name T31
Test name
Test status
Simulation time 1583070000 ps
CPU time 3.89 seconds
Started Mar 21 12:17:08 PM PDT 24
Finished Mar 21 12:17:17 PM PDT 24
Peak memory 165160 kb
Host smart-962abf55-a8c0-4a69-a720-815a05c8abfa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1807943117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1807943117
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1987205105
Short name T42
Test name
Test status
Simulation time 1271070000 ps
CPU time 4.8 seconds
Started Mar 21 12:20:16 PM PDT 24
Finished Mar 21 12:20:26 PM PDT 24
Peak memory 164804 kb
Host smart-c6f37154-76de-4049-ac6c-03dd6d7d005e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987205105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1987205105
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.225676664
Short name T59
Test name
Test status
Simulation time 1582670000 ps
CPU time 5.24 seconds
Started Mar 21 12:20:23 PM PDT 24
Finished Mar 21 12:20:35 PM PDT 24
Peak memory 164888 kb
Host smart-7cdec998-dfe9-40fe-8c10-11575cbb83ef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=225676664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.225676664
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.882215468
Short name T54
Test name
Test status
Simulation time 1574650000 ps
CPU time 4.31 seconds
Started Mar 21 12:16:33 PM PDT 24
Finished Mar 21 12:16:43 PM PDT 24
Peak memory 164624 kb
Host smart-f480cb08-05bb-4ae4-8e35-cf068f2a87fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=882215468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.882215468
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3635979400
Short name T33
Test name
Test status
Simulation time 1476750000 ps
CPU time 3.75 seconds
Started Mar 21 12:22:35 PM PDT 24
Finished Mar 21 12:22:44 PM PDT 24
Peak memory 164384 kb
Host smart-2298b926-0817-4529-b5a5-7d370a84467f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635979400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3635979400
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2988118990
Short name T65
Test name
Test status
Simulation time 1515430000 ps
CPU time 3.68 seconds
Started Mar 21 12:25:34 PM PDT 24
Finished Mar 21 12:25:43 PM PDT 24
Peak memory 164336 kb
Host smart-16b38d38-8fa0-407a-b381-b7ad167608c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2988118990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2988118990
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1964329232
Short name T8
Test name
Test status
Simulation time 1544130000 ps
CPU time 4.87 seconds
Started Mar 21 12:23:12 PM PDT 24
Finished Mar 21 12:23:23 PM PDT 24
Peak memory 163096 kb
Host smart-4c75309a-0b65-41fd-9109-a6f91967fd74
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964329232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1964329232
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1144061839
Short name T63
Test name
Test status
Simulation time 1508190000 ps
CPU time 4.71 seconds
Started Mar 21 12:25:34 PM PDT 24
Finished Mar 21 12:25:45 PM PDT 24
Peak memory 163844 kb
Host smart-fad8e02b-6122-44c2-b864-336db6d8a494
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1144061839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1144061839
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2369178011
Short name T2
Test name
Test status
Simulation time 1562510000 ps
CPU time 4.27 seconds
Started Mar 21 12:17:32 PM PDT 24
Finished Mar 21 12:17:42 PM PDT 24
Peak memory 164732 kb
Host smart-3e6834aa-16ab-476f-8311-645f57bdb895
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2369178011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2369178011
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2723215716
Short name T67
Test name
Test status
Simulation time 1475670000 ps
CPU time 4.87 seconds
Started Mar 21 12:25:34 PM PDT 24
Finished Mar 21 12:25:45 PM PDT 24
Peak memory 163232 kb
Host smart-d9bb9a19-60fd-44ff-9757-7cb1e471c22a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2723215716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2723215716
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1655687993
Short name T62
Test name
Test status
Simulation time 1463310000 ps
CPU time 4.01 seconds
Started Mar 21 12:17:31 PM PDT 24
Finished Mar 21 12:17:40 PM PDT 24
Peak memory 164652 kb
Host smart-665b1c56-313d-4b09-bf0b-d55630af317a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1655687993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1655687993
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1600980991
Short name T51
Test name
Test status
Simulation time 1346130000 ps
CPU time 4.36 seconds
Started Mar 21 12:23:12 PM PDT 24
Finished Mar 21 12:23:22 PM PDT 24
Peak memory 163732 kb
Host smart-db48ba0e-f10e-41c3-bc23-03240d9657de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1600980991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1600980991
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2953513893
Short name T47
Test name
Test status
Simulation time 1493650000 ps
CPU time 4.13 seconds
Started Mar 21 12:22:57 PM PDT 24
Finished Mar 21 12:23:07 PM PDT 24
Peak memory 163088 kb
Host smart-26e85be6-74e2-4d10-a397-0059dbeeb90a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953513893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2953513893
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2525187676
Short name T57
Test name
Test status
Simulation time 1384870000 ps
CPU time 3.97 seconds
Started Mar 21 12:22:57 PM PDT 24
Finished Mar 21 12:23:06 PM PDT 24
Peak memory 163656 kb
Host smart-ea8533ab-ca38-4eb9-aecc-f35af06db6ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525187676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2525187676
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1317625899
Short name T43
Test name
Test status
Simulation time 1513790000 ps
CPU time 5.16 seconds
Started Mar 21 12:16:31 PM PDT 24
Finished Mar 21 12:16:43 PM PDT 24
Peak memory 164796 kb
Host smart-5753eb51-69d7-446e-8253-43fd91bdd8a5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1317625899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1317625899
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.396072287
Short name T50
Test name
Test status
Simulation time 1456210000 ps
CPU time 4.44 seconds
Started Mar 21 12:22:23 PM PDT 24
Finished Mar 21 12:22:33 PM PDT 24
Peak memory 162912 kb
Host smart-4eacb801-a15a-4e4d-8bb8-181538f153fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396072287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.396072287
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.893321498
Short name T66
Test name
Test status
Simulation time 1473950000 ps
CPU time 5.95 seconds
Started Mar 21 12:16:33 PM PDT 24
Finished Mar 21 12:16:46 PM PDT 24
Peak memory 165008 kb
Host smart-fb644ad5-6014-41f4-b072-a121ad805cfe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=893321498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.893321498
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1247308460
Short name T3
Test name
Test status
Simulation time 1506370000 ps
CPU time 5.77 seconds
Started Mar 21 12:16:34 PM PDT 24
Finished Mar 21 12:16:48 PM PDT 24
Peak memory 164968 kb
Host smart-615ef45f-cb80-43bc-80a3-d0b4109824b5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1247308460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1247308460
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1692004688
Short name T39
Test name
Test status
Simulation time 1347670000 ps
CPU time 5.11 seconds
Started Mar 21 12:16:35 PM PDT 24
Finished Mar 21 12:16:46 PM PDT 24
Peak memory 164968 kb
Host smart-847ef205-502b-4cde-9fbe-492346aa2f58
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692004688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1692004688
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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