| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2929601233 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4260268207 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1400499320 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1036315003 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.485401859 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1186989840 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1471852986 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1564663475 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4214765370 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3707254995 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3953960952 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.211078450 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.635063200 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.281068939 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.761822888 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1063910451 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3517287496 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3289280710 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4151570952 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1894310693 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2182200540 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.625475917 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1601205680 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3954505834 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1541813184 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1426857166 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2965881028 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2440650562 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3502742202 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1196486043 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3259002778 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.792537732 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3849427240 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3127149587 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2279573506 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1671064094 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4076678286 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2582508309 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2521538398 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4260052511 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2461120341 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1572115503 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1980299204 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1354470225 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4024164369 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2596574445 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2553117435 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4113423794 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1861401736 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1175113797 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3315793047 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1291350212 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1493949719 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1779244510 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2740344665 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3177013725 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.298787128 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2106321641 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1118516691 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.481242127 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3947652004 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3337737094 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1131195504 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1980079558 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.289275008 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3325848562 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3773932936 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.808214683 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3312996556 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.435577032 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2093752420 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.366323764 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.217935254 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3104519164 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.646636797 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.431887389 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2636766869 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1285397133 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.422320401 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.48079712 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2110644379 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1729377054 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1837401779 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3935794849 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3843215658 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3345722982 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1395427102 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3975526379 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1412453061 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.954855156 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2791978867 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2632363432 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2689585872 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3860167783 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.998987439 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2613527387 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3300563780 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.250407528 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3879236549 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3095906914 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3748557280 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.486016762 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1613494856 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3962368111 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.208535547 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3146450126 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1769178603 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.856133293 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1701749310 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1886936327 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.548139280 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1094627678 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.190156930 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1879792447 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.419000735 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1791197210 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1219678294 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1698184255 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.466095295 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1780752326 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2976713806 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2425593755 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3298334435 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.639255676 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1102588502 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2218949819 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1261082367 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2504763940 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3884678987 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3425005179 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2734753008 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.677661571 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1608658884 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.389808791 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.114640628 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3752558786 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.925451971 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3224537963 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1178132111 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2447428876 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.799580185 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.163089423 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.25729943 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2008593295 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1386479233 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1618294225 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2573678812 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3475697758 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.166281434 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1540173409 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2887326278 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1823339976 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4025154753 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2638365223 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1684916402 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.530136319 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4259970251 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2807945998 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1525277663 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3105373819 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3070927274 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3574755387 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1681879153 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4293447060 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.581290285 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2862379759 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.721829535 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.293591759 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.667296740 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1353778942 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1907896796 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.835398450 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2714612420 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3535532318 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2278140023 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2110870756 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4125415805 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3932790710 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1281795112 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2830874559 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2500728139 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1820881594 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1088737601 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1726262914 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4047701446 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1436354730 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.182674461 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1996597078 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3005099351 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.783887691 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.829174532 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4177480522 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3797434046 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2393625225 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2684712518 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3458129231 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3208912413 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.231422707 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1864645855 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.472004295 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1353778942 | Mar 24 12:35:53 PM PDT 24 | Mar 24 12:36:01 PM PDT 24 | 1546570000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.581290285 | Mar 24 12:36:00 PM PDT 24 | Mar 24 12:36:08 PM PDT 24 | 1587930000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2929601233 | Mar 24 12:35:40 PM PDT 24 | Mar 24 12:35:48 PM PDT 24 | 1497110000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1281795112 | Mar 24 12:36:09 PM PDT 24 | Mar 24 12:36:18 PM PDT 24 | 1504610000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1907896796 | Mar 24 12:35:48 PM PDT 24 | Mar 24 12:35:56 PM PDT 24 | 1508430000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1684916402 | Mar 24 12:35:33 PM PDT 24 | Mar 24 12:35:39 PM PDT 24 | 1318290000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2684712518 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:03 PM PDT 24 | 1380290000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3574755387 | Mar 24 12:35:51 PM PDT 24 | Mar 24 12:35:58 PM PDT 24 | 1453610000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.721829535 | Mar 24 12:35:37 PM PDT 24 | Mar 24 12:35:43 PM PDT 24 | 1057030000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1823339976 | Mar 24 12:35:34 PM PDT 24 | Mar 24 12:35:42 PM PDT 24 | 1514930000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4047701446 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:03 PM PDT 24 | 1545250000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2393625225 | Mar 24 12:36:00 PM PDT 24 | Mar 24 12:36:08 PM PDT 24 | 1460110000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4259970251 | Mar 24 12:35:39 PM PDT 24 | Mar 24 12:35:46 PM PDT 24 | 1491630000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.835398450 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:15 PM PDT 24 | 1510350000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1088737601 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:02 PM PDT 24 | 1605590000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2862379759 | Mar 24 12:35:45 PM PDT 24 | Mar 24 12:35:53 PM PDT 24 | 1443690000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2110870756 | Mar 24 12:35:46 PM PDT 24 | Mar 24 12:35:52 PM PDT 24 | 1420530000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1726262914 | Mar 24 12:36:01 PM PDT 24 | Mar 24 12:36:09 PM PDT 24 | 1327410000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3797434046 | Mar 24 12:35:51 PM PDT 24 | Mar 24 12:36:00 PM PDT 24 | 1313070000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3105373819 | Mar 24 12:35:45 PM PDT 24 | Mar 24 12:35:57 PM PDT 24 | 1338050000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1436354730 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:04 PM PDT 24 | 1180210000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.231422707 | Mar 24 12:36:06 PM PDT 24 | Mar 24 12:36:13 PM PDT 24 | 1349010000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.667296740 | Mar 24 12:36:01 PM PDT 24 | Mar 24 12:36:09 PM PDT 24 | 1483490000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2500728139 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:03 PM PDT 24 | 1592610000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2638365223 | Mar 24 12:35:37 PM PDT 24 | Mar 24 12:35:45 PM PDT 24 | 1552710000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2807945998 | Mar 24 12:35:56 PM PDT 24 | Mar 24 12:36:03 PM PDT 24 | 1360150000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.783887691 | Mar 24 12:35:55 PM PDT 24 | Mar 24 12:36:04 PM PDT 24 | 1285070000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3005099351 | Mar 24 12:35:51 PM PDT 24 | Mar 24 12:35:58 PM PDT 24 | 1317990000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1681879153 | Mar 24 12:35:42 PM PDT 24 | Mar 24 12:35:49 PM PDT 24 | 1439630000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2714612420 | Mar 24 12:35:54 PM PDT 24 | Mar 24 12:36:04 PM PDT 24 | 1543210000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1864645855 | Mar 24 12:35:28 PM PDT 24 | Mar 24 12:35:38 PM PDT 24 | 1577710000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2278140023 | Mar 24 12:35:53 PM PDT 24 | Mar 24 12:36:00 PM PDT 24 | 1488450000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4025154753 | Mar 24 12:35:45 PM PDT 24 | Mar 24 12:35:52 PM PDT 24 | 1441770000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3070927274 | Mar 24 12:36:05 PM PDT 24 | Mar 24 12:36:17 PM PDT 24 | 1498730000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3535532318 | Mar 24 12:35:51 PM PDT 24 | Mar 24 12:35:59 PM PDT 24 | 1547050000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3208912413 | Mar 24 12:35:56 PM PDT 24 | Mar 24 12:36:03 PM PDT 24 | 1188490000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.472004295 | Mar 24 12:35:33 PM PDT 24 | Mar 24 12:35:40 PM PDT 24 | 1281570000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.293591759 | Mar 24 12:35:44 PM PDT 24 | Mar 24 12:35:51 PM PDT 24 | 1433370000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4125415805 | Mar 24 12:35:44 PM PDT 24 | Mar 24 12:35:53 PM PDT 24 | 1501630000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3932790710 | Mar 24 12:36:08 PM PDT 24 | Mar 24 12:36:14 PM PDT 24 | 1384770000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4293447060 | Mar 24 12:35:42 PM PDT 24 | Mar 24 12:35:49 PM PDT 24 | 1307290000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1996597078 | Mar 24 12:35:54 PM PDT 24 | Mar 24 12:36:04 PM PDT 24 | 1462970000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3458129231 | Mar 24 12:35:36 PM PDT 24 | Mar 24 12:35:44 PM PDT 24 | 1449030000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1820881594 | Mar 24 12:35:47 PM PDT 24 | Mar 24 12:35:53 PM PDT 24 | 1555430000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.530136319 | Mar 24 12:35:46 PM PDT 24 | Mar 24 12:35:55 PM PDT 24 | 1566130000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.182674461 | Mar 24 12:35:42 PM PDT 24 | Mar 24 12:35:48 PM PDT 24 | 1327230000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4177480522 | Mar 24 12:35:35 PM PDT 24 | Mar 24 12:35:43 PM PDT 24 | 1464890000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.829174532 | Mar 24 12:36:01 PM PDT 24 | Mar 24 12:36:08 PM PDT 24 | 1258890000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1525277663 | Mar 24 12:36:00 PM PDT 24 | Mar 24 12:36:08 PM PDT 24 | 1454110000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2830874559 | Mar 24 12:35:51 PM PDT 24 | Mar 24 12:35:59 PM PDT 24 | 1551750000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.466095295 | Mar 24 12:36:45 PM PDT 24 | Mar 24 12:36:54 PM PDT 24 | 1417830000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2447428876 | Mar 24 12:36:34 PM PDT 24 | Mar 24 12:36:41 PM PDT 24 | 1433050000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2218949819 | Mar 24 12:36:27 PM PDT 24 | Mar 24 12:36:36 PM PDT 24 | 1185290000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1178132111 | Mar 24 12:36:31 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1257870000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1780752326 | Mar 24 12:36:47 PM PDT 24 | Mar 24 12:36:58 PM PDT 24 | 1443390000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1618294225 | Mar 24 12:36:41 PM PDT 24 | Mar 24 12:37:04 PM PDT 24 | 1541030000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2887326278 | Mar 24 12:36:48 PM PDT 24 | Mar 24 12:36:57 PM PDT 24 | 1201590000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2573678812 | Mar 24 12:36:28 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1606870000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.166281434 | Mar 24 12:36:27 PM PDT 24 | Mar 24 12:36:33 PM PDT 24 | 1284250000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1036315003 | Mar 24 12:36:28 PM PDT 24 | Mar 24 12:36:40 PM PDT 24 | 1574810000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1698184255 | Mar 24 12:36:32 PM PDT 24 | Mar 24 12:36:40 PM PDT 24 | 1427710000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1386479233 | Mar 24 12:36:50 PM PDT 24 | Mar 24 12:36:58 PM PDT 24 | 1432650000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3298334435 | Mar 24 12:36:32 PM PDT 24 | Mar 24 12:36:42 PM PDT 24 | 1528810000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.639255676 | Mar 24 12:36:56 PM PDT 24 | Mar 24 12:37:04 PM PDT 24 | 1346810000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1261082367 | Mar 24 12:36:42 PM PDT 24 | Mar 24 12:36:50 PM PDT 24 | 1402690000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2734753008 | Mar 24 12:36:42 PM PDT 24 | Mar 24 12:36:52 PM PDT 24 | 1380370000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.190156930 | Mar 24 12:36:40 PM PDT 24 | Mar 24 12:36:50 PM PDT 24 | 1494010000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1879792447 | Mar 24 12:36:29 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1407990000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3884678987 | Mar 24 12:36:29 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1358750000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3224537963 | Mar 24 12:36:41 PM PDT 24 | Mar 24 12:36:52 PM PDT 24 | 1496510000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.925451971 | Mar 24 12:36:30 PM PDT 24 | Mar 24 12:36:40 PM PDT 24 | 1484270000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2008593295 | Mar 24 12:36:48 PM PDT 24 | Mar 24 12:36:58 PM PDT 24 | 1384590000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1769178603 | Mar 24 12:36:34 PM PDT 24 | Mar 24 12:36:42 PM PDT 24 | 1552490000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.208535547 | Mar 24 12:36:49 PM PDT 24 | Mar 24 12:36:59 PM PDT 24 | 1350290000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1540173409 | Mar 24 12:36:28 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1358870000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.163089423 | Mar 24 12:36:41 PM PDT 24 | Mar 24 12:36:48 PM PDT 24 | 1004510000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3962368111 | Mar 24 12:36:35 PM PDT 24 | Mar 24 12:36:43 PM PDT 24 | 1565850000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.389808791 | Mar 24 12:36:31 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1084850000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3425005179 | Mar 24 12:36:33 PM PDT 24 | Mar 24 12:36:42 PM PDT 24 | 1585790000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1094627678 | Mar 24 12:36:40 PM PDT 24 | Mar 24 12:36:52 PM PDT 24 | 1462710000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.114640628 | Mar 24 12:36:32 PM PDT 24 | Mar 24 12:36:41 PM PDT 24 | 1558750000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.25729943 | Mar 24 12:37:11 PM PDT 24 | Mar 24 12:37:19 PM PDT 24 | 1419830000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.419000735 | Mar 24 12:36:27 PM PDT 24 | Mar 24 12:36:36 PM PDT 24 | 1421150000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1886936327 | Mar 24 12:36:44 PM PDT 24 | Mar 24 12:36:53 PM PDT 24 | 1408150000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1791197210 | Mar 24 12:36:28 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1510670000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1701749310 | Mar 24 12:36:41 PM PDT 24 | Mar 24 12:36:52 PM PDT 24 | 1544550000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1613494856 | Mar 24 12:36:50 PM PDT 24 | Mar 24 12:36:56 PM PDT 24 | 1221810000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2976713806 | Mar 24 12:36:36 PM PDT 24 | Mar 24 12:36:42 PM PDT 24 | 1067670000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1608658884 | Mar 24 12:36:22 PM PDT 24 | Mar 24 12:36:30 PM PDT 24 | 1527330000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2425593755 | Mar 24 12:36:17 PM PDT 24 | Mar 24 12:36:23 PM PDT 24 | 1243150000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.677661571 | Mar 24 12:36:39 PM PDT 24 | Mar 24 12:36:51 PM PDT 24 | 1405390000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.856133293 | Mar 24 12:36:26 PM PDT 24 | Mar 24 12:36:34 PM PDT 24 | 1543630000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3752558786 | Mar 24 12:36:52 PM PDT 24 | Mar 24 12:37:00 PM PDT 24 | 1592270000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3146450126 | Mar 24 12:36:22 PM PDT 24 | Mar 24 12:36:30 PM PDT 24 | 1614210000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3475697758 | Mar 24 12:36:28 PM PDT 24 | Mar 24 12:36:37 PM PDT 24 | 1474110000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.799580185 | Mar 24 12:36:46 PM PDT 24 | Mar 24 12:36:58 PM PDT 24 | 1574590000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.548139280 | Mar 24 12:36:42 PM PDT 24 | Mar 24 12:36:51 PM PDT 24 | 1510010000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1102588502 | Mar 24 12:36:38 PM PDT 24 | Mar 24 12:36:51 PM PDT 24 | 1321430000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2504763940 | Mar 24 12:36:34 PM PDT 24 | Mar 24 12:36:41 PM PDT 24 | 1377470000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1219678294 | Mar 24 12:36:51 PM PDT 24 | Mar 24 12:37:00 PM PDT 24 | 1321250000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1175113797 | Mar 24 12:38:39 PM PDT 24 | Mar 24 01:09:05 PM PDT 24 | 337029110000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3954505834 | Mar 24 12:38:38 PM PDT 24 | Mar 24 01:12:35 PM PDT 24 | 337082570000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4260268207 | Mar 24 12:38:18 PM PDT 24 | Mar 24 01:07:19 PM PDT 24 | 337141550000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1291350212 | Mar 24 12:38:29 PM PDT 24 | Mar 24 01:14:00 PM PDT 24 | 337165390000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1426857166 | Mar 24 12:38:31 PM PDT 24 | Mar 24 01:05:14 PM PDT 24 | 336294750000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.625475917 | Mar 24 12:38:14 PM PDT 24 | Mar 24 01:14:24 PM PDT 24 | 336497370000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3953960952 | Mar 24 12:38:33 PM PDT 24 | Mar 24 01:20:04 PM PDT 24 | 336980210000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3315793047 | Mar 24 12:38:21 PM PDT 24 | Mar 24 01:10:22 PM PDT 24 | 336602230000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2182200540 | Mar 24 12:38:26 PM PDT 24 | Mar 24 01:17:52 PM PDT 24 | 336845870000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.792537732 | Mar 24 12:38:21 PM PDT 24 | Mar 24 01:06:38 PM PDT 24 | 336611910000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1063910451 | Mar 24 12:38:45 PM PDT 24 | Mar 24 01:15:30 PM PDT 24 | 337017650000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4024164369 | Mar 24 12:38:36 PM PDT 24 | Mar 24 01:08:24 PM PDT 24 | 336446270000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1196486043 | Mar 24 12:38:38 PM PDT 24 | Mar 24 01:14:54 PM PDT 24 | 336680370000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2521538398 | Mar 24 12:38:12 PM PDT 24 | Mar 24 01:10:16 PM PDT 24 | 336486190000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4113423794 | Mar 24 12:38:32 PM PDT 24 | Mar 24 01:08:12 PM PDT 24 | 337080670000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3502742202 | Mar 24 12:38:30 PM PDT 24 | Mar 24 01:18:43 PM PDT 24 | 336665790000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.211078450 | Mar 24 12:38:23 PM PDT 24 | Mar 24 01:12:59 PM PDT 24 | 336521770000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2596574445 | Mar 24 12:38:45 PM PDT 24 | Mar 24 01:11:10 PM PDT 24 | 336637990000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1541813184 | Mar 24 12:38:37 PM PDT 24 | Mar 24 01:05:35 PM PDT 24 | 337065110000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1572115503 | Mar 24 12:38:21 PM PDT 24 | Mar 24 01:13:35 PM PDT 24 | 336924850000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4151570952 | Mar 24 12:38:16 PM PDT 24 | Mar 24 01:12:10 PM PDT 24 | 337040130000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4076678286 | Mar 24 12:38:22 PM PDT 24 | Mar 24 01:07:48 PM PDT 24 | 336409570000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1671064094 | Mar 24 12:38:33 PM PDT 24 | Mar 24 01:10:03 PM PDT 24 | 336348970000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3127149587 | Mar 24 12:38:58 PM PDT 24 | Mar 24 01:09:12 PM PDT 24 | 336492590000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4214765370 | Mar 24 12:38:23 PM PDT 24 | Mar 24 01:10:10 PM PDT 24 | 336800830000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3259002778 | Mar 24 12:38:45 PM PDT 24 | Mar 24 01:09:11 PM PDT 24 | 336375670000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1493949719 | Mar 24 12:38:08 PM PDT 24 | Mar 24 01:09:01 PM PDT 24 | 336444370000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4260052511 | Mar 24 12:38:52 PM PDT 24 | Mar 24 01:12:55 PM PDT 24 | 336788550000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1861401736 | Mar 24 12:38:05 PM PDT 24 | Mar 24 01:08:59 PM PDT 24 | 336310290000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2965881028 | Mar 24 12:38:14 PM PDT 24 | Mar 24 01:12:07 PM PDT 24 | 336488670000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2582508309 | Mar 24 12:38:34 PM PDT 24 | Mar 24 01:09:54 PM PDT 24 | 336532050000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.761822888 | Mar 24 12:38:43 PM PDT 24 | Mar 24 01:13:54 PM PDT 24 | 336472690000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2553117435 | Mar 24 12:38:35 PM PDT 24 | Mar 24 01:11:49 PM PDT 24 | 336587870000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3289280710 | Mar 24 12:38:19 PM PDT 24 | Mar 24 01:04:13 PM PDT 24 | 336941430000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.485401859 | Mar 24 12:38:24 PM PDT 24 | Mar 24 01:10:54 PM PDT 24 | 336862030000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.281068939 | Mar 24 12:38:28 PM PDT 24 | Mar 24 01:04:11 PM PDT 24 | 337017490000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3707254995 | Mar 24 12:38:40 PM PDT 24 | Mar 24 01:19:59 PM PDT 24 | 336486270000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3849427240 | Mar 24 12:38:41 PM PDT 24 | Mar 24 01:10:39 PM PDT 24 | 336817610000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1564663475 | Mar 24 12:38:20 PM PDT 24 | Mar 24 01:03:28 PM PDT 24 | 336425090000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2461120341 | Mar 24 12:38:36 PM PDT 24 | Mar 24 12:59:59 PM PDT 24 | 337024070000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1186989840 | Mar 24 12:38:36 PM PDT 24 | Mar 24 01:13:40 PM PDT 24 | 336792590000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1980299204 | Mar 24 12:38:47 PM PDT 24 | Mar 24 01:07:09 PM PDT 24 | 336956370000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2440650562 | Mar 24 12:38:38 PM PDT 24 | Mar 24 01:04:16 PM PDT 24 | 336967810000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1894310693 | Mar 24 12:38:44 PM PDT 24 | Mar 24 01:09:05 PM PDT 24 | 336711210000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.635063200 | Mar 24 12:38:26 PM PDT 24 | Mar 24 01:19:46 PM PDT 24 | 336737550000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2279573506 | Mar 24 12:39:02 PM PDT 24 | Mar 24 01:12:55 PM PDT 24 | 337074150000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1354470225 | Mar 24 12:38:22 PM PDT 24 | Mar 24 01:07:18 PM PDT 24 | 336884570000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1471852986 | Mar 24 12:38:43 PM PDT 24 | Mar 24 01:09:58 PM PDT 24 | 336675990000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3517287496 | Mar 24 12:38:45 PM PDT 24 | Mar 24 01:03:46 PM PDT 24 | 336585070000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1601205680 | Mar 24 12:38:55 PM PDT 24 | Mar 24 01:18:02 PM PDT 24 | 336638830000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2791978867 | Mar 24 12:36:54 PM PDT 24 | Mar 24 01:17:21 PM PDT 24 | 336865990000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3325848562 | Mar 24 12:36:33 PM PDT 24 | Mar 24 01:00:59 PM PDT 24 | 336790730000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1285397133 | Mar 24 12:36:41 PM PDT 24 | Mar 24 01:02:52 PM PDT 24 | 336398190000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3947652004 | Mar 24 12:36:56 PM PDT 24 | Mar 24 01:17:27 PM PDT 24 | 336485990000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3177013725 | Mar 24 12:36:57 PM PDT 24 | Mar 24 01:13:28 PM PDT 24 | 336702830000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.298787128 | Mar 24 12:36:58 PM PDT 24 | Mar 24 01:13:45 PM PDT 24 | 337088010000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1400499320 | Mar 24 12:36:32 PM PDT 24 | Mar 24 01:11:39 PM PDT 24 | 336702830000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3975526379 | Mar 24 12:36:44 PM PDT 24 | Mar 24 01:11:42 PM PDT 24 | 336561930000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2740344665 | Mar 24 12:36:45 PM PDT 24 | Mar 24 01:17:57 PM PDT 24 | 336761930000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.435577032 | Mar 24 12:36:41 PM PDT 24 | Mar 24 01:00:42 PM PDT 24 | 336871890000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1837401779 | Mar 24 12:36:36 PM PDT 24 | Mar 24 01:11:29 PM PDT 24 | 336484130000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3860167783 | Mar 24 12:36:48 PM PDT 24 | Mar 24 01:07:47 PM PDT 24 | 336621950000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3879236549 | Mar 24 12:36:33 PM PDT 24 | Mar 24 01:14:58 PM PDT 24 | 336612210000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2613527387 | Mar 24 12:37:03 PM PDT 24 | Mar 24 01:11:08 PM PDT 24 | 336679950000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.998987439 | Mar 24 12:36:47 PM PDT 24 | Mar 24 01:08:58 PM PDT 24 | 336635850000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3935794849 | Mar 24 12:36:42 PM PDT 24 | Mar 24 01:13:18 PM PDT 24 | 336636570000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3095906914 | Mar 24 12:36:48 PM PDT 24 | Mar 24 01:11:57 PM PDT 24 | 336499010000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.808214683 | Mar 24 12:36:50 PM PDT 24 | Mar 24 01:12:58 PM PDT 24 | 336400850000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1395427102 | Mar 24 12:37:07 PM PDT 24 | Mar 24 01:03:55 PM PDT 24 | 336921330000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3773932936 | Mar 24 12:36:49 PM PDT 24 | Mar 24 01:05:10 PM PDT 24 | 336341110000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3337737094 | Mar 24 12:36:34 PM PDT 24 | Mar 24 01:11:50 PM PDT 24 | 336575050000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.486016762 | Mar 24 12:36:48 PM PDT 24 | Mar 24 01:12:18 PM PDT 24 | 336775570000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1118516691 | Mar 24 12:36:44 PM PDT 24 | Mar 24 12:59:52 PM PDT 24 | 336387570000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3312996556 | Mar 24 12:36:49 PM PDT 24 | Mar 24 01:06:51 PM PDT 24 | 337137670000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3843215658 | Mar 24 12:36:45 PM PDT 24 | Mar 24 01:17:38 PM PDT 24 | 336355230000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.366323764 | Mar 24 12:36:41 PM PDT 24 | Mar 24 01:08:44 PM PDT 24 | 336914730000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2110644379 | Mar 24 12:36:28 PM PDT 24 | Mar 24 01:13:30 PM PDT 24 | 336640810000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3345722982 | Mar 24 12:36:41 PM PDT 24 | Mar 24 01:14:38 PM PDT 24 | 336738010000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3748557280 | Mar 24 12:36:42 PM PDT 24 | Mar 24 01:04:56 PM PDT 24 | 336945210000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1412453061 | Mar 24 12:36:39 PM PDT 24 | Mar 24 01:14:13 PM PDT 24 | 336385710000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2106321641 | Mar 24 12:36:49 PM PDT 24 | Mar 24 01:09:03 PM PDT 24 | 336852110000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1729377054 | Mar 24 12:36:54 PM PDT 24 | Mar 24 01:16:50 PM PDT 24 | 337049510000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1131195504 | Mar 24 12:36:46 PM PDT 24 | Mar 24 01:06:22 PM PDT 24 | 337120290000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.217935254 | Mar 24 12:36:58 PM PDT 24 | Mar 24 01:16:55 PM PDT 24 | 337057510000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.289275008 | Mar 24 12:36:36 PM PDT 24 | Mar 24 01:16:31 PM PDT 24 | 336670970000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.422320401 | Mar 24 12:37:15 PM PDT 24 | Mar 24 01:12:19 PM PDT 24 | 336450090000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2689585872 | Mar 24 12:36:38 PM PDT 24 | Mar 24 01:07:38 PM PDT 24 | 336595370000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.250407528 | Mar 24 12:36:55 PM PDT 24 | Mar 24 01:10:23 PM PDT 24 | 336510370000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3104519164 | Mar 24 12:36:52 PM PDT 24 | Mar 24 01:10:10 PM PDT 24 | 337054070000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1779244510 | Mar 24 12:36:44 PM PDT 24 | Mar 24 01:04:47 PM PDT 24 | 336760470000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2632363432 | Mar 24 12:36:44 PM PDT 24 | Mar 24 01:04:10 PM PDT 24 | 336852550000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2093752420 | Mar 24 12:36:43 PM PDT 24 | Mar 24 01:03:21 PM PDT 24 | 336895290000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2636766869 | Mar 24 12:36:45 PM PDT 24 | Mar 24 01:08:27 PM PDT 24 | 336882130000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.48079712 | Mar 24 12:36:45 PM PDT 24 | Mar 24 01:08:49 PM PDT 24 | 336367030000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.954855156 | Mar 24 12:36:53 PM PDT 24 | Mar 24 01:15:32 PM PDT 24 | 336792390000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.481242127 | Mar 24 12:36:48 PM PDT 24 | Mar 24 01:11:24 PM PDT 24 | 336445990000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.431887389 | Mar 24 12:36:50 PM PDT 24 | Mar 24 01:05:26 PM PDT 24 | 336920830000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.646636797 | Mar 24 12:36:39 PM PDT 24 | Mar 24 01:10:51 PM PDT 24 | 336661030000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1980079558 | Mar 24 12:36:45 PM PDT 24 | Mar 24 01:13:38 PM PDT 24 | 336809570000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3300563780 | Mar 24 12:36:50 PM PDT 24 | Mar 24 01:07:56 PM PDT 24 | 336881410000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2929601233 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1497110000 ps |
| CPU time | 3.59 seconds |
| Started | Mar 24 12:35:40 PM PDT 24 |
| Finished | Mar 24 12:35:48 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-20ecb80a-78a6-41cc-a9cf-1ab530459d2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2929601233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2929601233 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4260268207 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 337141550000 ps |
| CPU time | 705.95 seconds |
| Started | Mar 24 12:38:18 PM PDT 24 |
| Finished | Mar 24 01:07:19 PM PDT 24 |
| Peak memory | 160944 kb |
| Host | smart-e3a316c5-404e-4f2e-b0e8-23a1b1f8ce5e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4260268207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4260268207 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1400499320 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336702830000 ps |
| CPU time | 862.06 seconds |
| Started | Mar 24 12:36:32 PM PDT 24 |
| Finished | Mar 24 01:11:39 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-9d94a498-ec87-4200-9a7c-817890e0292f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1400499320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1400499320 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1036315003 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1574810000 ps |
| CPU time | 4.63 seconds |
| Started | Mar 24 12:36:28 PM PDT 24 |
| Finished | Mar 24 12:36:40 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-386e7866-4ca6-4c3b-b336-8970c782a7c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1036315003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1036315003 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.485401859 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336862030000 ps |
| CPU time | 789.76 seconds |
| Started | Mar 24 12:38:24 PM PDT 24 |
| Finished | Mar 24 01:10:54 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-022948ce-e901-4aef-8a0e-bf19829a6f35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=485401859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.485401859 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1186989840 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336792590000 ps |
| CPU time | 846.51 seconds |
| Started | Mar 24 12:38:36 PM PDT 24 |
| Finished | Mar 24 01:13:40 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-54375f2f-42e4-449d-81b5-8b3841a68849 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1186989840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1186989840 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1471852986 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336675990000 ps |
| CPU time | 761.95 seconds |
| Started | Mar 24 12:38:43 PM PDT 24 |
| Finished | Mar 24 01:09:58 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-3415b145-5961-457a-956f-978212888dea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1471852986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1471852986 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1564663475 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336425090000 ps |
| CPU time | 599.69 seconds |
| Started | Mar 24 12:38:20 PM PDT 24 |
| Finished | Mar 24 01:03:28 PM PDT 24 |
| Peak memory | 161044 kb |
| Host | smart-3de25f76-5b19-4acc-804c-3f17a2d517bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1564663475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1564663475 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4214765370 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336800830000 ps |
| CPU time | 781.05 seconds |
| Started | Mar 24 12:38:23 PM PDT 24 |
| Finished | Mar 24 01:10:10 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-16bd51ee-22b6-4b27-bb14-4ac51a5ce4b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4214765370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4214765370 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3707254995 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336486270000 ps |
| CPU time | 990.6 seconds |
| Started | Mar 24 12:38:40 PM PDT 24 |
| Finished | Mar 24 01:19:59 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-75815acc-3f96-491d-acae-8a2022d04be6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3707254995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3707254995 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3953960952 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336980210000 ps |
| CPU time | 1001.24 seconds |
| Started | Mar 24 12:38:33 PM PDT 24 |
| Finished | Mar 24 01:20:04 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-18540912-78c7-48d4-af99-5c2907422d03 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3953960952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3953960952 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.211078450 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336521770000 ps |
| CPU time | 847.01 seconds |
| Started | Mar 24 12:38:23 PM PDT 24 |
| Finished | Mar 24 01:12:59 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-57e9ec5b-e315-409a-88b9-efbe57eddbb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=211078450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.211078450 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.635063200 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336737550000 ps |
| CPU time | 995.79 seconds |
| Started | Mar 24 12:38:26 PM PDT 24 |
| Finished | Mar 24 01:19:46 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-fbc26ac2-805a-42e9-b274-8a717a315378 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=635063200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.635063200 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.281068939 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 337017490000 ps |
| CPU time | 613.1 seconds |
| Started | Mar 24 12:38:28 PM PDT 24 |
| Finished | Mar 24 01:04:11 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-76c44f52-a828-4dc2-8251-4676a689d763 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=281068939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.281068939 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.761822888 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336472690000 ps |
| CPU time | 858.41 seconds |
| Started | Mar 24 12:38:43 PM PDT 24 |
| Finished | Mar 24 01:13:54 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-078c6dc5-0295-4846-b76c-9b3f2e2cd9f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=761822888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.761822888 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1063910451 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 337017650000 ps |
| CPU time | 886.27 seconds |
| Started | Mar 24 12:38:45 PM PDT 24 |
| Finished | Mar 24 01:15:30 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-3921b1db-9841-4ef6-8856-ee815976f6f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1063910451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1063910451 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3517287496 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336585070000 ps |
| CPU time | 591.31 seconds |
| Started | Mar 24 12:38:45 PM PDT 24 |
| Finished | Mar 24 01:03:46 PM PDT 24 |
| Peak memory | 161044 kb |
| Host | smart-8659d2e8-070c-4261-a050-d85bca5ce1c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3517287496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3517287496 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3289280710 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336941430000 ps |
| CPU time | 632.89 seconds |
| Started | Mar 24 12:38:19 PM PDT 24 |
| Finished | Mar 24 01:04:13 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-26ad842c-4ce0-483a-b6bb-54fe129a6c05 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3289280710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3289280710 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4151570952 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 337040130000 ps |
| CPU time | 817.08 seconds |
| Started | Mar 24 12:38:16 PM PDT 24 |
| Finished | Mar 24 01:12:10 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-e2d40e83-25ad-47c5-891b-5ff6eda21557 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4151570952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4151570952 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1894310693 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336711210000 ps |
| CPU time | 755.52 seconds |
| Started | Mar 24 12:38:44 PM PDT 24 |
| Finished | Mar 24 01:09:05 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-05d47162-8545-4029-8a96-4f4982e2cb74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1894310693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1894310693 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2182200540 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336845870000 ps |
| CPU time | 921.57 seconds |
| Started | Mar 24 12:38:26 PM PDT 24 |
| Finished | Mar 24 01:17:52 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-8f7ecb44-1090-40bb-bf3f-c7aedde1ca61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2182200540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2182200540 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.625475917 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336497370000 ps |
| CPU time | 882.27 seconds |
| Started | Mar 24 12:38:14 PM PDT 24 |
| Finished | Mar 24 01:14:24 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-04c4c470-8be7-43e2-811d-cf06fbaa4576 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=625475917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.625475917 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1601205680 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336638830000 ps |
| CPU time | 912.45 seconds |
| Started | Mar 24 12:38:55 PM PDT 24 |
| Finished | Mar 24 01:18:02 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-15289540-39d5-423b-a133-7dc05fd4e867 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1601205680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1601205680 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3954505834 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 337082570000 ps |
| CPU time | 829.61 seconds |
| Started | Mar 24 12:38:38 PM PDT 24 |
| Finished | Mar 24 01:12:35 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-b45913d2-a44b-4872-bca2-4174f172c02c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3954505834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3954505834 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1541813184 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 337065110000 ps |
| CPU time | 643.69 seconds |
| Started | Mar 24 12:38:37 PM PDT 24 |
| Finished | Mar 24 01:05:35 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-676130b1-5683-42c6-b2ab-5e886607cf3c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1541813184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1541813184 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1426857166 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336294750000 ps |
| CPU time | 654.22 seconds |
| Started | Mar 24 12:38:31 PM PDT 24 |
| Finished | Mar 24 01:05:14 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-ae41f302-93a7-408c-ad42-552285b68c05 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1426857166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1426857166 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2965881028 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336488670000 ps |
| CPU time | 826.49 seconds |
| Started | Mar 24 12:38:14 PM PDT 24 |
| Finished | Mar 24 01:12:07 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-32ee87a4-cde2-4391-8a90-14f1bf3a4780 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2965881028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2965881028 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2440650562 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336967810000 ps |
| CPU time | 612.66 seconds |
| Started | Mar 24 12:38:38 PM PDT 24 |
| Finished | Mar 24 01:04:16 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-c5705dba-5863-4ae1-a90a-dcd90ab04b02 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2440650562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2440650562 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3502742202 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336665790000 ps |
| CPU time | 957.13 seconds |
| Started | Mar 24 12:38:30 PM PDT 24 |
| Finished | Mar 24 01:18:43 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-7854e43c-13ce-4104-b8d8-77b3f0f5cff7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3502742202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3502742202 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1196486043 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336680370000 ps |
| CPU time | 865.13 seconds |
| Started | Mar 24 12:38:38 PM PDT 24 |
| Finished | Mar 24 01:14:54 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-9b453430-bbc8-4c78-87d4-b9d2afca0e74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1196486043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1196486043 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3259002778 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336375670000 ps |
| CPU time | 740.92 seconds |
| Started | Mar 24 12:38:45 PM PDT 24 |
| Finished | Mar 24 01:09:11 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-2697fd34-ea40-4666-8bb7-f46d1f86e6d2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3259002778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3259002778 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.792537732 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336611910000 ps |
| CPU time | 687.72 seconds |
| Started | Mar 24 12:38:21 PM PDT 24 |
| Finished | Mar 24 01:06:38 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-d0979884-21ff-4cba-aa88-f8c6f7be033a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=792537732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.792537732 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3849427240 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336817610000 ps |
| CPU time | 776.1 seconds |
| Started | Mar 24 12:38:41 PM PDT 24 |
| Finished | Mar 24 01:10:39 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-4216bb6d-495f-4695-b897-6517d59dcef8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3849427240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3849427240 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3127149587 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336492590000 ps |
| CPU time | 752.64 seconds |
| Started | Mar 24 12:38:58 PM PDT 24 |
| Finished | Mar 24 01:09:12 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-fd1a0765-5b4c-4afb-94e5-4e98fcc7065e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3127149587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3127149587 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2279573506 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 337074150000 ps |
| CPU time | 827.42 seconds |
| Started | Mar 24 12:39:02 PM PDT 24 |
| Finished | Mar 24 01:12:55 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-a30a5466-fd37-49ba-a1c1-46775e8560aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2279573506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2279573506 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1671064094 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336348970000 ps |
| CPU time | 769.29 seconds |
| Started | Mar 24 12:38:33 PM PDT 24 |
| Finished | Mar 24 01:10:03 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-e9852157-5ab8-4fe1-bce5-fb6340fb35e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1671064094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1671064094 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4076678286 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336409570000 ps |
| CPU time | 709.88 seconds |
| Started | Mar 24 12:38:22 PM PDT 24 |
| Finished | Mar 24 01:07:48 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-dd337911-2a4d-4364-9d9d-5356d683c2ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4076678286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4076678286 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2582508309 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336532050000 ps |
| CPU time | 770.46 seconds |
| Started | Mar 24 12:38:34 PM PDT 24 |
| Finished | Mar 24 01:09:54 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-0189f270-dda6-4504-b46f-2025d73c948a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2582508309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2582508309 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2521538398 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336486190000 ps |
| CPU time | 771.44 seconds |
| Started | Mar 24 12:38:12 PM PDT 24 |
| Finished | Mar 24 01:10:16 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-d09ca19f-ce55-461b-89f0-ef268275f251 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2521538398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2521538398 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4260052511 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336788550000 ps |
| CPU time | 823.06 seconds |
| Started | Mar 24 12:38:52 PM PDT 24 |
| Finished | Mar 24 01:12:55 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-21ffd477-25e4-45df-bf67-7675e46bc3df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4260052511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4260052511 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2461120341 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 337024070000 ps |
| CPU time | 494.49 seconds |
| Started | Mar 24 12:38:36 PM PDT 24 |
| Finished | Mar 24 12:59:59 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-d98fb469-b0b4-4357-8145-1689077808d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2461120341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2461120341 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1572115503 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336924850000 ps |
| CPU time | 867.73 seconds |
| Started | Mar 24 12:38:21 PM PDT 24 |
| Finished | Mar 24 01:13:35 PM PDT 24 |
| Peak memory | 160936 kb |
| Host | smart-6d00041a-2085-40cd-9207-30a36bf093b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1572115503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1572115503 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1980299204 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336956370000 ps |
| CPU time | 700.59 seconds |
| Started | Mar 24 12:38:47 PM PDT 24 |
| Finished | Mar 24 01:07:09 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-319209a0-5362-4e5e-bcb9-c6afec8bfc9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1980299204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1980299204 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1354470225 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336884570000 ps |
| CPU time | 703.87 seconds |
| Started | Mar 24 12:38:22 PM PDT 24 |
| Finished | Mar 24 01:07:18 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-88638d27-1113-4666-9845-fa7b012d8916 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1354470225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1354470225 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4024164369 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336446270000 ps |
| CPU time | 727.23 seconds |
| Started | Mar 24 12:38:36 PM PDT 24 |
| Finished | Mar 24 01:08:24 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-60cf984d-1857-4035-82cb-e7519a2c50b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4024164369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.4024164369 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2596574445 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336637990000 ps |
| CPU time | 787 seconds |
| Started | Mar 24 12:38:45 PM PDT 24 |
| Finished | Mar 24 01:11:10 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-b6d8e07a-b0aa-42c6-8c4b-04e49670580f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2596574445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2596574445 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2553117435 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336587870000 ps |
| CPU time | 821.85 seconds |
| Started | Mar 24 12:38:35 PM PDT 24 |
| Finished | Mar 24 01:11:49 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-92450e10-9121-4b95-83c8-78e3264efbb2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2553117435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2553117435 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4113423794 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 337080670000 ps |
| CPU time | 735.98 seconds |
| Started | Mar 24 12:38:32 PM PDT 24 |
| Finished | Mar 24 01:08:12 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-6fc783df-8496-43b6-9f05-66861052ee33 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4113423794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4113423794 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1861401736 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336310290000 ps |
| CPU time | 756.47 seconds |
| Started | Mar 24 12:38:05 PM PDT 24 |
| Finished | Mar 24 01:08:59 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-c1ec247b-cae4-4bff-b9bf-b4f2783ec935 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1861401736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1861401736 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1175113797 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 337029110000 ps |
| CPU time | 751.88 seconds |
| Started | Mar 24 12:38:39 PM PDT 24 |
| Finished | Mar 24 01:09:05 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-a2bed32a-5bbb-4f6d-87d5-eb4f0613a805 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1175113797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1175113797 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3315793047 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336602230000 ps |
| CPU time | 778.41 seconds |
| Started | Mar 24 12:38:21 PM PDT 24 |
| Finished | Mar 24 01:10:22 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-d9f500af-bb3e-4419-b245-e465ce6d3cd2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3315793047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3315793047 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1291350212 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 337165390000 ps |
| CPU time | 852.78 seconds |
| Started | Mar 24 12:38:29 PM PDT 24 |
| Finished | Mar 24 01:14:00 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-10cbc42f-e5e9-4be8-920d-62ced0dd2b7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1291350212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1291350212 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1493949719 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336444370000 ps |
| CPU time | 764.57 seconds |
| Started | Mar 24 12:38:08 PM PDT 24 |
| Finished | Mar 24 01:09:01 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-03d252f3-25cd-482a-a1b8-55b8e98118ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1493949719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1493949719 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1779244510 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336760470000 ps |
| CPU time | 683.32 seconds |
| Started | Mar 24 12:36:44 PM PDT 24 |
| Finished | Mar 24 01:04:47 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-a8d5bf18-6dce-4669-9c92-f9bce0ddb6ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1779244510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1779244510 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2740344665 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336761930000 ps |
| CPU time | 989.44 seconds |
| Started | Mar 24 12:36:45 PM PDT 24 |
| Finished | Mar 24 01:17:57 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-fc40985c-922f-405a-9d0c-e6c1848ae055 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2740344665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2740344665 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3177013725 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336702830000 ps |
| CPU time | 877.29 seconds |
| Started | Mar 24 12:36:57 PM PDT 24 |
| Finished | Mar 24 01:13:28 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-09977cd5-8f34-4063-aecf-39cbb57a5457 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3177013725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3177013725 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.298787128 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 337088010000 ps |
| CPU time | 880.74 seconds |
| Started | Mar 24 12:36:58 PM PDT 24 |
| Finished | Mar 24 01:13:45 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-3373e25d-478b-43ce-b2e0-aac7a5152139 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=298787128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.298787128 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2106321641 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336852110000 ps |
| CPU time | 778.22 seconds |
| Started | Mar 24 12:36:49 PM PDT 24 |
| Finished | Mar 24 01:09:03 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-0f08744e-ca8a-4491-82b2-e8e5a3a92e25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2106321641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2106321641 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1118516691 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336387570000 ps |
| CPU time | 537.12 seconds |
| Started | Mar 24 12:36:44 PM PDT 24 |
| Finished | Mar 24 12:59:52 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-658fa5a4-10d2-4eea-a1cc-d02660f0a06e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1118516691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1118516691 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.481242127 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336445990000 ps |
| CPU time | 836.16 seconds |
| Started | Mar 24 12:36:48 PM PDT 24 |
| Finished | Mar 24 01:11:24 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-3f0724ff-120e-43d4-8a1c-adf3e1969d2f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=481242127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.481242127 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3947652004 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336485990000 ps |
| CPU time | 968.89 seconds |
| Started | Mar 24 12:36:56 PM PDT 24 |
| Finished | Mar 24 01:17:27 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-eb12f1e5-1d5f-4f56-b322-d89bd1b79cef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3947652004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3947652004 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3337737094 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336575050000 ps |
| CPU time | 863.46 seconds |
| Started | Mar 24 12:36:34 PM PDT 24 |
| Finished | Mar 24 01:11:50 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-a737ff5f-9fe8-44e6-8b65-b0707c0d7e93 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3337737094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3337737094 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1131195504 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 337120290000 ps |
| CPU time | 711.91 seconds |
| Started | Mar 24 12:36:46 PM PDT 24 |
| Finished | Mar 24 01:06:22 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-7be8a1c9-8d8f-4998-ac42-e675f750d6cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1131195504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1131195504 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1980079558 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336809570000 ps |
| CPU time | 883.07 seconds |
| Started | Mar 24 12:36:45 PM PDT 24 |
| Finished | Mar 24 01:13:38 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-b3b0e46f-cd9e-4c40-bd93-e37e1eec502e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1980079558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1980079558 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.289275008 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336670970000 ps |
| CPU time | 955.24 seconds |
| Started | Mar 24 12:36:36 PM PDT 24 |
| Finished | Mar 24 01:16:31 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-f7702092-9b19-47d9-9de7-52cf2a20a6af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=289275008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.289275008 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3325848562 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336790730000 ps |
| CPU time | 564.39 seconds |
| Started | Mar 24 12:36:33 PM PDT 24 |
| Finished | Mar 24 01:00:59 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-683c9047-503c-4201-a6ca-bc9182314ba4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3325848562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3325848562 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3773932936 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336341110000 ps |
| CPU time | 695.76 seconds |
| Started | Mar 24 12:36:49 PM PDT 24 |
| Finished | Mar 24 01:05:10 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-dfdba170-d2d9-4f04-8721-4a7a026b8b99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3773932936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3773932936 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.808214683 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336400850000 ps |
| CPU time | 871.93 seconds |
| Started | Mar 24 12:36:50 PM PDT 24 |
| Finished | Mar 24 01:12:58 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-e5e934d9-2b34-4fc5-9c2d-a780f5887ab2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=808214683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.808214683 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3312996556 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 337137670000 ps |
| CPU time | 727.34 seconds |
| Started | Mar 24 12:36:49 PM PDT 24 |
| Finished | Mar 24 01:06:51 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-39bf16cb-eb93-4097-bed8-70f2ef18042d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3312996556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3312996556 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.435577032 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336871890000 ps |
| CPU time | 558.45 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 01:00:42 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-c7087783-5d79-4278-b84d-dcd71d4d1712 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=435577032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.435577032 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2093752420 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336895290000 ps |
| CPU time | 643.6 seconds |
| Started | Mar 24 12:36:43 PM PDT 24 |
| Finished | Mar 24 01:03:21 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-6df9742c-f3f8-43c5-8186-ac4f1570ce9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2093752420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2093752420 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.366323764 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336914730000 ps |
| CPU time | 771.83 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 01:08:44 PM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-98e0d864-9ff2-4801-a3c5-c5a6b99a3e27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=366323764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.366323764 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.217935254 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 337057510000 ps |
| CPU time | 963.73 seconds |
| Started | Mar 24 12:36:58 PM PDT 24 |
| Finished | Mar 24 01:16:55 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-d23a2428-8ed1-44e9-b819-1d24c009478f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=217935254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.217935254 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3104519164 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 337054070000 ps |
| CPU time | 805.81 seconds |
| Started | Mar 24 12:36:52 PM PDT 24 |
| Finished | Mar 24 01:10:10 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-d65c1705-ca15-41eb-b372-cda376815bde |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3104519164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3104519164 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.646636797 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336661030000 ps |
| CPU time | 824.75 seconds |
| Started | Mar 24 12:36:39 PM PDT 24 |
| Finished | Mar 24 01:10:51 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-40148c09-c32d-42c4-a860-d810505a9171 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=646636797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.646636797 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.431887389 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336920830000 ps |
| CPU time | 700.88 seconds |
| Started | Mar 24 12:36:50 PM PDT 24 |
| Finished | Mar 24 01:05:26 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-3947ea39-a7eb-42d5-bf6e-21ff3a42f319 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=431887389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.431887389 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2636766869 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336882130000 ps |
| CPU time | 773.07 seconds |
| Started | Mar 24 12:36:45 PM PDT 24 |
| Finished | Mar 24 01:08:27 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-f92ce623-52ac-4b0c-be7b-51912e9c6001 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2636766869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2636766869 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1285397133 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336398190000 ps |
| CPU time | 618.77 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 01:02:52 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-bd839455-6a08-4e67-806a-7fefd7fcd321 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1285397133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1285397133 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.422320401 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336450090000 ps |
| CPU time | 855.81 seconds |
| Started | Mar 24 12:37:15 PM PDT 24 |
| Finished | Mar 24 01:12:19 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-2059d41a-eda7-4697-b109-7165eeb539da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=422320401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.422320401 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.48079712 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336367030000 ps |
| CPU time | 777.59 seconds |
| Started | Mar 24 12:36:45 PM PDT 24 |
| Finished | Mar 24 01:08:49 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-cf85eaf7-9f14-4a97-854a-44b3954c2fc9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=48079712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.48079712 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2110644379 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336640810000 ps |
| CPU time | 889.74 seconds |
| Started | Mar 24 12:36:28 PM PDT 24 |
| Finished | Mar 24 01:13:30 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-2982b207-f07a-4d05-9d28-195c1d589f83 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2110644379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2110644379 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1729377054 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 337049510000 ps |
| CPU time | 965.3 seconds |
| Started | Mar 24 12:36:54 PM PDT 24 |
| Finished | Mar 24 01:16:50 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-2162ab01-6084-4557-90b3-445db0279971 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1729377054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1729377054 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1837401779 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336484130000 ps |
| CPU time | 851.35 seconds |
| Started | Mar 24 12:36:36 PM PDT 24 |
| Finished | Mar 24 01:11:29 PM PDT 24 |
| Peak memory | 160940 kb |
| Host | smart-ee26e278-a946-47c4-a984-71245c549bef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1837401779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1837401779 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3935794849 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336636570000 ps |
| CPU time | 879.75 seconds |
| Started | Mar 24 12:36:42 PM PDT 24 |
| Finished | Mar 24 01:13:18 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-bdadf39a-21c6-47de-8c68-61305cf74511 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3935794849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3935794849 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3843215658 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336355230000 ps |
| CPU time | 995.06 seconds |
| Started | Mar 24 12:36:45 PM PDT 24 |
| Finished | Mar 24 01:17:38 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-20a39f73-1172-4896-b742-3cf7225dfc0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3843215658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3843215658 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3345722982 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336738010000 ps |
| CPU time | 904.11 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 01:14:38 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-eeb32ada-5c88-4d5c-b46c-3ab441aa38f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3345722982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3345722982 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1395427102 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336921330000 ps |
| CPU time | 647.57 seconds |
| Started | Mar 24 12:37:07 PM PDT 24 |
| Finished | Mar 24 01:03:55 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-24733d80-a8f4-44ed-ab22-19285cc61ba3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1395427102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1395427102 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3975526379 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336561930000 ps |
| CPU time | 847.78 seconds |
| Started | Mar 24 12:36:44 PM PDT 24 |
| Finished | Mar 24 01:11:42 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-33fe45b0-4ed3-4d37-8ba8-aae7ddf45b14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3975526379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3975526379 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1412453061 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336385710000 ps |
| CPU time | 897.53 seconds |
| Started | Mar 24 12:36:39 PM PDT 24 |
| Finished | Mar 24 01:14:13 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-067c9bd6-7743-4fef-9c91-4cfe8d3daa34 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1412453061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1412453061 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.954855156 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336792390000 ps |
| CPU time | 934.74 seconds |
| Started | Mar 24 12:36:53 PM PDT 24 |
| Finished | Mar 24 01:15:32 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-4143321b-6a7b-426c-aa73-4e93678873e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=954855156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.954855156 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2791978867 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336865990000 ps |
| CPU time | 961.42 seconds |
| Started | Mar 24 12:36:54 PM PDT 24 |
| Finished | Mar 24 01:17:21 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-9b959283-c91d-4e8f-8854-8f4b651dd98a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2791978867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2791978867 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2632363432 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336852550000 ps |
| CPU time | 666.77 seconds |
| Started | Mar 24 12:36:44 PM PDT 24 |
| Finished | Mar 24 01:04:10 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-5ca6a24c-8dcf-4b00-8992-da9fb978c4c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2632363432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2632363432 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2689585872 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336595370000 ps |
| CPU time | 758.79 seconds |
| Started | Mar 24 12:36:38 PM PDT 24 |
| Finished | Mar 24 01:07:38 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-66ed5ce3-90e5-43fb-b845-56a2b83042c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2689585872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2689585872 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3860167783 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336621950000 ps |
| CPU time | 758.96 seconds |
| Started | Mar 24 12:36:48 PM PDT 24 |
| Finished | Mar 24 01:07:47 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-95a00b0d-7e16-4e59-b28a-0c84a0b9a904 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3860167783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3860167783 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.998987439 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336635850000 ps |
| CPU time | 786.17 seconds |
| Started | Mar 24 12:36:47 PM PDT 24 |
| Finished | Mar 24 01:08:58 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-6fa72c59-2c7b-4f0a-b885-5d5635b0d8c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=998987439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.998987439 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2613527387 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336679950000 ps |
| CPU time | 828.83 seconds |
| Started | Mar 24 12:37:03 PM PDT 24 |
| Finished | Mar 24 01:11:08 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-c5b451ea-c898-4e80-9b3e-64c78de405df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2613527387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2613527387 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3300563780 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336881410000 ps |
| CPU time | 748.11 seconds |
| Started | Mar 24 12:36:50 PM PDT 24 |
| Finished | Mar 24 01:07:56 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-6c42c9f0-3e8e-472b-a023-c63f82093855 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3300563780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3300563780 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.250407528 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336510370000 ps |
| CPU time | 810.44 seconds |
| Started | Mar 24 12:36:55 PM PDT 24 |
| Finished | Mar 24 01:10:23 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-74199216-90c6-4567-aadc-7d3b1d74bd1a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=250407528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.250407528 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3879236549 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336612210000 ps |
| CPU time | 912.44 seconds |
| Started | Mar 24 12:36:33 PM PDT 24 |
| Finished | Mar 24 01:14:58 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-484fd1ce-7341-436f-955c-ff2311260e6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3879236549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3879236549 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3095906914 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336499010000 ps |
| CPU time | 857.28 seconds |
| Started | Mar 24 12:36:48 PM PDT 24 |
| Finished | Mar 24 01:11:57 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-c619a647-a104-44f2-b722-c75da69a16e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3095906914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3095906914 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3748557280 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336945210000 ps |
| CPU time | 669.01 seconds |
| Started | Mar 24 12:36:42 PM PDT 24 |
| Finished | Mar 24 01:04:56 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-af0ad345-c05a-4346-ae8b-3dd7512da8c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3748557280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3748557280 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.486016762 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336775570000 ps |
| CPU time | 860.7 seconds |
| Started | Mar 24 12:36:48 PM PDT 24 |
| Finished | Mar 24 01:12:18 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-d9b74a25-6532-471e-8b8e-160b17a8d6f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=486016762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.486016762 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1613494856 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1221810000 ps |
| CPU time | 2.46 seconds |
| Started | Mar 24 12:36:50 PM PDT 24 |
| Finished | Mar 24 12:36:56 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-79fd3c14-c05d-4284-8a23-4cda9f022d86 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1613494856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1613494856 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3962368111 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1565850000 ps |
| CPU time | 3.54 seconds |
| Started | Mar 24 12:36:35 PM PDT 24 |
| Finished | Mar 24 12:36:43 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-14adbe7b-fc1e-4eaf-935e-3a20917f0d07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3962368111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3962368111 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.208535547 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1350290000 ps |
| CPU time | 4.13 seconds |
| Started | Mar 24 12:36:49 PM PDT 24 |
| Finished | Mar 24 12:36:59 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-b06fb3f9-7813-44a3-9859-ede83ee661f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=208535547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.208535547 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3146450126 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1614210000 ps |
| CPU time | 3.14 seconds |
| Started | Mar 24 12:36:22 PM PDT 24 |
| Finished | Mar 24 12:36:30 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-c1f9c87d-3c68-453d-bb0d-80ced735a1d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3146450126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3146450126 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1769178603 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1552490000 ps |
| CPU time | 3.19 seconds |
| Started | Mar 24 12:36:34 PM PDT 24 |
| Finished | Mar 24 12:36:42 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-ab8e7952-cd8b-44e0-8d02-94373ac041ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1769178603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1769178603 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.856133293 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1543630000 ps |
| CPU time | 3.15 seconds |
| Started | Mar 24 12:36:26 PM PDT 24 |
| Finished | Mar 24 12:36:34 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-11300845-48be-4f2e-a709-235e441aad66 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=856133293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.856133293 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1701749310 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1544550000 ps |
| CPU time | 3.9 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 12:36:52 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-8e498399-99ac-4735-b4ec-84a3804bbb12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1701749310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1701749310 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1886936327 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1408150000 ps |
| CPU time | 3.94 seconds |
| Started | Mar 24 12:36:44 PM PDT 24 |
| Finished | Mar 24 12:36:53 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-cb19a119-b838-4ee0-babe-b344a255feb7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1886936327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1886936327 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.548139280 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1510010000 ps |
| CPU time | 3.39 seconds |
| Started | Mar 24 12:36:42 PM PDT 24 |
| Finished | Mar 24 12:36:51 PM PDT 24 |
| Peak memory | 165012 kb |
| Host | smart-50df1fba-e353-4988-98fe-6347235c45d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=548139280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.548139280 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1094627678 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1462710000 ps |
| CPU time | 4.18 seconds |
| Started | Mar 24 12:36:40 PM PDT 24 |
| Finished | Mar 24 12:36:52 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-f4517007-19ed-4418-af5d-767101f49629 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1094627678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1094627678 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.190156930 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1494010000 ps |
| CPU time | 3.18 seconds |
| Started | Mar 24 12:36:40 PM PDT 24 |
| Finished | Mar 24 12:36:50 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-2092e727-4b25-4a66-9429-0029c43c3e9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=190156930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.190156930 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1879792447 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1407990000 ps |
| CPU time | 3.17 seconds |
| Started | Mar 24 12:36:29 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-37767e19-dafc-4931-95ec-6cc053d1be35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1879792447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1879792447 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.419000735 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1421150000 ps |
| CPU time | 3.05 seconds |
| Started | Mar 24 12:36:27 PM PDT 24 |
| Finished | Mar 24 12:36:36 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-5d3bdd7d-4977-4cb8-9ac7-b3f7eed62049 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=419000735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.419000735 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1791197210 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1510670000 ps |
| CPU time | 3.36 seconds |
| Started | Mar 24 12:36:28 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 165012 kb |
| Host | smart-1e095757-5a0c-40f4-90f9-6e48ebdb9cc7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1791197210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1791197210 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1219678294 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1321250000 ps |
| CPU time | 3.42 seconds |
| Started | Mar 24 12:36:51 PM PDT 24 |
| Finished | Mar 24 12:37:00 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-b3753a5f-b9e4-4fd3-9f05-a5133eca01f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1219678294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1219678294 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1698184255 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1427710000 ps |
| CPU time | 2.94 seconds |
| Started | Mar 24 12:36:32 PM PDT 24 |
| Finished | Mar 24 12:36:40 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-18e54815-29a8-4c15-aad4-82258cde0e52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1698184255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1698184255 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.466095295 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1417830000 ps |
| CPU time | 3.91 seconds |
| Started | Mar 24 12:36:45 PM PDT 24 |
| Finished | Mar 24 12:36:54 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-00037664-9b8c-444b-b82b-a6618d0e1e4e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=466095295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.466095295 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1780752326 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1443390000 ps |
| CPU time | 4.31 seconds |
| Started | Mar 24 12:36:47 PM PDT 24 |
| Finished | Mar 24 12:36:58 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-554bed30-b1a5-400d-9b56-8d6d1eade943 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1780752326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1780752326 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2976713806 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1067670000 ps |
| CPU time | 2.49 seconds |
| Started | Mar 24 12:36:36 PM PDT 24 |
| Finished | Mar 24 12:36:42 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-c823bbfd-09c9-4df5-a7c6-7ec8e83b7401 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2976713806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2976713806 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2425593755 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1243150000 ps |
| CPU time | 2.47 seconds |
| Started | Mar 24 12:36:17 PM PDT 24 |
| Finished | Mar 24 12:36:23 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-8e10f632-4404-467b-a682-93e59c5d5df6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2425593755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2425593755 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3298334435 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1528810000 ps |
| CPU time | 4.43 seconds |
| Started | Mar 24 12:36:32 PM PDT 24 |
| Finished | Mar 24 12:36:42 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-bd46b503-0060-4aaf-8af0-9ffc43167a87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3298334435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3298334435 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.639255676 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1346810000 ps |
| CPU time | 3.46 seconds |
| Started | Mar 24 12:36:56 PM PDT 24 |
| Finished | Mar 24 12:37:04 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-e0dec86f-a215-460c-8aad-8988f1e1eb90 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=639255676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.639255676 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1102588502 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1321430000 ps |
| CPU time | 4.12 seconds |
| Started | Mar 24 12:36:38 PM PDT 24 |
| Finished | Mar 24 12:36:51 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-ac9e295b-7b11-46bf-a1f0-c46fcd3c39b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1102588502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1102588502 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2218949819 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1185290000 ps |
| CPU time | 2.71 seconds |
| Started | Mar 24 12:36:27 PM PDT 24 |
| Finished | Mar 24 12:36:36 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-a4ab0204-4de1-42fc-ad65-c25c85136a94 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2218949819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2218949819 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1261082367 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1402690000 ps |
| CPU time | 2.92 seconds |
| Started | Mar 24 12:36:42 PM PDT 24 |
| Finished | Mar 24 12:36:50 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-e7302858-9d25-4d68-805e-c4c009c75bd4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1261082367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1261082367 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2504763940 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1377470000 ps |
| CPU time | 2.79 seconds |
| Started | Mar 24 12:36:34 PM PDT 24 |
| Finished | Mar 24 12:36:41 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-8512198a-1eab-4478-931c-f6f92b68371e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2504763940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2504763940 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3884678987 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1358750000 ps |
| CPU time | 2.98 seconds |
| Started | Mar 24 12:36:29 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-54b7e619-32cf-4cfb-98e0-ee546f96cf9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3884678987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3884678987 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3425005179 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1585790000 ps |
| CPU time | 3.53 seconds |
| Started | Mar 24 12:36:33 PM PDT 24 |
| Finished | Mar 24 12:36:42 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-a1079f23-65a7-480f-a3bf-25784994b21a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3425005179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3425005179 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2734753008 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1380370000 ps |
| CPU time | 3.89 seconds |
| Started | Mar 24 12:36:42 PM PDT 24 |
| Finished | Mar 24 12:36:52 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-816aea73-d69a-4691-b304-538e85240994 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2734753008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2734753008 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.677661571 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1405390000 ps |
| CPU time | 3.53 seconds |
| Started | Mar 24 12:36:39 PM PDT 24 |
| Finished | Mar 24 12:36:51 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-aed35688-7085-4007-bf5f-dddc8a5dfdc8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=677661571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.677661571 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1608658884 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1527330000 ps |
| CPU time | 3.08 seconds |
| Started | Mar 24 12:36:22 PM PDT 24 |
| Finished | Mar 24 12:36:30 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-241ee906-f376-4038-8a29-9893b9ddc5b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1608658884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1608658884 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.389808791 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1084850000 ps |
| CPU time | 2.61 seconds |
| Started | Mar 24 12:36:31 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-2e5bd68e-6601-4f93-b5bc-7ea165c81e9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=389808791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.389808791 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.114640628 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1558750000 ps |
| CPU time | 3.53 seconds |
| Started | Mar 24 12:36:32 PM PDT 24 |
| Finished | Mar 24 12:36:41 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-66b6e404-664a-41c4-972f-cb0bc20757bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=114640628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.114640628 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3752558786 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1592270000 ps |
| CPU time | 3.34 seconds |
| Started | Mar 24 12:36:52 PM PDT 24 |
| Finished | Mar 24 12:37:00 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-861220e9-f5d1-4902-92ee-d114318170b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3752558786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3752558786 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.925451971 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1484270000 ps |
| CPU time | 3.92 seconds |
| Started | Mar 24 12:36:30 PM PDT 24 |
| Finished | Mar 24 12:36:40 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-f3cff636-7b7f-4f7f-b58c-7a02c8bd334c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=925451971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.925451971 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3224537963 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1496510000 ps |
| CPU time | 3.91 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 12:36:52 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-99907fa6-0004-4807-a065-4259a28a6e7f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3224537963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3224537963 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1178132111 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1257870000 ps |
| CPU time | 2.65 seconds |
| Started | Mar 24 12:36:31 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-00e1a878-c963-4dce-b8ab-0013f19b315e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1178132111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1178132111 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2447428876 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1433050000 ps |
| CPU time | 2.76 seconds |
| Started | Mar 24 12:36:34 PM PDT 24 |
| Finished | Mar 24 12:36:41 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-02afa3ff-d48b-401e-a032-80ee5bddedae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2447428876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2447428876 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.799580185 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1574590000 ps |
| CPU time | 5.24 seconds |
| Started | Mar 24 12:36:46 PM PDT 24 |
| Finished | Mar 24 12:36:58 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-8b6236cb-64c8-4ec4-8bca-3c8514c7d4f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=799580185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.799580185 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.163089423 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1004510000 ps |
| CPU time | 2.44 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 12:36:48 PM PDT 24 |
| Peak memory | 165012 kb |
| Host | smart-eee7929e-bffb-4eff-b08e-12cbe5cf4779 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=163089423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.163089423 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.25729943 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1419830000 ps |
| CPU time | 3.09 seconds |
| Started | Mar 24 12:37:11 PM PDT 24 |
| Finished | Mar 24 12:37:19 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-954fd92b-d9ac-4c5c-a88a-3368c802d24b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=25729943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.25729943 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2008593295 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1384590000 ps |
| CPU time | 4.33 seconds |
| Started | Mar 24 12:36:48 PM PDT 24 |
| Finished | Mar 24 12:36:58 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-8bdfff54-3432-4e98-b08d-51fe90d97b60 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2008593295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2008593295 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1386479233 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1432650000 ps |
| CPU time | 3.14 seconds |
| Started | Mar 24 12:36:50 PM PDT 24 |
| Finished | Mar 24 12:36:58 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-c419923a-3682-4d7c-b9f7-466b085d7ec3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1386479233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1386479233 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1618294225 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1541030000 ps |
| CPU time | 4.96 seconds |
| Started | Mar 24 12:36:41 PM PDT 24 |
| Finished | Mar 24 12:37:04 PM PDT 24 |
| Peak memory | 165060 kb |
| Host | smart-d66944fd-e43d-4437-9cd4-2500c3860365 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1618294225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1618294225 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2573678812 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1606870000 ps |
| CPU time | 3.37 seconds |
| Started | Mar 24 12:36:28 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-885d1103-db00-4669-a5b1-3d2378932889 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2573678812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2573678812 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3475697758 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1474110000 ps |
| CPU time | 3.07 seconds |
| Started | Mar 24 12:36:28 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-ee0be0f6-06c5-43b8-8963-f72242a7e710 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3475697758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3475697758 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.166281434 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1284250000 ps |
| CPU time | 2.63 seconds |
| Started | Mar 24 12:36:27 PM PDT 24 |
| Finished | Mar 24 12:36:33 PM PDT 24 |
| Peak memory | 164736 kb |
| Host | smart-4aaf531e-3dbc-40b7-a7d7-3b5a10131de1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=166281434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.166281434 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1540173409 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1358870000 ps |
| CPU time | 3.11 seconds |
| Started | Mar 24 12:36:28 PM PDT 24 |
| Finished | Mar 24 12:36:37 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-b76fcbaa-5ade-47cc-be72-64f82f9a8fea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1540173409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1540173409 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2887326278 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1201590000 ps |
| CPU time | 3.74 seconds |
| Started | Mar 24 12:36:48 PM PDT 24 |
| Finished | Mar 24 12:36:57 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-25b6c30a-d3ce-4893-8ddd-295d8da4a461 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2887326278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2887326278 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1823339976 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1514930000 ps |
| CPU time | 3.42 seconds |
| Started | Mar 24 12:35:34 PM PDT 24 |
| Finished | Mar 24 12:35:42 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-d2b85b81-b519-423d-a5f8-6f9f043e1878 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1823339976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1823339976 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4025154753 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1441770000 ps |
| CPU time | 3.28 seconds |
| Started | Mar 24 12:35:45 PM PDT 24 |
| Finished | Mar 24 12:35:52 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-df1634e3-b416-4328-85df-7cf309e03583 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4025154753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4025154753 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2638365223 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1552710000 ps |
| CPU time | 3.37 seconds |
| Started | Mar 24 12:35:37 PM PDT 24 |
| Finished | Mar 24 12:35:45 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-e12b220d-ad76-471d-b420-b703fc7a616f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2638365223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2638365223 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1684916402 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1318290000 ps |
| CPU time | 2.85 seconds |
| Started | Mar 24 12:35:33 PM PDT 24 |
| Finished | Mar 24 12:35:39 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-09130703-764e-4133-8d20-52c0c503ee38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1684916402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1684916402 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.530136319 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1566130000 ps |
| CPU time | 3.78 seconds |
| Started | Mar 24 12:35:46 PM PDT 24 |
| Finished | Mar 24 12:35:55 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-7e65d49a-29b0-49b6-be53-c2963177ef83 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=530136319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.530136319 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4259970251 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1491630000 ps |
| CPU time | 3.13 seconds |
| Started | Mar 24 12:35:39 PM PDT 24 |
| Finished | Mar 24 12:35:46 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-f39265fd-55fe-450b-bac4-81cb76b524a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4259970251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.4259970251 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2807945998 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1360150000 ps |
| CPU time | 3.02 seconds |
| Started | Mar 24 12:35:56 PM PDT 24 |
| Finished | Mar 24 12:36:03 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-3b732c9b-fe20-483b-93e9-6cc7d564c7ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2807945998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2807945998 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1525277663 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1454110000 ps |
| CPU time | 3.33 seconds |
| Started | Mar 24 12:36:00 PM PDT 24 |
| Finished | Mar 24 12:36:08 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-83045765-21b7-4876-ae1f-d1d64560c4cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1525277663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1525277663 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3105373819 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1338050000 ps |
| CPU time | 2.87 seconds |
| Started | Mar 24 12:35:45 PM PDT 24 |
| Finished | Mar 24 12:35:57 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-a1dbd233-e75d-48ad-935e-590141a1d7b4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3105373819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3105373819 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3070927274 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1498730000 ps |
| CPU time | 3.38 seconds |
| Started | Mar 24 12:36:05 PM PDT 24 |
| Finished | Mar 24 12:36:17 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-0d6bc572-18c3-482f-94e3-e4b4b4ae108f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3070927274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3070927274 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3574755387 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1453610000 ps |
| CPU time | 3.12 seconds |
| Started | Mar 24 12:35:51 PM PDT 24 |
| Finished | Mar 24 12:35:58 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-b3c54822-67e4-4370-922d-0c0b35d3c6d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3574755387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3574755387 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1681879153 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1439630000 ps |
| CPU time | 3.12 seconds |
| Started | Mar 24 12:35:42 PM PDT 24 |
| Finished | Mar 24 12:35:49 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-abe1345f-a1e2-46ea-a60a-0bf40a3d01e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1681879153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1681879153 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4293447060 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1307290000 ps |
| CPU time | 3.16 seconds |
| Started | Mar 24 12:35:42 PM PDT 24 |
| Finished | Mar 24 12:35:49 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-adfcb26d-ea67-4bd4-ba11-f28231601daf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4293447060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4293447060 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.581290285 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1587930000 ps |
| CPU time | 3.12 seconds |
| Started | Mar 24 12:36:00 PM PDT 24 |
| Finished | Mar 24 12:36:08 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-67f2ed9f-7b8e-43b5-9ac0-5a482cc55994 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=581290285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.581290285 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2862379759 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1443690000 ps |
| CPU time | 3.36 seconds |
| Started | Mar 24 12:35:45 PM PDT 24 |
| Finished | Mar 24 12:35:53 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-2d31c40b-332b-4add-b9bd-6ac861838560 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2862379759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2862379759 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.721829535 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1057030000 ps |
| CPU time | 2.66 seconds |
| Started | Mar 24 12:35:37 PM PDT 24 |
| Finished | Mar 24 12:35:43 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-feb71619-1246-4f49-a5d3-c629474512e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=721829535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.721829535 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.293591759 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1433370000 ps |
| CPU time | 3.29 seconds |
| Started | Mar 24 12:35:44 PM PDT 24 |
| Finished | Mar 24 12:35:51 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-35b0ff59-286d-4bcd-951a-f385eb57f64c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=293591759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.293591759 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.667296740 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1483490000 ps |
| CPU time | 3.32 seconds |
| Started | Mar 24 12:36:01 PM PDT 24 |
| Finished | Mar 24 12:36:09 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-4dfa8bf5-a4b9-4af5-bc21-aa9e39ee5520 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=667296740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.667296740 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1353778942 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1546570000 ps |
| CPU time | 3.7 seconds |
| Started | Mar 24 12:35:53 PM PDT 24 |
| Finished | Mar 24 12:36:01 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-43357faa-efd3-4bf0-8592-92a6e92d69d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1353778942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1353778942 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1907896796 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1508430000 ps |
| CPU time | 3.17 seconds |
| Started | Mar 24 12:35:48 PM PDT 24 |
| Finished | Mar 24 12:35:56 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-07a6fe0e-f814-496c-8171-0b34454ed917 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1907896796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1907896796 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.835398450 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1510350000 ps |
| CPU time | 4.11 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:15 PM PDT 24 |
| Peak memory | 164688 kb |
| Host | smart-3b4e3102-2fe3-4100-ae6c-634c9dfb149f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=835398450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.835398450 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2714612420 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1543210000 ps |
| CPU time | 4.11 seconds |
| Started | Mar 24 12:35:54 PM PDT 24 |
| Finished | Mar 24 12:36:04 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-d97415c8-3afe-43fb-80a7-ae7c44ed5d69 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2714612420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2714612420 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3535532318 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1547050000 ps |
| CPU time | 3.46 seconds |
| Started | Mar 24 12:35:51 PM PDT 24 |
| Finished | Mar 24 12:35:59 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-cd5e5700-121d-45c6-b7af-8d565332980a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3535532318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3535532318 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2278140023 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1488450000 ps |
| CPU time | 3.28 seconds |
| Started | Mar 24 12:35:53 PM PDT 24 |
| Finished | Mar 24 12:36:00 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-cdbf9e02-83b6-45de-82ce-a0649b84ea36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2278140023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2278140023 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2110870756 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1420530000 ps |
| CPU time | 2.89 seconds |
| Started | Mar 24 12:35:46 PM PDT 24 |
| Finished | Mar 24 12:35:52 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-1ee0bf69-dd42-4726-92a4-a9e6b38628e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2110870756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2110870756 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4125415805 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1501630000 ps |
| CPU time | 3.8 seconds |
| Started | Mar 24 12:35:44 PM PDT 24 |
| Finished | Mar 24 12:35:53 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-00b6eb7c-a365-45a5-b780-2997f18efc6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4125415805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4125415805 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3932790710 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1384770000 ps |
| CPU time | 3.01 seconds |
| Started | Mar 24 12:36:08 PM PDT 24 |
| Finished | Mar 24 12:36:14 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-1e871037-2985-4bae-88e9-4d579df4c79d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3932790710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3932790710 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1281795112 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1504610000 ps |
| CPU time | 3.95 seconds |
| Started | Mar 24 12:36:09 PM PDT 24 |
| Finished | Mar 24 12:36:18 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-484d103d-edcd-4382-9a3d-765ab363ecce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1281795112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1281795112 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2830874559 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1551750000 ps |
| CPU time | 3.55 seconds |
| Started | Mar 24 12:35:51 PM PDT 24 |
| Finished | Mar 24 12:35:59 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-e0a426be-5fd6-4fbf-9472-935620eeb105 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2830874559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2830874559 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2500728139 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1592610000 ps |
| CPU time | 3.83 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:03 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-137c13c8-b943-4066-a282-12e65e319628 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2500728139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2500728139 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1820881594 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1555430000 ps |
| CPU time | 2.93 seconds |
| Started | Mar 24 12:35:47 PM PDT 24 |
| Finished | Mar 24 12:35:53 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-d3b70906-dfd0-4d0d-9ecf-7ce0c038a1ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1820881594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1820881594 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1088737601 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1605590000 ps |
| CPU time | 3.17 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:02 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-cdc11a97-f0a6-48a9-a069-caf917312c22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1088737601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1088737601 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1726262914 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1327410000 ps |
| CPU time | 3.01 seconds |
| Started | Mar 24 12:36:01 PM PDT 24 |
| Finished | Mar 24 12:36:09 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-e27d1003-955a-4e25-a272-b038625fa566 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1726262914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1726262914 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.4047701446 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1545250000 ps |
| CPU time | 3.33 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:03 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-3d53cf57-435e-4580-9327-e055e72ac290 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4047701446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.4047701446 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1436354730 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1180210000 ps |
| CPU time | 2.79 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:04 PM PDT 24 |
| Peak memory | 164684 kb |
| Host | smart-52fffc7d-30f4-4ef5-af8d-d47ede16fe5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1436354730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1436354730 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.182674461 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1327230000 ps |
| CPU time | 2.7 seconds |
| Started | Mar 24 12:35:42 PM PDT 24 |
| Finished | Mar 24 12:35:48 PM PDT 24 |
| Peak memory | 164688 kb |
| Host | smart-a88e294b-5fa6-43c9-bb8f-0a5f34ceee01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=182674461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.182674461 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1996597078 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1462970000 ps |
| CPU time | 4.28 seconds |
| Started | Mar 24 12:35:54 PM PDT 24 |
| Finished | Mar 24 12:36:04 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-69afb3d0-d6df-4106-995c-f0eecfef34b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1996597078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1996597078 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3005099351 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1317990000 ps |
| CPU time | 2.85 seconds |
| Started | Mar 24 12:35:51 PM PDT 24 |
| Finished | Mar 24 12:35:58 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-88bd219f-67a8-43f0-8c7e-097d51d2fabc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3005099351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3005099351 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.783887691 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1285070000 ps |
| CPU time | 2.78 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:04 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-56de385b-56bb-4a13-8acb-b338eced17f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=783887691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.783887691 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.829174532 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1258890000 ps |
| CPU time | 2.94 seconds |
| Started | Mar 24 12:36:01 PM PDT 24 |
| Finished | Mar 24 12:36:08 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-7e684f15-3ae2-4c2b-bbcd-dfd1a79c05e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=829174532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.829174532 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4177480522 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1464890000 ps |
| CPU time | 3.11 seconds |
| Started | Mar 24 12:35:35 PM PDT 24 |
| Finished | Mar 24 12:35:43 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-23035dda-d265-432d-b7d7-6de5fd99a77a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4177480522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4177480522 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3797434046 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1313070000 ps |
| CPU time | 3.95 seconds |
| Started | Mar 24 12:35:51 PM PDT 24 |
| Finished | Mar 24 12:36:00 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-6446b29a-5310-4a6d-b938-40ca69f909de |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3797434046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3797434046 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2393625225 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1460110000 ps |
| CPU time | 3.59 seconds |
| Started | Mar 24 12:36:00 PM PDT 24 |
| Finished | Mar 24 12:36:08 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-6b61cb8d-8456-4613-90e0-74e2cce892dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2393625225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2393625225 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2684712518 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1380290000 ps |
| CPU time | 3.31 seconds |
| Started | Mar 24 12:35:55 PM PDT 24 |
| Finished | Mar 24 12:36:03 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-948d5e82-f39b-4d4c-8a7f-8ea3c4d3dc81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2684712518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2684712518 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3458129231 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1449030000 ps |
| CPU time | 3.57 seconds |
| Started | Mar 24 12:35:36 PM PDT 24 |
| Finished | Mar 24 12:35:44 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-67178515-9f58-4609-b069-a39ccd3d0693 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3458129231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3458129231 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3208912413 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1188490000 ps |
| CPU time | 3.25 seconds |
| Started | Mar 24 12:35:56 PM PDT 24 |
| Finished | Mar 24 12:36:03 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-198ca313-fc78-45cc-8f00-18fc75ccee07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3208912413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3208912413 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.231422707 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1349010000 ps |
| CPU time | 3.11 seconds |
| Started | Mar 24 12:36:06 PM PDT 24 |
| Finished | Mar 24 12:36:13 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-70c3ed09-639e-426b-bbb5-051689bcd61a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=231422707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.231422707 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1864645855 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1577710000 ps |
| CPU time | 3.46 seconds |
| Started | Mar 24 12:35:28 PM PDT 24 |
| Finished | Mar 24 12:35:38 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-d010d121-1ac7-47f0-9139-64b9f3106f87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1864645855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1864645855 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.472004295 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1281570000 ps |
| CPU time | 2.85 seconds |
| Started | Mar 24 12:35:33 PM PDT 24 |
| Finished | Mar 24 12:35:40 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-f93794e9-f444-4e30-b449-acb4c0047ba2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=472004295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.472004295 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |