Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1967665335
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2630642643
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1021192093
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.751287698

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2734778701
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.545151515
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3139243305
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2108111849
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4124847804
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3672591323
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2052267811
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.862156055
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.702949475
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1491306611
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2356217661
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1687007911
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.918744932
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3837485468
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.945285847
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1543972570
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.848187178
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.805038972
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3885064248
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1830366223
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1908104256
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.756681970
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2908212384
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1723148437
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3749255252
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.686076732
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3515723890
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.618155069
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2199433028
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1415993324
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2836306302
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3512174025
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.732234311
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3336881554
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4211498639
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3923633211
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1932825084
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2073742668
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1549481706
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1822739680
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.666643421
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1959193303
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3750110547
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1955448833
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3110843524
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3184556862
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3084827780
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1050395518
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3123849914
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2543129700
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1278424361
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1727879402
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2461739375
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2232441797
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3903067586
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4079121647
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2926196169
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.945077084
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4254906650
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.556427621
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2864087700
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2410297368
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.934587582
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3709837404
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.418576172
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.111309576
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2080965942
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1160753373
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3469815325
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2878143231
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2829634267
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2262106291
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.428091309
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.846080557
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1356168746
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2089389713
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.5889063
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3071269450
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1186553294
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4223719781
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4122786905
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1995024616
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3633595362
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2273383811
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3261480171
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4178436655
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2538897777
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2873429570
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1632655942
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1051953108
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1901936260
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.999268033
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1127833473
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2359777486
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1594357350
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.759022583
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3982623629
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3091794348
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.259856510
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.391453728
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.40548924
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3215377414
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.441322398
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3348340661
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.675376845
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3707858495
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.78412385
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3980999436
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.618787660
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4003204284
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3838431647
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3647690667
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2532760456
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.889295822
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4102738488
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.235167513
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2283670975
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2961814961
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3305570612
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.859362479
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2155328031
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2093629401
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4136103524
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2289000239
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3707564609
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2331516070
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3082109121
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3732306521
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2483752936
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3266352662
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3676727762
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1537903035
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3900725050
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4152143687
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3113143783
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1068559806
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.774171294
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1842542295
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1614735419
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.605342518
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3752043682
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2905064959
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3177504292
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1321318593
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4016964609
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.524933756
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1279517791
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4038523141
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.277968630
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3135157056
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2057014658
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3492982664
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.378025625
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1841411643
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1785648093
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2308894156
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4183152486
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3030870176
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4252981436
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1590027510
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3026465525
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3664890320
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4241237121
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.228325226
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1010693389
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3562914525
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4066473838
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1952983994
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.8268947
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.314683348
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2477203313
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1972968491
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1467596225
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2750399143
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.873512263
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3205591747
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1877365911
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.797550784
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1133817996
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3422344728
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2234320019
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3027641504
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2768150477
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2213964854
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3937781654
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3559382218
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2666196569
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2661819718
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2041536739
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1200375373
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2355271882
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.428886231
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1856726006
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3654904238
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1997592575
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1468205316



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3026465525 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:04 PM PDT 24 1556630000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1010693389 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:02 PM PDT 24 1368570000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.873512263 Mar 26 01:50:59 PM PDT 24 Mar 26 01:51:08 PM PDT 24 1485250000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.797550784 Mar 26 01:50:54 PM PDT 24 Mar 26 01:51:04 PM PDT 24 1583870000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1997592575 Mar 26 01:50:51 PM PDT 24 Mar 26 01:51:03 PM PDT 24 1461990000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1972968491 Mar 26 01:50:52 PM PDT 24 Mar 26 01:51:01 PM PDT 24 1569670000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2041536739 Mar 26 01:51:07 PM PDT 24 Mar 26 01:51:16 PM PDT 24 1554050000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2661819718 Mar 26 01:51:00 PM PDT 24 Mar 26 01:51:10 PM PDT 24 1109670000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3030870176 Mar 26 01:50:55 PM PDT 24 Mar 26 01:51:05 PM PDT 24 1597310000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1967665335 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:56 PM PDT 24 1604870000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1841411643 Mar 26 01:50:45 PM PDT 24 Mar 26 01:50:54 PM PDT 24 1109430000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3492982664 Mar 26 01:50:51 PM PDT 24 Mar 26 01:51:02 PM PDT 24 1504970000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.277968630 Mar 26 01:50:51 PM PDT 24 Mar 26 01:51:03 PM PDT 24 1559110000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2213964854 Mar 26 01:51:05 PM PDT 24 Mar 26 01:51:16 PM PDT 24 1404310000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4183152486 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:03 PM PDT 24 1368590000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3559382218 Mar 26 01:51:07 PM PDT 24 Mar 26 01:51:16 PM PDT 24 1417870000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1785648093 Mar 26 01:50:52 PM PDT 24 Mar 26 01:51:01 PM PDT 24 1561330000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1468205316 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:54 PM PDT 24 1546690000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2477203313 Mar 26 01:50:54 PM PDT 24 Mar 26 01:51:04 PM PDT 24 1386850000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1856726006 Mar 26 01:50:45 PM PDT 24 Mar 26 01:50:55 PM PDT 24 1307290000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2768150477 Mar 26 01:51:00 PM PDT 24 Mar 26 01:51:07 PM PDT 24 1493550000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2750399143 Mar 26 01:50:52 PM PDT 24 Mar 26 01:51:02 PM PDT 24 1311350000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3654904238 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:03 PM PDT 24 1418970000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.378025625 Mar 26 01:50:50 PM PDT 24 Mar 26 01:51:03 PM PDT 24 1548390000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2057014658 Mar 26 01:50:45 PM PDT 24 Mar 26 01:50:57 PM PDT 24 1589370000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.228325226 Mar 26 01:50:58 PM PDT 24 Mar 26 01:51:07 PM PDT 24 1418130000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4252981436 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:55 PM PDT 24 1545410000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2234320019 Mar 26 01:50:45 PM PDT 24 Mar 26 01:51:00 PM PDT 24 1530770000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3562914525 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:05 PM PDT 24 1332850000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3664890320 Mar 26 01:50:52 PM PDT 24 Mar 26 01:51:07 PM PDT 24 1511550000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.428886231 Mar 26 01:50:45 PM PDT 24 Mar 26 01:50:58 PM PDT 24 1518870000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2666196569 Mar 26 01:51:01 PM PDT 24 Mar 26 01:51:12 PM PDT 24 1540190000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3205591747 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:07 PM PDT 24 1555670000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4241237121 Mar 26 01:50:54 PM PDT 24 Mar 26 01:51:05 PM PDT 24 1512590000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3937781654 Mar 26 01:51:02 PM PDT 24 Mar 26 01:51:10 PM PDT 24 1568490000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1952983994 Mar 26 01:51:00 PM PDT 24 Mar 26 01:51:09 PM PDT 24 1529590000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1133817996 Mar 26 01:50:59 PM PDT 24 Mar 26 01:51:06 PM PDT 24 1169050000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.8268947 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:05 PM PDT 24 1559010000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2308894156 Mar 26 01:50:56 PM PDT 24 Mar 26 01:51:08 PM PDT 24 1608510000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4038523141 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:52 PM PDT 24 1316350000 ps
T71 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1877365911 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:04 PM PDT 24 1464110000 ps
T72 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1467596225 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:06 PM PDT 24 1365350000 ps
T73 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2355271882 Mar 26 01:51:02 PM PDT 24 Mar 26 01:51:11 PM PDT 24 1275190000 ps
T74 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1590027510 Mar 26 01:50:54 PM PDT 24 Mar 26 01:51:07 PM PDT 24 1397330000 ps
T75 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3027641504 Mar 26 01:51:05 PM PDT 24 Mar 26 01:51:15 PM PDT 24 1285310000 ps
T76 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1200375373 Mar 26 01:51:05 PM PDT 24 Mar 26 01:51:13 PM PDT 24 1340910000 ps
T77 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3422344728 Mar 26 01:51:07 PM PDT 24 Mar 26 01:51:16 PM PDT 24 1429050000 ps
T78 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4066473838 Mar 26 01:50:53 PM PDT 24 Mar 26 01:51:06 PM PDT 24 1580090000 ps
T79 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3135157056 Mar 26 01:50:47 PM PDT 24 Mar 26 01:50:58 PM PDT 24 1311790000 ps
T80 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.314683348 Mar 26 01:50:45 PM PDT 24 Mar 26 01:50:56 PM PDT 24 1355410000 ps
T5 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3732306521 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:50 PM PDT 24 1429890000 ps
T6 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1068559806 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:50 PM PDT 24 1334570000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3707564609 Mar 26 01:50:37 PM PDT 24 Mar 26 01:50:48 PM PDT 24 1529450000 ps
T24 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3348340661 Mar 26 01:50:30 PM PDT 24 Mar 26 01:50:41 PM PDT 24 1538830000 ps
T25 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2905064959 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:56 PM PDT 24 1446870000 ps
T26 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.751287698 Mar 26 01:50:22 PM PDT 24 Mar 26 01:50:32 PM PDT 24 1207670000 ps
T27 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3177504292 Mar 26 01:50:21 PM PDT 24 Mar 26 01:50:27 PM PDT 24 1248370000 ps
T28 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1279517791 Mar 26 01:50:21 PM PDT 24 Mar 26 01:50:32 PM PDT 24 1198070000 ps
T29 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3647690667 Mar 26 01:50:30 PM PDT 24 Mar 26 01:50:40 PM PDT 24 1569710000 ps
T30 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1842542295 Mar 26 01:50:38 PM PDT 24 Mar 26 01:50:48 PM PDT 24 1455370000 ps
T81 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.774171294 Mar 26 01:50:37 PM PDT 24 Mar 26 01:50:44 PM PDT 24 1307990000 ps
T82 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.78412385 Mar 26 01:50:31 PM PDT 24 Mar 26 01:50:38 PM PDT 24 1197690000 ps
T83 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.675376845 Mar 26 01:50:29 PM PDT 24 Mar 26 01:50:42 PM PDT 24 1300150000 ps
T84 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3082109121 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:52 PM PDT 24 1434190000 ps
T85 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.40548924 Mar 26 01:50:24 PM PDT 24 Mar 26 01:50:37 PM PDT 24 1395050000 ps
T86 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4016964609 Mar 26 01:50:21 PM PDT 24 Mar 26 01:50:33 PM PDT 24 1424270000 ps
T87 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1537903035 Mar 26 01:50:21 PM PDT 24 Mar 26 01:50:31 PM PDT 24 1379950000 ps
T88 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2289000239 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:46 PM PDT 24 1196130000 ps
T89 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.889295822 Mar 26 01:50:33 PM PDT 24 Mar 26 01:50:43 PM PDT 24 1601630000 ps
T90 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3707858495 Mar 26 01:50:30 PM PDT 24 Mar 26 01:50:42 PM PDT 24 1490730000 ps
T91 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1614735419 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:57 PM PDT 24 1357490000 ps
T92 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2331516070 Mar 26 01:50:44 PM PDT 24 Mar 26 01:50:54 PM PDT 24 1311970000 ps
T93 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3266352662 Mar 26 01:50:37 PM PDT 24 Mar 26 01:50:48 PM PDT 24 1347910000 ps
T94 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2155328031 Mar 26 01:50:21 PM PDT 24 Mar 26 01:50:30 PM PDT 24 1398490000 ps
T95 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3752043682 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:57 PM PDT 24 1538230000 ps
T96 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3838431647 Mar 26 01:50:31 PM PDT 24 Mar 26 01:50:40 PM PDT 24 1430470000 ps
T97 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2093629401 Mar 26 01:50:37 PM PDT 24 Mar 26 01:50:49 PM PDT 24 1509750000 ps
T98 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.391453728 Mar 26 01:50:22 PM PDT 24 Mar 26 01:50:34 PM PDT 24 1523250000 ps
T99 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3305570612 Mar 26 01:50:37 PM PDT 24 Mar 26 01:50:44 PM PDT 24 1441570000 ps
T100 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.441322398 Mar 26 01:50:30 PM PDT 24 Mar 26 01:50:37 PM PDT 24 1599890000 ps
T101 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4136103524 Mar 26 01:50:37 PM PDT 24 Mar 26 01:50:46 PM PDT 24 1590070000 ps
T102 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3980999436 Mar 26 01:50:31 PM PDT 24 Mar 26 01:50:40 PM PDT 24 1408510000 ps
T103 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3676727762 Mar 26 01:50:44 PM PDT 24 Mar 26 01:50:54 PM PDT 24 1374450000 ps
T104 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2961814961 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:50 PM PDT 24 1536990000 ps
T105 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.605342518 Mar 26 01:50:46 PM PDT 24 Mar 26 01:50:53 PM PDT 24 1540770000 ps
T106 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3900725050 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:52 PM PDT 24 1494030000 ps
T107 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.859362479 Mar 26 01:50:39 PM PDT 24 Mar 26 01:50:48 PM PDT 24 1527430000 ps
T108 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.259856510 Mar 26 01:50:23 PM PDT 24 Mar 26 01:50:34 PM PDT 24 1403330000 ps
T109 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.618787660 Mar 26 01:50:32 PM PDT 24 Mar 26 01:50:39 PM PDT 24 1480390000 ps
T110 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2283670975 Mar 26 01:50:30 PM PDT 24 Mar 26 01:50:40 PM PDT 24 1583910000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3113143783 Mar 26 01:50:38 PM PDT 24 Mar 26 01:50:50 PM PDT 24 1505950000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2483752936 Mar 26 01:50:44 PM PDT 24 Mar 26 01:50:55 PM PDT 24 1506910000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4102738488 Mar 26 01:50:29 PM PDT 24 Mar 26 01:50:41 PM PDT 24 1337450000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2532760456 Mar 26 01:50:31 PM PDT 24 Mar 26 01:50:40 PM PDT 24 1314110000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4152143687 Mar 26 01:50:44 PM PDT 24 Mar 26 01:50:54 PM PDT 24 1350690000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.235167513 Mar 26 01:50:31 PM PDT 24 Mar 26 01:50:42 PM PDT 24 1531870000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4003204284 Mar 26 01:50:24 PM PDT 24 Mar 26 01:50:32 PM PDT 24 1483330000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.524933756 Mar 26 01:50:21 PM PDT 24 Mar 26 01:50:34 PM PDT 24 1557110000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3215377414 Mar 26 01:50:22 PM PDT 24 Mar 26 01:50:31 PM PDT 24 1599130000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1321318593 Mar 26 01:50:23 PM PDT 24 Mar 26 01:50:32 PM PDT 24 1185650000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.756681970 Mar 26 02:00:35 PM PDT 24 Mar 26 02:36:50 PM PDT 24 336946750000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.666643421 Mar 26 02:00:38 PM PDT 24 Mar 26 02:39:11 PM PDT 24 336800290000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1908104256 Mar 26 02:00:39 PM PDT 24 Mar 26 02:35:15 PM PDT 24 336959490000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2630642643 Mar 26 02:00:27 PM PDT 24 Mar 26 02:30:34 PM PDT 24 336682850000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3750110547 Mar 26 02:00:38 PM PDT 24 Mar 26 02:40:54 PM PDT 24 336411630000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.545151515 Mar 26 02:00:32 PM PDT 24 Mar 26 02:37:04 PM PDT 24 336745130000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3512174025 Mar 26 02:00:35 PM PDT 24 Mar 26 02:34:07 PM PDT 24 336766210000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2836306302 Mar 26 02:00:37 PM PDT 24 Mar 26 02:34:57 PM PDT 24 336996690000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4124847804 Mar 26 02:00:32 PM PDT 24 Mar 26 02:33:54 PM PDT 24 336547710000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.848187178 Mar 26 02:00:41 PM PDT 24 Mar 26 02:41:44 PM PDT 24 336457630000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1932825084 Mar 26 02:00:37 PM PDT 24 Mar 26 02:43:31 PM PDT 24 336404510000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1549481706 Mar 26 02:00:36 PM PDT 24 Mar 26 02:34:12 PM PDT 24 336949710000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.805038972 Mar 26 02:00:38 PM PDT 24 Mar 26 02:40:15 PM PDT 24 337093010000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3110843524 Mar 26 02:00:27 PM PDT 24 Mar 26 02:37:41 PM PDT 24 336957750000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4211498639 Mar 26 02:00:39 PM PDT 24 Mar 26 02:37:20 PM PDT 24 336494410000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1723148437 Mar 26 02:00:37 PM PDT 24 Mar 26 02:33:58 PM PDT 24 336675250000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3885064248 Mar 26 02:00:41 PM PDT 24 Mar 26 02:41:46 PM PDT 24 336990490000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3184556862 Mar 26 02:00:27 PM PDT 24 Mar 26 02:34:15 PM PDT 24 337046070000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3837485468 Mar 26 02:00:35 PM PDT 24 Mar 26 02:38:53 PM PDT 24 336898610000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3515723890 Mar 26 02:00:38 PM PDT 24 Mar 26 02:37:13 PM PDT 24 336393490000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1415993324 Mar 26 02:00:38 PM PDT 24 Mar 26 02:40:25 PM PDT 24 336918550000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2356217661 Mar 26 02:00:39 PM PDT 24 Mar 26 02:33:51 PM PDT 24 336924730000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3336881554 Mar 26 02:00:31 PM PDT 24 Mar 26 02:30:00 PM PDT 24 336390730000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.702949475 Mar 26 02:00:37 PM PDT 24 Mar 26 02:38:13 PM PDT 24 336948490000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3749255252 Mar 26 02:00:37 PM PDT 24 Mar 26 02:34:48 PM PDT 24 336620010000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.686076732 Mar 26 02:00:41 PM PDT 24 Mar 26 02:41:54 PM PDT 24 336637710000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3123849914 Mar 26 02:00:29 PM PDT 24 Mar 26 02:28:37 PM PDT 24 336731710000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.862156055 Mar 26 02:00:38 PM PDT 24 Mar 26 02:33:51 PM PDT 24 337084770000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2199433028 Mar 26 02:00:39 PM PDT 24 Mar 26 02:34:07 PM PDT 24 336618910000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1543972570 Mar 26 02:00:37 PM PDT 24 Mar 26 02:41:28 PM PDT 24 336614990000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3084827780 Mar 26 02:00:28 PM PDT 24 Mar 26 02:33:55 PM PDT 24 336557710000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3923633211 Mar 26 02:00:39 PM PDT 24 Mar 26 02:35:56 PM PDT 24 336451970000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.945285847 Mar 26 02:00:36 PM PDT 24 Mar 26 02:38:11 PM PDT 24 336848410000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1955448833 Mar 26 02:00:37 PM PDT 24 Mar 26 02:43:38 PM PDT 24 336533390000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2734778701 Mar 26 02:00:29 PM PDT 24 Mar 26 02:35:58 PM PDT 24 336409910000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2052267811 Mar 26 02:00:40 PM PDT 24 Mar 26 02:46:48 PM PDT 24 336938230000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2108111849 Mar 26 02:00:31 PM PDT 24 Mar 26 02:33:55 PM PDT 24 336851270000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1050395518 Mar 26 02:00:32 PM PDT 24 Mar 26 02:32:38 PM PDT 24 336404310000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3672591323 Mar 26 02:00:38 PM PDT 24 Mar 26 02:34:16 PM PDT 24 336842390000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1822739680 Mar 26 02:00:40 PM PDT 24 Mar 26 02:47:05 PM PDT 24 336818010000 ps
T151 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2908212384 Mar 26 02:00:28 PM PDT 24 Mar 26 02:29:46 PM PDT 24 336541950000 ps
T152 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.618155069 Mar 26 02:00:39 PM PDT 24 Mar 26 02:37:24 PM PDT 24 336867790000 ps
T153 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1830366223 Mar 26 02:00:36 PM PDT 24 Mar 26 02:33:00 PM PDT 24 336770870000 ps
T154 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2073742668 Mar 26 02:00:38 PM PDT 24 Mar 26 02:35:00 PM PDT 24 336366570000 ps
T155 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1687007911 Mar 26 02:00:28 PM PDT 24 Mar 26 02:34:30 PM PDT 24 336683930000 ps
T156 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3139243305 Mar 26 02:00:31 PM PDT 24 Mar 26 02:30:32 PM PDT 24 337049930000 ps
T157 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.918744932 Mar 26 02:00:38 PM PDT 24 Mar 26 02:34:59 PM PDT 24 336360790000 ps
T158 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1959193303 Mar 26 02:00:37 PM PDT 24 Mar 26 02:43:38 PM PDT 24 336820450000 ps
T159 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.732234311 Mar 26 02:00:35 PM PDT 24 Mar 26 02:32:18 PM PDT 24 336863930000 ps
T160 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1491306611 Mar 26 02:00:38 PM PDT 24 Mar 26 02:35:13 PM PDT 24 336712470000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.759022583 Mar 26 02:00:39 PM PDT 24 Mar 26 02:37:24 PM PDT 24 336947530000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.111309576 Mar 26 02:00:39 PM PDT 24 Mar 26 02:38:42 PM PDT 24 336645910000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1632655942 Mar 26 02:00:48 PM PDT 24 Mar 26 02:37:24 PM PDT 24 336907550000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2262106291 Mar 26 02:00:39 PM PDT 24 Mar 26 02:39:32 PM PDT 24 336611130000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.428091309 Mar 26 02:00:53 PM PDT 24 Mar 26 02:41:45 PM PDT 24 336558830000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.934587582 Mar 26 02:00:35 PM PDT 24 Mar 26 02:36:55 PM PDT 24 336475310000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3091794348 Mar 26 02:00:36 PM PDT 24 Mar 26 02:39:23 PM PDT 24 336690830000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2273383811 Mar 26 02:00:49 PM PDT 24 Mar 26 02:32:13 PM PDT 24 336863190000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1901936260 Mar 26 02:00:51 PM PDT 24 Mar 26 02:28:33 PM PDT 24 336956470000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1021192093 Mar 26 02:00:41 PM PDT 24 Mar 26 02:42:06 PM PDT 24 336676610000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1127833473 Mar 26 02:00:51 PM PDT 24 Mar 26 02:36:12 PM PDT 24 336629030000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1186553294 Mar 26 02:00:49 PM PDT 24 Mar 26 02:38:25 PM PDT 24 336924970000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3982623629 Mar 26 02:00:34 PM PDT 24 Mar 26 02:31:41 PM PDT 24 336401070000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3261480171 Mar 26 02:00:53 PM PDT 24 Mar 26 02:33:28 PM PDT 24 336651150000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.846080557 Mar 26 02:00:50 PM PDT 24 Mar 26 02:30:24 PM PDT 24 336673670000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2461739375 Mar 26 02:00:41 PM PDT 24 Mar 26 02:42:32 PM PDT 24 337038870000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3709837404 Mar 26 02:00:38 PM PDT 24 Mar 26 02:39:06 PM PDT 24 336655690000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1995024616 Mar 26 02:00:49 PM PDT 24 Mar 26 02:26:42 PM PDT 24 336780730000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2359777486 Mar 26 02:00:37 PM PDT 24 Mar 26 02:34:11 PM PDT 24 336410110000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2080965942 Mar 26 02:00:36 PM PDT 24 Mar 26 02:32:17 PM PDT 24 336954750000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.418576172 Mar 26 02:00:41 PM PDT 24 Mar 26 02:42:19 PM PDT 24 336467050000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2926196169 Mar 26 02:00:38 PM PDT 24 Mar 26 02:41:40 PM PDT 24 336374090000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1594357350 Mar 26 02:00:38 PM PDT 24 Mar 26 02:36:24 PM PDT 24 337072650000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2089389713 Mar 26 02:00:50 PM PDT 24 Mar 26 02:34:03 PM PDT 24 336759830000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2410297368 Mar 26 02:00:41 PM PDT 24 Mar 26 02:41:45 PM PDT 24 337062210000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3903067586 Mar 26 02:00:39 PM PDT 24 Mar 26 02:39:21 PM PDT 24 336500010000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4223719781 Mar 26 02:00:52 PM PDT 24 Mar 26 02:35:55 PM PDT 24 336673390000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.556427621 Mar 26 02:00:36 PM PDT 24 Mar 26 02:39:06 PM PDT 24 336472270000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2878143231 Mar 26 02:00:36 PM PDT 24 Mar 26 02:31:15 PM PDT 24 336732590000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2829634267 Mar 26 02:00:36 PM PDT 24 Mar 26 02:31:20 PM PDT 24 336725750000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1278424361 Mar 26 02:00:35 PM PDT 24 Mar 26 02:23:33 PM PDT 24 336623850000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2538897777 Mar 26 02:00:50 PM PDT 24 Mar 26 02:37:06 PM PDT 24 336914170000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3469815325 Mar 26 02:00:35 PM PDT 24 Mar 26 02:31:39 PM PDT 24 337090550000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2232441797 Mar 26 02:00:41 PM PDT 24 Mar 26 02:42:26 PM PDT 24 336982410000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4254906650 Mar 26 02:00:38 PM PDT 24 Mar 26 02:36:05 PM PDT 24 336910710000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1051953108 Mar 26 02:00:49 PM PDT 24 Mar 26 02:34:10 PM PDT 24 336795010000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.5889063 Mar 26 02:00:52 PM PDT 24 Mar 26 02:33:28 PM PDT 24 336402190000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2864087700 Mar 26 02:00:41 PM PDT 24 Mar 26 02:46:55 PM PDT 24 336829970000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2543129700 Mar 26 02:00:39 PM PDT 24 Mar 26 02:34:05 PM PDT 24 336650410000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.945077084 Mar 26 02:00:38 PM PDT 24 Mar 26 02:36:20 PM PDT 24 336575610000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1160753373 Mar 26 02:00:38 PM PDT 24 Mar 26 02:41:15 PM PDT 24 336485690000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.999268033 Mar 26 02:00:54 PM PDT 24 Mar 26 02:42:25 PM PDT 24 336895130000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1727879402 Mar 26 02:00:40 PM PDT 24 Mar 26 02:41:48 PM PDT 24 336361270000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4122786905 Mar 26 02:00:49 PM PDT 24 Mar 26 02:37:09 PM PDT 24 336743150000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4178436655 Mar 26 02:00:50 PM PDT 24 Mar 26 02:34:04 PM PDT 24 336659090000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3633595362 Mar 26 02:00:40 PM PDT 24 Mar 26 02:47:09 PM PDT 24 336556470000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4079121647 Mar 26 02:00:38 PM PDT 24 Mar 26 02:38:53 PM PDT 24 336508470000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3071269450 Mar 26 02:00:53 PM PDT 24 Mar 26 02:46:25 PM PDT 24 336313850000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2873429570 Mar 26 02:00:51 PM PDT 24 Mar 26 02:31:45 PM PDT 24 336716090000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1356168746 Mar 26 02:00:51 PM PDT 24 Mar 26 02:39:07 PM PDT 24 336612570000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1967665335
Short name T13
Test name
Test status
Simulation time 1604870000 ps
CPU time 4.38 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:56 PM PDT 24
Peak memory 164828 kb
Host smart-38da65ad-5098-4262-8d2d-b7d17b51b34b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1967665335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1967665335
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2630642643
Short name T17
Test name
Test status
Simulation time 336682850000 ps
CPU time 738.45 seconds
Started Mar 26 02:00:27 PM PDT 24
Finished Mar 26 02:30:34 PM PDT 24
Peak memory 160788 kb
Host smart-29838b33-c3ba-4573-84d6-2357343883ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2630642643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2630642643
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1021192093
Short name T40
Test name
Test status
Simulation time 336676610000 ps
CPU time 984.92 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:42:06 PM PDT 24
Peak memory 160752 kb
Host smart-fc6051c9-4460-46fa-a1be-6905d9d9de53
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1021192093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1021192093
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.751287698
Short name T26
Test name
Test status
Simulation time 1207670000 ps
CPU time 4.74 seconds
Started Mar 26 01:50:22 PM PDT 24
Finished Mar 26 01:50:32 PM PDT 24
Peak memory 164872 kb
Host smart-78791933-1fbe-4d85-8977-229764ac4891
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=751287698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.751287698
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2734778701
Short name T145
Test name
Test status
Simulation time 336409910000 ps
CPU time 878.28 seconds
Started Mar 26 02:00:29 PM PDT 24
Finished Mar 26 02:35:58 PM PDT 24
Peak memory 160800 kb
Host smart-4aa0a661-e306-4e19-b9d6-e5af4148ec76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2734778701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2734778701
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.545151515
Short name T19
Test name
Test status
Simulation time 336745130000 ps
CPU time 895.65 seconds
Started Mar 26 02:00:32 PM PDT 24
Finished Mar 26 02:37:04 PM PDT 24
Peak memory 160800 kb
Host smart-96356e7a-fa16-4ad6-8333-427ac6b3272b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=545151515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.545151515
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3139243305
Short name T156
Test name
Test status
Simulation time 337049930000 ps
CPU time 724.62 seconds
Started Mar 26 02:00:31 PM PDT 24
Finished Mar 26 02:30:32 PM PDT 24
Peak memory 160788 kb
Host smart-47ecd2e7-f2db-4572-b862-533f4b629523
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3139243305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3139243305
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2108111849
Short name T147
Test name
Test status
Simulation time 336851270000 ps
CPU time 789.15 seconds
Started Mar 26 02:00:31 PM PDT 24
Finished Mar 26 02:33:55 PM PDT 24
Peak memory 160720 kb
Host smart-2955a29b-6fb7-47ba-8ebb-39e12fbe2cac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2108111849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2108111849
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.4124847804
Short name T22
Test name
Test status
Simulation time 336547710000 ps
CPU time 784.98 seconds
Started Mar 26 02:00:32 PM PDT 24
Finished Mar 26 02:33:54 PM PDT 24
Peak memory 160720 kb
Host smart-56bdb79d-38c7-48b3-a3ba-58d8db996c5f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4124847804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.4124847804
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3672591323
Short name T149
Test name
Test status
Simulation time 336842390000 ps
CPU time 812.12 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:34:16 PM PDT 24
Peak memory 160796 kb
Host smart-4d77abe8-5916-46b7-a2fa-df15a747610c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3672591323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3672591323
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2052267811
Short name T146
Test name
Test status
Simulation time 336938230000 ps
CPU time 1048.05 seconds
Started Mar 26 02:00:40 PM PDT 24
Finished Mar 26 02:46:48 PM PDT 24
Peak memory 160792 kb
Host smart-794030ec-6d94-4fd7-985f-ffd8dc9d9dca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2052267811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2052267811
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.862156055
Short name T138
Test name
Test status
Simulation time 337084770000 ps
CPU time 800.07 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:33:51 PM PDT 24
Peak memory 160784 kb
Host smart-0c93c853-954d-429b-bd26-5f56dbef05cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=862156055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.862156055
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.702949475
Short name T134
Test name
Test status
Simulation time 336948490000 ps
CPU time 907.95 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:38:13 PM PDT 24
Peak memory 160768 kb
Host smart-fccd9140-c104-47a7-921b-9032c19e2b4a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=702949475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.702949475
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1491306611
Short name T160
Test name
Test status
Simulation time 336712470000 ps
CPU time 846.16 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:35:13 PM PDT 24
Peak memory 160752 kb
Host smart-a736cbd6-7d0f-47eb-b374-51dff17e85a7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1491306611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1491306611
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2356217661
Short name T132
Test name
Test status
Simulation time 336924730000 ps
CPU time 786.58 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:33:51 PM PDT 24
Peak memory 160704 kb
Host smart-31625121-ae16-4114-8a06-51806cdab92a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2356217661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2356217661
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1687007911
Short name T155
Test name
Test status
Simulation time 336683930000 ps
CPU time 846.33 seconds
Started Mar 26 02:00:28 PM PDT 24
Finished Mar 26 02:34:30 PM PDT 24
Peak memory 160692 kb
Host smart-310c9794-0856-4130-9248-dd30ff3a50f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1687007911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1687007911
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.918744932
Short name T157
Test name
Test status
Simulation time 336360790000 ps
CPU time 830.48 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:34:59 PM PDT 24
Peak memory 160788 kb
Host smart-90e9b538-91ba-4147-8cf0-ed60f497286e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=918744932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.918744932
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3837485468
Short name T129
Test name
Test status
Simulation time 336898610000 ps
CPU time 929.27 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:38:53 PM PDT 24
Peak memory 160704 kb
Host smart-a80ae94a-d281-4ab4-ac11-8c5e1ece4052
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3837485468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3837485468
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.945285847
Short name T143
Test name
Test status
Simulation time 336848410000 ps
CPU time 907.35 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:38:11 PM PDT 24
Peak memory 160768 kb
Host smart-5e2b61c6-c4b6-4245-9a62-4a629ba59ea9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=945285847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.945285847
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1543972570
Short name T140
Test name
Test status
Simulation time 336614990000 ps
CPU time 979.02 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:41:28 PM PDT 24
Peak memory 160752 kb
Host smart-7f4eaaf5-ee0f-4fb3-95e3-c79205f4531e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1543972570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1543972570
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.848187178
Short name T23
Test name
Test status
Simulation time 336457630000 ps
CPU time 971.12 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:41:44 PM PDT 24
Peak memory 160144 kb
Host smart-a9b17482-b234-4c0f-a684-89b0a231f728
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=848187178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.848187178
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.805038972
Short name T123
Test name
Test status
Simulation time 337093010000 ps
CPU time 951.18 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:40:15 PM PDT 24
Peak memory 160780 kb
Host smart-b180acd3-3218-4ea3-8580-770aa0fee9e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=805038972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.805038972
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3885064248
Short name T127
Test name
Test status
Simulation time 336990490000 ps
CPU time 968.93 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:41:46 PM PDT 24
Peak memory 160248 kb
Host smart-03854bfe-0903-4bfb-8a96-0b88a16d10a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3885064248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3885064248
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1830366223
Short name T153
Test name
Test status
Simulation time 336770870000 ps
CPU time 808.3 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:33:00 PM PDT 24
Peak memory 160756 kb
Host smart-9d0383d6-7154-4a47-8535-86aadaeee96f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1830366223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1830366223
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1908104256
Short name T16
Test name
Test status
Simulation time 336959490000 ps
CPU time 843.66 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:35:15 PM PDT 24
Peak memory 160728 kb
Host smart-e7539ae9-07c2-4910-a003-f8b8ea18acb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1908104256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1908104256
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.756681970
Short name T14
Test name
Test status
Simulation time 336946750000 ps
CPU time 890.98 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:36:50 PM PDT 24
Peak memory 160788 kb
Host smart-033ada4a-5894-44a2-8e7e-b9cab0f78f9d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=756681970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.756681970
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2908212384
Short name T151
Test name
Test status
Simulation time 336541950000 ps
CPU time 717.79 seconds
Started Mar 26 02:00:28 PM PDT 24
Finished Mar 26 02:29:46 PM PDT 24
Peak memory 160744 kb
Host smart-0acb6073-bf23-4418-88e6-ac68981c748b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2908212384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2908212384
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1723148437
Short name T126
Test name
Test status
Simulation time 336675250000 ps
CPU time 801.49 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:33:58 PM PDT 24
Peak memory 160796 kb
Host smart-09a56a8a-8f89-40cf-9210-c012e1789ef0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1723148437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1723148437
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3749255252
Short name T135
Test name
Test status
Simulation time 336620010000 ps
CPU time 828.82 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:34:48 PM PDT 24
Peak memory 160792 kb
Host smart-5a54b05d-6fbb-4036-8fc8-3d70261692db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3749255252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3749255252
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.686076732
Short name T136
Test name
Test status
Simulation time 336637710000 ps
CPU time 945.69 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:41:54 PM PDT 24
Peak memory 160788 kb
Host smart-df752266-a728-43ce-a755-a211ac049553
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=686076732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.686076732
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3515723890
Short name T130
Test name
Test status
Simulation time 336393490000 ps
CPU time 857.55 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:37:13 PM PDT 24
Peak memory 160772 kb
Host smart-9bec443f-e854-4bf9-9bb9-28b9c75c882b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3515723890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3515723890
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.618155069
Short name T152
Test name
Test status
Simulation time 336867790000 ps
CPU time 852.12 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:37:24 PM PDT 24
Peak memory 160076 kb
Host smart-8dce4a4a-9e08-4125-8786-0162e716cb06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=618155069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.618155069
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2199433028
Short name T139
Test name
Test status
Simulation time 336618910000 ps
CPU time 797.31 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:34:07 PM PDT 24
Peak memory 160500 kb
Host smart-887db3ae-943f-45f5-a13f-7fc79ef72da3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2199433028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2199433028
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1415993324
Short name T131
Test name
Test status
Simulation time 336918550000 ps
CPU time 962.76 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:40:25 PM PDT 24
Peak memory 160792 kb
Host smart-7882638b-dec8-405b-bdea-a56e27487830
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1415993324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1415993324
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2836306302
Short name T21
Test name
Test status
Simulation time 336996690000 ps
CPU time 805.56 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:34:57 PM PDT 24
Peak memory 160768 kb
Host smart-2976297c-504b-4362-9041-95345a0c37a0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2836306302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2836306302
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3512174025
Short name T20
Test name
Test status
Simulation time 336766210000 ps
CPU time 816.26 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:34:07 PM PDT 24
Peak memory 160736 kb
Host smart-3e36a731-a940-45c7-b1a7-d270bea248fe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3512174025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3512174025
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.732234311
Short name T159
Test name
Test status
Simulation time 336863930000 ps
CPU time 788.44 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:32:18 PM PDT 24
Peak memory 160716 kb
Host smart-e6c0a622-bbd8-483d-913c-9a7ad02ee4d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=732234311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.732234311
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3336881554
Short name T133
Test name
Test status
Simulation time 336390730000 ps
CPU time 718.37 seconds
Started Mar 26 02:00:31 PM PDT 24
Finished Mar 26 02:30:00 PM PDT 24
Peak memory 160740 kb
Host smart-1a138eec-7c76-4465-b91b-ee80b99a3f06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3336881554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3336881554
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4211498639
Short name T125
Test name
Test status
Simulation time 336494410000 ps
CPU time 848.15 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:37:20 PM PDT 24
Peak memory 160188 kb
Host smart-c8856e42-9241-4583-91c7-4209f28a1344
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4211498639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4211498639
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3923633211
Short name T142
Test name
Test status
Simulation time 336451970000 ps
CPU time 869.47 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:35:56 PM PDT 24
Peak memory 160736 kb
Host smart-15ea6e09-6222-49ca-a62f-29de10866ab4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3923633211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3923633211
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1932825084
Short name T121
Test name
Test status
Simulation time 336404510000 ps
CPU time 999.99 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:43:31 PM PDT 24
Peak memory 160764 kb
Host smart-fd5f1ca0-f267-4477-b8db-d8ef0ffb3625
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1932825084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1932825084
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2073742668
Short name T154
Test name
Test status
Simulation time 336366570000 ps
CPU time 830.98 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:35:00 PM PDT 24
Peak memory 160792 kb
Host smart-43268341-1c18-46de-820b-6ed9eb8a4d3e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2073742668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2073742668
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1549481706
Short name T122
Test name
Test status
Simulation time 336949710000 ps
CPU time 779.16 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:34:12 PM PDT 24
Peak memory 160768 kb
Host smart-62ac1ac5-d9aa-425e-ab9b-185fa26fcebd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1549481706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1549481706
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1822739680
Short name T150
Test name
Test status
Simulation time 336818010000 ps
CPU time 1045.89 seconds
Started Mar 26 02:00:40 PM PDT 24
Finished Mar 26 02:47:05 PM PDT 24
Peak memory 160788 kb
Host smart-071dfc2b-9a3a-4653-833b-93eaca2dff86
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1822739680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1822739680
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.666643421
Short name T15
Test name
Test status
Simulation time 336800290000 ps
CPU time 926.33 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:39:11 PM PDT 24
Peak memory 160704 kb
Host smart-4b81dbbb-9fee-4697-adee-151b1e734bcc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=666643421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.666643421
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1959193303
Short name T158
Test name
Test status
Simulation time 336820450000 ps
CPU time 1008.7 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:43:38 PM PDT 24
Peak memory 160764 kb
Host smart-504f0e07-f99f-4161-93e1-601f4c19abe9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1959193303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1959193303
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3750110547
Short name T18
Test name
Test status
Simulation time 336411630000 ps
CPU time 986.96 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 160792 kb
Host smart-a8d90ab3-0a9f-4a83-acc1-9d4f9013d8b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3750110547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3750110547
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1955448833
Short name T144
Test name
Test status
Simulation time 336533390000 ps
CPU time 1001.6 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:43:38 PM PDT 24
Peak memory 160764 kb
Host smart-7d6a1155-6bad-4d9a-b818-b7afd434fa54
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1955448833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1955448833
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3110843524
Short name T124
Test name
Test status
Simulation time 336957750000 ps
CPU time 907.78 seconds
Started Mar 26 02:00:27 PM PDT 24
Finished Mar 26 02:37:41 PM PDT 24
Peak memory 160796 kb
Host smart-f000c30c-e1e4-4571-b1dc-1a2b5ad031ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3110843524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3110843524
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3184556862
Short name T128
Test name
Test status
Simulation time 337046070000 ps
CPU time 813.31 seconds
Started Mar 26 02:00:27 PM PDT 24
Finished Mar 26 02:34:15 PM PDT 24
Peak memory 160744 kb
Host smart-c53afb4d-8894-4c1f-ad2a-bc06bb40b944
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3184556862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3184556862
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3084827780
Short name T141
Test name
Test status
Simulation time 336557710000 ps
CPU time 828.05 seconds
Started Mar 26 02:00:28 PM PDT 24
Finished Mar 26 02:33:55 PM PDT 24
Peak memory 160720 kb
Host smart-1845d9b4-27c2-49b5-896c-55fa66898609
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3084827780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3084827780
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1050395518
Short name T148
Test name
Test status
Simulation time 336404310000 ps
CPU time 774.82 seconds
Started Mar 26 02:00:32 PM PDT 24
Finished Mar 26 02:32:38 PM PDT 24
Peak memory 160728 kb
Host smart-45e3580e-2e01-412f-a09f-b6a051647e6f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1050395518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1050395518
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3123849914
Short name T137
Test name
Test status
Simulation time 336731710000 ps
CPU time 682.46 seconds
Started Mar 26 02:00:29 PM PDT 24
Finished Mar 26 02:28:37 PM PDT 24
Peak memory 160800 kb
Host smart-9c617e48-1cc9-414a-8ea3-e5030fdc9d67
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3123849914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3123849914
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2543129700
Short name T189
Test name
Test status
Simulation time 336650410000 ps
CPU time 793.6 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:34:05 PM PDT 24
Peak memory 160484 kb
Host smart-5857e48a-8853-4b1e-a04b-b805f71497e1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2543129700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2543129700
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1278424361
Short name T181
Test name
Test status
Simulation time 336623850000 ps
CPU time 533.2 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:23:33 PM PDT 24
Peak memory 161072 kb
Host smart-263911ee-dfd8-45be-b7e5-17f44773dc0d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1278424361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1278424361
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1727879402
Short name T193
Test name
Test status
Simulation time 336361270000 ps
CPU time 958.97 seconds
Started Mar 26 02:00:40 PM PDT 24
Finished Mar 26 02:41:48 PM PDT 24
Peak memory 160796 kb
Host smart-16ac2f7c-ac89-494b-adba-d0be73b5085e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1727879402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1727879402
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2461739375
Short name T166
Test name
Test status
Simulation time 337038870000 ps
CPU time 979.5 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:42:32 PM PDT 24
Peak memory 160752 kb
Host smart-88e71afb-dfef-4771-b679-21b7854ce8eb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2461739375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2461739375
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2232441797
Short name T184
Test name
Test status
Simulation time 336982410000 ps
CPU time 989.56 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:42:26 PM PDT 24
Peak memory 160756 kb
Host smart-6070f657-5f8e-4f1a-840f-c162b79ffbf6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2232441797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2232441797
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3903067586
Short name T176
Test name
Test status
Simulation time 336500010000 ps
CPU time 920.54 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:39:21 PM PDT 24
Peak memory 160796 kb
Host smart-782b8d58-8cb4-4cd4-863f-3b30dbba26bc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3903067586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3903067586
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4079121647
Short name T197
Test name
Test status
Simulation time 336508470000 ps
CPU time 915.93 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:38:53 PM PDT 24
Peak memory 160720 kb
Host smart-b0060993-b8aa-4b69-a288-fd80a4102b13
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4079121647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4079121647
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2926196169
Short name T172
Test name
Test status
Simulation time 336374090000 ps
CPU time 988.85 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:41:40 PM PDT 24
Peak memory 160756 kb
Host smart-21399848-8dc3-41f3-8615-a6b7cc97c41d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2926196169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2926196169
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.945077084
Short name T190
Test name
Test status
Simulation time 336575610000 ps
CPU time 868.96 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:36:20 PM PDT 24
Peak memory 160720 kb
Host smart-b0b58209-45a9-49a7-8a96-04a35880274b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=945077084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.945077084
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4254906650
Short name T185
Test name
Test status
Simulation time 336910710000 ps
CPU time 861 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:36:05 PM PDT 24
Peak memory 160732 kb
Host smart-4cb98f4d-7cb4-4165-a564-73e134b5a7b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4254906650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4254906650
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.556427621
Short name T178
Test name
Test status
Simulation time 336472270000 ps
CPU time 921.85 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:39:06 PM PDT 24
Peak memory 160704 kb
Host smart-aa0098ee-9885-4f55-8650-149a0e03c342
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=556427621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.556427621
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2864087700
Short name T188
Test name
Test status
Simulation time 336829970000 ps
CPU time 1057.76 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:46:55 PM PDT 24
Peak memory 160792 kb
Host smart-0a0d5d5e-cfba-47c4-af18-58074b72e5a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2864087700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2864087700
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2410297368
Short name T175
Test name
Test status
Simulation time 337062210000 ps
CPU time 971.39 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:41:45 PM PDT 24
Peak memory 160756 kb
Host smart-907140f7-b1e7-49b9-b640-a6af3c95566b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2410297368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2410297368
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.934587582
Short name T36
Test name
Test status
Simulation time 336475310000 ps
CPU time 895.56 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:36:55 PM PDT 24
Peak memory 160792 kb
Host smart-a01ab9a8-ca87-4a8f-97ed-193ce8771a8c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=934587582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.934587582
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3709837404
Short name T167
Test name
Test status
Simulation time 336655690000 ps
CPU time 923.67 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:39:06 PM PDT 24
Peak memory 160720 kb
Host smart-6e1d1fc9-01aa-4b5d-b938-f106eaff312c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3709837404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3709837404
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.418576172
Short name T171
Test name
Test status
Simulation time 336467050000 ps
CPU time 976.78 seconds
Started Mar 26 02:00:41 PM PDT 24
Finished Mar 26 02:42:19 PM PDT 24
Peak memory 160616 kb
Host smart-2991675a-d70f-4b80-8d68-b0d6131a293b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=418576172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.418576172
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.111309576
Short name T32
Test name
Test status
Simulation time 336645910000 ps
CPU time 894.77 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:38:42 PM PDT 24
Peak memory 160784 kb
Host smart-435bae44-e219-416d-9399-3a15fc2bb43c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=111309576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.111309576
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2080965942
Short name T170
Test name
Test status
Simulation time 336954750000 ps
CPU time 776.52 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:32:17 PM PDT 24
Peak memory 160760 kb
Host smart-1575929c-c5ae-4afb-812a-c6c73d83d6c6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2080965942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2080965942
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1160753373
Short name T191
Test name
Test status
Simulation time 336485690000 ps
CPU time 964.4 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:41:15 PM PDT 24
Peak memory 160756 kb
Host smart-1a62ad6e-2a02-4a17-8ea8-ed09114f0cd7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1160753373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1160753373
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3469815325
Short name T183
Test name
Test status
Simulation time 337090550000 ps
CPU time 759.29 seconds
Started Mar 26 02:00:35 PM PDT 24
Finished Mar 26 02:31:39 PM PDT 24
Peak memory 160688 kb
Host smart-ae04afde-e879-43b0-9340-da1c5dd8f77f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3469815325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3469815325
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2878143231
Short name T179
Test name
Test status
Simulation time 336732590000 ps
CPU time 746.54 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:31:15 PM PDT 24
Peak memory 160688 kb
Host smart-2b1062d3-92fe-4dde-a554-4b3ea803f839
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2878143231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2878143231
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2829634267
Short name T180
Test name
Test status
Simulation time 336725750000 ps
CPU time 748.27 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:31:20 PM PDT 24
Peak memory 160688 kb
Host smart-c9afd8f3-b5cb-4784-b231-5effb4ba8341
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2829634267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2829634267
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2262106291
Short name T34
Test name
Test status
Simulation time 336611130000 ps
CPU time 932.54 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:39:32 PM PDT 24
Peak memory 160788 kb
Host smart-e9d9ab07-5678-4b0a-bd3a-ec103385608a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2262106291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2262106291
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.428091309
Short name T35
Test name
Test status
Simulation time 336558830000 ps
CPU time 946.18 seconds
Started Mar 26 02:00:53 PM PDT 24
Finished Mar 26 02:41:45 PM PDT 24
Peak memory 160792 kb
Host smart-1d29f5fc-6d34-4511-8a59-2658524f80a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=428091309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.428091309
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.846080557
Short name T165
Test name
Test status
Simulation time 336673670000 ps
CPU time 720.23 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:30:24 PM PDT 24
Peak memory 160744 kb
Host smart-a38f181b-50f8-4c9a-8b77-edda10ca6989
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846080557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.846080557
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1356168746
Short name T200
Test name
Test status
Simulation time 336612570000 ps
CPU time 905.07 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:39:07 PM PDT 24
Peak memory 160796 kb
Host smart-54e5c12a-d269-4620-b9b7-7bffe4a6d1a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1356168746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1356168746
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2089389713
Short name T174
Test name
Test status
Simulation time 336759830000 ps
CPU time 779.24 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:34:03 PM PDT 24
Peak memory 160724 kb
Host smart-a1a88333-59d8-4708-8849-c7baa1033e4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2089389713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2089389713
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.5889063
Short name T187
Test name
Test status
Simulation time 336402190000 ps
CPU time 771.95 seconds
Started Mar 26 02:00:52 PM PDT 24
Finished Mar 26 02:33:28 PM PDT 24
Peak memory 160724 kb
Host smart-24e27b7e-d059-4a49-a1db-62a9326aa1b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=5889063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.5889063
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3071269450
Short name T198
Test name
Test status
Simulation time 336313850000 ps
CPU time 1025.73 seconds
Started Mar 26 02:00:53 PM PDT 24
Finished Mar 26 02:46:25 PM PDT 24
Peak memory 160796 kb
Host smart-998db83b-e97c-4387-98ed-2e85eb231eb7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3071269450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3071269450
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1186553294
Short name T162
Test name
Test status
Simulation time 336924970000 ps
CPU time 946.46 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:38:25 PM PDT 24
Peak memory 160788 kb
Host smart-87f6fbc6-fa17-48f2-b4d4-7576bcc04b76
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1186553294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1186553294
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4223719781
Short name T177
Test name
Test status
Simulation time 336673390000 ps
CPU time 853.77 seconds
Started Mar 26 02:00:52 PM PDT 24
Finished Mar 26 02:35:55 PM PDT 24
Peak memory 160756 kb
Host smart-7fe24a2c-bcca-4584-92d9-eb4adff3548c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4223719781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4223719781
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4122786905
Short name T194
Test name
Test status
Simulation time 336743150000 ps
CPU time 879.71 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:37:09 PM PDT 24
Peak memory 160808 kb
Host smart-22c6a94b-59c2-44ad-94ec-b5eec9af9441
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4122786905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.4122786905
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1995024616
Short name T168
Test name
Test status
Simulation time 336780730000 ps
CPU time 625.38 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:26:42 PM PDT 24
Peak memory 160752 kb
Host smart-9347a158-2ba0-4aef-825c-5e4c34fd7ca9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1995024616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1995024616
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3633595362
Short name T196
Test name
Test status
Simulation time 336556470000 ps
CPU time 1055.91 seconds
Started Mar 26 02:00:40 PM PDT 24
Finished Mar 26 02:47:09 PM PDT 24
Peak memory 160792 kb
Host smart-067bdb64-d031-4bbd-b711-a6cee365d361
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3633595362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3633595362
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2273383811
Short name T38
Test name
Test status
Simulation time 336863190000 ps
CPU time 785.98 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:32:13 PM PDT 24
Peak memory 160792 kb
Host smart-2e41c862-07dd-41ff-afa6-82d280ff6317
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2273383811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2273383811
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3261480171
Short name T164
Test name
Test status
Simulation time 336651150000 ps
CPU time 809.04 seconds
Started Mar 26 02:00:53 PM PDT 24
Finished Mar 26 02:33:28 PM PDT 24
Peak memory 160776 kb
Host smart-4f2fe815-4250-40cf-bb7d-e2d14eb9ba39
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3261480171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3261480171
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4178436655
Short name T195
Test name
Test status
Simulation time 336659090000 ps
CPU time 806.69 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:34:04 PM PDT 24
Peak memory 160796 kb
Host smart-e9524a09-5e76-44a8-8ed9-b203d06d881d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4178436655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.4178436655
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2538897777
Short name T182
Test name
Test status
Simulation time 336914170000 ps
CPU time 883.27 seconds
Started Mar 26 02:00:50 PM PDT 24
Finished Mar 26 02:37:06 PM PDT 24
Peak memory 160828 kb
Host smart-de273daf-bbd2-4984-a0ca-7d5b0374e8c4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2538897777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2538897777
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2873429570
Short name T199
Test name
Test status
Simulation time 336716090000 ps
CPU time 754.37 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:31:45 PM PDT 24
Peak memory 160792 kb
Host smart-84899540-468e-45b6-8a56-5172f7751d77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2873429570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2873429570
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1632655942
Short name T33
Test name
Test status
Simulation time 336907550000 ps
CPU time 922.83 seconds
Started Mar 26 02:00:48 PM PDT 24
Finished Mar 26 02:37:24 PM PDT 24
Peak memory 160792 kb
Host smart-653ced2f-cf5e-4715-84b1-9bcd8eedb9bd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1632655942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1632655942
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1051953108
Short name T186
Test name
Test status
Simulation time 336795010000 ps
CPU time 803.53 seconds
Started Mar 26 02:00:49 PM PDT 24
Finished Mar 26 02:34:10 PM PDT 24
Peak memory 160752 kb
Host smart-4f0d80ac-4f96-4407-b926-4fc038176468
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1051953108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1051953108
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1901936260
Short name T39
Test name
Test status
Simulation time 336956470000 ps
CPU time 664.3 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:28:33 PM PDT 24
Peak memory 160800 kb
Host smart-3b97a5c3-5429-49fe-8d1b-73f0411f0556
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1901936260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1901936260
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.999268033
Short name T192
Test name
Test status
Simulation time 336895130000 ps
CPU time 983.65 seconds
Started Mar 26 02:00:54 PM PDT 24
Finished Mar 26 02:42:25 PM PDT 24
Peak memory 160752 kb
Host smart-ec8f2f1a-6b0e-4e48-964e-12c948bcc37e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=999268033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.999268033
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1127833473
Short name T161
Test name
Test status
Simulation time 336629030000 ps
CPU time 887.23 seconds
Started Mar 26 02:00:51 PM PDT 24
Finished Mar 26 02:36:12 PM PDT 24
Peak memory 160776 kb
Host smart-b42c9275-86b5-4dc8-b7e3-9bab7aac095d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1127833473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1127833473
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2359777486
Short name T169
Test name
Test status
Simulation time 336410110000 ps
CPU time 779.46 seconds
Started Mar 26 02:00:37 PM PDT 24
Finished Mar 26 02:34:11 PM PDT 24
Peak memory 160764 kb
Host smart-2e73f902-565b-4e59-a27d-3809e1abc72f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2359777486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2359777486
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1594357350
Short name T173
Test name
Test status
Simulation time 337072650000 ps
CPU time 877.2 seconds
Started Mar 26 02:00:38 PM PDT 24
Finished Mar 26 02:36:24 PM PDT 24
Peak memory 160724 kb
Host smart-31311cf8-3b7f-4b5d-ab6f-ad87868b4aa0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1594357350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1594357350
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.759022583
Short name T31
Test name
Test status
Simulation time 336947530000 ps
CPU time 846.88 seconds
Started Mar 26 02:00:39 PM PDT 24
Finished Mar 26 02:37:24 PM PDT 24
Peak memory 160612 kb
Host smart-53b18b65-aa00-48ee-844f-fc0084207594
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=759022583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.759022583
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3982623629
Short name T163
Test name
Test status
Simulation time 336401070000 ps
CPU time 769.43 seconds
Started Mar 26 02:00:34 PM PDT 24
Finished Mar 26 02:31:41 PM PDT 24
Peak memory 160792 kb
Host smart-f3a7db9f-4741-4f29-9900-8c3c71acb6ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3982623629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3982623629
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3091794348
Short name T37
Test name
Test status
Simulation time 336690830000 ps
CPU time 928.87 seconds
Started Mar 26 02:00:36 PM PDT 24
Finished Mar 26 02:39:23 PM PDT 24
Peak memory 160704 kb
Host smart-9db0a842-666f-4406-9e2f-3c47b0afaf3a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3091794348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3091794348
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.259856510
Short name T108
Test name
Test status
Simulation time 1403330000 ps
CPU time 5.11 seconds
Started Mar 26 01:50:23 PM PDT 24
Finished Mar 26 01:50:34 PM PDT 24
Peak memory 164892 kb
Host smart-bc43a4b2-4fcb-4071-b6a7-3a1a7b292c7b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=259856510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.259856510
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.391453728
Short name T98
Test name
Test status
Simulation time 1523250000 ps
CPU time 5.35 seconds
Started Mar 26 01:50:22 PM PDT 24
Finished Mar 26 01:50:34 PM PDT 24
Peak memory 164844 kb
Host smart-edc073ee-2ce0-4f88-bbf6-ee931afefc6f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=391453728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.391453728
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.40548924
Short name T85
Test name
Test status
Simulation time 1395050000 ps
CPU time 6.05 seconds
Started Mar 26 01:50:24 PM PDT 24
Finished Mar 26 01:50:37 PM PDT 24
Peak memory 164868 kb
Host smart-cfc4122c-da8e-447d-8947-4f28c2207d3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=40548924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.40548924
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3215377414
Short name T119
Test name
Test status
Simulation time 1599130000 ps
CPU time 3.78 seconds
Started Mar 26 01:50:22 PM PDT 24
Finished Mar 26 01:50:31 PM PDT 24
Peak memory 164888 kb
Host smart-e7e4dc22-1dcf-4f6e-8f16-3cf2290889f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215377414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3215377414
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.441322398
Short name T100
Test name
Test status
Simulation time 1599890000 ps
CPU time 3.07 seconds
Started Mar 26 01:50:30 PM PDT 24
Finished Mar 26 01:50:37 PM PDT 24
Peak memory 164884 kb
Host smart-5e8af859-342a-478c-9c90-d252c4a182cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=441322398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.441322398
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3348340661
Short name T24
Test name
Test status
Simulation time 1538830000 ps
CPU time 4.86 seconds
Started Mar 26 01:50:30 PM PDT 24
Finished Mar 26 01:50:41 PM PDT 24
Peak memory 164880 kb
Host smart-e233ae7b-a150-4f6a-a83b-ecf1a878d08b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3348340661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3348340661
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.675376845
Short name T83
Test name
Test status
Simulation time 1300150000 ps
CPU time 5.83 seconds
Started Mar 26 01:50:29 PM PDT 24
Finished Mar 26 01:50:42 PM PDT 24
Peak memory 164892 kb
Host smart-58440281-f5d4-4a7e-be3f-e3be54c7edff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=675376845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.675376845
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3707858495
Short name T90
Test name
Test status
Simulation time 1490730000 ps
CPU time 6.06 seconds
Started Mar 26 01:50:30 PM PDT 24
Finished Mar 26 01:50:42 PM PDT 24
Peak memory 164900 kb
Host smart-441e3958-5f28-4efd-8ae3-83cd8a5593bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3707858495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3707858495
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.78412385
Short name T82
Test name
Test status
Simulation time 1197690000 ps
CPU time 3.57 seconds
Started Mar 26 01:50:31 PM PDT 24
Finished Mar 26 01:50:38 PM PDT 24
Peak memory 164884 kb
Host smart-0136eb0a-4d76-43f5-adbc-b2371a74af0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78412385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.78412385
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3980999436
Short name T102
Test name
Test status
Simulation time 1408510000 ps
CPU time 4.02 seconds
Started Mar 26 01:50:31 PM PDT 24
Finished Mar 26 01:50:40 PM PDT 24
Peak memory 164888 kb
Host smart-9d1dad06-3f5e-48ad-892d-546c5db0f936
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980999436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3980999436
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.618787660
Short name T109
Test name
Test status
Simulation time 1480390000 ps
CPU time 3.53 seconds
Started Mar 26 01:50:32 PM PDT 24
Finished Mar 26 01:50:39 PM PDT 24
Peak memory 164816 kb
Host smart-c7fe42ca-633e-476d-970a-ec99ff38f5bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=618787660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.618787660
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4003204284
Short name T117
Test name
Test status
Simulation time 1483330000 ps
CPU time 3.88 seconds
Started Mar 26 01:50:24 PM PDT 24
Finished Mar 26 01:50:32 PM PDT 24
Peak memory 164868 kb
Host smart-f2151222-d221-41cb-a971-d29c71ce84e6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4003204284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4003204284
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3838431647
Short name T96
Test name
Test status
Simulation time 1430470000 ps
CPU time 4.35 seconds
Started Mar 26 01:50:31 PM PDT 24
Finished Mar 26 01:50:40 PM PDT 24
Peak memory 164856 kb
Host smart-2b94509d-51a9-46d6-bb57-f27bd76d5bc5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3838431647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3838431647
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3647690667
Short name T29
Test name
Test status
Simulation time 1569710000 ps
CPU time 4.48 seconds
Started Mar 26 01:50:30 PM PDT 24
Finished Mar 26 01:50:40 PM PDT 24
Peak memory 164868 kb
Host smart-9f333f88-cb6f-4a88-b461-1300d1d83bfb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3647690667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3647690667
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2532760456
Short name T114
Test name
Test status
Simulation time 1314110000 ps
CPU time 4.01 seconds
Started Mar 26 01:50:31 PM PDT 24
Finished Mar 26 01:50:40 PM PDT 24
Peak memory 164824 kb
Host smart-eb2c03ea-969d-451f-be16-967f42ca1348
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2532760456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2532760456
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.889295822
Short name T89
Test name
Test status
Simulation time 1601630000 ps
CPU time 4.97 seconds
Started Mar 26 01:50:33 PM PDT 24
Finished Mar 26 01:50:43 PM PDT 24
Peak memory 164812 kb
Host smart-0e29bf49-f516-4094-9528-9db229636748
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889295822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.889295822
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4102738488
Short name T113
Test name
Test status
Simulation time 1337450000 ps
CPU time 5.64 seconds
Started Mar 26 01:50:29 PM PDT 24
Finished Mar 26 01:50:41 PM PDT 24
Peak memory 164852 kb
Host smart-6695a962-493d-46be-a18f-49f8d25cb57c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102738488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4102738488
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.235167513
Short name T116
Test name
Test status
Simulation time 1531870000 ps
CPU time 5.08 seconds
Started Mar 26 01:50:31 PM PDT 24
Finished Mar 26 01:50:42 PM PDT 24
Peak memory 164872 kb
Host smart-9ad8bfff-45e9-406a-970d-5654ba1c82f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=235167513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.235167513
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2283670975
Short name T110
Test name
Test status
Simulation time 1583910000 ps
CPU time 4.73 seconds
Started Mar 26 01:50:30 PM PDT 24
Finished Mar 26 01:50:40 PM PDT 24
Peak memory 164876 kb
Host smart-0e6e1276-78b5-4bf3-891a-3231c9e1a166
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2283670975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2283670975
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2961814961
Short name T104
Test name
Test status
Simulation time 1536990000 ps
CPU time 4.88 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:50 PM PDT 24
Peak memory 164820 kb
Host smart-7ce81c9c-0206-43c8-8c80-d8d22da62778
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2961814961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2961814961
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3305570612
Short name T99
Test name
Test status
Simulation time 1441570000 ps
CPU time 3.3 seconds
Started Mar 26 01:50:37 PM PDT 24
Finished Mar 26 01:50:44 PM PDT 24
Peak memory 164928 kb
Host smart-f62b5751-bee9-4458-bc9e-bc81f7eb3c7d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305570612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3305570612
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.859362479
Short name T107
Test name
Test status
Simulation time 1527430000 ps
CPU time 4.18 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:48 PM PDT 24
Peak memory 164828 kb
Host smart-059fd33f-1795-4531-9eeb-f168d949ef11
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=859362479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.859362479
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2155328031
Short name T94
Test name
Test status
Simulation time 1398490000 ps
CPU time 4.1 seconds
Started Mar 26 01:50:21 PM PDT 24
Finished Mar 26 01:50:30 PM PDT 24
Peak memory 164824 kb
Host smart-45611fd2-0dd2-409f-897a-a2e318feb0b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2155328031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2155328031
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2093629401
Short name T97
Test name
Test status
Simulation time 1509750000 ps
CPU time 5.95 seconds
Started Mar 26 01:50:37 PM PDT 24
Finished Mar 26 01:50:49 PM PDT 24
Peak memory 164912 kb
Host smart-8cc474ad-6c4e-49d5-b7d9-b9c798ba6e0a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2093629401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2093629401
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4136103524
Short name T101
Test name
Test status
Simulation time 1590070000 ps
CPU time 4.06 seconds
Started Mar 26 01:50:37 PM PDT 24
Finished Mar 26 01:50:46 PM PDT 24
Peak memory 164884 kb
Host smart-825810ce-dedd-4271-8294-3e1326ed180d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4136103524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4136103524
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2289000239
Short name T88
Test name
Test status
Simulation time 1196130000 ps
CPU time 3.57 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:46 PM PDT 24
Peak memory 164828 kb
Host smart-cdd1eedc-4295-49ef-97a9-c5b3fb7dbafe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2289000239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2289000239
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3707564609
Short name T7
Test name
Test status
Simulation time 1529450000 ps
CPU time 5.16 seconds
Started Mar 26 01:50:37 PM PDT 24
Finished Mar 26 01:50:48 PM PDT 24
Peak memory 164896 kb
Host smart-f78ae976-b961-4f6e-80ee-d24569204602
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3707564609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3707564609
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2331516070
Short name T92
Test name
Test status
Simulation time 1311970000 ps
CPU time 4.27 seconds
Started Mar 26 01:50:44 PM PDT 24
Finished Mar 26 01:50:54 PM PDT 24
Peak memory 164808 kb
Host smart-44a2bdaa-d09d-4fcd-ba11-169e50b70160
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331516070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2331516070
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3082109121
Short name T84
Test name
Test status
Simulation time 1434190000 ps
CPU time 6.04 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:52 PM PDT 24
Peak memory 164868 kb
Host smart-6e6119d7-dd65-432a-b7fc-251624a4c73f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3082109121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3082109121
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3732306521
Short name T5
Test name
Test status
Simulation time 1429890000 ps
CPU time 4.57 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:50 PM PDT 24
Peak memory 164880 kb
Host smart-7ad6d817-b83d-48e1-b591-1f6fd25eaf2e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3732306521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3732306521
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2483752936
Short name T112
Test name
Test status
Simulation time 1506910000 ps
CPU time 4.69 seconds
Started Mar 26 01:50:44 PM PDT 24
Finished Mar 26 01:50:55 PM PDT 24
Peak memory 164488 kb
Host smart-a976ee0e-1c40-4c49-b38d-3021a7fb73e4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2483752936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2483752936
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3266352662
Short name T93
Test name
Test status
Simulation time 1347910000 ps
CPU time 4.72 seconds
Started Mar 26 01:50:37 PM PDT 24
Finished Mar 26 01:50:48 PM PDT 24
Peak memory 164900 kb
Host smart-754ea12b-946c-4179-927e-23546d955fe7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3266352662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3266352662
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3676727762
Short name T103
Test name
Test status
Simulation time 1374450000 ps
CPU time 4.26 seconds
Started Mar 26 01:50:44 PM PDT 24
Finished Mar 26 01:50:54 PM PDT 24
Peak memory 164808 kb
Host smart-f27b8537-3b55-46dd-97b6-6e04e4b1ec19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3676727762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3676727762
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1537903035
Short name T87
Test name
Test status
Simulation time 1379950000 ps
CPU time 4.78 seconds
Started Mar 26 01:50:21 PM PDT 24
Finished Mar 26 01:50:31 PM PDT 24
Peak memory 164800 kb
Host smart-e26b5c66-37af-4c10-93de-24287ff80744
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1537903035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1537903035
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3900725050
Short name T106
Test name
Test status
Simulation time 1494030000 ps
CPU time 6.07 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:52 PM PDT 24
Peak memory 164868 kb
Host smart-1dff453e-6111-4c7b-92b1-dc7b18c93ebd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900725050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3900725050
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.4152143687
Short name T115
Test name
Test status
Simulation time 1350690000 ps
CPU time 4.2 seconds
Started Mar 26 01:50:44 PM PDT 24
Finished Mar 26 01:50:54 PM PDT 24
Peak memory 164372 kb
Host smart-7c04d877-4079-4e0f-b134-508d77d576a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152143687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.4152143687
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3113143783
Short name T111
Test name
Test status
Simulation time 1505950000 ps
CPU time 5.62 seconds
Started Mar 26 01:50:38 PM PDT 24
Finished Mar 26 01:50:50 PM PDT 24
Peak memory 164948 kb
Host smart-0134dab4-4526-4226-bea8-c5ac3fa07d35
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3113143783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3113143783
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1068559806
Short name T6
Test name
Test status
Simulation time 1334570000 ps
CPU time 4.79 seconds
Started Mar 26 01:50:39 PM PDT 24
Finished Mar 26 01:50:50 PM PDT 24
Peak memory 164924 kb
Host smart-31627a11-60f6-4c3d-866d-e213d0a752b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1068559806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1068559806
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.774171294
Short name T81
Test name
Test status
Simulation time 1307990000 ps
CPU time 2.99 seconds
Started Mar 26 01:50:37 PM PDT 24
Finished Mar 26 01:50:44 PM PDT 24
Peak memory 164808 kb
Host smart-c72de05f-1f19-4806-bdb4-77f19b18f6ea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=774171294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.774171294
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1842542295
Short name T30
Test name
Test status
Simulation time 1455370000 ps
CPU time 4.59 seconds
Started Mar 26 01:50:38 PM PDT 24
Finished Mar 26 01:50:48 PM PDT 24
Peak memory 164848 kb
Host smart-e0a8ff15-1205-4d51-b6c8-a0e883448d8a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1842542295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1842542295
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1614735419
Short name T91
Test name
Test status
Simulation time 1357490000 ps
CPU time 5.06 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:57 PM PDT 24
Peak memory 164844 kb
Host smart-5fa704af-726c-4fb4-88d6-eee7647fb08e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1614735419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1614735419
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.605342518
Short name T105
Test name
Test status
Simulation time 1540770000 ps
CPU time 3.26 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:53 PM PDT 24
Peak memory 164784 kb
Host smart-b32da2d8-b39b-43df-bf04-8d13ed127885
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605342518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.605342518
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3752043682
Short name T95
Test name
Test status
Simulation time 1538230000 ps
CPU time 4.65 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:57 PM PDT 24
Peak memory 164836 kb
Host smart-dcd85733-35af-4eb4-a501-f75570a1eb88
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3752043682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3752043682
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2905064959
Short name T25
Test name
Test status
Simulation time 1446870000 ps
CPU time 4.02 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:56 PM PDT 24
Peak memory 164920 kb
Host smart-8e731058-9702-451c-a8f5-5009c65dd0f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2905064959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2905064959
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3177504292
Short name T27
Test name
Test status
Simulation time 1248370000 ps
CPU time 2.91 seconds
Started Mar 26 01:50:21 PM PDT 24
Finished Mar 26 01:50:27 PM PDT 24
Peak memory 164880 kb
Host smart-49ec6386-8921-4faf-a8b1-5fd8b2b81215
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3177504292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3177504292
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1321318593
Short name T120
Test name
Test status
Simulation time 1185650000 ps
CPU time 4.09 seconds
Started Mar 26 01:50:23 PM PDT 24
Finished Mar 26 01:50:32 PM PDT 24
Peak memory 164872 kb
Host smart-e9673cf1-f29a-47f9-a58d-0d890bb91d8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1321318593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1321318593
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4016964609
Short name T86
Test name
Test status
Simulation time 1424270000 ps
CPU time 5.88 seconds
Started Mar 26 01:50:21 PM PDT 24
Finished Mar 26 01:50:33 PM PDT 24
Peak memory 164864 kb
Host smart-13b3a175-cebd-4832-82dc-4ec3f84c3a83
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4016964609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.4016964609
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.524933756
Short name T118
Test name
Test status
Simulation time 1557110000 ps
CPU time 6.25 seconds
Started Mar 26 01:50:21 PM PDT 24
Finished Mar 26 01:50:34 PM PDT 24
Peak memory 164872 kb
Host smart-3f8d84f0-d398-4974-8ba0-7eb2bed99a8d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=524933756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.524933756
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1279517791
Short name T28
Test name
Test status
Simulation time 1198070000 ps
CPU time 5.02 seconds
Started Mar 26 01:50:21 PM PDT 24
Finished Mar 26 01:50:32 PM PDT 24
Peak memory 164816 kb
Host smart-24ad0014-8d1c-46dc-b1da-2f8dc20c8a16
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279517791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1279517791
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4038523141
Short name T70
Test name
Test status
Simulation time 1316350000 ps
CPU time 2.76 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:52 PM PDT 24
Peak memory 164784 kb
Host smart-5d29cd44-aee4-4074-a40e-fc3e25389da3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4038523141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4038523141
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.277968630
Short name T43
Test name
Test status
Simulation time 1559110000 ps
CPU time 5.18 seconds
Started Mar 26 01:50:51 PM PDT 24
Finished Mar 26 01:51:03 PM PDT 24
Peak memory 164980 kb
Host smart-583e7e77-2b9c-49ba-83ba-15ec739ce08a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=277968630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.277968630
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3135157056
Short name T79
Test name
Test status
Simulation time 1311790000 ps
CPU time 5.2 seconds
Started Mar 26 01:50:47 PM PDT 24
Finished Mar 26 01:50:58 PM PDT 24
Peak memory 164876 kb
Host smart-d7a6c27d-b7ee-45cd-96c2-c36d0e726cff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3135157056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3135157056
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2057014658
Short name T55
Test name
Test status
Simulation time 1589370000 ps
CPU time 5.44 seconds
Started Mar 26 01:50:45 PM PDT 24
Finished Mar 26 01:50:57 PM PDT 24
Peak memory 164900 kb
Host smart-e58d5706-a9d1-4bb1-b9da-0e8e6b17a36e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2057014658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2057014658
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3492982664
Short name T42
Test name
Test status
Simulation time 1504970000 ps
CPU time 4.57 seconds
Started Mar 26 01:50:51 PM PDT 24
Finished Mar 26 01:51:02 PM PDT 24
Peak memory 164916 kb
Host smart-bcd1b886-75d2-4161-9875-5c3ed1bfcc83
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3492982664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3492982664
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.378025625
Short name T54
Test name
Test status
Simulation time 1548390000 ps
CPU time 5.95 seconds
Started Mar 26 01:50:50 PM PDT 24
Finished Mar 26 01:51:03 PM PDT 24
Peak memory 164876 kb
Host smart-6ac161f5-9633-4915-8ac1-d412d8504316
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=378025625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.378025625
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1841411643
Short name T41
Test name
Test status
Simulation time 1109430000 ps
CPU time 3.8 seconds
Started Mar 26 01:50:45 PM PDT 24
Finished Mar 26 01:50:54 PM PDT 24
Peak memory 164924 kb
Host smart-9cd80d2d-ec56-4a63-9231-a024f0561645
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1841411643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1841411643
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1785648093
Short name T47
Test name
Test status
Simulation time 1561330000 ps
CPU time 3.95 seconds
Started Mar 26 01:50:52 PM PDT 24
Finished Mar 26 01:51:01 PM PDT 24
Peak memory 164884 kb
Host smart-a7e176ae-7510-435d-a3de-cd36dc7cb74f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1785648093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1785648093
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2308894156
Short name T69
Test name
Test status
Simulation time 1608510000 ps
CPU time 4.84 seconds
Started Mar 26 01:50:56 PM PDT 24
Finished Mar 26 01:51:08 PM PDT 24
Peak memory 164900 kb
Host smart-744f465a-aeb6-46ab-a716-17345af73b5a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2308894156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2308894156
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4183152486
Short name T45
Test name
Test status
Simulation time 1368590000 ps
CPU time 4.69 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:03 PM PDT 24
Peak memory 164924 kb
Host smart-50e00a0d-69d0-4200-ab62-f9f95df03e85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4183152486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4183152486
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3030870176
Short name T12
Test name
Test status
Simulation time 1597310000 ps
CPU time 4.71 seconds
Started Mar 26 01:50:55 PM PDT 24
Finished Mar 26 01:51:05 PM PDT 24
Peak memory 164828 kb
Host smart-ad2ef6e5-2160-4796-82be-a35e00b2e04a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3030870176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3030870176
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4252981436
Short name T57
Test name
Test status
Simulation time 1545410000 ps
CPU time 4.32 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:55 PM PDT 24
Peak memory 164872 kb
Host smart-d31bed35-a7f3-40c0-be27-2db08d9d80dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252981436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4252981436
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1590027510
Short name T74
Test name
Test status
Simulation time 1397330000 ps
CPU time 5.72 seconds
Started Mar 26 01:50:54 PM PDT 24
Finished Mar 26 01:51:07 PM PDT 24
Peak memory 164848 kb
Host smart-2f060af2-2200-4374-ac4f-d33ab1be0fec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1590027510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1590027510
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3026465525
Short name T1
Test name
Test status
Simulation time 1556630000 ps
CPU time 5.1 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:04 PM PDT 24
Peak memory 164900 kb
Host smart-c47f676b-c97c-4624-86f2-d1673d403ea6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3026465525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3026465525
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3664890320
Short name T60
Test name
Test status
Simulation time 1511550000 ps
CPU time 5.95 seconds
Started Mar 26 01:50:52 PM PDT 24
Finished Mar 26 01:51:07 PM PDT 24
Peak memory 164872 kb
Host smart-9d590914-36c8-41f0-865a-48ae49fab3a3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3664890320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3664890320
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4241237121
Short name T64
Test name
Test status
Simulation time 1512590000 ps
CPU time 4.97 seconds
Started Mar 26 01:50:54 PM PDT 24
Finished Mar 26 01:51:05 PM PDT 24
Peak memory 164884 kb
Host smart-0ed18662-cb94-4098-af41-4bfe15b0a656
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4241237121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4241237121
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.228325226
Short name T56
Test name
Test status
Simulation time 1418130000 ps
CPU time 4.1 seconds
Started Mar 26 01:50:58 PM PDT 24
Finished Mar 26 01:51:07 PM PDT 24
Peak memory 164820 kb
Host smart-0a3ea71e-a77d-4681-aecd-724a0033f01d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=228325226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.228325226
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1010693389
Short name T2
Test name
Test status
Simulation time 1368570000 ps
CPU time 4.09 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:02 PM PDT 24
Peak memory 164824 kb
Host smart-e4149e0c-aba4-4af2-ba6a-f1cd79eaabd7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1010693389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1010693389
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3562914525
Short name T59
Test name
Test status
Simulation time 1332850000 ps
CPU time 5.04 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:05 PM PDT 24
Peak memory 164936 kb
Host smart-8e28a796-f25e-4ee0-b5a0-cea39acdb0bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3562914525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3562914525
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4066473838
Short name T78
Test name
Test status
Simulation time 1580090000 ps
CPU time 5.98 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:06 PM PDT 24
Peak memory 164872 kb
Host smart-edb24a08-4fe8-4f31-9832-da2452e32e69
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4066473838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4066473838
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1952983994
Short name T66
Test name
Test status
Simulation time 1529590000 ps
CPU time 4.18 seconds
Started Mar 26 01:51:00 PM PDT 24
Finished Mar 26 01:51:09 PM PDT 24
Peak memory 164808 kb
Host smart-5477e1c3-5a01-4ab7-b4e9-85a9c9684e8b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952983994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1952983994
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.8268947
Short name T68
Test name
Test status
Simulation time 1559010000 ps
CPU time 5.5 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:05 PM PDT 24
Peak memory 164880 kb
Host smart-f48f8668-0689-4f93-99f4-f81cf4101184
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=8268947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.8268947
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.314683348
Short name T80
Test name
Test status
Simulation time 1355410000 ps
CPU time 5.15 seconds
Started Mar 26 01:50:45 PM PDT 24
Finished Mar 26 01:50:56 PM PDT 24
Peak memory 164844 kb
Host smart-746ba028-9640-4ec0-a737-695270306ae9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=314683348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.314683348
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2477203313
Short name T49
Test name
Test status
Simulation time 1386850000 ps
CPU time 4.33 seconds
Started Mar 26 01:50:54 PM PDT 24
Finished Mar 26 01:51:04 PM PDT 24
Peak memory 164900 kb
Host smart-61ce20e6-4144-4f05-b5f4-d70b663a6413
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477203313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2477203313
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1972968491
Short name T9
Test name
Test status
Simulation time 1569670000 ps
CPU time 3.83 seconds
Started Mar 26 01:50:52 PM PDT 24
Finished Mar 26 01:51:01 PM PDT 24
Peak memory 164884 kb
Host smart-ec699e5a-e085-4f86-b67a-5c4449e82dec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1972968491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1972968491
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1467596225
Short name T72
Test name
Test status
Simulation time 1365350000 ps
CPU time 6.2 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:06 PM PDT 24
Peak memory 164928 kb
Host smart-1847518d-69ae-4004-89f8-cd282fe69e7b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467596225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1467596225
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2750399143
Short name T52
Test name
Test status
Simulation time 1311350000 ps
CPU time 4.75 seconds
Started Mar 26 01:50:52 PM PDT 24
Finished Mar 26 01:51:02 PM PDT 24
Peak memory 164892 kb
Host smart-ce82bc26-318b-45a4-8cad-267626a95d4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2750399143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2750399143
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.873512263
Short name T3
Test name
Test status
Simulation time 1485250000 ps
CPU time 3.89 seconds
Started Mar 26 01:50:59 PM PDT 24
Finished Mar 26 01:51:08 PM PDT 24
Peak memory 164840 kb
Host smart-bf39220f-d6fd-4dc2-af5f-8a68fd15e732
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=873512263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.873512263
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3205591747
Short name T63
Test name
Test status
Simulation time 1555670000 ps
CPU time 5.87 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:07 PM PDT 24
Peak memory 164904 kb
Host smart-98db3105-8fe5-44ae-aa4f-f3f0fe6efa5d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205591747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3205591747
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1877365911
Short name T71
Test name
Test status
Simulation time 1464110000 ps
CPU time 4.71 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:04 PM PDT 24
Peak memory 164928 kb
Host smart-46ffddbe-9a25-4d13-9f28-a46cc49a088d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877365911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1877365911
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.797550784
Short name T4
Test name
Test status
Simulation time 1583870000 ps
CPU time 4.25 seconds
Started Mar 26 01:50:54 PM PDT 24
Finished Mar 26 01:51:04 PM PDT 24
Peak memory 164892 kb
Host smart-c15decec-2890-42c0-adf4-b921e3282d76
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797550784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.797550784
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1133817996
Short name T67
Test name
Test status
Simulation time 1169050000 ps
CPU time 3.47 seconds
Started Mar 26 01:50:59 PM PDT 24
Finished Mar 26 01:51:06 PM PDT 24
Peak memory 164808 kb
Host smart-2c004b58-955f-488a-b39a-e4787ac11f7b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1133817996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1133817996
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3422344728
Short name T77
Test name
Test status
Simulation time 1429050000 ps
CPU time 4.19 seconds
Started Mar 26 01:51:07 PM PDT 24
Finished Mar 26 01:51:16 PM PDT 24
Peak memory 164884 kb
Host smart-445bfe68-bfdf-4cee-9f34-d69ab5039d3a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3422344728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3422344728
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2234320019
Short name T58
Test name
Test status
Simulation time 1530770000 ps
CPU time 6.25 seconds
Started Mar 26 01:50:45 PM PDT 24
Finished Mar 26 01:51:00 PM PDT 24
Peak memory 164880 kb
Host smart-56b3ee13-4fec-4d31-a465-c6e2dd35e2e6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2234320019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2234320019
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3027641504
Short name T75
Test name
Test status
Simulation time 1285310000 ps
CPU time 4.73 seconds
Started Mar 26 01:51:05 PM PDT 24
Finished Mar 26 01:51:15 PM PDT 24
Peak memory 164824 kb
Host smart-44e759d7-b9b7-42c9-b9ae-564db9a63719
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3027641504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3027641504
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2768150477
Short name T51
Test name
Test status
Simulation time 1493550000 ps
CPU time 3.22 seconds
Started Mar 26 01:51:00 PM PDT 24
Finished Mar 26 01:51:07 PM PDT 24
Peak memory 164820 kb
Host smart-12822562-c928-43da-b482-3ae793f30dab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768150477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2768150477
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2213964854
Short name T44
Test name
Test status
Simulation time 1404310000 ps
CPU time 5.08 seconds
Started Mar 26 01:51:05 PM PDT 24
Finished Mar 26 01:51:16 PM PDT 24
Peak memory 164780 kb
Host smart-dfbbb0de-d58d-4800-9802-2d00eb14a4ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2213964854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2213964854
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3937781654
Short name T65
Test name
Test status
Simulation time 1568490000 ps
CPU time 3.32 seconds
Started Mar 26 01:51:02 PM PDT 24
Finished Mar 26 01:51:10 PM PDT 24
Peak memory 164884 kb
Host smart-8f3079fe-84e1-4bf3-a013-78bb75e811ee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3937781654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3937781654
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3559382218
Short name T46
Test name
Test status
Simulation time 1417870000 ps
CPU time 3.98 seconds
Started Mar 26 01:51:07 PM PDT 24
Finished Mar 26 01:51:16 PM PDT 24
Peak memory 164872 kb
Host smart-74db6d7d-47b4-4bda-a154-51ae093e2706
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3559382218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3559382218
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2666196569
Short name T62
Test name
Test status
Simulation time 1540190000 ps
CPU time 5.2 seconds
Started Mar 26 01:51:01 PM PDT 24
Finished Mar 26 01:51:12 PM PDT 24
Peak memory 164828 kb
Host smart-85119bbb-b917-4542-be0b-3d7e66f01625
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2666196569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2666196569
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2661819718
Short name T11
Test name
Test status
Simulation time 1109670000 ps
CPU time 4.38 seconds
Started Mar 26 01:51:00 PM PDT 24
Finished Mar 26 01:51:10 PM PDT 24
Peak memory 164928 kb
Host smart-b8f2253d-0c67-43c5-9d15-eb7373bf9dd2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2661819718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2661819718
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2041536739
Short name T10
Test name
Test status
Simulation time 1554050000 ps
CPU time 4.1 seconds
Started Mar 26 01:51:07 PM PDT 24
Finished Mar 26 01:51:16 PM PDT 24
Peak memory 164884 kb
Host smart-8f5bdf56-f818-4006-8486-70328d54513f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041536739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2041536739
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1200375373
Short name T76
Test name
Test status
Simulation time 1340910000 ps
CPU time 3.8 seconds
Started Mar 26 01:51:05 PM PDT 24
Finished Mar 26 01:51:13 PM PDT 24
Peak memory 164808 kb
Host smart-9b6a6619-5544-4f41-af52-b896b371d584
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200375373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1200375373
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2355271882
Short name T73
Test name
Test status
Simulation time 1275190000 ps
CPU time 4.3 seconds
Started Mar 26 01:51:02 PM PDT 24
Finished Mar 26 01:51:11 PM PDT 24
Peak memory 164928 kb
Host smart-a4bc536d-d376-431f-87a3-9caf57302835
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2355271882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2355271882
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.428886231
Short name T61
Test name
Test status
Simulation time 1518870000 ps
CPU time 6.28 seconds
Started Mar 26 01:50:45 PM PDT 24
Finished Mar 26 01:50:58 PM PDT 24
Peak memory 164948 kb
Host smart-f9d39401-ff48-4656-b1d0-a3d2e7fe27f8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=428886231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.428886231
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1856726006
Short name T50
Test name
Test status
Simulation time 1307290000 ps
CPU time 4.66 seconds
Started Mar 26 01:50:45 PM PDT 24
Finished Mar 26 01:50:55 PM PDT 24
Peak memory 164824 kb
Host smart-f661a38f-757c-478a-ab95-c6dff1212d8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1856726006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1856726006
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3654904238
Short name T53
Test name
Test status
Simulation time 1418970000 ps
CPU time 4.46 seconds
Started Mar 26 01:50:53 PM PDT 24
Finished Mar 26 01:51:03 PM PDT 24
Peak memory 164916 kb
Host smart-8a342165-bb91-4fc7-a354-1136574422ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654904238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3654904238
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1997592575
Short name T8
Test name
Test status
Simulation time 1461990000 ps
CPU time 5.18 seconds
Started Mar 26 01:50:51 PM PDT 24
Finished Mar 26 01:51:03 PM PDT 24
Peak memory 164916 kb
Host smart-b368250d-212d-4e14-b885-8a496ba8c948
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997592575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1997592575
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1468205316
Short name T48
Test name
Test status
Simulation time 1546690000 ps
CPU time 3.33 seconds
Started Mar 26 01:50:46 PM PDT 24
Finished Mar 26 01:50:54 PM PDT 24
Peak memory 164808 kb
Host smart-8ad03a5c-4757-4729-8c56-0b6a27481951
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1468205316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1468205316
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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