Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3421784409
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.848392799
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3666445836

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.882616301
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.46907010
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2990521074
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.896759824
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1995224345
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.622455927
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.252504092
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2545135507
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2920099996
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4232032154
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4039644485
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3643588172
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.662402113
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.498821077
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3318216824
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1205477446
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1674000944
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1733526986
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3352536965
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2215315639
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2216918065
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2531369735
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2688648026
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1018215889
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3302967490
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.54840772
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1566754695
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1195934966
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2296374346
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3924462108
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2085822891
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.181709052
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1469945669
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1411519499
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3016061136
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3692377739
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3688103679
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2657881594
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3449476080
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.29967012
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2379419412
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2935891306
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3772653946
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1940049310
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3383871910
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3031451403
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4068514716
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1058021530
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3593087311
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2768359765
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3603238358
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4045143016
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.295779630
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2819505987
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.537860811
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1201409250
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1288954412
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.174202233
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.872371650
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3692398058
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.480842269
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3344274387
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4160973331
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3155165479
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3132281097
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3274040027
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2499151289
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.747222494
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3720440920
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.842694809
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2340981080
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3754251727
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1287390849
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.687589275
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2804808040
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3689926056
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1896953068
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3006066834
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4108637903
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3843438408
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3415011680
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.245065955
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3120344570
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1593320478
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.877643569
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3074744033
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3545357281
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.289429093
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3832145658
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2237762611
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3723698623
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3722027065
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1600618941
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1647256076
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1756092851
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1622435941
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1060107462
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3813569488
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1825909657
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.216356268
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.517658771
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4031364736
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1908525294
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1177977660
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4259042394
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2385599128
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3371919013
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2328088039
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.631393583
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2840697179
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2180019083
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3078128376
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.298666401
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1504357470
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2519242718
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3280609817
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2245811939
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2694314679
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.627605333
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3134726562
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2562630576
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2986971223
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3393265018
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.206204597
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2664187343
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2589868834
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.222311325
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1611870464
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1363385204
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2857196634
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.288974250
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.846759265
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2870085922
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3788816539
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1159007194
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4059733528
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1968013152
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3352576188
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3175276270
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.398220428
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3277100590
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2267094705
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4290257468
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4246482959
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1532360495
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.717118218
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.714728788
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1177105463
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2750687618
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3507120579
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.347126889
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2825203687
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1922395846
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2072621148
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.818396232
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.85096550
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4245907112
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3476288053
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3757378798
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1477459803
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2588472136
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2099422568
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2389057040
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2366885581
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.119319748
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.388576988
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3075162
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2271044838
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2030140937
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3742575799
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1182630893
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.159265802
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4108209504
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4047231418
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.459621421
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3016020215
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3534335367
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1911561441
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1200834475
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.495605685
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2687628089
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3620271942
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.724091216
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2272193628
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2728551346
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.26233891
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2525096350
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.7467134
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2631321953
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4253044018
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3102124826
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1262071705
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1813562485
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.165275362
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1666035940
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3514694483
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1155503794



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.85096550 Mar 28 12:43:26 PM PDT 24 Mar 28 12:43:33 PM PDT 24 1554330000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4245907112 Mar 28 12:43:25 PM PDT 24 Mar 28 12:43:33 PM PDT 24 1551870000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2030140937 Mar 28 12:43:24 PM PDT 24 Mar 28 12:43:34 PM PDT 24 1491710000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.388576988 Mar 28 12:43:25 PM PDT 24 Mar 28 12:43:36 PM PDT 24 1479850000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3742575799 Mar 28 12:43:27 PM PDT 24 Mar 28 12:43:39 PM PDT 24 1387810000 ps
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T139 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4259042394 Mar 28 12:34:58 PM PDT 24 Mar 28 12:35:05 PM PDT 24 1428510000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.298666401 Mar 28 12:34:58 PM PDT 24 Mar 28 12:35:10 PM PDT 24 1349770000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3280609817 Mar 28 12:34:58 PM PDT 24 Mar 28 12:35:13 PM PDT 24 1412310000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1504357470 Mar 28 12:35:00 PM PDT 24 Mar 28 12:35:09 PM PDT 24 1212550000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1611870464 Mar 28 12:34:54 PM PDT 24 Mar 28 12:35:01 PM PDT 24 1363490000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4290257468 Mar 28 12:35:05 PM PDT 24 Mar 28 12:35:19 PM PDT 24 1189810000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4059733528 Mar 28 12:34:58 PM PDT 24 Mar 28 12:35:06 PM PDT 24 1422450000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.398220428 Mar 28 12:34:56 PM PDT 24 Mar 28 12:35:05 PM PDT 24 1028390000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1908525294 Mar 28 12:34:54 PM PDT 24 Mar 28 12:35:06 PM PDT 24 1520730000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3371919013 Mar 28 12:34:45 PM PDT 24 Mar 28 12:34:52 PM PDT 24 1330690000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2328088039 Mar 28 12:34:51 PM PDT 24 Mar 28 12:34:58 PM PDT 24 1572290000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3175276270 Mar 28 12:34:54 PM PDT 24 Mar 28 12:35:03 PM PDT 24 1342790000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1532360495 Mar 28 12:34:54 PM PDT 24 Mar 28 12:35:06 PM PDT 24 1592870000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3277100590 Mar 28 12:34:52 PM PDT 24 Mar 28 12:35:02 PM PDT 24 1476690000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.206204597 Mar 28 12:34:51 PM PDT 24 Mar 28 12:35:02 PM PDT 24 1498690000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2870085922 Mar 28 12:34:52 PM PDT 24 Mar 28 12:35:00 PM PDT 24 1519350000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2245811939 Mar 28 12:34:52 PM PDT 24 Mar 28 12:35:01 PM PDT 24 1361650000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3393265018 Mar 28 12:34:51 PM PDT 24 Mar 28 12:35:00 PM PDT 24 1341650000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1968013152 Mar 28 12:35:12 PM PDT 24 Mar 28 12:35:24 PM PDT 24 1563690000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2385599128 Mar 28 12:34:51 PM PDT 24 Mar 28 12:35:01 PM PDT 24 1377310000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1177105463 Mar 28 12:34:54 PM PDT 24 Mar 28 12:35:00 PM PDT 24 1310970000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2694314679 Mar 28 12:34:51 PM PDT 24 Mar 28 12:35:04 PM PDT 24 1526190000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3813569488 Mar 28 12:34:53 PM PDT 24 Mar 28 12:59:49 PM PDT 24 336540890000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3132281097 Mar 28 12:35:01 PM PDT 24 Mar 28 01:13:06 PM PDT 24 337004670000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4045143016 Mar 28 12:35:02 PM PDT 24 Mar 28 01:12:48 PM PDT 24 336437270000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3006066834 Mar 28 12:34:59 PM PDT 24 Mar 28 01:14:26 PM PDT 24 336935210000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1287390849 Mar 28 12:35:01 PM PDT 24 Mar 28 01:13:15 PM PDT 24 336937370000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2804808040 Mar 28 12:34:59 PM PDT 24 Mar 28 01:11:52 PM PDT 24 336833810000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3666445836 Mar 28 12:34:57 PM PDT 24 Mar 28 01:10:26 PM PDT 24 337009070000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2499151289 Mar 28 12:35:07 PM PDT 24 Mar 28 01:13:30 PM PDT 24 337049990000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3344274387 Mar 28 12:35:09 PM PDT 24 Mar 28 01:11:47 PM PDT 24 336698290000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.480842269 Mar 28 12:34:52 PM PDT 24 Mar 28 01:00:28 PM PDT 24 336401350000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1647256076 Mar 28 12:34:55 PM PDT 24 Mar 28 01:03:38 PM PDT 24 336321950000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2768359765 Mar 28 12:34:57 PM PDT 24 Mar 28 01:07:20 PM PDT 24 336508210000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4108637903 Mar 28 12:35:01 PM PDT 24 Mar 28 01:12:58 PM PDT 24 336697990000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3832145658 Mar 28 12:35:02 PM PDT 24 Mar 28 01:13:22 PM PDT 24 336926450000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3754251727 Mar 28 12:35:08 PM PDT 24 Mar 28 01:10:59 PM PDT 24 337136610000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1896953068 Mar 28 12:34:59 PM PDT 24 Mar 28 01:15:08 PM PDT 24 336825230000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3415011680 Mar 28 12:34:57 PM PDT 24 Mar 28 01:12:48 PM PDT 24 336909370000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1600618941 Mar 28 12:35:03 PM PDT 24 Mar 28 01:15:36 PM PDT 24 336998750000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.289429093 Mar 28 12:34:59 PM PDT 24 Mar 28 01:14:40 PM PDT 24 336607930000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.687589275 Mar 28 12:34:54 PM PDT 24 Mar 28 01:07:02 PM PDT 24 337058610000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3155165479 Mar 28 12:34:52 PM PDT 24 Mar 28 01:03:46 PM PDT 24 336329570000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.245065955 Mar 28 12:35:02 PM PDT 24 Mar 28 01:13:32 PM PDT 24 336856270000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3274040027 Mar 28 12:35:08 PM PDT 24 Mar 28 01:13:06 PM PDT 24 336418730000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.174202233 Mar 28 12:35:09 PM PDT 24 Mar 28 01:10:49 PM PDT 24 336801030000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2340981080 Mar 28 12:35:03 PM PDT 24 Mar 28 01:13:14 PM PDT 24 336984430000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.872371650 Mar 28 12:34:57 PM PDT 24 Mar 28 01:12:06 PM PDT 24 336693210000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.537860811 Mar 28 12:35:08 PM PDT 24 Mar 28 01:13:21 PM PDT 24 336789790000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3074744033 Mar 28 12:34:59 PM PDT 24 Mar 28 01:15:16 PM PDT 24 336952370000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1756092851 Mar 28 12:35:06 PM PDT 24 Mar 28 01:09:13 PM PDT 24 336824450000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1593320478 Mar 28 12:34:58 PM PDT 24 Mar 28 01:12:04 PM PDT 24 336918770000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3689926056 Mar 28 12:35:00 PM PDT 24 Mar 28 01:14:42 PM PDT 24 336741470000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3545357281 Mar 28 12:34:47 PM PDT 24 Mar 28 01:13:53 PM PDT 24 336792910000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1288954412 Mar 28 12:34:52 PM PDT 24 Mar 28 01:06:44 PM PDT 24 337068690000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3603238358 Mar 28 12:35:08 PM PDT 24 Mar 28 01:16:24 PM PDT 24 336620790000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2819505987 Mar 28 12:34:57 PM PDT 24 Mar 28 01:12:42 PM PDT 24 336786350000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1201409250 Mar 28 12:35:10 PM PDT 24 Mar 28 01:10:39 PM PDT 24 336966990000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2237762611 Mar 28 12:34:59 PM PDT 24 Mar 28 01:14:16 PM PDT 24 336340090000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3723698623 Mar 28 12:34:53 PM PDT 24 Mar 28 01:11:18 PM PDT 24 336377270000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3720440920 Mar 28 12:35:00 PM PDT 24 Mar 28 01:13:13 PM PDT 24 336491630000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1060107462 Mar 28 12:34:57 PM PDT 24 Mar 28 01:05:46 PM PDT 24 337011210000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4160973331 Mar 28 12:35:04 PM PDT 24 Mar 28 01:14:21 PM PDT 24 337165050000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3722027065 Mar 28 12:34:49 PM PDT 24 Mar 28 01:13:26 PM PDT 24 336497210000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.747222494 Mar 28 12:34:53 PM PDT 24 Mar 28 01:13:17 PM PDT 24 336396610000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.295779630 Mar 28 12:34:53 PM PDT 24 Mar 28 01:05:50 PM PDT 24 336819690000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.842694809 Mar 28 12:35:06 PM PDT 24 Mar 28 01:09:06 PM PDT 24 336743890000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.877643569 Mar 28 12:34:58 PM PDT 24 Mar 28 01:11:57 PM PDT 24 336529090000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3120344570 Mar 28 12:35:05 PM PDT 24 Mar 28 01:16:34 PM PDT 24 336759490000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1622435941 Mar 28 12:35:06 PM PDT 24 Mar 28 01:16:32 PM PDT 24 336538230000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3843438408 Mar 28 12:35:03 PM PDT 24 Mar 28 01:06:18 PM PDT 24 336534930000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3692398058 Mar 28 12:34:55 PM PDT 24 Mar 28 01:07:01 PM PDT 24 336347490000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3421784409
Short name T13
Test name
Test status
Simulation time 1501210000 ps
CPU time 4.44 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:32 PM PDT 24
Peak memory 164924 kb
Host smart-3260f429-2476-496e-8efb-47bfd3a182ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3421784409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3421784409
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.848392799
Short name T14
Test name
Test status
Simulation time 336309730000 ps
CPU time 929.89 seconds
Started Mar 28 12:40:11 PM PDT 24
Finished Mar 28 01:18:32 PM PDT 24
Peak memory 160688 kb
Host smart-06d69198-dc15-4a30-aca8-8eaf1e2d0c02
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=848392799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.848392799
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3666445836
Short name T27
Test name
Test status
Simulation time 337009070000 ps
CPU time 855.46 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 01:10:26 PM PDT 24
Peak memory 160688 kb
Host smart-4b4552a6-f168-45d0-8be0-2187d12660fe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3666445836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3666445836
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.882616301
Short name T78
Test name
Test status
Simulation time 337117950000 ps
CPU time 999.42 seconds
Started Mar 28 12:39:42 PM PDT 24
Finished Mar 28 01:20:40 PM PDT 24
Peak memory 160708 kb
Host smart-0ba8d90b-e7a5-4d0e-8f6a-be889907b30e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=882616301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.882616301
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.46907010
Short name T80
Test name
Test status
Simulation time 337055370000 ps
CPU time 780.03 seconds
Started Mar 28 12:40:11 PM PDT 24
Finished Mar 28 01:11:58 PM PDT 24
Peak memory 160700 kb
Host smart-7c95385b-d711-4718-b63f-bc2785abee1a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=46907010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.46907010
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2990521074
Short name T90
Test name
Test status
Simulation time 336874110000 ps
CPU time 757.33 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 01:10:30 PM PDT 24
Peak memory 160796 kb
Host smart-eed11b94-07cd-49dc-97dd-2a0e16d8257b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2990521074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2990521074
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.896759824
Short name T102
Test name
Test status
Simulation time 336394790000 ps
CPU time 631.04 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 01:05:45 PM PDT 24
Peak memory 160708 kb
Host smart-8ae57028-4b14-4cf7-bbf2-51e83a349eb7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=896759824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.896759824
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1995224345
Short name T93
Test name
Test status
Simulation time 336402950000 ps
CPU time 845.33 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 01:14:14 PM PDT 24
Peak memory 160700 kb
Host smart-eacd93a6-281f-4ac5-b557-43a9485dd999
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1995224345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1995224345
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.622455927
Short name T105
Test name
Test status
Simulation time 336585150000 ps
CPU time 863 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 01:14:47 PM PDT 24
Peak memory 160688 kb
Host smart-c83368e8-50fe-4ba5-84d1-570114a83622
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622455927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.622455927
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.252504092
Short name T77
Test name
Test status
Simulation time 336652850000 ps
CPU time 635.42 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 01:05:55 PM PDT 24
Peak memory 160764 kb
Host smart-7438d170-5468-4935-8578-3d4ebd748439
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=252504092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.252504092
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2545135507
Short name T94
Test name
Test status
Simulation time 336863970000 ps
CPU time 745.46 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 01:10:12 PM PDT 24
Peak memory 160700 kb
Host smart-6e698ee4-83fe-4004-88b7-75b7ee01b289
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2545135507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2545135507
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2920099996
Short name T79
Test name
Test status
Simulation time 336371990000 ps
CPU time 956.12 seconds
Started Mar 28 12:39:34 PM PDT 24
Finished Mar 28 01:19:12 PM PDT 24
Peak memory 160664 kb
Host smart-a4e9ec11-0f18-487f-8bbb-d64c31361374
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2920099996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2920099996
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4232032154
Short name T109
Test name
Test status
Simulation time 336377710000 ps
CPU time 980.17 seconds
Started Mar 28 12:40:03 PM PDT 24
Finished Mar 28 01:19:38 PM PDT 24
Peak memory 160696 kb
Host smart-415c7cf4-50db-4ff7-9937-b484378114c5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4232032154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4232032154
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4039644485
Short name T106
Test name
Test status
Simulation time 336911650000 ps
CPU time 773.34 seconds
Started Mar 28 12:40:13 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 160712 kb
Host smart-e4ac4d48-02c5-403b-a266-b334062e9cb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4039644485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.4039644485
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3643588172
Short name T19
Test name
Test status
Simulation time 336854510000 ps
CPU time 812.39 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 01:12:45 PM PDT 24
Peak memory 160696 kb
Host smart-e1db955b-9137-460a-8070-d901502620b2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3643588172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3643588172
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.662402113
Short name T84
Test name
Test status
Simulation time 336668730000 ps
CPU time 710.28 seconds
Started Mar 28 12:40:01 PM PDT 24
Finished Mar 28 01:09:29 PM PDT 24
Peak memory 160700 kb
Host smart-5ebeb675-6991-4613-a3c3-8c6ae3e50553
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=662402113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.662402113
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.498821077
Short name T4
Test name
Test status
Simulation time 336946310000 ps
CPU time 822.12 seconds
Started Mar 28 12:40:06 PM PDT 24
Finished Mar 28 01:13:43 PM PDT 24
Peak memory 160684 kb
Host smart-98ec7f9d-a5ff-4a60-9677-1901236005d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=498821077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.498821077
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3318216824
Short name T75
Test name
Test status
Simulation time 336876630000 ps
CPU time 860.22 seconds
Started Mar 28 12:40:04 PM PDT 24
Finished Mar 28 01:15:47 PM PDT 24
Peak memory 160712 kb
Host smart-186b60e6-dcbf-4e45-9895-d64ff34d9a2b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3318216824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3318216824
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1205477446
Short name T73
Test name
Test status
Simulation time 336588190000 ps
CPU time 924.53 seconds
Started Mar 28 12:40:07 PM PDT 24
Finished Mar 28 01:17:59 PM PDT 24
Peak memory 160672 kb
Host smart-03ffe39c-5be2-4a9a-af32-e9b3e0b856c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1205477446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1205477446
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1674000944
Short name T97
Test name
Test status
Simulation time 336972470000 ps
CPU time 711.04 seconds
Started Mar 28 12:40:04 PM PDT 24
Finished Mar 28 01:09:30 PM PDT 24
Peak memory 160712 kb
Host smart-a3259b77-6035-4821-815b-cae6c5153072
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1674000944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1674000944
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1733526986
Short name T5
Test name
Test status
Simulation time 336376290000 ps
CPU time 829.68 seconds
Started Mar 28 12:40:07 PM PDT 24
Finished Mar 28 01:14:13 PM PDT 24
Peak memory 160684 kb
Host smart-2ba825f0-4c05-4184-b81c-450a376c6a95
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1733526986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1733526986
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3352536965
Short name T88
Test name
Test status
Simulation time 336440110000 ps
CPU time 973.98 seconds
Started Mar 28 12:40:15 PM PDT 24
Finished Mar 28 01:20:23 PM PDT 24
Peak memory 160704 kb
Host smart-74e17ac5-ae0a-4653-95b2-74a84af4a06f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3352536965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3352536965
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2215315639
Short name T83
Test name
Test status
Simulation time 337043050000 ps
CPU time 906.82 seconds
Started Mar 28 12:40:06 PM PDT 24
Finished Mar 28 01:17:19 PM PDT 24
Peak memory 160704 kb
Host smart-211b4ea2-abe2-4140-98bf-873684892be4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2215315639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2215315639
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2216918065
Short name T91
Test name
Test status
Simulation time 336892890000 ps
CPU time 872.31 seconds
Started Mar 28 12:40:05 PM PDT 24
Finished Mar 28 01:16:21 PM PDT 24
Peak memory 160716 kb
Host smart-cb36599d-11d6-4e8f-8544-dce03b6212be
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2216918065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2216918065
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2531369735
Short name T104
Test name
Test status
Simulation time 336564550000 ps
CPU time 970.68 seconds
Started Mar 28 12:40:18 PM PDT 24
Finished Mar 28 01:20:20 PM PDT 24
Peak memory 160704 kb
Host smart-7dc01533-27d8-44fb-b3b8-d4557cec29ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2531369735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2531369735
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2688648026
Short name T86
Test name
Test status
Simulation time 336538850000 ps
CPU time 752.03 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 01:10:34 PM PDT 24
Peak memory 160712 kb
Host smart-c3b7fcdf-a43f-4fdf-b649-e9d6a1b757a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2688648026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2688648026
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1018215889
Short name T95
Test name
Test status
Simulation time 337111850000 ps
CPU time 988.65 seconds
Started Mar 28 12:40:07 PM PDT 24
Finished Mar 28 01:20:49 PM PDT 24
Peak memory 160692 kb
Host smart-94e9b78f-7b74-4857-aecc-b26569b22213
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1018215889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1018215889
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3302967490
Short name T100
Test name
Test status
Simulation time 336533450000 ps
CPU time 977.11 seconds
Started Mar 28 12:40:15 PM PDT 24
Finished Mar 28 01:20:24 PM PDT 24
Peak memory 160704 kb
Host smart-be2ab24f-81fe-4b21-8477-557353960290
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3302967490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3302967490
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.54840772
Short name T110
Test name
Test status
Simulation time 337073410000 ps
CPU time 895.45 seconds
Started Mar 28 12:39:58 PM PDT 24
Finished Mar 28 01:16:43 PM PDT 24
Peak memory 160740 kb
Host smart-5ce6257a-738d-45e4-9729-559dbb4022ed
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=54840772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.54840772
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1566754695
Short name T15
Test name
Test status
Simulation time 336945150000 ps
CPU time 719.92 seconds
Started Mar 28 12:40:08 PM PDT 24
Finished Mar 28 01:10:03 PM PDT 24
Peak memory 160696 kb
Host smart-4d9bb2a2-59a9-4b2c-94c7-aa1152ff43b0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1566754695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1566754695
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1195934966
Short name T81
Test name
Test status
Simulation time 336812310000 ps
CPU time 952.55 seconds
Started Mar 28 12:40:03 PM PDT 24
Finished Mar 28 01:19:38 PM PDT 24
Peak memory 160664 kb
Host smart-0e9f3f79-ca02-4555-acce-ebb7d524ec63
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1195934966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1195934966
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2296374346
Short name T87
Test name
Test status
Simulation time 336616070000 ps
CPU time 986.64 seconds
Started Mar 28 12:40:08 PM PDT 24
Finished Mar 28 01:20:58 PM PDT 24
Peak memory 160696 kb
Host smart-d513516f-c9e8-493a-9a7b-a0c4c757d820
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2296374346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2296374346
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3924462108
Short name T98
Test name
Test status
Simulation time 336613170000 ps
CPU time 988.55 seconds
Started Mar 28 12:40:07 PM PDT 24
Finished Mar 28 01:20:58 PM PDT 24
Peak memory 160696 kb
Host smart-7c5234a1-f4d1-4b8f-996d-6c7ce515c7e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3924462108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3924462108
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2085822891
Short name T108
Test name
Test status
Simulation time 336648230000 ps
CPU time 895.46 seconds
Started Mar 28 12:40:02 PM PDT 24
Finished Mar 28 01:16:46 PM PDT 24
Peak memory 160728 kb
Host smart-8ce994ea-3e29-457f-8ba2-e6fe36de7e00
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2085822891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2085822891
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.181709052
Short name T72
Test name
Test status
Simulation time 336945070000 ps
CPU time 765.81 seconds
Started Mar 28 12:39:54 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 160704 kb
Host smart-e99b9cb2-bd76-4a7c-8bc7-86c1c25bf6e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=181709052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.181709052
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1469945669
Short name T103
Test name
Test status
Simulation time 336452830000 ps
CPU time 992.79 seconds
Started Mar 28 12:40:06 PM PDT 24
Finished Mar 28 01:20:57 PM PDT 24
Peak memory 160696 kb
Host smart-31c2c31d-143d-4c9d-95ec-75832cb9a42b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1469945669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1469945669
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1411519499
Short name T6
Test name
Test status
Simulation time 336631210000 ps
CPU time 749.08 seconds
Started Mar 28 12:39:36 PM PDT 24
Finished Mar 28 01:10:35 PM PDT 24
Peak memory 160680 kb
Host smart-0263574d-a7d7-4fa4-a822-ea1dfa454433
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1411519499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1411519499
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3016061136
Short name T85
Test name
Test status
Simulation time 336999490000 ps
CPU time 728.29 seconds
Started Mar 28 12:39:51 PM PDT 24
Finished Mar 28 01:09:59 PM PDT 24
Peak memory 160708 kb
Host smart-88731a88-d34c-4b6a-8056-3d07f7f83a97
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3016061136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3016061136
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3692377739
Short name T76
Test name
Test status
Simulation time 336492570000 ps
CPU time 716.95 seconds
Started Mar 28 12:40:09 PM PDT 24
Finished Mar 28 01:09:29 PM PDT 24
Peak memory 160688 kb
Host smart-428060ab-5b87-4f97-938f-c939ae04e0b4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3692377739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3692377739
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3688103679
Short name T92
Test name
Test status
Simulation time 336723930000 ps
CPU time 748.5 seconds
Started Mar 28 12:40:04 PM PDT 24
Finished Mar 28 01:09:46 PM PDT 24
Peak memory 160788 kb
Host smart-b9eb0f60-d244-444a-aa03-df2564a56e15
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3688103679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3688103679
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2657881594
Short name T101
Test name
Test status
Simulation time 337088370000 ps
CPU time 710.78 seconds
Started Mar 28 12:40:03 PM PDT 24
Finished Mar 28 01:09:15 PM PDT 24
Peak memory 160712 kb
Host smart-54e2ad99-a794-49a4-95b1-969b7e9fc771
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2657881594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2657881594
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3449476080
Short name T71
Test name
Test status
Simulation time 336306790000 ps
CPU time 907.41 seconds
Started Mar 28 12:40:12 PM PDT 24
Finished Mar 28 01:17:50 PM PDT 24
Peak memory 160700 kb
Host smart-73c6965f-4854-49ce-baf1-32b0c2c3f499
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3449476080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3449476080
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.29967012
Short name T17
Test name
Test status
Simulation time 337009850000 ps
CPU time 895.83 seconds
Started Mar 28 12:39:59 PM PDT 24
Finished Mar 28 01:16:42 PM PDT 24
Peak memory 160740 kb
Host smart-9d5e10ca-9e2e-4ca8-9531-899734f042ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=29967012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.29967012
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2379419412
Short name T20
Test name
Test status
Simulation time 336598930000 ps
CPU time 998.52 seconds
Started Mar 28 12:40:06 PM PDT 24
Finished Mar 28 01:20:56 PM PDT 24
Peak memory 160692 kb
Host smart-cfdfb869-6171-4482-8078-464502447dc2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2379419412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2379419412
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2935891306
Short name T99
Test name
Test status
Simulation time 336631770000 ps
CPU time 917.39 seconds
Started Mar 28 12:40:12 PM PDT 24
Finished Mar 28 01:18:20 PM PDT 24
Peak memory 160700 kb
Host smart-cab92f68-a753-46dd-b976-dcb5e570e745
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2935891306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2935891306
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3772653946
Short name T82
Test name
Test status
Simulation time 336376470000 ps
CPU time 882.8 seconds
Started Mar 28 12:40:04 PM PDT 24
Finished Mar 28 01:16:31 PM PDT 24
Peak memory 160716 kb
Host smart-16d7523b-460a-4187-a411-03a10d772c82
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3772653946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3772653946
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1940049310
Short name T16
Test name
Test status
Simulation time 336676190000 ps
CPU time 842.81 seconds
Started Mar 28 12:39:57 PM PDT 24
Finished Mar 28 01:14:20 PM PDT 24
Peak memory 160684 kb
Host smart-de645ede-7fac-4a0f-9ac9-828ba03203a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1940049310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1940049310
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3383871910
Short name T107
Test name
Test status
Simulation time 336581370000 ps
CPU time 770.65 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 160712 kb
Host smart-09265402-29ab-4735-82dd-f843afb6344e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3383871910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3383871910
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3031451403
Short name T89
Test name
Test status
Simulation time 336342350000 ps
CPU time 765.66 seconds
Started Mar 28 12:39:39 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 160712 kb
Host smart-351c7d22-e4fa-424e-8e3c-9129d3ba706c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3031451403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3031451403
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4068514716
Short name T18
Test name
Test status
Simulation time 336956510000 ps
CPU time 840.68 seconds
Started Mar 28 12:39:38 PM PDT 24
Finished Mar 28 01:14:13 PM PDT 24
Peak memory 160696 kb
Host smart-6a537ac1-f60b-4a37-8e57-8053cfb972a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4068514716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4068514716
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1058021530
Short name T96
Test name
Test status
Simulation time 336421210000 ps
CPU time 835.41 seconds
Started Mar 28 12:39:48 PM PDT 24
Finished Mar 28 01:14:10 PM PDT 24
Peak memory 160704 kb
Host smart-5eb0d4ef-139d-44ee-9837-e33ca9484634
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1058021530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1058021530
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3593087311
Short name T74
Test name
Test status
Simulation time 336976870000 ps
CPU time 632.06 seconds
Started Mar 28 12:39:40 PM PDT 24
Finished Mar 28 01:05:40 PM PDT 24
Peak memory 160708 kb
Host smart-8d726c7c-fd4e-423a-a12a-5f0866701834
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3593087311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3593087311
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2768359765
Short name T162
Test name
Test status
Simulation time 336508210000 ps
CPU time 791.87 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 01:07:20 PM PDT 24
Peak memory 160676 kb
Host smart-78717112-702a-441f-aa5f-db4d0871e6dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2768359765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2768359765
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3603238358
Short name T184
Test name
Test status
Simulation time 336620790000 ps
CPU time 975.93 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 01:16:24 PM PDT 24
Peak memory 160632 kb
Host smart-80f363d3-fa9c-4a3d-9a1c-95d9bdbb386d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3603238358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3603238358
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4045143016
Short name T23
Test name
Test status
Simulation time 336437270000 ps
CPU time 920.13 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 01:12:48 PM PDT 24
Peak memory 160688 kb
Host smart-08b462fe-4f74-42d4-aef8-2356fb3af6f0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4045143016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.4045143016
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.295779630
Short name T194
Test name
Test status
Simulation time 336819690000 ps
CPU time 772.13 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 01:05:50 PM PDT 24
Peak memory 160676 kb
Host smart-9662ebc4-bb9a-48a4-8b47-640268b104ad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=295779630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.295779630
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2819505987
Short name T185
Test name
Test status
Simulation time 336786350000 ps
CPU time 921.86 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 01:12:42 PM PDT 24
Peak memory 160692 kb
Host smart-4f34a013-d57e-42f0-9bcd-213d4b4f5f18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2819505987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2819505987
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.537860811
Short name T177
Test name
Test status
Simulation time 336789790000 ps
CPU time 949.72 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 01:13:21 PM PDT 24
Peak memory 160620 kb
Host smart-96a579c3-6142-4ae7-afba-a274a4147433
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=537860811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.537860811
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1201409250
Short name T186
Test name
Test status
Simulation time 336966990000 ps
CPU time 877.95 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 01:10:39 PM PDT 24
Peak memory 160688 kb
Host smart-de823347-4726-4ba0-8139-208b0bfa072e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1201409250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1201409250
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1288954412
Short name T183
Test name
Test status
Simulation time 337068690000 ps
CPU time 771.52 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 01:06:44 PM PDT 24
Peak memory 160752 kb
Host smart-68317964-c19a-4344-a321-c79265094742
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1288954412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1288954412
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.174202233
Short name T174
Test name
Test status
Simulation time 336801030000 ps
CPU time 885.35 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 160676 kb
Host smart-8230c2a1-086e-481e-b5cf-73f494623c97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=174202233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.174202233
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.872371650
Short name T176
Test name
Test status
Simulation time 336693210000 ps
CPU time 907.08 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 01:12:06 PM PDT 24
Peak memory 160684 kb
Host smart-a13bfa7c-b91a-43a5-b105-c82cc6749613
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=872371650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.872371650
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3692398058
Short name T200
Test name
Test status
Simulation time 336347490000 ps
CPU time 782.28 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 01:07:01 PM PDT 24
Peak memory 160632 kb
Host smart-ff979643-8278-4613-9226-be88293132ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3692398058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3692398058
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.480842269
Short name T30
Test name
Test status
Simulation time 336401350000 ps
CPU time 611.6 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 01:00:28 PM PDT 24
Peak memory 160708 kb
Host smart-774fd719-39fc-482b-8b1d-dff90658e881
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=480842269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.480842269
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3344274387
Short name T29
Test name
Test status
Simulation time 336698290000 ps
CPU time 871.26 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 01:11:47 PM PDT 24
Peak memory 160632 kb
Host smart-37664fa5-486d-4987-8df4-fde51d5c4881
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3344274387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3344274387
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4160973331
Short name T191
Test name
Test status
Simulation time 337165050000 ps
CPU time 950.78 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 01:14:21 PM PDT 24
Peak memory 160632 kb
Host smart-b6e0e0cf-46c6-4ee5-a637-8f5c80fe9b18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4160973331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4160973331
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3155165479
Short name T171
Test name
Test status
Simulation time 336329570000 ps
CPU time 706.23 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 01:03:46 PM PDT 24
Peak memory 160676 kb
Host smart-cbc3eee7-8c96-46bc-97c8-fb9ee704f8ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3155165479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3155165479
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3132281097
Short name T22
Test name
Test status
Simulation time 337004670000 ps
CPU time 941.55 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 01:13:06 PM PDT 24
Peak memory 160668 kb
Host smart-b349ec6a-f28c-4888-af90-388ccc07522a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3132281097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3132281097
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3274040027
Short name T173
Test name
Test status
Simulation time 336418730000 ps
CPU time 924.74 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 01:13:06 PM PDT 24
Peak memory 160632 kb
Host smart-3c892f52-ef2d-4d41-bfa1-cd0cc5df1af0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3274040027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3274040027
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2499151289
Short name T28
Test name
Test status
Simulation time 337049990000 ps
CPU time 935.96 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 01:13:30 PM PDT 24
Peak memory 160632 kb
Host smart-cb6f7b9a-f2f0-4f26-8c8c-67b7ff3ed1c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2499151289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2499151289
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.747222494
Short name T193
Test name
Test status
Simulation time 336396610000 ps
CPU time 949.2 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 01:13:17 PM PDT 24
Peak memory 160656 kb
Host smart-85e494f9-76fb-452a-8253-2e1da6d5f5d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=747222494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.747222494
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3720440920
Short name T189
Test name
Test status
Simulation time 336491630000 ps
CPU time 938.62 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 01:13:13 PM PDT 24
Peak memory 160668 kb
Host smart-a119dc08-2f3d-42fd-aac8-628ea770c6ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3720440920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3720440920
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.842694809
Short name T195
Test name
Test status
Simulation time 336743890000 ps
CPU time 814.15 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 01:09:06 PM PDT 24
Peak memory 160748 kb
Host smart-2da1d52f-1508-40cc-a8a0-2d0f4884a8bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=842694809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.842694809
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2340981080
Short name T175
Test name
Test status
Simulation time 336984430000 ps
CPU time 940.93 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 01:13:14 PM PDT 24
Peak memory 160668 kb
Host smart-ed56864f-ae10-490e-9a1f-25bedd59551f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2340981080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2340981080
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3754251727
Short name T165
Test name
Test status
Simulation time 337136610000 ps
CPU time 868.9 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 01:10:59 PM PDT 24
Peak memory 160708 kb
Host smart-c96d62d3-427b-44ae-9796-48f850039222
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3754251727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3754251727
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1287390849
Short name T25
Test name
Test status
Simulation time 336937370000 ps
CPU time 942.04 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 01:13:15 PM PDT 24
Peak memory 160668 kb
Host smart-cf836b74-3a14-45f5-89fe-601fce7a6701
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1287390849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1287390849
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.687589275
Short name T170
Test name
Test status
Simulation time 337058610000 ps
CPU time 773.4 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 01:07:02 PM PDT 24
Peak memory 160728 kb
Host smart-595b8e35-1d12-4d35-95b9-3ec0ab9fb37d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=687589275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.687589275
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2804808040
Short name T26
Test name
Test status
Simulation time 336833810000 ps
CPU time 905.73 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 160668 kb
Host smart-e924da7c-e9f6-4542-8298-69635f990a2e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2804808040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2804808040
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3689926056
Short name T181
Test name
Test status
Simulation time 336741470000 ps
CPU time 980.97 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 01:14:42 PM PDT 24
Peak memory 160648 kb
Host smart-e1979ef1-2594-40a0-b7a0-77fcce2e3e03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3689926056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3689926056
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1896953068
Short name T166
Test name
Test status
Simulation time 336825230000 ps
CPU time 972.62 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 01:15:08 PM PDT 24
Peak memory 160644 kb
Host smart-5fe966ed-0fce-4a0f-801a-41d6a0575146
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1896953068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1896953068
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3006066834
Short name T24
Test name
Test status
Simulation time 336935210000 ps
CPU time 961.35 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 01:14:26 PM PDT 24
Peak memory 160648 kb
Host smart-56df3549-603f-4814-a49e-dfa1fae61994
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3006066834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3006066834
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4108637903
Short name T163
Test name
Test status
Simulation time 336697990000 ps
CPU time 935.15 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 01:12:58 PM PDT 24
Peak memory 160668 kb
Host smart-f4de0d05-7bc3-4bdd-900a-848241d7bdb0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4108637903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.4108637903
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3843438408
Short name T199
Test name
Test status
Simulation time 336534930000 ps
CPU time 759.86 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 01:06:18 PM PDT 24
Peak memory 160692 kb
Host smart-f8f9cb0b-0169-434a-b018-3995d38cc72c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3843438408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3843438408
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3415011680
Short name T167
Test name
Test status
Simulation time 336909370000 ps
CPU time 918.82 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 01:12:48 PM PDT 24
Peak memory 160648 kb
Host smart-0c09fb5d-6c8f-46d7-bcf9-aa62cc749442
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3415011680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3415011680
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.245065955
Short name T172
Test name
Test status
Simulation time 336856270000 ps
CPU time 952.19 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 01:13:32 PM PDT 24
Peak memory 160656 kb
Host smart-53e3e494-f9a6-4c06-9efa-9ea105b6fc6e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=245065955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.245065955
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3120344570
Short name T197
Test name
Test status
Simulation time 336759490000 ps
CPU time 981.5 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 01:16:34 PM PDT 24
Peak memory 160632 kb
Host smart-42696b21-9d4d-4e8f-b153-ff211f5c0a65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3120344570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3120344570
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1593320478
Short name T180
Test name
Test status
Simulation time 336918770000 ps
CPU time 866.57 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 01:12:04 PM PDT 24
Peak memory 160648 kb
Host smart-a12785c9-90de-412c-8e10-67ce33e87909
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1593320478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1593320478
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.877643569
Short name T196
Test name
Test status
Simulation time 336529090000 ps
CPU time 879.29 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 01:11:57 PM PDT 24
Peak memory 160644 kb
Host smart-652da369-f9fc-4b19-a284-d6b9fef2f9ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=877643569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.877643569
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3074744033
Short name T178
Test name
Test status
Simulation time 336952370000 ps
CPU time 975.06 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 01:15:16 PM PDT 24
Peak memory 160648 kb
Host smart-58b05f7f-55ad-482f-a43d-7ea5806a9839
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3074744033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3074744033
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3545357281
Short name T182
Test name
Test status
Simulation time 336792910000 ps
CPU time 951.43 seconds
Started Mar 28 12:34:47 PM PDT 24
Finished Mar 28 01:13:53 PM PDT 24
Peak memory 160648 kb
Host smart-55f487c6-ef65-478b-bc81-cdfbb8f81077
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3545357281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3545357281
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.289429093
Short name T169
Test name
Test status
Simulation time 336607930000 ps
CPU time 942.06 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 01:14:40 PM PDT 24
Peak memory 160644 kb
Host smart-61953ae4-41bf-4022-b35d-d98c7ade9c49
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=289429093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.289429093
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3832145658
Short name T164
Test name
Test status
Simulation time 336926450000 ps
CPU time 944.04 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 01:13:22 PM PDT 24
Peak memory 160668 kb
Host smart-95f50f18-4cc5-45b4-b824-fd96e3ba3e58
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3832145658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3832145658
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2237762611
Short name T187
Test name
Test status
Simulation time 336340090000 ps
CPU time 946.47 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 01:14:16 PM PDT 24
Peak memory 160648 kb
Host smart-2340ae4d-2663-4ebb-bb98-2e1c174ed148
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2237762611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2237762611
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3723698623
Short name T188
Test name
Test status
Simulation time 336377270000 ps
CPU time 895.9 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 01:11:18 PM PDT 24
Peak memory 160668 kb
Host smart-ec8f0d0c-5bcc-450a-8110-2cc7a4f4a93d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3723698623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3723698623
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3722027065
Short name T192
Test name
Test status
Simulation time 336497210000 ps
CPU time 929.6 seconds
Started Mar 28 12:34:49 PM PDT 24
Finished Mar 28 01:13:26 PM PDT 24
Peak memory 160636 kb
Host smart-d7344f36-0dee-449b-9958-ad09f5241494
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3722027065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3722027065
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1600618941
Short name T168
Test name
Test status
Simulation time 336998750000 ps
CPU time 966.91 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 01:15:36 PM PDT 24
Peak memory 160624 kb
Host smart-2b3ef2df-c8c8-48de-803a-28f132abb814
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1600618941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1600618941
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1647256076
Short name T161
Test name
Test status
Simulation time 336321950000 ps
CPU time 681.52 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 01:03:38 PM PDT 24
Peak memory 160676 kb
Host smart-d1acbf69-0a8e-49a6-879c-2f4dc1d723b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1647256076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1647256076
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1756092851
Short name T179
Test name
Test status
Simulation time 336824450000 ps
CPU time 831.83 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 01:09:13 PM PDT 24
Peak memory 160676 kb
Host smart-060d1c2d-01c4-413d-8517-0dac321f16b5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1756092851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1756092851
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1622435941
Short name T198
Test name
Test status
Simulation time 336538230000 ps
CPU time 982.85 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 01:16:32 PM PDT 24
Peak memory 160632 kb
Host smart-9f0bc8a8-2d89-4543-9ab5-eea3fdb29357
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1622435941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1622435941
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1060107462
Short name T190
Test name
Test status
Simulation time 337011210000 ps
CPU time 744.66 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 01:05:46 PM PDT 24
Peak memory 160676 kb
Host smart-3d182867-5cc7-43e0-92e3-50349d312220
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1060107462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1060107462
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3813569488
Short name T21
Test name
Test status
Simulation time 336540890000 ps
CPU time 597.94 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:59:49 PM PDT 24
Peak memory 160664 kb
Host smart-0ca946d5-cc70-4f1b-b20a-a637b9ba2b8d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813569488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3813569488
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1825909657
Short name T116
Test name
Test status
Simulation time 1460190000 ps
CPU time 4.3 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 164772 kb
Host smart-b1038a31-4ca8-49b8-b621-e73b858291cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1825909657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1825909657
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.216356268
Short name T133
Test name
Test status
Simulation time 1555290000 ps
CPU time 5.04 seconds
Started Mar 28 12:34:49 PM PDT 24
Finished Mar 28 12:35:01 PM PDT 24
Peak memory 164768 kb
Host smart-ab9a4475-934f-48da-843d-ca6cf01d7165
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=216356268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.216356268
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.517658771
Short name T112
Test name
Test status
Simulation time 1521030000 ps
CPU time 3.36 seconds
Started Mar 28 12:34:42 PM PDT 24
Finished Mar 28 12:34:50 PM PDT 24
Peak memory 164792 kb
Host smart-b241caa5-c234-4a41-bc3b-5758c05a1f66
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=517658771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.517658771
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4031364736
Short name T117
Test name
Test status
Simulation time 1507770000 ps
CPU time 5.74 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 164732 kb
Host smart-2607d35b-13df-4364-af36-5544693352d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4031364736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4031364736
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1908525294
Short name T147
Test name
Test status
Simulation time 1520730000 ps
CPU time 5.57 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 164796 kb
Host smart-fe0ca757-469b-4345-91cc-386419cb6ae0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1908525294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1908525294
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1177977660
Short name T136
Test name
Test status
Simulation time 1403490000 ps
CPU time 3.62 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 164816 kb
Host smart-65b7ec5e-8429-4406-80b2-2262f9684541
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177977660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1177977660
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4259042394
Short name T139
Test name
Test status
Simulation time 1428510000 ps
CPU time 3.23 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 164764 kb
Host smart-a7438434-6662-47e4-a5c2-efb9a3d2fb51
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4259042394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4259042394
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2385599128
Short name T158
Test name
Test status
Simulation time 1377310000 ps
CPU time 4.02 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:35:01 PM PDT 24
Peak memory 164824 kb
Host smart-f5dbaf59-6920-4692-8556-b6b120bc6ebb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385599128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2385599128
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3371919013
Short name T148
Test name
Test status
Simulation time 1330690000 ps
CPU time 2.78 seconds
Started Mar 28 12:34:45 PM PDT 24
Finished Mar 28 12:34:52 PM PDT 24
Peak memory 164760 kb
Host smart-e7d90df2-cb8b-4ec2-bc50-9b9d35665b74
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371919013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3371919013
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2328088039
Short name T149
Test name
Test status
Simulation time 1572290000 ps
CPU time 3.28 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:34:58 PM PDT 24
Peak memory 164956 kb
Host smart-d5ba5756-7c04-442d-b052-3fad5e837cac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328088039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2328088039
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.631393583
Short name T114
Test name
Test status
Simulation time 1334770000 ps
CPU time 2.73 seconds
Started Mar 28 12:34:44 PM PDT 24
Finished Mar 28 12:34:51 PM PDT 24
Peak memory 165024 kb
Host smart-7cede0c7-4232-45b9-b107-33fe79bc4829
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=631393583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.631393583
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2840697179
Short name T119
Test name
Test status
Simulation time 1370910000 ps
CPU time 4.59 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 164800 kb
Host smart-9bc42453-8460-4efa-ba0d-36e1305fe6bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2840697179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2840697179
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2180019083
Short name T126
Test name
Test status
Simulation time 1588610000 ps
CPU time 3.05 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 164856 kb
Host smart-08f157ec-14d5-42fb-abbe-fffaad125129
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2180019083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2180019083
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3078128376
Short name T137
Test name
Test status
Simulation time 1563730000 ps
CPU time 5.78 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 12:35:16 PM PDT 24
Peak memory 164780 kb
Host smart-2c6e4cf6-e461-4539-a4d2-323c4e2a271d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078128376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3078128376
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.298666401
Short name T140
Test name
Test status
Simulation time 1349770000 ps
CPU time 4.17 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 164764 kb
Host smart-7f1a8fc3-f109-45b5-b5ae-8ca331fc3b01
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=298666401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.298666401
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1504357470
Short name T142
Test name
Test status
Simulation time 1212550000 ps
CPU time 2.62 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:09 PM PDT 24
Peak memory 164956 kb
Host smart-f7a3c389-aad6-40df-b0da-976e4bc7c91a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504357470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1504357470
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2519242718
Short name T120
Test name
Test status
Simulation time 1528950000 ps
CPU time 3.52 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:19 PM PDT 24
Peak memory 164780 kb
Host smart-7014da5f-e4ca-4796-af5f-76544ff18136
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2519242718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2519242718
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3280609817
Short name T141
Test name
Test status
Simulation time 1412310000 ps
CPU time 5.33 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 164748 kb
Host smart-476587d3-acd1-46a5-b541-b110f8343d61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280609817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3280609817
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2245811939
Short name T155
Test name
Test status
Simulation time 1361650000 ps
CPU time 4.07 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 12:35:01 PM PDT 24
Peak memory 164724 kb
Host smart-9b9f76e7-9805-4f45-a0f8-3f4af2a560fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2245811939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2245811939
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2694314679
Short name T160
Test name
Test status
Simulation time 1526190000 ps
CPU time 5.72 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:35:04 PM PDT 24
Peak memory 164796 kb
Host smart-dcf14606-bb1e-4b4f-986f-ea8301ba9be9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2694314679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2694314679
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.627605333
Short name T124
Test name
Test status
Simulation time 1092730000 ps
CPU time 3.19 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 12:34:59 PM PDT 24
Peak memory 164720 kb
Host smart-967acd49-a2fa-4df4-bc25-5683816d0344
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=627605333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.627605333
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3134726562
Short name T130
Test name
Test status
Simulation time 1559110000 ps
CPU time 5.19 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 12:35:16 PM PDT 24
Peak memory 164772 kb
Host smart-c3adc2ac-97e7-41b6-9937-2a5a6ceeb080
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3134726562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3134726562
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2562630576
Short name T118
Test name
Test status
Simulation time 1397630000 ps
CPU time 4.12 seconds
Started Mar 28 12:34:49 PM PDT 24
Finished Mar 28 12:34:58 PM PDT 24
Peak memory 164796 kb
Host smart-6e75a7c2-2ad2-4963-95ec-e4338d720d80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2562630576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2562630576
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2986971223
Short name T125
Test name
Test status
Simulation time 1533430000 ps
CPU time 4.9 seconds
Started Mar 28 12:34:48 PM PDT 24
Finished Mar 28 12:34:59 PM PDT 24
Peak memory 164740 kb
Host smart-e692a2d2-ea8c-4fca-a658-235714323262
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2986971223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2986971223
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3393265018
Short name T156
Test name
Test status
Simulation time 1341650000 ps
CPU time 3.83 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 164812 kb
Host smart-615494a3-4fd4-4466-8e89-47c148d14977
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3393265018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3393265018
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.206204597
Short name T153
Test name
Test status
Simulation time 1498690000 ps
CPU time 4.7 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:35:02 PM PDT 24
Peak memory 164768 kb
Host smart-2ac0107d-c979-4753-a800-a059fa7711e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=206204597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.206204597
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2664187343
Short name T132
Test name
Test status
Simulation time 1541230000 ps
CPU time 4.25 seconds
Started Mar 28 12:34:41 PM PDT 24
Finished Mar 28 12:34:51 PM PDT 24
Peak memory 164796 kb
Host smart-9e52ce27-a242-4fec-a688-859faa154344
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2664187343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2664187343
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2589868834
Short name T111
Test name
Test status
Simulation time 1340750000 ps
CPU time 4.4 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:03 PM PDT 24
Peak memory 164772 kb
Host smart-7faa68be-24f8-44fa-86a7-77ad7ea6b640
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2589868834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2589868834
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.222311325
Short name T127
Test name
Test status
Simulation time 1474390000 ps
CPU time 4.31 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 164760 kb
Host smart-b3b12600-5b27-455f-a0da-55298df841ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=222311325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.222311325
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1611870464
Short name T143
Test name
Test status
Simulation time 1363490000 ps
CPU time 3.18 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:01 PM PDT 24
Peak memory 164832 kb
Host smart-92b0bd70-8c2d-4627-9752-843cbd1834b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1611870464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1611870464
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1363385204
Short name T123
Test name
Test status
Simulation time 1415350000 ps
CPU time 3.36 seconds
Started Mar 28 12:35:12 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 164780 kb
Host smart-45699670-c0a0-46fc-9749-6763f30b6ba8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1363385204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1363385204
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2857196634
Short name T121
Test name
Test status
Simulation time 1484710000 ps
CPU time 3.94 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 12:35:07 PM PDT 24
Peak memory 164764 kb
Host smart-bc55dcb9-48b9-4e28-b832-be40019ea1d5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2857196634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2857196634
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.288974250
Short name T131
Test name
Test status
Simulation time 1454570000 ps
CPU time 3.15 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:34:59 PM PDT 24
Peak memory 165024 kb
Host smart-7bb012b8-4c52-446c-8f3d-ba53184c3dea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288974250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.288974250
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.846759265
Short name T138
Test name
Test status
Simulation time 1445890000 ps
CPU time 5.24 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 12:35:09 PM PDT 24
Peak memory 164744 kb
Host smart-fbaca8e3-e654-41b6-ac45-a1de15926814
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=846759265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.846759265
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2870085922
Short name T154
Test name
Test status
Simulation time 1519350000 ps
CPU time 3.28 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 164764 kb
Host smart-ce2bbd07-2228-4af9-aa1a-b7973ee2e660
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2870085922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2870085922
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3788816539
Short name T135
Test name
Test status
Simulation time 1628710000 ps
CPU time 5.28 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 164756 kb
Host smart-34eef93b-9dab-4989-9361-c80ebf3da01b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788816539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3788816539
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1159007194
Short name T129
Test name
Test status
Simulation time 1496650000 ps
CPU time 5.15 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 12:35:09 PM PDT 24
Peak memory 164800 kb
Host smart-05fd1f01-a6b8-4300-a9f4-f5a5d8a6a7e8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159007194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1159007194
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4059733528
Short name T145
Test name
Test status
Simulation time 1422450000 ps
CPU time 3.34 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 164756 kb
Host smart-33acb56a-7188-48ba-a820-924b33991389
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4059733528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.4059733528
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1968013152
Short name T157
Test name
Test status
Simulation time 1563690000 ps
CPU time 5.01 seconds
Started Mar 28 12:35:12 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 164772 kb
Host smart-5917edf7-a159-4f61-91e4-ab53a14127ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968013152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1968013152
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3352576188
Short name T115
Test name
Test status
Simulation time 1380610000 ps
CPU time 4.88 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 164800 kb
Host smart-ff01f520-202b-4368-9d91-16cf473d4cfe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3352576188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3352576188
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3175276270
Short name T150
Test name
Test status
Simulation time 1342790000 ps
CPU time 3.92 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:03 PM PDT 24
Peak memory 164888 kb
Host smart-ddad32ef-a78e-4825-ad4e-4cfc574d5255
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3175276270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3175276270
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.398220428
Short name T146
Test name
Test status
Simulation time 1028390000 ps
CPU time 3.3 seconds
Started Mar 28 12:34:56 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 164832 kb
Host smart-36fb7f4e-2a0e-48b8-8fd3-c83cf0e8612f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398220428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.398220428
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3277100590
Short name T152
Test name
Test status
Simulation time 1476690000 ps
CPU time 4.29 seconds
Started Mar 28 12:34:52 PM PDT 24
Finished Mar 28 12:35:02 PM PDT 24
Peak memory 164888 kb
Host smart-d51e9780-79ad-4b70-ac42-03cbca82bad0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3277100590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3277100590
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2267094705
Short name T122
Test name
Test status
Simulation time 1266590000 ps
CPU time 4.06 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 12:35:04 PM PDT 24
Peak memory 164888 kb
Host smart-3a8c3c80-99ba-4b7b-95c0-393bd5b94e8b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2267094705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2267094705
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4290257468
Short name T144
Test name
Test status
Simulation time 1189810000 ps
CPU time 4.77 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:19 PM PDT 24
Peak memory 164748 kb
Host smart-2c36849f-444a-4c6c-8083-7bb0e6d96758
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290257468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4290257468
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4246482959
Short name T113
Test name
Test status
Simulation time 1473050000 ps
CPU time 4.42 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:35:02 PM PDT 24
Peak memory 164720 kb
Host smart-2df50b3e-e2e0-4022-b123-a9da506ce017
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4246482959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.4246482959
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1532360495
Short name T151
Test name
Test status
Simulation time 1592870000 ps
CPU time 5.32 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 164740 kb
Host smart-0c705758-07fa-4d35-b29e-ef4c1af0fdab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532360495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1532360495
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.717118218
Short name T128
Test name
Test status
Simulation time 1493350000 ps
CPU time 3.06 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 12:35:02 PM PDT 24
Peak memory 164784 kb
Host smart-261b1441-f72a-4084-8c5e-c01ca9b5811e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=717118218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.717118218
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.714728788
Short name T134
Test name
Test status
Simulation time 1529250000 ps
CPU time 4.87 seconds
Started Mar 28 12:34:51 PM PDT 24
Finished Mar 28 12:35:02 PM PDT 24
Peak memory 164720 kb
Host smart-502e26eb-1d22-4cec-8951-c8921043a635
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=714728788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.714728788
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1177105463
Short name T159
Test name
Test status
Simulation time 1310970000 ps
CPU time 2.85 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 164776 kb
Host smart-861c97d3-f4ac-4843-9891-3772329969a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177105463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1177105463
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2750687618
Short name T32
Test name
Test status
Simulation time 1306850000 ps
CPU time 3.54 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:32 PM PDT 24
Peak memory 164888 kb
Host smart-cdfcbf12-26a2-4447-83a1-277c7d705c01
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2750687618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2750687618
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3507120579
Short name T68
Test name
Test status
Simulation time 1488750000 ps
CPU time 4.9 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164908 kb
Host smart-21e35fa8-ad46-4a1d-ae59-04e72a15f6c0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3507120579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3507120579
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.347126889
Short name T37
Test name
Test status
Simulation time 1282190000 ps
CPU time 4.31 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164896 kb
Host smart-aaa4a41d-146e-4461-a422-d66540ef4f8f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347126889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.347126889
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2825203687
Short name T63
Test name
Test status
Simulation time 1512130000 ps
CPU time 5.85 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:38 PM PDT 24
Peak memory 164832 kb
Host smart-c8095041-ef91-4cdb-a746-13b2824e28dc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2825203687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2825203687
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1922395846
Short name T60
Test name
Test status
Simulation time 1268050000 ps
CPU time 4.94 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164832 kb
Host smart-da5580c6-da34-47b9-a410-08bb0dee3fa4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1922395846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1922395846
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2072621148
Short name T35
Test name
Test status
Simulation time 1419890000 ps
CPU time 5.84 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:39 PM PDT 24
Peak memory 164896 kb
Host smart-1692f842-a0ff-498c-afb6-d614c0b09eea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072621148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2072621148
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.818396232
Short name T48
Test name
Test status
Simulation time 1323210000 ps
CPU time 2.81 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:33 PM PDT 24
Peak memory 164812 kb
Host smart-6b99dcdd-fda7-49b0-b104-27ca5149c664
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=818396232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.818396232
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.85096550
Short name T1
Test name
Test status
Simulation time 1554330000 ps
CPU time 3.2 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:33 PM PDT 24
Peak memory 164868 kb
Host smart-1f167bd7-98f6-49c0-b3c8-0e01c8171683
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=85096550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.85096550
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4245907112
Short name T2
Test name
Test status
Simulation time 1551870000 ps
CPU time 3.42 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:33 PM PDT 24
Peak memory 164880 kb
Host smart-c91125a4-43ba-4a9a-8d13-ecd56208f107
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4245907112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.4245907112
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3476288053
Short name T40
Test name
Test status
Simulation time 1605570000 ps
CPU time 3.37 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164876 kb
Host smart-c8d75ab9-5f1c-457e-837c-4c60c7d2cfb2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3476288053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3476288053
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3757378798
Short name T31
Test name
Test status
Simulation time 1459510000 ps
CPU time 5.86 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164928 kb
Host smart-b693211f-2463-443f-abed-3b8caecba064
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3757378798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3757378798
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1477459803
Short name T53
Test name
Test status
Simulation time 1453910000 ps
CPU time 5.37 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164816 kb
Host smart-ed00c8c7-9c27-4ca8-b1e2-751b2e97682a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1477459803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1477459803
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2588472136
Short name T43
Test name
Test status
Simulation time 1436990000 ps
CPU time 4.5 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164928 kb
Host smart-cfbaf46c-9332-4532-9cf8-914daceabd40
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2588472136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2588472136
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2099422568
Short name T62
Test name
Test status
Simulation time 1455830000 ps
CPU time 4.52 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:37 PM PDT 24
Peak memory 164928 kb
Host smart-56dc8fde-9a1a-43fc-97f6-90e967a30f92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2099422568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2099422568
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2389057040
Short name T54
Test name
Test status
Simulation time 1308770000 ps
CPU time 2.75 seconds
Started Mar 28 12:43:29 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164908 kb
Host smart-02efb3d9-f943-4009-b792-7f61a7ab54d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2389057040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2389057040
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2366885581
Short name T44
Test name
Test status
Simulation time 1451150000 ps
CPU time 4.26 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164928 kb
Host smart-136222d1-e198-4edf-bde5-7a4b2f4b9e21
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2366885581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2366885581
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.119319748
Short name T47
Test name
Test status
Simulation time 1477670000 ps
CPU time 2.9 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:29 PM PDT 24
Peak memory 164876 kb
Host smart-6527813f-9ecd-437c-bc69-6751edbfbafd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=119319748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.119319748
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.388576988
Short name T7
Test name
Test status
Simulation time 1479850000 ps
CPU time 5.39 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164808 kb
Host smart-536a86ff-3f00-4761-8c29-7f2ef12c51dd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388576988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.388576988
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3075162
Short name T70
Test name
Test status
Simulation time 1360010000 ps
CPU time 4.65 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164952 kb
Host smart-f994e236-e6bd-4164-a51c-f3ccdcad7ca9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3075162
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2271044838
Short name T38
Test name
Test status
Simulation time 1542370000 ps
CPU time 4.98 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:34 PM PDT 24
Peak memory 164948 kb
Host smart-93e7b9bb-7bcb-4b64-a1d7-364a85339f30
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271044838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2271044838
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2030140937
Short name T3
Test name
Test status
Simulation time 1491710000 ps
CPU time 4.46 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:34 PM PDT 24
Peak memory 164948 kb
Host smart-fac88ac5-fa8a-4ca3-80d1-f78d351d7f39
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2030140937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2030140937
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3742575799
Short name T8
Test name
Test status
Simulation time 1387810000 ps
CPU time 5.69 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:39 PM PDT 24
Peak memory 164896 kb
Host smart-940e26e2-ea25-4a97-9455-b6aa30f1b6d1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742575799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3742575799
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1182630893
Short name T41
Test name
Test status
Simulation time 1539370000 ps
CPU time 5.03 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164892 kb
Host smart-9e3ab098-8852-40df-9ae9-577fe482ea5b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1182630893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1182630893
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.159265802
Short name T55
Test name
Test status
Simulation time 1486210000 ps
CPU time 5.68 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:37 PM PDT 24
Peak memory 164808 kb
Host smart-eab9b9a8-7489-4d6f-8a25-9ea49e60922f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=159265802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.159265802
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.4108209504
Short name T11
Test name
Test status
Simulation time 1455230000 ps
CPU time 4.84 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164948 kb
Host smart-901e896d-f0fb-40a1-9ca2-f32762254f2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108209504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.4108209504
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4047231418
Short name T45
Test name
Test status
Simulation time 1461390000 ps
CPU time 4.83 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164952 kb
Host smart-ef27bf4f-14b1-4c9f-9a0b-5fdc4b0c0ac9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4047231418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4047231418
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.459621421
Short name T51
Test name
Test status
Simulation time 1408390000 ps
CPU time 5.12 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 164808 kb
Host smart-ccb0dbb0-c561-42f1-8d41-6c01807b2ab6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459621421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.459621421
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3016020215
Short name T56
Test name
Test status
Simulation time 1427370000 ps
CPU time 4.63 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 164952 kb
Host smart-48fc9e1c-471a-4830-8128-d40f65333dce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3016020215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3016020215
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3534335367
Short name T64
Test name
Test status
Simulation time 1377630000 ps
CPU time 4.96 seconds
Started Mar 28 12:43:49 PM PDT 24
Finished Mar 28 12:44:00 PM PDT 24
Peak memory 164908 kb
Host smart-8cdf950c-b548-44f4-96e2-7a1e4e7932af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3534335367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3534335367
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1911561441
Short name T57
Test name
Test status
Simulation time 1296510000 ps
CPU time 3.99 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 164884 kb
Host smart-43d8b0a9-9982-405f-9a9c-495f6b8e8656
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1911561441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1911561441
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1200834475
Short name T36
Test name
Test status
Simulation time 1503170000 ps
CPU time 4.83 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:04 PM PDT 24
Peak memory 164928 kb
Host smart-7a851240-eb76-470d-a3bc-e19fd27eda05
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200834475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1200834475
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.495605685
Short name T69
Test name
Test status
Simulation time 1390890000 ps
CPU time 5.17 seconds
Started Mar 28 12:43:57 PM PDT 24
Finished Mar 28 12:44:08 PM PDT 24
Peak memory 164800 kb
Host smart-39a1851e-8ff9-43f1-813e-54c9ca792101
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=495605685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.495605685
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2687628089
Short name T52
Test name
Test status
Simulation time 1304610000 ps
CPU time 4.22 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:05 PM PDT 24
Peak memory 164908 kb
Host smart-7ea3cc00-cf26-4685-abea-7f1ec029532c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2687628089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2687628089
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3620271942
Short name T39
Test name
Test status
Simulation time 1538490000 ps
CPU time 5.09 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164872 kb
Host smart-d1f14318-323b-4621-8d5b-4910f1c44349
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620271942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3620271942
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.724091216
Short name T59
Test name
Test status
Simulation time 1361510000 ps
CPU time 3.8 seconds
Started Mar 28 12:43:54 PM PDT 24
Finished Mar 28 12:44:02 PM PDT 24
Peak memory 164900 kb
Host smart-513983eb-0af0-4714-89b1-1097fa138c4a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=724091216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.724091216
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2272193628
Short name T10
Test name
Test status
Simulation time 1461750000 ps
CPU time 4.72 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:06 PM PDT 24
Peak memory 164864 kb
Host smart-1226236f-3794-4a13-985a-e052e42ac28e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2272193628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2272193628
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2728551346
Short name T49
Test name
Test status
Simulation time 1383230000 ps
CPU time 5.06 seconds
Started Mar 28 12:43:52 PM PDT 24
Finished Mar 28 12:44:04 PM PDT 24
Peak memory 164928 kb
Host smart-32b51766-412a-41a7-8f4d-edb7d634fa9c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2728551346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2728551346
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.26233891
Short name T46
Test name
Test status
Simulation time 1096490000 ps
CPU time 4.21 seconds
Started Mar 28 12:43:52 PM PDT 24
Finished Mar 28 12:44:02 PM PDT 24
Peak memory 164872 kb
Host smart-946e752e-d592-4518-bc33-0b22f27c55cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=26233891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.26233891
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2525096350
Short name T66
Test name
Test status
Simulation time 1407830000 ps
CPU time 4.36 seconds
Started Mar 28 12:43:50 PM PDT 24
Finished Mar 28 12:44:00 PM PDT 24
Peak memory 164948 kb
Host smart-d6660e36-95bc-46bb-aa26-77556df57a35
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525096350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2525096350
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.7467134
Short name T65
Test name
Test status
Simulation time 1504710000 ps
CPU time 4.54 seconds
Started Mar 28 12:43:55 PM PDT 24
Finished Mar 28 12:44:05 PM PDT 24
Peak memory 164892 kb
Host smart-eae92c20-1215-4d08-8ca0-c3a74bf54b98
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=7467134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.7467134
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2631321953
Short name T12
Test name
Test status
Simulation time 1340250000 ps
CPU time 3.26 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:08 PM PDT 24
Peak memory 164876 kb
Host smart-4ff47849-188c-43d4-bb41-06aef538866e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631321953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2631321953
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4253044018
Short name T33
Test name
Test status
Simulation time 1588910000 ps
CPU time 3.83 seconds
Started Mar 28 12:44:01 PM PDT 24
Finished Mar 28 12:44:10 PM PDT 24
Peak memory 164876 kb
Host smart-69a8906d-f714-4ef1-847c-ee71fcc42d12
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253044018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4253044018
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3102124826
Short name T61
Test name
Test status
Simulation time 1440650000 ps
CPU time 5.32 seconds
Started Mar 28 12:43:49 PM PDT 24
Finished Mar 28 12:44:01 PM PDT 24
Peak memory 164856 kb
Host smart-833ab556-c29f-4b95-b9c8-171de4b552fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3102124826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3102124826
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1262071705
Short name T58
Test name
Test status
Simulation time 1511450000 ps
CPU time 7.19 seconds
Started Mar 28 12:43:56 PM PDT 24
Finished Mar 28 12:44:10 PM PDT 24
Peak memory 164904 kb
Host smart-e52b91fe-e766-4862-a858-badf4ca9078e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1262071705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1262071705
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1813562485
Short name T50
Test name
Test status
Simulation time 1494630000 ps
CPU time 4.97 seconds
Started Mar 28 12:43:28 PM PDT 24
Finished Mar 28 12:43:40 PM PDT 24
Peak memory 164808 kb
Host smart-bd2b99a3-4075-4b8f-9e1d-ef748ee88be0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1813562485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1813562485
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.165275362
Short name T34
Test name
Test status
Simulation time 1155870000 ps
CPU time 3.2 seconds
Started Mar 28 12:43:28 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164876 kb
Host smart-2eb39701-6b1c-4314-944b-6fdf8c0ce3cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=165275362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.165275362
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1666035940
Short name T9
Test name
Test status
Simulation time 1395110000 ps
CPU time 3.98 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:35 PM PDT 24
Peak memory 164836 kb
Host smart-7182a35b-7caa-4019-9bb6-7ee4027a2075
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1666035940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1666035940
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3514694483
Short name T42
Test name
Test status
Simulation time 1480570000 ps
CPU time 3.35 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:33 PM PDT 24
Peak memory 164888 kb
Host smart-4afc93a7-bb2a-427d-bacb-a3b26cbc36f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514694483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3514694483
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1155503794
Short name T67
Test name
Test status
Simulation time 1553050000 ps
CPU time 5.04 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:36 PM PDT 24
Peak memory 164908 kb
Host smart-2ab62763-aad1-40e9-89fa-9ae5abfc55d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1155503794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1155503794
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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