Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3086214408
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3773407574
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4157820259

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3007887258
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2473471137
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2146049921
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3155764413
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.680035065
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4051250337
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2963740005
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3309350308
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1493163549
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.38004348
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.4104101825
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3993355167
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2614526296
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2344065023
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3559940421
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3310487844
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3374497094
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1236828658
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2225894737
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4016911575
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2368741427
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2811595577
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1974482020
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3066503838
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1005562298
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3007668797
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1247628357
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.292814931
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2286764797
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1242435446
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3296699019
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3465957757
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1790466868
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2659273886
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.145530943
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.791701290
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1529110327
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.953100050
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2936816084
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.505307287
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2775193521
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2804387110
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2392700255
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4066426310
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1986706612
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2989867040
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1748403563
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2928711999
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2822661410
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.855143974
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1217954353
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.689766345
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2427361449
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3520457628
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2709605636
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.687349331
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.784030212
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3731180478
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.599243282
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1141849914
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2861876056
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.251328254
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.175553275
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1299245315
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1536301395
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1154817577
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2699274358
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1009781033
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2466450737
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3731677914
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2319257460
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3986526008
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.445595885
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2922030797
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2333546665
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4077358445
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4184237384
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2631330065
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3303243436
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4254161703
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3928865507
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4191881765
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1898372362
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3359140
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2066961868
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1430391058
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1072956386
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.721805328
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1036014937
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1250348899
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1657325657
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3901099623
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2843571888
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1261990227
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2806557784
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.142177557
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3211313918
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.140548616
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2814598363
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2825708544
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4279822215
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.867201742
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1110946366
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2340788847
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2178424260
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3909163054
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1057180811
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2192699633
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2650716191
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3684411041
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2113116865
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.210801685
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3014023966
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3112729472
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4184845406
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2773591708
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2993889184
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1484700020
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.279840770
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1076604421
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2825100914
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3693700639
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1111855900
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2211032943
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2863764148
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1992041223
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.456639283
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.109794817
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.918255941
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1552215576
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2971731670
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1373831532
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3219252791
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3668851261
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1141477543
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3078411400
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.518018829
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3777556391
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3301124938
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1544989334
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4221567277
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.749953880
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2946861389
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4205913850
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.550957770
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3305499475
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2782434643
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2375679774
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2059320588
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2078525261
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3089523892
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1395990708
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.194464399
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3558711629
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2274017142
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3268197580
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3373074818
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2455919878
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1316982488
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4069539080
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.50897398
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.435501396
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.341787456
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.119349489
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2079047179
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1989244744
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4047473794
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4085970590
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.72172021
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4234857088
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2139081710
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4200764764
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.559070392
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.105546932
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4246933976
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.512449497
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1640571879
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.205806115
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1562365687
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3964280551
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3000904394
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.342961305
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2445564657
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1864307114
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1215636686
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3725291193
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1160904313
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1027634364
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.657559859
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3964244353
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.760039492
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1739506772
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2114191030
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1331464032
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1866836991
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1077577587
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3954763853



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1395990708 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1592650000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2139081710 Mar 31 12:36:42 PM PDT 24 Mar 31 12:36:51 PM PDT 24 1459230000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3964280551 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1371850000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.105546932 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1383050000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.512449497 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1261410000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1866836991 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:38 PM PDT 24 1468390000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3000904394 Mar 31 12:36:25 PM PDT 24 Mar 31 12:36:32 PM PDT 24 1092170000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3086214408 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1505810000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3558711629 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1477210000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1077577587 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1574270000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1215636686 Mar 31 12:36:30 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1426510000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2274017142 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:37 PM PDT 24 1542630000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4047473794 Mar 31 12:36:26 PM PDT 24 Mar 31 12:36:37 PM PDT 24 1473530000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.342961305 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:36 PM PDT 24 1498090000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1989244744 Mar 31 12:36:26 PM PDT 24 Mar 31 12:36:38 PM PDT 24 1454910000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1739506772 Mar 31 12:36:40 PM PDT 24 Mar 31 12:36:47 PM PDT 24 1313850000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4069539080 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:39 PM PDT 24 1456070000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3268197580 Mar 31 12:36:26 PM PDT 24 Mar 31 12:36:36 PM PDT 24 1491110000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.119349489 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:42 PM PDT 24 1441050000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3373074818 Mar 31 12:36:26 PM PDT 24 Mar 31 12:36:35 PM PDT 24 1484430000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1562365687 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1549330000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1160904313 Mar 31 12:36:29 PM PDT 24 Mar 31 12:36:39 PM PDT 24 1419070000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1640571879 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:42 PM PDT 24 1471350000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1316982488 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1379210000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.205806115 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1357350000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.760039492 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1513070000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2078525261 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1524210000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2079047179 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1380590000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2059320588 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:37 PM PDT 24 1305670000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2445564657 Mar 31 12:36:30 PM PDT 24 Mar 31 12:36:40 PM PDT 24 1531430000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.559070392 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1396950000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3089523892 Mar 31 12:36:38 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1456250000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.435501396 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1359930000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4085970590 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1455690000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3725291193 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1535790000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.50897398 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:39 PM PDT 24 1115990000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.194464399 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:36 PM PDT 24 1419430000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4234857088 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1535690000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1331464032 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1381510000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2114191030 Mar 31 12:36:30 PM PDT 24 Mar 31 12:36:40 PM PDT 24 1555230000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.72172021 Mar 31 12:36:30 PM PDT 24 Mar 31 12:36:40 PM PDT 24 1517230000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.341787456 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1280170000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2455919878 Mar 31 12:36:38 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1516170000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3964244353 Mar 31 12:36:39 PM PDT 24 Mar 31 12:36:47 PM PDT 24 1399270000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4246933976 Mar 31 12:36:42 PM PDT 24 Mar 31 12:36:55 PM PDT 24 1444070000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3954763853 Mar 31 12:36:43 PM PDT 24 Mar 31 12:36:54 PM PDT 24 1571190000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1864307114 Mar 31 12:36:29 PM PDT 24 Mar 31 12:36:37 PM PDT 24 1204470000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.657559859 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1435750000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4200764764 Mar 31 12:36:39 PM PDT 24 Mar 31 12:36:48 PM PDT 24 1535210000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1027634364 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1405630000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3309350308 Mar 31 12:28:07 PM PDT 24 Mar 31 12:59:24 PM PDT 24 336711430000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2989867040 Mar 31 12:28:31 PM PDT 24 Mar 31 12:53:20 PM PDT 24 336492770000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2286764797 Mar 31 12:29:31 PM PDT 24 Mar 31 01:12:16 PM PDT 24 337008730000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3773407574 Mar 31 12:28:22 PM PDT 24 Mar 31 01:05:52 PM PDT 24 336702550000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3465957757 Mar 31 12:28:22 PM PDT 24 Mar 31 01:01:24 PM PDT 24 336793030000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2368741427 Mar 31 12:27:58 PM PDT 24 Mar 31 01:01:36 PM PDT 24 336632850000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3310487844 Mar 31 12:28:24 PM PDT 24 Mar 31 01:02:00 PM PDT 24 336579570000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1005562298 Mar 31 12:28:02 PM PDT 24 Mar 31 12:56:47 PM PDT 24 336546090000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2614526296 Mar 31 12:28:23 PM PDT 24 Mar 31 12:59:58 PM PDT 24 336486330000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1529110327 Mar 31 12:29:34 PM PDT 24 Mar 31 01:11:55 PM PDT 24 336308110000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3559940421 Mar 31 12:29:01 PM PDT 24 Mar 31 01:07:17 PM PDT 24 336637850000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2344065023 Mar 31 12:28:15 PM PDT 24 Mar 31 12:56:58 PM PDT 24 336509390000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3993355167 Mar 31 12:28:26 PM PDT 24 Mar 31 12:57:46 PM PDT 24 336804390000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.953100050 Mar 31 12:28:07 PM PDT 24 Mar 31 12:58:16 PM PDT 24 337035750000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.791701290 Mar 31 12:29:26 PM PDT 24 Mar 31 01:07:26 PM PDT 24 336752370000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.680035065 Mar 31 12:29:26 PM PDT 24 Mar 31 01:06:22 PM PDT 24 336702750000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.4104101825 Mar 31 12:29:31 PM PDT 24 Mar 31 01:11:16 PM PDT 24 336656050000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3296699019 Mar 31 12:28:17 PM PDT 24 Mar 31 12:56:50 PM PDT 24 337071150000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3155764413 Mar 31 12:27:55 PM PDT 24 Mar 31 12:55:59 PM PDT 24 336674770000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2822661410 Mar 31 12:28:11 PM PDT 24 Mar 31 12:57:33 PM PDT 24 336392750000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.145530943 Mar 31 12:29:27 PM PDT 24 Mar 31 01:06:41 PM PDT 24 336660190000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2811595577 Mar 31 12:29:27 PM PDT 24 Mar 31 01:06:02 PM PDT 24 336742830000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2804387110 Mar 31 12:29:31 PM PDT 24 Mar 31 01:12:10 PM PDT 24 336912210000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1242435446 Mar 31 12:28:12 PM PDT 24 Mar 31 12:58:57 PM PDT 24 336891890000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3374497094 Mar 31 12:28:09 PM PDT 24 Mar 31 12:58:54 PM PDT 24 336970990000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2225894737 Mar 31 12:28:11 PM PDT 24 Mar 31 12:57:28 PM PDT 24 336736930000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2473471137 Mar 31 12:28:00 PM PDT 24 Mar 31 12:53:53 PM PDT 24 337066770000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1236828658 Mar 31 12:27:56 PM PDT 24 Mar 31 12:59:13 PM PDT 24 336413510000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2146049921 Mar 31 12:29:23 PM PDT 24 Mar 31 01:06:38 PM PDT 24 336422270000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2936816084 Mar 31 12:28:20 PM PDT 24 Mar 31 12:56:59 PM PDT 24 336362870000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.38004348 Mar 31 12:29:23 PM PDT 24 Mar 31 01:07:00 PM PDT 24 336849930000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3007668797 Mar 31 12:28:33 PM PDT 24 Mar 31 01:00:14 PM PDT 24 336611530000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1247628357 Mar 31 12:29:22 PM PDT 24 Mar 31 01:05:15 PM PDT 24 336956570000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4066426310 Mar 31 12:28:20 PM PDT 24 Mar 31 12:56:41 PM PDT 24 336605670000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2659273886 Mar 31 12:28:23 PM PDT 24 Mar 31 12:57:13 PM PDT 24 336596330000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.292814931 Mar 31 12:28:07 PM PDT 24 Mar 31 12:58:23 PM PDT 24 336981890000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1790466868 Mar 31 12:27:58 PM PDT 24 Mar 31 01:01:21 PM PDT 24 336560070000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1986706612 Mar 31 12:28:05 PM PDT 24 Mar 31 12:58:53 PM PDT 24 336785570000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2928711999 Mar 31 12:29:29 PM PDT 24 Mar 31 01:12:30 PM PDT 24 336515330000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2392700255 Mar 31 12:29:29 PM PDT 24 Mar 31 01:11:29 PM PDT 24 337076230000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.505307287 Mar 31 12:27:51 PM PDT 24 Mar 31 01:00:25 PM PDT 24 336755750000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3007887258 Mar 31 12:28:27 PM PDT 24 Mar 31 01:00:14 PM PDT 24 337007190000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1493163549 Mar 31 12:28:15 PM PDT 24 Mar 31 12:58:33 PM PDT 24 336786970000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1974482020 Mar 31 12:29:24 PM PDT 24 Mar 31 01:05:36 PM PDT 24 336371990000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4051250337 Mar 31 12:28:26 PM PDT 24 Mar 31 12:52:26 PM PDT 24 336451930000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1748403563 Mar 31 12:27:57 PM PDT 24 Mar 31 01:01:52 PM PDT 24 336650650000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4016911575 Mar 31 12:28:59 PM PDT 24 Mar 31 01:11:05 PM PDT 24 336468310000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2963740005 Mar 31 12:29:32 PM PDT 24 Mar 31 01:11:58 PM PDT 24 336912310000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2775193521 Mar 31 12:28:20 PM PDT 24 Mar 31 12:54:50 PM PDT 24 336914350000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3066503838 Mar 31 12:28:10 PM PDT 24 Mar 31 12:57:49 PM PDT 24 336446290000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2946861389 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1458590000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1992041223 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1596130000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1111855900 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1411390000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2971731670 Mar 31 12:36:31 PM PDT 24 Mar 31 12:36:39 PM PDT 24 1476610000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3219252791 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1532730000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3014023966 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1497490000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2192699633 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1416050000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.279840770 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1531030000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.918255941 Mar 31 12:36:40 PM PDT 24 Mar 31 12:36:49 PM PDT 24 1560630000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3078411400 Mar 31 12:36:38 PM PDT 24 Mar 31 12:36:47 PM PDT 24 1285010000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3684411041 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1519230000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1373831532 Mar 31 12:36:31 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1647750000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.550957770 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1527310000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2782434643 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1603630000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2650716191 Mar 31 12:36:53 PM PDT 24 Mar 31 12:37:01 PM PDT 24 1416450000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3909163054 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:48 PM PDT 24 1528530000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.109794817 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1372810000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2178424260 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1524730000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.749953880 Mar 31 12:36:42 PM PDT 24 Mar 31 12:36:52 PM PDT 24 1459650000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1057180811 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1529610000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2375679774 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1430170000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3668851261 Mar 31 12:36:42 PM PDT 24 Mar 31 12:36:48 PM PDT 24 1276850000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4279822215 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1408150000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3305499475 Mar 31 12:36:38 PM PDT 24 Mar 31 12:36:47 PM PDT 24 1531630000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1544989334 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:40 PM PDT 24 1596850000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3777556391 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1515730000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2773591708 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1102390000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1141477543 Mar 31 12:36:44 PM PDT 24 Mar 31 12:36:53 PM PDT 24 1569510000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4205913850 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:40 PM PDT 24 1583970000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2825708544 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1325090000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4221567277 Mar 31 12:36:48 PM PDT 24 Mar 31 12:36:58 PM PDT 24 1411790000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.518018829 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:47 PM PDT 24 1613050000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1552215576 Mar 31 12:36:37 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1576290000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2863764148 Mar 31 12:36:30 PM PDT 24 Mar 31 12:36:38 PM PDT 24 1452970000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2993889184 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1493530000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2340788847 Mar 31 12:36:30 PM PDT 24 Mar 31 12:36:42 PM PDT 24 1493010000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1076604421 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1427670000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3693700639 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1570350000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.867201742 Mar 31 12:36:39 PM PDT 24 Mar 31 12:36:46 PM PDT 24 1310570000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.210801685 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1426610000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2814598363 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1484330000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3301124938 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:43 PM PDT 24 1288730000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3112729472 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1518390000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1484700020 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1323450000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1110946366 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1455390000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2211032943 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1503790000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4184845406 Mar 31 12:36:32 PM PDT 24 Mar 31 12:36:41 PM PDT 24 1564650000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.456639283 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:44 PM PDT 24 1492550000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2113116865 Mar 31 12:36:39 PM PDT 24 Mar 31 12:36:47 PM PDT 24 1351350000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2825100914 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:45 PM PDT 24 1407430000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4157820259 Mar 31 12:36:37 PM PDT 24 Mar 31 01:02:32 PM PDT 24 336452770000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2427361449 Mar 31 12:36:36 PM PDT 24 Mar 31 01:03:55 PM PDT 24 336959390000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3986526008 Mar 31 12:36:34 PM PDT 24 Mar 31 01:08:52 PM PDT 24 336382750000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4184237384 Mar 31 12:36:39 PM PDT 24 Mar 31 01:08:59 PM PDT 24 336400210000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1141849914 Mar 31 12:36:40 PM PDT 24 Mar 31 01:07:46 PM PDT 24 336786670000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2066961868 Mar 31 12:36:40 PM PDT 24 Mar 31 01:10:23 PM PDT 24 336917510000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.140548616 Mar 31 12:37:21 PM PDT 24 Mar 31 01:11:30 PM PDT 24 337171830000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2861876056 Mar 31 12:36:37 PM PDT 24 Mar 31 01:06:44 PM PDT 24 337029550000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1072956386 Mar 31 12:36:40 PM PDT 24 Mar 31 01:08:02 PM PDT 24 336367870000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1154817577 Mar 31 12:36:41 PM PDT 24 Mar 31 01:00:52 PM PDT 24 336827170000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1299245315 Mar 31 12:36:49 PM PDT 24 Mar 31 01:09:26 PM PDT 24 336491210000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1250348899 Mar 31 12:37:04 PM PDT 24 Mar 31 01:07:55 PM PDT 24 336763350000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2319257460 Mar 31 12:37:05 PM PDT 24 Mar 31 01:11:14 PM PDT 24 336880890000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1536301395 Mar 31 12:36:42 PM PDT 24 Mar 31 01:12:07 PM PDT 24 336895910000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.721805328 Mar 31 12:37:06 PM PDT 24 Mar 31 01:10:45 PM PDT 24 336924510000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1898372362 Mar 31 12:37:12 PM PDT 24 Mar 31 01:12:42 PM PDT 24 336975330000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4191881765 Mar 31 12:36:40 PM PDT 24 Mar 31 01:07:44 PM PDT 24 336910130000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1657325657 Mar 31 12:36:41 PM PDT 24 Mar 31 01:07:27 PM PDT 24 336512830000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3211313918 Mar 31 12:36:36 PM PDT 24 Mar 31 01:03:15 PM PDT 24 336470890000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3359140 Mar 31 12:36:46 PM PDT 24 Mar 31 01:10:24 PM PDT 24 336753870000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3731180478 Mar 31 12:36:40 PM PDT 24 Mar 31 01:10:34 PM PDT 24 336913570000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3520457628 Mar 31 12:36:36 PM PDT 24 Mar 31 01:07:27 PM PDT 24 336868610000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3901099623 Mar 31 12:37:00 PM PDT 24 Mar 31 01:12:21 PM PDT 24 336771290000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1261990227 Mar 31 12:36:37 PM PDT 24 Mar 31 01:06:25 PM PDT 24 336718710000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.251328254 Mar 31 12:36:39 PM PDT 24 Mar 31 01:08:03 PM PDT 24 336876630000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2922030797 Mar 31 12:37:11 PM PDT 24 Mar 31 01:05:43 PM PDT 24 336562310000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.784030212 Mar 31 12:36:37 PM PDT 24 Mar 31 01:06:12 PM PDT 24 336792130000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.855143974 Mar 31 12:36:37 PM PDT 24 Mar 31 01:12:17 PM PDT 24 336939590000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.175553275 Mar 31 12:36:48 PM PDT 24 Mar 31 01:06:12 PM PDT 24 337006930000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2709605636 Mar 31 12:36:39 PM PDT 24 Mar 31 01:06:16 PM PDT 24 337110470000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3928865507 Mar 31 12:36:42 PM PDT 24 Mar 31 01:03:16 PM PDT 24 336618750000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3303243436 Mar 31 12:36:59 PM PDT 24 Mar 31 01:11:28 PM PDT 24 337141150000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2466450737 Mar 31 12:36:58 PM PDT 24 Mar 31 01:07:36 PM PDT 24 336388190000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4077358445 Mar 31 12:36:40 PM PDT 24 Mar 31 01:10:41 PM PDT 24 336885270000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.599243282 Mar 31 12:36:34 PM PDT 24 Mar 31 01:07:43 PM PDT 24 336947650000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1009781033 Mar 31 12:36:42 PM PDT 24 Mar 31 01:08:13 PM PDT 24 336380490000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.445595885 Mar 31 12:36:44 PM PDT 24 Mar 31 01:11:06 PM PDT 24 336903850000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2806557784 Mar 31 12:36:46 PM PDT 24 Mar 31 01:09:01 PM PDT 24 336415930000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.687349331 Mar 31 12:36:38 PM PDT 24 Mar 31 01:16:15 PM PDT 24 337069530000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2333546665 Mar 31 12:36:38 PM PDT 24 Mar 31 01:08:16 PM PDT 24 336944630000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2631330065 Mar 31 12:36:57 PM PDT 24 Mar 31 01:08:24 PM PDT 24 336778570000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1217954353 Mar 31 12:36:40 PM PDT 24 Mar 31 01:06:58 PM PDT 24 336944410000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2843571888 Mar 31 12:37:06 PM PDT 24 Mar 31 01:13:05 PM PDT 24 336897390000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2699274358 Mar 31 12:36:40 PM PDT 24 Mar 31 01:12:51 PM PDT 24 336879990000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1036014937 Mar 31 12:36:41 PM PDT 24 Mar 31 01:08:07 PM PDT 24 336566630000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1430391058 Mar 31 12:36:55 PM PDT 24 Mar 31 01:06:20 PM PDT 24 336381950000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.142177557 Mar 31 12:36:42 PM PDT 24 Mar 31 01:11:17 PM PDT 24 337080970000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3731677914 Mar 31 12:37:04 PM PDT 24 Mar 31 01:13:07 PM PDT 24 336807230000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4254161703 Mar 31 12:36:56 PM PDT 24 Mar 31 01:05:19 PM PDT 24 336380630000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.689766345 Mar 31 12:36:50 PM PDT 24 Mar 31 01:14:01 PM PDT 24 336726430000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3086214408
Short name T11
Test name
Test status
Simulation time 1505810000 ps
CPU time 3.88 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164864 kb
Host smart-f22d5e75-2cd8-41fb-ab5b-2d1627999057
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3086214408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3086214408
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3773407574
Short name T14
Test name
Test status
Simulation time 336702550000 ps
CPU time 935.18 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 01:05:52 PM PDT 24
Peak memory 160700 kb
Host smart-e1203753-c5e9-4cf2-a47f-9e27b69e23f7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3773407574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3773407574
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4157820259
Short name T21
Test name
Test status
Simulation time 336452770000 ps
CPU time 628.77 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 01:02:32 PM PDT 24
Peak memory 160692 kb
Host smart-cb672070-d587-435c-9342-9053ee34e15c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4157820259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.4157820259
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3007887258
Short name T102
Test name
Test status
Simulation time 337007190000 ps
CPU time 769.36 seconds
Started Mar 31 12:28:27 PM PDT 24
Finished Mar 31 01:00:14 PM PDT 24
Peak memory 160676 kb
Host smart-86793f07-e270-4b2e-a1fd-3c3576f1e5bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3007887258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3007887258
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2473471137
Short name T87
Test name
Test status
Simulation time 337066770000 ps
CPU time 629.57 seconds
Started Mar 31 12:28:00 PM PDT 24
Finished Mar 31 12:53:53 PM PDT 24
Peak memory 160704 kb
Host smart-a2805711-1784-4164-9b58-fa99ba66aa05
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2473471137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2473471137
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2146049921
Short name T89
Test name
Test status
Simulation time 336422270000 ps
CPU time 891.91 seconds
Started Mar 31 12:29:23 PM PDT 24
Finished Mar 31 01:06:38 PM PDT 24
Peak memory 160232 kb
Host smart-ba8b870c-5456-4595-a4dd-935eec511aa6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2146049921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2146049921
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3155764413
Short name T79
Test name
Test status
Simulation time 336674770000 ps
CPU time 685.72 seconds
Started Mar 31 12:27:55 PM PDT 24
Finished Mar 31 12:55:59 PM PDT 24
Peak memory 160644 kb
Host smart-c4f979fa-fc54-445d-abd2-1c301058110d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3155764413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3155764413
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.680035065
Short name T76
Test name
Test status
Simulation time 336702750000 ps
CPU time 874.49 seconds
Started Mar 31 12:29:26 PM PDT 24
Finished Mar 31 01:06:22 PM PDT 24
Peak memory 160220 kb
Host smart-d3192d6e-7b7f-428f-ab19-3666ebd89b6b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=680035065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.680035065
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4051250337
Short name T105
Test name
Test status
Simulation time 336451930000 ps
CPU time 575.97 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:52:26 PM PDT 24
Peak memory 160704 kb
Host smart-6e1f67c8-da88-426d-b5b9-88ae5d8f3cdd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4051250337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4051250337
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2963740005
Short name T108
Test name
Test status
Simulation time 336912310000 ps
CPU time 1013.65 seconds
Started Mar 31 12:29:32 PM PDT 24
Finished Mar 31 01:11:58 PM PDT 24
Peak memory 160608 kb
Host smart-50f49441-416f-445a-8527-32b21965975b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963740005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2963740005
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3309350308
Short name T4
Test name
Test status
Simulation time 336711430000 ps
CPU time 757.43 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:59:24 PM PDT 24
Peak memory 160712 kb
Host smart-3224e7d5-836d-4035-ba7f-322072d3542a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3309350308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3309350308
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1493163549
Short name T103
Test name
Test status
Simulation time 336786970000 ps
CPU time 729.08 seconds
Started Mar 31 12:28:15 PM PDT 24
Finished Mar 31 12:58:33 PM PDT 24
Peak memory 160680 kb
Host smart-1cf9d954-308b-4001-a7ce-f0488df3ff79
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1493163549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1493163549
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.38004348
Short name T91
Test name
Test status
Simulation time 336849930000 ps
CPU time 899.86 seconds
Started Mar 31 12:29:23 PM PDT 24
Finished Mar 31 01:07:00 PM PDT 24
Peak memory 160224 kb
Host smart-1c58c1db-6fe3-4f40-8a66-21924206bcbc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=38004348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.38004348
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.4104101825
Short name T77
Test name
Test status
Simulation time 336656050000 ps
CPU time 997.66 seconds
Started Mar 31 12:29:31 PM PDT 24
Finished Mar 31 01:11:16 PM PDT 24
Peak memory 160608 kb
Host smart-a6800824-c67d-4abd-ba13-09fcb3cbb7c3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4104101825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.4104101825
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3993355167
Short name T73
Test name
Test status
Simulation time 336804390000 ps
CPU time 716.6 seconds
Started Mar 31 12:28:26 PM PDT 24
Finished Mar 31 12:57:46 PM PDT 24
Peak memory 160696 kb
Host smart-b7856378-9e38-4214-b01e-65dae87e3638
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3993355167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3993355167
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2614526296
Short name T19
Test name
Test status
Simulation time 336486330000 ps
CPU time 785.45 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:59:58 PM PDT 24
Peak memory 160772 kb
Host smart-7bfb09ee-eaec-4a27-973c-dab6aee237d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2614526296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2614526296
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2344065023
Short name T72
Test name
Test status
Simulation time 336509390000 ps
CPU time 694.21 seconds
Started Mar 31 12:28:15 PM PDT 24
Finished Mar 31 12:56:58 PM PDT 24
Peak memory 160708 kb
Host smart-92d05bae-c845-42ee-b588-12f1ee7a29e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2344065023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2344065023
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3559940421
Short name T71
Test name
Test status
Simulation time 336637850000 ps
CPU time 933.65 seconds
Started Mar 31 12:29:01 PM PDT 24
Finished Mar 31 01:07:17 PM PDT 24
Peak memory 159736 kb
Host smart-d4757ad8-8cb7-4aa0-82ac-9089f72b42cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3559940421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3559940421
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3310487844
Short name T17
Test name
Test status
Simulation time 336579570000 ps
CPU time 832.24 seconds
Started Mar 31 12:28:24 PM PDT 24
Finished Mar 31 01:02:00 PM PDT 24
Peak memory 160704 kb
Host smart-37091acf-7328-4143-afb4-76d4fd7e78db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3310487844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3310487844
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3374497094
Short name T85
Test name
Test status
Simulation time 336970990000 ps
CPU time 755.41 seconds
Started Mar 31 12:28:09 PM PDT 24
Finished Mar 31 12:58:54 PM PDT 24
Peak memory 160676 kb
Host smart-ce164413-00f2-4845-a2e4-205679f2ae63
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3374497094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3374497094
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1236828658
Short name T88
Test name
Test status
Simulation time 336413510000 ps
CPU time 751.97 seconds
Started Mar 31 12:27:56 PM PDT 24
Finished Mar 31 12:59:13 PM PDT 24
Peak memory 160680 kb
Host smart-6128cffa-9aa3-4f97-b506-c17a66445bb4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1236828658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1236828658
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2225894737
Short name T86
Test name
Test status
Simulation time 336736930000 ps
CPU time 716.75 seconds
Started Mar 31 12:28:11 PM PDT 24
Finished Mar 31 12:57:28 PM PDT 24
Peak memory 160664 kb
Host smart-fdec6c1c-282c-44fd-9fa9-232d326d04a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2225894737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2225894737
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4016911575
Short name T107
Test name
Test status
Simulation time 336468310000 ps
CPU time 1014.5 seconds
Started Mar 31 12:28:59 PM PDT 24
Finished Mar 31 01:11:05 PM PDT 24
Peak memory 159620 kb
Host smart-02f40f71-c647-4838-af78-49e508a5c38f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4016911575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4016911575
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2368741427
Short name T16
Test name
Test status
Simulation time 336632850000 ps
CPU time 803.76 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 01:01:36 PM PDT 24
Peak memory 160696 kb
Host smart-be58a2a7-5f0e-4939-88d9-a6e1473651e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2368741427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2368741427
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2811595577
Short name T82
Test name
Test status
Simulation time 336742830000 ps
CPU time 871.27 seconds
Started Mar 31 12:29:27 PM PDT 24
Finished Mar 31 01:06:02 PM PDT 24
Peak memory 160468 kb
Host smart-aec10c04-9fd0-49d4-995a-ae10a15aede0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2811595577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2811595577
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1974482020
Short name T104
Test name
Test status
Simulation time 336371990000 ps
CPU time 849.77 seconds
Started Mar 31 12:29:24 PM PDT 24
Finished Mar 31 01:05:36 PM PDT 24
Peak memory 160228 kb
Host smart-387cfc4f-2de8-47e8-901d-38afa5633d87
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1974482020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1974482020
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3066503838
Short name T110
Test name
Test status
Simulation time 336446290000 ps
CPU time 724.06 seconds
Started Mar 31 12:28:10 PM PDT 24
Finished Mar 31 12:57:49 PM PDT 24
Peak memory 160736 kb
Host smart-2ecdbf95-54b1-45e4-9d70-8caf9b0c3df8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3066503838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3066503838
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1005562298
Short name T18
Test name
Test status
Simulation time 336546090000 ps
CPU time 699.26 seconds
Started Mar 31 12:28:02 PM PDT 24
Finished Mar 31 12:56:47 PM PDT 24
Peak memory 160708 kb
Host smart-31aa38c6-ffc6-4385-9289-91ea4944bc4d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1005562298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1005562298
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3007668797
Short name T92
Test name
Test status
Simulation time 336611530000 ps
CPU time 780.82 seconds
Started Mar 31 12:28:33 PM PDT 24
Finished Mar 31 01:00:14 PM PDT 24
Peak memory 160740 kb
Host smart-7f86c06f-d164-4585-8d78-b18069c9b7f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3007668797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3007668797
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1247628357
Short name T93
Test name
Test status
Simulation time 336956570000 ps
CPU time 830.26 seconds
Started Mar 31 12:29:22 PM PDT 24
Finished Mar 31 01:05:15 PM PDT 24
Peak memory 160220 kb
Host smart-47688560-7398-49ff-bc1d-a03f7bfccd2d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1247628357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1247628357
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.292814931
Short name T96
Test name
Test status
Simulation time 336981890000 ps
CPU time 736.27 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:58:23 PM PDT 24
Peak memory 160696 kb
Host smart-c7e78437-0e09-4eca-848a-45ebe337cff2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=292814931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.292814931
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2286764797
Short name T6
Test name
Test status
Simulation time 337008730000 ps
CPU time 1025.76 seconds
Started Mar 31 12:29:31 PM PDT 24
Finished Mar 31 01:12:16 PM PDT 24
Peak memory 160608 kb
Host smart-b76bc44c-579e-454b-8282-095810a8037d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2286764797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2286764797
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1242435446
Short name T84
Test name
Test status
Simulation time 336891890000 ps
CPU time 754.87 seconds
Started Mar 31 12:28:12 PM PDT 24
Finished Mar 31 12:58:57 PM PDT 24
Peak memory 160692 kb
Host smart-ba5f7db3-bf26-474f-bf44-fe9d496340d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1242435446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1242435446
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3296699019
Short name T78
Test name
Test status
Simulation time 337071150000 ps
CPU time 700.25 seconds
Started Mar 31 12:28:17 PM PDT 24
Finished Mar 31 12:56:50 PM PDT 24
Peak memory 160708 kb
Host smart-a94cbf36-69d5-4d19-8f39-9aeee7954f1e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3296699019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3296699019
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3465957757
Short name T15
Test name
Test status
Simulation time 336793030000 ps
CPU time 815.06 seconds
Started Mar 31 12:28:22 PM PDT 24
Finished Mar 31 01:01:24 PM PDT 24
Peak memory 160692 kb
Host smart-a48936f8-450d-4d41-bb71-4fbf74a08903
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3465957757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3465957757
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1790466868
Short name T97
Test name
Test status
Simulation time 336560070000 ps
CPU time 803.55 seconds
Started Mar 31 12:27:58 PM PDT 24
Finished Mar 31 01:01:21 PM PDT 24
Peak memory 160696 kb
Host smart-1aee5d36-bf93-4fc9-8361-a23926269c42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1790466868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1790466868
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2659273886
Short name T95
Test name
Test status
Simulation time 336596330000 ps
CPU time 703.26 seconds
Started Mar 31 12:28:23 PM PDT 24
Finished Mar 31 12:57:13 PM PDT 24
Peak memory 160776 kb
Host smart-90a614ad-a2e4-4b55-909a-c57f6f08ad59
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2659273886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2659273886
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.145530943
Short name T81
Test name
Test status
Simulation time 336660190000 ps
CPU time 896.22 seconds
Started Mar 31 12:29:27 PM PDT 24
Finished Mar 31 01:06:41 PM PDT 24
Peak memory 160452 kb
Host smart-152b2c0d-6760-4048-a056-0ca5d8e7e53c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=145530943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.145530943
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.791701290
Short name T75
Test name
Test status
Simulation time 336752370000 ps
CPU time 919.71 seconds
Started Mar 31 12:29:26 PM PDT 24
Finished Mar 31 01:07:26 PM PDT 24
Peak memory 160220 kb
Host smart-95be23da-e9c1-4db6-94ad-4a048542d4ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=791701290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.791701290
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1529110327
Short name T20
Test name
Test status
Simulation time 336308110000 ps
CPU time 1011.78 seconds
Started Mar 31 12:29:34 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 160608 kb
Host smart-87ad4010-71b2-4b78-ba82-f3cdb285e06c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529110327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1529110327
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.953100050
Short name T74
Test name
Test status
Simulation time 337035750000 ps
CPU time 721.97 seconds
Started Mar 31 12:28:07 PM PDT 24
Finished Mar 31 12:58:16 PM PDT 24
Peak memory 160680 kb
Host smart-5c13c608-8068-49bd-a6b6-d69f9185196f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=953100050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.953100050
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2936816084
Short name T90
Test name
Test status
Simulation time 336362870000 ps
CPU time 710.25 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:56:59 PM PDT 24
Peak memory 160656 kb
Host smart-3bbf0249-1050-49d6-a126-26f97dd7637b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2936816084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2936816084
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.505307287
Short name T101
Test name
Test status
Simulation time 336755750000 ps
CPU time 781.14 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 01:00:25 PM PDT 24
Peak memory 160696 kb
Host smart-b40667af-5a52-4068-9863-acae12df1a05
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505307287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.505307287
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2775193521
Short name T109
Test name
Test status
Simulation time 336914350000 ps
CPU time 640.69 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:54:50 PM PDT 24
Peak memory 160680 kb
Host smart-77fbc036-e967-43d6-a1f7-39e84c99cebb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2775193521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2775193521
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2804387110
Short name T83
Test name
Test status
Simulation time 336912210000 ps
CPU time 1018.38 seconds
Started Mar 31 12:29:31 PM PDT 24
Finished Mar 31 01:12:10 PM PDT 24
Peak memory 160608 kb
Host smart-e704839f-c04b-475c-9dd1-4a0b1236cf81
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2804387110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2804387110
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2392700255
Short name T100
Test name
Test status
Simulation time 337076230000 ps
CPU time 1000.83 seconds
Started Mar 31 12:29:29 PM PDT 24
Finished Mar 31 01:11:29 PM PDT 24
Peak memory 160608 kb
Host smart-99106efb-0f7c-4531-a7fb-eeb305fbc719
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2392700255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2392700255
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4066426310
Short name T94
Test name
Test status
Simulation time 336605670000 ps
CPU time 694.48 seconds
Started Mar 31 12:28:20 PM PDT 24
Finished Mar 31 12:56:41 PM PDT 24
Peak memory 160708 kb
Host smart-0d447cda-9b4c-4c02-a46c-28bd76a27a8d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4066426310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4066426310
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1986706612
Short name T98
Test name
Test status
Simulation time 336785570000 ps
CPU time 744.32 seconds
Started Mar 31 12:28:05 PM PDT 24
Finished Mar 31 12:58:53 PM PDT 24
Peak memory 160672 kb
Host smart-41693386-8c70-42ae-99f6-cf674223d9ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1986706612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1986706612
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2989867040
Short name T5
Test name
Test status
Simulation time 336492770000 ps
CPU time 596.69 seconds
Started Mar 31 12:28:31 PM PDT 24
Finished Mar 31 12:53:20 PM PDT 24
Peak memory 160696 kb
Host smart-0bf7a6e0-5cda-4c55-98ef-32bb6954f950
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2989867040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2989867040
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1748403563
Short name T106
Test name
Test status
Simulation time 336650650000 ps
CPU time 834.88 seconds
Started Mar 31 12:27:57 PM PDT 24
Finished Mar 31 01:01:52 PM PDT 24
Peak memory 160668 kb
Host smart-47552d8c-6768-4761-b644-5163b7237d11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1748403563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1748403563
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2928711999
Short name T99
Test name
Test status
Simulation time 336515330000 ps
CPU time 1035.5 seconds
Started Mar 31 12:29:29 PM PDT 24
Finished Mar 31 01:12:30 PM PDT 24
Peak memory 160604 kb
Host smart-b31136ae-2b4d-4581-8442-e83aceb8c92d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928711999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2928711999
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2822661410
Short name T80
Test name
Test status
Simulation time 336392750000 ps
CPU time 712.45 seconds
Started Mar 31 12:28:11 PM PDT 24
Finished Mar 31 12:57:33 PM PDT 24
Peak memory 160700 kb
Host smart-2a99a938-4369-49af-8c8a-9c970a1b2d14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2822661410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2822661410
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.855143974
Short name T178
Test name
Test status
Simulation time 336939590000 ps
CPU time 879.15 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 01:12:17 PM PDT 24
Peak memory 160792 kb
Host smart-c1a5e473-ea2b-49d8-9e63-485642c5eac9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=855143974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.855143974
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1217954353
Short name T192
Test name
Test status
Simulation time 336944410000 ps
CPU time 740.95 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:06:58 PM PDT 24
Peak memory 160788 kb
Host smart-efdf2bdc-a1de-4742-afde-e4d264855f8e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1217954353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1217954353
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.689766345
Short name T200
Test name
Test status
Simulation time 336726430000 ps
CPU time 921.3 seconds
Started Mar 31 12:36:50 PM PDT 24
Finished Mar 31 01:14:01 PM PDT 24
Peak memory 160696 kb
Host smart-9ca2061b-7f20-4951-b5b9-a6611adb91d3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=689766345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.689766345
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2427361449
Short name T22
Test name
Test status
Simulation time 336959390000 ps
CPU time 670.62 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 01:03:55 PM PDT 24
Peak memory 160784 kb
Host smart-b9096b04-5208-4d20-8307-8672f9e7f93a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2427361449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2427361449
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3520457628
Short name T172
Test name
Test status
Simulation time 336868610000 ps
CPU time 748.64 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 01:07:27 PM PDT 24
Peak memory 160796 kb
Host smart-974b4059-e834-417d-bba4-330da7022058
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3520457628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3520457628
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2709605636
Short name T180
Test name
Test status
Simulation time 337110470000 ps
CPU time 707.22 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 01:06:16 PM PDT 24
Peak memory 160716 kb
Host smart-770b847b-9768-4b5e-91a4-822b63cb477b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2709605636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2709605636
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.687349331
Short name T189
Test name
Test status
Simulation time 337069530000 ps
CPU time 995.37 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 01:16:15 PM PDT 24
Peak memory 160708 kb
Host smart-8e6ad37f-122c-40aa-b7b1-b02e3fafc6be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=687349331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.687349331
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.784030212
Short name T177
Test name
Test status
Simulation time 336792130000 ps
CPU time 729.1 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 01:06:12 PM PDT 24
Peak memory 160792 kb
Host smart-1eb9b531-42c0-480d-8767-98107cdfd680
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=784030212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.784030212
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3731180478
Short name T171
Test name
Test status
Simulation time 336913570000 ps
CPU time 827.94 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:10:34 PM PDT 24
Peak memory 160804 kb
Host smart-beacc33f-d6c7-4f62-aeb8-12c87115c96c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3731180478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3731180478
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.599243282
Short name T185
Test name
Test status
Simulation time 336947650000 ps
CPU time 767.17 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 01:07:43 PM PDT 24
Peak memory 160684 kb
Host smart-d3c06d15-f5f6-42f4-8024-53cce0134f04
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=599243282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.599243282
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1141849914
Short name T25
Test name
Test status
Simulation time 336786670000 ps
CPU time 747.78 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:07:46 PM PDT 24
Peak memory 160796 kb
Host smart-25b4f0a8-40b1-4e8c-b700-92ae52c3b703
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1141849914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1141849914
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2861876056
Short name T28
Test name
Test status
Simulation time 337029550000 ps
CPU time 736.9 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 01:06:44 PM PDT 24
Peak memory 160684 kb
Host smart-d8ea331d-3d7a-4dd2-ad81-e321f4d6b963
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2861876056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2861876056
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.251328254
Short name T175
Test name
Test status
Simulation time 336876630000 ps
CPU time 762.01 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 01:08:03 PM PDT 24
Peak memory 160708 kb
Host smart-3b01c35d-eaa6-4a5a-88cb-3b9b867b364e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=251328254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.251328254
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.175553275
Short name T179
Test name
Test status
Simulation time 337006930000 ps
CPU time 720.07 seconds
Started Mar 31 12:36:48 PM PDT 24
Finished Mar 31 01:06:12 PM PDT 24
Peak memory 160788 kb
Host smart-cb9a7627-5157-4fdf-be40-154640a5deea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=175553275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.175553275
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1299245315
Short name T161
Test name
Test status
Simulation time 336491210000 ps
CPU time 803.36 seconds
Started Mar 31 12:36:49 PM PDT 24
Finished Mar 31 01:09:26 PM PDT 24
Peak memory 160700 kb
Host smart-266b21ce-b97e-4a98-b207-8c9f560d4e2b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1299245315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1299245315
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1536301395
Short name T164
Test name
Test status
Simulation time 336895910000 ps
CPU time 867.57 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 01:12:07 PM PDT 24
Peak memory 160796 kb
Host smart-4e993d57-5e76-4f76-8261-5333c882ecfe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1536301395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1536301395
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1154817577
Short name T30
Test name
Test status
Simulation time 336827170000 ps
CPU time 565.7 seconds
Started Mar 31 12:36:41 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 160852 kb
Host smart-3f11c364-7ae0-4839-8afc-074318c9673f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1154817577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1154817577
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2699274358
Short name T194
Test name
Test status
Simulation time 336879990000 ps
CPU time 879.35 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:12:51 PM PDT 24
Peak memory 160796 kb
Host smart-fb978761-4d20-4a0b-a76c-ba3d83f53c51
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2699274358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2699274358
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1009781033
Short name T186
Test name
Test status
Simulation time 336380490000 ps
CPU time 759.78 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 01:08:13 PM PDT 24
Peak memory 160796 kb
Host smart-5f0c1c26-4c2e-4ec4-a82a-d51d2eee4737
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1009781033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1009781033
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2466450737
Short name T183
Test name
Test status
Simulation time 336388190000 ps
CPU time 744.14 seconds
Started Mar 31 12:36:58 PM PDT 24
Finished Mar 31 01:07:36 PM PDT 24
Peak memory 160716 kb
Host smart-bcdac572-e53c-4e09-8d83-18bdb6ee5f81
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2466450737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2466450737
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3731677914
Short name T198
Test name
Test status
Simulation time 336807230000 ps
CPU time 877.37 seconds
Started Mar 31 12:37:04 PM PDT 24
Finished Mar 31 01:13:07 PM PDT 24
Peak memory 160720 kb
Host smart-355c5826-bf19-4b98-b09e-3a945b4c4aa8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3731677914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3731677914
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2319257460
Short name T163
Test name
Test status
Simulation time 336880890000 ps
CPU time 831.15 seconds
Started Mar 31 12:37:05 PM PDT 24
Finished Mar 31 01:11:14 PM PDT 24
Peak memory 160804 kb
Host smart-21a7a0fc-dbb8-4bcb-91cd-30eccb216009
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2319257460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2319257460
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3986526008
Short name T23
Test name
Test status
Simulation time 336382750000 ps
CPU time 795.37 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 01:08:52 PM PDT 24
Peak memory 160696 kb
Host smart-611a0c31-0e05-4e94-a7d9-5a6c9df12204
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3986526008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3986526008
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.445595885
Short name T187
Test name
Test status
Simulation time 336903850000 ps
CPU time 842.35 seconds
Started Mar 31 12:36:44 PM PDT 24
Finished Mar 31 01:11:06 PM PDT 24
Peak memory 160760 kb
Host smart-d016bdce-d29d-404a-a3f6-58f47f35eed3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=445595885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.445595885
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2922030797
Short name T176
Test name
Test status
Simulation time 336562310000 ps
CPU time 688.77 seconds
Started Mar 31 12:37:11 PM PDT 24
Finished Mar 31 01:05:43 PM PDT 24
Peak memory 160800 kb
Host smart-1faa839e-12e4-4215-9daf-a5e827825532
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2922030797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2922030797
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2333546665
Short name T190
Test name
Test status
Simulation time 336944630000 ps
CPU time 761.66 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 01:08:16 PM PDT 24
Peak memory 160796 kb
Host smart-93216526-68df-4277-b93e-435588a9bd6e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2333546665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2333546665
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4077358445
Short name T184
Test name
Test status
Simulation time 336885270000 ps
CPU time 835.84 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:10:41 PM PDT 24
Peak memory 160684 kb
Host smart-2467d2d0-6516-4f2c-9c38-57b7fe41f880
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4077358445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4077358445
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4184237384
Short name T24
Test name
Test status
Simulation time 336400210000 ps
CPU time 795.09 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 01:08:59 PM PDT 24
Peak memory 160696 kb
Host smart-87ab2d3b-e055-4c93-aa61-da898197bd29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4184237384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.4184237384
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2631330065
Short name T191
Test name
Test status
Simulation time 336778570000 ps
CPU time 762.47 seconds
Started Mar 31 12:36:57 PM PDT 24
Finished Mar 31 01:08:24 PM PDT 24
Peak memory 160716 kb
Host smart-f861ac2c-ed65-480a-82b7-338ea6c33a72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2631330065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2631330065
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3303243436
Short name T182
Test name
Test status
Simulation time 337141150000 ps
CPU time 853.81 seconds
Started Mar 31 12:36:59 PM PDT 24
Finished Mar 31 01:11:28 PM PDT 24
Peak memory 160720 kb
Host smart-8b92fc97-b4eb-4530-8983-4ee089e85c4a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3303243436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3303243436
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4254161703
Short name T199
Test name
Test status
Simulation time 336380630000 ps
CPU time 698.16 seconds
Started Mar 31 12:36:56 PM PDT 24
Finished Mar 31 01:05:19 PM PDT 24
Peak memory 160784 kb
Host smart-beb2ab69-c51a-46ec-ae4c-a9a1432fdc3a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4254161703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4254161703
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3928865507
Short name T181
Test name
Test status
Simulation time 336618750000 ps
CPU time 645.26 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 01:03:16 PM PDT 24
Peak memory 160692 kb
Host smart-ca2320eb-6604-4ed1-ae5f-bd6322880953
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3928865507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3928865507
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4191881765
Short name T167
Test name
Test status
Simulation time 336910130000 ps
CPU time 750.89 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:07:44 PM PDT 24
Peak memory 160772 kb
Host smart-4cadcd07-557c-4444-a889-a5f8d40f53a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4191881765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.4191881765
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1898372362
Short name T166
Test name
Test status
Simulation time 336975330000 ps
CPU time 866.72 seconds
Started Mar 31 12:37:12 PM PDT 24
Finished Mar 31 01:12:42 PM PDT 24
Peak memory 160792 kb
Host smart-9e241c45-4c94-4376-91d7-76707ffcb787
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1898372362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1898372362
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3359140
Short name T170
Test name
Test status
Simulation time 336753870000 ps
CPU time 829.12 seconds
Started Mar 31 12:36:46 PM PDT 24
Finished Mar 31 01:10:24 PM PDT 24
Peak memory 160760 kb
Host smart-a4d0c100-aac1-441d-9046-20688d237883
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3359140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3359140
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2066961868
Short name T26
Test name
Test status
Simulation time 336917510000 ps
CPU time 837.42 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:10:23 PM PDT 24
Peak memory 160784 kb
Host smart-b697764f-9ced-4c5a-a34e-4ac16bebc50c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2066961868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2066961868
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1430391058
Short name T196
Test name
Test status
Simulation time 336381950000 ps
CPU time 704.53 seconds
Started Mar 31 12:36:55 PM PDT 24
Finished Mar 31 01:06:20 PM PDT 24
Peak memory 160692 kb
Host smart-5216385f-cf05-4eb4-bff3-41d254b7e672
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1430391058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1430391058
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1072956386
Short name T29
Test name
Test status
Simulation time 336367870000 ps
CPU time 779.82 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 01:08:02 PM PDT 24
Peak memory 160792 kb
Host smart-598fff9c-9e05-439f-a710-ecb160df9f7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1072956386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1072956386
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.721805328
Short name T165
Test name
Test status
Simulation time 336924510000 ps
CPU time 822.51 seconds
Started Mar 31 12:37:06 PM PDT 24
Finished Mar 31 01:10:45 PM PDT 24
Peak memory 160708 kb
Host smart-5441b26c-480e-4aee-b76d-4661bdb204db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=721805328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.721805328
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1036014937
Short name T195
Test name
Test status
Simulation time 336566630000 ps
CPU time 761.96 seconds
Started Mar 31 12:36:41 PM PDT 24
Finished Mar 31 01:08:07 PM PDT 24
Peak memory 160796 kb
Host smart-7ce8fd73-5df4-4b24-95b4-bba9e6291814
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1036014937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1036014937
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1250348899
Short name T162
Test name
Test status
Simulation time 336763350000 ps
CPU time 753.81 seconds
Started Mar 31 12:37:04 PM PDT 24
Finished Mar 31 01:07:55 PM PDT 24
Peak memory 160720 kb
Host smart-b8ce3038-6379-4173-a6d9-76f48fb8454d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1250348899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1250348899
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1657325657
Short name T168
Test name
Test status
Simulation time 336512830000 ps
CPU time 758 seconds
Started Mar 31 12:36:41 PM PDT 24
Finished Mar 31 01:07:27 PM PDT 24
Peak memory 160748 kb
Host smart-54c6d23b-e0de-4f65-b20e-c5d4750f3c7a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1657325657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1657325657
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3901099623
Short name T173
Test name
Test status
Simulation time 336771290000 ps
CPU time 872.64 seconds
Started Mar 31 12:37:00 PM PDT 24
Finished Mar 31 01:12:21 PM PDT 24
Peak memory 160716 kb
Host smart-9a7bf654-cf82-4ee5-b175-abc69d8183d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3901099623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3901099623
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2843571888
Short name T193
Test name
Test status
Simulation time 336897390000 ps
CPU time 870.83 seconds
Started Mar 31 12:37:06 PM PDT 24
Finished Mar 31 01:13:05 PM PDT 24
Peak memory 160720 kb
Host smart-5840b8e7-3a8f-4439-a898-115fbcd4fada
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2843571888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2843571888
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1261990227
Short name T174
Test name
Test status
Simulation time 336718710000 ps
CPU time 726.54 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 01:06:25 PM PDT 24
Peak memory 160684 kb
Host smart-3a4919e7-70fd-48cb-99e2-0d16edd90d54
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1261990227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1261990227
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2806557784
Short name T188
Test name
Test status
Simulation time 336415930000 ps
CPU time 797.01 seconds
Started Mar 31 12:36:46 PM PDT 24
Finished Mar 31 01:09:01 PM PDT 24
Peak memory 160692 kb
Host smart-47486dc4-fc81-4270-a00e-0283bc39d912
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2806557784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2806557784
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.142177557
Short name T197
Test name
Test status
Simulation time 337080970000 ps
CPU time 844.57 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 01:11:17 PM PDT 24
Peak memory 160712 kb
Host smart-e439809b-4193-44af-a006-8942da6df82a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=142177557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.142177557
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3211313918
Short name T169
Test name
Test status
Simulation time 336470890000 ps
CPU time 641.47 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 01:03:15 PM PDT 24
Peak memory 160680 kb
Host smart-5ac8b385-0a2c-4176-892d-0324ae501bef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3211313918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3211313918
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.140548616
Short name T27
Test name
Test status
Simulation time 337171830000 ps
CPU time 828.63 seconds
Started Mar 31 12:37:21 PM PDT 24
Finished Mar 31 01:11:30 PM PDT 24
Peak memory 160796 kb
Host smart-6c7e5124-c108-40d3-addc-652d113ff8bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=140548616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.140548616
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2814598363
Short name T151
Test name
Test status
Simulation time 1484330000 ps
CPU time 5.25 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164816 kb
Host smart-4f4909f2-b360-4d3e-a4fe-a3c1c27f06cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814598363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2814598363
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2825708544
Short name T140
Test name
Test status
Simulation time 1325090000 ps
CPU time 3.95 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164892 kb
Host smart-6e787566-203c-426e-b1d6-fffad812fc08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2825708544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2825708544
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4279822215
Short name T133
Test name
Test status
Simulation time 1408150000 ps
CPU time 4.49 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164852 kb
Host smart-da4f6b17-afb5-4eca-9b31-2485e4a7437f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4279822215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4279822215
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.867201742
Short name T149
Test name
Test status
Simulation time 1310570000 ps
CPU time 3.07 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164904 kb
Host smart-e8990e49-f52e-4bd4-b6d2-c51bb95e6aa1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=867201742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.867201742
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1110946366
Short name T155
Test name
Test status
Simulation time 1455390000 ps
CPU time 3.63 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164920 kb
Host smart-3994950a-b088-4ec1-a96f-29e3dbfe9ebe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1110946366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1110946366
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2340788847
Short name T146
Test name
Test status
Simulation time 1493010000 ps
CPU time 5.37 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 164868 kb
Host smart-f66ab764-8906-4b9b-9f9d-3bdb61556113
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2340788847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2340788847
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2178424260
Short name T128
Test name
Test status
Simulation time 1524730000 ps
CPU time 5.09 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164872 kb
Host smart-2477c766-8c95-41f2-b442-e3e37e331add
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2178424260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2178424260
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3909163054
Short name T126
Test name
Test status
Simulation time 1528530000 ps
CPU time 5.19 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:48 PM PDT 24
Peak memory 164872 kb
Host smart-ae3181da-700e-47d5-87fe-cfae2e9a9c6c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909163054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3909163054
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1057180811
Short name T130
Test name
Test status
Simulation time 1529610000 ps
CPU time 3.35 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164872 kb
Host smart-9d4c1318-9f8b-4047-828e-035ce90c671e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1057180811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1057180811
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2192699633
Short name T117
Test name
Test status
Simulation time 1416050000 ps
CPU time 5.09 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164872 kb
Host smart-9951d850-a4e0-4e8b-80c1-836066d27f97
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2192699633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2192699633
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2650716191
Short name T125
Test name
Test status
Simulation time 1416450000 ps
CPU time 3.49 seconds
Started Mar 31 12:36:53 PM PDT 24
Finished Mar 31 12:37:01 PM PDT 24
Peak memory 164828 kb
Host smart-a2ad4ee1-b6a6-450d-a356-2abd5bc19a61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2650716191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2650716191
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3684411041
Short name T121
Test name
Test status
Simulation time 1519230000 ps
CPU time 5.1 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164872 kb
Host smart-df6d5d71-4709-4ae4-9fd0-cd87d44f1bf3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684411041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3684411041
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2113116865
Short name T159
Test name
Test status
Simulation time 1351350000 ps
CPU time 3.77 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 164824 kb
Host smart-89c9ea20-ac3a-4696-bffe-5fae4d45a6c5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2113116865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2113116865
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.210801685
Short name T150
Test name
Test status
Simulation time 1426610000 ps
CPU time 4.35 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164808 kb
Host smart-98f0fe66-9dbe-44a9-95a4-819f3cecb547
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=210801685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.210801685
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3014023966
Short name T116
Test name
Test status
Simulation time 1497490000 ps
CPU time 5.19 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164872 kb
Host smart-b9ddaf99-b061-469c-8b0b-c3ee44edb7a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3014023966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3014023966
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3112729472
Short name T153
Test name
Test status
Simulation time 1518390000 ps
CPU time 4.46 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164952 kb
Host smart-d17885f9-da74-462f-8388-ebd55dcb8736
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3112729472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3112729472
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4184845406
Short name T157
Test name
Test status
Simulation time 1564650000 ps
CPU time 4.06 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164832 kb
Host smart-06872d2d-abb5-47ae-af90-7887e6d102be
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4184845406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.4184845406
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2773591708
Short name T137
Test name
Test status
Simulation time 1102390000 ps
CPU time 3.46 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164952 kb
Host smart-d7bd2d25-e479-47f5-a412-d18e3179f9d7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773591708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2773591708
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2993889184
Short name T145
Test name
Test status
Simulation time 1493530000 ps
CPU time 3.75 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164832 kb
Host smart-0bf787a1-2e70-4e95-b4e1-00b56662f886
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2993889184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2993889184
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1484700020
Short name T154
Test name
Test status
Simulation time 1323450000 ps
CPU time 4.2 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164952 kb
Host smart-c057165e-56bc-4193-a21f-acf59d671ee9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1484700020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1484700020
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.279840770
Short name T118
Test name
Test status
Simulation time 1531030000 ps
CPU time 4.36 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164872 kb
Host smart-92b386ef-178b-461f-8f3d-7d11f0b76b0d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=279840770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.279840770
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1076604421
Short name T147
Test name
Test status
Simulation time 1427670000 ps
CPU time 4.36 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164952 kb
Host smart-6c9070ba-19ea-430f-8e23-53c898a201ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076604421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1076604421
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2825100914
Short name T160
Test name
Test status
Simulation time 1407430000 ps
CPU time 4.3 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164952 kb
Host smart-5ddf8157-3cb0-4784-9658-90cde6a35815
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2825100914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2825100914
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3693700639
Short name T148
Test name
Test status
Simulation time 1570350000 ps
CPU time 4.67 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164860 kb
Host smart-1d1763bc-3c3b-46b7-bb50-2a0068a9bac1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3693700639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3693700639
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1111855900
Short name T113
Test name
Test status
Simulation time 1411390000 ps
CPU time 4.45 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164952 kb
Host smart-c029711f-ba5b-42a8-bd9f-80f2770764cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1111855900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1111855900
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2211032943
Short name T156
Test name
Test status
Simulation time 1503790000 ps
CPU time 4.47 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164952 kb
Host smart-76787580-5801-4451-b908-b285c93af5ba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2211032943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2211032943
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2863764148
Short name T144
Test name
Test status
Simulation time 1452970000 ps
CPU time 3.67 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:38 PM PDT 24
Peak memory 164868 kb
Host smart-c2383c6a-384b-482c-9e1f-a0b8ae63f243
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2863764148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2863764148
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1992041223
Short name T112
Test name
Test status
Simulation time 1596130000 ps
CPU time 4.83 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164852 kb
Host smart-22c1ac37-8dc3-4e6a-934c-a4be6fededec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992041223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1992041223
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.456639283
Short name T158
Test name
Test status
Simulation time 1492550000 ps
CPU time 4.9 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164884 kb
Host smart-343cba34-e8f5-4eb8-8bab-749dc044e0f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=456639283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.456639283
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.109794817
Short name T127
Test name
Test status
Simulation time 1372810000 ps
CPU time 4.12 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164892 kb
Host smart-fd13a3ac-da53-40b0-b7cb-5cf83cdb9082
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=109794817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.109794817
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.918255941
Short name T119
Test name
Test status
Simulation time 1560630000 ps
CPU time 3.66 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:49 PM PDT 24
Peak memory 164896 kb
Host smart-5ccb528f-8aed-4166-88d4-2c8ae31b09c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=918255941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.918255941
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1552215576
Short name T143
Test name
Test status
Simulation time 1576290000 ps
CPU time 4.03 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164848 kb
Host smart-ff5bac39-6989-4f0c-97ec-531541a666f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1552215576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1552215576
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2971731670
Short name T114
Test name
Test status
Simulation time 1476610000 ps
CPU time 3.41 seconds
Started Mar 31 12:36:31 PM PDT 24
Finished Mar 31 12:36:39 PM PDT 24
Peak memory 164892 kb
Host smart-92ec9a18-244d-4050-9863-d60b004c3835
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2971731670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2971731670
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1373831532
Short name T122
Test name
Test status
Simulation time 1647750000 ps
CPU time 4.98 seconds
Started Mar 31 12:36:31 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164924 kb
Host smart-39278788-6a37-446b-a474-1a9c773f3056
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1373831532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1373831532
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3219252791
Short name T115
Test name
Test status
Simulation time 1532730000 ps
CPU time 4.32 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164808 kb
Host smart-b1bb6c8d-6422-4d00-af3d-3b7fa229a0a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3219252791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3219252791
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3668851261
Short name T132
Test name
Test status
Simulation time 1276850000 ps
CPU time 3.03 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 12:36:48 PM PDT 24
Peak memory 164856 kb
Host smart-e5f31b66-71c0-4ede-9905-84cbbeb4e2bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668851261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3668851261
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1141477543
Short name T138
Test name
Test status
Simulation time 1569510000 ps
CPU time 4.08 seconds
Started Mar 31 12:36:44 PM PDT 24
Finished Mar 31 12:36:53 PM PDT 24
Peak memory 164848 kb
Host smart-c78f24f4-4a5c-431d-81fa-53e760bff2b0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1141477543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1141477543
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3078411400
Short name T120
Test name
Test status
Simulation time 1285010000 ps
CPU time 3.73 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 164828 kb
Host smart-82ddcb66-79e1-462a-9b4b-c60e4e3e9e81
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078411400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3078411400
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.518018829
Short name T142
Test name
Test status
Simulation time 1613050000 ps
CPU time 4.19 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 164860 kb
Host smart-2c1e4e03-47f7-4dee-b886-553b820c4285
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518018829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.518018829
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3777556391
Short name T136
Test name
Test status
Simulation time 1515730000 ps
CPU time 4.44 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164856 kb
Host smart-9bca4d7f-982f-4d8f-9e30-2b7eb88c661d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3777556391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3777556391
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3301124938
Short name T152
Test name
Test status
Simulation time 1288730000 ps
CPU time 3.98 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164864 kb
Host smart-c0fe8977-a93e-4eae-9385-6db1f7b3717c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3301124938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3301124938
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1544989334
Short name T135
Test name
Test status
Simulation time 1596850000 ps
CPU time 3.2 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 164896 kb
Host smart-fe74a8b7-d19f-4d5c-b850-4f89a1402b0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1544989334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1544989334
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4221567277
Short name T141
Test name
Test status
Simulation time 1411790000 ps
CPU time 4.34 seconds
Started Mar 31 12:36:48 PM PDT 24
Finished Mar 31 12:36:58 PM PDT 24
Peak memory 164832 kb
Host smart-fabf3983-bc5c-4b0f-af86-b36d5b4d4688
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221567277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.4221567277
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.749953880
Short name T129
Test name
Test status
Simulation time 1459650000 ps
CPU time 4.54 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 12:36:52 PM PDT 24
Peak memory 164812 kb
Host smart-8fa7ff25-9f2f-48ff-9c55-f066d756cbbc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749953880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.749953880
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2946861389
Short name T111
Test name
Test status
Simulation time 1458590000 ps
CPU time 3.6 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164860 kb
Host smart-23358914-7b92-4ceb-b719-0ec263cea7ea
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2946861389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2946861389
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4205913850
Short name T139
Test name
Test status
Simulation time 1583970000 ps
CPU time 3.89 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 164920 kb
Host smart-58b73be4-81d4-4a6b-978e-932c38b92bcc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205913850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.4205913850
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.550957770
Short name T123
Test name
Test status
Simulation time 1527310000 ps
CPU time 5.29 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164816 kb
Host smart-8c2d7099-f1a5-4364-ba35-361426cff9cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=550957770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.550957770
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3305499475
Short name T134
Test name
Test status
Simulation time 1531630000 ps
CPU time 4.13 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 164892 kb
Host smart-543f1b6a-d78d-4a17-9155-e0015b8de37e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305499475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3305499475
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2782434643
Short name T124
Test name
Test status
Simulation time 1603630000 ps
CPU time 4.62 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164860 kb
Host smart-6b90432f-2015-48eb-9779-b9e046725dc2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2782434643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2782434643
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2375679774
Short name T131
Test name
Test status
Simulation time 1430170000 ps
CPU time 4.77 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164852 kb
Host smart-66efc1b2-dab4-4e1b-8939-39738f8a6ed9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2375679774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2375679774
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2059320588
Short name T49
Test name
Test status
Simulation time 1305670000 ps
CPU time 3.88 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 164824 kb
Host smart-755c7004-156f-4b1f-b5f7-494da6a0eff8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059320588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2059320588
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2078525261
Short name T47
Test name
Test status
Simulation time 1524210000 ps
CPU time 4.06 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164908 kb
Host smart-546471be-9c95-43f5-a038-dc50dfcd7521
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2078525261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2078525261
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3089523892
Short name T52
Test name
Test status
Simulation time 1456250000 ps
CPU time 3.72 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164992 kb
Host smart-d5e8880c-f28d-4cbf-8992-faba32c44d76
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3089523892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3089523892
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1395990708
Short name T1
Test name
Test status
Simulation time 1592650000 ps
CPU time 3.56 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164832 kb
Host smart-38444dd8-710e-4687-b777-7500645f0b47
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1395990708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1395990708
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.194464399
Short name T57
Test name
Test status
Simulation time 1419430000 ps
CPU time 3.77 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 164860 kb
Host smart-23fcfdcf-f137-49e6-a352-fe7463446aad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=194464399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.194464399
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3558711629
Short name T12
Test name
Test status
Simulation time 1477210000 ps
CPU time 3.77 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164900 kb
Host smart-a8669f34-8bee-4e88-8b46-15d44705bbaf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558711629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3558711629
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2274017142
Short name T32
Test name
Test status
Simulation time 1542630000 ps
CPU time 4.09 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 164936 kb
Host smart-386db9c2-88c2-4245-8d99-40f23397611c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274017142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2274017142
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3268197580
Short name T38
Test name
Test status
Simulation time 1491110000 ps
CPU time 4.43 seconds
Started Mar 31 12:36:26 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 164836 kb
Host smart-83adaad3-02b9-4e86-8618-b0c370508134
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3268197580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3268197580
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3373074818
Short name T40
Test name
Test status
Simulation time 1484430000 ps
CPU time 3.58 seconds
Started Mar 31 12:36:26 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 164948 kb
Host smart-22328b2c-af7b-4ff9-9641-ca9625a0bc6e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373074818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3373074818
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2455919878
Short name T63
Test name
Test status
Simulation time 1516170000 ps
CPU time 3.7 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164816 kb
Host smart-bb5ab4bf-89b1-4a36-9e98-dbbde6793559
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2455919878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2455919878
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1316982488
Short name T44
Test name
Test status
Simulation time 1379210000 ps
CPU time 4.53 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164848 kb
Host smart-93198048-d68f-4ef9-9bfa-5562614536f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1316982488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1316982488
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4069539080
Short name T37
Test name
Test status
Simulation time 1456070000 ps
CPU time 5.43 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:39 PM PDT 24
Peak memory 164880 kb
Host smart-46cc3cdb-f7d6-4e31-a4d7-257c50782df8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069539080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4069539080
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.50897398
Short name T56
Test name
Test status
Simulation time 1115990000 ps
CPU time 2.99 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:39 PM PDT 24
Peak memory 164956 kb
Host smart-dc1f2e4e-52d1-4b1e-8a51-385c5087343b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=50897398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.50897398
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.435501396
Short name T53
Test name
Test status
Simulation time 1359930000 ps
CPU time 4.39 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164820 kb
Host smart-3ba69b30-bcc3-458a-b4b0-6d8dffdcd381
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=435501396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.435501396
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.341787456
Short name T62
Test name
Test status
Simulation time 1280170000 ps
CPU time 3.22 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164900 kb
Host smart-5631d0e2-c2e9-45e5-83cd-501fcee0a6d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=341787456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.341787456
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.119349489
Short name T39
Test name
Test status
Simulation time 1441050000 ps
CPU time 3.51 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 164864 kb
Host smart-40b4f9b2-d59c-4437-811b-0bd21821a5a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=119349489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.119349489
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2079047179
Short name T48
Test name
Test status
Simulation time 1380590000 ps
CPU time 3.72 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164892 kb
Host smart-e0030728-27b1-4bd4-a00a-c154d4998567
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2079047179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2079047179
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1989244744
Short name T35
Test name
Test status
Simulation time 1454910000 ps
CPU time 5.35 seconds
Started Mar 31 12:36:26 PM PDT 24
Finished Mar 31 12:36:38 PM PDT 24
Peak memory 164936 kb
Host smart-9971992d-57a6-4c40-95c2-c52f951df4fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1989244744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1989244744
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4047473794
Short name T33
Test name
Test status
Simulation time 1473530000 ps
CPU time 4.86 seconds
Started Mar 31 12:36:26 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 164924 kb
Host smart-3e967920-ee1e-4f44-812d-ef6ce03f1d82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4047473794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4047473794
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4085970590
Short name T54
Test name
Test status
Simulation time 1455690000 ps
CPU time 4.02 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164888 kb
Host smart-9503d688-9bf5-47e6-a479-7d9215f7a116
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4085970590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4085970590
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.72172021
Short name T61
Test name
Test status
Simulation time 1517230000 ps
CPU time 4.62 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 164804 kb
Host smart-f0e3c021-0fae-4c12-a0bb-acb721f0f583
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=72172021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.72172021
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4234857088
Short name T58
Test name
Test status
Simulation time 1535690000 ps
CPU time 3.81 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164908 kb
Host smart-abc9bb4c-80ae-43c6-8de0-032abfc1af32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4234857088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.4234857088
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2139081710
Short name T2
Test name
Test status
Simulation time 1459230000 ps
CPU time 4.08 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 12:36:51 PM PDT 24
Peak memory 164820 kb
Host smart-8dc1b956-19bf-4c02-8c3d-3470775464d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2139081710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2139081710
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4200764764
Short name T69
Test name
Test status
Simulation time 1535210000 ps
CPU time 4.26 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 12:36:48 PM PDT 24
Peak memory 164816 kb
Host smart-4e6ac85c-30d5-45b0-b3b9-0f01ed4484ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4200764764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.4200764764
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.559070392
Short name T51
Test name
Test status
Simulation time 1396950000 ps
CPU time 3.85 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 164880 kb
Host smart-7d8aba8b-7439-41f2-9e80-ff9aecfd5ec9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=559070392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.559070392
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.105546932
Short name T7
Test name
Test status
Simulation time 1383050000 ps
CPU time 3.46 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164912 kb
Host smart-4998f7c7-47f3-4a75-a08e-952d1f11397d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=105546932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.105546932
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4246933976
Short name T65
Test name
Test status
Simulation time 1444070000 ps
CPU time 6.21 seconds
Started Mar 31 12:36:42 PM PDT 24
Finished Mar 31 12:36:55 PM PDT 24
Peak memory 164848 kb
Host smart-d0dde162-c05e-4d17-a585-09faddabcaf5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4246933976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4246933976
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.512449497
Short name T8
Test name
Test status
Simulation time 1261410000 ps
CPU time 4.55 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164816 kb
Host smart-3edc11e4-cb5c-44af-969d-58612a2a9708
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512449497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.512449497
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1640571879
Short name T43
Test name
Test status
Simulation time 1471350000 ps
CPU time 3.68 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 164808 kb
Host smart-a9e425a5-a1c6-4c51-aa0f-54067c1d7d7b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1640571879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1640571879
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.205806115
Short name T45
Test name
Test status
Simulation time 1357350000 ps
CPU time 4.18 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 164892 kb
Host smart-7367ccf4-4ae1-4417-a193-3906d1466bf4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=205806115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.205806115
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1562365687
Short name T41
Test name
Test status
Simulation time 1549330000 ps
CPU time 4.96 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164876 kb
Host smart-744f95d6-4c70-4c44-8dac-88f9d14e11b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1562365687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1562365687
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3964280551
Short name T3
Test name
Test status
Simulation time 1371850000 ps
CPU time 3.16 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164832 kb
Host smart-02b11321-39a0-446c-9c65-98d0a4f3971e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3964280551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3964280551
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3000904394
Short name T10
Test name
Test status
Simulation time 1092170000 ps
CPU time 3.28 seconds
Started Mar 31 12:36:25 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 164852 kb
Host smart-5bc391c4-919d-4ee6-9d4b-a2bd54202ec4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3000904394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3000904394
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.342961305
Short name T34
Test name
Test status
Simulation time 1498090000 ps
CPU time 3.93 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 164880 kb
Host smart-be3242c7-ed0e-44cc-a144-6f9b9b61f96c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=342961305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.342961305
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2445564657
Short name T50
Test name
Test status
Simulation time 1531430000 ps
CPU time 4.26 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 164892 kb
Host smart-74c89203-515a-4b28-b65f-1fabf9d919e6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2445564657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2445564657
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1864307114
Short name T67
Test name
Test status
Simulation time 1204470000 ps
CPU time 3.55 seconds
Started Mar 31 12:36:29 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 164892 kb
Host smart-2c8479e6-c70e-4e47-a1fa-9a931750f330
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1864307114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1864307114
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1215636686
Short name T31
Test name
Test status
Simulation time 1426510000 ps
CPU time 5.34 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 164812 kb
Host smart-944127a1-ddb2-434c-a9ca-c489db9efbe8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1215636686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1215636686
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3725291193
Short name T55
Test name
Test status
Simulation time 1535790000 ps
CPU time 3.3 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164896 kb
Host smart-ad74b488-c4bb-492d-bbf1-abe1604f64b1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3725291193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3725291193
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1160904313
Short name T42
Test name
Test status
Simulation time 1419070000 ps
CPU time 4.21 seconds
Started Mar 31 12:36:29 PM PDT 24
Finished Mar 31 12:36:39 PM PDT 24
Peak memory 164892 kb
Host smart-95b1abd0-e1ed-4a34-a2ac-f3658e43dce0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1160904313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1160904313
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1027634364
Short name T70
Test name
Test status
Simulation time 1405630000 ps
CPU time 3.13 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164908 kb
Host smart-f3329ef7-7057-4fc3-9737-cbdcc64a2aad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1027634364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1027634364
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.657559859
Short name T68
Test name
Test status
Simulation time 1435750000 ps
CPU time 4.68 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164820 kb
Host smart-4dee9ef5-70d8-47d6-8caf-86179b2c4abb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=657559859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.657559859
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3964244353
Short name T64
Test name
Test status
Simulation time 1399270000 ps
CPU time 3.62 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 164904 kb
Host smart-5ef889be-5409-40cb-8cb6-26513b54e459
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3964244353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3964244353
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.760039492
Short name T46
Test name
Test status
Simulation time 1513070000 ps
CPU time 4.92 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164820 kb
Host smart-a0d80264-86ed-4906-af1c-465e48dd0a1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=760039492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.760039492
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1739506772
Short name T36
Test name
Test status
Simulation time 1313850000 ps
CPU time 3.36 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:47 PM PDT 24
Peak memory 164904 kb
Host smart-11d03bfa-e3bf-4a3a-b7c8-ae49930a5ae1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1739506772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1739506772
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2114191030
Short name T60
Test name
Test status
Simulation time 1555230000 ps
CPU time 4.41 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 164804 kb
Host smart-4279c0cc-bdae-473d-84a6-f5353a73959b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2114191030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2114191030
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1331464032
Short name T59
Test name
Test status
Simulation time 1381510000 ps
CPU time 4.07 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 164824 kb
Host smart-3c8afcc1-8a84-452c-805e-b4cbfdfb423b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331464032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1331464032
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1866836991
Short name T9
Test name
Test status
Simulation time 1468390000 ps
CPU time 4.51 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:38 PM PDT 24
Peak memory 164788 kb
Host smart-3d66fc02-575f-4387-bb93-00096989d860
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866836991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1866836991
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1077577587
Short name T13
Test name
Test status
Simulation time 1574270000 ps
CPU time 3.83 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 164900 kb
Host smart-08009664-2b6d-42d5-86e7-4fde9db70cfe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077577587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1077577587
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3954763853
Short name T66
Test name
Test status
Simulation time 1571190000 ps
CPU time 4.78 seconds
Started Mar 31 12:36:43 PM PDT 24
Finished Mar 31 12:36:54 PM PDT 24
Peak memory 164864 kb
Host smart-2e303f08-b41f-492d-a236-5c6ee8ba6d81
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3954763853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3954763853
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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