| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2563651245 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.778419638 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2931325045 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.159619031 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2914989748 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.180850543 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1989221402 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2375402330 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1935608175 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.77406260 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.579686633 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3947524545 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1530299914 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3496940766 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2945637226 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2386736105 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2775201372 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2874033096 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2056501987 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.394460477 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1228355526 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.72965984 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3487429164 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4020855090 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4074945558 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1791870655 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3472571931 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1049265004 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4194190718 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1794250982 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3628724679 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2776509404 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1617336782 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4173806727 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.389067249 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1189157533 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3091659553 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.172780597 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.777486695 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3079495515 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1603222549 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3903278243 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1745922177 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.829819837 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.919615910 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1358308248 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1707878552 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2220143750 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1878078684 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.438562489 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2748830522 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1493000662 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.797285634 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1607345813 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3811397606 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2963083495 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3920670508 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2587274146 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3469084929 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1251568744 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2061077878 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2582274159 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2641581258 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.663102404 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3036222214 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2209876399 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3192969904 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3712445839 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3707326423 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.351329345 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2835983166 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.259433577 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2412957028 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3186530634 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2547290098 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.582910676 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4204004214 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3495150159 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.752928605 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3572807682 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1506641465 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1907001006 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.187062575 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2309722643 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3913144579 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.772461701 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2440706395 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2465947331 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3049397173 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1787698876 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3161733593 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3789719130 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3016633531 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4277333871 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3833168974 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.139898486 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1157885946 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3053436628 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3339450183 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1945275889 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3694671060 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1457213121 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1612491708 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2245388189 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3664890087 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3780569630 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3356002115 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.261000421 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2187929464 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3928489826 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4059220122 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3742361580 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1013574945 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3671707247 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1167402962 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4168709587 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1510954963 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2384503601 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2339145501 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4263486462 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3779266510 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3209438899 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3408209157 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.93345964 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2492555125 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.824386819 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1725971032 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.700029139 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3903959115 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2058743349 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3914995273 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2127117952 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3568484525 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.945882262 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.193961420 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3740015722 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1260704609 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1760849456 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4118328422 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1885830371 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1220053781 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4207518081 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.546795471 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2645484764 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2936641753 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.283662007 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.655151645 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.988612552 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3214429839 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.833720080 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1229295416 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1406926506 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2536162019 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.998127557 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4057517194 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1847086495 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2557888489 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2109323855 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.931470058 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3890009159 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.708354420 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1701322408 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3401496406 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1175081521 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.834856719 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.260758832 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.715935043 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1877964162 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1840390140 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4248967407 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4201276181 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2384299872 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3873283871 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4183130175 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4144999835 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1456447989 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4001481529 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.700430334 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4045908322 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.627179099 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1198342527 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3329258053 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2949584264 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2491323024 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.424184123 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2032340134 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3758313471 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.29053622 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.18566902 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3074895088 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4253631765 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4090144311 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.417049342 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1842611523 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.10809229 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1189998712 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.438150533 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4146888979 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1311054851 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2928959863 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1840390140 | Apr 28 02:56:41 PM PDT 24 | Apr 28 02:56:50 PM PDT 24 | 1402850000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4201276181 | Apr 28 02:56:40 PM PDT 24 | Apr 28 02:56:48 PM PDT 24 | 1478710000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2032340134 | Apr 28 02:56:44 PM PDT 24 | Apr 28 02:56:53 PM PDT 24 | 1543870000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2557888489 | Apr 28 02:56:42 PM PDT 24 | Apr 28 02:56:51 PM PDT 24 | 1419790000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.29053622 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:53 PM PDT 24 | 1268010000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.424184123 | Apr 28 02:56:38 PM PDT 24 | Apr 28 02:56:49 PM PDT 24 | 1483050000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.998127557 | Apr 28 02:56:41 PM PDT 24 | Apr 28 02:56:50 PM PDT 24 | 1309830000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2563651245 | Apr 28 02:56:36 PM PDT 24 | Apr 28 02:56:48 PM PDT 24 | 1561830000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.700430334 | Apr 28 02:56:47 PM PDT 24 | Apr 28 02:56:59 PM PDT 24 | 1580530000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3074895088 | Apr 28 02:56:46 PM PDT 24 | Apr 28 02:56:56 PM PDT 24 | 1483590000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2928959863 | Apr 28 02:56:38 PM PDT 24 | Apr 28 02:56:48 PM PDT 24 | 1348410000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1877964162 | Apr 28 02:56:43 PM PDT 24 | Apr 28 02:56:55 PM PDT 24 | 1544390000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4253631765 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:53 PM PDT 24 | 1357330000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1842611523 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1429950000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4001481529 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:54 PM PDT 24 | 1320610000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4144999835 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:57 PM PDT 24 | 1511330000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2536162019 | Apr 28 02:56:49 PM PDT 24 | Apr 28 02:57:00 PM PDT 24 | 1487430000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.18566902 | Apr 28 02:56:46 PM PDT 24 | Apr 28 02:56:55 PM PDT 24 | 1442550000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.708354420 | Apr 28 02:56:41 PM PDT 24 | Apr 28 02:56:49 PM PDT 24 | 1248010000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1311054851 | Apr 28 02:56:39 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1622450000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3401496406 | Apr 28 02:56:35 PM PDT 24 | Apr 28 02:56:45 PM PDT 24 | 1474350000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1456447989 | Apr 28 02:56:47 PM PDT 24 | Apr 28 02:56:56 PM PDT 24 | 1321830000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2949584264 | Apr 28 02:56:46 PM PDT 24 | Apr 28 02:56:55 PM PDT 24 | 1572510000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.834856719 | Apr 28 02:56:43 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1130990000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4090144311 | Apr 28 02:56:49 PM PDT 24 | Apr 28 02:57:01 PM PDT 24 | 1547670000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1406926506 | Apr 28 02:56:35 PM PDT 24 | Apr 28 02:56:45 PM PDT 24 | 1564350000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2109323855 | Apr 28 02:56:43 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1415550000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3758313471 | Apr 28 02:56:46 PM PDT 24 | Apr 28 02:56:56 PM PDT 24 | 1428590000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4248967407 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:58 PM PDT 24 | 1434350000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4057517194 | Apr 28 02:56:49 PM PDT 24 | Apr 28 02:57:00 PM PDT 24 | 1424490000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.931470058 | Apr 28 02:56:40 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1396810000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1847086495 | Apr 28 02:56:43 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1407690000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.260758832 | Apr 28 02:56:43 PM PDT 24 | Apr 28 02:56:51 PM PDT 24 | 1119190000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.627179099 | Apr 28 02:56:44 PM PDT 24 | Apr 28 02:56:54 PM PDT 24 | 1549930000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2491323024 | Apr 28 02:56:47 PM PDT 24 | Apr 28 02:56:57 PM PDT 24 | 1478250000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1189998712 | Apr 28 02:56:38 PM PDT 24 | Apr 28 02:56:47 PM PDT 24 | 1328290000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4146888979 | Apr 28 02:56:35 PM PDT 24 | Apr 28 02:56:46 PM PDT 24 | 1506030000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.10809229 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:53 PM PDT 24 | 1437810000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1701322408 | Apr 28 02:56:43 PM PDT 24 | Apr 28 02:56:55 PM PDT 24 | 1552630000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.417049342 | Apr 28 02:56:49 PM PDT 24 | Apr 28 02:57:00 PM PDT 24 | 1548950000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.438150533 | Apr 28 02:56:36 PM PDT 24 | Apr 28 02:56:42 PM PDT 24 | 1253690000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1175081521 | Apr 28 02:56:40 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1498070000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3329258053 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:57 PM PDT 24 | 1207630000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1198342527 | Apr 28 02:56:47 PM PDT 24 | Apr 28 02:56:56 PM PDT 24 | 1324110000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3890009159 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:59 PM PDT 24 | 1557030000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3873283871 | Apr 28 02:56:49 PM PDT 24 | Apr 28 02:57:00 PM PDT 24 | 1496210000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4183130175 | Apr 28 02:56:35 PM PDT 24 | Apr 28 02:56:47 PM PDT 24 | 1313450000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2384299872 | Apr 28 02:56:40 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1555930000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4045908322 | Apr 28 02:56:45 PM PDT 24 | Apr 28 02:56:52 PM PDT 24 | 1428670000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.715935043 | Apr 28 02:56:41 PM PDT 24 | Apr 28 02:56:51 PM PDT 24 | 1389850000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4059220122 | Apr 28 12:28:16 PM PDT 24 | Apr 28 12:28:26 PM PDT 24 | 1553010000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1510954963 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:28:10 PM PDT 24 | 1394710000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3903959115 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:28:14 PM PDT 24 | 1378690000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3740015722 | Apr 28 12:27:53 PM PDT 24 | Apr 28 12:28:01 PM PDT 24 | 1500270000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4168709587 | Apr 28 12:28:07 PM PDT 24 | Apr 28 12:28:15 PM PDT 24 | 1470950000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.988612552 | Apr 28 12:28:11 PM PDT 24 | Apr 28 12:28:19 PM PDT 24 | 1481190000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4263486462 | Apr 28 12:28:10 PM PDT 24 | Apr 28 12:28:19 PM PDT 24 | 1280810000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1885830371 | Apr 28 12:27:56 PM PDT 24 | Apr 28 12:28:04 PM PDT 24 | 1383490000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2058743349 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:28:15 PM PDT 24 | 1555950000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.159619031 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:28:17 PM PDT 24 | 1559950000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.833720080 | Apr 28 12:27:46 PM PDT 24 | Apr 28 12:27:53 PM PDT 24 | 1498370000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.261000421 | Apr 28 12:28:07 PM PDT 24 | Apr 28 12:28:17 PM PDT 24 | 1444150000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3356002115 | Apr 28 12:27:48 PM PDT 24 | Apr 28 12:27:55 PM PDT 24 | 1499270000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3742361580 | Apr 28 12:28:11 PM PDT 24 | Apr 28 12:28:19 PM PDT 24 | 1512870000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3914995273 | Apr 28 12:28:12 PM PDT 24 | Apr 28 12:28:22 PM PDT 24 | 1464550000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2187929464 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:28:12 PM PDT 24 | 1438590000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1760849456 | Apr 28 12:27:42 PM PDT 24 | Apr 28 12:27:50 PM PDT 24 | 1542790000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.283662007 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:28:15 PM PDT 24 | 1584550000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.655151645 | Apr 28 12:27:57 PM PDT 24 | Apr 28 12:28:04 PM PDT 24 | 1308250000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1229295416 | Apr 28 12:28:01 PM PDT 24 | Apr 28 12:28:13 PM PDT 24 | 1550750000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1013574945 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:28:15 PM PDT 24 | 1438970000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.546795471 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:28:15 PM PDT 24 | 1547950000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1167402962 | Apr 28 12:28:00 PM PDT 24 | Apr 28 12:28:09 PM PDT 24 | 1337150000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.824386819 | Apr 28 12:27:46 PM PDT 24 | Apr 28 12:27:54 PM PDT 24 | 1441030000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3568484525 | Apr 28 12:28:00 PM PDT 24 | Apr 28 12:28:09 PM PDT 24 | 1428550000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3671707247 | Apr 28 12:27:59 PM PDT 24 | Apr 28 12:28:07 PM PDT 24 | 1538230000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2127117952 | Apr 28 12:28:00 PM PDT 24 | Apr 28 12:28:07 PM PDT 24 | 1127650000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3408209157 | Apr 28 12:27:57 PM PDT 24 | Apr 28 12:28:05 PM PDT 24 | 1480130000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2936641753 | Apr 28 12:27:54 PM PDT 24 | Apr 28 12:28:03 PM PDT 24 | 1507910000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1220053781 | Apr 28 12:28:03 PM PDT 24 | Apr 28 12:28:12 PM PDT 24 | 1528770000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3209438899 | Apr 28 12:28:08 PM PDT 24 | Apr 28 12:28:16 PM PDT 24 | 1539830000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1260704609 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:28:12 PM PDT 24 | 1532750000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1612491708 | Apr 28 12:27:55 PM PDT 24 | Apr 28 12:28:03 PM PDT 24 | 1465630000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4118328422 | Apr 28 12:28:10 PM PDT 24 | Apr 28 12:28:23 PM PDT 24 | 1526790000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.93345964 | Apr 28 12:27:51 PM PDT 24 | Apr 28 12:28:02 PM PDT 24 | 1564990000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2384503601 | Apr 28 12:28:18 PM PDT 24 | Apr 28 12:28:25 PM PDT 24 | 1213970000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.700029139 | Apr 28 12:28:06 PM PDT 24 | Apr 28 12:28:16 PM PDT 24 | 1471110000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1725971032 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:28:11 PM PDT 24 | 1494770000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3780569630 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:28:23 PM PDT 24 | 1305970000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2645484764 | Apr 28 12:28:01 PM PDT 24 | Apr 28 12:28:08 PM PDT 24 | 1383510000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3214429839 | Apr 28 12:28:12 PM PDT 24 | Apr 28 12:28:20 PM PDT 24 | 1569250000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3779266510 | Apr 28 12:28:11 PM PDT 24 | Apr 28 12:28:19 PM PDT 24 | 1447930000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2339145501 | Apr 28 12:28:12 PM PDT 24 | Apr 28 12:28:20 PM PDT 24 | 1149110000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.945882262 | Apr 28 12:28:10 PM PDT 24 | Apr 28 12:28:18 PM PDT 24 | 1533210000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.193961420 | Apr 28 12:27:58 PM PDT 24 | Apr 28 12:28:06 PM PDT 24 | 1419010000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2245388189 | Apr 28 12:27:59 PM PDT 24 | Apr 28 12:28:06 PM PDT 24 | 1365510000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2492555125 | Apr 28 12:28:19 PM PDT 24 | Apr 28 12:28:27 PM PDT 24 | 1472610000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4207518081 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:28:10 PM PDT 24 | 1455310000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3664890087 | Apr 28 12:28:01 PM PDT 24 | Apr 28 12:28:08 PM PDT 24 | 1061890000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3928489826 | Apr 28 12:27:56 PM PDT 24 | Apr 28 12:28:05 PM PDT 24 | 1528190000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2641581258 | Apr 28 12:28:35 PM PDT 24 | Apr 28 12:57:04 PM PDT 24 | 336390930000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4277333871 | Apr 28 12:28:10 PM PDT 24 | Apr 28 01:01:08 PM PDT 24 | 337045110000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.752928605 | Apr 28 12:28:06 PM PDT 24 | Apr 28 12:55:54 PM PDT 24 | 336612350000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3036222214 | Apr 28 12:28:14 PM PDT 24 | Apr 28 01:00:28 PM PDT 24 | 336521410000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4204004214 | Apr 28 12:28:14 PM PDT 24 | Apr 28 12:51:26 PM PDT 24 | 337128870000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2209876399 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:56:43 PM PDT 24 | 336378730000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1787698876 | Apr 28 12:28:18 PM PDT 24 | Apr 28 12:56:36 PM PDT 24 | 336327030000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3811397606 | Apr 28 12:28:23 PM PDT 24 | Apr 28 12:59:17 PM PDT 24 | 336697210000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.778419638 | Apr 28 12:27:50 PM PDT 24 | Apr 28 12:58:24 PM PDT 24 | 336554610000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2440706395 | Apr 28 12:28:01 PM PDT 24 | Apr 28 12:57:09 PM PDT 24 | 336978650000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3920670508 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:57:13 PM PDT 24 | 336460430000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3016633531 | Apr 28 12:28:16 PM PDT 24 | Apr 28 12:59:14 PM PDT 24 | 336711970000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.351329345 | Apr 28 12:28:13 PM PDT 24 | Apr 28 01:02:45 PM PDT 24 | 336836650000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.259433577 | Apr 28 12:28:01 PM PDT 24 | Apr 28 01:01:55 PM PDT 24 | 336974330000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3192969904 | Apr 28 12:28:21 PM PDT 24 | Apr 28 12:56:54 PM PDT 24 | 336867330000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3186530634 | Apr 28 12:28:04 PM PDT 24 | Apr 28 01:00:26 PM PDT 24 | 336981490000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1457213121 | Apr 28 12:28:03 PM PDT 24 | Apr 28 12:50:11 PM PDT 24 | 337052970000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1945275889 | Apr 28 12:27:55 PM PDT 24 | Apr 28 01:00:08 PM PDT 24 | 336646450000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3707326423 | Apr 28 12:28:04 PM PDT 24 | Apr 28 12:58:32 PM PDT 24 | 336382750000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.187062575 | Apr 28 12:28:00 PM PDT 24 | Apr 28 12:58:36 PM PDT 24 | 336694430000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2587274146 | Apr 28 12:28:18 PM PDT 24 | Apr 28 12:55:49 PM PDT 24 | 336964410000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.582910676 | Apr 28 12:28:06 PM PDT 24 | Apr 28 01:00:53 PM PDT 24 | 336644230000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1251568744 | Apr 28 12:28:12 PM PDT 24 | Apr 28 01:00:33 PM PDT 24 | 336428470000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3161733593 | Apr 28 12:28:15 PM PDT 24 | Apr 28 01:02:34 PM PDT 24 | 337098770000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3913144579 | Apr 28 12:28:15 PM PDT 24 | Apr 28 01:02:18 PM PDT 24 | 336871950000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3694671060 | Apr 28 12:28:07 PM PDT 24 | Apr 28 12:55:56 PM PDT 24 | 336966530000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3712445839 | Apr 28 12:28:04 PM PDT 24 | Apr 28 01:01:59 PM PDT 24 | 337012870000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3339450183 | Apr 28 12:28:07 PM PDT 24 | Apr 28 12:56:09 PM PDT 24 | 336448930000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1907001006 | Apr 28 12:28:10 PM PDT 24 | Apr 28 01:02:26 PM PDT 24 | 336377890000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.663102404 | Apr 28 12:28:06 PM PDT 24 | Apr 28 12:58:12 PM PDT 24 | 336430690000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1607345813 | Apr 28 12:27:57 PM PDT 24 | Apr 28 12:58:54 PM PDT 24 | 336575730000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.772461701 | Apr 28 12:28:10 PM PDT 24 | Apr 28 01:02:37 PM PDT 24 | 336630490000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3833168974 | Apr 28 12:28:18 PM PDT 24 | Apr 28 01:02:14 PM PDT 24 | 336658890000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2061077878 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:55:34 PM PDT 24 | 336932570000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2582274159 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:56:37 PM PDT 24 | 336421470000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2412957028 | Apr 28 12:28:12 PM PDT 24 | Apr 28 12:56:56 PM PDT 24 | 336362130000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1157885946 | Apr 28 12:28:07 PM PDT 24 | Apr 28 12:54:57 PM PDT 24 | 336411550000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3049397173 | Apr 28 12:28:14 PM PDT 24 | Apr 28 12:56:30 PM PDT 24 | 336543310000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3789719130 | Apr 28 12:28:22 PM PDT 24 | Apr 28 12:58:26 PM PDT 24 | 337081290000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2465947331 | Apr 28 12:28:13 PM PDT 24 | Apr 28 12:58:15 PM PDT 24 | 337055890000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.139898486 | Apr 28 12:28:08 PM PDT 24 | Apr 28 12:58:17 PM PDT 24 | 337067690000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2309722643 | Apr 28 12:28:26 PM PDT 24 | Apr 28 01:02:39 PM PDT 24 | 336503310000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2963083495 | Apr 28 12:28:06 PM PDT 24 | Apr 28 01:00:54 PM PDT 24 | 336301390000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2547290098 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:59:21 PM PDT 24 | 336844270000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3495150159 | Apr 28 12:28:12 PM PDT 24 | Apr 28 12:57:54 PM PDT 24 | 336415970000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3572807682 | Apr 28 12:28:18 PM PDT 24 | Apr 28 01:02:04 PM PDT 24 | 336415070000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2835983166 | Apr 28 12:28:10 PM PDT 24 | Apr 28 01:02:32 PM PDT 24 | 336907590000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1506641465 | Apr 28 12:28:05 PM PDT 24 | Apr 28 12:57:16 PM PDT 24 | 336594290000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3053436628 | Apr 28 12:28:14 PM PDT 24 | Apr 28 12:55:00 PM PDT 24 | 337057950000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3469084929 | Apr 28 12:28:16 PM PDT 24 | Apr 28 12:58:29 PM PDT 24 | 336385310000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1228355526 | Apr 28 12:28:15 PM PDT 24 | Apr 28 01:02:31 PM PDT 24 | 336961150000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.438562489 | Apr 28 12:28:26 PM PDT 24 | Apr 28 01:02:04 PM PDT 24 | 336715590000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.919615910 | Apr 28 12:28:29 PM PDT 24 | Apr 28 12:59:43 PM PDT 24 | 336861890000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3496940766 | Apr 28 12:28:09 PM PDT 24 | Apr 28 12:56:23 PM PDT 24 | 336871130000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1530299914 | Apr 28 12:28:13 PM PDT 24 | Apr 28 01:00:41 PM PDT 24 | 337186610000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.389067249 | Apr 28 12:28:15 PM PDT 24 | Apr 28 01:02:02 PM PDT 24 | 336526530000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2874033096 | Apr 28 12:28:29 PM PDT 24 | Apr 28 12:56:55 PM PDT 24 | 337023570000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3487429164 | Apr 28 12:28:20 PM PDT 24 | Apr 28 01:01:22 PM PDT 24 | 336510470000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2931325045 | Apr 28 12:28:19 PM PDT 24 | Apr 28 01:02:43 PM PDT 24 | 336931650000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3628724679 | Apr 28 12:28:25 PM PDT 24 | Apr 28 12:57:21 PM PDT 24 | 336560470000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1049265004 | Apr 28 12:28:33 PM PDT 24 | Apr 28 12:58:44 PM PDT 24 | 336569230000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.394460477 | Apr 28 12:28:01 PM PDT 24 | Apr 28 12:57:34 PM PDT 24 | 337033810000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.72965984 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:56:17 PM PDT 24 | 337066570000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1617336782 | Apr 28 12:28:25 PM PDT 24 | Apr 28 01:02:55 PM PDT 24 | 336695930000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.172780597 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:59:52 PM PDT 24 | 336596150000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.77406260 | Apr 28 12:28:31 PM PDT 24 | Apr 28 12:57:08 PM PDT 24 | 336631070000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.579686633 | Apr 28 12:28:09 PM PDT 24 | Apr 28 01:01:54 PM PDT 24 | 336657610000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1493000662 | Apr 28 12:28:28 PM PDT 24 | Apr 28 01:00:16 PM PDT 24 | 336819590000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.180850543 | Apr 28 12:28:19 PM PDT 24 | Apr 28 12:57:54 PM PDT 24 | 336836330000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1878078684 | Apr 28 12:28:12 PM PDT 24 | Apr 28 12:57:20 PM PDT 24 | 336845770000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3903278243 | Apr 28 12:28:22 PM PDT 24 | Apr 28 01:00:29 PM PDT 24 | 336493550000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1603222549 | Apr 28 12:28:48 PM PDT 24 | Apr 28 01:02:09 PM PDT 24 | 336951670000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1935608175 | Apr 28 12:28:11 PM PDT 24 | Apr 28 01:02:04 PM PDT 24 | 336370010000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2775201372 | Apr 28 12:28:07 PM PDT 24 | Apr 28 12:58:24 PM PDT 24 | 336456630000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3091659553 | Apr 28 12:28:21 PM PDT 24 | Apr 28 12:56:46 PM PDT 24 | 336466630000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1791870655 | Apr 28 12:28:10 PM PDT 24 | Apr 28 12:55:53 PM PDT 24 | 336490470000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2220143750 | Apr 28 12:28:25 PM PDT 24 | Apr 28 01:02:47 PM PDT 24 | 336697890000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.797285634 | Apr 28 12:28:34 PM PDT 24 | Apr 28 12:56:48 PM PDT 24 | 336779630000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2748830522 | Apr 28 12:28:13 PM PDT 24 | Apr 28 01:01:15 PM PDT 24 | 337083930000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3947524545 | Apr 28 12:28:32 PM PDT 24 | Apr 28 12:57:10 PM PDT 24 | 337074710000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2056501987 | Apr 28 12:28:14 PM PDT 24 | Apr 28 12:56:25 PM PDT 24 | 336782010000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3472571931 | Apr 28 12:28:19 PM PDT 24 | Apr 28 12:56:20 PM PDT 24 | 336422070000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4194190718 | Apr 28 12:28:19 PM PDT 24 | Apr 28 12:57:40 PM PDT 24 | 336678370000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.829819837 | Apr 28 12:28:20 PM PDT 24 | Apr 28 12:57:53 PM PDT 24 | 336548690000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1189157533 | Apr 28 12:28:20 PM PDT 24 | Apr 28 12:56:28 PM PDT 24 | 336967910000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.777486695 | Apr 28 12:28:19 PM PDT 24 | Apr 28 12:56:27 PM PDT 24 | 336456770000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4173806727 | Apr 28 12:28:31 PM PDT 24 | Apr 28 01:00:44 PM PDT 24 | 336519810000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1707878552 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:55:49 PM PDT 24 | 336638250000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4074945558 | Apr 28 12:28:30 PM PDT 24 | Apr 28 12:58:04 PM PDT 24 | 336739210000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2386736105 | Apr 28 12:28:02 PM PDT 24 | Apr 28 12:56:30 PM PDT 24 | 336819530000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2945637226 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:57:02 PM PDT 24 | 336748590000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1745922177 | Apr 28 12:28:10 PM PDT 24 | Apr 28 01:00:09 PM PDT 24 | 336903570000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3079495515 | Apr 28 12:28:17 PM PDT 24 | Apr 28 12:55:55 PM PDT 24 | 336446770000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2375402330 | Apr 28 12:28:22 PM PDT 24 | Apr 28 12:58:01 PM PDT 24 | 336378730000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4020855090 | Apr 28 12:28:05 PM PDT 24 | Apr 28 01:00:47 PM PDT 24 | 336770410000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2776509404 | Apr 28 12:28:22 PM PDT 24 | Apr 28 12:59:36 PM PDT 24 | 336561150000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1794250982 | Apr 28 12:28:14 PM PDT 24 | Apr 28 01:02:09 PM PDT 24 | 337043810000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1989221402 | Apr 28 12:28:07 PM PDT 24 | Apr 28 01:01:31 PM PDT 24 | 336928870000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1358308248 | Apr 28 12:28:49 PM PDT 24 | Apr 28 12:59:39 PM PDT 24 | 336621650000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2914989748 | Apr 28 12:28:21 PM PDT 24 | Apr 28 12:57:53 PM PDT 24 | 336531290000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2563651245 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1561830000 ps |
| CPU time | 5.34 seconds |
| Started | Apr 28 02:56:36 PM PDT 24 |
| Finished | Apr 28 02:56:48 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-efa652b9-3b34-4db1-8d02-31657f569200 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2563651245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2563651245 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.778419638 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336554610000 ps |
| CPU time | 743.04 seconds |
| Started | Apr 28 12:27:50 PM PDT 24 |
| Finished | Apr 28 12:58:24 PM PDT 24 |
| Peak memory | 160612 kb |
| Host | smart-7067c17f-0e9e-49c0-ae9c-35bac025509a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=778419638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.778419638 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2931325045 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336931650000 ps |
| CPU time | 839.35 seconds |
| Started | Apr 28 12:28:19 PM PDT 24 |
| Finished | Apr 28 01:02:43 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-e1cb66b4-230e-4422-a0aa-54432d9ccd84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2931325045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2931325045 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.159619031 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1559950000 ps |
| CPU time | 4.47 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:28:17 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-11faf3b8-c0ad-4ad9-8a3c-c26542967b09 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=159619031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.159619031 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2914989748 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336531290000 ps |
| CPU time | 719.87 seconds |
| Started | Apr 28 12:28:21 PM PDT 24 |
| Finished | Apr 28 12:57:53 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-f3f0cb25-da59-4287-9a2b-a71637e2f6b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2914989748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2914989748 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.180850543 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336836330000 ps |
| CPU time | 722.94 seconds |
| Started | Apr 28 12:28:19 PM PDT 24 |
| Finished | Apr 28 12:57:54 PM PDT 24 |
| Peak memory | 160588 kb |
| Host | smart-a6171b29-3c88-45c9-bd3a-d3ec854e08b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=180850543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.180850543 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1989221402 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336928870000 ps |
| CPU time | 812.99 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 01:01:31 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-c3aff950-b8c5-40d6-a051-9081030e5b0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1989221402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1989221402 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2375402330 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336378730000 ps |
| CPU time | 718.5 seconds |
| Started | Apr 28 12:28:22 PM PDT 24 |
| Finished | Apr 28 12:58:01 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-9f7f7094-effb-4354-882e-6e05a06754e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2375402330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2375402330 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1935608175 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336370010000 ps |
| CPU time | 824.44 seconds |
| Started | Apr 28 12:28:11 PM PDT 24 |
| Finished | Apr 28 01:02:04 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-41f76153-eb6f-4e84-bbd4-4b5a41462573 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1935608175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1935608175 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.77406260 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336631070000 ps |
| CPU time | 694.52 seconds |
| Started | Apr 28 12:28:31 PM PDT 24 |
| Finished | Apr 28 12:57:08 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-37ced9aa-0e5b-43e4-a619-6d6830193fa7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=77406260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.77406260 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.579686633 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336657610000 ps |
| CPU time | 814.83 seconds |
| Started | Apr 28 12:28:09 PM PDT 24 |
| Finished | Apr 28 01:01:54 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-e35d995a-4a05-4fb9-9435-4e9176d1aebb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=579686633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.579686633 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3947524545 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 337074710000 ps |
| CPU time | 692.88 seconds |
| Started | Apr 28 12:28:32 PM PDT 24 |
| Finished | Apr 28 12:57:10 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-2e2f8bb7-5dc6-48eb-b67d-5acb06d291db |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3947524545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3947524545 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1530299914 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 337186610000 ps |
| CPU time | 779.4 seconds |
| Started | Apr 28 12:28:13 PM PDT 24 |
| Finished | Apr 28 01:00:41 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-35cd1093-ad40-45b3-80b1-2a8b78d7b3f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1530299914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1530299914 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3496940766 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336871130000 ps |
| CPU time | 681.05 seconds |
| Started | Apr 28 12:28:09 PM PDT 24 |
| Finished | Apr 28 12:56:23 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-4face837-c37d-4fd9-9092-f2a471df9f9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3496940766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3496940766 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2945637226 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336748590000 ps |
| CPU time | 692.45 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:57:02 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-d72b3899-9358-4a63-aec7-41f3e2c5f829 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2945637226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2945637226 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2386736105 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336819530000 ps |
| CPU time | 687.14 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:56:30 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-06355072-af50-40dc-94fc-1ed41e229e0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2386736105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2386736105 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2775201372 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336456630000 ps |
| CPU time | 736.22 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 12:58:24 PM PDT 24 |
| Peak memory | 160632 kb |
| Host | smart-b9662418-5293-4ace-886f-26759d719d6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2775201372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2775201372 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2874033096 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 337023570000 ps |
| CPU time | 695.34 seconds |
| Started | Apr 28 12:28:29 PM PDT 24 |
| Finished | Apr 28 12:56:55 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-463d400f-f514-4c32-8fdd-47d25b5f1748 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2874033096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2874033096 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2056501987 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336782010000 ps |
| CPU time | 687.72 seconds |
| Started | Apr 28 12:28:14 PM PDT 24 |
| Finished | Apr 28 12:56:25 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-6d6b8b03-0593-4ac4-90a6-35df69046d1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2056501987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2056501987 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.394460477 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 337033810000 ps |
| CPU time | 724.53 seconds |
| Started | Apr 28 12:28:01 PM PDT 24 |
| Finished | Apr 28 12:57:34 PM PDT 24 |
| Peak memory | 160588 kb |
| Host | smart-21c25d6c-eb74-4655-b626-18733977945a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=394460477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.394460477 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1228355526 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336961150000 ps |
| CPU time | 824.61 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 01:02:31 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-b724e376-e3b4-491b-8145-6265acdf679b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1228355526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1228355526 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.72965984 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 337066570000 ps |
| CPU time | 674.22 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:56:17 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-b40aa40e-70ad-4ae2-93bd-1b86a2ecdf45 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=72965984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.72965984 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3487429164 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336510470000 ps |
| CPU time | 796.94 seconds |
| Started | Apr 28 12:28:20 PM PDT 24 |
| Finished | Apr 28 01:01:22 PM PDT 24 |
| Peak memory | 160612 kb |
| Host | smart-af7c80b9-1db7-4d0a-a258-75f143ff1326 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3487429164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3487429164 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4020855090 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336770410000 ps |
| CPU time | 783.28 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 01:00:47 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-f31d8fec-e4b5-4079-b58b-5bb59552f8fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4020855090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4020855090 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4074945558 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336739210000 ps |
| CPU time | 726.48 seconds |
| Started | Apr 28 12:28:30 PM PDT 24 |
| Finished | Apr 28 12:58:04 PM PDT 24 |
| Peak memory | 160560 kb |
| Host | smart-ac36648d-03b2-49d4-98ff-b4fc8637d66e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4074945558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4074945558 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1791870655 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336490470000 ps |
| CPU time | 665.81 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 12:55:53 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-49faf510-b2a7-434e-9176-1da34dda9980 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1791870655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1791870655 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3472571931 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336422070000 ps |
| CPU time | 672.81 seconds |
| Started | Apr 28 12:28:19 PM PDT 24 |
| Finished | Apr 28 12:56:20 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-50c39607-8ce7-4a64-b069-74da56f425b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3472571931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3472571931 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1049265004 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336569230000 ps |
| CPU time | 731.8 seconds |
| Started | Apr 28 12:28:33 PM PDT 24 |
| Finished | Apr 28 12:58:44 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-34a93359-e3b8-4000-97df-1db8068ab319 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1049265004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1049265004 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4194190718 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336678370000 ps |
| CPU time | 708.97 seconds |
| Started | Apr 28 12:28:19 PM PDT 24 |
| Finished | Apr 28 12:57:40 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-79819993-6081-46ee-a047-819f4c12d82d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4194190718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.4194190718 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1794250982 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 337043810000 ps |
| CPU time | 824.53 seconds |
| Started | Apr 28 12:28:14 PM PDT 24 |
| Finished | Apr 28 01:02:09 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-dd0ab858-622a-4610-92fc-a2fe4001ac5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1794250982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1794250982 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3628724679 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336560470000 ps |
| CPU time | 709.89 seconds |
| Started | Apr 28 12:28:25 PM PDT 24 |
| Finished | Apr 28 12:57:21 PM PDT 24 |
| Peak memory | 160604 kb |
| Host | smart-5671c540-8a89-4b9d-b124-2b5d880300d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3628724679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3628724679 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2776509404 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336561150000 ps |
| CPU time | 768.66 seconds |
| Started | Apr 28 12:28:22 PM PDT 24 |
| Finished | Apr 28 12:59:36 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-ddcdff46-1636-4bd4-adfe-4d7704c23283 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2776509404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2776509404 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1617336782 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336695930000 ps |
| CPU time | 829.1 seconds |
| Started | Apr 28 12:28:25 PM PDT 24 |
| Finished | Apr 28 01:02:55 PM PDT 24 |
| Peak memory | 160604 kb |
| Host | smart-08e4b72f-31fa-4a4c-823c-e7456465a12d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1617336782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1617336782 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4173806727 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336519810000 ps |
| CPU time | 787.46 seconds |
| Started | Apr 28 12:28:31 PM PDT 24 |
| Finished | Apr 28 01:00:44 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-c2dd5fa8-0c0b-4e1c-aac7-90504d7c8983 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4173806727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.4173806727 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.389067249 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336526530000 ps |
| CPU time | 805.04 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 01:02:02 PM PDT 24 |
| Peak memory | 160596 kb |
| Host | smart-56eb5201-fbbf-4fc4-a18a-67d18ad7f7b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=389067249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.389067249 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1189157533 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336967910000 ps |
| CPU time | 682.01 seconds |
| Started | Apr 28 12:28:20 PM PDT 24 |
| Finished | Apr 28 12:56:28 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-a6cb3adb-0ca0-47c1-a5c0-b5408228f9ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1189157533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1189157533 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3091659553 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336466630000 ps |
| CPU time | 694.53 seconds |
| Started | Apr 28 12:28:21 PM PDT 24 |
| Finished | Apr 28 12:56:46 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-0e4a8907-fe1b-41db-982e-b91b8b4a59e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3091659553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3091659553 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.172780597 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336596150000 ps |
| CPU time | 772.16 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:59:52 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-b5c62166-3f2c-4a49-88ac-2e714e07cb54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=172780597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.172780597 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.777486695 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336456770000 ps |
| CPU time | 685.07 seconds |
| Started | Apr 28 12:28:19 PM PDT 24 |
| Finished | Apr 28 12:56:27 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-28ea4266-941c-454f-a214-8cf2f4af9ed0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=777486695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.777486695 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3079495515 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336446770000 ps |
| CPU time | 664.24 seconds |
| Started | Apr 28 12:28:17 PM PDT 24 |
| Finished | Apr 28 12:55:55 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-a6374ca7-67b1-46a8-928a-2dcba18b119b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3079495515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3079495515 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1603222549 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336951670000 ps |
| CPU time | 804.9 seconds |
| Started | Apr 28 12:28:48 PM PDT 24 |
| Finished | Apr 28 01:02:09 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-9810da64-715c-4717-bc42-71ff85935bab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1603222549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1603222549 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3903278243 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336493550000 ps |
| CPU time | 785.14 seconds |
| Started | Apr 28 12:28:22 PM PDT 24 |
| Finished | Apr 28 01:00:29 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-671d7c07-1565-4bfb-946a-5d83e0f5cc81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3903278243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3903278243 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1745922177 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336903570000 ps |
| CPU time | 795.15 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 01:00:09 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-efd839f8-19d7-4750-a7eb-b643f5c46f0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1745922177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1745922177 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.829819837 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336548690000 ps |
| CPU time | 717.04 seconds |
| Started | Apr 28 12:28:20 PM PDT 24 |
| Finished | Apr 28 12:57:53 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-9bfcf2dc-fe0a-42ca-be42-65d53cd871f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=829819837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.829819837 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.919615910 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336861890000 ps |
| CPU time | 763.8 seconds |
| Started | Apr 28 12:28:29 PM PDT 24 |
| Finished | Apr 28 12:59:43 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-fadb52d0-37d6-4c5e-b7d7-d5da51e09caa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=919615910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.919615910 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1358308248 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336621650000 ps |
| CPU time | 759.43 seconds |
| Started | Apr 28 12:28:49 PM PDT 24 |
| Finished | Apr 28 12:59:39 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-f51b8d85-8d83-4cc6-a21b-23cc9ad66a6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1358308248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1358308248 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1707878552 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336638250000 ps |
| CPU time | 662.39 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:55:49 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-ad070c08-3d75-46d8-96bb-930be1126c16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1707878552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1707878552 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2220143750 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336697890000 ps |
| CPU time | 815.28 seconds |
| Started | Apr 28 12:28:25 PM PDT 24 |
| Finished | Apr 28 01:02:47 PM PDT 24 |
| Peak memory | 160604 kb |
| Host | smart-cf0cb977-b497-4310-baa1-b4c962fbaecd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2220143750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2220143750 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1878078684 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336845770000 ps |
| CPU time | 712.49 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 12:57:20 PM PDT 24 |
| Peak memory | 160612 kb |
| Host | smart-71e53bd7-66d0-47ce-8cd2-80fb439bf0c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1878078684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1878078684 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.438562489 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336715590000 ps |
| CPU time | 816.86 seconds |
| Started | Apr 28 12:28:26 PM PDT 24 |
| Finished | Apr 28 01:02:04 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-543cd8d4-f5fc-4ed3-9f36-27067f83dd59 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=438562489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.438562489 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2748830522 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 337083930000 ps |
| CPU time | 797.01 seconds |
| Started | Apr 28 12:28:13 PM PDT 24 |
| Finished | Apr 28 01:01:15 PM PDT 24 |
| Peak memory | 160604 kb |
| Host | smart-0fd577b6-bb36-4050-897c-2a6bf1438e79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2748830522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2748830522 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1493000662 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336819590000 ps |
| CPU time | 774.64 seconds |
| Started | Apr 28 12:28:28 PM PDT 24 |
| Finished | Apr 28 01:00:16 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-ad260529-03f6-49cc-87d3-d2d0441232b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1493000662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1493000662 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.797285634 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336779630000 ps |
| CPU time | 691.09 seconds |
| Started | Apr 28 12:28:34 PM PDT 24 |
| Finished | Apr 28 12:56:48 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-f264cdf7-2b46-41c8-bd9e-9de3bc4184f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=797285634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.797285634 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1607345813 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336575730000 ps |
| CPU time | 754.63 seconds |
| Started | Apr 28 12:27:57 PM PDT 24 |
| Finished | Apr 28 12:58:54 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-c7b7feb7-9f2d-4845-8aac-cfeafa2b6376 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1607345813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1607345813 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3811397606 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336697210000 ps |
| CPU time | 753.62 seconds |
| Started | Apr 28 12:28:23 PM PDT 24 |
| Finished | Apr 28 12:59:17 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-9758cbfe-e4c2-49d2-91c5-33ca0bab9de6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3811397606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3811397606 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2963083495 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336301390000 ps |
| CPU time | 786.46 seconds |
| Started | Apr 28 12:28:06 PM PDT 24 |
| Finished | Apr 28 01:00:54 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-058350a4-b18d-435e-950a-e45b253126e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2963083495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2963083495 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3920670508 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336460430000 ps |
| CPU time | 714.8 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:57:13 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-46b22db0-ea10-4dba-9d1a-6ba0f2572209 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3920670508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3920670508 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2587274146 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336964410000 ps |
| CPU time | 670.25 seconds |
| Started | Apr 28 12:28:18 PM PDT 24 |
| Finished | Apr 28 12:55:49 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-10607181-249f-412c-a1f4-3d9a38531a5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2587274146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2587274146 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3469084929 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336385310000 ps |
| CPU time | 731.76 seconds |
| Started | Apr 28 12:28:16 PM PDT 24 |
| Finished | Apr 28 12:58:29 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-1c05f3c4-ed72-43f8-ba53-7fe8ca326650 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3469084929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3469084929 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1251568744 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336428470000 ps |
| CPU time | 791.47 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 01:00:33 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-21b24ed1-fddc-4703-a227-c5b3c66e9c1f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1251568744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1251568744 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2061077878 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336932570000 ps |
| CPU time | 670.74 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:55:34 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-11f28eb4-9b2a-4461-adbb-326bce66edb0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2061077878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2061077878 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2582274159 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336421470000 ps |
| CPU time | 696.33 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:56:37 PM PDT 24 |
| Peak memory | 160612 kb |
| Host | smart-f0ee30f3-517f-4d20-8247-ea6117138ab5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2582274159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2582274159 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2641581258 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336390930000 ps |
| CPU time | 684.7 seconds |
| Started | Apr 28 12:28:35 PM PDT 24 |
| Finished | Apr 28 12:57:04 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-90df6f72-fd43-439b-ac6a-cd930a074350 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2641581258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2641581258 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.663102404 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336430690000 ps |
| CPU time | 730.2 seconds |
| Started | Apr 28 12:28:06 PM PDT 24 |
| Finished | Apr 28 12:58:12 PM PDT 24 |
| Peak memory | 160584 kb |
| Host | smart-b5276698-f477-4fb3-bafe-d4d747b3765c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=663102404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.663102404 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3036222214 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336521410000 ps |
| CPU time | 785.58 seconds |
| Started | Apr 28 12:28:14 PM PDT 24 |
| Finished | Apr 28 01:00:28 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-5ebcca4c-b2a2-4ec6-b727-c8af8508a762 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3036222214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3036222214 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2209876399 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336378730000 ps |
| CPU time | 692.76 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:56:43 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-4be18b1b-86b2-4167-933b-7973383f3762 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2209876399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2209876399 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3192969904 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336867330000 ps |
| CPU time | 695.54 seconds |
| Started | Apr 28 12:28:21 PM PDT 24 |
| Finished | Apr 28 12:56:54 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-17b8fec5-1f85-478e-95ed-496d8b8c2fa7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3192969904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3192969904 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3712445839 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 337012870000 ps |
| CPU time | 828.35 seconds |
| Started | Apr 28 12:28:04 PM PDT 24 |
| Finished | Apr 28 01:01:59 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-d095f0f1-64ad-4c5e-821a-da323603c752 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3712445839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3712445839 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3707326423 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336382750000 ps |
| CPU time | 742.09 seconds |
| Started | Apr 28 12:28:04 PM PDT 24 |
| Finished | Apr 28 12:58:32 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-42658703-91fd-4dfd-a00a-0298e7c39d41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3707326423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3707326423 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.351329345 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336836650000 ps |
| CPU time | 815.09 seconds |
| Started | Apr 28 12:28:13 PM PDT 24 |
| Finished | Apr 28 01:02:45 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-f3db8953-1e00-407c-b910-ffaeca3a3f60 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=351329345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.351329345 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2835983166 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336907590000 ps |
| CPU time | 821.03 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 01:02:32 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-06b5ccef-9e5a-4f33-9701-c0ff83b7ca10 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2835983166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2835983166 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.259433577 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336974330000 ps |
| CPU time | 826.92 seconds |
| Started | Apr 28 12:28:01 PM PDT 24 |
| Finished | Apr 28 01:01:55 PM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-b739c812-c561-4d89-8b04-06613ebdb6b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=259433577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.259433577 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2412957028 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336362130000 ps |
| CPU time | 696.76 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 12:56:56 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-b3a8b8c9-c746-449d-9ff9-6cae904d53f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2412957028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2412957028 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3186530634 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336981490000 ps |
| CPU time | 793.27 seconds |
| Started | Apr 28 12:28:04 PM PDT 24 |
| Finished | Apr 28 01:00:26 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-9979463c-7572-4cd8-9a07-74f5da31a775 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3186530634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3186530634 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2547290098 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336844270000 ps |
| CPU time | 758.4 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:59:21 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-ba22e4fa-20e2-43c6-b343-786a67c87512 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2547290098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2547290098 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.582910676 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336644230000 ps |
| CPU time | 781.23 seconds |
| Started | Apr 28 12:28:06 PM PDT 24 |
| Finished | Apr 28 01:00:53 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-4f066481-1777-40c5-8a16-f6f364bd4754 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=582910676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.582910676 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4204004214 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 337128870000 ps |
| CPU time | 540.89 seconds |
| Started | Apr 28 12:28:14 PM PDT 24 |
| Finished | Apr 28 12:51:26 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-b4e14dc0-a81b-4a12-b8fb-3df021e6cef1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4204004214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.4204004214 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3495150159 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336415970000 ps |
| CPU time | 721.8 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 12:57:54 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-056c8579-1e1e-48f9-8bd6-f45fe7be1f9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3495150159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3495150159 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.752928605 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336612350000 ps |
| CPU time | 671.6 seconds |
| Started | Apr 28 12:28:06 PM PDT 24 |
| Finished | Apr 28 12:55:54 PM PDT 24 |
| Peak memory | 160628 kb |
| Host | smart-78c9467d-b151-47eb-b002-227f46672696 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=752928605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.752928605 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3572807682 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336415070000 ps |
| CPU time | 813.52 seconds |
| Started | Apr 28 12:28:18 PM PDT 24 |
| Finished | Apr 28 01:02:04 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-db2b63af-44cd-40ab-a9d8-cc96ae65cd5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3572807682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3572807682 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1506641465 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336594290000 ps |
| CPU time | 712.04 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:57:16 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-64053bd3-e357-43a1-b2bb-d199e77a3355 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1506641465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1506641465 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1907001006 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336377890000 ps |
| CPU time | 830.06 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 01:02:26 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-f01d31a7-388a-4d49-8119-929da303244c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1907001006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1907001006 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.187062575 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336694430000 ps |
| CPU time | 748.96 seconds |
| Started | Apr 28 12:28:00 PM PDT 24 |
| Finished | Apr 28 12:58:36 PM PDT 24 |
| Peak memory | 160580 kb |
| Host | smart-17fd187f-1d20-4e33-8375-efbdd0ecd238 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=187062575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.187062575 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2309722643 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336503310000 ps |
| CPU time | 828.36 seconds |
| Started | Apr 28 12:28:26 PM PDT 24 |
| Finished | Apr 28 01:02:39 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-de0eb7aa-5fac-4b82-9b9b-11a7dab82a82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2309722643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2309722643 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3913144579 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336871950000 ps |
| CPU time | 824.26 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 01:02:18 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-ef269d26-209a-41a7-92d9-3d31b9f0a4c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3913144579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3913144579 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.772461701 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336630490000 ps |
| CPU time | 837.5 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 01:02:37 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-ac824d9b-6486-4ba2-80a4-a1d2cf9577e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=772461701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.772461701 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2440706395 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336978650000 ps |
| CPU time | 712.14 seconds |
| Started | Apr 28 12:28:01 PM PDT 24 |
| Finished | Apr 28 12:57:09 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-0302e6f8-002b-4f3f-b1b5-e000322f4019 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2440706395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2440706395 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2465947331 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 337055890000 ps |
| CPU time | 733.3 seconds |
| Started | Apr 28 12:28:13 PM PDT 24 |
| Finished | Apr 28 12:58:15 PM PDT 24 |
| Peak memory | 160592 kb |
| Host | smart-b24285e6-7cfb-4634-831d-9029c8089d7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2465947331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2465947331 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3049397173 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336543310000 ps |
| CPU time | 693.86 seconds |
| Started | Apr 28 12:28:14 PM PDT 24 |
| Finished | Apr 28 12:56:30 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-3d81b0f3-ca65-4cb4-8efb-71139648f023 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3049397173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3049397173 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1787698876 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336327030000 ps |
| CPU time | 693.04 seconds |
| Started | Apr 28 12:28:18 PM PDT 24 |
| Finished | Apr 28 12:56:36 PM PDT 24 |
| Peak memory | 160568 kb |
| Host | smart-60fc354a-9908-434d-b921-51a34228b19d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1787698876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1787698876 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3161733593 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 337098770000 ps |
| CPU time | 825.6 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 01:02:34 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-71da3c58-7440-40cd-9c6e-fa8792c08093 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3161733593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3161733593 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3789719130 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 337081290000 ps |
| CPU time | 737 seconds |
| Started | Apr 28 12:28:22 PM PDT 24 |
| Finished | Apr 28 12:58:26 PM PDT 24 |
| Peak memory | 160564 kb |
| Host | smart-db8fd64a-a1a3-411d-87e5-be7459dae8eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3789719130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3789719130 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3016633531 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336711970000 ps |
| CPU time | 752.21 seconds |
| Started | Apr 28 12:28:16 PM PDT 24 |
| Finished | Apr 28 12:59:14 PM PDT 24 |
| Peak memory | 160588 kb |
| Host | smart-c6f15c27-61e0-417e-953a-7a5e5d54abbb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3016633531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3016633531 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4277333871 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 337045110000 ps |
| CPU time | 801.22 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 01:01:08 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-5373f7da-30fc-472d-a736-d47110484947 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4277333871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.4277333871 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3833168974 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336658890000 ps |
| CPU time | 818.08 seconds |
| Started | Apr 28 12:28:18 PM PDT 24 |
| Finished | Apr 28 01:02:14 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-6fb84719-b430-4a3e-ad2b-5847bd604d38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3833168974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3833168974 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.139898486 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 337067690000 ps |
| CPU time | 729.87 seconds |
| Started | Apr 28 12:28:08 PM PDT 24 |
| Finished | Apr 28 12:58:17 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-7610ba1e-7956-4d23-88c4-1e3261a4b6d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=139898486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.139898486 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1157885946 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336411550000 ps |
| CPU time | 647.83 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 12:54:57 PM PDT 24 |
| Peak memory | 160580 kb |
| Host | smart-7da2e3d3-d88c-4940-b486-9888756127af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1157885946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1157885946 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3053436628 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 337057950000 ps |
| CPU time | 642.36 seconds |
| Started | Apr 28 12:28:14 PM PDT 24 |
| Finished | Apr 28 12:55:00 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-1c02d79a-02b9-43d9-9a6c-9d8a719c014d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3053436628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3053436628 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3339450183 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336448930000 ps |
| CPU time | 683.27 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 12:56:09 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-aae8a7b0-d2a4-417f-be97-5857c7ab28a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3339450183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3339450183 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1945275889 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336646450000 ps |
| CPU time | 775.87 seconds |
| Started | Apr 28 12:27:55 PM PDT 24 |
| Finished | Apr 28 01:00:08 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-a252a649-0016-4374-bc5c-545ef6434001 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1945275889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1945275889 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3694671060 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336966530000 ps |
| CPU time | 675.85 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 12:55:56 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-daff977e-c4a7-401f-939d-d45360e82523 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3694671060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3694671060 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1457213121 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 337052970000 ps |
| CPU time | 520.7 seconds |
| Started | Apr 28 12:28:03 PM PDT 24 |
| Finished | Apr 28 12:50:11 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-4c2502eb-4939-45a9-9e66-7e71589015b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1457213121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1457213121 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1612491708 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1465630000 ps |
| CPU time | 3.25 seconds |
| Started | Apr 28 12:27:55 PM PDT 24 |
| Finished | Apr 28 12:28:03 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-b390d5ff-874c-43bc-b8c5-b74b5047fb94 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1612491708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1612491708 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2245388189 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1365510000 ps |
| CPU time | 2.69 seconds |
| Started | Apr 28 12:27:59 PM PDT 24 |
| Finished | Apr 28 12:28:06 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-a82e2d48-27c0-4329-9908-bf9ae1f2371f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2245388189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2245388189 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3664890087 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1061890000 ps |
| CPU time | 2.92 seconds |
| Started | Apr 28 12:28:01 PM PDT 24 |
| Finished | Apr 28 12:28:08 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-6deba1a5-cfc0-4132-82b7-2c29f637430d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3664890087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3664890087 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3780569630 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1305970000 ps |
| CPU time | 3.53 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:28:23 PM PDT 24 |
| Peak memory | 164724 kb |
| Host | smart-9bd0e2ca-9159-4a88-a86d-02b7e82c57cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3780569630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3780569630 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3356002115 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1499270000 ps |
| CPU time | 3.16 seconds |
| Started | Apr 28 12:27:48 PM PDT 24 |
| Finished | Apr 28 12:27:55 PM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-af75a2f7-b5d7-4510-9019-f1253c41d85a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3356002115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3356002115 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.261000421 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1444150000 ps |
| CPU time | 3.87 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 12:28:17 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-2fe6ff64-8187-4d69-9407-5b4fe996b1c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=261000421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.261000421 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2187929464 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1438590000 ps |
| CPU time | 3.92 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:28:12 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-9bad8b35-ceac-46d8-811b-ff9a5d5e45a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2187929464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2187929464 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3928489826 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1528190000 ps |
| CPU time | 3.74 seconds |
| Started | Apr 28 12:27:56 PM PDT 24 |
| Finished | Apr 28 12:28:05 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-e1aa0ab7-e9d3-4758-ae8d-d0662e4ac13a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3928489826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3928489826 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4059220122 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1553010000 ps |
| CPU time | 4.23 seconds |
| Started | Apr 28 12:28:16 PM PDT 24 |
| Finished | Apr 28 12:28:26 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-dba94c37-d4f3-4e2d-ba3a-59dccd27ec36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4059220122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4059220122 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3742361580 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1512870000 ps |
| CPU time | 3.24 seconds |
| Started | Apr 28 12:28:11 PM PDT 24 |
| Finished | Apr 28 12:28:19 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-81cabdee-d09f-4474-8450-5a1363ac9642 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3742361580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3742361580 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1013574945 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1438970000 ps |
| CPU time | 3.96 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:28:15 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-746424b2-5693-497b-bd1e-bc07be89cedf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1013574945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1013574945 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3671707247 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1538230000 ps |
| CPU time | 3.04 seconds |
| Started | Apr 28 12:27:59 PM PDT 24 |
| Finished | Apr 28 12:28:07 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-fd4dd8e0-3188-453f-937f-3923919280c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3671707247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3671707247 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1167402962 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1337150000 ps |
| CPU time | 3.48 seconds |
| Started | Apr 28 12:28:00 PM PDT 24 |
| Finished | Apr 28 12:28:09 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-3ec9fbcf-ed11-4b5a-947e-de474f6e8b7e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1167402962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1167402962 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4168709587 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1470950000 ps |
| CPU time | 3.08 seconds |
| Started | Apr 28 12:28:07 PM PDT 24 |
| Finished | Apr 28 12:28:15 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-19a33ed7-2500-4c4f-818d-e7c040d3e48f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4168709587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4168709587 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1510954963 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1394710000 ps |
| CPU time | 3.48 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:28:10 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-d453420d-7cc6-44ca-a58f-1b9a664bb909 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1510954963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1510954963 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2384503601 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1213970000 ps |
| CPU time | 2.78 seconds |
| Started | Apr 28 12:28:18 PM PDT 24 |
| Finished | Apr 28 12:28:25 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-118a0562-8629-4e0a-ad25-6cfbf3df9948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2384503601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2384503601 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2339145501 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1149110000 ps |
| CPU time | 3.11 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 12:28:20 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-22f67d47-e8ef-4c92-a137-cef21fe19bbd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2339145501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2339145501 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4263486462 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1280810000 ps |
| CPU time | 3.81 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 12:28:19 PM PDT 24 |
| Peak memory | 164692 kb |
| Host | smart-6cd11865-5167-4505-bc36-e315c7bea2c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4263486462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4263486462 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3779266510 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1447930000 ps |
| CPU time | 3.45 seconds |
| Started | Apr 28 12:28:11 PM PDT 24 |
| Finished | Apr 28 12:28:19 PM PDT 24 |
| Peak memory | 164728 kb |
| Host | smart-7994d4b2-9048-4362-9027-2edd5eb844e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3779266510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3779266510 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3209438899 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1539830000 ps |
| CPU time | 3.12 seconds |
| Started | Apr 28 12:28:08 PM PDT 24 |
| Finished | Apr 28 12:28:16 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-2a059687-8fd4-4c8d-be46-9b1752920a7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3209438899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3209438899 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3408209157 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1480130000 ps |
| CPU time | 3.47 seconds |
| Started | Apr 28 12:27:57 PM PDT 24 |
| Finished | Apr 28 12:28:05 PM PDT 24 |
| Peak memory | 164728 kb |
| Host | smart-909de52f-4824-4f67-b789-3a6725f8983c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3408209157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3408209157 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.93345964 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1564990000 ps |
| CPU time | 4.61 seconds |
| Started | Apr 28 12:27:51 PM PDT 24 |
| Finished | Apr 28 12:28:02 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-1cc9c888-dbaa-464b-8ae2-14b096868749 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=93345964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.93345964 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2492555125 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1472610000 ps |
| CPU time | 2.91 seconds |
| Started | Apr 28 12:28:19 PM PDT 24 |
| Finished | Apr 28 12:28:27 PM PDT 24 |
| Peak memory | 164692 kb |
| Host | smart-4d9b7321-1790-4159-ba8a-cbab8fc9672c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2492555125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2492555125 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.824386819 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1441030000 ps |
| CPU time | 3.37 seconds |
| Started | Apr 28 12:27:46 PM PDT 24 |
| Finished | Apr 28 12:27:54 PM PDT 24 |
| Peak memory | 164720 kb |
| Host | smart-c12232c9-6f35-459d-8b69-825a79a78a7e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=824386819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.824386819 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1725971032 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1494770000 ps |
| CPU time | 3.69 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:28:11 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-7c1ce338-1ebf-4cbf-ac1c-614fc65a3df8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1725971032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1725971032 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.700029139 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1471110000 ps |
| CPU time | 3.8 seconds |
| Started | Apr 28 12:28:06 PM PDT 24 |
| Finished | Apr 28 12:28:16 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-26eea466-dd0f-4f74-b53c-aa1f5ffe699c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=700029139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.700029139 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3903959115 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1378690000 ps |
| CPU time | 3.65 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:28:14 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-37bba548-243f-41af-ac6e-5493c24766a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3903959115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3903959115 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2058743349 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1555950000 ps |
| CPU time | 4.11 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:28:15 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-8aa94f97-c419-49a0-b11a-72e516b7687a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2058743349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2058743349 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3914995273 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1464550000 ps |
| CPU time | 3.91 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 12:28:22 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-789c4b5f-5d77-49b3-9867-9d668b23ef63 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3914995273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3914995273 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2127117952 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1127650000 ps |
| CPU time | 3.01 seconds |
| Started | Apr 28 12:28:00 PM PDT 24 |
| Finished | Apr 28 12:28:07 PM PDT 24 |
| Peak memory | 164716 kb |
| Host | smart-d5eff7a5-bf49-4e71-8704-06dcb8693d89 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2127117952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2127117952 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3568484525 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1428550000 ps |
| CPU time | 3.57 seconds |
| Started | Apr 28 12:28:00 PM PDT 24 |
| Finished | Apr 28 12:28:09 PM PDT 24 |
| Peak memory | 164720 kb |
| Host | smart-ddcf01df-bbb0-4105-b791-c6262c1c4955 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3568484525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3568484525 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.945882262 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1533210000 ps |
| CPU time | 3.01 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 12:28:18 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-5f70b861-29dc-4bda-a93f-c14ee02ffbdf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=945882262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.945882262 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.193961420 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1419010000 ps |
| CPU time | 3.13 seconds |
| Started | Apr 28 12:27:58 PM PDT 24 |
| Finished | Apr 28 12:28:06 PM PDT 24 |
| Peak memory | 164724 kb |
| Host | smart-001417b0-9bb4-4a31-a5fa-3a57cfc20a5e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=193961420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.193961420 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3740015722 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1500270000 ps |
| CPU time | 3.48 seconds |
| Started | Apr 28 12:27:53 PM PDT 24 |
| Finished | Apr 28 12:28:01 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-28af402e-5c89-41f0-ad1e-886c155f5904 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3740015722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3740015722 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1260704609 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1532750000 ps |
| CPU time | 3.75 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:28:12 PM PDT 24 |
| Peak memory | 166388 kb |
| Host | smart-895fda9b-d902-43b0-9fa7-463b6086702a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1260704609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1260704609 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1760849456 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1542790000 ps |
| CPU time | 3.58 seconds |
| Started | Apr 28 12:27:42 PM PDT 24 |
| Finished | Apr 28 12:27:50 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-4470868e-42fc-4f25-9a24-8a3f35bea5c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1760849456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1760849456 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4118328422 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1526790000 ps |
| CPU time | 5.14 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 12:28:23 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-1e5d7068-4882-465c-8a1e-1b1dc0b1644c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4118328422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.4118328422 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1885830371 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1383490000 ps |
| CPU time | 3.34 seconds |
| Started | Apr 28 12:27:56 PM PDT 24 |
| Finished | Apr 28 12:28:04 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-75507764-79a5-4976-bd3a-64b105631da9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1885830371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1885830371 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1220053781 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1528770000 ps |
| CPU time | 3.69 seconds |
| Started | Apr 28 12:28:03 PM PDT 24 |
| Finished | Apr 28 12:28:12 PM PDT 24 |
| Peak memory | 164724 kb |
| Host | smart-c68e089a-fe74-4130-b92d-1c7c5f4b4088 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1220053781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1220053781 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4207518081 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1455310000 ps |
| CPU time | 3.3 seconds |
| Started | Apr 28 12:28:02 PM PDT 24 |
| Finished | Apr 28 12:28:10 PM PDT 24 |
| Peak memory | 164736 kb |
| Host | smart-e62b7428-6d4a-46b7-9122-cca1f0b1b9bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4207518081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.4207518081 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.546795471 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1547950000 ps |
| CPU time | 3.82 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:28:15 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-8d54eb51-10a9-4f18-a1cb-26c258b833db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=546795471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.546795471 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2645484764 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1383510000 ps |
| CPU time | 3.03 seconds |
| Started | Apr 28 12:28:01 PM PDT 24 |
| Finished | Apr 28 12:28:08 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-a4d6fa2f-81f4-4847-8787-f868d91c6e1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2645484764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2645484764 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2936641753 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1507910000 ps |
| CPU time | 3.89 seconds |
| Started | Apr 28 12:27:54 PM PDT 24 |
| Finished | Apr 28 12:28:03 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-80e06fef-41bc-47bd-bdbe-e4bc0e45cc65 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2936641753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2936641753 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.283662007 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1584550000 ps |
| CPU time | 4.37 seconds |
| Started | Apr 28 12:28:05 PM PDT 24 |
| Finished | Apr 28 12:28:15 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-cb0f4d7c-acbc-4006-9ca1-107ec8cfea46 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=283662007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.283662007 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.655151645 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1308250000 ps |
| CPU time | 3.12 seconds |
| Started | Apr 28 12:27:57 PM PDT 24 |
| Finished | Apr 28 12:28:04 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-9c249f38-9721-465f-ba37-296344411409 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=655151645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.655151645 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.988612552 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1481190000 ps |
| CPU time | 3.48 seconds |
| Started | Apr 28 12:28:11 PM PDT 24 |
| Finished | Apr 28 12:28:19 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-f764c826-1b90-4ac6-89b7-e93ff3f6843e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=988612552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.988612552 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3214429839 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1569250000 ps |
| CPU time | 2.99 seconds |
| Started | Apr 28 12:28:12 PM PDT 24 |
| Finished | Apr 28 12:28:20 PM PDT 24 |
| Peak memory | 164692 kb |
| Host | smart-56f71b4e-cdfd-47ff-9f5a-90dd4cc9d918 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3214429839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3214429839 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.833720080 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1498370000 ps |
| CPU time | 3.26 seconds |
| Started | Apr 28 12:27:46 PM PDT 24 |
| Finished | Apr 28 12:27:53 PM PDT 24 |
| Peak memory | 166312 kb |
| Host | smart-867bcd84-10af-469c-8cd7-68f0b7a14f7d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=833720080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.833720080 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1229295416 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1550750000 ps |
| CPU time | 4.68 seconds |
| Started | Apr 28 12:28:01 PM PDT 24 |
| Finished | Apr 28 12:28:13 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-8dfee707-e80e-4ee1-9c26-6460136817f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1229295416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1229295416 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1406926506 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1564350000 ps |
| CPU time | 4.02 seconds |
| Started | Apr 28 02:56:35 PM PDT 24 |
| Finished | Apr 28 02:56:45 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-2fa4e2cd-325a-4bd7-b405-804759da9c92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1406926506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1406926506 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2536162019 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1487430000 ps |
| CPU time | 4.58 seconds |
| Started | Apr 28 02:56:49 PM PDT 24 |
| Finished | Apr 28 02:57:00 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-7d03ad23-fd1e-443d-aab2-bd78f068443c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2536162019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2536162019 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.998127557 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1309830000 ps |
| CPU time | 3.81 seconds |
| Started | Apr 28 02:56:41 PM PDT 24 |
| Finished | Apr 28 02:56:50 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-fdc2a082-aaad-4bf8-90ab-23d4935d06f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=998127557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.998127557 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4057517194 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1424490000 ps |
| CPU time | 4.36 seconds |
| Started | Apr 28 02:56:49 PM PDT 24 |
| Finished | Apr 28 02:57:00 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-20b5d3eb-a5ea-476c-96ad-0a94f185add6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4057517194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4057517194 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1847086495 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1407690000 ps |
| CPU time | 3.73 seconds |
| Started | Apr 28 02:56:43 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-2ffbfe65-9315-4a30-9070-9fd982f8d1d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1847086495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1847086495 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2557888489 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1419790000 ps |
| CPU time | 4.08 seconds |
| Started | Apr 28 02:56:42 PM PDT 24 |
| Finished | Apr 28 02:56:51 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-760fb659-bc32-4cbc-8355-afa1b565fc98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2557888489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2557888489 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2109323855 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1415550000 ps |
| CPU time | 3.99 seconds |
| Started | Apr 28 02:56:43 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-341c6c87-6bd8-456f-a980-9229f4efc144 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2109323855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2109323855 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.931470058 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1396810000 ps |
| CPU time | 5.57 seconds |
| Started | Apr 28 02:56:40 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-6106b82c-fee3-4e8f-99dd-80ef7bc1bcfc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=931470058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.931470058 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3890009159 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1557030000 ps |
| CPU time | 5.42 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:59 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-058b9954-8cf9-464a-8163-21fcc7e055c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3890009159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3890009159 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.708354420 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1248010000 ps |
| CPU time | 3.47 seconds |
| Started | Apr 28 02:56:41 PM PDT 24 |
| Finished | Apr 28 02:56:49 PM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-f9c443cd-a581-4f93-9783-5c5c61b6cf29 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=708354420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.708354420 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1701322408 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1552630000 ps |
| CPU time | 4.92 seconds |
| Started | Apr 28 02:56:43 PM PDT 24 |
| Finished | Apr 28 02:56:55 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-696849e3-a6b5-4a0e-800a-9323000744ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1701322408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1701322408 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3401496406 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1474350000 ps |
| CPU time | 4.49 seconds |
| Started | Apr 28 02:56:35 PM PDT 24 |
| Finished | Apr 28 02:56:45 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-9edb871e-1113-4f8d-a992-7ca2554c1cff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3401496406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3401496406 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1175081521 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1498070000 ps |
| CPU time | 5.93 seconds |
| Started | Apr 28 02:56:40 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-17c1382c-9f2c-4eab-8d4a-22c997ce58ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1175081521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1175081521 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.834856719 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1130990000 ps |
| CPU time | 4.18 seconds |
| Started | Apr 28 02:56:43 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164984 kb |
| Host | smart-490ad89a-fdbe-4fab-8404-99b7580b2880 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=834856719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.834856719 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.260758832 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1119190000 ps |
| CPU time | 3.45 seconds |
| Started | Apr 28 02:56:43 PM PDT 24 |
| Finished | Apr 28 02:56:51 PM PDT 24 |
| Peak memory | 164996 kb |
| Host | smart-f965911c-0db3-43d2-9530-d1669010a36b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=260758832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.260758832 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.715935043 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1389850000 ps |
| CPU time | 4.32 seconds |
| Started | Apr 28 02:56:41 PM PDT 24 |
| Finished | Apr 28 02:56:51 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-162ace7f-a746-4512-a3f8-e4e248ec9ca6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=715935043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.715935043 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1877964162 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1544390000 ps |
| CPU time | 4.87 seconds |
| Started | Apr 28 02:56:43 PM PDT 24 |
| Finished | Apr 28 02:56:55 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-9a9547ed-7574-41c9-99c6-da7cf78cf421 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1877964162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1877964162 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1840390140 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1402850000 ps |
| CPU time | 3.89 seconds |
| Started | Apr 28 02:56:41 PM PDT 24 |
| Finished | Apr 28 02:56:50 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-3961511d-5967-41d2-8559-79054acb43db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1840390140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1840390140 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4248967407 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1434350000 ps |
| CPU time | 5.25 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:58 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-90937171-9768-411d-86d8-873711d45e7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4248967407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4248967407 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4201276181 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1478710000 ps |
| CPU time | 3.2 seconds |
| Started | Apr 28 02:56:40 PM PDT 24 |
| Finished | Apr 28 02:56:48 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-a7b8ff9f-ea94-4a31-80a3-cfa5d7f29e9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4201276181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4201276181 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2384299872 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1555930000 ps |
| CPU time | 5.67 seconds |
| Started | Apr 28 02:56:40 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-02507665-1b84-46f7-8418-21cd4507594d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2384299872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2384299872 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3873283871 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1496210000 ps |
| CPU time | 4.73 seconds |
| Started | Apr 28 02:56:49 PM PDT 24 |
| Finished | Apr 28 02:57:00 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-adcc5578-5c53-4ed4-9cce-83000f5f2773 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3873283871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3873283871 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4183130175 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1313450000 ps |
| CPU time | 5.49 seconds |
| Started | Apr 28 02:56:35 PM PDT 24 |
| Finished | Apr 28 02:56:47 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-0e31f4f6-f856-4664-9c60-43fe8928496e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4183130175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.4183130175 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4144999835 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1511330000 ps |
| CPU time | 4.79 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:57 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-b1b87551-2e8e-4c15-9ad6-70df00431cac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4144999835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.4144999835 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1456447989 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1321830000 ps |
| CPU time | 3.61 seconds |
| Started | Apr 28 02:56:47 PM PDT 24 |
| Finished | Apr 28 02:56:56 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-5a9d33ef-dca9-4348-bbd1-de2af447b9cc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1456447989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1456447989 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4001481529 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1320610000 ps |
| CPU time | 3.66 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:54 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-3b6bbc87-6ac3-4c29-815e-47fb9b486e43 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4001481529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4001481529 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.700430334 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1580530000 ps |
| CPU time | 5.19 seconds |
| Started | Apr 28 02:56:47 PM PDT 24 |
| Finished | Apr 28 02:56:59 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-7c181e7a-e1dc-41de-9e3b-fc6fb6c25bad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=700430334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.700430334 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4045908322 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1428670000 ps |
| CPU time | 3.07 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-2a4f53ce-1c13-457e-8c9b-f4c4dc589b22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4045908322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.4045908322 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.627179099 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1549930000 ps |
| CPU time | 4.36 seconds |
| Started | Apr 28 02:56:44 PM PDT 24 |
| Finished | Apr 28 02:56:54 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-e53a25d0-07b0-4aa6-9ffe-d8596f67981d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=627179099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.627179099 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1198342527 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1324110000 ps |
| CPU time | 3.73 seconds |
| Started | Apr 28 02:56:47 PM PDT 24 |
| Finished | Apr 28 02:56:56 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-31e5c5b0-5e9d-4af1-ae40-eceb53056c35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1198342527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1198342527 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3329258053 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1207630000 ps |
| CPU time | 5.18 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:57 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-a5d4b695-d522-49f3-b389-1a8e809f7b9a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3329258053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3329258053 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2949584264 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1572510000 ps |
| CPU time | 3.47 seconds |
| Started | Apr 28 02:56:46 PM PDT 24 |
| Finished | Apr 28 02:56:55 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-0ba16a76-908a-47e5-a613-f55553c68a2d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2949584264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2949584264 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2491323024 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1478250000 ps |
| CPU time | 4.29 seconds |
| Started | Apr 28 02:56:47 PM PDT 24 |
| Finished | Apr 28 02:56:57 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-07891733-32a4-4e6d-a7f5-223aec145497 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2491323024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2491323024 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.424184123 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1483050000 ps |
| CPU time | 4.69 seconds |
| Started | Apr 28 02:56:38 PM PDT 24 |
| Finished | Apr 28 02:56:49 PM PDT 24 |
| Peak memory | 166416 kb |
| Host | smart-777781cb-77ec-4ba1-bdbc-128176598c76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=424184123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.424184123 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2032340134 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1543870000 ps |
| CPU time | 3.58 seconds |
| Started | Apr 28 02:56:44 PM PDT 24 |
| Finished | Apr 28 02:56:53 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-e233eb7a-612a-473b-807b-ecaae041d158 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2032340134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2032340134 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3758313471 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1428590000 ps |
| CPU time | 4.22 seconds |
| Started | Apr 28 02:56:46 PM PDT 24 |
| Finished | Apr 28 02:56:56 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-63fc95fb-08e6-407a-bff3-425b731e1591 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3758313471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3758313471 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.29053622 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1268010000 ps |
| CPU time | 2.74 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:53 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-6078bb24-80b2-41f0-a6b4-817deb440952 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=29053622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.29053622 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.18566902 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1442550000 ps |
| CPU time | 3.15 seconds |
| Started | Apr 28 02:56:46 PM PDT 24 |
| Finished | Apr 28 02:56:55 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-09bda0cb-1c98-4b44-8d45-3c5421212e9c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=18566902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.18566902 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3074895088 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1483590000 ps |
| CPU time | 3.76 seconds |
| Started | Apr 28 02:56:46 PM PDT 24 |
| Finished | Apr 28 02:56:56 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-ec88e98a-86ba-4ba7-bc97-063a7babbfee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3074895088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3074895088 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4253631765 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1357330000 ps |
| CPU time | 3.36 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:53 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-d9e16d5a-b5cf-4ef8-8860-a8a0b2ba2ad6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4253631765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4253631765 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4090144311 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1547670000 ps |
| CPU time | 4.8 seconds |
| Started | Apr 28 02:56:49 PM PDT 24 |
| Finished | Apr 28 02:57:01 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-5d16a061-488e-4085-8ff7-a33c8aca1b99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4090144311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4090144311 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.417049342 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1548950000 ps |
| CPU time | 4.55 seconds |
| Started | Apr 28 02:56:49 PM PDT 24 |
| Finished | Apr 28 02:57:00 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-bf49b090-3770-463e-9243-9fd9aff4e851 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=417049342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.417049342 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1842611523 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1429950000 ps |
| CPU time | 3 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-a60c13a0-c417-4223-8926-29591e3be99c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1842611523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1842611523 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.10809229 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1437810000 ps |
| CPU time | 3.38 seconds |
| Started | Apr 28 02:56:45 PM PDT 24 |
| Finished | Apr 28 02:56:53 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-46d19d1f-ec9f-4c0c-80eb-c74ea9e8cac7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=10809229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.10809229 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1189998712 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1328290000 ps |
| CPU time | 3.53 seconds |
| Started | Apr 28 02:56:38 PM PDT 24 |
| Finished | Apr 28 02:56:47 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-17fd6f8f-9d90-4c75-9145-7ad9785513f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1189998712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1189998712 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.438150533 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1253690000 ps |
| CPU time | 2.77 seconds |
| Started | Apr 28 02:56:36 PM PDT 24 |
| Finished | Apr 28 02:56:42 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-cdd6a64e-6de8-475f-9ac6-782b84160f42 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=438150533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.438150533 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4146888979 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1506030000 ps |
| CPU time | 4.44 seconds |
| Started | Apr 28 02:56:35 PM PDT 24 |
| Finished | Apr 28 02:56:46 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-2bb071e0-87ef-44e3-8351-0d4a1036d2ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4146888979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.4146888979 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1311054851 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1622450000 ps |
| CPU time | 5.95 seconds |
| Started | Apr 28 02:56:39 PM PDT 24 |
| Finished | Apr 28 02:56:52 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-f2abec4f-3b3a-4723-8bab-a0a5b1a7c84c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1311054851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1311054851 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2928959863 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1348410000 ps |
| CPU time | 4.2 seconds |
| Started | Apr 28 02:56:38 PM PDT 24 |
| Finished | Apr 28 02:56:48 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-11087acc-c6a5-4939-8487-35a783105e13 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2928959863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2928959863 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |