| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3887821688 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1174523589 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1090924974 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3110316167 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1424035905 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3846083035 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3562295168 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4132125303 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.472036277 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3951548294 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1650728378 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2873556563 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1809392722 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2754694063 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1169313882 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.396708565 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1639875358 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1224913345 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1521214881 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3537652218 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2756831258 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.363386600 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3080615316 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3505365710 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1868124496 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3305942280 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.654901325 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3563370736 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.158567454 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.405703274 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.64163560 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.297472422 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2209724302 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2247669360 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1401293666 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3497278732 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.627520145 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3310259782 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4142400195 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1787451677 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1741762838 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.317655351 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2887500088 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1744785762 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.246221242 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2108238375 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.775587654 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2898984029 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3983751446 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.575732689 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2191528170 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.662151565 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2770689071 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3365495852 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2389421526 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1581440307 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4095723716 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.509270258 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3620544054 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.185818887 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1822930117 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2373546362 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3121732188 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2260613375 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2139250863 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3294479847 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.775041050 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.505989066 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.207980147 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.684070490 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.184231066 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2524372360 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2392908587 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3168199515 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3701221354 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2258481410 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1441354628 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2593568945 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4033141462 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.173828925 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1127062138 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3483016379 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1244689456 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2346169992 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.40781974 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2084690118 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3314345189 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2451998367 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1664303010 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.637539097 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.247110865 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.756601230 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2848339440 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2060126277 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2968675081 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2893052226 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1080809319 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3286664574 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.177596680 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4120687228 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3766328299 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3877068997 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3730345867 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2607013430 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3071739954 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2597319053 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2802024895 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2171934002 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1028041693 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.415125654 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1556742100 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2032712093 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2409034427 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3748609537 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3964017128 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3754141877 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2278045578 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4228185201 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.841374326 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.672988581 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2541863166 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.200215114 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.955459829 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3255413044 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2831744094 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1035652267 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3664728347 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2009879810 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1201122805 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.359189873 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3173384069 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1201669378 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2176367216 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3126738803 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3762198658 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1146899292 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3531200800 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3343162524 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.753107378 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2250778761 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2326107558 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1161185529 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1577962603 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.420265531 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1365113810 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2844721823 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1082324481 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3658521611 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4289121289 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1073798095 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2931175103 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4256550895 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3855164635 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1241868380 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3317129329 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3752091715 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1814992885 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3321637106 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2511441394 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.600495680 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1692589730 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3938779424 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.813073599 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4233429289 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1010607641 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.150621736 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3773086681 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.74955068 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.269348503 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2429184407 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2121939600 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2811274614 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.189623957 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2236692172 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.277828423 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1380389026 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1211100042 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3064953194 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4100343355 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3099812799 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.735459740 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.434538474 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2362978836 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.163586644 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3361362661 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.78426229 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3097781811 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2589254448 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1784176297 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3819782775 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1668544253 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.641306050 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.313214992 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2859970998 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3936677033 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3198762239 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2637535854 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2127920960 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3700936611 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3968189573 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3887821688 | May 02 12:30:42 PM PDT 24 | May 02 12:30:55 PM PDT 24 | 1421790000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3968189573 | May 02 12:31:11 PM PDT 24 | May 02 12:31:21 PM PDT 24 | 1494290000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4233429289 | May 02 12:30:58 PM PDT 24 | May 02 12:31:09 PM PDT 24 | 1436310000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.313214992 | May 02 12:30:54 PM PDT 24 | May 02 12:31:05 PM PDT 24 | 1587170000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3938779424 | May 02 12:30:48 PM PDT 24 | May 02 12:30:59 PM PDT 24 | 1417830000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3097781811 | May 02 12:31:15 PM PDT 24 | May 02 12:31:24 PM PDT 24 | 1523390000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2859970998 | May 02 12:31:00 PM PDT 24 | May 02 12:31:08 PM PDT 24 | 1569170000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2589254448 | May 02 12:31:05 PM PDT 24 | May 02 12:31:15 PM PDT 24 | 1361470000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3317129329 | May 02 12:31:08 PM PDT 24 | May 02 12:31:17 PM PDT 24 | 1236070000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.189623957 | May 02 12:31:00 PM PDT 24 | May 02 12:31:10 PM PDT 24 | 1493850000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2429184407 | May 02 12:31:09 PM PDT 24 | May 02 12:31:18 PM PDT 24 | 1369770000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.600495680 | May 02 12:30:55 PM PDT 24 | May 02 12:31:06 PM PDT 24 | 1497210000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.74955068 | May 02 12:31:07 PM PDT 24 | May 02 12:31:17 PM PDT 24 | 1603790000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3361362661 | May 02 12:30:58 PM PDT 24 | May 02 12:31:05 PM PDT 24 | 1121810000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.735459740 | May 02 12:31:00 PM PDT 24 | May 02 12:31:09 PM PDT 24 | 1372790000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4100343355 | May 02 12:30:56 PM PDT 24 | May 02 12:31:05 PM PDT 24 | 1592370000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2362978836 | May 02 12:31:18 PM PDT 24 | May 02 12:31:24 PM PDT 24 | 1174190000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.78426229 | May 02 12:31:04 PM PDT 24 | May 02 12:31:11 PM PDT 24 | 1503350000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3936677033 | May 02 12:31:17 PM PDT 24 | May 02 12:31:25 PM PDT 24 | 1574710000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2236692172 | May 02 12:30:49 PM PDT 24 | May 02 12:31:02 PM PDT 24 | 1646750000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.269348503 | May 02 12:31:01 PM PDT 24 | May 02 12:31:10 PM PDT 24 | 1494510000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3752091715 | May 02 12:30:54 PM PDT 24 | May 02 12:31:05 PM PDT 24 | 1542190000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.150621736 | May 02 12:30:54 PM PDT 24 | May 02 12:31:06 PM PDT 24 | 1618850000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2811274614 | May 02 12:30:42 PM PDT 24 | May 02 12:30:49 PM PDT 24 | 1477690000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.277828423 | May 02 12:31:06 PM PDT 24 | May 02 12:31:14 PM PDT 24 | 1243650000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1668544253 | May 02 12:31:17 PM PDT 24 | May 02 12:31:26 PM PDT 24 | 1299910000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3321637106 | May 02 12:31:00 PM PDT 24 | May 02 12:31:10 PM PDT 24 | 1541090000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4256550895 | May 02 12:30:41 PM PDT 24 | May 02 12:30:48 PM PDT 24 | 1459890000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3700936611 | May 02 12:31:04 PM PDT 24 | May 02 12:31:13 PM PDT 24 | 1335170000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2637535854 | May 02 12:30:56 PM PDT 24 | May 02 12:31:07 PM PDT 24 | 1592950000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1814992885 | May 02 12:31:04 PM PDT 24 | May 02 12:31:19 PM PDT 24 | 1582310000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3198762239 | May 02 12:31:04 PM PDT 24 | May 02 12:31:13 PM PDT 24 | 1430230000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2127920960 | May 02 12:30:49 PM PDT 24 | May 02 12:31:00 PM PDT 24 | 1533490000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3064953194 | May 02 12:31:00 PM PDT 24 | May 02 12:31:09 PM PDT 24 | 1494530000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2121939600 | May 02 12:31:13 PM PDT 24 | May 02 12:31:21 PM PDT 24 | 1602710000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1010607641 | May 02 12:30:58 PM PDT 24 | May 02 12:31:07 PM PDT 24 | 1553130000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3855164635 | May 02 12:30:55 PM PDT 24 | May 02 12:31:05 PM PDT 24 | 1430950000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3099812799 | May 02 12:30:59 PM PDT 24 | May 02 12:31:08 PM PDT 24 | 1511050000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1241868380 | May 02 12:31:08 PM PDT 24 | May 02 12:31:17 PM PDT 24 | 1526570000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.641306050 | May 02 12:31:16 PM PDT 24 | May 02 12:31:23 PM PDT 24 | 1310810000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.434538474 | May 02 12:31:15 PM PDT 24 | May 02 12:31:22 PM PDT 24 | 1354490000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.163586644 | May 02 12:31:16 PM PDT 24 | May 02 12:31:24 PM PDT 24 | 1423690000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1784176297 | May 02 12:31:11 PM PDT 24 | May 02 12:31:20 PM PDT 24 | 1414990000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3819782775 | May 02 12:31:08 PM PDT 24 | May 02 12:31:17 PM PDT 24 | 1556750000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1380389026 | May 02 12:30:56 PM PDT 24 | May 02 12:31:06 PM PDT 24 | 1422490000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1692589730 | May 02 12:30:55 PM PDT 24 | May 02 12:31:05 PM PDT 24 | 1543950000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2511441394 | May 02 12:31:06 PM PDT 24 | May 02 12:31:14 PM PDT 24 | 1512890000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.813073599 | May 02 12:31:01 PM PDT 24 | May 02 12:31:10 PM PDT 24 | 1546650000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1211100042 | May 02 12:30:58 PM PDT 24 | May 02 12:31:08 PM PDT 24 | 1443450000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3773086681 | May 02 12:30:59 PM PDT 24 | May 02 12:31:08 PM PDT 24 | 1483910000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2802024895 | May 02 12:28:46 PM PDT 24 | May 02 12:28:57 PM PDT 24 | 1454850000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3126738803 | May 02 12:29:35 PM PDT 24 | May 02 12:29:44 PM PDT 24 | 1155810000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.955459829 | May 02 12:30:09 PM PDT 24 | May 02 12:30:19 PM PDT 24 | 1476190000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3754141877 | May 02 12:27:32 PM PDT 24 | May 02 12:27:43 PM PDT 24 | 1366490000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4289121289 | May 02 12:30:05 PM PDT 24 | May 02 12:30:16 PM PDT 24 | 1405770000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3531200800 | May 02 12:30:09 PM PDT 24 | May 02 12:30:20 PM PDT 24 | 1556510000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3071739954 | May 02 12:29:19 PM PDT 24 | May 02 12:29:30 PM PDT 24 | 1523250000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3110316167 | May 02 12:28:12 PM PDT 24 | May 02 12:28:18 PM PDT 24 | 1149310000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1161185529 | May 02 12:29:18 PM PDT 24 | May 02 12:29:31 PM PDT 24 | 1393010000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1577962603 | May 02 12:29:34 PM PDT 24 | May 02 12:29:45 PM PDT 24 | 1312210000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1035652267 | May 02 12:29:20 PM PDT 24 | May 02 12:29:30 PM PDT 24 | 1470550000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.359189873 | May 02 12:30:10 PM PDT 24 | May 02 12:30:17 PM PDT 24 | 943170000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1201122805 | May 02 12:29:00 PM PDT 24 | May 02 12:29:09 PM PDT 24 | 1449150000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2009879810 | May 02 12:25:17 PM PDT 24 | May 02 12:25:28 PM PDT 24 | 1471910000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1146899292 | May 02 12:30:05 PM PDT 24 | May 02 12:30:16 PM PDT 24 | 1515350000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3255413044 | May 02 12:29:48 PM PDT 24 | May 02 12:30:00 PM PDT 24 | 1505650000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3748609537 | May 02 12:29:18 PM PDT 24 | May 02 12:29:29 PM PDT 24 | 1516170000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2844721823 | May 02 12:26:08 PM PDT 24 | May 02 12:26:21 PM PDT 24 | 1456670000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2176367216 | May 02 12:28:46 PM PDT 24 | May 02 12:28:57 PM PDT 24 | 1371450000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1365113810 | May 02 12:29:18 PM PDT 24 | May 02 12:29:32 PM PDT 24 | 1535850000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2171934002 | May 02 12:28:46 PM PDT 24 | May 02 12:28:58 PM PDT 24 | 1528450000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4228185201 | May 02 12:30:01 PM PDT 24 | May 02 12:30:10 PM PDT 24 | 1500510000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.200215114 | May 02 12:29:33 PM PDT 24 | May 02 12:29:46 PM PDT 24 | 1569270000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2326107558 | May 02 12:29:07 PM PDT 24 | May 02 12:29:19 PM PDT 24 | 1583850000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.420265531 | May 02 12:29:34 PM PDT 24 | May 02 12:29:46 PM PDT 24 | 1549830000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3343162524 | May 02 12:29:18 PM PDT 24 | May 02 12:29:29 PM PDT 24 | 1177990000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3173384069 | May 02 12:29:34 PM PDT 24 | May 02 12:29:45 PM PDT 24 | 1276510000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3964017128 | May 02 12:29:00 PM PDT 24 | May 02 12:29:08 PM PDT 24 | 1094570000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2597319053 | May 02 12:30:09 PM PDT 24 | May 02 12:30:21 PM PDT 24 | 1581070000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2541863166 | May 02 12:28:46 PM PDT 24 | May 02 12:28:57 PM PDT 24 | 1514530000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.753107378 | May 02 12:28:14 PM PDT 24 | May 02 12:28:22 PM PDT 24 | 1285590000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3762198658 | May 02 12:25:28 PM PDT 24 | May 02 12:25:39 PM PDT 24 | 1226630000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.672988581 | May 02 12:29:07 PM PDT 24 | May 02 12:29:17 PM PDT 24 | 1162830000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1556742100 | May 02 12:25:18 PM PDT 24 | May 02 12:25:26 PM PDT 24 | 1460730000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3664728347 | May 02 12:30:02 PM PDT 24 | May 02 12:30:11 PM PDT 24 | 1472510000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2607013430 | May 02 12:29:04 PM PDT 24 | May 02 12:29:16 PM PDT 24 | 1483390000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1028041693 | May 02 12:29:02 PM PDT 24 | May 02 12:29:13 PM PDT 24 | 1189090000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1073798095 | May 02 12:30:06 PM PDT 24 | May 02 12:30:15 PM PDT 24 | 1256310000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.415125654 | May 02 12:27:18 PM PDT 24 | May 02 12:27:29 PM PDT 24 | 1463050000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2409034427 | May 02 12:27:25 PM PDT 24 | May 02 12:27:36 PM PDT 24 | 1458710000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2032712093 | May 02 12:29:07 PM PDT 24 | May 02 12:29:19 PM PDT 24 | 1544930000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3730345867 | May 02 12:25:38 PM PDT 24 | May 02 12:25:49 PM PDT 24 | 1501810000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2278045578 | May 02 12:30:08 PM PDT 24 | May 02 12:30:18 PM PDT 24 | 1506590000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2250778761 | May 02 12:26:40 PM PDT 24 | May 02 12:26:51 PM PDT 24 | 1424690000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1201669378 | May 02 12:29:03 PM PDT 24 | May 02 12:29:16 PM PDT 24 | 1351190000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.841374326 | May 02 12:29:33 PM PDT 24 | May 02 12:29:45 PM PDT 24 | 1419410000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1082324481 | May 02 12:30:05 PM PDT 24 | May 02 12:30:15 PM PDT 24 | 1495290000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2831744094 | May 02 12:29:34 PM PDT 24 | May 02 12:29:45 PM PDT 24 | 1416870000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3658521611 | May 02 12:30:05 PM PDT 24 | May 02 12:30:17 PM PDT 24 | 1501650000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2931175103 | May 02 12:26:05 PM PDT 24 | May 02 12:26:16 PM PDT 24 | 1418890000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3620544054 | May 02 02:05:43 PM PDT 24 | May 02 02:36:09 PM PDT 24 | 336306850000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2346169992 | May 02 02:06:00 PM PDT 24 | May 02 02:37:12 PM PDT 24 | 336327530000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2258481410 | May 02 02:05:45 PM PDT 24 | May 02 02:39:18 PM PDT 24 | 336909070000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1174523589 | May 02 02:05:44 PM PDT 24 | May 02 02:42:22 PM PDT 24 | 336671350000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3877068997 | May 02 02:05:44 PM PDT 24 | May 02 02:36:59 PM PDT 24 | 337059290000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3701221354 | May 02 02:05:51 PM PDT 24 | May 02 02:37:31 PM PDT 24 | 336368690000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1822930117 | May 02 02:05:42 PM PDT 24 | May 02 02:37:30 PM PDT 24 | 337099130000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1441354628 | May 02 02:05:51 PM PDT 24 | May 02 02:35:39 PM PDT 24 | 336484150000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.509270258 | May 02 02:05:44 PM PDT 24 | May 02 02:41:13 PM PDT 24 | 336660170000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.756601230 | May 02 02:06:01 PM PDT 24 | May 02 02:36:21 PM PDT 24 | 336937290000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.775041050 | May 02 02:05:45 PM PDT 24 | May 02 02:39:02 PM PDT 24 | 336710950000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3168199515 | May 02 02:05:53 PM PDT 24 | May 02 02:37:50 PM PDT 24 | 336590510000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3294479847 | May 02 02:05:44 PM PDT 24 | May 02 02:36:52 PM PDT 24 | 336945330000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2451998367 | May 02 02:06:01 PM PDT 24 | May 02 02:41:26 PM PDT 24 | 337090270000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3483016379 | May 02 02:05:53 PM PDT 24 | May 02 02:39:25 PM PDT 24 | 336351510000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1244689456 | May 02 02:05:52 PM PDT 24 | May 02 02:36:25 PM PDT 24 | 336638470000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.505989066 | May 02 02:05:52 PM PDT 24 | May 02 02:37:58 PM PDT 24 | 336402430000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2893052226 | May 02 02:06:00 PM PDT 24 | May 02 02:39:51 PM PDT 24 | 336850510000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2260613375 | May 02 02:05:46 PM PDT 24 | May 02 02:41:50 PM PDT 24 | 336734570000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.247110865 | May 02 02:05:59 PM PDT 24 | May 02 02:38:50 PM PDT 24 | 336992610000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.684070490 | May 02 02:05:52 PM PDT 24 | May 02 02:37:10 PM PDT 24 | 337055210000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.637539097 | May 02 02:06:00 PM PDT 24 | May 02 02:40:23 PM PDT 24 | 336814190000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.207980147 | May 02 02:05:51 PM PDT 24 | May 02 02:35:28 PM PDT 24 | 336320690000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3314345189 | May 02 02:05:44 PM PDT 24 | May 02 02:30:55 PM PDT 24 | 336783530000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3286664574 | May 02 02:05:44 PM PDT 24 | May 02 02:40:07 PM PDT 24 | 336608710000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1127062138 | May 02 02:05:53 PM PDT 24 | May 02 02:38:48 PM PDT 24 | 336496030000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2084690118 | May 02 02:05:59 PM PDT 24 | May 02 02:33:54 PM PDT 24 | 336668110000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4033141462 | May 02 02:05:51 PM PDT 24 | May 02 02:42:13 PM PDT 24 | 336397390000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1080809319 | May 02 02:06:03 PM PDT 24 | May 02 02:42:45 PM PDT 24 | 336652230000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.40781974 | May 02 02:06:00 PM PDT 24 | May 02 02:47:37 PM PDT 24 | 336440330000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3121732188 | May 02 02:05:42 PM PDT 24 | May 02 02:35:22 PM PDT 24 | 336467430000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1664303010 | May 02 02:05:59 PM PDT 24 | May 02 02:33:35 PM PDT 24 | 336527690000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2392908587 | May 02 02:05:54 PM PDT 24 | May 02 02:36:41 PM PDT 24 | 336926610000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1581440307 | May 02 02:05:44 PM PDT 24 | May 02 02:37:04 PM PDT 24 | 336991750000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2524372360 | May 02 02:05:51 PM PDT 24 | May 02 02:32:06 PM PDT 24 | 336510870000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3365495852 | May 02 02:05:46 PM PDT 24 | May 02 02:41:57 PM PDT 24 | 336885330000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.184231066 | May 02 02:05:52 PM PDT 24 | May 02 02:32:51 PM PDT 24 | 336759830000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2060126277 | May 02 02:06:01 PM PDT 24 | May 02 02:37:21 PM PDT 24 | 337069030000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2389421526 | May 02 02:05:43 PM PDT 24 | May 02 02:40:41 PM PDT 24 | 336656370000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4120687228 | May 02 02:05:45 PM PDT 24 | May 02 02:39:21 PM PDT 24 | 336583090000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.177596680 | May 02 02:05:44 PM PDT 24 | May 02 02:36:22 PM PDT 24 | 336792090000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2968675081 | May 02 02:06:04 PM PDT 24 | May 02 02:37:47 PM PDT 24 | 336657810000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2593568945 | May 02 02:05:52 PM PDT 24 | May 02 02:33:15 PM PDT 24 | 337007270000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.185818887 | May 02 02:05:44 PM PDT 24 | May 02 02:38:14 PM PDT 24 | 336570210000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2848339440 | May 02 02:06:01 PM PDT 24 | May 02 02:39:43 PM PDT 24 | 336770610000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.173828925 | May 02 02:05:52 PM PDT 24 | May 02 02:35:02 PM PDT 24 | 336674250000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2373546362 | May 02 02:05:45 PM PDT 24 | May 02 02:38:30 PM PDT 24 | 337021010000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3766328299 | May 02 02:05:45 PM PDT 24 | May 02 02:37:08 PM PDT 24 | 336684050000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4095723716 | May 02 02:05:43 PM PDT 24 | May 02 02:37:22 PM PDT 24 | 336837790000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2139250863 | May 02 02:05:43 PM PDT 24 | May 02 02:47:00 PM PDT 24 | 336423030000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2209724302 | May 02 12:31:50 PM PDT 24 | May 02 01:03:31 PM PDT 24 | 336881730000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1401293666 | May 02 12:30:42 PM PDT 24 | May 02 12:53:23 PM PDT 24 | 336774290000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1744785762 | May 02 12:30:51 PM PDT 24 | May 02 12:58:33 PM PDT 24 | 336884110000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1809392722 | May 02 12:31:50 PM PDT 24 | May 02 01:03:34 PM PDT 24 | 336575650000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2770689071 | May 02 12:29:17 PM PDT 24 | May 02 12:57:32 PM PDT 24 | 337091430000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2756831258 | May 02 12:31:49 PM PDT 24 | May 02 01:05:02 PM PDT 24 | 336304810000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1787451677 | May 02 12:30:50 PM PDT 24 | May 02 12:55:13 PM PDT 24 | 337002090000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1090924974 | May 02 12:29:17 PM PDT 24 | May 02 12:57:34 PM PDT 24 | 336415930000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3497278732 | May 02 12:30:52 PM PDT 24 | May 02 01:02:10 PM PDT 24 | 336742330000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.396708565 | May 02 12:29:04 PM PDT 24 | May 02 01:08:12 PM PDT 24 | 336506530000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3505365710 | May 02 12:30:42 PM PDT 24 | May 02 12:56:24 PM PDT 24 | 336711910000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3562295168 | May 02 12:29:34 PM PDT 24 | May 02 12:59:44 PM PDT 24 | 336855910000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.363386600 | May 02 12:31:49 PM PDT 24 | May 02 01:05:00 PM PDT 24 | 336524290000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3310259782 | May 02 12:29:04 PM PDT 24 | May 02 01:08:12 PM PDT 24 | 336749570000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2247669360 | May 02 12:30:41 PM PDT 24 | May 02 01:00:31 PM PDT 24 | 336635190000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3951548294 | May 02 12:29:19 PM PDT 24 | May 02 12:55:06 PM PDT 24 | 336959730000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1639875358 | May 02 12:30:54 PM PDT 24 | May 02 01:06:17 PM PDT 24 | 337054030000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.575732689 | May 02 12:29:03 PM PDT 24 | May 02 01:08:32 PM PDT 24 | 337051310000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.472036277 | May 02 12:23:56 PM PDT 24 | May 02 12:53:19 PM PDT 24 | 337061830000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2873556563 | May 02 12:31:04 PM PDT 24 | May 02 01:00:55 PM PDT 24 | 336519890000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1650728378 | May 02 12:26:34 PM PDT 24 | May 02 12:54:16 PM PDT 24 | 336423290000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.246221242 | May 02 12:30:53 PM PDT 24 | May 02 12:58:20 PM PDT 24 | 336564670000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1224913345 | May 02 12:30:57 PM PDT 24 | May 02 01:05:41 PM PDT 24 | 336961670000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1169313882 | May 02 12:30:50 PM PDT 24 | May 02 12:57:09 PM PDT 24 | 336550870000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2754694063 | May 02 12:30:47 PM PDT 24 | May 02 01:05:58 PM PDT 24 | 336627670000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1521214881 | May 02 12:30:47 PM PDT 24 | May 02 01:05:21 PM PDT 24 | 336557330000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.158567454 | May 02 12:30:54 PM PDT 24 | May 02 12:56:46 PM PDT 24 | 336993270000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3846083035 | May 02 12:29:43 PM PDT 24 | May 02 01:00:29 PM PDT 24 | 336940950000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3305942280 | May 02 12:31:50 PM PDT 24 | May 02 01:04:27 PM PDT 24 | 336555430000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2898984029 | May 02 12:30:47 PM PDT 24 | May 02 01:10:23 PM PDT 24 | 336741430000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3080615316 | May 02 12:30:54 PM PDT 24 | May 02 01:00:21 PM PDT 24 | 336848650000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1741762838 | May 02 12:30:50 PM PDT 24 | May 02 01:01:41 PM PDT 24 | 336745450000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4132125303 | May 02 12:29:19 PM PDT 24 | May 02 12:55:06 PM PDT 24 | 336539290000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.64163560 | May 02 12:30:37 PM PDT 24 | May 02 01:10:14 PM PDT 24 | 336741530000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2191528170 | May 02 12:29:31 PM PDT 24 | May 02 12:56:04 PM PDT 24 | 336481690000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2108238375 | May 02 12:30:56 PM PDT 24 | May 02 12:58:58 PM PDT 24 | 336443670000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.654901325 | May 02 12:27:27 PM PDT 24 | May 02 12:51:42 PM PDT 24 | 336660250000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4142400195 | May 02 12:30:56 PM PDT 24 | May 02 12:56:53 PM PDT 24 | 336719630000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.775587654 | May 02 12:31:06 PM PDT 24 | May 02 12:56:08 PM PDT 24 | 336377270000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1868124496 | May 02 12:30:52 PM PDT 24 | May 02 01:06:00 PM PDT 24 | 336960270000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3563370736 | May 02 12:30:56 PM PDT 24 | May 02 12:56:40 PM PDT 24 | 336951650000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2887500088 | May 02 12:31:16 PM PDT 24 | May 02 01:01:35 PM PDT 24 | 336671430000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.405703274 | May 02 12:30:35 PM PDT 24 | May 02 12:58:08 PM PDT 24 | 336352050000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3537652218 | May 02 12:31:49 PM PDT 24 | May 02 01:04:58 PM PDT 24 | 337050950000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.627520145 | May 02 12:31:03 PM PDT 24 | May 02 12:56:43 PM PDT 24 | 337048090000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1424035905 | May 02 12:29:39 PM PDT 24 | May 02 12:56:59 PM PDT 24 | 336558430000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.662151565 | May 02 12:29:43 PM PDT 24 | May 02 01:00:16 PM PDT 24 | 337096330000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.297472422 | May 02 12:31:04 PM PDT 24 | May 02 12:56:47 PM PDT 24 | 336423830000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3983751446 | May 02 12:29:41 PM PDT 24 | May 02 12:59:36 PM PDT 24 | 336499610000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.317655351 | May 02 12:30:47 PM PDT 24 | May 02 12:56:30 PM PDT 24 | 337068650000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3887821688 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1421790000 ps |
| CPU time | 3.22 seconds |
| Started | May 02 12:30:42 PM PDT 24 |
| Finished | May 02 12:30:55 PM PDT 24 |
| Peak memory | 164464 kb |
| Host | smart-b820aca9-56c5-4dee-b86a-82c8a0b7d8e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3887821688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3887821688 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1174523589 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336671350000 ps |
| CPU time | 880.68 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:42:22 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-b7442fbb-12fe-408e-8bee-67eed23a32d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1174523589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1174523589 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1090924974 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336415930000 ps |
| CPU time | 692.23 seconds |
| Started | May 02 12:29:17 PM PDT 24 |
| Finished | May 02 12:57:34 PM PDT 24 |
| Peak memory | 159356 kb |
| Host | smart-fbe25c17-08a1-41b7-84e0-549f87dc189f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1090924974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1090924974 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3110316167 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1149310000 ps |
| CPU time | 2.53 seconds |
| Started | May 02 12:28:12 PM PDT 24 |
| Finished | May 02 12:28:18 PM PDT 24 |
| Peak memory | 164560 kb |
| Host | smart-f3c766d6-f7db-4e38-ae49-d84abe0b321e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3110316167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3110316167 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1424035905 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336558430000 ps |
| CPU time | 662.58 seconds |
| Started | May 02 12:29:39 PM PDT 24 |
| Finished | May 02 12:56:59 PM PDT 24 |
| Peak memory | 160336 kb |
| Host | smart-ba14b538-34aa-435f-b2fe-6a6d6ee18b6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1424035905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1424035905 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3846083035 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336940950000 ps |
| CPU time | 736.9 seconds |
| Started | May 02 12:29:43 PM PDT 24 |
| Finished | May 02 01:00:29 PM PDT 24 |
| Peak memory | 160232 kb |
| Host | smart-94e7a3af-18dd-4ad1-b8e8-38d7e021ecdb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3846083035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3846083035 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3562295168 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336855910000 ps |
| CPU time | 733.22 seconds |
| Started | May 02 12:29:34 PM PDT 24 |
| Finished | May 02 12:59:44 PM PDT 24 |
| Peak memory | 159112 kb |
| Host | smart-fb151554-0fa2-434f-bff5-52eb515e7496 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3562295168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3562295168 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4132125303 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336539290000 ps |
| CPU time | 628.16 seconds |
| Started | May 02 12:29:19 PM PDT 24 |
| Finished | May 02 12:55:06 PM PDT 24 |
| Peak memory | 158972 kb |
| Host | smart-6da06ab6-fc6d-4d16-88fa-a95581fc8bc1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4132125303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4132125303 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.472036277 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 337061830000 ps |
| CPU time | 710.04 seconds |
| Started | May 02 12:23:56 PM PDT 24 |
| Finished | May 02 12:53:19 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-2b09ad09-44ae-4158-949f-348ee0880b7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=472036277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.472036277 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3951548294 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336959730000 ps |
| CPU time | 630.91 seconds |
| Started | May 02 12:29:19 PM PDT 24 |
| Finished | May 02 12:55:06 PM PDT 24 |
| Peak memory | 158928 kb |
| Host | smart-f791adbb-8bdf-42dd-91af-f7284c34a966 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3951548294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3951548294 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1650728378 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336423290000 ps |
| CPU time | 665.59 seconds |
| Started | May 02 12:26:34 PM PDT 24 |
| Finished | May 02 12:54:16 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-1ede3064-028a-46b3-8706-8b9ce1dc43d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1650728378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1650728378 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2873556563 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336519890000 ps |
| CPU time | 727.72 seconds |
| Started | May 02 12:31:04 PM PDT 24 |
| Finished | May 02 01:00:55 PM PDT 24 |
| Peak memory | 160428 kb |
| Host | smart-94251bcc-beff-4e07-a798-ae281ce2c4dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2873556563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2873556563 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1809392722 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336575650000 ps |
| CPU time | 756.71 seconds |
| Started | May 02 12:31:50 PM PDT 24 |
| Finished | May 02 01:03:34 PM PDT 24 |
| Peak memory | 159472 kb |
| Host | smart-c8d22a5d-f684-4e46-abc4-988b7ff5bc24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1809392722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1809392722 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2754694063 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336627670000 ps |
| CPU time | 841.5 seconds |
| Started | May 02 12:30:47 PM PDT 24 |
| Finished | May 02 01:05:58 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-75ba8695-ce98-4f03-b466-0f8aa705def6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2754694063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2754694063 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1169313882 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336550870000 ps |
| CPU time | 624.59 seconds |
| Started | May 02 12:30:50 PM PDT 24 |
| Finished | May 02 12:57:09 PM PDT 24 |
| Peak memory | 160500 kb |
| Host | smart-66e0f00f-4994-4993-a903-32523a1a983e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1169313882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1169313882 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.396708565 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336506530000 ps |
| CPU time | 930.75 seconds |
| Started | May 02 12:29:04 PM PDT 24 |
| Finished | May 02 01:08:12 PM PDT 24 |
| Peak memory | 160260 kb |
| Host | smart-b2bf898d-d0bd-4d9b-b6f7-d93155d6f310 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=396708565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.396708565 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1639875358 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 337054030000 ps |
| CPU time | 851.33 seconds |
| Started | May 02 12:30:54 PM PDT 24 |
| Finished | May 02 01:06:17 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-006a8b53-aca7-45a6-8815-608516e80017 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1639875358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1639875358 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1224913345 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336961670000 ps |
| CPU time | 827.23 seconds |
| Started | May 02 12:30:57 PM PDT 24 |
| Finished | May 02 01:05:41 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-d04ffca4-d9bb-4430-ba4f-c75e3df574c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1224913345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1224913345 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1521214881 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336557330000 ps |
| CPU time | 834.44 seconds |
| Started | May 02 12:30:47 PM PDT 24 |
| Finished | May 02 01:05:21 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-3697cf2c-eb7b-4d55-bf5d-7229814e0d38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1521214881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1521214881 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3537652218 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 337050950000 ps |
| CPU time | 789.32 seconds |
| Started | May 02 12:31:49 PM PDT 24 |
| Finished | May 02 01:04:58 PM PDT 24 |
| Peak memory | 158228 kb |
| Host | smart-686611e7-2fde-4858-97dc-81708355583b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3537652218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3537652218 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2756831258 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336304810000 ps |
| CPU time | 790.02 seconds |
| Started | May 02 12:31:49 PM PDT 24 |
| Finished | May 02 01:05:02 PM PDT 24 |
| Peak memory | 158584 kb |
| Host | smart-761c46dd-241f-4880-8808-17edacc38b3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2756831258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2756831258 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.363386600 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336524290000 ps |
| CPU time | 794.17 seconds |
| Started | May 02 12:31:49 PM PDT 24 |
| Finished | May 02 01:05:00 PM PDT 24 |
| Peak memory | 158904 kb |
| Host | smart-d8d120c1-b74c-4163-aa9b-75997a131467 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=363386600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.363386600 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3080615316 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336848650000 ps |
| CPU time | 713.53 seconds |
| Started | May 02 12:30:54 PM PDT 24 |
| Finished | May 02 01:00:21 PM PDT 24 |
| Peak memory | 160500 kb |
| Host | smart-34d98916-ef2d-4f42-a046-80b2a6e22c84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3080615316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3080615316 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3505365710 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336711910000 ps |
| CPU time | 623.66 seconds |
| Started | May 02 12:30:42 PM PDT 24 |
| Finished | May 02 12:56:24 PM PDT 24 |
| Peak memory | 160420 kb |
| Host | smart-245fb070-506d-4fef-88ef-82ebeddbe978 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3505365710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3505365710 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1868124496 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336960270000 ps |
| CPU time | 837.78 seconds |
| Started | May 02 12:30:52 PM PDT 24 |
| Finished | May 02 01:06:00 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-c7b8d2de-859f-4a84-8b6a-a0c7bfb5d8c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1868124496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1868124496 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3305942280 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336555430000 ps |
| CPU time | 770.24 seconds |
| Started | May 02 12:31:50 PM PDT 24 |
| Finished | May 02 01:04:27 PM PDT 24 |
| Peak memory | 158604 kb |
| Host | smart-d15788be-bcdb-46b7-8e34-2bb13add0cd1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3305942280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3305942280 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.654901325 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336660250000 ps |
| CPU time | 569.81 seconds |
| Started | May 02 12:27:27 PM PDT 24 |
| Finished | May 02 12:51:42 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-d0491af6-a94d-4ade-a977-166d518f3043 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=654901325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.654901325 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3563370736 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336951650000 ps |
| CPU time | 631.01 seconds |
| Started | May 02 12:30:56 PM PDT 24 |
| Finished | May 02 12:56:40 PM PDT 24 |
| Peak memory | 160428 kb |
| Host | smart-f1ce054e-857a-419d-8ddd-eea72bb1c596 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3563370736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3563370736 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.158567454 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336993270000 ps |
| CPU time | 624.75 seconds |
| Started | May 02 12:30:54 PM PDT 24 |
| Finished | May 02 12:56:46 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-50fed289-d1ce-40b4-ae6b-8bd173461760 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=158567454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.158567454 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.405703274 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336352050000 ps |
| CPU time | 668.99 seconds |
| Started | May 02 12:30:35 PM PDT 24 |
| Finished | May 02 12:58:08 PM PDT 24 |
| Peak memory | 160504 kb |
| Host | smart-5a90f6c6-0d19-4c03-b560-f5b9cc51dd11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=405703274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.405703274 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.64163560 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336741530000 ps |
| CPU time | 945.87 seconds |
| Started | May 02 12:30:37 PM PDT 24 |
| Finished | May 02 01:10:14 PM PDT 24 |
| Peak memory | 160512 kb |
| Host | smart-6a33dc62-906e-4962-93f0-9bbc8d03e8ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=64163560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.64163560 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.297472422 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336423830000 ps |
| CPU time | 610.27 seconds |
| Started | May 02 12:31:04 PM PDT 24 |
| Finished | May 02 12:56:47 PM PDT 24 |
| Peak memory | 160480 kb |
| Host | smart-f6f28e41-f60b-4275-95b3-22dc261c4e1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=297472422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.297472422 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2209724302 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336881730000 ps |
| CPU time | 751.75 seconds |
| Started | May 02 12:31:50 PM PDT 24 |
| Finished | May 02 01:03:31 PM PDT 24 |
| Peak memory | 160148 kb |
| Host | smart-bb927b74-9ff3-4dc3-b573-1deb7b09af3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2209724302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2209724302 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2247669360 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336635190000 ps |
| CPU time | 724.53 seconds |
| Started | May 02 12:30:41 PM PDT 24 |
| Finished | May 02 01:00:31 PM PDT 24 |
| Peak memory | 160404 kb |
| Host | smart-871406f2-017e-4350-928d-bc10e4f60cb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2247669360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2247669360 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1401293666 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336774290000 ps |
| CPU time | 535.9 seconds |
| Started | May 02 12:30:42 PM PDT 24 |
| Finished | May 02 12:53:23 PM PDT 24 |
| Peak memory | 160428 kb |
| Host | smart-efdb9592-1aa9-47fd-9ba4-fa6fbb910191 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1401293666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1401293666 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3497278732 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336742330000 ps |
| CPU time | 748.08 seconds |
| Started | May 02 12:30:52 PM PDT 24 |
| Finished | May 02 01:02:10 PM PDT 24 |
| Peak memory | 160244 kb |
| Host | smart-8e802dcc-248e-43f9-870a-8622c51b8022 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3497278732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3497278732 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.627520145 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337048090000 ps |
| CPU time | 620.3 seconds |
| Started | May 02 12:31:03 PM PDT 24 |
| Finished | May 02 12:56:43 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-770ff5e2-c681-461c-8217-7ae92dc64342 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=627520145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.627520145 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3310259782 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336749570000 ps |
| CPU time | 939.19 seconds |
| Started | May 02 12:29:04 PM PDT 24 |
| Finished | May 02 01:08:12 PM PDT 24 |
| Peak memory | 160260 kb |
| Host | smart-18768c00-5dd4-44fe-8d8c-b2c4fa926886 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3310259782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3310259782 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4142400195 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336719630000 ps |
| CPU time | 627.35 seconds |
| Started | May 02 12:30:56 PM PDT 24 |
| Finished | May 02 12:56:53 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-5c13aff8-e6cd-494f-9cea-17c0d49edea5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4142400195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4142400195 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1787451677 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 337002090000 ps |
| CPU time | 585.81 seconds |
| Started | May 02 12:30:50 PM PDT 24 |
| Finished | May 02 12:55:13 PM PDT 24 |
| Peak memory | 160416 kb |
| Host | smart-a2b0c526-5b72-4f4f-8976-079df2009421 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1787451677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1787451677 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1741762838 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336745450000 ps |
| CPU time | 744.47 seconds |
| Started | May 02 12:30:50 PM PDT 24 |
| Finished | May 02 01:01:41 PM PDT 24 |
| Peak memory | 159748 kb |
| Host | smart-6b2ad47b-4e1a-449a-b253-623bcf3ddc23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1741762838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1741762838 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.317655351 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 337068650000 ps |
| CPU time | 617.4 seconds |
| Started | May 02 12:30:47 PM PDT 24 |
| Finished | May 02 12:56:30 PM PDT 24 |
| Peak memory | 160380 kb |
| Host | smart-a000d8af-b4f7-46df-8967-d98338fcc363 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=317655351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.317655351 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2887500088 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336671430000 ps |
| CPU time | 742.27 seconds |
| Started | May 02 12:31:16 PM PDT 24 |
| Finished | May 02 01:01:35 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-b86c2622-70c7-4e64-b5b8-c9db08735b52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2887500088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2887500088 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1744785762 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336884110000 ps |
| CPU time | 668.86 seconds |
| Started | May 02 12:30:51 PM PDT 24 |
| Finished | May 02 12:58:33 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-f7cb0146-a25f-475c-8782-9a9b87bd7a31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1744785762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1744785762 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.246221242 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336564670000 ps |
| CPU time | 657.24 seconds |
| Started | May 02 12:30:53 PM PDT 24 |
| Finished | May 02 12:58:20 PM PDT 24 |
| Peak memory | 160464 kb |
| Host | smart-dd53be7d-5079-40b7-b529-ea9b58e7d490 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=246221242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.246221242 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2108238375 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336443670000 ps |
| CPU time | 674.33 seconds |
| Started | May 02 12:30:56 PM PDT 24 |
| Finished | May 02 12:58:58 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-73bb3830-5a58-422e-8c75-8ba4d6c23f81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2108238375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2108238375 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.775587654 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336377270000 ps |
| CPU time | 604.87 seconds |
| Started | May 02 12:31:06 PM PDT 24 |
| Finished | May 02 12:56:08 PM PDT 24 |
| Peak memory | 160412 kb |
| Host | smart-35ce6f58-8079-4b06-b4d5-f30227879c5a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=775587654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.775587654 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2898984029 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336741430000 ps |
| CPU time | 945.07 seconds |
| Started | May 02 12:30:47 PM PDT 24 |
| Finished | May 02 01:10:23 PM PDT 24 |
| Peak memory | 160520 kb |
| Host | smart-c7c5f038-8cd0-438b-be46-1902b519257e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2898984029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2898984029 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3983751446 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336499610000 ps |
| CPU time | 715.81 seconds |
| Started | May 02 12:29:41 PM PDT 24 |
| Finished | May 02 12:59:36 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-8513acf9-6d24-4362-9d6d-625060ddadd5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3983751446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3983751446 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.575732689 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 337051310000 ps |
| CPU time | 947.37 seconds |
| Started | May 02 12:29:03 PM PDT 24 |
| Finished | May 02 01:08:32 PM PDT 24 |
| Peak memory | 160252 kb |
| Host | smart-ead234fd-dce6-4069-82ab-4396f5f22fb7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=575732689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.575732689 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2191528170 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336481690000 ps |
| CPU time | 657.03 seconds |
| Started | May 02 12:29:31 PM PDT 24 |
| Finished | May 02 12:56:04 PM PDT 24 |
| Peak memory | 159588 kb |
| Host | smart-c8c56ca4-3c63-47f2-8aca-083a09508940 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2191528170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2191528170 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.662151565 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 337096330000 ps |
| CPU time | 731.16 seconds |
| Started | May 02 12:29:43 PM PDT 24 |
| Finished | May 02 01:00:16 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-2c4ff7d2-7443-43af-988a-973bbfad2229 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=662151565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.662151565 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2770689071 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 337091430000 ps |
| CPU time | 685.2 seconds |
| Started | May 02 12:29:17 PM PDT 24 |
| Finished | May 02 12:57:32 PM PDT 24 |
| Peak memory | 159452 kb |
| Host | smart-58227f37-f0b7-4df7-bd21-2d0c6e17e0fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2770689071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2770689071 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3365495852 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336885330000 ps |
| CPU time | 864.11 seconds |
| Started | May 02 02:05:46 PM PDT 24 |
| Finished | May 02 02:41:57 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-3d70c04c-216e-4fbd-ba5b-8c5a7ba5325b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3365495852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3365495852 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2389421526 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336656370000 ps |
| CPU time | 852.42 seconds |
| Started | May 02 02:05:43 PM PDT 24 |
| Finished | May 02 02:40:41 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-de303727-fca9-4472-acfd-d162e10befa7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2389421526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2389421526 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1581440307 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336991750000 ps |
| CPU time | 757.06 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:37:04 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-2e5c5e15-c5c2-49e7-9f36-3cf136cd2d30 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1581440307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1581440307 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4095723716 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336837790000 ps |
| CPU time | 789.55 seconds |
| Started | May 02 02:05:43 PM PDT 24 |
| Finished | May 02 02:37:22 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-4e8a42bf-d0f2-4b0b-b72e-d6c9dcce1415 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4095723716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4095723716 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.509270258 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336660170000 ps |
| CPU time | 852.97 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:41:13 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-00002405-939b-49cb-b9ee-ae46e9e56edc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=509270258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.509270258 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3620544054 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336306850000 ps |
| CPU time | 744.49 seconds |
| Started | May 02 02:05:43 PM PDT 24 |
| Finished | May 02 02:36:09 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-2573e108-2e04-484e-a4ae-e52416930107 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3620544054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3620544054 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.185818887 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336570210000 ps |
| CPU time | 797.22 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:38:14 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-2bed9c5b-c9cf-4bc4-8217-fdcb5589c888 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=185818887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.185818887 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1822930117 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 337099130000 ps |
| CPU time | 770.05 seconds |
| Started | May 02 02:05:42 PM PDT 24 |
| Finished | May 02 02:37:30 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-b12abe18-4ecf-4ae8-8fb8-8527ceee5ee8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1822930117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1822930117 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2373546362 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 337021010000 ps |
| CPU time | 797.01 seconds |
| Started | May 02 02:05:45 PM PDT 24 |
| Finished | May 02 02:38:30 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-3071b6f6-9b69-4727-9995-ca7e321ed6b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2373546362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2373546362 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3121732188 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336467430000 ps |
| CPU time | 722.59 seconds |
| Started | May 02 02:05:42 PM PDT 24 |
| Finished | May 02 02:35:22 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-58f3cd64-7914-4cc1-983b-3d79a78e42de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3121732188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3121732188 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2260613375 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336734570000 ps |
| CPU time | 866.98 seconds |
| Started | May 02 02:05:46 PM PDT 24 |
| Finished | May 02 02:41:50 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-39a0bba9-aaa4-4a01-b7a4-b6824af8746d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2260613375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2260613375 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2139250863 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336423030000 ps |
| CPU time | 977.6 seconds |
| Started | May 02 02:05:43 PM PDT 24 |
| Finished | May 02 02:47:00 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-51a5334d-d4fb-432d-8698-2cfdac65b31e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2139250863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2139250863 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3294479847 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336945330000 ps |
| CPU time | 741.62 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:36:52 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-675e9256-eb55-4282-8261-aa70cae53723 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3294479847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3294479847 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.775041050 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336710950000 ps |
| CPU time | 801.66 seconds |
| Started | May 02 02:05:45 PM PDT 24 |
| Finished | May 02 02:39:02 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-99dff86f-9775-441f-ac9b-c3bdae1feea9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=775041050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.775041050 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.505989066 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336402430000 ps |
| CPU time | 790.61 seconds |
| Started | May 02 02:05:52 PM PDT 24 |
| Finished | May 02 02:37:58 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-4fa42b46-fd66-455e-95f9-7db80cb0a74d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=505989066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.505989066 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.207980147 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336320690000 ps |
| CPU time | 722.44 seconds |
| Started | May 02 02:05:51 PM PDT 24 |
| Finished | May 02 02:35:28 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-92cf0399-6ed8-4215-b2ac-c7fc4029b68b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=207980147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.207980147 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.684070490 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 337055210000 ps |
| CPU time | 745.98 seconds |
| Started | May 02 02:05:52 PM PDT 24 |
| Finished | May 02 02:37:10 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-a0f4b339-efbb-4b27-a553-d80192c7a34a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=684070490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.684070490 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.184231066 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336759830000 ps |
| CPU time | 641.57 seconds |
| Started | May 02 02:05:52 PM PDT 24 |
| Finished | May 02 02:32:51 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-0fd099c2-27bd-481e-8d70-887c9a3288ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=184231066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.184231066 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2524372360 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336510870000 ps |
| CPU time | 639.27 seconds |
| Started | May 02 02:05:51 PM PDT 24 |
| Finished | May 02 02:32:06 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-5008c34d-9b3b-42b2-a704-1f312880840e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2524372360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2524372360 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2392908587 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336926610000 ps |
| CPU time | 747.72 seconds |
| Started | May 02 02:05:54 PM PDT 24 |
| Finished | May 02 02:36:41 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-f8c45ac5-86be-4e31-b547-18aad4f902e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2392908587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2392908587 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3168199515 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336590510000 ps |
| CPU time | 761.55 seconds |
| Started | May 02 02:05:53 PM PDT 24 |
| Finished | May 02 02:37:50 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-a03458de-049f-49a3-ba47-61c6f8115923 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3168199515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3168199515 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3701221354 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336368690000 ps |
| CPU time | 764.05 seconds |
| Started | May 02 02:05:51 PM PDT 24 |
| Finished | May 02 02:37:31 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-8ea5c02a-95b6-4558-8591-4307b72364df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3701221354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3701221354 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2258481410 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336909070000 ps |
| CPU time | 806.37 seconds |
| Started | May 02 02:05:45 PM PDT 24 |
| Finished | May 02 02:39:18 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-01274f36-3b72-4cd0-83af-bc436fb28fb6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2258481410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2258481410 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1441354628 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336484150000 ps |
| CPU time | 730.39 seconds |
| Started | May 02 02:05:51 PM PDT 24 |
| Finished | May 02 02:35:39 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-2649fc2d-c780-4d62-aab9-d09ef530e3e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1441354628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1441354628 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2593568945 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 337007270000 ps |
| CPU time | 657.97 seconds |
| Started | May 02 02:05:52 PM PDT 24 |
| Finished | May 02 02:33:15 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-ab7085d6-19a5-4dcf-9e0e-b954304d66ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2593568945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2593568945 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4033141462 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336397390000 ps |
| CPU time | 874.41 seconds |
| Started | May 02 02:05:51 PM PDT 24 |
| Finished | May 02 02:42:13 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-063c945b-2de6-491b-9f2f-49328d5762d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4033141462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4033141462 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.173828925 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336674250000 ps |
| CPU time | 711.89 seconds |
| Started | May 02 02:05:52 PM PDT 24 |
| Finished | May 02 02:35:02 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-aa3db0ef-4ca5-46b5-898a-cafe7e846f22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=173828925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.173828925 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1127062138 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336496030000 ps |
| CPU time | 796.36 seconds |
| Started | May 02 02:05:53 PM PDT 24 |
| Finished | May 02 02:38:48 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-7973f349-c358-4f4f-8525-382bfdcf5c30 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1127062138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1127062138 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3483016379 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336351510000 ps |
| CPU time | 812.84 seconds |
| Started | May 02 02:05:53 PM PDT 24 |
| Finished | May 02 02:39:25 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-f8d10d48-7948-43b3-8bd6-6e912150ff37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3483016379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3483016379 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1244689456 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336638470000 ps |
| CPU time | 738.03 seconds |
| Started | May 02 02:05:52 PM PDT 24 |
| Finished | May 02 02:36:25 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-c6ab20a6-7ab8-4613-b7b6-8a9acdedd187 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1244689456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1244689456 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2346169992 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336327530000 ps |
| CPU time | 765 seconds |
| Started | May 02 02:06:00 PM PDT 24 |
| Finished | May 02 02:37:12 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-e419b47d-9cb2-4158-b8ec-ef4c07ab1e3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2346169992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2346169992 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.40781974 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336440330000 ps |
| CPU time | 959.27 seconds |
| Started | May 02 02:06:00 PM PDT 24 |
| Finished | May 02 02:47:37 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-3adbe394-e675-48b1-9c15-0f402967c560 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=40781974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.40781974 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2084690118 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336668110000 ps |
| CPU time | 682.79 seconds |
| Started | May 02 02:05:59 PM PDT 24 |
| Finished | May 02 02:33:54 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-77f1cb00-fa85-47ef-985e-1da142a90f89 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2084690118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2084690118 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3314345189 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336783530000 ps |
| CPU time | 591.94 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:30:55 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-dba2d2d7-5eca-4a4c-a3f8-bf63a0130397 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3314345189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3314345189 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2451998367 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 337090270000 ps |
| CPU time | 858.59 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:41:26 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-149aa4c5-ef63-485a-b1bf-84102f31ca09 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2451998367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2451998367 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1664303010 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336527690000 ps |
| CPU time | 677.18 seconds |
| Started | May 02 02:05:59 PM PDT 24 |
| Finished | May 02 02:33:35 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-1c064bab-29a0-40e1-970c-0a171593fed1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1664303010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1664303010 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.637539097 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336814190000 ps |
| CPU time | 839.93 seconds |
| Started | May 02 02:06:00 PM PDT 24 |
| Finished | May 02 02:40:23 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-b8b0efb7-c396-4576-9cd8-d9f2418bdda7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=637539097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.637539097 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.247110865 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336992610000 ps |
| CPU time | 796.6 seconds |
| Started | May 02 02:05:59 PM PDT 24 |
| Finished | May 02 02:38:50 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-274b2fc1-7a44-4289-8329-4c6a71fec443 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=247110865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.247110865 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.756601230 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336937290000 ps |
| CPU time | 744.8 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:36:21 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-ec1cddf5-45a9-45af-85c9-224f8e58986f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=756601230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.756601230 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2848339440 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336770610000 ps |
| CPU time | 814.76 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:39:43 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-7f8c710f-c957-4a49-be24-4c7e4dde3de3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2848339440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2848339440 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2060126277 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 337069030000 ps |
| CPU time | 769.92 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:37:21 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-25afddf8-1044-40ec-bfb9-66e1465075b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2060126277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2060126277 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2968675081 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336657810000 ps |
| CPU time | 747.59 seconds |
| Started | May 02 02:06:04 PM PDT 24 |
| Finished | May 02 02:37:47 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-0c5acbe8-a1ad-49d4-852c-6be506a590a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2968675081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2968675081 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2893052226 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336850510000 ps |
| CPU time | 825.17 seconds |
| Started | May 02 02:06:00 PM PDT 24 |
| Finished | May 02 02:39:51 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-19336182-81c1-4404-8b76-a0f97636f4ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2893052226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2893052226 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1080809319 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336652230000 ps |
| CPU time | 876.95 seconds |
| Started | May 02 02:06:03 PM PDT 24 |
| Finished | May 02 02:42:45 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-1343d562-0845-4338-8fef-e54a308ff049 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1080809319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1080809319 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3286664574 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336608710000 ps |
| CPU time | 848.52 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:40:07 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-86dd9902-2d01-43e9-bd82-26b04184e254 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3286664574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3286664574 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.177596680 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336792090000 ps |
| CPU time | 744.06 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:36:22 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-d54bd951-caa4-49a9-9656-855834fa5732 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=177596680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.177596680 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4120687228 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336583090000 ps |
| CPU time | 811.93 seconds |
| Started | May 02 02:05:45 PM PDT 24 |
| Finished | May 02 02:39:21 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-206362c7-1597-4cfa-b922-110aad5386ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4120687228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.4120687228 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3766328299 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336684050000 ps |
| CPU time | 746.16 seconds |
| Started | May 02 02:05:45 PM PDT 24 |
| Finished | May 02 02:37:08 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-fb4aca6c-4159-44cd-a889-8bd61681dcd6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3766328299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3766328299 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3877068997 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 337059290000 ps |
| CPU time | 752.67 seconds |
| Started | May 02 02:05:44 PM PDT 24 |
| Finished | May 02 02:36:59 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-3a26903f-7249-4d04-8a87-be17bcf099e9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3877068997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3877068997 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3730345867 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1501810000 ps |
| CPU time | 4.79 seconds |
| Started | May 02 12:25:38 PM PDT 24 |
| Finished | May 02 12:25:49 PM PDT 24 |
| Peak memory | 164604 kb |
| Host | smart-60014a3f-8d11-4d41-b49f-ea0e05123a38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3730345867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3730345867 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2607013430 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1483390000 ps |
| CPU time | 5.32 seconds |
| Started | May 02 12:29:04 PM PDT 24 |
| Finished | May 02 12:29:16 PM PDT 24 |
| Peak memory | 164308 kb |
| Host | smart-b6c6a422-0381-4ba1-80dd-90a810c2b4cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2607013430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2607013430 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3071739954 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1523250000 ps |
| CPU time | 4.18 seconds |
| Started | May 02 12:29:19 PM PDT 24 |
| Finished | May 02 12:29:30 PM PDT 24 |
| Peak memory | 165084 kb |
| Host | smart-08091601-8faa-46e7-b877-d04eaa52b0ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3071739954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3071739954 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2597319053 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1581070000 ps |
| CPU time | 4.36 seconds |
| Started | May 02 12:30:09 PM PDT 24 |
| Finished | May 02 12:30:21 PM PDT 24 |
| Peak memory | 164364 kb |
| Host | smart-edf6fb7b-64a2-4389-80db-25139a6bd062 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2597319053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2597319053 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2802024895 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1454850000 ps |
| CPU time | 4.44 seconds |
| Started | May 02 12:28:46 PM PDT 24 |
| Finished | May 02 12:28:57 PM PDT 24 |
| Peak memory | 162536 kb |
| Host | smart-db0a5c9a-61c6-4911-8800-ad6e16e0867f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2802024895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2802024895 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2171934002 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1528450000 ps |
| CPU time | 4.71 seconds |
| Started | May 02 12:28:46 PM PDT 24 |
| Finished | May 02 12:28:58 PM PDT 24 |
| Peak memory | 162136 kb |
| Host | smart-d36e7b29-5254-47f6-9a6b-400406422cfe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2171934002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2171934002 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1028041693 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1189090000 ps |
| CPU time | 4.5 seconds |
| Started | May 02 12:29:02 PM PDT 24 |
| Finished | May 02 12:29:13 PM PDT 24 |
| Peak memory | 164384 kb |
| Host | smart-a116a442-4b82-42c6-add7-34a33bbb7878 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1028041693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1028041693 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.415125654 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1463050000 ps |
| CPU time | 4.42 seconds |
| Started | May 02 12:27:18 PM PDT 24 |
| Finished | May 02 12:27:29 PM PDT 24 |
| Peak memory | 164568 kb |
| Host | smart-cd355eec-1da1-47f4-96ee-7a7a9d250091 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=415125654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.415125654 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1556742100 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1460730000 ps |
| CPU time | 3.44 seconds |
| Started | May 02 12:25:18 PM PDT 24 |
| Finished | May 02 12:25:26 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-a3f8e17b-1935-4e2c-be11-2add4b6936ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1556742100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1556742100 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2032712093 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1544930000 ps |
| CPU time | 4.69 seconds |
| Started | May 02 12:29:07 PM PDT 24 |
| Finished | May 02 12:29:19 PM PDT 24 |
| Peak memory | 162412 kb |
| Host | smart-3190599f-d17c-4f96-a6de-b774f5c66f78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2032712093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2032712093 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2409034427 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1458710000 ps |
| CPU time | 4.4 seconds |
| Started | May 02 12:27:25 PM PDT 24 |
| Finished | May 02 12:27:36 PM PDT 24 |
| Peak memory | 164560 kb |
| Host | smart-2daab93f-93a8-4c6f-8345-81262be6ca16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2409034427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2409034427 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3748609537 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1516170000 ps |
| CPU time | 4.18 seconds |
| Started | May 02 12:29:18 PM PDT 24 |
| Finished | May 02 12:29:29 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-183cfda6-b9aa-4fcf-af00-12716b682c0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3748609537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3748609537 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3964017128 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1094570000 ps |
| CPU time | 3.04 seconds |
| Started | May 02 12:29:00 PM PDT 24 |
| Finished | May 02 12:29:08 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-cdede631-f9b5-43d1-a3a1-221181e13c9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3964017128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3964017128 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3754141877 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1366490000 ps |
| CPU time | 4.97 seconds |
| Started | May 02 12:27:32 PM PDT 24 |
| Finished | May 02 12:27:43 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-a2397ad9-4004-4fa5-8167-aa6d2c59d1ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3754141877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3754141877 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2278045578 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1506590000 ps |
| CPU time | 4.19 seconds |
| Started | May 02 12:30:08 PM PDT 24 |
| Finished | May 02 12:30:18 PM PDT 24 |
| Peak memory | 164340 kb |
| Host | smart-878bba8c-b440-455f-8e59-92929847df50 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2278045578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2278045578 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4228185201 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1500510000 ps |
| CPU time | 3.47 seconds |
| Started | May 02 12:30:01 PM PDT 24 |
| Finished | May 02 12:30:10 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-665c1b63-9b48-43c1-8a7f-3cda2d86681c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4228185201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.4228185201 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.841374326 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1419410000 ps |
| CPU time | 4.51 seconds |
| Started | May 02 12:29:33 PM PDT 24 |
| Finished | May 02 12:29:45 PM PDT 24 |
| Peak memory | 163744 kb |
| Host | smart-540f3553-2540-4d27-9aff-afd00ab2a71b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=841374326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.841374326 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.672988581 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1162830000 ps |
| CPU time | 3.69 seconds |
| Started | May 02 12:29:07 PM PDT 24 |
| Finished | May 02 12:29:17 PM PDT 24 |
| Peak memory | 163228 kb |
| Host | smart-a9bbf1cd-a14a-4614-a385-fbef594d6349 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=672988581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.672988581 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2541863166 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1514530000 ps |
| CPU time | 4.64 seconds |
| Started | May 02 12:28:46 PM PDT 24 |
| Finished | May 02 12:28:57 PM PDT 24 |
| Peak memory | 162432 kb |
| Host | smart-53994b24-bf4e-4c10-9e9c-d1a15126363c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2541863166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2541863166 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.200215114 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1569270000 ps |
| CPU time | 4.44 seconds |
| Started | May 02 12:29:33 PM PDT 24 |
| Finished | May 02 12:29:46 PM PDT 24 |
| Peak memory | 164268 kb |
| Host | smart-81c4785b-1618-4390-836c-0dc9537840f0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=200215114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.200215114 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.955459829 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1476190000 ps |
| CPU time | 3.95 seconds |
| Started | May 02 12:30:09 PM PDT 24 |
| Finished | May 02 12:30:19 PM PDT 24 |
| Peak memory | 164360 kb |
| Host | smart-13464bd5-ed88-49c6-96e9-c9e8d565dc26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=955459829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.955459829 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3255413044 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1505650000 ps |
| CPU time | 4.33 seconds |
| Started | May 02 12:29:48 PM PDT 24 |
| Finished | May 02 12:30:00 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-fd966a18-5dfa-4e41-b9c5-8371f2cdd962 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3255413044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3255413044 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2831744094 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1416870000 ps |
| CPU time | 4.19 seconds |
| Started | May 02 12:29:34 PM PDT 24 |
| Finished | May 02 12:29:45 PM PDT 24 |
| Peak memory | 163888 kb |
| Host | smart-e771aeb9-7a7d-4c0f-b21e-9a53296d5297 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2831744094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2831744094 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1035652267 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1470550000 ps |
| CPU time | 3.77 seconds |
| Started | May 02 12:29:20 PM PDT 24 |
| Finished | May 02 12:29:30 PM PDT 24 |
| Peak memory | 165620 kb |
| Host | smart-01a414a3-caa0-418e-a309-24a9b9531df6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1035652267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1035652267 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3664728347 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1472510000 ps |
| CPU time | 3.56 seconds |
| Started | May 02 12:30:02 PM PDT 24 |
| Finished | May 02 12:30:11 PM PDT 24 |
| Peak memory | 164300 kb |
| Host | smart-639156d7-d9b2-4f29-99b7-1a28a050f5dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3664728347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3664728347 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2009879810 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1471910000 ps |
| CPU time | 4.82 seconds |
| Started | May 02 12:25:17 PM PDT 24 |
| Finished | May 02 12:25:28 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-8e796a94-b52b-4f6d-a85e-b2985fc699a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2009879810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2009879810 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1201122805 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1449150000 ps |
| CPU time | 3.77 seconds |
| Started | May 02 12:29:00 PM PDT 24 |
| Finished | May 02 12:29:09 PM PDT 24 |
| Peak memory | 164164 kb |
| Host | smart-ea36aff5-98b7-4ce2-966c-eafcbd981fd0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1201122805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1201122805 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.359189873 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 943170000 ps |
| CPU time | 2.93 seconds |
| Started | May 02 12:30:10 PM PDT 24 |
| Finished | May 02 12:30:17 PM PDT 24 |
| Peak memory | 164364 kb |
| Host | smart-c2ad148b-d227-4c67-ae0f-f290019f37df |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=359189873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.359189873 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3173384069 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1276510000 ps |
| CPU time | 3.88 seconds |
| Started | May 02 12:29:34 PM PDT 24 |
| Finished | May 02 12:29:45 PM PDT 24 |
| Peak memory | 164212 kb |
| Host | smart-e79f7cfa-d3b4-4261-bc22-39b5a356b6d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3173384069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3173384069 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1201669378 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1351190000 ps |
| CPU time | 5.2 seconds |
| Started | May 02 12:29:03 PM PDT 24 |
| Finished | May 02 12:29:16 PM PDT 24 |
| Peak memory | 164248 kb |
| Host | smart-ab5c411a-1f61-4697-9b49-65210571e2dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1201669378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1201669378 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2176367216 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1371450000 ps |
| CPU time | 4.4 seconds |
| Started | May 02 12:28:46 PM PDT 24 |
| Finished | May 02 12:28:57 PM PDT 24 |
| Peak memory | 162124 kb |
| Host | smart-a0b52951-ef31-4eef-929b-0d297d89357f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2176367216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2176367216 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3126738803 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1155810000 ps |
| CPU time | 3.48 seconds |
| Started | May 02 12:29:35 PM PDT 24 |
| Finished | May 02 12:29:44 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-815fb951-b766-4c3f-b506-fc415f987a1a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3126738803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3126738803 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3762198658 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1226630000 ps |
| CPU time | 4.53 seconds |
| Started | May 02 12:25:28 PM PDT 24 |
| Finished | May 02 12:25:39 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-60149ae2-20de-4c55-aa9b-a20e17371917 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3762198658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3762198658 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1146899292 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1515350000 ps |
| CPU time | 3.79 seconds |
| Started | May 02 12:30:05 PM PDT 24 |
| Finished | May 02 12:30:16 PM PDT 24 |
| Peak memory | 163124 kb |
| Host | smart-028fc948-cddb-4792-8a57-769599cf9f01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1146899292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1146899292 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3531200800 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1556510000 ps |
| CPU time | 4.37 seconds |
| Started | May 02 12:30:09 PM PDT 24 |
| Finished | May 02 12:30:20 PM PDT 24 |
| Peak memory | 164336 kb |
| Host | smart-b822d9b5-a3ad-4eb8-a761-1778fb271351 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3531200800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3531200800 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3343162524 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1177990000 ps |
| CPU time | 4.38 seconds |
| Started | May 02 12:29:18 PM PDT 24 |
| Finished | May 02 12:29:29 PM PDT 24 |
| Peak memory | 164296 kb |
| Host | smart-08a608aa-87ec-4cf5-919e-74190f1df5c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3343162524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3343162524 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.753107378 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1285590000 ps |
| CPU time | 3.16 seconds |
| Started | May 02 12:28:14 PM PDT 24 |
| Finished | May 02 12:28:22 PM PDT 24 |
| Peak memory | 164564 kb |
| Host | smart-1b614b83-d77a-4e0f-b972-fe72f063e130 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=753107378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.753107378 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2250778761 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1424690000 ps |
| CPU time | 4.29 seconds |
| Started | May 02 12:26:40 PM PDT 24 |
| Finished | May 02 12:26:51 PM PDT 24 |
| Peak memory | 164596 kb |
| Host | smart-a039cc48-a8ed-46f1-a5b5-ffe4974f1b84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2250778761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2250778761 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2326107558 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1583850000 ps |
| CPU time | 4.83 seconds |
| Started | May 02 12:29:07 PM PDT 24 |
| Finished | May 02 12:29:19 PM PDT 24 |
| Peak memory | 162940 kb |
| Host | smart-ce1d68eb-25c4-44f6-83ab-c312f56fad89 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2326107558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2326107558 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1161185529 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1393010000 ps |
| CPU time | 5.32 seconds |
| Started | May 02 12:29:18 PM PDT 24 |
| Finished | May 02 12:29:31 PM PDT 24 |
| Peak memory | 162580 kb |
| Host | smart-fb940bf0-89f8-4718-858b-b01cdb7e22a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1161185529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1161185529 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1577962603 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1312210000 ps |
| CPU time | 4.03 seconds |
| Started | May 02 12:29:34 PM PDT 24 |
| Finished | May 02 12:29:45 PM PDT 24 |
| Peak memory | 164212 kb |
| Host | smart-fbacb2f7-a2b0-4f58-af9a-4651b3872eab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1577962603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1577962603 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.420265531 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1549830000 ps |
| CPU time | 4.24 seconds |
| Started | May 02 12:29:34 PM PDT 24 |
| Finished | May 02 12:29:46 PM PDT 24 |
| Peak memory | 163668 kb |
| Host | smart-7c1653f4-3ddf-4465-b464-ed2a3c6ff2a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=420265531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.420265531 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1365113810 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1535850000 ps |
| CPU time | 5.68 seconds |
| Started | May 02 12:29:18 PM PDT 24 |
| Finished | May 02 12:29:32 PM PDT 24 |
| Peak memory | 162760 kb |
| Host | smart-37a35173-97c1-4be2-836d-256696dd760b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1365113810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1365113810 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2844721823 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1456670000 ps |
| CPU time | 5.3 seconds |
| Started | May 02 12:26:08 PM PDT 24 |
| Finished | May 02 12:26:21 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-c77098f1-c3c7-44c2-96f2-e55fa18f0493 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2844721823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2844721823 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1082324481 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1495290000 ps |
| CPU time | 3.65 seconds |
| Started | May 02 12:30:05 PM PDT 24 |
| Finished | May 02 12:30:15 PM PDT 24 |
| Peak memory | 163852 kb |
| Host | smart-7239e0e4-7a46-4f31-8efd-05072051ad58 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1082324481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1082324481 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3658521611 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1501650000 ps |
| CPU time | 4.65 seconds |
| Started | May 02 12:30:05 PM PDT 24 |
| Finished | May 02 12:30:17 PM PDT 24 |
| Peak memory | 164236 kb |
| Host | smart-d8cb0adc-c025-4330-b75f-9371bc0aa2a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3658521611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3658521611 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4289121289 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1405770000 ps |
| CPU time | 4.56 seconds |
| Started | May 02 12:30:05 PM PDT 24 |
| Finished | May 02 12:30:16 PM PDT 24 |
| Peak memory | 163596 kb |
| Host | smart-0f44dac9-3f77-49ee-83ad-508105c72721 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4289121289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.4289121289 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1073798095 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1256310000 ps |
| CPU time | 3.52 seconds |
| Started | May 02 12:30:06 PM PDT 24 |
| Finished | May 02 12:30:15 PM PDT 24 |
| Peak memory | 164352 kb |
| Host | smart-9faca041-d16e-4b90-bf2d-7ce7fc708e0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1073798095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1073798095 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2931175103 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1418890000 ps |
| CPU time | 4.58 seconds |
| Started | May 02 12:26:05 PM PDT 24 |
| Finished | May 02 12:26:16 PM PDT 24 |
| Peak memory | 164556 kb |
| Host | smart-89ca8f98-ef15-4f92-a495-b77eb6b9bf1a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2931175103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2931175103 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4256550895 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1459890000 ps |
| CPU time | 2.96 seconds |
| Started | May 02 12:30:41 PM PDT 24 |
| Finished | May 02 12:30:48 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-b824c598-dc5c-4cfb-96b9-779c9f95c78f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4256550895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4256550895 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3855164635 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1430950000 ps |
| CPU time | 4.42 seconds |
| Started | May 02 12:30:55 PM PDT 24 |
| Finished | May 02 12:31:05 PM PDT 24 |
| Peak memory | 164528 kb |
| Host | smart-d101c8e6-3f85-4846-b457-034699381065 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3855164635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3855164635 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1241868380 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1526570000 ps |
| CPU time | 3.76 seconds |
| Started | May 02 12:31:08 PM PDT 24 |
| Finished | May 02 12:31:17 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-6d2721e4-2252-44c0-a5a7-1fc3e2b9774a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1241868380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1241868380 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3317129329 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1236070000 ps |
| CPU time | 3.4 seconds |
| Started | May 02 12:31:08 PM PDT 24 |
| Finished | May 02 12:31:17 PM PDT 24 |
| Peak memory | 164572 kb |
| Host | smart-fedddf52-709c-4bf4-8453-92ce698dace0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3317129329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3317129329 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3752091715 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1542190000 ps |
| CPU time | 4.35 seconds |
| Started | May 02 12:30:54 PM PDT 24 |
| Finished | May 02 12:31:05 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-13804b71-bf31-4b52-9d76-65ebc68367a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3752091715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3752091715 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1814992885 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1582310000 ps |
| CPU time | 3.99 seconds |
| Started | May 02 12:31:04 PM PDT 24 |
| Finished | May 02 12:31:19 PM PDT 24 |
| Peak memory | 164572 kb |
| Host | smart-096b9f0e-1c62-4177-9def-d985afb78da9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1814992885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1814992885 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3321637106 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1541090000 ps |
| CPU time | 4.16 seconds |
| Started | May 02 12:31:00 PM PDT 24 |
| Finished | May 02 12:31:10 PM PDT 24 |
| Peak memory | 164572 kb |
| Host | smart-47cf0901-d211-4868-9897-637d94186ef2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3321637106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3321637106 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2511441394 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1512890000 ps |
| CPU time | 3.63 seconds |
| Started | May 02 12:31:06 PM PDT 24 |
| Finished | May 02 12:31:14 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-bc000a07-7060-4a7e-9908-275d493c416b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2511441394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2511441394 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.600495680 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1497210000 ps |
| CPU time | 4.49 seconds |
| Started | May 02 12:30:55 PM PDT 24 |
| Finished | May 02 12:31:06 PM PDT 24 |
| Peak memory | 164568 kb |
| Host | smart-13d6a2ca-d332-4ee3-941e-d4b941597568 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=600495680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.600495680 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1692589730 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1543950000 ps |
| CPU time | 4.12 seconds |
| Started | May 02 12:30:55 PM PDT 24 |
| Finished | May 02 12:31:05 PM PDT 24 |
| Peak memory | 164320 kb |
| Host | smart-a4899864-dd54-4731-916c-ced1ba20ad8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1692589730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1692589730 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3938779424 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1417830000 ps |
| CPU time | 4.39 seconds |
| Started | May 02 12:30:48 PM PDT 24 |
| Finished | May 02 12:30:59 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-958a59eb-eb7d-4fa3-b3da-1a271adc5119 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3938779424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3938779424 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.813073599 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1546650000 ps |
| CPU time | 3.56 seconds |
| Started | May 02 12:31:01 PM PDT 24 |
| Finished | May 02 12:31:10 PM PDT 24 |
| Peak memory | 166072 kb |
| Host | smart-8eccfeeb-eed9-4bff-8451-54b4b7ca2105 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=813073599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.813073599 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4233429289 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1436310000 ps |
| CPU time | 4.92 seconds |
| Started | May 02 12:30:58 PM PDT 24 |
| Finished | May 02 12:31:09 PM PDT 24 |
| Peak memory | 164596 kb |
| Host | smart-6b78e09e-f8b5-4d16-9ccb-c9956de70015 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4233429289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4233429289 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1010607641 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1553130000 ps |
| CPU time | 3.7 seconds |
| Started | May 02 12:30:58 PM PDT 24 |
| Finished | May 02 12:31:07 PM PDT 24 |
| Peak memory | 164304 kb |
| Host | smart-6bd015a5-19e7-4bc8-a416-6e843ad1ed71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1010607641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1010607641 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.150621736 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1618850000 ps |
| CPU time | 4.65 seconds |
| Started | May 02 12:30:54 PM PDT 24 |
| Finished | May 02 12:31:06 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-7da566b3-d9fe-439e-9d72-8902f44fa4d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=150621736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.150621736 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3773086681 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1483910000 ps |
| CPU time | 3.54 seconds |
| Started | May 02 12:30:59 PM PDT 24 |
| Finished | May 02 12:31:08 PM PDT 24 |
| Peak memory | 164496 kb |
| Host | smart-b440b498-3c6c-452b-9f71-319cdeb9223e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3773086681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3773086681 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.74955068 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1603790000 ps |
| CPU time | 4.67 seconds |
| Started | May 02 12:31:07 PM PDT 24 |
| Finished | May 02 12:31:17 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-fbfb582b-4ba9-48e8-8605-33b8248e0b04 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=74955068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.74955068 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.269348503 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1494510000 ps |
| CPU time | 3.78 seconds |
| Started | May 02 12:31:01 PM PDT 24 |
| Finished | May 02 12:31:10 PM PDT 24 |
| Peak memory | 164552 kb |
| Host | smart-a9dd5b2d-94ac-4146-b593-07e3c757ee87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=269348503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.269348503 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2429184407 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1369770000 ps |
| CPU time | 3.84 seconds |
| Started | May 02 12:31:09 PM PDT 24 |
| Finished | May 02 12:31:18 PM PDT 24 |
| Peak memory | 164572 kb |
| Host | smart-9ce8c93d-1812-4e9c-9a51-03bd57644282 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2429184407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2429184407 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2121939600 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1602710000 ps |
| CPU time | 3.52 seconds |
| Started | May 02 12:31:13 PM PDT 24 |
| Finished | May 02 12:31:21 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-bcde5f63-5b6c-444e-b206-29e26451b629 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2121939600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2121939600 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2811274614 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1477690000 ps |
| CPU time | 2.78 seconds |
| Started | May 02 12:30:42 PM PDT 24 |
| Finished | May 02 12:30:49 PM PDT 24 |
| Peak memory | 164496 kb |
| Host | smart-1091b6c1-b02e-41da-9b55-a6c19641d917 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2811274614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2811274614 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.189623957 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1493850000 ps |
| CPU time | 4.24 seconds |
| Started | May 02 12:31:00 PM PDT 24 |
| Finished | May 02 12:31:10 PM PDT 24 |
| Peak memory | 164604 kb |
| Host | smart-e5d9b928-7152-4afc-81ea-5fd3a3ce54d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=189623957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.189623957 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2236692172 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1646750000 ps |
| CPU time | 5.17 seconds |
| Started | May 02 12:30:49 PM PDT 24 |
| Finished | May 02 12:31:02 PM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-5e08edf4-2401-493a-a606-97030e49f815 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2236692172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2236692172 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.277828423 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1243650000 ps |
| CPU time | 3.27 seconds |
| Started | May 02 12:31:06 PM PDT 24 |
| Finished | May 02 12:31:14 PM PDT 24 |
| Peak memory | 164528 kb |
| Host | smart-62fe917d-ff45-4f7c-9e53-884c31b73524 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=277828423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.277828423 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1380389026 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1422490000 ps |
| CPU time | 4.25 seconds |
| Started | May 02 12:30:56 PM PDT 24 |
| Finished | May 02 12:31:06 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-474ce559-2dd1-4138-98a4-37be851c35c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1380389026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1380389026 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1211100042 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1443450000 ps |
| CPU time | 4.25 seconds |
| Started | May 02 12:30:58 PM PDT 24 |
| Finished | May 02 12:31:08 PM PDT 24 |
| Peak memory | 164572 kb |
| Host | smart-82f28ac6-09f7-4e29-9f07-2ca426814d26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1211100042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1211100042 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3064953194 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1494530000 ps |
| CPU time | 3.84 seconds |
| Started | May 02 12:31:00 PM PDT 24 |
| Finished | May 02 12:31:09 PM PDT 24 |
| Peak memory | 164444 kb |
| Host | smart-81476da2-0a77-4a19-8567-389e7d93e789 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3064953194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3064953194 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4100343355 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1592370000 ps |
| CPU time | 3.53 seconds |
| Started | May 02 12:30:56 PM PDT 24 |
| Finished | May 02 12:31:05 PM PDT 24 |
| Peak memory | 164344 kb |
| Host | smart-30a5ec6a-f4a4-41f5-ba39-9483f973a968 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4100343355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.4100343355 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3099812799 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1511050000 ps |
| CPU time | 3.9 seconds |
| Started | May 02 12:30:59 PM PDT 24 |
| Finished | May 02 12:31:08 PM PDT 24 |
| Peak memory | 164456 kb |
| Host | smart-ee638b8f-470f-4710-845a-672c34ece865 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3099812799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3099812799 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.735459740 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1372790000 ps |
| CPU time | 3.64 seconds |
| Started | May 02 12:31:00 PM PDT 24 |
| Finished | May 02 12:31:09 PM PDT 24 |
| Peak memory | 164568 kb |
| Host | smart-f73f1384-9c22-4a6a-88e8-447a5ec48418 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=735459740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.735459740 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.434538474 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1354490000 ps |
| CPU time | 3 seconds |
| Started | May 02 12:31:15 PM PDT 24 |
| Finished | May 02 12:31:22 PM PDT 24 |
| Peak memory | 164604 kb |
| Host | smart-720b1a81-acf8-41d6-a19a-d56675193535 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=434538474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.434538474 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2362978836 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1174190000 ps |
| CPU time | 2.35 seconds |
| Started | May 02 12:31:18 PM PDT 24 |
| Finished | May 02 12:31:24 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-4b934bad-05ab-43d5-b696-4b29c566a1c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2362978836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2362978836 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.163586644 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1423690000 ps |
| CPU time | 3.22 seconds |
| Started | May 02 12:31:16 PM PDT 24 |
| Finished | May 02 12:31:24 PM PDT 24 |
| Peak memory | 164504 kb |
| Host | smart-4d2b7fd3-9333-43af-a248-b8f63b15b402 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=163586644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.163586644 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3361362661 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1121810000 ps |
| CPU time | 2.79 seconds |
| Started | May 02 12:30:58 PM PDT 24 |
| Finished | May 02 12:31:05 PM PDT 24 |
| Peak memory | 164556 kb |
| Host | smart-c6d12d2c-604d-43ee-a516-4a4bdcb64586 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3361362661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3361362661 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.78426229 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1503350000 ps |
| CPU time | 3.03 seconds |
| Started | May 02 12:31:04 PM PDT 24 |
| Finished | May 02 12:31:11 PM PDT 24 |
| Peak memory | 164528 kb |
| Host | smart-12c53102-1b98-407f-91de-e3a3d06a95b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=78426229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.78426229 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3097781811 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1523390000 ps |
| CPU time | 3.75 seconds |
| Started | May 02 12:31:15 PM PDT 24 |
| Finished | May 02 12:31:24 PM PDT 24 |
| Peak memory | 164492 kb |
| Host | smart-e0f471e7-4881-4554-b169-8fc314bd50c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3097781811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3097781811 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2589254448 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1361470000 ps |
| CPU time | 4.33 seconds |
| Started | May 02 12:31:05 PM PDT 24 |
| Finished | May 02 12:31:15 PM PDT 24 |
| Peak memory | 164564 kb |
| Host | smart-64525669-eb97-428b-8d2a-bf058c38af3e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2589254448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2589254448 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1784176297 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1414990000 ps |
| CPU time | 3.59 seconds |
| Started | May 02 12:31:11 PM PDT 24 |
| Finished | May 02 12:31:20 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-1caf1ceb-819b-4c67-99a5-4f1cabd9e219 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1784176297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1784176297 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3819782775 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1556750000 ps |
| CPU time | 3.43 seconds |
| Started | May 02 12:31:08 PM PDT 24 |
| Finished | May 02 12:31:17 PM PDT 24 |
| Peak memory | 164496 kb |
| Host | smart-b988a896-8a67-4b61-8616-e8c9929e8b78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3819782775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3819782775 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1668544253 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1299910000 ps |
| CPU time | 3.76 seconds |
| Started | May 02 12:31:17 PM PDT 24 |
| Finished | May 02 12:31:26 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-034087bc-39b1-4e47-8c0e-8a0955d0d258 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1668544253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1668544253 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.641306050 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1310810000 ps |
| CPU time | 2.92 seconds |
| Started | May 02 12:31:16 PM PDT 24 |
| Finished | May 02 12:31:23 PM PDT 24 |
| Peak memory | 164516 kb |
| Host | smart-7bb68561-4ade-47f9-85d2-49b5bd626175 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=641306050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.641306050 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.313214992 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1587170000 ps |
| CPU time | 4.21 seconds |
| Started | May 02 12:30:54 PM PDT 24 |
| Finished | May 02 12:31:05 PM PDT 24 |
| Peak memory | 164508 kb |
| Host | smart-7e8942b6-e4f0-424d-b04f-c7218baa112a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=313214992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.313214992 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2859970998 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1569170000 ps |
| CPU time | 3.46 seconds |
| Started | May 02 12:31:00 PM PDT 24 |
| Finished | May 02 12:31:08 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-ae99c1fa-0be9-4ec9-b80d-2a55051c0a07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2859970998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2859970998 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3936677033 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1574710000 ps |
| CPU time | 3.14 seconds |
| Started | May 02 12:31:17 PM PDT 24 |
| Finished | May 02 12:31:25 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-e10e8353-7009-4935-8b4a-65f2ee9b7753 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3936677033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3936677033 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3198762239 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1430230000 ps |
| CPU time | 3.89 seconds |
| Started | May 02 12:31:04 PM PDT 24 |
| Finished | May 02 12:31:13 PM PDT 24 |
| Peak memory | 164628 kb |
| Host | smart-1e31e622-dfb0-4882-a6e1-f7304fca3a12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3198762239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3198762239 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2637535854 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1592950000 ps |
| CPU time | 4.75 seconds |
| Started | May 02 12:30:56 PM PDT 24 |
| Finished | May 02 12:31:07 PM PDT 24 |
| Peak memory | 164628 kb |
| Host | smart-b560fc5c-2d8a-4de7-acb8-ad005cbb3cfc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2637535854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2637535854 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2127920960 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1533490000 ps |
| CPU time | 4.54 seconds |
| Started | May 02 12:30:49 PM PDT 24 |
| Finished | May 02 12:31:00 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-02390a19-d33c-4112-8f00-4632c694ba2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2127920960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2127920960 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3700936611 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1335170000 ps |
| CPU time | 3.3 seconds |
| Started | May 02 12:31:04 PM PDT 24 |
| Finished | May 02 12:31:13 PM PDT 24 |
| Peak memory | 164528 kb |
| Host | smart-0304bcc4-cfa2-42b5-b7a7-b7e6b79f70fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3700936611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3700936611 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3968189573 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1494290000 ps |
| CPU time | 3.9 seconds |
| Started | May 02 12:31:11 PM PDT 24 |
| Finished | May 02 12:31:21 PM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-128f5830-d243-4551-8791-77d181611a0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3968189573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3968189573 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |