| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3918965961 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.630688762 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.594380347 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.913624613 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2984811712 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2823771150 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.294346341 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.980879816 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3713567092 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4011236922 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1227169087 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3670626819 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1853644516 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.925060880 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.62637812 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.369129293 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1565534063 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1496704752 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1031853180 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3703523707 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2450111132 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.374729362 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.71437976 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2023288154 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2138661043 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2448577255 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3536635086 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1960880268 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4030665420 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1746397760 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4285081405 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2872198645 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2032555424 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3973096895 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1255979645 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.82301568 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1048993753 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2377662958 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2438819700 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.436248768 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.531117777 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2289734706 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.79923364 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3779098441 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.721666405 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.860040754 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4253717279 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3517088678 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2496041616 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.824213026 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3404919887 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4193612318 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1542686721 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1448669545 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1539879912 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3356284777 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2674000371 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2289269189 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2134541825 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1692347322 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1999495325 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2266704352 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2501764906 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3427814078 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1256323705 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3937069147 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.845102898 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2194660699 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.939960078 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2567847202 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3741146690 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2687645731 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2064166803 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3089154780 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4030468473 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1306454199 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.773105528 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4042902115 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1817838767 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.45940304 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2000398431 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4009400440 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3260082172 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2012948616 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4177466330 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1854720556 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1815469659 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1283564615 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3009003710 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3592001109 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3653250684 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1721745103 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1671608574 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2693078811 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2613947129 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2845665651 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.959693041 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2196498596 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.609074033 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3414490296 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2028322404 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1153078197 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3218174287 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1082696997 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.874180215 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1330989597 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2247267518 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2815253347 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.20495954 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3495501726 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3009604274 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2552006400 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4097870257 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1285530799 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1409169186 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2774820179 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3270613570 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.229418382 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4244425504 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1182885447 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2466104299 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2309340053 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.707855127 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3995349456 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.687095530 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2788656288 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.833618229 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2380548723 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1511315178 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2563788477 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3356879564 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3246198277 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1812946759 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3762022305 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.593032672 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3119529929 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3165960365 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1772875784 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2888612864 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3533074291 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1321105416 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4221941001 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3379474979 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1215688555 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2567224376 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.214286791 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2862563276 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3806464182 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1022868662 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1035723685 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3191804190 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4047965141 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4233216804 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2781167288 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4059302802 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.495907117 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3219702043 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.555682934 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.454629415 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4050964947 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3801641093 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.460468364 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4255040610 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.765497974 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2967013890 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1280855794 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.396576256 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2200441997 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4135796128 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.266925390 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1320204338 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.977812793 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2338291487 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3377400283 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3361567679 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.658823560 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1038362672 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2527999161 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3574366205 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2161688250 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2025728728 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4011153993 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1198236399 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.97368999 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1910700525 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.490573087 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1677655420 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2747347949 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1349325637 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2171585544 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.876022832 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2557881146 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2777493404 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2402108252 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1327991162 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1863975801 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3195317654 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.157850454 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3069815002 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2417309977 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1198236399 | May 07 02:15:50 PM PDT 24 | May 07 02:16:01 PM PDT 24 | 1381070000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2025728728 | May 07 02:15:50 PM PDT 24 | May 07 02:16:00 PM PDT 24 | 1311350000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3195317654 | May 07 02:15:03 PM PDT 24 | May 07 02:15:16 PM PDT 24 | 1390850000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1349325637 | May 07 02:15:58 PM PDT 24 | May 07 02:16:10 PM PDT 24 | 1445590000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.266925390 | May 07 02:15:39 PM PDT 24 | May 07 02:15:54 PM PDT 24 | 1582610000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2777493404 | May 07 02:16:01 PM PDT 24 | May 07 02:16:13 PM PDT 24 | 1608330000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2527999161 | May 07 02:15:44 PM PDT 24 | May 07 02:15:58 PM PDT 24 | 1524910000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1038362672 | May 07 02:15:45 PM PDT 24 | May 07 02:15:59 PM PDT 24 | 1514850000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.490573087 | May 07 02:15:50 PM PDT 24 | May 07 02:16:04 PM PDT 24 | 1549430000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3918965961 | May 07 02:14:58 PM PDT 24 | May 07 02:15:15 PM PDT 24 | 1639050000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.157850454 | May 07 02:15:05 PM PDT 24 | May 07 02:15:17 PM PDT 24 | 1556050000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4233216804 | May 07 02:14:58 PM PDT 24 | May 07 02:15:12 PM PDT 24 | 1590250000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4255040610 | May 07 02:15:35 PM PDT 24 | May 07 02:15:44 PM PDT 24 | 1548630000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1280855794 | May 07 02:15:39 PM PDT 24 | May 07 02:15:47 PM PDT 24 | 1423410000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1320204338 | May 07 02:15:44 PM PDT 24 | May 07 02:15:55 PM PDT 24 | 1465110000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4047965141 | May 07 02:14:57 PM PDT 24 | May 07 02:15:12 PM PDT 24 | 1469750000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4059302802 | May 07 02:15:08 PM PDT 24 | May 07 02:15:23 PM PDT 24 | 1598770000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2171585544 | May 07 02:16:01 PM PDT 24 | May 07 02:16:10 PM PDT 24 | 1383990000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2781167288 | May 07 02:15:08 PM PDT 24 | May 07 02:15:22 PM PDT 24 | 1569290000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.765497974 | May 07 02:15:35 PM PDT 24 | May 07 02:15:44 PM PDT 24 | 1415750000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4050964947 | May 07 02:15:25 PM PDT 24 | May 07 02:15:41 PM PDT 24 | 1562910000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3219702043 | May 07 02:15:15 PM PDT 24 | May 07 02:15:23 PM PDT 24 | 1420550000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3361567679 | May 07 02:15:46 PM PDT 24 | May 07 02:15:59 PM PDT 24 | 1495450000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3069815002 | May 07 02:15:11 PM PDT 24 | May 07 02:15:22 PM PDT 24 | 1478130000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2967013890 | May 07 02:15:40 PM PDT 24 | May 07 02:15:51 PM PDT 24 | 1567050000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.495907117 | May 07 02:15:14 PM PDT 24 | May 07 02:15:24 PM PDT 24 | 1523090000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.460468364 | May 07 02:15:27 PM PDT 24 | May 07 02:15:40 PM PDT 24 | 1482150000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2200441997 | May 07 02:15:37 PM PDT 24 | May 07 02:15:45 PM PDT 24 | 1427570000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3801641093 | May 07 02:15:25 PM PDT 24 | May 07 02:15:37 PM PDT 24 | 1439710000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2747347949 | May 07 02:16:00 PM PDT 24 | May 07 02:16:10 PM PDT 24 | 1562650000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4135796128 | May 07 02:15:44 PM PDT 24 | May 07 02:15:57 PM PDT 24 | 1605330000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3574366205 | May 07 02:15:44 PM PDT 24 | May 07 02:15:51 PM PDT 24 | 1505430000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1677655420 | May 07 02:15:49 PM PDT 24 | May 07 02:16:03 PM PDT 24 | 1454570000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2161688250 | May 07 02:15:44 PM PDT 24 | May 07 02:15:52 PM PDT 24 | 1515510000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.97368999 | May 07 02:15:50 PM PDT 24 | May 07 02:16:03 PM PDT 24 | 1516310000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.555682934 | May 07 02:15:20 PM PDT 24 | May 07 02:15:29 PM PDT 24 | 1510990000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.876022832 | May 07 02:16:01 PM PDT 24 | May 07 02:16:11 PM PDT 24 | 1511050000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3377400283 | May 07 02:15:04 PM PDT 24 | May 07 02:15:17 PM PDT 24 | 1477670000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4011153993 | May 07 02:15:49 PM PDT 24 | May 07 02:15:59 PM PDT 24 | 1499370000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1327991162 | May 07 02:16:01 PM PDT 24 | May 07 02:16:08 PM PDT 24 | 1492050000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.658823560 | May 07 02:15:45 PM PDT 24 | May 07 02:15:57 PM PDT 24 | 1329530000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.396576256 | May 07 02:15:44 PM PDT 24 | May 07 02:15:55 PM PDT 24 | 1434030000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2402108252 | May 07 02:16:01 PM PDT 24 | May 07 02:16:14 PM PDT 24 | 1470170000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.977812793 | May 07 02:15:44 PM PDT 24 | May 07 02:15:56 PM PDT 24 | 1542630000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.454629415 | May 07 02:15:20 PM PDT 24 | May 07 02:15:28 PM PDT 24 | 1504450000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2557881146 | May 07 02:15:56 PM PDT 24 | May 07 02:16:09 PM PDT 24 | 1613730000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1910700525 | May 07 02:15:04 PM PDT 24 | May 07 02:15:12 PM PDT 24 | 1284950000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1863975801 | May 07 02:15:04 PM PDT 24 | May 07 02:15:18 PM PDT 24 | 1370890000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2338291487 | May 07 02:15:45 PM PDT 24 | May 07 02:15:55 PM PDT 24 | 1429310000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2417309977 | May 07 02:15:10 PM PDT 24 | May 07 02:15:24 PM PDT 24 | 1461430000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2774820179 | May 07 12:25:00 PM PDT 24 | May 07 12:25:10 PM PDT 24 | 1371150000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3995349456 | May 07 12:24:55 PM PDT 24 | May 07 12:25:04 PM PDT 24 | 1279270000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1409169186 | May 07 12:25:00 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1554230000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2815253347 | May 07 12:24:49 PM PDT 24 | May 07 12:25:00 PM PDT 24 | 1485470000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1022868662 | May 07 12:20:47 PM PDT 24 | May 07 12:20:57 PM PDT 24 | 1459530000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.214286791 | May 07 12:25:01 PM PDT 24 | May 07 12:25:14 PM PDT 24 | 1492410000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3009604274 | May 07 12:24:54 PM PDT 24 | May 07 12:25:05 PM PDT 24 | 1363770000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3762022305 | May 07 12:25:00 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1455410000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3165960365 | May 07 12:25:00 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1568750000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.913624613 | May 07 12:20:22 PM PDT 24 | May 07 12:20:32 PM PDT 24 | 1593890000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1285530799 | May 07 12:20:21 PM PDT 24 | May 07 12:20:32 PM PDT 24 | 1389450000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3119529929 | May 07 12:20:40 PM PDT 24 | May 07 12:20:49 PM PDT 24 | 1475310000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.833618229 | May 07 12:24:56 PM PDT 24 | May 07 12:25:06 PM PDT 24 | 1265410000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3379474979 | May 07 12:25:03 PM PDT 24 | May 07 12:25:14 PM PDT 24 | 1453110000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1082696997 | May 07 12:24:50 PM PDT 24 | May 07 12:25:01 PM PDT 24 | 1558350000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.707855127 | May 07 12:24:59 PM PDT 24 | May 07 12:25:07 PM PDT 24 | 1464530000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1035723685 | May 07 12:24:09 PM PDT 24 | May 07 12:24:21 PM PDT 24 | 1606490000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3356879564 | May 07 12:24:58 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1553530000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1511315178 | May 07 12:25:12 PM PDT 24 | May 07 12:25:25 PM PDT 24 | 1456470000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2552006400 | May 07 12:25:00 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1440930000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3495501726 | May 07 12:24:55 PM PDT 24 | May 07 12:25:06 PM PDT 24 | 1557490000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3533074291 | May 07 12:25:02 PM PDT 24 | May 07 12:25:13 PM PDT 24 | 1464030000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.229418382 | May 07 12:25:05 PM PDT 24 | May 07 12:25:14 PM PDT 24 | 1402590000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1215688555 | May 07 12:25:09 PM PDT 24 | May 07 12:25:19 PM PDT 24 | 1538410000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3270613570 | May 07 12:24:58 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1524250000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4244425504 | May 07 12:24:55 PM PDT 24 | May 07 12:25:06 PM PDT 24 | 1508790000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3191804190 | May 07 12:24:08 PM PDT 24 | May 07 12:24:20 PM PDT 24 | 1617270000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.20495954 | May 07 12:20:13 PM PDT 24 | May 07 12:20:24 PM PDT 24 | 1273470000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2247267518 | May 07 12:23:48 PM PDT 24 | May 07 12:23:59 PM PDT 24 | 1364530000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3218174287 | May 07 12:19:50 PM PDT 24 | May 07 12:19:57 PM PDT 24 | 1180290000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1772875784 | May 07 12:25:04 PM PDT 24 | May 07 12:25:15 PM PDT 24 | 1445890000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4221941001 | May 07 12:25:01 PM PDT 24 | May 07 12:25:07 PM PDT 24 | 1174910000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2888612864 | May 07 12:25:04 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1196410000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1182885447 | May 07 12:24:50 PM PDT 24 | May 07 12:25:01 PM PDT 24 | 1449570000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1321105416 | May 07 12:24:59 PM PDT 24 | May 07 12:25:07 PM PDT 24 | 1148070000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.687095530 | May 07 12:23:49 PM PDT 24 | May 07 12:24:00 PM PDT 24 | 1234670000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1330989597 | May 07 12:24:08 PM PDT 24 | May 07 12:24:19 PM PDT 24 | 1441110000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3806464182 | May 07 12:20:42 PM PDT 24 | May 07 12:20:52 PM PDT 24 | 1321070000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2862563276 | May 07 12:24:00 PM PDT 24 | May 07 12:24:10 PM PDT 24 | 1445590000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2567224376 | May 07 12:24:59 PM PDT 24 | May 07 12:25:08 PM PDT 24 | 1510650000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.593032672 | May 07 12:25:04 PM PDT 24 | May 07 12:25:14 PM PDT 24 | 1351050000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.874180215 | May 07 12:21:49 PM PDT 24 | May 07 12:22:00 PM PDT 24 | 1567670000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2380548723 | May 07 12:25:04 PM PDT 24 | May 07 12:25:15 PM PDT 24 | 1371630000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2788656288 | May 07 12:24:59 PM PDT 24 | May 07 12:25:09 PM PDT 24 | 1490610000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2563788477 | May 07 12:25:00 PM PDT 24 | May 07 12:25:09 PM PDT 24 | 1471250000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2466104299 | May 07 12:24:57 PM PDT 24 | May 07 12:25:05 PM PDT 24 | 1535070000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1812946759 | May 07 12:24:59 PM PDT 24 | May 07 12:25:10 PM PDT 24 | 1525370000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4097870257 | May 07 12:25:00 PM PDT 24 | May 07 12:25:11 PM PDT 24 | 1551350000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2309340053 | May 07 12:24:50 PM PDT 24 | May 07 12:25:00 PM PDT 24 | 1540210000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3246198277 | May 07 12:25:05 PM PDT 24 | May 07 12:25:16 PM PDT 24 | 1361630000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3414490296 | May 07 12:25:13 PM PDT 24 | May 07 12:57:06 PM PDT 24 | 336855090000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1721745103 | May 07 12:25:12 PM PDT 24 | May 07 12:54:26 PM PDT 24 | 336998050000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2501764906 | May 07 12:25:10 PM PDT 24 | May 07 12:52:17 PM PDT 24 | 336897290000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3009003710 | May 07 12:25:14 PM PDT 24 | May 07 12:54:54 PM PDT 24 | 337063470000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2196498596 | May 07 12:25:03 PM PDT 24 | May 07 12:57:20 PM PDT 24 | 336372870000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.630688762 | May 07 12:25:04 PM PDT 24 | May 07 01:02:37 PM PDT 24 | 336344330000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4177466330 | May 07 12:25:14 PM PDT 24 | May 07 01:02:22 PM PDT 24 | 336348910000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1999495325 | May 07 12:25:02 PM PDT 24 | May 07 01:02:23 PM PDT 24 | 336917830000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1854720556 | May 07 12:25:12 PM PDT 24 | May 07 12:49:37 PM PDT 24 | 336478950000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2266704352 | May 07 12:25:04 PM PDT 24 | May 07 01:01:10 PM PDT 24 | 336499610000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3260082172 | May 07 12:25:12 PM PDT 24 | May 07 01:06:32 PM PDT 24 | 336667050000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2064166803 | May 07 12:25:04 PM PDT 24 | May 07 12:56:07 PM PDT 24 | 336892550000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2012948616 | May 07 12:25:22 PM PDT 24 | May 07 12:59:04 PM PDT 24 | 336518250000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1283564615 | May 07 12:25:14 PM PDT 24 | May 07 01:00:06 PM PDT 24 | 336696550000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4030468473 | May 07 12:25:04 PM PDT 24 | May 07 01:01:00 PM PDT 24 | 336784450000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3089154780 | May 07 12:25:12 PM PDT 24 | May 07 01:06:31 PM PDT 24 | 336770450000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.959693041 | May 07 12:25:22 PM PDT 24 | May 07 12:49:04 PM PDT 24 | 336361930000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3653250684 | May 07 12:25:15 PM PDT 24 | May 07 12:55:33 PM PDT 24 | 336732230000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.845102898 | May 07 12:25:07 PM PDT 24 | May 07 01:08:05 PM PDT 24 | 336862810000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2687645731 | May 07 12:25:01 PM PDT 24 | May 07 01:07:22 PM PDT 24 | 336635390000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2289269189 | May 07 12:25:11 PM PDT 24 | May 07 12:59:10 PM PDT 24 | 336857890000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.939960078 | May 07 12:25:12 PM PDT 24 | May 07 01:06:42 PM PDT 24 | 336730090000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2000398431 | May 07 12:25:00 PM PDT 24 | May 07 01:06:09 PM PDT 24 | 337048270000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1539879912 | May 07 12:25:02 PM PDT 24 | May 07 01:02:17 PM PDT 24 | 336546490000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3741146690 | May 07 12:25:06 PM PDT 24 | May 07 01:07:53 PM PDT 24 | 336496030000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1448669545 | May 07 12:24:59 PM PDT 24 | May 07 12:52:06 PM PDT 24 | 337037270000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3356284777 | May 07 12:25:02 PM PDT 24 | May 07 01:02:19 PM PDT 24 | 336981630000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1671608574 | May 07 12:25:13 PM PDT 24 | May 07 12:55:22 PM PDT 24 | 336642870000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2134541825 | May 07 12:25:03 PM PDT 24 | May 07 12:57:14 PM PDT 24 | 336526510000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1256323705 | May 07 12:25:06 PM PDT 24 | May 07 12:53:49 PM PDT 24 | 336853090000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1153078197 | May 07 12:25:03 PM PDT 24 | May 07 12:57:15 PM PDT 24 | 336944910000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3592001109 | May 07 12:25:15 PM PDT 24 | May 07 12:57:48 PM PDT 24 | 336528450000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1817838767 | May 07 12:25:00 PM PDT 24 | May 07 01:06:06 PM PDT 24 | 336834370000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3937069147 | May 07 12:25:02 PM PDT 24 | May 07 01:06:00 PM PDT 24 | 336620230000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.609074033 | May 07 12:25:04 PM PDT 24 | May 07 01:01:18 PM PDT 24 | 337135590000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.45940304 | May 07 12:25:09 PM PDT 24 | May 07 12:58:34 PM PDT 24 | 336378090000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3427814078 | May 07 12:25:01 PM PDT 24 | May 07 12:59:21 PM PDT 24 | 336836370000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2674000371 | May 07 12:25:12 PM PDT 24 | May 07 01:06:38 PM PDT 24 | 336727210000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.773105528 | May 07 12:25:12 PM PDT 24 | May 07 01:06:39 PM PDT 24 | 336915190000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1306454199 | May 07 12:25:07 PM PDT 24 | May 07 01:08:06 PM PDT 24 | 336362290000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2693078811 | May 07 12:25:15 PM PDT 24 | May 07 12:55:25 PM PDT 24 | 336852930000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2028322404 | May 07 12:25:03 PM PDT 24 | May 07 12:59:06 PM PDT 24 | 336915070000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2845665651 | May 07 12:25:13 PM PDT 24 | May 07 12:56:40 PM PDT 24 | 336340450000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4042902115 | May 07 12:25:12 PM PDT 24 | May 07 01:07:05 PM PDT 24 | 336834650000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2613947129 | May 07 12:25:15 PM PDT 24 | May 07 01:01:59 PM PDT 24 | 336741010000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1692347322 | May 07 12:25:12 PM PDT 24 | May 07 01:06:35 PM PDT 24 | 336318370000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2194660699 | May 07 12:25:02 PM PDT 24 | May 07 01:08:08 PM PDT 24 | 336760370000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2567847202 | May 07 12:25:00 PM PDT 24 | May 07 12:52:00 PM PDT 24 | 336674210000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1815469659 | May 07 12:25:01 PM PDT 24 | May 07 12:59:26 PM PDT 24 | 336881730000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4009400440 | May 07 12:24:59 PM PDT 24 | May 07 12:51:42 PM PDT 24 | 336956510000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2823771150 | May 07 12:25:11 PM PDT 24 | May 07 12:56:11 PM PDT 24 | 336985790000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.79923364 | May 07 12:25:26 PM PDT 24 | May 07 12:51:56 PM PDT 24 | 336995170000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2984811712 | May 07 12:25:20 PM PDT 24 | May 07 01:08:08 PM PDT 24 | 336449230000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2138661043 | May 07 12:26:37 PM PDT 24 | May 07 12:55:36 PM PDT 24 | 336800590000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1031853180 | May 07 12:25:18 PM PDT 24 | May 07 12:58:08 PM PDT 24 | 336761670000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.594380347 | May 07 12:25:17 PM PDT 24 | May 07 12:51:55 PM PDT 24 | 336772470000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3973096895 | May 07 12:25:33 PM PDT 24 | May 07 12:58:10 PM PDT 24 | 336821910000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.824213026 | May 07 12:25:15 PM PDT 24 | May 07 01:07:16 PM PDT 24 | 336853650000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.294346341 | May 07 12:25:12 PM PDT 24 | May 07 12:58:53 PM PDT 24 | 337003670000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2450111132 | May 07 12:25:27 PM PDT 24 | May 07 12:58:31 PM PDT 24 | 336728690000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1746397760 | May 07 12:25:25 PM PDT 24 | May 07 12:57:25 PM PDT 24 | 336801930000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4253717279 | May 07 12:25:27 PM PDT 24 | May 07 01:07:35 PM PDT 24 | 336858210000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3713567092 | May 07 12:25:23 PM PDT 24 | May 07 12:52:14 PM PDT 24 | 336789350000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4030665420 | May 07 12:25:25 PM PDT 24 | May 07 12:50:29 PM PDT 24 | 336814710000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2289734706 | May 07 12:25:27 PM PDT 24 | May 07 01:00:01 PM PDT 24 | 336966190000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1542686721 | May 07 12:25:21 PM PDT 24 | May 07 01:00:17 PM PDT 24 | 336521070000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3670626819 | May 07 12:25:22 PM PDT 24 | May 07 12:59:54 PM PDT 24 | 336604950000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.980879816 | May 07 12:25:16 PM PDT 24 | May 07 01:00:47 PM PDT 24 | 336934670000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4193612318 | May 07 12:25:15 PM PDT 24 | May 07 01:07:18 PM PDT 24 | 336703710000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3536635086 | May 07 12:25:13 PM PDT 24 | May 07 01:07:00 PM PDT 24 | 336896510000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1853644516 | May 07 12:25:21 PM PDT 24 | May 07 01:08:16 PM PDT 24 | 336378930000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2032555424 | May 07 12:25:27 PM PDT 24 | May 07 12:59:58 PM PDT 24 | 336334490000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2438819700 | May 07 12:25:30 PM PDT 24 | May 07 12:50:54 PM PDT 24 | 336660670000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1048993753 | May 07 12:25:26 PM PDT 24 | May 07 12:57:43 PM PDT 24 | 337155770000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.71437976 | May 07 12:25:24 PM PDT 24 | May 07 12:58:28 PM PDT 24 | 336693490000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1227169087 | May 07 12:25:21 PM PDT 24 | May 07 01:00:13 PM PDT 24 | 336573130000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1960880268 | May 07 12:25:24 PM PDT 24 | May 07 12:59:33 PM PDT 24 | 337088890000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4285081405 | May 07 12:25:23 PM PDT 24 | May 07 12:54:14 PM PDT 24 | 336323610000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.436248768 | May 07 12:25:26 PM PDT 24 | May 07 12:58:12 PM PDT 24 | 336610870000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.531117777 | May 07 12:25:22 PM PDT 24 | May 07 12:52:11 PM PDT 24 | 336482230000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.860040754 | May 07 12:25:25 PM PDT 24 | May 07 01:06:20 PM PDT 24 | 336670370000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2023288154 | May 07 12:25:23 PM PDT 24 | May 07 12:52:31 PM PDT 24 | 336798270000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2496041616 | May 07 12:25:16 PM PDT 24 | May 07 12:53:40 PM PDT 24 | 336752790000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.62637812 | May 07 12:25:17 PM PDT 24 | May 07 12:51:47 PM PDT 24 | 337084910000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.721666405 | May 07 12:25:28 PM PDT 24 | May 07 12:56:12 PM PDT 24 | 336986290000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2448577255 | May 07 12:25:25 PM PDT 24 | May 07 12:53:36 PM PDT 24 | 336702670000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.369129293 | May 07 12:25:15 PM PDT 24 | May 07 12:57:38 PM PDT 24 | 336689850000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3517088678 | May 07 12:26:37 PM PDT 24 | May 07 12:55:40 PM PDT 24 | 337110370000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2377662958 | May 07 12:25:14 PM PDT 24 | May 07 01:07:30 PM PDT 24 | 336595630000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1496704752 | May 07 12:25:20 PM PDT 24 | May 07 01:08:21 PM PDT 24 | 336990370000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.374729362 | May 07 12:25:26 PM PDT 24 | May 07 12:57:48 PM PDT 24 | 336413470000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1565534063 | May 07 12:25:22 PM PDT 24 | May 07 12:57:04 PM PDT 24 | 336533830000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.82301568 | May 07 12:25:26 PM PDT 24 | May 07 12:59:10 PM PDT 24 | 336930290000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.925060880 | May 07 12:25:12 PM PDT 24 | May 07 12:55:39 PM PDT 24 | 336958210000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4011236922 | May 07 12:25:20 PM PDT 24 | May 07 01:08:25 PM PDT 24 | 337090710000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3779098441 | May 07 12:25:24 PM PDT 24 | May 07 12:50:02 PM PDT 24 | 336914770000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2872198645 | May 07 12:25:23 PM PDT 24 | May 07 12:51:03 PM PDT 24 | 336649470000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3703523707 | May 07 12:25:17 PM PDT 24 | May 07 01:00:33 PM PDT 24 | 336541870000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3404919887 | May 07 12:25:23 PM PDT 24 | May 07 12:57:02 PM PDT 24 | 336988490000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1255979645 | May 07 12:25:24 PM PDT 24 | May 07 01:08:00 PM PDT 24 | 336720790000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3918965961 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1639050000 ps |
| CPU time | 7.72 seconds |
| Started | May 07 02:14:58 PM PDT 24 |
| Finished | May 07 02:15:15 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-e73b2e85-9224-48e5-a841-fe2cfe39013f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3918965961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3918965961 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.630688762 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336344330000 ps |
| CPU time | 900.39 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 01:02:37 PM PDT 24 |
| Peak memory | 160444 kb |
| Host | smart-751a05da-8ec2-4af1-9e74-0ba8d6fda261 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=630688762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.630688762 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.594380347 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336772470000 ps |
| CPU time | 648.71 seconds |
| Started | May 07 12:25:17 PM PDT 24 |
| Finished | May 07 12:51:55 PM PDT 24 |
| Peak memory | 160252 kb |
| Host | smart-06a0a41b-3ab4-4c83-acc3-1d329012d70e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=594380347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.594380347 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.913624613 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1593890000 ps |
| CPU time | 4.31 seconds |
| Started | May 07 12:20:22 PM PDT 24 |
| Finished | May 07 12:20:32 PM PDT 24 |
| Peak memory | 164456 kb |
| Host | smart-a99337a8-f37d-4313-9ab1-1047e0741fd7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=913624613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.913624613 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2984811712 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336449230000 ps |
| CPU time | 1022.94 seconds |
| Started | May 07 12:25:20 PM PDT 24 |
| Finished | May 07 01:08:08 PM PDT 24 |
| Peak memory | 160516 kb |
| Host | smart-ec923153-7516-43c0-a701-65a427d8fcb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2984811712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2984811712 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2823771150 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336985790000 ps |
| CPU time | 758.24 seconds |
| Started | May 07 12:25:11 PM PDT 24 |
| Finished | May 07 12:56:11 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-40f0ee4c-9375-42a7-ac88-05a7c7366ea2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2823771150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2823771150 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.294346341 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 337003670000 ps |
| CPU time | 812.64 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 12:58:53 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-c895032e-eef7-43a5-8871-328e3daa2c53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=294346341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.294346341 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.980879816 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336934670000 ps |
| CPU time | 857.66 seconds |
| Started | May 07 12:25:16 PM PDT 24 |
| Finished | May 07 01:00:47 PM PDT 24 |
| Peak memory | 160520 kb |
| Host | smart-02f778ec-7169-40b3-bc41-867d05be22a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=980879816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.980879816 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3713567092 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336789350000 ps |
| CPU time | 648.74 seconds |
| Started | May 07 12:25:23 PM PDT 24 |
| Finished | May 07 12:52:14 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-431b47bb-d384-4de9-9aa7-c95352ca0eb7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3713567092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3713567092 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4011236922 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337090710000 ps |
| CPU time | 1024.19 seconds |
| Started | May 07 12:25:20 PM PDT 24 |
| Finished | May 07 01:08:25 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-d9f536ef-e845-4d3c-bd8a-ca56ef47eeaa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4011236922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4011236922 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1227169087 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336573130000 ps |
| CPU time | 844.24 seconds |
| Started | May 07 12:25:21 PM PDT 24 |
| Finished | May 07 01:00:13 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-e122d3b9-7983-4930-bfcf-04f7e36d4097 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1227169087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1227169087 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3670626819 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336604950000 ps |
| CPU time | 832.83 seconds |
| Started | May 07 12:25:22 PM PDT 24 |
| Finished | May 07 12:59:54 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-f299d01a-6d0e-4274-88f8-f13c4cfea5c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3670626819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3670626819 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1853644516 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336378930000 ps |
| CPU time | 1015.83 seconds |
| Started | May 07 12:25:21 PM PDT 24 |
| Finished | May 07 01:08:16 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-085b3586-7e55-4935-8c77-1f1d3417663b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1853644516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1853644516 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.925060880 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336958210000 ps |
| CPU time | 741.48 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 12:55:39 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-dc7aa544-cc45-42a2-bfce-337ee1e75389 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=925060880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.925060880 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.62637812 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 337084910000 ps |
| CPU time | 643.99 seconds |
| Started | May 07 12:25:17 PM PDT 24 |
| Finished | May 07 12:51:47 PM PDT 24 |
| Peak memory | 160260 kb |
| Host | smart-183b82e4-e2d1-47c6-b238-822c393369ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=62637812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.62637812 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.369129293 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336689850000 ps |
| CPU time | 789.89 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 12:57:38 PM PDT 24 |
| Peak memory | 160504 kb |
| Host | smart-0c2da9a9-d6c2-4d46-994f-58f839f00e26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=369129293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.369129293 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1565534063 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336533830000 ps |
| CPU time | 771.69 seconds |
| Started | May 07 12:25:22 PM PDT 24 |
| Finished | May 07 12:57:04 PM PDT 24 |
| Peak memory | 160560 kb |
| Host | smart-eb861ce4-557f-4557-b539-630ca3af2b5b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1565534063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1565534063 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1496704752 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336990370000 ps |
| CPU time | 1018.52 seconds |
| Started | May 07 12:25:20 PM PDT 24 |
| Finished | May 07 01:08:21 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-ff562840-20a8-4b5c-acc1-de32b2a0efa1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1496704752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1496704752 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1031853180 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336761670000 ps |
| CPU time | 797.32 seconds |
| Started | May 07 12:25:18 PM PDT 24 |
| Finished | May 07 12:58:08 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-68f0e9f4-294c-479f-a5a1-37018a62f09f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1031853180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1031853180 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3703523707 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336541870000 ps |
| CPU time | 854.47 seconds |
| Started | May 07 12:25:17 PM PDT 24 |
| Finished | May 07 01:00:33 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-250421bf-d21a-4053-8b18-95ba09f674cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3703523707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3703523707 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2450111132 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336728690000 ps |
| CPU time | 803.62 seconds |
| Started | May 07 12:25:27 PM PDT 24 |
| Finished | May 07 12:58:31 PM PDT 24 |
| Peak memory | 160512 kb |
| Host | smart-7adb79e6-9a02-4342-bd20-5c8030321d52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2450111132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2450111132 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.374729362 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336413470000 ps |
| CPU time | 782.74 seconds |
| Started | May 07 12:25:26 PM PDT 24 |
| Finished | May 07 12:57:48 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-160291c0-2907-4971-8e43-c515ac4ca16d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=374729362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.374729362 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.71437976 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336693490000 ps |
| CPU time | 801.04 seconds |
| Started | May 07 12:25:24 PM PDT 24 |
| Finished | May 07 12:58:28 PM PDT 24 |
| Peak memory | 160504 kb |
| Host | smart-8bd04cff-fc49-4ecc-b517-795b1af82dd8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=71437976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.71437976 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2023288154 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336798270000 ps |
| CPU time | 655.92 seconds |
| Started | May 07 12:25:23 PM PDT 24 |
| Finished | May 07 12:52:31 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-7a32f7b3-0188-4853-b70c-4d8656d77308 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2023288154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2023288154 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2138661043 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336800590000 ps |
| CPU time | 697.81 seconds |
| Started | May 07 12:26:37 PM PDT 24 |
| Finished | May 07 12:55:36 PM PDT 24 |
| Peak memory | 158680 kb |
| Host | smart-8f102e36-1dc1-405b-963b-54b40a936db1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2138661043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2138661043 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2448577255 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336702670000 ps |
| CPU time | 692.96 seconds |
| Started | May 07 12:25:25 PM PDT 24 |
| Finished | May 07 12:53:36 PM PDT 24 |
| Peak memory | 160500 kb |
| Host | smart-b2624d93-fa3a-402f-876b-8eeadee4de5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2448577255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2448577255 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3536635086 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336896510000 ps |
| CPU time | 995.26 seconds |
| Started | May 07 12:25:13 PM PDT 24 |
| Finished | May 07 01:07:00 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-a8593e8f-ccd0-4eb7-9b21-1e2cf37e47cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3536635086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3536635086 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1960880268 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 337088890000 ps |
| CPU time | 823.72 seconds |
| Started | May 07 12:25:24 PM PDT 24 |
| Finished | May 07 12:59:33 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-e7614a96-39b0-4fa4-8904-64271135eba2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1960880268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1960880268 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4030665420 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336814710000 ps |
| CPU time | 605.62 seconds |
| Started | May 07 12:25:25 PM PDT 24 |
| Finished | May 07 12:50:29 PM PDT 24 |
| Peak memory | 160488 kb |
| Host | smart-494a9c34-d6ce-49d1-93e4-f3764d24d006 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4030665420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.4030665420 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1746397760 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336801930000 ps |
| CPU time | 775.12 seconds |
| Started | May 07 12:25:25 PM PDT 24 |
| Finished | May 07 12:57:25 PM PDT 24 |
| Peak memory | 160560 kb |
| Host | smart-d70eeae1-6b21-4a9f-bb4c-f4224625a7dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1746397760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1746397760 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4285081405 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336323610000 ps |
| CPU time | 703.75 seconds |
| Started | May 07 12:25:23 PM PDT 24 |
| Finished | May 07 12:54:14 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-d85fc8ab-c944-4e58-ab71-d9cef5f21e1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4285081405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.4285081405 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2872198645 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336649470000 ps |
| CPU time | 615.64 seconds |
| Started | May 07 12:25:23 PM PDT 24 |
| Finished | May 07 12:51:03 PM PDT 24 |
| Peak memory | 160476 kb |
| Host | smart-30bdae55-aa36-45ff-891a-673be3404912 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2872198645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2872198645 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2032555424 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336334490000 ps |
| CPU time | 832.6 seconds |
| Started | May 07 12:25:27 PM PDT 24 |
| Finished | May 07 12:59:58 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-895f8c33-b3cb-41a5-8ff4-474307767370 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2032555424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2032555424 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3973096895 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336821910000 ps |
| CPU time | 791.44 seconds |
| Started | May 07 12:25:33 PM PDT 24 |
| Finished | May 07 12:58:10 PM PDT 24 |
| Peak memory | 160544 kb |
| Host | smart-f93948d0-5a00-44eb-a817-71a75b4253e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3973096895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3973096895 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1255979645 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336720790000 ps |
| CPU time | 1023.86 seconds |
| Started | May 07 12:25:24 PM PDT 24 |
| Finished | May 07 01:08:00 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-88d7792a-8d4b-4c66-a633-e04e14c20126 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1255979645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1255979645 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.82301568 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336930290000 ps |
| CPU time | 820.01 seconds |
| Started | May 07 12:25:26 PM PDT 24 |
| Finished | May 07 12:59:10 PM PDT 24 |
| Peak memory | 160468 kb |
| Host | smart-aa669d8b-d13e-4343-8e7a-ce15d8941a8c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=82301568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.82301568 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1048993753 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 337155770000 ps |
| CPU time | 780.84 seconds |
| Started | May 07 12:25:26 PM PDT 24 |
| Finished | May 07 12:57:43 PM PDT 24 |
| Peak memory | 160512 kb |
| Host | smart-f2422969-8ed5-446f-9e32-a98457bc3dd3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1048993753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1048993753 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2377662958 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336595630000 ps |
| CPU time | 1011.31 seconds |
| Started | May 07 12:25:14 PM PDT 24 |
| Finished | May 07 01:07:30 PM PDT 24 |
| Peak memory | 160880 kb |
| Host | smart-4b382e68-64ef-4044-84ab-21ad3518a180 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2377662958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2377662958 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2438819700 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336660670000 ps |
| CPU time | 609.21 seconds |
| Started | May 07 12:25:30 PM PDT 24 |
| Finished | May 07 12:50:54 PM PDT 24 |
| Peak memory | 160568 kb |
| Host | smart-0fd353cd-f3da-45f9-a01f-9887266bc95b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2438819700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2438819700 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.436248768 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336610870000 ps |
| CPU time | 783 seconds |
| Started | May 07 12:25:26 PM PDT 24 |
| Finished | May 07 12:58:12 PM PDT 24 |
| Peak memory | 160480 kb |
| Host | smart-f9727fab-6a65-4f7e-8059-d3e2de869145 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=436248768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.436248768 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.531117777 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336482230000 ps |
| CPU time | 646.83 seconds |
| Started | May 07 12:25:22 PM PDT 24 |
| Finished | May 07 12:52:11 PM PDT 24 |
| Peak memory | 160520 kb |
| Host | smart-feb85511-d788-4c92-a2c3-1283566cf135 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=531117777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.531117777 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2289734706 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336966190000 ps |
| CPU time | 832.21 seconds |
| Started | May 07 12:25:27 PM PDT 24 |
| Finished | May 07 01:00:01 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-f4272084-d885-4f1f-baed-a3879aec7178 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2289734706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2289734706 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.79923364 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336995170000 ps |
| CPU time | 642.54 seconds |
| Started | May 07 12:25:26 PM PDT 24 |
| Finished | May 07 12:51:56 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-da0404e6-0b6e-479d-9366-d25bc42f1da4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=79923364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.79923364 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3779098441 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336914770000 ps |
| CPU time | 592.11 seconds |
| Started | May 07 12:25:24 PM PDT 24 |
| Finished | May 07 12:50:02 PM PDT 24 |
| Peak memory | 160436 kb |
| Host | smart-0edf7e51-a293-4aac-bda0-e026d6bf5d0e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3779098441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3779098441 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.721666405 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336986290000 ps |
| CPU time | 749.95 seconds |
| Started | May 07 12:25:28 PM PDT 24 |
| Finished | May 07 12:56:12 PM PDT 24 |
| Peak memory | 160520 kb |
| Host | smart-41e299bf-5a92-4ee1-94a4-80627b3b4a8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=721666405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.721666405 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.860040754 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336670370000 ps |
| CPU time | 988.34 seconds |
| Started | May 07 12:25:25 PM PDT 24 |
| Finished | May 07 01:06:20 PM PDT 24 |
| Peak memory | 160552 kb |
| Host | smart-20539d6f-58a3-4f44-a712-8b6e781cf11a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=860040754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.860040754 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4253717279 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336858210000 ps |
| CPU time | 1006.64 seconds |
| Started | May 07 12:25:27 PM PDT 24 |
| Finished | May 07 01:07:35 PM PDT 24 |
| Peak memory | 160896 kb |
| Host | smart-b2496918-6aea-4352-a240-6050cb680c35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4253717279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4253717279 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3517088678 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 337110370000 ps |
| CPU time | 700.68 seconds |
| Started | May 07 12:26:37 PM PDT 24 |
| Finished | May 07 12:55:40 PM PDT 24 |
| Peak memory | 158520 kb |
| Host | smart-f414445d-d3d2-4d97-9328-bd5cd46d3392 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3517088678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3517088678 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2496041616 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336752790000 ps |
| CPU time | 700.28 seconds |
| Started | May 07 12:25:16 PM PDT 24 |
| Finished | May 07 12:53:40 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-93bb015a-8551-4168-bf44-da92cc501267 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2496041616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2496041616 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.824213026 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336853650000 ps |
| CPU time | 1007.02 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 01:07:16 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-97625d54-8781-41d7-8e82-032d45b86c35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=824213026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.824213026 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3404919887 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336988490000 ps |
| CPU time | 751.63 seconds |
| Started | May 07 12:25:23 PM PDT 24 |
| Finished | May 07 12:57:02 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-66a8006d-89ed-4d2d-8034-7c1ca546dafc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3404919887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3404919887 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4193612318 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336703710000 ps |
| CPU time | 1007.05 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 01:07:18 PM PDT 24 |
| Peak memory | 160880 kb |
| Host | smart-ba6826ba-eedd-4b52-a964-90ec1e937e36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4193612318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.4193612318 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1542686721 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336521070000 ps |
| CPU time | 841.19 seconds |
| Started | May 07 12:25:21 PM PDT 24 |
| Finished | May 07 01:00:17 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-096e6328-b3b1-4989-b34e-12204bb8d783 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1542686721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1542686721 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1448669545 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 337037270000 ps |
| CPU time | 659.7 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:52:06 PM PDT 24 |
| Peak memory | 160560 kb |
| Host | smart-0beb0688-cc4f-4366-b39e-09bfe9bd82ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1448669545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1448669545 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1539879912 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336546490000 ps |
| CPU time | 887.63 seconds |
| Started | May 07 12:25:02 PM PDT 24 |
| Finished | May 07 01:02:17 PM PDT 24 |
| Peak memory | 160000 kb |
| Host | smart-ebfd53f3-6c22-423d-96aa-0bcc33e8d1ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1539879912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1539879912 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3356284777 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336981630000 ps |
| CPU time | 892.75 seconds |
| Started | May 07 12:25:02 PM PDT 24 |
| Finished | May 07 01:02:19 PM PDT 24 |
| Peak memory | 159972 kb |
| Host | smart-7db79865-e09b-40a8-8aee-53b6121c8427 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3356284777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3356284777 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2674000371 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336727210000 ps |
| CPU time | 947.1 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:06:38 PM PDT 24 |
| Peak memory | 158536 kb |
| Host | smart-4b7b52d0-d833-4928-9061-2489ec0d0af2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2674000371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2674000371 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2289269189 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336857890000 ps |
| CPU time | 823.37 seconds |
| Started | May 07 12:25:11 PM PDT 24 |
| Finished | May 07 12:59:10 PM PDT 24 |
| Peak memory | 160484 kb |
| Host | smart-c5ccf2e2-faa9-4638-adde-e434f5f5736c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2289269189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2289269189 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2134541825 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336526510000 ps |
| CPU time | 790.6 seconds |
| Started | May 07 12:25:03 PM PDT 24 |
| Finished | May 07 12:57:14 PM PDT 24 |
| Peak memory | 160544 kb |
| Host | smart-de29f6f3-217d-43e2-834c-866f8ece1c5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2134541825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2134541825 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1692347322 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336318370000 ps |
| CPU time | 950.54 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:06:35 PM PDT 24 |
| Peak memory | 158444 kb |
| Host | smart-8378b196-c3df-4e5a-a793-af98bc0ff31f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1692347322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1692347322 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1999495325 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336917830000 ps |
| CPU time | 896.05 seconds |
| Started | May 07 12:25:02 PM PDT 24 |
| Finished | May 07 01:02:23 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-d8938905-6407-400d-8887-0e14bbf407b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1999495325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1999495325 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2266704352 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336499610000 ps |
| CPU time | 877.01 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 01:01:10 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-d4a89555-0240-4ae7-8755-0b738c2d8942 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2266704352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2266704352 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2501764906 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336897290000 ps |
| CPU time | 650.9 seconds |
| Started | May 07 12:25:10 PM PDT 24 |
| Finished | May 07 12:52:17 PM PDT 24 |
| Peak memory | 160516 kb |
| Host | smart-1262afd8-db94-40df-a68b-a9af0d846f79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2501764906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2501764906 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3427814078 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336836370000 ps |
| CPU time | 841 seconds |
| Started | May 07 12:25:01 PM PDT 24 |
| Finished | May 07 12:59:21 PM PDT 24 |
| Peak memory | 160484 kb |
| Host | smart-bf0eff90-7516-48a9-a855-a9b4451ae8d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3427814078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3427814078 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1256323705 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336853090000 ps |
| CPU time | 687.45 seconds |
| Started | May 07 12:25:06 PM PDT 24 |
| Finished | May 07 12:53:49 PM PDT 24 |
| Peak memory | 160520 kb |
| Host | smart-08326d30-8d11-4c43-8ed9-f92e357927f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1256323705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1256323705 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3937069147 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336620230000 ps |
| CPU time | 990.23 seconds |
| Started | May 07 12:25:02 PM PDT 24 |
| Finished | May 07 01:06:00 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-465da477-3e8b-4bb5-a1cf-6e4fa8330572 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3937069147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3937069147 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.845102898 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336862810000 ps |
| CPU time | 1030.63 seconds |
| Started | May 07 12:25:07 PM PDT 24 |
| Finished | May 07 01:08:05 PM PDT 24 |
| Peak memory | 160536 kb |
| Host | smart-5f5e57f2-2216-4c79-a01b-042eaaf9fd31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=845102898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.845102898 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2194660699 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336760370000 ps |
| CPU time | 1027 seconds |
| Started | May 07 12:25:02 PM PDT 24 |
| Finished | May 07 01:08:08 PM PDT 24 |
| Peak memory | 160432 kb |
| Host | smart-d624c6b7-8398-4550-9379-397136d4685f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2194660699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2194660699 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.939960078 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336730090000 ps |
| CPU time | 952.58 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:06:42 PM PDT 24 |
| Peak memory | 158936 kb |
| Host | smart-636fcf57-d3e7-4622-9442-3321c1cd89ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=939960078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.939960078 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2567847202 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336674210000 ps |
| CPU time | 657.96 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:52:00 PM PDT 24 |
| Peak memory | 160572 kb |
| Host | smart-01be66f4-07b8-419f-b788-77dbe060b6d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2567847202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2567847202 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3741146690 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336496030000 ps |
| CPU time | 1018.65 seconds |
| Started | May 07 12:25:06 PM PDT 24 |
| Finished | May 07 01:07:53 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-19157d84-7b03-4adb-b06c-2d8ab8162768 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3741146690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3741146690 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2687645731 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336635390000 ps |
| CPU time | 1016.74 seconds |
| Started | May 07 12:25:01 PM PDT 24 |
| Finished | May 07 01:07:22 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-17164d89-635f-4f4e-b691-9de06647e563 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2687645731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2687645731 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2064166803 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336892550000 ps |
| CPU time | 756.06 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 12:56:07 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-8f393e41-ebe0-47c7-8ac8-24211b53c1b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2064166803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2064166803 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3089154780 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336770450000 ps |
| CPU time | 950.5 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:06:31 PM PDT 24 |
| Peak memory | 158940 kb |
| Host | smart-85eb219c-5a14-4b7d-8e72-e4582bd9a48c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3089154780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3089154780 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4030468473 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336784450000 ps |
| CPU time | 873.93 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 01:01:00 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-53fa06a8-3e18-4cfc-8a00-cabcef95553e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4030468473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4030468473 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1306454199 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336362290000 ps |
| CPU time | 1032.42 seconds |
| Started | May 07 12:25:07 PM PDT 24 |
| Finished | May 07 01:08:06 PM PDT 24 |
| Peak memory | 160584 kb |
| Host | smart-e5425933-681d-4138-918e-2ca0cd008ec9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1306454199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1306454199 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.773105528 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336915190000 ps |
| CPU time | 951.02 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:06:39 PM PDT 24 |
| Peak memory | 158624 kb |
| Host | smart-1c993e02-4365-4b75-af5c-9a31df6470ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=773105528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.773105528 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4042902115 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336834650000 ps |
| CPU time | 997.09 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:07:05 PM PDT 24 |
| Peak memory | 159168 kb |
| Host | smart-fb96efd7-f55d-4d05-a94f-5b809ee74970 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4042902115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4042902115 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1817838767 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336834370000 ps |
| CPU time | 997.09 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 01:06:06 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-d6670b0b-4fbb-4df1-a490-29a14418b79e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1817838767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1817838767 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.45940304 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336378090000 ps |
| CPU time | 804.49 seconds |
| Started | May 07 12:25:09 PM PDT 24 |
| Finished | May 07 12:58:34 PM PDT 24 |
| Peak memory | 160416 kb |
| Host | smart-c12ab051-f90b-4b85-9cdd-6b1dc53f0076 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=45940304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.45940304 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2000398431 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 337048270000 ps |
| CPU time | 993.12 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 01:06:09 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-0fada142-ba59-4a44-8725-39494fc2ba9b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2000398431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2000398431 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4009400440 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336956510000 ps |
| CPU time | 649.89 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:51:42 PM PDT 24 |
| Peak memory | 160536 kb |
| Host | smart-ed65512c-fce4-468c-b5fc-8fd3c8ec12e9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4009400440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.4009400440 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3260082172 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336667050000 ps |
| CPU time | 947.8 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 01:06:32 PM PDT 24 |
| Peak memory | 158992 kb |
| Host | smart-39b0a710-e3ee-4169-ad63-5b1076577232 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3260082172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3260082172 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2012948616 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336518250000 ps |
| CPU time | 817.42 seconds |
| Started | May 07 12:25:22 PM PDT 24 |
| Finished | May 07 12:59:04 PM PDT 24 |
| Peak memory | 160484 kb |
| Host | smart-d6e0323e-0979-4781-8dee-45019410f0fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2012948616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2012948616 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.4177466330 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336348910000 ps |
| CPU time | 891.64 seconds |
| Started | May 07 12:25:14 PM PDT 24 |
| Finished | May 07 01:02:22 PM PDT 24 |
| Peak memory | 160448 kb |
| Host | smart-14661de4-f779-4c74-8448-be61d82d70e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4177466330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.4177466330 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1854720556 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336478950000 ps |
| CPU time | 583.03 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 12:49:37 PM PDT 24 |
| Peak memory | 160440 kb |
| Host | smart-6862e499-69a0-4db3-b5b2-fe74e040119e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1854720556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1854720556 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1815469659 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336881730000 ps |
| CPU time | 848.94 seconds |
| Started | May 07 12:25:01 PM PDT 24 |
| Finished | May 07 12:59:26 PM PDT 24 |
| Peak memory | 160408 kb |
| Host | smart-9da0b676-e5f4-4446-ac69-a0e6f5d92eaf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1815469659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1815469659 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1283564615 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336696550000 ps |
| CPU time | 856.37 seconds |
| Started | May 07 12:25:14 PM PDT 24 |
| Finished | May 07 01:00:06 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-413b3913-0755-440a-993e-afbc5f036b03 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1283564615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1283564615 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3009003710 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 337063470000 ps |
| CPU time | 717.65 seconds |
| Started | May 07 12:25:14 PM PDT 24 |
| Finished | May 07 12:54:54 PM PDT 24 |
| Peak memory | 160440 kb |
| Host | smart-7a5e7cef-3f28-4a21-9fab-1d03786ca9b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3009003710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3009003710 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3592001109 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336528450000 ps |
| CPU time | 794.17 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 12:57:48 PM PDT 24 |
| Peak memory | 160440 kb |
| Host | smart-0b35ad83-96d9-42a9-9a94-909108fa8fc6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3592001109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3592001109 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3653250684 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336732230000 ps |
| CPU time | 733.82 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 12:55:33 PM PDT 24 |
| Peak memory | 160488 kb |
| Host | smart-eb01eb4d-9db4-40ed-902f-16e653cd5114 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3653250684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3653250684 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1721745103 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336998050000 ps |
| CPU time | 710.93 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 12:54:26 PM PDT 24 |
| Peak memory | 160504 kb |
| Host | smart-55b30066-3c8e-4e75-8933-2b8a223e1b99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1721745103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1721745103 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1671608574 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336642870000 ps |
| CPU time | 737.75 seconds |
| Started | May 07 12:25:13 PM PDT 24 |
| Finished | May 07 12:55:22 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-febcfe12-16d5-460c-a23e-0c01cde5e69f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1671608574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1671608574 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2693078811 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336852930000 ps |
| CPU time | 732.24 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 12:55:25 PM PDT 24 |
| Peak memory | 160492 kb |
| Host | smart-80d33e64-270c-4fd9-a0fd-b71577bab884 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2693078811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2693078811 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2613947129 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336741010000 ps |
| CPU time | 873.55 seconds |
| Started | May 07 12:25:15 PM PDT 24 |
| Finished | May 07 01:01:59 PM PDT 24 |
| Peak memory | 160448 kb |
| Host | smart-712b8548-e8e7-4106-9a67-714a24fe15b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2613947129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2613947129 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2845665651 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336340450000 ps |
| CPU time | 767.66 seconds |
| Started | May 07 12:25:13 PM PDT 24 |
| Finished | May 07 12:56:40 PM PDT 24 |
| Peak memory | 160420 kb |
| Host | smart-3d6e745b-c9af-44ae-999b-31a57625a395 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2845665651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2845665651 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.959693041 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336361930000 ps |
| CPU time | 555.93 seconds |
| Started | May 07 12:25:22 PM PDT 24 |
| Finished | May 07 12:49:04 PM PDT 24 |
| Peak memory | 160380 kb |
| Host | smart-90ac3bee-dc0c-4e19-a3a1-f2155ffd76b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=959693041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.959693041 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2196498596 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336372870000 ps |
| CPU time | 793.8 seconds |
| Started | May 07 12:25:03 PM PDT 24 |
| Finished | May 07 12:57:20 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-1344b55b-8ffb-441d-9310-a3f39eeec603 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2196498596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2196498596 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.609074033 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 337135590000 ps |
| CPU time | 886.66 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 01:01:18 PM PDT 24 |
| Peak memory | 160540 kb |
| Host | smart-debf2344-b916-48ad-bc14-7146ea229058 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=609074033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.609074033 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3414490296 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336855090000 ps |
| CPU time | 766 seconds |
| Started | May 07 12:25:13 PM PDT 24 |
| Finished | May 07 12:57:06 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-ada35d6e-cef3-43dc-8851-e84787935cdd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3414490296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3414490296 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2028322404 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336915070000 ps |
| CPU time | 823.47 seconds |
| Started | May 07 12:25:03 PM PDT 24 |
| Finished | May 07 12:59:06 PM PDT 24 |
| Peak memory | 160504 kb |
| Host | smart-3c6610a5-10e3-4da3-9c87-8a1eecb46e48 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2028322404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2028322404 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1153078197 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336944910000 ps |
| CPU time | 794.85 seconds |
| Started | May 07 12:25:03 PM PDT 24 |
| Finished | May 07 12:57:15 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-e61854f2-c1a9-4773-bbd5-1729d860b7a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1153078197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1153078197 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3218174287 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1180290000 ps |
| CPU time | 2.96 seconds |
| Started | May 07 12:19:50 PM PDT 24 |
| Finished | May 07 12:19:57 PM PDT 24 |
| Peak memory | 164496 kb |
| Host | smart-2402da72-1493-48e3-b423-1c1ef196d075 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3218174287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3218174287 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1082696997 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1558350000 ps |
| CPU time | 4.17 seconds |
| Started | May 07 12:24:50 PM PDT 24 |
| Finished | May 07 12:25:01 PM PDT 24 |
| Peak memory | 164212 kb |
| Host | smart-8180c647-5663-442f-a981-f9d953bdcf13 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1082696997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1082696997 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.874180215 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1567670000 ps |
| CPU time | 4.58 seconds |
| Started | May 07 12:21:49 PM PDT 24 |
| Finished | May 07 12:22:00 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-58ef8d52-1024-4303-97d0-8528cd94b6c0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=874180215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.874180215 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1330989597 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1441110000 ps |
| CPU time | 3.95 seconds |
| Started | May 07 12:24:08 PM PDT 24 |
| Finished | May 07 12:24:19 PM PDT 24 |
| Peak memory | 163492 kb |
| Host | smart-0575ebbe-a209-4601-a65a-63f5ff062879 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1330989597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1330989597 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2247267518 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1364530000 ps |
| CPU time | 3.95 seconds |
| Started | May 07 12:23:48 PM PDT 24 |
| Finished | May 07 12:23:59 PM PDT 24 |
| Peak memory | 163572 kb |
| Host | smart-84b0689b-67e2-47c0-a79a-697cf630eca9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2247267518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2247267518 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2815253347 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1485470000 ps |
| CPU time | 4.12 seconds |
| Started | May 07 12:24:49 PM PDT 24 |
| Finished | May 07 12:25:00 PM PDT 24 |
| Peak memory | 164136 kb |
| Host | smart-41703ec6-b85a-46b7-b20a-555af8830486 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2815253347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2815253347 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.20495954 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1273470000 ps |
| CPU time | 4.89 seconds |
| Started | May 07 12:20:13 PM PDT 24 |
| Finished | May 07 12:20:24 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-2ad939e0-4bcd-4f17-a44b-764f7153158a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=20495954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.20495954 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3495501726 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1557490000 ps |
| CPU time | 4.62 seconds |
| Started | May 07 12:24:55 PM PDT 24 |
| Finished | May 07 12:25:06 PM PDT 24 |
| Peak memory | 164512 kb |
| Host | smart-b7ba7ffa-b509-4237-83fd-6d184e2f194d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3495501726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3495501726 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3009604274 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1363770000 ps |
| CPU time | 4.16 seconds |
| Started | May 07 12:24:54 PM PDT 24 |
| Finished | May 07 12:25:05 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-3f6101e0-069a-4962-a05f-b8c5504a903b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3009604274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3009604274 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2552006400 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1440930000 ps |
| CPU time | 4.13 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164508 kb |
| Host | smart-56313557-3d42-4f51-99df-e8b4fea7da99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2552006400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2552006400 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4097870257 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1551350000 ps |
| CPU time | 4.37 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-a0dd3e8f-1abf-41e7-be61-c55d8a0b0027 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4097870257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.4097870257 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1285530799 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1389450000 ps |
| CPU time | 4.67 seconds |
| Started | May 07 12:20:21 PM PDT 24 |
| Finished | May 07 12:20:32 PM PDT 24 |
| Peak memory | 164520 kb |
| Host | smart-cf57bab9-d768-421e-aab5-ee0b63d9306f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1285530799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1285530799 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1409169186 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1554230000 ps |
| CPU time | 4.37 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-d253ec8b-f095-4d0a-9498-e99bf3b684a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1409169186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1409169186 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2774820179 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1371150000 ps |
| CPU time | 4 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:10 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-e3193dae-8cc3-4d16-a96a-13f55da1c60c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2774820179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2774820179 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3270613570 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1524250000 ps |
| CPU time | 5.89 seconds |
| Started | May 07 12:24:58 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-c2eb76c3-6191-4012-9a8b-9bb74d1966e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3270613570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3270613570 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.229418382 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1402590000 ps |
| CPU time | 3.32 seconds |
| Started | May 07 12:25:05 PM PDT 24 |
| Finished | May 07 12:25:14 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-3b50f77a-8da7-4bde-be1b-e96b9c7f959a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=229418382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.229418382 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4244425504 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1508790000 ps |
| CPU time | 4.66 seconds |
| Started | May 07 12:24:55 PM PDT 24 |
| Finished | May 07 12:25:06 PM PDT 24 |
| Peak memory | 164512 kb |
| Host | smart-5b95be99-bd05-4fa8-b27a-ab851837b96e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4244425504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4244425504 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1182885447 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1449570000 ps |
| CPU time | 4.34 seconds |
| Started | May 07 12:24:50 PM PDT 24 |
| Finished | May 07 12:25:01 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-7d0a4495-797c-4899-aeb4-651233c56d23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1182885447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1182885447 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2466104299 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1535070000 ps |
| CPU time | 3.52 seconds |
| Started | May 07 12:24:57 PM PDT 24 |
| Finished | May 07 12:25:05 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-a9495db4-438c-4b9c-8c19-e414a5838c93 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2466104299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2466104299 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2309340053 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1540210000 ps |
| CPU time | 4.13 seconds |
| Started | May 07 12:24:50 PM PDT 24 |
| Finished | May 07 12:25:00 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-04a59e5b-8c2b-459a-b8e1-c02b21e66f3c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2309340053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2309340053 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.707855127 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1464530000 ps |
| CPU time | 3.13 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:25:07 PM PDT 24 |
| Peak memory | 164448 kb |
| Host | smart-b4b84457-5489-4dfb-a81a-e698aa79ef6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=707855127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.707855127 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3995349456 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1279270000 ps |
| CPU time | 3.88 seconds |
| Started | May 07 12:24:55 PM PDT 24 |
| Finished | May 07 12:25:04 PM PDT 24 |
| Peak memory | 164512 kb |
| Host | smart-d3d84681-d54d-4fd6-b3e3-a1467f70ca0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3995349456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3995349456 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.687095530 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1234670000 ps |
| CPU time | 4.33 seconds |
| Started | May 07 12:23:49 PM PDT 24 |
| Finished | May 07 12:24:00 PM PDT 24 |
| Peak memory | 163404 kb |
| Host | smart-757c4061-1ad9-4e96-a8c7-36f806918122 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=687095530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.687095530 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2788656288 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1490610000 ps |
| CPU time | 4.35 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:25:09 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-ef383136-4af3-42cd-8f44-0fd0532e15ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2788656288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2788656288 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.833618229 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1265410000 ps |
| CPU time | 4.12 seconds |
| Started | May 07 12:24:56 PM PDT 24 |
| Finished | May 07 12:25:06 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-b00dddfd-2099-40fd-94fb-2659909bacf6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=833618229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.833618229 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2380548723 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1371630000 ps |
| CPU time | 4 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 12:25:15 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-a6853613-4665-4788-93ee-c2ac18bc4d6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2380548723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2380548723 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1511315178 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1456470000 ps |
| CPU time | 5.51 seconds |
| Started | May 07 12:25:12 PM PDT 24 |
| Finished | May 07 12:25:25 PM PDT 24 |
| Peak memory | 163656 kb |
| Host | smart-e362ef52-2748-468e-90a4-1cc8f494ae39 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1511315178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1511315178 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2563788477 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1471250000 ps |
| CPU time | 3.09 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:09 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-2beca50d-8c55-4ff2-915a-899b4d1a00f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2563788477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2563788477 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3356879564 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1553530000 ps |
| CPU time | 5.39 seconds |
| Started | May 07 12:24:58 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164280 kb |
| Host | smart-d39b0cbc-f48a-4271-8813-c8a601f80819 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3356879564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3356879564 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3246198277 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1361630000 ps |
| CPU time | 4.64 seconds |
| Started | May 07 12:25:05 PM PDT 24 |
| Finished | May 07 12:25:16 PM PDT 24 |
| Peak memory | 164444 kb |
| Host | smart-fb819617-6261-40a0-aa47-d33e66693e66 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3246198277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3246198277 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1812946759 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1525370000 ps |
| CPU time | 4.61 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:25:10 PM PDT 24 |
| Peak memory | 164512 kb |
| Host | smart-2a02f0b2-975c-4ac4-b4f8-deed6aab2cda |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1812946759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1812946759 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3762022305 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1455410000 ps |
| CPU time | 4.12 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-7c0106b8-ce1b-40b8-a880-78834386d0ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3762022305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3762022305 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.593032672 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1351050000 ps |
| CPU time | 3.94 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 12:25:14 PM PDT 24 |
| Peak memory | 164488 kb |
| Host | smart-6c42acca-4636-46a9-9afe-41af6fa7f906 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=593032672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.593032672 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3119529929 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1475310000 ps |
| CPU time | 4.04 seconds |
| Started | May 07 12:20:40 PM PDT 24 |
| Finished | May 07 12:20:49 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-9c9acfaf-f6db-4c6a-ba3c-6a8aa58d4436 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3119529929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3119529929 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3165960365 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1568750000 ps |
| CPU time | 4.52 seconds |
| Started | May 07 12:25:00 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-8d213766-3049-46f3-a9fa-814d32c0a5ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3165960365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3165960365 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1772875784 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1445890000 ps |
| CPU time | 4.38 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 12:25:15 PM PDT 24 |
| Peak memory | 164496 kb |
| Host | smart-442b6dea-3daf-40c2-a59c-8ef9819b6c9c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1772875784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1772875784 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2888612864 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1196410000 ps |
| CPU time | 2.59 seconds |
| Started | May 07 12:25:04 PM PDT 24 |
| Finished | May 07 12:25:11 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-1faea075-c331-4709-b2a6-9199e34ef1d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2888612864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2888612864 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3533074291 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1464030000 ps |
| CPU time | 4.31 seconds |
| Started | May 07 12:25:02 PM PDT 24 |
| Finished | May 07 12:25:13 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-085cce8b-9bde-4def-b0a7-6b6d5e313ded |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3533074291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3533074291 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1321105416 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1148070000 ps |
| CPU time | 3.13 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:25:07 PM PDT 24 |
| Peak memory | 164452 kb |
| Host | smart-ff0c8137-500e-4120-b3b0-ce0a04cd32df |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1321105416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1321105416 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4221941001 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1174910000 ps |
| CPU time | 2.43 seconds |
| Started | May 07 12:25:01 PM PDT 24 |
| Finished | May 07 12:25:07 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-e768c7ad-df63-404d-ac2d-190c2c46ec67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4221941001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.4221941001 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3379474979 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1453110000 ps |
| CPU time | 4.45 seconds |
| Started | May 07 12:25:03 PM PDT 24 |
| Finished | May 07 12:25:14 PM PDT 24 |
| Peak memory | 164500 kb |
| Host | smart-10381992-520c-49b6-81dc-6ea3cd997318 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3379474979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3379474979 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1215688555 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1538410000 ps |
| CPU time | 3.99 seconds |
| Started | May 07 12:25:09 PM PDT 24 |
| Finished | May 07 12:25:19 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-8b754847-3aa8-4188-86fa-d3d996e23467 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1215688555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1215688555 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2567224376 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1510650000 ps |
| CPU time | 3.74 seconds |
| Started | May 07 12:24:59 PM PDT 24 |
| Finished | May 07 12:25:08 PM PDT 24 |
| Peak memory | 164452 kb |
| Host | smart-be5380c6-d1a8-4b55-88ae-b5ecaf570435 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2567224376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2567224376 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.214286791 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1492410000 ps |
| CPU time | 5.27 seconds |
| Started | May 07 12:25:01 PM PDT 24 |
| Finished | May 07 12:25:14 PM PDT 24 |
| Peak memory | 164492 kb |
| Host | smart-1d0a58dc-732a-4679-8512-14b2edeefcad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=214286791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.214286791 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2862563276 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1445590000 ps |
| CPU time | 3.58 seconds |
| Started | May 07 12:24:00 PM PDT 24 |
| Finished | May 07 12:24:10 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-fee4e9f1-1e15-4da8-ad59-077c78c1a9b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2862563276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2862563276 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3806464182 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1321070000 ps |
| CPU time | 4.05 seconds |
| Started | May 07 12:20:42 PM PDT 24 |
| Finished | May 07 12:20:52 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-08822072-7e69-446f-b974-595476f96bc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3806464182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3806464182 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1022868662 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1459530000 ps |
| CPU time | 4.37 seconds |
| Started | May 07 12:20:47 PM PDT 24 |
| Finished | May 07 12:20:57 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-f37f82a3-5f1c-4756-a746-9190d552cb34 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1022868662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1022868662 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1035723685 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1606490000 ps |
| CPU time | 4.4 seconds |
| Started | May 07 12:24:09 PM PDT 24 |
| Finished | May 07 12:24:21 PM PDT 24 |
| Peak memory | 164212 kb |
| Host | smart-1424d9bc-7806-4c77-93b0-3efe245ba514 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1035723685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1035723685 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3191804190 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1617270000 ps |
| CPU time | 4.52 seconds |
| Started | May 07 12:24:08 PM PDT 24 |
| Finished | May 07 12:24:20 PM PDT 24 |
| Peak memory | 162624 kb |
| Host | smart-089ffa4c-81f7-407a-9e72-574f695d6dca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3191804190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3191804190 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4047965141 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1469750000 ps |
| CPU time | 6.91 seconds |
| Started | May 07 02:14:57 PM PDT 24 |
| Finished | May 07 02:15:12 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-cff29e8e-9880-4136-ab51-1f5f8a27cb69 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4047965141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4047965141 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4233216804 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1590250000 ps |
| CPU time | 6.26 seconds |
| Started | May 07 02:14:58 PM PDT 24 |
| Finished | May 07 02:15:12 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-aee5d07f-4dad-4df4-8515-2685a4f7562e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4233216804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4233216804 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2781167288 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1569290000 ps |
| CPU time | 6 seconds |
| Started | May 07 02:15:08 PM PDT 24 |
| Finished | May 07 02:15:22 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-e0c2f880-108a-4867-9999-6ab15e37f15e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2781167288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2781167288 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4059302802 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1598770000 ps |
| CPU time | 6.41 seconds |
| Started | May 07 02:15:08 PM PDT 24 |
| Finished | May 07 02:15:23 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-2044575a-7dd7-4143-b74b-07503f343362 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4059302802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.4059302802 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.495907117 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1523090000 ps |
| CPU time | 3.82 seconds |
| Started | May 07 02:15:14 PM PDT 24 |
| Finished | May 07 02:15:24 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-c5eae7c8-027c-49e2-b02a-4e84f894e97d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=495907117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.495907117 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3219702043 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1420550000 ps |
| CPU time | 3.36 seconds |
| Started | May 07 02:15:15 PM PDT 24 |
| Finished | May 07 02:15:23 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-7b9dd670-de55-4007-adb1-8d291a9f594a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3219702043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3219702043 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.555682934 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1510990000 ps |
| CPU time | 3.77 seconds |
| Started | May 07 02:15:20 PM PDT 24 |
| Finished | May 07 02:15:29 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-b8892f8f-76a7-48d3-b346-809d43af410b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=555682934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.555682934 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.454629415 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1504450000 ps |
| CPU time | 3.23 seconds |
| Started | May 07 02:15:20 PM PDT 24 |
| Finished | May 07 02:15:28 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-a8950ef4-0a6a-43e7-97d9-a5ff66a50929 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=454629415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.454629415 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4050964947 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1562910000 ps |
| CPU time | 7.05 seconds |
| Started | May 07 02:15:25 PM PDT 24 |
| Finished | May 07 02:15:41 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-d6b25178-cd3d-4bee-aceb-b748fb2922ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4050964947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.4050964947 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3801641093 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1439710000 ps |
| CPU time | 5.29 seconds |
| Started | May 07 02:15:25 PM PDT 24 |
| Finished | May 07 02:15:37 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-b1d796ca-1b82-4a7f-b259-18b657949715 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3801641093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3801641093 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.460468364 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1482150000 ps |
| CPU time | 5.34 seconds |
| Started | May 07 02:15:27 PM PDT 24 |
| Finished | May 07 02:15:40 PM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-b1edc2b5-1ebc-49d9-9795-7ab46ecfd182 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=460468364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.460468364 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4255040610 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1548630000 ps |
| CPU time | 3.74 seconds |
| Started | May 07 02:15:35 PM PDT 24 |
| Finished | May 07 02:15:44 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-7484f0b2-82df-4e6c-b2c9-4930ac15e658 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4255040610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.4255040610 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.765497974 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1415750000 ps |
| CPU time | 3.81 seconds |
| Started | May 07 02:15:35 PM PDT 24 |
| Finished | May 07 02:15:44 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-80bd1c17-3677-4b52-b300-3683d8720ce9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=765497974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.765497974 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2967013890 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1567050000 ps |
| CPU time | 4.74 seconds |
| Started | May 07 02:15:40 PM PDT 24 |
| Finished | May 07 02:15:51 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-6e0c882c-89ac-41db-906a-2257bdc45131 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2967013890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2967013890 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1280855794 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1423410000 ps |
| CPU time | 2.98 seconds |
| Started | May 07 02:15:39 PM PDT 24 |
| Finished | May 07 02:15:47 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-dec39927-105d-4689-a912-75b049048d76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1280855794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1280855794 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.396576256 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1434030000 ps |
| CPU time | 4.62 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:55 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-d97d8c5a-4317-42d7-a322-4142a42c76a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=396576256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.396576256 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2200441997 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1427570000 ps |
| CPU time | 3.61 seconds |
| Started | May 07 02:15:37 PM PDT 24 |
| Finished | May 07 02:15:45 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-4a750a41-429f-413a-8777-b29a92d89158 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2200441997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2200441997 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4135796128 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1605330000 ps |
| CPU time | 5.33 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:57 PM PDT 24 |
| Peak memory | 164732 kb |
| Host | smart-1b9984ce-3520-41b8-bf5d-39ecf34e7319 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4135796128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4135796128 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.266925390 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1582610000 ps |
| CPU time | 6.99 seconds |
| Started | May 07 02:15:39 PM PDT 24 |
| Finished | May 07 02:15:54 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-9528e264-19ed-4900-baef-7ed1f6f416f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=266925390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.266925390 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1320204338 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1465110000 ps |
| CPU time | 4.51 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:55 PM PDT 24 |
| Peak memory | 164720 kb |
| Host | smart-bb76fdf4-b3c5-440d-9a66-56b198a5afc2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1320204338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1320204338 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.977812793 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1542630000 ps |
| CPU time | 5.02 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:56 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-e83b04ac-7a96-4f43-b105-95e08e1f00c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=977812793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.977812793 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2338291487 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1429310000 ps |
| CPU time | 4.05 seconds |
| Started | May 07 02:15:45 PM PDT 24 |
| Finished | May 07 02:15:55 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-bd0fd51e-abb6-4b99-88cc-da10031cfbcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2338291487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2338291487 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3377400283 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1477670000 ps |
| CPU time | 5.15 seconds |
| Started | May 07 02:15:04 PM PDT 24 |
| Finished | May 07 02:15:17 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-543a6e53-7d2a-4e3c-ac2c-29e420440469 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3377400283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3377400283 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3361567679 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1495450000 ps |
| CPU time | 5.7 seconds |
| Started | May 07 02:15:46 PM PDT 24 |
| Finished | May 07 02:15:59 PM PDT 24 |
| Peak memory | 165008 kb |
| Host | smart-bb2a443c-41b5-4672-8ae8-ddf9c1e7ec07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3361567679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3361567679 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.658823560 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1329530000 ps |
| CPU time | 4.91 seconds |
| Started | May 07 02:15:45 PM PDT 24 |
| Finished | May 07 02:15:57 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-e32000d0-7853-4ff8-9ec3-2e773d55e2e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=658823560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.658823560 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1038362672 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1514850000 ps |
| CPU time | 6.25 seconds |
| Started | May 07 02:15:45 PM PDT 24 |
| Finished | May 07 02:15:59 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-8bf8cc1c-a26c-447f-ad5c-fc8f0102d4c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1038362672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1038362672 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2527999161 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1524910000 ps |
| CPU time | 6.2 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:58 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-ef7becde-4e86-4b31-b4f5-0923ed2279c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2527999161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2527999161 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3574366205 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1505430000 ps |
| CPU time | 2.9 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:51 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-824fe6bb-3731-4bc3-8379-dfdc9fd20cdb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3574366205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3574366205 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2161688250 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1515510000 ps |
| CPU time | 3.45 seconds |
| Started | May 07 02:15:44 PM PDT 24 |
| Finished | May 07 02:15:52 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-f09faf49-367a-4874-be74-88822fd2e277 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2161688250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2161688250 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2025728728 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1311350000 ps |
| CPU time | 4.31 seconds |
| Started | May 07 02:15:50 PM PDT 24 |
| Finished | May 07 02:16:00 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-a00a8ed6-628f-44b0-b6ac-e9b5c7370961 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2025728728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2025728728 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4011153993 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1499370000 ps |
| CPU time | 4.27 seconds |
| Started | May 07 02:15:49 PM PDT 24 |
| Finished | May 07 02:15:59 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-f0152c18-027e-4527-9ade-091a0ba5d99d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4011153993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4011153993 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1198236399 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1381070000 ps |
| CPU time | 5.05 seconds |
| Started | May 07 02:15:50 PM PDT 24 |
| Finished | May 07 02:16:01 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-1851a773-f68e-4ca3-80c1-4e67c42d7edf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1198236399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1198236399 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.97368999 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1516310000 ps |
| CPU time | 5.76 seconds |
| Started | May 07 02:15:50 PM PDT 24 |
| Finished | May 07 02:16:03 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-e634a3f7-8267-44b1-8642-195a09f60995 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=97368999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.97368999 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1910700525 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1284950000 ps |
| CPU time | 3.13 seconds |
| Started | May 07 02:15:04 PM PDT 24 |
| Finished | May 07 02:15:12 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-07e4387a-9424-4081-904b-441ce7eac382 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1910700525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1910700525 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.490573087 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1549430000 ps |
| CPU time | 6.6 seconds |
| Started | May 07 02:15:50 PM PDT 24 |
| Finished | May 07 02:16:04 PM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-c6616746-aebc-4505-8fd2-23cb542a32f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=490573087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.490573087 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1677655420 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1454570000 ps |
| CPU time | 6.92 seconds |
| Started | May 07 02:15:49 PM PDT 24 |
| Finished | May 07 02:16:03 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-a062d97c-1650-437c-be1f-68440f33ee6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1677655420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1677655420 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2747347949 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1562650000 ps |
| CPU time | 4.16 seconds |
| Started | May 07 02:16:00 PM PDT 24 |
| Finished | May 07 02:16:10 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-b00743b9-ca38-4662-bb8b-b79fd30c3afd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2747347949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2747347949 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1349325637 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1445590000 ps |
| CPU time | 5.54 seconds |
| Started | May 07 02:15:58 PM PDT 24 |
| Finished | May 07 02:16:10 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-4e362412-30f1-4e9f-bc02-bef0d1bbb2e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1349325637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1349325637 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2171585544 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1383990000 ps |
| CPU time | 3.8 seconds |
| Started | May 07 02:16:01 PM PDT 24 |
| Finished | May 07 02:16:10 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-47ff6dc1-94e4-4bef-8d8a-86349836e0f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2171585544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2171585544 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.876022832 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1511050000 ps |
| CPU time | 4.14 seconds |
| Started | May 07 02:16:01 PM PDT 24 |
| Finished | May 07 02:16:11 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-1f719330-bc11-4a25-91a3-3890e958b770 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=876022832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.876022832 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2557881146 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1613730000 ps |
| CPU time | 6.19 seconds |
| Started | May 07 02:15:56 PM PDT 24 |
| Finished | May 07 02:16:09 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-97b7600c-f9d6-42da-9ef9-16487500105c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2557881146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2557881146 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2777493404 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1608330000 ps |
| CPU time | 5.03 seconds |
| Started | May 07 02:16:01 PM PDT 24 |
| Finished | May 07 02:16:13 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-6f37d72c-84a3-42de-a5c0-c39f1285b5af |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2777493404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2777493404 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2402108252 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1470170000 ps |
| CPU time | 5.69 seconds |
| Started | May 07 02:16:01 PM PDT 24 |
| Finished | May 07 02:16:14 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-111a87be-35ef-4c3e-b5f9-3b7fdf96e414 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2402108252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2402108252 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1327991162 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1492050000 ps |
| CPU time | 3.14 seconds |
| Started | May 07 02:16:01 PM PDT 24 |
| Finished | May 07 02:16:08 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-9b7ccda3-cff9-4cee-9498-18f2d609bc74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1327991162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1327991162 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1863975801 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1370890000 ps |
| CPU time | 5.53 seconds |
| Started | May 07 02:15:04 PM PDT 24 |
| Finished | May 07 02:15:18 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-6875e91a-b24b-4d79-9e76-e24996a72aba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1863975801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1863975801 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3195317654 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1390850000 ps |
| CPU time | 5.8 seconds |
| Started | May 07 02:15:03 PM PDT 24 |
| Finished | May 07 02:15:16 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-6e3b75e7-7c74-470e-a3df-f58d4e11e4e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3195317654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3195317654 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.157850454 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1556050000 ps |
| CPU time | 5.47 seconds |
| Started | May 07 02:15:05 PM PDT 24 |
| Finished | May 07 02:15:17 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-aee04992-77da-4e0f-acd1-819bc988e3eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=157850454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.157850454 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3069815002 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1478130000 ps |
| CPU time | 4.59 seconds |
| Started | May 07 02:15:11 PM PDT 24 |
| Finished | May 07 02:15:22 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-f6c77e45-4133-448b-9b32-b537cefd7eeb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3069815002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3069815002 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2417309977 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1461430000 ps |
| CPU time | 6.84 seconds |
| Started | May 07 02:15:10 PM PDT 24 |
| Finished | May 07 02:15:24 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-045ef305-1bd1-4e12-9178-5f80bd05df6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2417309977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2417309977 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |