| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2384296632 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2191341241 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2368034093 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3570223344 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2386244180 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3350576779 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2105095072 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1142310138 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3024628250 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2751431877 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.128837165 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1974194731 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3770614837 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.308474293 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2808481349 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2214691075 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2530221998 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1148256981 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3611884668 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2234790623 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2097109614 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2004588413 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2352685133 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.577445699 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3206796575 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2700166433 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1683446103 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3879645807 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3022676223 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2902200623 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3931193261 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3576604457 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3804252712 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2807290578 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1151835350 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3549311416 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1352200850 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3776057291 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2708249732 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.499885512 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1943901583 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.305794520 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1005938972 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3856360342 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.690264161 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3018557101 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4175042486 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.473236268 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3732987523 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.561932433 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.816350863 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1019293489 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3589271963 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.516616675 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.707792136 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3530048770 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3165392761 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.900064998 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2434531013 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1368973658 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3851031464 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2439951722 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2251731797 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1315757151 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1479741753 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2853497124 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4013598951 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.209040861 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2156129739 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1261205348 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.441690136 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3226170516 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2539662296 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2729761097 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3386838695 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.837949153 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1220998512 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2117832008 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.159190521 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1453350738 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.584382036 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.155809223 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.302513447 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4206264902 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3921040294 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.269249367 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3976207973 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1245168500 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1251407636 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1563097456 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.864696338 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1427845707 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1465553860 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1421462157 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2261881946 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2903973119 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.286937604 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3865154103 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2056429506 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.744583870 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1594031295 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1915890128 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1136602844 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3719781692 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1570122729 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.581787199 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.233887659 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2000151160 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2182187886 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1080206544 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3446680038 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1332122969 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3574849122 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3695974789 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1853450762 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3694958640 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1385289635 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1394399877 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.859609761 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1836980864 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1683314008 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3590098592 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2855357691 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1968765068 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.633295457 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2301358256 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2301559847 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.867245912 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2002431337 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1717575772 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1964767973 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3283705388 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2657533187 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3904402162 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2043819212 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3356652863 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2112030238 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2529279166 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3753321542 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3560430405 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.72373643 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3948791876 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3519984378 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2926003487 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3057400929 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1798421948 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2427795017 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2956793989 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.852569513 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.331103451 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3418737873 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3552092151 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1807911071 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3320999558 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3416661851 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1879896132 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2269432413 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3305928441 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4448124 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.12983056 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2172160544 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1089866480 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3660923285 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1367762064 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2348351075 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.444411594 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2376923628 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3694891400 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4243577776 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2718873834 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3953532555 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.972360118 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4199961939 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.41379705 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1018072721 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2741463026 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2056061624 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1900445730 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1178913224 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4176321478 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1570094818 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3908138001 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.217037932 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3312940640 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1104863406 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1764159308 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2578700778 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3758115328 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.841929839 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2549362597 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4287520656 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3262550725 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2801459 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3581610904 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2248494956 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3330210769 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3285649331 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.783405242 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.349038547 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1761982535 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3305928441 | May 09 12:28:04 PM PDT 24 | May 09 12:28:17 PM PDT 24 | 1535290000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2384296632 | May 09 12:31:33 PM PDT 24 | May 09 12:31:52 PM PDT 24 | 1365450000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3660923285 | May 09 12:26:14 PM PDT 24 | May 09 12:26:25 PM PDT 24 | 1458790000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2269432413 | May 09 12:28:50 PM PDT 24 | May 09 12:28:59 PM PDT 24 | 1383370000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3262550725 | May 09 12:31:34 PM PDT 24 | May 09 12:31:53 PM PDT 24 | 1478290000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2376923628 | May 09 12:31:52 PM PDT 24 | May 09 12:32:11 PM PDT 24 | 1499950000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1178913224 | May 09 12:30:16 PM PDT 24 | May 09 12:30:26 PM PDT 24 | 1283750000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1764159308 | May 09 12:30:32 PM PDT 24 | May 09 12:30:44 PM PDT 24 | 1473410000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3908138001 | May 09 12:27:46 PM PDT 24 | May 09 12:27:56 PM PDT 24 | 1382790000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.841929839 | May 09 12:31:53 PM PDT 24 | May 09 12:32:11 PM PDT 24 | 1451930000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3320999558 | May 09 12:29:45 PM PDT 24 | May 09 12:29:56 PM PDT 24 | 1390710000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2741463026 | May 09 12:28:57 PM PDT 24 | May 09 12:29:10 PM PDT 24 | 1569810000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.444411594 | May 09 12:27:56 PM PDT 24 | May 09 12:28:06 PM PDT 24 | 1570850000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3330210769 | May 09 12:26:16 PM PDT 24 | May 09 12:26:27 PM PDT 24 | 1531230000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.972360118 | May 09 12:31:52 PM PDT 24 | May 09 12:32:10 PM PDT 24 | 1472770000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2801459 | May 09 12:31:52 PM PDT 24 | May 09 12:32:10 PM PDT 24 | 1347490000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3416661851 | May 09 12:29:54 PM PDT 24 | May 09 12:30:04 PM PDT 24 | 1327350000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4448124 | May 09 12:27:45 PM PDT 24 | May 09 12:27:57 PM PDT 24 | 1596730000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3694891400 | May 09 12:28:58 PM PDT 24 | May 09 12:29:10 PM PDT 24 | 1581590000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4243577776 | May 09 12:25:32 PM PDT 24 | May 09 12:25:43 PM PDT 24 | 1435610000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3581610904 | May 09 12:28:28 PM PDT 24 | May 09 12:28:39 PM PDT 24 | 1460870000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3285649331 | May 09 12:27:54 PM PDT 24 | May 09 12:28:06 PM PDT 24 | 1387870000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2056061624 | May 09 12:28:53 PM PDT 24 | May 09 12:29:02 PM PDT 24 | 1429190000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1570094818 | May 09 12:27:24 PM PDT 24 | May 09 12:27:33 PM PDT 24 | 1333050000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2248494956 | May 09 12:28:58 PM PDT 24 | May 09 12:29:10 PM PDT 24 | 1400530000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1018072721 | May 09 12:31:30 PM PDT 24 | May 09 12:31:45 PM PDT 24 | 1494590000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1104863406 | May 09 12:25:13 PM PDT 24 | May 09 12:25:25 PM PDT 24 | 1539090000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3953532555 | May 09 12:31:53 PM PDT 24 | May 09 12:32:11 PM PDT 24 | 1550950000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2718873834 | May 09 12:29:53 PM PDT 24 | May 09 12:30:04 PM PDT 24 | 1444190000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1807911071 | May 09 12:26:58 PM PDT 24 | May 09 12:27:11 PM PDT 24 | 1595170000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1879896132 | May 09 12:31:52 PM PDT 24 | May 09 12:32:11 PM PDT 24 | 1505990000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1367762064 | May 09 12:26:42 PM PDT 24 | May 09 12:26:52 PM PDT 24 | 1356110000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2549362597 | May 09 12:28:57 PM PDT 24 | May 09 12:29:10 PM PDT 24 | 1585590000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.41379705 | May 09 12:25:53 PM PDT 24 | May 09 12:26:04 PM PDT 24 | 1456450000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4199961939 | May 09 12:30:29 PM PDT 24 | May 09 12:30:41 PM PDT 24 | 1497090000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4176321478 | May 09 12:29:47 PM PDT 24 | May 09 12:29:58 PM PDT 24 | 1465350000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1761982535 | May 09 12:25:31 PM PDT 24 | May 09 12:25:41 PM PDT 24 | 1498090000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.349038547 | May 09 12:28:57 PM PDT 24 | May 09 12:29:09 PM PDT 24 | 1470970000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2578700778 | May 09 12:28:18 PM PDT 24 | May 09 12:28:28 PM PDT 24 | 1412510000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2172160544 | May 09 12:28:36 PM PDT 24 | May 09 12:28:47 PM PDT 24 | 1590910000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3312940640 | May 09 12:28:26 PM PDT 24 | May 09 12:28:33 PM PDT 24 | 1251590000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1900445730 | May 09 12:27:57 PM PDT 24 | May 09 12:28:07 PM PDT 24 | 1419310000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.783405242 | May 09 12:29:45 PM PDT 24 | May 09 12:30:00 PM PDT 24 | 1551370000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.12983056 | May 09 12:27:23 PM PDT 24 | May 09 12:27:33 PM PDT 24 | 1514910000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1089866480 | May 09 12:28:08 PM PDT 24 | May 09 12:28:17 PM PDT 24 | 1387310000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2348351075 | May 09 12:28:57 PM PDT 24 | May 09 12:29:09 PM PDT 24 | 1404710000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3758115328 | May 09 12:27:24 PM PDT 24 | May 09 12:27:36 PM PDT 24 | 1488390000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3552092151 | May 09 12:26:22 PM PDT 24 | May 09 12:26:34 PM PDT 24 | 1472710000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.217037932 | May 09 12:28:18 PM PDT 24 | May 09 12:28:30 PM PDT 24 | 1429590000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4287520656 | May 09 12:31:52 PM PDT 24 | May 09 12:32:10 PM PDT 24 | 1454410000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3057400929 | May 09 12:53:10 PM PDT 24 | May 09 12:53:25 PM PDT 24 | 1549190000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2000151160 | May 09 12:52:54 PM PDT 24 | May 09 12:53:07 PM PDT 24 | 1519170000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.331103451 | May 09 12:52:44 PM PDT 24 | May 09 12:52:52 PM PDT 24 | 1402130000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1798421948 | May 09 12:53:11 PM PDT 24 | May 09 12:53:20 PM PDT 24 | 1444890000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1385289635 | May 09 12:52:55 PM PDT 24 | May 09 12:53:06 PM PDT 24 | 1253490000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3570223344 | May 09 12:52:45 PM PDT 24 | May 09 12:52:54 PM PDT 24 | 1408130000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3356652863 | May 09 12:52:42 PM PDT 24 | May 09 12:52:53 PM PDT 24 | 1494890000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3574849122 | May 09 12:52:55 PM PDT 24 | May 09 12:53:07 PM PDT 24 | 1538030000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2529279166 | May 09 12:53:14 PM PDT 24 | May 09 12:53:29 PM PDT 24 | 1603570000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2427795017 | May 09 12:52:44 PM PDT 24 | May 09 12:52:55 PM PDT 24 | 1451970000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3694958640 | May 09 12:52:54 PM PDT 24 | May 09 12:53:08 PM PDT 24 | 1510390000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2657533187 | May 09 12:52:55 PM PDT 24 | May 09 12:53:06 PM PDT 24 | 1493370000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2956793989 | May 09 12:52:42 PM PDT 24 | May 09 12:52:51 PM PDT 24 | 1177410000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1836980864 | May 09 12:52:54 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1440050000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.859609761 | May 09 12:52:56 PM PDT 24 | May 09 12:53:10 PM PDT 24 | 1618290000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3590098592 | May 09 12:52:55 PM PDT 24 | May 09 12:53:07 PM PDT 24 | 1500530000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1853450762 | May 09 12:52:55 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1507310000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.72373643 | May 09 12:53:11 PM PDT 24 | May 09 12:53:22 PM PDT 24 | 1500370000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2182187886 | May 09 12:52:55 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1198490000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2301358256 | May 09 12:52:54 PM PDT 24 | May 09 12:53:04 PM PDT 24 | 1492550000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3519984378 | May 09 12:53:13 PM PDT 24 | May 09 12:53:26 PM PDT 24 | 1420790000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3560430405 | May 09 12:53:11 PM PDT 24 | May 09 12:53:22 PM PDT 24 | 1417590000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2043819212 | May 09 12:53:12 PM PDT 24 | May 09 12:53:25 PM PDT 24 | 1489590000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.867245912 | May 09 12:52:54 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1381250000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3418737873 | May 09 12:52:44 PM PDT 24 | May 09 12:52:52 PM PDT 24 | 1077710000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3753321542 | May 09 12:53:11 PM PDT 24 | May 09 12:53:21 PM PDT 24 | 1343090000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.233887659 | May 09 12:52:43 PM PDT 24 | May 09 12:52:54 PM PDT 24 | 1296390000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3283705388 | May 09 12:52:55 PM PDT 24 | May 09 12:53:07 PM PDT 24 | 1344010000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1080206544 | May 09 12:52:55 PM PDT 24 | May 09 12:53:04 PM PDT 24 | 1068530000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1964767973 | May 09 12:52:55 PM PDT 24 | May 09 12:53:07 PM PDT 24 | 1294270000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3948791876 | May 09 12:53:11 PM PDT 24 | May 09 12:53:21 PM PDT 24 | 1330910000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1683314008 | May 09 12:52:53 PM PDT 24 | May 09 12:53:04 PM PDT 24 | 1448310000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3719781692 | May 09 12:52:42 PM PDT 24 | May 09 12:52:52 PM PDT 24 | 1606570000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1332122969 | May 09 12:52:59 PM PDT 24 | May 09 12:53:08 PM PDT 24 | 1304690000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2855357691 | May 09 12:52:55 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1415050000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1394399877 | May 09 12:52:56 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1347710000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1717575772 | May 09 12:52:56 PM PDT 24 | May 09 12:53:11 PM PDT 24 | 1481650000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2112030238 | May 09 12:53:12 PM PDT 24 | May 09 12:53:26 PM PDT 24 | 1427590000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1136602844 | May 09 12:52:43 PM PDT 24 | May 09 12:52:55 PM PDT 24 | 1556510000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2301559847 | May 09 12:52:56 PM PDT 24 | May 09 12:53:08 PM PDT 24 | 1327110000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.852569513 | May 09 12:52:45 PM PDT 24 | May 09 12:52:57 PM PDT 24 | 1479830000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3446680038 | May 09 12:52:53 PM PDT 24 | May 09 12:53:05 PM PDT 24 | 1381630000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.581787199 | May 09 12:52:47 PM PDT 24 | May 09 12:52:57 PM PDT 24 | 1361530000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1968765068 | May 09 12:52:58 PM PDT 24 | May 09 12:53:10 PM PDT 24 | 1455230000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3695974789 | May 09 12:52:43 PM PDT 24 | May 09 12:52:55 PM PDT 24 | 1543770000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2002431337 | May 09 12:52:56 PM PDT 24 | May 09 12:53:09 PM PDT 24 | 1358950000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3904402162 | May 09 12:53:12 PM PDT 24 | May 09 12:53:23 PM PDT 24 | 1482150000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1570122729 | May 09 12:52:43 PM PDT 24 | May 09 12:52:56 PM PDT 24 | 1520810000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2926003487 | May 09 12:53:11 PM PDT 24 | May 09 12:53:21 PM PDT 24 | 1071170000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.633295457 | May 09 12:52:44 PM PDT 24 | May 09 12:52:58 PM PDT 24 | 1513790000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2191341241 | May 09 12:53:13 PM PDT 24 | May 09 01:22:45 PM PDT 24 | 336788870000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.584382036 | May 09 12:53:10 PM PDT 24 | May 09 01:20:49 PM PDT 24 | 336333210000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4206264902 | May 09 12:53:13 PM PDT 24 | May 09 01:29:18 PM PDT 24 | 336812830000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1465553860 | May 09 12:53:15 PM PDT 24 | May 09 01:21:22 PM PDT 24 | 336392370000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2903973119 | May 09 12:53:12 PM PDT 24 | May 09 01:25:24 PM PDT 24 | 337007090000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.155809223 | May 09 12:53:11 PM PDT 24 | May 09 01:22:41 PM PDT 24 | 336511230000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.837949153 | May 09 12:53:12 PM PDT 24 | May 09 01:24:51 PM PDT 24 | 336844250000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3865154103 | May 09 12:53:15 PM PDT 24 | May 09 01:29:04 PM PDT 24 | 336784470000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3851031464 | May 09 12:53:11 PM PDT 24 | May 09 01:21:53 PM PDT 24 | 336959770000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3386838695 | May 09 12:53:16 PM PDT 24 | May 09 01:31:00 PM PDT 24 | 336611310000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.269249367 | May 09 12:53:12 PM PDT 24 | May 09 01:24:38 PM PDT 24 | 336426490000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1479741753 | May 09 12:53:12 PM PDT 24 | May 09 01:23:14 PM PDT 24 | 336533970000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1368973658 | May 09 12:53:15 PM PDT 24 | May 09 01:24:37 PM PDT 24 | 336651530000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1594031295 | May 09 12:53:10 PM PDT 24 | May 09 01:27:24 PM PDT 24 | 337067990000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3226170516 | May 09 12:53:14 PM PDT 24 | May 09 01:23:37 PM PDT 24 | 336412210000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2853497124 | May 09 12:53:16 PM PDT 24 | May 09 01:25:52 PM PDT 24 | 336697070000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3921040294 | May 09 12:53:13 PM PDT 24 | May 09 01:23:11 PM PDT 24 | 336989570000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2729761097 | May 09 12:53:11 PM PDT 24 | May 09 01:24:40 PM PDT 24 | 336903670000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1915890128 | May 09 12:53:12 PM PDT 24 | May 09 01:23:08 PM PDT 24 | 336848730000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1315757151 | May 09 12:53:13 PM PDT 24 | May 09 01:25:53 PM PDT 24 | 336409170000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.744583870 | May 09 12:53:13 PM PDT 24 | May 09 01:23:50 PM PDT 24 | 336449510000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.441690136 | May 09 12:53:15 PM PDT 24 | May 09 01:24:11 PM PDT 24 | 336948430000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4013598951 | May 09 12:53:10 PM PDT 24 | May 09 01:23:16 PM PDT 24 | 336848950000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3165392761 | May 09 12:53:10 PM PDT 24 | May 09 01:22:37 PM PDT 24 | 337145710000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2251731797 | May 09 12:53:11 PM PDT 24 | May 09 01:23:13 PM PDT 24 | 336531630000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3530048770 | May 09 12:53:10 PM PDT 24 | May 09 01:26:41 PM PDT 24 | 336478030000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.864696338 | May 09 12:53:16 PM PDT 24 | May 09 01:26:08 PM PDT 24 | 336575250000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1427845707 | May 09 12:53:14 PM PDT 24 | May 09 01:22:31 PM PDT 24 | 336718730000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1421462157 | May 09 12:53:15 PM PDT 24 | May 09 01:28:52 PM PDT 24 | 336904310000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.302513447 | May 09 12:53:13 PM PDT 24 | May 09 01:29:25 PM PDT 24 | 336719330000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1220998512 | May 09 12:53:13 PM PDT 24 | May 09 01:23:29 PM PDT 24 | 336662890000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2434531013 | May 09 12:53:13 PM PDT 24 | May 09 01:20:12 PM PDT 24 | 336747870000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1245168500 | May 09 12:53:13 PM PDT 24 | May 09 01:21:32 PM PDT 24 | 337046350000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1251407636 | May 09 12:53:12 PM PDT 24 | May 09 01:25:29 PM PDT 24 | 336492190000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.900064998 | May 09 12:53:13 PM PDT 24 | May 09 01:24:09 PM PDT 24 | 336336910000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2261881946 | May 09 12:53:16 PM PDT 24 | May 09 01:26:08 PM PDT 24 | 336498210000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1453350738 | May 09 12:53:15 PM PDT 24 | May 09 01:28:51 PM PDT 24 | 336430950000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2156129739 | May 09 12:53:11 PM PDT 24 | May 09 01:21:07 PM PDT 24 | 336806610000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1261205348 | May 09 12:53:15 PM PDT 24 | May 09 01:24:03 PM PDT 24 | 336882710000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.707792136 | May 09 12:53:13 PM PDT 24 | May 09 01:25:58 PM PDT 24 | 337015170000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3976207973 | May 09 12:53:13 PM PDT 24 | May 09 01:29:41 PM PDT 24 | 336878330000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2539662296 | May 09 12:53:11 PM PDT 24 | May 09 01:24:19 PM PDT 24 | 336521070000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.159190521 | May 09 12:53:11 PM PDT 24 | May 09 01:24:49 PM PDT 24 | 336476990000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.516616675 | May 09 12:53:13 PM PDT 24 | May 09 01:25:53 PM PDT 24 | 336977330000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2056429506 | May 09 12:53:12 PM PDT 24 | May 09 01:25:02 PM PDT 24 | 336471850000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1563097456 | May 09 12:53:17 PM PDT 24 | May 09 01:31:05 PM PDT 24 | 336859670000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2117832008 | May 09 12:53:14 PM PDT 24 | May 09 01:23:33 PM PDT 24 | 336512990000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.286937604 | May 09 12:53:12 PM PDT 24 | May 09 01:23:07 PM PDT 24 | 336326330000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.209040861 | May 09 12:53:11 PM PDT 24 | May 09 01:24:32 PM PDT 24 | 336677970000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2439951722 | May 09 12:53:12 PM PDT 24 | May 09 01:24:39 PM PDT 24 | 336686970000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3576604457 | May 09 12:53:25 PM PDT 24 | May 09 01:23:37 PM PDT 24 | 336943930000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2700166433 | May 09 12:53:26 PM PDT 24 | May 09 01:22:46 PM PDT 24 | 336434030000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1005938972 | May 09 12:53:23 PM PDT 24 | May 09 01:22:36 PM PDT 24 | 336620150000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3611884668 | May 09 12:53:26 PM PDT 24 | May 09 01:27:11 PM PDT 24 | 337022210000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2751431877 | May 09 12:53:25 PM PDT 24 | May 09 01:25:59 PM PDT 24 | 336634310000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2004588413 | May 09 12:53:22 PM PDT 24 | May 09 01:26:31 PM PDT 24 | 336872430000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2214691075 | May 09 12:53:13 PM PDT 24 | May 09 01:24:15 PM PDT 24 | 336784310000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4175042486 | May 09 12:53:21 PM PDT 24 | May 09 01:23:19 PM PDT 24 | 336604410000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3931193261 | May 09 12:53:22 PM PDT 24 | May 09 01:28:23 PM PDT 24 | 336865270000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2368034093 | May 09 12:53:22 PM PDT 24 | May 09 01:19:16 PM PDT 24 | 336741770000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3776057291 | May 09 12:53:22 PM PDT 24 | May 09 01:22:50 PM PDT 24 | 336412530000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.308474293 | May 09 12:53:24 PM PDT 24 | May 09 01:24:00 PM PDT 24 | 336714490000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2902200623 | May 09 12:53:22 PM PDT 24 | May 09 01:29:21 PM PDT 24 | 336698790000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1151835350 | May 09 12:53:24 PM PDT 24 | May 09 01:21:23 PM PDT 24 | 336688870000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3770614837 | May 09 12:53:22 PM PDT 24 | May 09 01:22:37 PM PDT 24 | 337094410000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3549311416 | May 09 12:53:24 PM PDT 24 | May 09 01:23:10 PM PDT 24 | 336974810000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1148256981 | May 09 12:53:21 PM PDT 24 | May 09 01:22:37 PM PDT 24 | 336987990000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1974194731 | May 09 12:53:22 PM PDT 24 | May 09 01:22:11 PM PDT 24 | 336890410000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2708249732 | May 09 12:53:21 PM PDT 24 | May 09 01:20:21 PM PDT 24 | 336900610000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2352685133 | May 09 12:53:26 PM PDT 24 | May 09 01:21:56 PM PDT 24 | 336790270000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3018557101 | May 09 12:53:28 PM PDT 24 | May 09 01:25:54 PM PDT 24 | 336820710000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3350576779 | May 09 12:53:17 PM PDT 24 | May 09 01:30:51 PM PDT 24 | 336892710000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2097109614 | May 09 12:53:25 PM PDT 24 | May 09 01:21:27 PM PDT 24 | 336854270000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.473236268 | May 09 12:53:22 PM PDT 24 | May 09 01:21:48 PM PDT 24 | 336376270000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3732987523 | May 09 12:53:23 PM PDT 24 | May 09 01:24:31 PM PDT 24 | 336720730000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3024628250 | May 09 12:53:24 PM PDT 24 | May 09 01:23:06 PM PDT 24 | 336904170000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.305794520 | May 09 12:53:24 PM PDT 24 | May 09 01:24:01 PM PDT 24 | 336352510000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1142310138 | May 09 12:53:21 PM PDT 24 | May 09 01:18:47 PM PDT 24 | 336440090000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.499885512 | May 09 12:53:24 PM PDT 24 | May 09 01:23:19 PM PDT 24 | 336980990000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2105095072 | May 09 12:53:26 PM PDT 24 | May 09 01:26:56 PM PDT 24 | 336341730000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.816350863 | May 09 12:53:22 PM PDT 24 | May 09 01:23:14 PM PDT 24 | 336645210000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2234790623 | May 09 12:53:25 PM PDT 24 | May 09 01:21:48 PM PDT 24 | 336953230000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.690264161 | May 09 12:53:25 PM PDT 24 | May 09 01:24:40 PM PDT 24 | 336329010000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2807290578 | May 09 12:53:21 PM PDT 24 | May 09 01:21:57 PM PDT 24 | 336756970000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3206796575 | May 09 12:53:25 PM PDT 24 | May 09 01:22:17 PM PDT 24 | 336732230000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1352200850 | May 09 12:53:21 PM PDT 24 | May 09 01:20:50 PM PDT 24 | 337094850000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.561932433 | May 09 12:53:20 PM PDT 24 | May 09 01:19:23 PM PDT 24 | 336622570000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3804252712 | May 09 12:53:21 PM PDT 24 | May 09 01:21:05 PM PDT 24 | 336682930000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3589271963 | May 09 12:53:24 PM PDT 24 | May 09 01:23:04 PM PDT 24 | 337044590000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3856360342 | May 09 12:53:28 PM PDT 24 | May 09 01:25:47 PM PDT 24 | 336650270000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.577445699 | May 09 12:53:20 PM PDT 24 | May 09 01:22:47 PM PDT 24 | 336716650000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.128837165 | May 09 12:53:24 PM PDT 24 | May 09 01:27:27 PM PDT 24 | 336915690000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1019293489 | May 09 12:53:22 PM PDT 24 | May 09 01:26:22 PM PDT 24 | 336948890000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2386244180 | May 09 12:53:17 PM PDT 24 | May 09 01:30:37 PM PDT 24 | 336772590000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3022676223 | May 09 12:53:26 PM PDT 24 | May 09 01:22:05 PM PDT 24 | 337122430000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1943901583 | May 09 12:53:22 PM PDT 24 | May 09 01:19:30 PM PDT 24 | 336747110000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2530221998 | May 09 12:53:22 PM PDT 24 | May 09 01:21:59 PM PDT 24 | 336956750000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3879645807 | May 09 12:53:29 PM PDT 24 | May 09 01:21:05 PM PDT 24 | 336504910000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2808481349 | May 09 12:53:23 PM PDT 24 | May 09 01:27:09 PM PDT 24 | 336329650000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1683446103 | May 09 12:53:22 PM PDT 24 | May 09 01:22:57 PM PDT 24 | 337022930000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2384296632 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1365450000 ps |
| CPU time | 3.42 seconds |
| Started | May 09 12:31:33 PM PDT 24 |
| Finished | May 09 12:31:52 PM PDT 24 |
| Peak memory | 163004 kb |
| Host | smart-7d187f52-4bed-49bd-95f5-57b0644bb9bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2384296632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2384296632 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2191341241 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336788870000 ps |
| CPU time | 720.64 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:22:45 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-719efecf-9224-4ea7-900e-ce87c0d1d4f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2191341241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2191341241 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2368034093 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336741770000 ps |
| CPU time | 628.55 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:19:16 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-96aefcb5-796a-4213-ab20-dbda0276eefa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2368034093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2368034093 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3570223344 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1408130000 ps |
| CPU time | 3.15 seconds |
| Started | May 09 12:52:45 PM PDT 24 |
| Finished | May 09 12:52:54 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-47c1be9b-805c-4d8c-a5b1-2086a0be82ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3570223344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3570223344 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2386244180 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336772590000 ps |
| CPU time | 907.25 seconds |
| Started | May 09 12:53:17 PM PDT 24 |
| Finished | May 09 01:30:37 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-44daa49c-d0a8-462d-85d3-24759a986100 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2386244180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2386244180 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3350576779 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336892710000 ps |
| CPU time | 909.34 seconds |
| Started | May 09 12:53:17 PM PDT 24 |
| Finished | May 09 01:30:51 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-9390d0b9-ce5f-48f6-88f1-52878e7c11fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3350576779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3350576779 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2105095072 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336341730000 ps |
| CPU time | 808.49 seconds |
| Started | May 09 12:53:26 PM PDT 24 |
| Finished | May 09 01:26:56 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-a8ca934b-b1d3-4203-9673-2c7299fd7e7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2105095072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2105095072 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1142310138 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336440090000 ps |
| CPU time | 613.55 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:18:47 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-60056173-5951-4291-a576-bc744124ac01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1142310138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1142310138 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3024628250 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336904170000 ps |
| CPU time | 726.53 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:23:06 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-1c15de4b-ce84-4380-ac72-659ede0f81f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3024628250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3024628250 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2751431877 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336634310000 ps |
| CPU time | 782.27 seconds |
| Started | May 09 12:53:25 PM PDT 24 |
| Finished | May 09 01:25:59 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-4c078a57-4a09-4132-9747-49783c22e133 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2751431877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2751431877 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.128837165 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336915690000 ps |
| CPU time | 810.79 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:27:27 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-8343f999-6e12-45f5-86cd-84ec3a582c03 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=128837165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.128837165 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1974194731 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336890410000 ps |
| CPU time | 695.52 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:22:11 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-8f72cacc-66d0-4ffa-b75c-e257feaa2e01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1974194731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1974194731 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3770614837 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 337094410000 ps |
| CPU time | 703.01 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:22:37 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-8897bcec-77af-4273-be41-1b857aec8df1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3770614837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3770614837 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.308474293 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336714490000 ps |
| CPU time | 739.6 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:24:00 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-35f4672e-8470-43ca-9ea4-00c27175f5cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=308474293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.308474293 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2808481349 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336329650000 ps |
| CPU time | 801 seconds |
| Started | May 09 12:53:23 PM PDT 24 |
| Finished | May 09 01:27:09 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-a1aa7f2d-145d-4789-adec-23bdc3584d6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2808481349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2808481349 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2214691075 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336784310000 ps |
| CPU time | 734.16 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:24:15 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-e4c00d0f-9347-4623-a244-5313091d2d42 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2214691075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2214691075 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2530221998 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336956750000 ps |
| CPU time | 689.16 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:21:59 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-30a62daa-83cf-4089-b9ff-b9346bc90399 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2530221998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2530221998 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1148256981 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336987990000 ps |
| CPU time | 715.17 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:22:37 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-44381320-2301-419d-9e57-76a62ef85592 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1148256981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1148256981 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3611884668 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 337022210000 ps |
| CPU time | 821.55 seconds |
| Started | May 09 12:53:26 PM PDT 24 |
| Finished | May 09 01:27:11 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-d2e7b5df-eeee-4fe4-b68e-323176bcd832 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3611884668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3611884668 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2234790623 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336953230000 ps |
| CPU time | 680.24 seconds |
| Started | May 09 12:53:25 PM PDT 24 |
| Finished | May 09 01:21:48 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-37ba88f9-da2f-4923-b36c-0e2bb513794b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2234790623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2234790623 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2097109614 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336854270000 ps |
| CPU time | 682.71 seconds |
| Started | May 09 12:53:25 PM PDT 24 |
| Finished | May 09 01:21:27 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-ecbcfbaa-c03e-43f0-8a06-097207ffd486 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2097109614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2097109614 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2004588413 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336872430000 ps |
| CPU time | 796.49 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:26:31 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-b2bc38f7-7a0b-456d-a9d8-f0b25fb78987 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2004588413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2004588413 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2352685133 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336790270000 ps |
| CPU time | 693.2 seconds |
| Started | May 09 12:53:26 PM PDT 24 |
| Finished | May 09 01:21:56 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-de090adb-4691-414d-bf68-ade9000cafff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2352685133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2352685133 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.577445699 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336716650000 ps |
| CPU time | 712.76 seconds |
| Started | May 09 12:53:20 PM PDT 24 |
| Finished | May 09 01:22:47 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-12db745b-7a87-4c4a-bb27-6e0c90430e97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=577445699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.577445699 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3206796575 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336732230000 ps |
| CPU time | 693.25 seconds |
| Started | May 09 12:53:25 PM PDT 24 |
| Finished | May 09 01:22:17 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-23855733-6f42-4277-96fc-899eda079e8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3206796575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3206796575 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2700166433 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336434030000 ps |
| CPU time | 704.75 seconds |
| Started | May 09 12:53:26 PM PDT 24 |
| Finished | May 09 01:22:46 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-5fa3ceb6-99db-4b9a-823e-cf833bb0222b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2700166433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2700166433 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1683446103 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 337022930000 ps |
| CPU time | 705 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:22:57 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-752433e7-6ac6-454f-b11a-9c241c103e56 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1683446103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1683446103 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3879645807 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336504910000 ps |
| CPU time | 663.64 seconds |
| Started | May 09 12:53:29 PM PDT 24 |
| Finished | May 09 01:21:05 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-cfe2d776-07b7-4376-8a82-d55d7babb367 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3879645807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3879645807 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3022676223 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337122430000 ps |
| CPU time | 696.72 seconds |
| Started | May 09 12:53:26 PM PDT 24 |
| Finished | May 09 01:22:05 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-b01a2c2a-6247-455f-8806-6afba06c5bc2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3022676223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3022676223 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2902200623 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336698790000 ps |
| CPU time | 851.43 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:29:21 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-0e67df57-73b8-4880-9d73-235c5d9a0a8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2902200623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2902200623 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3931193261 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336865270000 ps |
| CPU time | 827.59 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:28:23 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-b39dca0d-819a-4c30-9b16-d16f7248d68d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3931193261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3931193261 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3576604457 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336943930000 ps |
| CPU time | 715.3 seconds |
| Started | May 09 12:53:25 PM PDT 24 |
| Finished | May 09 01:23:37 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-2df82377-3847-47a1-a92b-61dbffc3853b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3576604457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3576604457 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3804252712 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336682930000 ps |
| CPU time | 669.26 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:21:05 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-b7579472-06c7-4e53-95f8-66b8330c5acb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3804252712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3804252712 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2807290578 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336756970000 ps |
| CPU time | 690.27 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:21:57 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-e06271f2-593b-4c7b-8a76-027649be4b16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2807290578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2807290578 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1151835350 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336688870000 ps |
| CPU time | 683.37 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:21:23 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-993a23ab-b91c-417d-a604-fa3487060c57 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1151835350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1151835350 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3549311416 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336974810000 ps |
| CPU time | 725.47 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:23:10 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-8103c3c9-ff83-4928-a4dc-2a3db4c24082 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3549311416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3549311416 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1352200850 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 337094850000 ps |
| CPU time | 666.76 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:20:50 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-59f298c9-2a58-4d5d-ae98-a2968b9068b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1352200850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1352200850 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3776057291 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336412530000 ps |
| CPU time | 708.83 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:22:50 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-330fec11-ce10-48c3-b80a-54a5ff824839 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3776057291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3776057291 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2708249732 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336900610000 ps |
| CPU time | 646.27 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:20:21 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-855f5b08-9569-45d9-bded-73e7eef9ac51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2708249732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2708249732 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.499885512 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336980990000 ps |
| CPU time | 731.82 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:23:19 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-12b6821e-a420-45c6-b656-9e1c92a57d33 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=499885512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.499885512 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1943901583 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336747110000 ps |
| CPU time | 629.83 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:19:30 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-aae19ea6-1ad5-464f-8fe3-5cd9cca055b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1943901583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1943901583 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.305794520 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336352510000 ps |
| CPU time | 743.5 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:24:01 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-9c602128-16e9-4f9c-9216-1c7bf2bae15b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=305794520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.305794520 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1005938972 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336620150000 ps |
| CPU time | 698.05 seconds |
| Started | May 09 12:53:23 PM PDT 24 |
| Finished | May 09 01:22:36 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-9050f116-8510-40e4-8616-801adf232fc8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1005938972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1005938972 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3856360342 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336650270000 ps |
| CPU time | 764.09 seconds |
| Started | May 09 12:53:28 PM PDT 24 |
| Finished | May 09 01:25:47 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-8fa0e2b6-ae78-4d9b-9c94-a83e2e8d7990 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3856360342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3856360342 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.690264161 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336329010000 ps |
| CPU time | 753.45 seconds |
| Started | May 09 12:53:25 PM PDT 24 |
| Finished | May 09 01:24:40 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-e28b30fd-5dea-4567-bd61-6826b71f89a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=690264161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.690264161 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3018557101 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336820710000 ps |
| CPU time | 774.67 seconds |
| Started | May 09 12:53:28 PM PDT 24 |
| Finished | May 09 01:25:54 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-0f1c7a08-107d-40e7-80fe-d73631784aa3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3018557101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3018557101 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4175042486 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336604410000 ps |
| CPU time | 717.27 seconds |
| Started | May 09 12:53:21 PM PDT 24 |
| Finished | May 09 01:23:19 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-9f787c6e-b5d9-49e2-ad0d-3b12378e416a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4175042486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4175042486 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.473236268 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336376270000 ps |
| CPU time | 685.02 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:21:48 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-c7f2d2d7-064a-4c3b-87c9-e48cd1dfa9a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=473236268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.473236268 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3732987523 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336720730000 ps |
| CPU time | 755.83 seconds |
| Started | May 09 12:53:23 PM PDT 24 |
| Finished | May 09 01:24:31 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-948f551f-2133-4339-9729-e9a8e490f734 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3732987523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3732987523 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.561932433 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336622570000 ps |
| CPU time | 629.27 seconds |
| Started | May 09 12:53:20 PM PDT 24 |
| Finished | May 09 01:19:23 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-20cacca2-b3df-453a-a64c-c52cd2641048 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=561932433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.561932433 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.816350863 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336645210000 ps |
| CPU time | 724.53 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:23:14 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-571fe6d8-62dc-448a-95da-57c9e96d9ca0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=816350863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.816350863 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1019293489 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336948890000 ps |
| CPU time | 793.77 seconds |
| Started | May 09 12:53:22 PM PDT 24 |
| Finished | May 09 01:26:22 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-c143ab8f-1a27-406e-b410-bfc0817f8e33 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1019293489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1019293489 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3589271963 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 337044590000 ps |
| CPU time | 716.4 seconds |
| Started | May 09 12:53:24 PM PDT 24 |
| Finished | May 09 01:23:04 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-8a693da6-5c89-44eb-ac91-68db73f0d01f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3589271963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3589271963 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.516616675 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336977330000 ps |
| CPU time | 792.17 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:25:53 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-2be05140-3e91-452a-8200-c9e3caf1132e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=516616675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.516616675 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.707792136 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 337015170000 ps |
| CPU time | 786.57 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:25:58 PM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-a821d3d5-c87d-4075-87b9-c0a62633d05f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=707792136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.707792136 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3530048770 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336478030000 ps |
| CPU time | 808.62 seconds |
| Started | May 09 12:53:10 PM PDT 24 |
| Finished | May 09 01:26:41 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-71279b79-32f9-43a1-b5f6-20683c258557 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3530048770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3530048770 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3165392761 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 337145710000 ps |
| CPU time | 711.08 seconds |
| Started | May 09 12:53:10 PM PDT 24 |
| Finished | May 09 01:22:37 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-3aa6300c-2d15-4ddd-97bd-d0f2ee18d247 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3165392761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3165392761 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.900064998 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336336910000 ps |
| CPU time | 741.83 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:24:09 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-fdb0d23b-1e44-45c5-9740-263dbcdf1569 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=900064998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.900064998 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2434531013 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336747870000 ps |
| CPU time | 653.96 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:20:12 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-d62860d2-1174-413c-afaf-7e3a1c136c39 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2434531013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2434531013 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1368973658 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336651530000 ps |
| CPU time | 764.85 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:24:37 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-cde5c0d2-127d-4b91-bef6-bc3a1fe6d229 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1368973658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1368973658 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3851031464 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336959770000 ps |
| CPU time | 690.14 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:21:53 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-9c8444e6-90a4-4a66-82f5-32f1443a2e58 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3851031464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3851031464 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2439951722 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336686970000 ps |
| CPU time | 763.63 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:24:39 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-ea6eac7d-3aee-4ed7-8665-221e728870a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2439951722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2439951722 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2251731797 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336531630000 ps |
| CPU time | 713.84 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:23:13 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-e5f88d27-8760-4135-810a-c67579092bae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2251731797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2251731797 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1315757151 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336409170000 ps |
| CPU time | 789.33 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:25:53 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-239f1818-e497-411c-88de-8c3ee5acdb9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1315757151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1315757151 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1479741753 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336533970000 ps |
| CPU time | 726.81 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:23:14 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-fb3f892d-3399-4840-8608-2c4ce72c44da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1479741753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1479741753 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2853497124 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336697070000 ps |
| CPU time | 778.5 seconds |
| Started | May 09 12:53:16 PM PDT 24 |
| Finished | May 09 01:25:52 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-7864777e-b3cd-4da0-aeff-014db825295b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2853497124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2853497124 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4013598951 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336848950000 ps |
| CPU time | 720.1 seconds |
| Started | May 09 12:53:10 PM PDT 24 |
| Finished | May 09 01:23:16 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-3c58cbf5-2bdc-43d9-89aa-1af625a09339 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4013598951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4013598951 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.209040861 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336677970000 ps |
| CPU time | 760.77 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:24:32 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-5b337a3d-7da3-4c16-84ff-6ad47516a63e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=209040861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.209040861 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2156129739 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336806610000 ps |
| CPU time | 680.92 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:21:07 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-f398c2df-ef85-427d-a399-f75f612c9af0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2156129739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2156129739 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1261205348 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336882710000 ps |
| CPU time | 747.65 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:24:03 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-68d73adb-86d5-432e-984e-53436c112244 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1261205348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1261205348 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.441690136 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336948430000 ps |
| CPU time | 757.19 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:24:11 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-af1b6369-7c0e-408c-b013-5bfc6b825b4a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=441690136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.441690136 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3226170516 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336412210000 ps |
| CPU time | 744.67 seconds |
| Started | May 09 12:53:14 PM PDT 24 |
| Finished | May 09 01:23:37 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-96edcd62-156a-465c-a338-126db090d409 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3226170516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3226170516 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2539662296 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336521070000 ps |
| CPU time | 763.22 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:24:19 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-e0298b77-c415-4f86-bf85-fdba666b219b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2539662296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2539662296 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2729761097 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336903670000 ps |
| CPU time | 766.37 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:24:40 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-e30a9286-df96-4960-8d82-09b07cfe487e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2729761097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2729761097 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3386838695 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336611310000 ps |
| CPU time | 918.12 seconds |
| Started | May 09 12:53:16 PM PDT 24 |
| Finished | May 09 01:31:00 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-2de24d12-55f9-4da1-b3c7-5b2b94dc3e10 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3386838695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3386838695 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.837949153 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336844250000 ps |
| CPU time | 760.34 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:24:51 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-3f08bce7-f63a-4776-8ad8-e04e6b48c761 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=837949153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.837949153 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1220998512 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336662890000 ps |
| CPU time | 734.3 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:23:29 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-d9d1624f-eab3-4910-93cd-f28c1d14b9c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1220998512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1220998512 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2117832008 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336512990000 ps |
| CPU time | 737.98 seconds |
| Started | May 09 12:53:14 PM PDT 24 |
| Finished | May 09 01:23:33 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-5cd603a5-5d15-46f1-87b6-6ec4297deffb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2117832008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2117832008 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.159190521 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336476990000 ps |
| CPU time | 765.68 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:24:49 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-98c13356-7ef8-4ccf-87a4-4c353b226a58 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=159190521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.159190521 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1453350738 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336430950000 ps |
| CPU time | 850.52 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:28:51 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-f2455df0-436e-4648-a68e-36ebec931fc4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1453350738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1453350738 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.584382036 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336333210000 ps |
| CPU time | 668.9 seconds |
| Started | May 09 12:53:10 PM PDT 24 |
| Finished | May 09 01:20:49 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-d566735e-690c-4dcd-a686-c01b1f915b9a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=584382036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.584382036 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.155809223 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336511230000 ps |
| CPU time | 706.08 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 01:22:41 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-88e1bd97-ad0b-4c73-ab67-c7c4bb5dea00 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=155809223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.155809223 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.302513447 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336719330000 ps |
| CPU time | 860.03 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:29:25 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-17b1ca95-7a3e-4449-a061-ed63c5eba9ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=302513447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.302513447 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4206264902 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336812830000 ps |
| CPU time | 859.02 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:29:18 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-230b9eb8-7f21-46de-acf8-4595683c1a19 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4206264902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4206264902 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3921040294 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336989570000 ps |
| CPU time | 733.41 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:23:11 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-47e948c8-a60a-4cdd-b4d2-1f7ed5d707cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3921040294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3921040294 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.269249367 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336426490000 ps |
| CPU time | 769.7 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:24:38 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-79ee7f74-3b63-4cbf-9c82-bf1f5182e3df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=269249367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.269249367 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3976207973 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336878330000 ps |
| CPU time | 868.46 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:29:41 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-e44e1518-b2c6-4e8d-8c88-f02e4bb1dd25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3976207973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3976207973 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1245168500 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 337046350000 ps |
| CPU time | 690.87 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:21:32 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-b0279699-a8cd-4c12-b095-6602af301f43 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1245168500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1245168500 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1251407636 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336492190000 ps |
| CPU time | 772.26 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:25:29 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-1b97ef04-503c-4531-85c7-76c3601873b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1251407636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1251407636 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1563097456 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336859670000 ps |
| CPU time | 918.65 seconds |
| Started | May 09 12:53:17 PM PDT 24 |
| Finished | May 09 01:31:05 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-6342b9a8-4ec0-4906-be97-e74b072d29c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1563097456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1563097456 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.864696338 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336575250000 ps |
| CPU time | 797.12 seconds |
| Started | May 09 12:53:16 PM PDT 24 |
| Finished | May 09 01:26:08 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-27f73af2-98b9-4061-aba0-c3c91dfb3ce4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=864696338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.864696338 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1427845707 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336718730000 ps |
| CPU time | 722.97 seconds |
| Started | May 09 12:53:14 PM PDT 24 |
| Finished | May 09 01:22:31 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-2f652786-f1f0-46d3-92e4-dc4a61d00005 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1427845707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1427845707 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1465553860 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336392370000 ps |
| CPU time | 685.16 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:21:22 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-51b949aa-ab40-4641-a003-c7902e7cb985 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1465553860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1465553860 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1421462157 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336904310000 ps |
| CPU time | 837.15 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:28:52 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-dc7cbe56-4740-460e-a25a-02fbc74ce729 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1421462157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1421462157 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2261881946 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336498210000 ps |
| CPU time | 788.29 seconds |
| Started | May 09 12:53:16 PM PDT 24 |
| Finished | May 09 01:26:08 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-1c6a529e-7e82-416e-ac32-30ddeff11f74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2261881946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2261881946 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2903973119 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 337007090000 ps |
| CPU time | 770.72 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:25:24 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-584384e9-4fbb-4184-8cf8-1edc7dc020be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2903973119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2903973119 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.286937604 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336326330000 ps |
| CPU time | 724.64 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:23:07 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-a13c3a98-c19a-499e-9ad9-855561baae1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=286937604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.286937604 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3865154103 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336784470000 ps |
| CPU time | 841.72 seconds |
| Started | May 09 12:53:15 PM PDT 24 |
| Finished | May 09 01:29:04 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-dd61e0a9-15ec-4c56-8e4a-19edf1a01d7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3865154103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3865154103 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2056429506 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336471850000 ps |
| CPU time | 759.94 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:25:02 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-da878ae0-f0f6-4732-9445-c488c1d0ecc6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2056429506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2056429506 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.744583870 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336449510000 ps |
| CPU time | 737.81 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 01:23:50 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-4d7cf456-1f3f-426d-bc3b-0597c7a26911 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=744583870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.744583870 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1594031295 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 337067990000 ps |
| CPU time | 813.06 seconds |
| Started | May 09 12:53:10 PM PDT 24 |
| Finished | May 09 01:27:24 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-5a4578da-7a72-41b6-b3cb-6173ac87133b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1594031295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1594031295 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1915890128 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336848730000 ps |
| CPU time | 725.82 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 01:23:08 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-f4748829-2086-4b37-8a8e-6f11dde9d811 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1915890128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1915890128 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1136602844 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1556510000 ps |
| CPU time | 4.45 seconds |
| Started | May 09 12:52:43 PM PDT 24 |
| Finished | May 09 12:52:55 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-6a5fcb81-ead4-4575-8b7f-5a63e1cded78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1136602844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1136602844 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3719781692 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1606570000 ps |
| CPU time | 3.32 seconds |
| Started | May 09 12:52:42 PM PDT 24 |
| Finished | May 09 12:52:52 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-8fd3f72b-8408-4ac7-8003-b0ad8db5b2f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3719781692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3719781692 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1570122729 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1520810000 ps |
| CPU time | 4.98 seconds |
| Started | May 09 12:52:43 PM PDT 24 |
| Finished | May 09 12:52:56 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-0b15110f-f169-43f0-aced-87492385035f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1570122729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1570122729 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.581787199 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1361530000 ps |
| CPU time | 3.78 seconds |
| Started | May 09 12:52:47 PM PDT 24 |
| Finished | May 09 12:52:57 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-823a9cf4-ac54-4ac7-9373-2b85c6ec9350 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=581787199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.581787199 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.233887659 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1296390000 ps |
| CPU time | 3.71 seconds |
| Started | May 09 12:52:43 PM PDT 24 |
| Finished | May 09 12:52:54 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-ef5dc311-5411-48f2-83ee-9b0a48ad55e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=233887659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.233887659 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2000151160 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1519170000 ps |
| CPU time | 5.1 seconds |
| Started | May 09 12:52:54 PM PDT 24 |
| Finished | May 09 12:53:07 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-66408992-faa8-4b07-a92b-447307412e2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2000151160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2000151160 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2182187886 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1198490000 ps |
| CPU time | 3.59 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-0c363900-5ddf-44cb-9041-95c6126aa506 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2182187886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2182187886 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1080206544 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1068530000 ps |
| CPU time | 3.22 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:04 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-f2aecf13-d7bb-4f8f-b231-4658b515a865 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1080206544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1080206544 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3446680038 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1381630000 ps |
| CPU time | 4.41 seconds |
| Started | May 09 12:52:53 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-8f1b5d1a-bdce-45d1-8f3b-11fc8fb56b0b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3446680038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3446680038 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1332122969 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1304690000 ps |
| CPU time | 3.47 seconds |
| Started | May 09 12:52:59 PM PDT 24 |
| Finished | May 09 12:53:08 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-2f8c8ac3-0a8e-4d8e-acc6-f7afe3de6d49 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1332122969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1332122969 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3574849122 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1538030000 ps |
| CPU time | 4.31 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:07 PM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-e31c3b3d-7ae8-404a-8305-2765d48bf8c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3574849122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3574849122 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3695974789 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1543770000 ps |
| CPU time | 4.65 seconds |
| Started | May 09 12:52:43 PM PDT 24 |
| Finished | May 09 12:52:55 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-74ffd49f-eab9-489f-b85a-131271abd3c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3695974789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3695974789 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1853450762 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1507310000 ps |
| CPU time | 3.55 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-e14ad5aa-8f58-4cca-8390-cb20ce04da85 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1853450762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1853450762 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3694958640 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1510390000 ps |
| CPU time | 5.1 seconds |
| Started | May 09 12:52:54 PM PDT 24 |
| Finished | May 09 12:53:08 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-3be92beb-d24e-4e15-8bfb-392600f5c982 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3694958640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3694958640 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1385289635 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1253490000 ps |
| CPU time | 3.92 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:06 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-cbe742df-fe82-4444-83ec-310c52ce3566 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1385289635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1385289635 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1394399877 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1347710000 ps |
| CPU time | 3.21 seconds |
| Started | May 09 12:52:56 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-7e6d7b39-fbbc-4662-9475-1cc2aa69d434 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1394399877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1394399877 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.859609761 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1618290000 ps |
| CPU time | 5.77 seconds |
| Started | May 09 12:52:56 PM PDT 24 |
| Finished | May 09 12:53:10 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-2269cfc8-6dbb-465f-a8d9-662d5ceed813 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=859609761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.859609761 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1836980864 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1440050000 ps |
| CPU time | 4.19 seconds |
| Started | May 09 12:52:54 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-9eea4590-a8d9-4af3-997f-b38fdf9bd419 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1836980864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1836980864 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1683314008 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1448310000 ps |
| CPU time | 4.33 seconds |
| Started | May 09 12:52:53 PM PDT 24 |
| Finished | May 09 12:53:04 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-120030c9-117c-4071-a994-99fd743f6454 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1683314008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1683314008 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3590098592 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1500530000 ps |
| CPU time | 4.8 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:07 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-f44dfb84-7292-44d8-bf88-ce9b90c59fec |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3590098592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3590098592 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2855357691 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1415050000 ps |
| CPU time | 3.65 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-709e9b97-7dea-4d00-ad1e-eb773af24eba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2855357691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2855357691 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1968765068 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1455230000 ps |
| CPU time | 4.87 seconds |
| Started | May 09 12:52:58 PM PDT 24 |
| Finished | May 09 12:53:10 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-82da5245-2079-4332-b408-de57dddc794a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1968765068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1968765068 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.633295457 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1513790000 ps |
| CPU time | 5.41 seconds |
| Started | May 09 12:52:44 PM PDT 24 |
| Finished | May 09 12:52:58 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-79404b8c-63b6-453c-a313-c94c708984a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=633295457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.633295457 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2301358256 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1492550000 ps |
| CPU time | 3.23 seconds |
| Started | May 09 12:52:54 PM PDT 24 |
| Finished | May 09 12:53:04 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-b9b32890-d847-4e0f-8c9a-e55185f80744 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2301358256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2301358256 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2301559847 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1327110000 ps |
| CPU time | 4.46 seconds |
| Started | May 09 12:52:56 PM PDT 24 |
| Finished | May 09 12:53:08 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-e3696834-0a70-4fe5-a05a-07739217fcd3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2301559847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2301559847 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.867245912 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1381250000 ps |
| CPU time | 4.1 seconds |
| Started | May 09 12:52:54 PM PDT 24 |
| Finished | May 09 12:53:05 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-512f4cce-a621-46c4-a240-edad57775ee3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=867245912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.867245912 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2002431337 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1358950000 ps |
| CPU time | 4.87 seconds |
| Started | May 09 12:52:56 PM PDT 24 |
| Finished | May 09 12:53:09 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-8036f051-2616-4970-9661-75df8c5c33de |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2002431337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2002431337 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1717575772 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1481650000 ps |
| CPU time | 5.91 seconds |
| Started | May 09 12:52:56 PM PDT 24 |
| Finished | May 09 12:53:11 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-3dba3ecd-23c5-4acd-957b-ccfa19a10d31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1717575772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1717575772 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1964767973 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1294270000 ps |
| CPU time | 4.72 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:07 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-e5c362bb-5df9-4f84-8a99-b2b74143b131 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1964767973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1964767973 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3283705388 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1344010000 ps |
| CPU time | 4.26 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:07 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-2f7f6e74-e1b7-4bf2-92ca-3cdc27947cda |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3283705388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3283705388 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2657533187 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1493370000 ps |
| CPU time | 4.15 seconds |
| Started | May 09 12:52:55 PM PDT 24 |
| Finished | May 09 12:53:06 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-79879eda-bfdd-46d1-a6bc-2cd33005bab8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2657533187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2657533187 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3904402162 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1482150000 ps |
| CPU time | 4 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 12:53:23 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-3f0d7ec9-e61e-4dd3-a66c-1fdd8d0d3bce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3904402162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3904402162 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2043819212 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1489590000 ps |
| CPU time | 4.61 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 12:53:25 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-0b432bed-d8de-4f2c-8b51-fb42e92e9b59 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2043819212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2043819212 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3356652863 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1494890000 ps |
| CPU time | 4.13 seconds |
| Started | May 09 12:52:42 PM PDT 24 |
| Finished | May 09 12:52:53 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-e09f4d44-64b0-4928-bb84-4296c3a0011f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3356652863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3356652863 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2112030238 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1427590000 ps |
| CPU time | 4.9 seconds |
| Started | May 09 12:53:12 PM PDT 24 |
| Finished | May 09 12:53:26 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-76e0e73b-3e62-450b-8bd7-f79bda9f93b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2112030238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2112030238 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2529279166 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1603570000 ps |
| CPU time | 6.01 seconds |
| Started | May 09 12:53:14 PM PDT 24 |
| Finished | May 09 12:53:29 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-b2108fa4-c549-4ff2-a065-bf56d3e042f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2529279166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2529279166 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3753321542 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1343090000 ps |
| CPU time | 3.39 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 12:53:21 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-01081012-1c8b-4f79-b453-efdb770e9e51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3753321542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3753321542 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3560430405 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1417590000 ps |
| CPU time | 3.8 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 12:53:22 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-13ab0c8b-058d-4c33-a904-2839ad89b7a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3560430405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3560430405 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.72373643 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1500370000 ps |
| CPU time | 4.33 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 12:53:22 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-abe27e3e-b197-4649-a0c3-68d9a7102de0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=72373643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.72373643 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3948791876 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1330910000 ps |
| CPU time | 3.72 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 12:53:21 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-da982a42-217e-42f0-ab71-8383ddcc435f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3948791876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3948791876 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3519984378 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1420790000 ps |
| CPU time | 4.6 seconds |
| Started | May 09 12:53:13 PM PDT 24 |
| Finished | May 09 12:53:26 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-80d53c7e-3618-4f63-83b3-3b8cbe557f2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3519984378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3519984378 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2926003487 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1071170000 ps |
| CPU time | 3.65 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 12:53:21 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-d9cd0cc6-258b-42a7-8440-67b06e38322f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2926003487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2926003487 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3057400929 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1549190000 ps |
| CPU time | 6.01 seconds |
| Started | May 09 12:53:10 PM PDT 24 |
| Finished | May 09 12:53:25 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-0073710d-0895-4742-b5aa-e9deb904ae2d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3057400929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3057400929 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1798421948 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1444890000 ps |
| CPU time | 3.68 seconds |
| Started | May 09 12:53:11 PM PDT 24 |
| Finished | May 09 12:53:20 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-6f437bf2-900e-4eff-af19-ca8d94d6859b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1798421948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1798421948 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2427795017 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1451970000 ps |
| CPU time | 3.61 seconds |
| Started | May 09 12:52:44 PM PDT 24 |
| Finished | May 09 12:52:55 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-e5fd4be0-9531-4958-a5e5-fd3b5895b5e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2427795017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2427795017 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2956793989 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1177410000 ps |
| CPU time | 3.01 seconds |
| Started | May 09 12:52:42 PM PDT 24 |
| Finished | May 09 12:52:51 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-657103cc-46fc-4a95-b022-30f7f6e658ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2956793989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2956793989 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.852569513 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1479830000 ps |
| CPU time | 4.3 seconds |
| Started | May 09 12:52:45 PM PDT 24 |
| Finished | May 09 12:52:57 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-3cf98d2d-f534-4424-8dd6-5aefdc197115 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=852569513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.852569513 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.331103451 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1402130000 ps |
| CPU time | 2.9 seconds |
| Started | May 09 12:52:44 PM PDT 24 |
| Finished | May 09 12:52:52 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-d9dae764-122f-4cb7-a0c9-f7cf7796db51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=331103451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.331103451 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3418737873 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1077710000 ps |
| CPU time | 2.71 seconds |
| Started | May 09 12:52:44 PM PDT 24 |
| Finished | May 09 12:52:52 PM PDT 24 |
| Peak memory | 165072 kb |
| Host | smart-db1aa819-6f56-4070-b771-e7e95afbab7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3418737873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3418737873 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3552092151 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1472710000 ps |
| CPU time | 5.18 seconds |
| Started | May 09 12:26:22 PM PDT 24 |
| Finished | May 09 12:26:34 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-7fb5589e-aeec-4087-9b2e-dcdce8bf7636 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3552092151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3552092151 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1807911071 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1595170000 ps |
| CPU time | 5.67 seconds |
| Started | May 09 12:26:58 PM PDT 24 |
| Finished | May 09 12:27:11 PM PDT 24 |
| Peak memory | 165072 kb |
| Host | smart-f3857204-bb6e-4f3d-ad59-d9303e6acbee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1807911071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1807911071 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3320999558 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1390710000 ps |
| CPU time | 3.22 seconds |
| Started | May 09 12:29:45 PM PDT 24 |
| Finished | May 09 12:29:56 PM PDT 24 |
| Peak memory | 164716 kb |
| Host | smart-5a152b3d-c729-419d-a1b2-5e5c696d6ac3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3320999558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3320999558 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3416661851 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1327350000 ps |
| CPU time | 3.29 seconds |
| Started | May 09 12:29:54 PM PDT 24 |
| Finished | May 09 12:30:04 PM PDT 24 |
| Peak memory | 164280 kb |
| Host | smart-8117ca59-a648-4593-85bf-18d692e9e201 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3416661851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3416661851 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1879896132 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1505990000 ps |
| CPU time | 4.64 seconds |
| Started | May 09 12:31:52 PM PDT 24 |
| Finished | May 09 12:32:11 PM PDT 24 |
| Peak memory | 162780 kb |
| Host | smart-b58f9e01-25f1-472e-a164-45fe5dfd3c36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1879896132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1879896132 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2269432413 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1383370000 ps |
| CPU time | 3.37 seconds |
| Started | May 09 12:28:50 PM PDT 24 |
| Finished | May 09 12:28:59 PM PDT 24 |
| Peak memory | 164436 kb |
| Host | smart-eee1cc4b-170a-4435-9640-beead72eae11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2269432413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2269432413 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3305928441 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1535290000 ps |
| CPU time | 5.33 seconds |
| Started | May 09 12:28:04 PM PDT 24 |
| Finished | May 09 12:28:17 PM PDT 24 |
| Peak memory | 164688 kb |
| Host | smart-da9f27b5-66d8-4702-aed2-d88715b89422 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3305928441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3305928441 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4448124 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1596730000 ps |
| CPU time | 4.67 seconds |
| Started | May 09 12:27:45 PM PDT 24 |
| Finished | May 09 12:27:57 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-b372b2e7-abf4-47fd-9e93-cdd94e60ccb0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4448124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.4448124 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.12983056 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1514910000 ps |
| CPU time | 4.54 seconds |
| Started | May 09 12:27:23 PM PDT 24 |
| Finished | May 09 12:27:33 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-ccaaa76f-746d-439e-baf4-57c105062bd8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=12983056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.12983056 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2172160544 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1590910000 ps |
| CPU time | 3.95 seconds |
| Started | May 09 12:28:36 PM PDT 24 |
| Finished | May 09 12:28:47 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-c1e97519-a432-44d4-a019-78f10f7db179 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2172160544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2172160544 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1089866480 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1387310000 ps |
| CPU time | 3.54 seconds |
| Started | May 09 12:28:08 PM PDT 24 |
| Finished | May 09 12:28:17 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-4d49330e-3936-4689-adf1-a4ff1fba76ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1089866480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1089866480 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3660923285 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1458790000 ps |
| CPU time | 4.68 seconds |
| Started | May 09 12:26:14 PM PDT 24 |
| Finished | May 09 12:26:25 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-67ac8099-0fa9-4618-bf17-8e9a38d0ee48 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3660923285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3660923285 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1367762064 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1356110000 ps |
| CPU time | 4.45 seconds |
| Started | May 09 12:26:42 PM PDT 24 |
| Finished | May 09 12:26:52 PM PDT 24 |
| Peak memory | 165076 kb |
| Host | smart-72feb8bf-9779-4d11-a710-03f53baa3d6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1367762064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1367762064 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2348351075 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1404710000 ps |
| CPU time | 4.06 seconds |
| Started | May 09 12:28:57 PM PDT 24 |
| Finished | May 09 12:29:09 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-cfa93ab1-b96d-46f4-9c6d-5abb570baffc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2348351075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2348351075 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.444411594 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1570850000 ps |
| CPU time | 4.15 seconds |
| Started | May 09 12:27:56 PM PDT 24 |
| Finished | May 09 12:28:06 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-52ef9661-dc49-40ed-8264-a097da847b9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=444411594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.444411594 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2376923628 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1499950000 ps |
| CPU time | 4.68 seconds |
| Started | May 09 12:31:52 PM PDT 24 |
| Finished | May 09 12:32:11 PM PDT 24 |
| Peak memory | 162072 kb |
| Host | smart-19a9ad58-2b07-47e2-b3b7-49d507669e7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2376923628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2376923628 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3694891400 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1581590000 ps |
| CPU time | 4.28 seconds |
| Started | May 09 12:28:58 PM PDT 24 |
| Finished | May 09 12:29:10 PM PDT 24 |
| Peak memory | 164328 kb |
| Host | smart-7b0eb6f4-96f7-4bf1-b576-c8961d2da34e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3694891400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3694891400 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4243577776 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1435610000 ps |
| CPU time | 4.11 seconds |
| Started | May 09 12:25:32 PM PDT 24 |
| Finished | May 09 12:25:43 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-a3618bf6-10a5-4590-b822-281afbb7977a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4243577776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4243577776 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2718873834 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1444190000 ps |
| CPU time | 3.57 seconds |
| Started | May 09 12:29:53 PM PDT 24 |
| Finished | May 09 12:30:04 PM PDT 24 |
| Peak memory | 162968 kb |
| Host | smart-6547045a-4b61-4f6c-99c6-15354a2e586b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2718873834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2718873834 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3953532555 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1550950000 ps |
| CPU time | 4.57 seconds |
| Started | May 09 12:31:53 PM PDT 24 |
| Finished | May 09 12:32:11 PM PDT 24 |
| Peak memory | 164044 kb |
| Host | smart-9cebb7db-2579-43ff-95db-9d50c7c2597d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3953532555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3953532555 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.972360118 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1472770000 ps |
| CPU time | 4.59 seconds |
| Started | May 09 12:31:52 PM PDT 24 |
| Finished | May 09 12:32:10 PM PDT 24 |
| Peak memory | 162684 kb |
| Host | smart-338c4b5d-7848-470a-ac28-741474003ff3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=972360118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.972360118 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4199961939 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1497090000 ps |
| CPU time | 3.6 seconds |
| Started | May 09 12:30:29 PM PDT 24 |
| Finished | May 09 12:30:41 PM PDT 24 |
| Peak memory | 164684 kb |
| Host | smart-f07ab773-edef-4bcf-9908-0498a8a13a49 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4199961939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.4199961939 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.41379705 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1456450000 ps |
| CPU time | 4.63 seconds |
| Started | May 09 12:25:53 PM PDT 24 |
| Finished | May 09 12:26:04 PM PDT 24 |
| Peak memory | 164444 kb |
| Host | smart-5f3ea8a8-8e33-4332-a7f1-778b2365363b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=41379705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.41379705 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1018072721 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1494590000 ps |
| CPU time | 3.12 seconds |
| Started | May 09 12:31:30 PM PDT 24 |
| Finished | May 09 12:31:45 PM PDT 24 |
| Peak memory | 162656 kb |
| Host | smart-67f3db8e-5066-4c46-83de-719506cc0087 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1018072721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1018072721 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2741463026 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1569810000 ps |
| CPU time | 4.25 seconds |
| Started | May 09 12:28:57 PM PDT 24 |
| Finished | May 09 12:29:10 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-e0414395-cb5e-4487-8ebe-d60f752f8399 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2741463026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2741463026 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2056061624 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1429190000 ps |
| CPU time | 2.97 seconds |
| Started | May 09 12:28:53 PM PDT 24 |
| Finished | May 09 12:29:02 PM PDT 24 |
| Peak memory | 164388 kb |
| Host | smart-8abb5457-2b40-4356-ad90-aee5cac9c542 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2056061624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2056061624 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1900445730 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1419310000 ps |
| CPU time | 4.27 seconds |
| Started | May 09 12:27:57 PM PDT 24 |
| Finished | May 09 12:28:07 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-c58ce00c-9c55-49a9-8a69-768f40804f2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1900445730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1900445730 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1178913224 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1283750000 ps |
| CPU time | 2.68 seconds |
| Started | May 09 12:30:16 PM PDT 24 |
| Finished | May 09 12:30:26 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-f6610c7e-3e26-4473-91b1-6dd85aabce41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1178913224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1178913224 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4176321478 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1465350000 ps |
| CPU time | 3.8 seconds |
| Started | May 09 12:29:47 PM PDT 24 |
| Finished | May 09 12:29:58 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-f34e1aac-1e47-4b96-895c-cdf3e6b096f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4176321478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.4176321478 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1570094818 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1333050000 ps |
| CPU time | 3.7 seconds |
| Started | May 09 12:27:24 PM PDT 24 |
| Finished | May 09 12:27:33 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-4aa94cc4-af96-4943-85d6-0237765d4c08 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1570094818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1570094818 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3908138001 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1382790000 ps |
| CPU time | 4.29 seconds |
| Started | May 09 12:27:46 PM PDT 24 |
| Finished | May 09 12:27:56 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-903d3623-330f-4d03-b06a-8e00007fa85a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3908138001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3908138001 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.217037932 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1429590000 ps |
| CPU time | 4.79 seconds |
| Started | May 09 12:28:18 PM PDT 24 |
| Finished | May 09 12:28:30 PM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-eccc6d55-0286-4839-868d-45ba854ee97a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=217037932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.217037932 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3312940640 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1251590000 ps |
| CPU time | 3.02 seconds |
| Started | May 09 12:28:26 PM PDT 24 |
| Finished | May 09 12:28:33 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-a7f4925a-72d1-436d-9f89-01742982438c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3312940640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3312940640 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1104863406 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1539090000 ps |
| CPU time | 4.79 seconds |
| Started | May 09 12:25:13 PM PDT 24 |
| Finished | May 09 12:25:25 PM PDT 24 |
| Peak memory | 164532 kb |
| Host | smart-02a425b6-e304-47c8-9e56-a1dbf29336e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1104863406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1104863406 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1764159308 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1473410000 ps |
| CPU time | 3.27 seconds |
| Started | May 09 12:30:32 PM PDT 24 |
| Finished | May 09 12:30:44 PM PDT 24 |
| Peak memory | 164632 kb |
| Host | smart-b4b00f6a-4b0e-4192-a7a0-36309aa0074d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1764159308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1764159308 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2578700778 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1412510000 ps |
| CPU time | 3.85 seconds |
| Started | May 09 12:28:18 PM PDT 24 |
| Finished | May 09 12:28:28 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-2699bcbb-f536-4f9d-9e29-290c03a81958 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2578700778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2578700778 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3758115328 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1488390000 ps |
| CPU time | 5.09 seconds |
| Started | May 09 12:27:24 PM PDT 24 |
| Finished | May 09 12:27:36 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-50db5af2-e162-41da-9c3f-efc873dd22be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3758115328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3758115328 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.841929839 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1451930000 ps |
| CPU time | 4.37 seconds |
| Started | May 09 12:31:53 PM PDT 24 |
| Finished | May 09 12:32:11 PM PDT 24 |
| Peak memory | 163980 kb |
| Host | smart-7d1979e5-cccc-49dc-9b1f-a73de496a334 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=841929839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.841929839 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2549362597 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1585590000 ps |
| CPU time | 4.58 seconds |
| Started | May 09 12:28:57 PM PDT 24 |
| Finished | May 09 12:29:10 PM PDT 24 |
| Peak memory | 162968 kb |
| Host | smart-374bc7c1-de55-4a2e-9e95-611be5a3b59e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2549362597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2549362597 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4287520656 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1454410000 ps |
| CPU time | 4.3 seconds |
| Started | May 09 12:31:52 PM PDT 24 |
| Finished | May 09 12:32:10 PM PDT 24 |
| Peak memory | 164044 kb |
| Host | smart-a8f45408-c53b-4606-98e4-f173b20dd1a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4287520656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4287520656 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3262550725 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1478290000 ps |
| CPU time | 3.51 seconds |
| Started | May 09 12:31:34 PM PDT 24 |
| Finished | May 09 12:31:53 PM PDT 24 |
| Peak memory | 164412 kb |
| Host | smart-b258f9df-e11c-4ad0-80f4-43654eaea9f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3262550725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3262550725 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2801459 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1347490000 ps |
| CPU time | 4.39 seconds |
| Started | May 09 12:31:52 PM PDT 24 |
| Finished | May 09 12:32:10 PM PDT 24 |
| Peak memory | 161912 kb |
| Host | smart-efa8b2b5-c641-4679-8a3d-0c94f84a5c13 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2801459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2801459 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3581610904 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1460870000 ps |
| CPU time | 4.1 seconds |
| Started | May 09 12:28:28 PM PDT 24 |
| Finished | May 09 12:28:39 PM PDT 24 |
| Peak memory | 164688 kb |
| Host | smart-69c592e9-8949-4659-b1b0-e4100104ca6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3581610904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3581610904 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2248494956 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1400530000 ps |
| CPU time | 3.94 seconds |
| Started | May 09 12:28:58 PM PDT 24 |
| Finished | May 09 12:29:10 PM PDT 24 |
| Peak memory | 164328 kb |
| Host | smart-c57d960e-09ee-4b45-a5a6-469f4835d006 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2248494956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2248494956 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3330210769 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1531230000 ps |
| CPU time | 4.47 seconds |
| Started | May 09 12:26:16 PM PDT 24 |
| Finished | May 09 12:26:27 PM PDT 24 |
| Peak memory | 164704 kb |
| Host | smart-304311b9-f015-4577-a611-1c94cf878b7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3330210769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3330210769 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3285649331 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1387870000 ps |
| CPU time | 4.93 seconds |
| Started | May 09 12:27:54 PM PDT 24 |
| Finished | May 09 12:28:06 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-190201e6-1200-4f2c-971e-30199a0d7181 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3285649331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3285649331 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.783405242 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1551370000 ps |
| CPU time | 5.69 seconds |
| Started | May 09 12:29:45 PM PDT 24 |
| Finished | May 09 12:30:00 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-a50aa45d-dc69-45f1-b0f8-b55cc5ba9238 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=783405242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.783405242 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.349038547 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1470970000 ps |
| CPU time | 4 seconds |
| Started | May 09 12:28:57 PM PDT 24 |
| Finished | May 09 12:29:09 PM PDT 24 |
| Peak memory | 163416 kb |
| Host | smart-51c61e60-7047-471f-9d72-e6c347a254fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=349038547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.349038547 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1761982535 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1498090000 ps |
| CPU time | 4.33 seconds |
| Started | May 09 12:25:31 PM PDT 24 |
| Finished | May 09 12:25:41 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-c9bfcc08-d8c2-4573-ad11-3458a9d780c0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1761982535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1761982535 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |