| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2943705759 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.95136469 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2970144896 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1064759483 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3770418039 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.204298048 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2219716411 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.776526377 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.509561822 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4291940203 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2558025397 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3250231628 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1489117174 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3611093867 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3034442548 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1968400327 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2903204561 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1208550154 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1696317110 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2102245708 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.663779633 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.863000405 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2379275227 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3944961394 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.967600391 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3376469911 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.810818131 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3232836401 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3199513938 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3546443389 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1376105750 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3595581197 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1794646959 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3924508683 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2029838299 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.963102832 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.441096545 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1196495403 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2478646114 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1441102901 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3151867909 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2639503905 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.493096399 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.114242798 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3888848384 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.782584540 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.260171460 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2778678532 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2767605179 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.360122646 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4085254546 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1254703055 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2222800048 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4249057459 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2841857502 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1219689195 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.526243066 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3937407501 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1771019837 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4237573197 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.605120698 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.710569948 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.393464480 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.770948376 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1031543000 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2177050716 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3311154452 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3637732348 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1944023821 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3319785028 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3601779275 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1711654931 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3747632156 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1076874 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.759962538 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1461644403 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3063618356 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3258557540 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.397328974 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3661702385 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4107097206 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.542914684 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1576104732 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2746914658 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3410145741 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.782020127 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4231300270 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.879890279 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1491922869 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.763068673 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3091838371 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1931175229 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3178981531 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.719757607 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.940076746 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1547798990 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.981649266 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3090278485 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2903095410 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3669029814 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2519196386 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2671296082 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3356130643 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2980773964 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.37700768 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2881250475 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.17043861 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1679955017 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3867844006 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3898792868 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2948233723 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.125197707 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.422798870 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1840209653 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2614851046 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3878388764 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3460982346 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3422433081 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1333135439 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2653788513 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2385815284 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1162067451 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1878380251 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2332561034 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2648408395 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2802188256 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.671067133 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1194973659 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1772871418 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3029546994 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.839350285 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3142957964 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2806447512 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3968993024 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2074021712 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3428094904 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2153347692 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1964935931 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1490847481 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1568134492 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1345293132 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2400223873 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1534874050 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.770184811 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.412386527 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3021114662 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2771088988 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2466787792 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3129960747 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1818787293 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.712307462 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.984133380 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.338274883 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4059297182 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2195891376 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2336445000 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.96150921 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.503496690 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1282941290 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.956587044 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1340605884 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1419756882 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.874655668 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3735410662 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.131547739 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3504698201 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2576918716 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2820368503 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2382552976 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3600444786 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3557352859 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1694540859 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3638303421 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1178089666 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2152649222 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1715175006 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.315414081 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2648949760 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.463326112 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3895922332 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2232154111 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1764091849 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2332108116 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.149773662 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1680639179 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.263505086 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.35404776 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.215393759 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.134819552 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2367103722 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2551169789 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2853928431 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1475542030 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.502484085 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2780729897 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1140221750 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2944889844 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.716779763 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1539829516 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3084177586 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1178089666 | May 12 01:53:06 PM PDT 24 | May 12 01:53:16 PM PDT 24 | 1250190000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2232154111 | May 12 01:53:56 PM PDT 24 | May 12 01:54:08 PM PDT 24 | 1323750000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.134819552 | May 12 01:53:59 PM PDT 24 | May 12 01:54:10 PM PDT 24 | 1576970000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.149773662 | May 12 01:53:56 PM PDT 24 | May 12 01:54:07 PM PDT 24 | 1493410000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2943705759 | May 12 01:53:05 PM PDT 24 | May 12 01:53:16 PM PDT 24 | 1380850000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2332108116 | May 12 01:53:56 PM PDT 24 | May 12 01:54:05 PM PDT 24 | 1465990000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.502484085 | May 12 01:54:06 PM PDT 24 | May 12 01:54:14 PM PDT 24 | 1531990000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2195891376 | May 12 01:53:19 PM PDT 24 | May 12 01:53:33 PM PDT 24 | 1527810000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1715175006 | May 12 01:53:53 PM PDT 24 | May 12 01:54:02 PM PDT 24 | 1401690000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2367103722 | May 12 01:54:03 PM PDT 24 | May 12 01:54:11 PM PDT 24 | 1440810000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3557352859 | May 12 01:53:49 PM PDT 24 | May 12 01:53:59 PM PDT 24 | 1513290000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.503496690 | May 12 01:53:29 PM PDT 24 | May 12 01:53:41 PM PDT 24 | 1284590000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2944889844 | May 12 01:53:10 PM PDT 24 | May 12 01:53:20 PM PDT 24 | 1278210000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2780729897 | May 12 01:54:08 PM PDT 24 | May 12 01:54:20 PM PDT 24 | 1494430000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.315414081 | May 12 01:53:53 PM PDT 24 | May 12 01:54:04 PM PDT 24 | 1435970000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.96150921 | May 12 01:53:24 PM PDT 24 | May 12 01:53:32 PM PDT 24 | 1443070000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3638303421 | May 12 01:53:53 PM PDT 24 | May 12 01:54:05 PM PDT 24 | 1543130000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.215393759 | May 12 01:53:59 PM PDT 24 | May 12 01:54:08 PM PDT 24 | 1451690000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2382552976 | May 12 01:53:45 PM PDT 24 | May 12 01:53:53 PM PDT 24 | 1523010000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2648949760 | May 12 01:53:52 PM PDT 24 | May 12 01:54:00 PM PDT 24 | 1511670000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1140221750 | May 12 01:53:10 PM PDT 24 | May 12 01:53:21 PM PDT 24 | 1461390000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3600444786 | May 12 01:53:49 PM PDT 24 | May 12 01:54:02 PM PDT 24 | 1518070000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3504698201 | May 12 01:53:44 PM PDT 24 | May 12 01:53:58 PM PDT 24 | 1562530000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.35404776 | May 12 01:54:00 PM PDT 24 | May 12 01:54:12 PM PDT 24 | 1448970000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.956587044 | May 12 01:53:32 PM PDT 24 | May 12 01:53:46 PM PDT 24 | 1436530000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1340605884 | May 12 01:53:34 PM PDT 24 | May 12 01:53:42 PM PDT 24 | 1523890000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3735410662 | May 12 01:53:43 PM PDT 24 | May 12 01:53:56 PM PDT 24 | 1475410000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1694540859 | May 12 01:53:52 PM PDT 24 | May 12 01:54:06 PM PDT 24 | 1595110000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1680639179 | May 12 01:53:08 PM PDT 24 | May 12 01:53:16 PM PDT 24 | 1564970000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.263505086 | May 12 01:54:00 PM PDT 24 | May 12 01:54:09 PM PDT 24 | 1450950000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2576918716 | May 12 01:53:45 PM PDT 24 | May 12 01:53:56 PM PDT 24 | 1251290000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.984133380 | May 12 01:53:05 PM PDT 24 | May 12 01:53:17 PM PDT 24 | 1302730000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.463326112 | May 12 01:53:54 PM PDT 24 | May 12 01:54:07 PM PDT 24 | 1416470000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1419756882 | May 12 01:53:40 PM PDT 24 | May 12 01:53:49 PM PDT 24 | 1364510000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1764091849 | May 12 01:53:57 PM PDT 24 | May 12 01:54:10 PM PDT 24 | 1495170000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1475542030 | May 12 01:54:03 PM PDT 24 | May 12 01:54:11 PM PDT 24 | 1484470000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.874655668 | May 12 01:53:03 PM PDT 24 | May 12 01:53:11 PM PDT 24 | 1358310000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3084177586 | May 12 01:53:14 PM PDT 24 | May 12 01:53:27 PM PDT 24 | 1568050000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2152649222 | May 12 01:53:52 PM PDT 24 | May 12 01:54:00 PM PDT 24 | 1500990000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2820368503 | May 12 01:53:48 PM PDT 24 | May 12 01:53:58 PM PDT 24 | 1299930000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4059297182 | May 12 01:53:17 PM PDT 24 | May 12 01:53:26 PM PDT 24 | 1528850000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.716779763 | May 12 01:53:10 PM PDT 24 | May 12 01:53:21 PM PDT 24 | 1488390000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1539829516 | May 12 01:53:10 PM PDT 24 | May 12 01:53:23 PM PDT 24 | 1547930000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3895922332 | May 12 01:53:54 PM PDT 24 | May 12 01:54:05 PM PDT 24 | 1342370000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2336445000 | May 12 01:53:21 PM PDT 24 | May 12 01:53:30 PM PDT 24 | 1463830000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1282941290 | May 12 01:53:30 PM PDT 24 | May 12 01:53:39 PM PDT 24 | 1416010000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2853928431 | May 12 01:54:04 PM PDT 24 | May 12 01:54:18 PM PDT 24 | 1559990000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.338274883 | May 12 01:53:13 PM PDT 24 | May 12 01:53:23 PM PDT 24 | 1400190000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.131547739 | May 12 01:53:42 PM PDT 24 | May 12 01:53:53 PM PDT 24 | 1448710000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2551169789 | May 12 01:54:04 PM PDT 24 | May 12 01:54:16 PM PDT 24 | 1220770000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3867844006 | May 12 01:46:13 PM PDT 24 | May 12 01:46:23 PM PDT 24 | 1568490000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1490847481 | May 12 01:46:18 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1272750000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3142957964 | May 12 01:46:18 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1371030000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2074021712 | May 12 01:46:17 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1573130000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2400223873 | May 12 01:46:23 PM PDT 24 | May 12 01:46:38 PM PDT 24 | 1524610000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3021114662 | May 12 01:46:08 PM PDT 24 | May 12 01:46:18 PM PDT 24 | 1555530000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.412386527 | May 12 01:46:18 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1454410000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1064759483 | May 12 01:46:15 PM PDT 24 | May 12 01:46:30 PM PDT 24 | 1472190000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3968993024 | May 12 01:46:17 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1508930000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1772871418 | May 12 01:46:16 PM PDT 24 | May 12 01:46:25 PM PDT 24 | 1297650000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2614851046 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1589890000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.37700768 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1453770000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2653788513 | May 12 01:46:17 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1204490000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3460982346 | May 12 01:46:12 PM PDT 24 | May 12 01:46:21 PM PDT 24 | 1454550000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1679955017 | May 12 01:46:15 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1541250000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3898792868 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1226190000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.770184811 | May 12 01:46:20 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1109790000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.125197707 | May 12 01:46:14 PM PDT 24 | May 12 01:46:24 PM PDT 24 | 1417350000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2648408395 | May 12 01:46:15 PM PDT 24 | May 12 01:46:25 PM PDT 24 | 1560250000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3878388764 | May 12 01:46:15 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1486010000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2802188256 | May 12 01:46:16 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1406830000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.422798870 | May 12 01:46:17 PM PDT 24 | May 12 01:46:31 PM PDT 24 | 1571350000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.839350285 | May 12 01:46:18 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1426210000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3428094904 | May 12 01:46:14 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1573930000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1878380251 | May 12 01:46:14 PM PDT 24 | May 12 01:46:24 PM PDT 24 | 1286790000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1568134492 | May 12 01:46:18 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1350690000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1534874050 | May 12 01:46:20 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1367330000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2806447512 | May 12 01:46:17 PM PDT 24 | May 12 01:46:28 PM PDT 24 | 1505870000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.712307462 | May 12 01:46:14 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1505290000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1194973659 | May 12 01:46:01 PM PDT 24 | May 12 01:46:08 PM PDT 24 | 1464030000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2881250475 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1437790000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1162067451 | May 12 01:46:16 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1527090000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2466787792 | May 12 01:46:12 PM PDT 24 | May 12 01:46:20 PM PDT 24 | 1467330000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1345293132 | May 12 01:46:17 PM PDT 24 | May 12 01:46:24 PM PDT 24 | 1412390000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3356130643 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1441710000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2153347692 | May 12 01:46:15 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1548510000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1840209653 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1471230000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2771088988 | May 12 01:46:12 PM PDT 24 | May 12 01:46:21 PM PDT 24 | 1288430000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2332561034 | May 12 01:46:15 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1514410000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2948233723 | May 12 01:46:18 PM PDT 24 | May 12 01:46:31 PM PDT 24 | 1531210000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3129960747 | May 12 01:46:11 PM PDT 24 | May 12 01:46:22 PM PDT 24 | 1564530000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1964935931 | May 12 01:46:16 PM PDT 24 | May 12 01:46:29 PM PDT 24 | 1616090000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1333135439 | May 12 01:46:15 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1427270000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1818787293 | May 12 01:46:14 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1637270000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.671067133 | May 12 01:46:16 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1338690000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2385815284 | May 12 01:45:59 PM PDT 24 | May 12 01:46:09 PM PDT 24 | 1450970000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.17043861 | May 12 01:46:16 PM PDT 24 | May 12 01:46:26 PM PDT 24 | 1489230000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3422433081 | May 12 01:46:15 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1431590000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3029546994 | May 12 01:46:17 PM PDT 24 | May 12 01:46:27 PM PDT 24 | 1515910000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2980773964 | May 12 01:46:13 PM PDT 24 | May 12 01:46:21 PM PDT 24 | 1439830000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.509561822 | May 12 01:52:27 PM PDT 24 | May 12 02:30:48 PM PDT 24 | 336923370000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1441102901 | May 12 01:52:52 PM PDT 24 | May 12 02:26:13 PM PDT 24 | 336593650000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1696317110 | May 12 01:52:38 PM PDT 24 | May 12 02:26:32 PM PDT 24 | 336811970000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.967600391 | May 12 01:52:44 PM PDT 24 | May 12 02:31:40 PM PDT 24 | 336908010000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3250231628 | May 12 01:52:34 PM PDT 24 | May 12 02:22:14 PM PDT 24 | 337085430000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1968400327 | May 12 01:52:20 PM PDT 24 | May 12 02:26:39 PM PDT 24 | 336622430000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.95136469 | May 12 01:52:28 PM PDT 24 | May 12 02:22:18 PM PDT 24 | 336454030000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2379275227 | May 12 01:52:41 PM PDT 24 | May 12 02:23:05 PM PDT 24 | 336750930000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3888848384 | May 12 01:53:00 PM PDT 24 | May 12 02:25:48 PM PDT 24 | 336545050000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.782584540 | May 12 01:52:59 PM PDT 24 | May 12 02:27:41 PM PDT 24 | 336676350000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2558025397 | May 12 01:52:30 PM PDT 24 | May 12 02:23:46 PM PDT 24 | 336620270000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2778678532 | May 12 01:53:13 PM PDT 24 | May 12 02:30:55 PM PDT 24 | 336945490000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1196495403 | May 12 01:52:21 PM PDT 24 | May 12 02:28:54 PM PDT 24 | 336916690000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.360122646 | May 12 01:52:22 PM PDT 24 | May 12 02:28:50 PM PDT 24 | 336775050000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3034442548 | May 12 01:52:37 PM PDT 24 | May 12 02:25:20 PM PDT 24 | 336940050000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3546443389 | May 12 01:52:45 PM PDT 24 | May 12 02:32:39 PM PDT 24 | 336543370000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1376105750 | May 12 01:52:48 PM PDT 24 | May 12 02:30:35 PM PDT 24 | 336484350000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1254703055 | May 12 01:52:24 PM PDT 24 | May 12 02:23:36 PM PDT 24 | 336337370000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.260171460 | May 12 01:53:04 PM PDT 24 | May 12 02:23:15 PM PDT 24 | 336818110000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1794646959 | May 12 01:52:48 PM PDT 24 | May 12 02:30:41 PM PDT 24 | 336951050000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3232836401 | May 12 01:52:42 PM PDT 24 | May 12 02:21:00 PM PDT 24 | 336302990000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2767605179 | May 12 01:52:22 PM PDT 24 | May 12 02:26:55 PM PDT 24 | 336932170000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2222800048 | May 12 01:52:25 PM PDT 24 | May 12 02:32:51 PM PDT 24 | 337016150000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4291940203 | May 12 01:52:29 PM PDT 24 | May 12 02:25:00 PM PDT 24 | 336477290000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3944961394 | May 12 01:52:41 PM PDT 24 | May 12 02:24:13 PM PDT 24 | 336835770000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1208550154 | May 12 01:52:39 PM PDT 24 | May 12 02:25:09 PM PDT 24 | 336444910000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3151867909 | May 12 01:52:51 PM PDT 24 | May 12 02:27:04 PM PDT 24 | 337022370000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3611093867 | May 12 01:52:36 PM PDT 24 | May 12 02:25:09 PM PDT 24 | 336890170000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3595581197 | May 12 01:52:45 PM PDT 24 | May 12 02:27:29 PM PDT 24 | 336861210000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.114242798 | May 12 01:52:55 PM PDT 24 | May 12 02:28:59 PM PDT 24 | 336367490000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.441096545 | May 12 01:52:48 PM PDT 24 | May 12 02:26:27 PM PDT 24 | 336407730000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2639503905 | May 12 01:52:52 PM PDT 24 | May 12 02:27:23 PM PDT 24 | 336942930000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.663779633 | May 12 01:52:38 PM PDT 24 | May 12 02:25:36 PM PDT 24 | 336934450000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.493096399 | May 12 01:52:55 PM PDT 24 | May 12 02:25:22 PM PDT 24 | 336518450000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2478646114 | May 12 01:52:52 PM PDT 24 | May 12 02:35:34 PM PDT 24 | 337005910000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2029838299 | May 12 01:52:47 PM PDT 24 | May 12 02:27:22 PM PDT 24 | 336539370000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.776526377 | May 12 01:52:27 PM PDT 24 | May 12 02:29:39 PM PDT 24 | 336614050000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3770418039 | May 12 01:52:16 PM PDT 24 | May 12 02:24:18 PM PDT 24 | 336805030000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.204298048 | May 12 01:52:17 PM PDT 24 | May 12 02:23:26 PM PDT 24 | 336802350000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4085254546 | May 12 01:52:24 PM PDT 24 | May 12 02:29:33 PM PDT 24 | 337026030000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2219716411 | May 12 01:52:24 PM PDT 24 | May 12 02:23:29 PM PDT 24 | 336969590000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.863000405 | May 12 01:52:44 PM PDT 24 | May 12 02:31:38 PM PDT 24 | 336732670000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.963102832 | May 12 01:52:47 PM PDT 24 | May 12 02:24:18 PM PDT 24 | 336836850000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3199513938 | May 12 01:52:42 PM PDT 24 | May 12 02:24:54 PM PDT 24 | 336687650000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2903204561 | May 12 01:52:38 PM PDT 24 | May 12 02:25:36 PM PDT 24 | 336472930000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3376469911 | May 12 01:52:41 PM PDT 24 | May 12 02:26:42 PM PDT 24 | 337025030000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2102245708 | May 12 01:52:38 PM PDT 24 | May 12 02:24:05 PM PDT 24 | 336748890000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.810818131 | May 12 01:52:22 PM PDT 24 | May 12 02:28:23 PM PDT 24 | 336721830000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1489117174 | May 12 01:52:34 PM PDT 24 | May 12 02:27:59 PM PDT 24 | 336692110000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3924508683 | May 12 01:52:49 PM PDT 24 | May 12 02:30:36 PM PDT 24 | 336879750000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.879890279 | May 12 01:54:41 PM PDT 24 | May 12 02:25:32 PM PDT 24 | 336582570000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3311154452 | May 12 01:54:27 PM PDT 24 | May 12 02:33:45 PM PDT 24 | 336975850000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3410145741 | May 12 01:54:38 PM PDT 24 | May 12 02:25:41 PM PDT 24 | 336492590000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1031543000 | May 12 01:54:15 PM PDT 24 | May 12 02:36:58 PM PDT 24 | 336562550000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.981649266 | May 12 01:54:42 PM PDT 24 | May 12 02:31:25 PM PDT 24 | 336918750000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3319785028 | May 12 01:54:30 PM PDT 24 | May 12 02:27:54 PM PDT 24 | 336793110000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.763068673 | May 12 01:54:38 PM PDT 24 | May 12 02:25:59 PM PDT 24 | 336340410000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.940076746 | May 12 01:54:42 PM PDT 24 | May 12 02:33:04 PM PDT 24 | 336701930000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1076874 | May 12 01:54:37 PM PDT 24 | May 12 02:27:40 PM PDT 24 | 336982730000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2970144896 | May 12 01:54:24 PM PDT 24 | May 12 02:31:53 PM PDT 24 | 336586630000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.605120698 | May 12 01:54:22 PM PDT 24 | May 12 02:31:47 PM PDT 24 | 336870750000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1711654931 | May 12 01:54:31 PM PDT 24 | May 12 02:24:02 PM PDT 24 | 336537110000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3747632156 | May 12 01:54:31 PM PDT 24 | May 12 02:28:25 PM PDT 24 | 336566030000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2841857502 | May 12 01:54:06 PM PDT 24 | May 12 02:26:13 PM PDT 24 | 336531930000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.719757607 | May 12 01:54:42 PM PDT 24 | May 12 02:27:35 PM PDT 24 | 336693850000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3637732348 | May 12 01:54:28 PM PDT 24 | May 12 02:37:03 PM PDT 24 | 336463490000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.393464480 | May 12 01:54:28 PM PDT 24 | May 12 02:30:17 PM PDT 24 | 336844410000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1576104732 | May 12 01:54:34 PM PDT 24 | May 12 02:20:06 PM PDT 24 | 336911770000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3669029814 | May 12 01:54:16 PM PDT 24 | May 12 02:25:09 PM PDT 24 | 336554630000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1491922869 | May 12 01:54:39 PM PDT 24 | May 12 02:31:20 PM PDT 24 | 336262630000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1461644403 | May 12 01:54:16 PM PDT 24 | May 12 02:27:39 PM PDT 24 | 336878850000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.397328974 | May 12 01:54:34 PM PDT 24 | May 12 02:31:42 PM PDT 24 | 336995810000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.526243066 | May 12 01:54:21 PM PDT 24 | May 12 02:28:40 PM PDT 24 | 336751250000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3178981531 | May 12 01:54:42 PM PDT 24 | May 12 02:28:44 PM PDT 24 | 336793630000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.770948376 | May 12 01:54:28 PM PDT 24 | May 12 02:26:02 PM PDT 24 | 336442130000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3063618356 | May 12 01:54:37 PM PDT 24 | May 12 02:32:38 PM PDT 24 | 336695550000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1931175229 | May 12 01:54:41 PM PDT 24 | May 12 02:25:45 PM PDT 24 | 336662930000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3937407501 | May 12 01:54:20 PM PDT 24 | May 12 02:28:52 PM PDT 24 | 336982510000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3091838371 | May 12 01:54:38 PM PDT 24 | May 12 02:32:19 PM PDT 24 | 336446290000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3090278485 | May 12 01:54:15 PM PDT 24 | May 12 02:33:27 PM PDT 24 | 336644250000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3601779275 | May 12 01:54:31 PM PDT 24 | May 12 02:28:43 PM PDT 24 | 336468510000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1547798990 | May 12 01:54:44 PM PDT 24 | May 12 02:24:56 PM PDT 24 | 336682270000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.710569948 | May 12 01:54:23 PM PDT 24 | May 12 02:28:34 PM PDT 24 | 336566210000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4237573197 | May 12 01:54:20 PM PDT 24 | May 12 02:25:35 PM PDT 24 | 336636130000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2177050716 | May 12 01:54:27 PM PDT 24 | May 12 02:25:33 PM PDT 24 | 336978530000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2903095410 | May 12 01:54:14 PM PDT 24 | May 12 02:29:04 PM PDT 24 | 337144850000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1219689195 | May 12 01:54:22 PM PDT 24 | May 12 02:27:03 PM PDT 24 | 336804210000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2746914658 | May 12 01:54:38 PM PDT 24 | May 12 02:27:18 PM PDT 24 | 336619430000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2519196386 | May 12 01:54:17 PM PDT 24 | May 12 02:25:45 PM PDT 24 | 336940950000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.542914684 | May 12 01:54:38 PM PDT 24 | May 12 02:27:07 PM PDT 24 | 336731990000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1771019837 | May 12 01:54:22 PM PDT 24 | May 12 02:32:06 PM PDT 24 | 336722190000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2671296082 | May 12 01:54:17 PM PDT 24 | May 12 02:25:22 PM PDT 24 | 336445450000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.782020127 | May 12 01:54:40 PM PDT 24 | May 12 02:37:18 PM PDT 24 | 336755750000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1944023821 | May 12 01:54:28 PM PDT 24 | May 12 02:26:06 PM PDT 24 | 336403190000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3258557540 | May 12 01:54:34 PM PDT 24 | May 12 02:24:33 PM PDT 24 | 336806750000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4249057459 | May 12 01:54:07 PM PDT 24 | May 12 02:28:09 PM PDT 24 | 336980150000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4231300270 | May 12 01:54:16 PM PDT 24 | May 12 02:27:51 PM PDT 24 | 336923330000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.759962538 | May 12 01:54:34 PM PDT 24 | May 12 02:27:32 PM PDT 24 | 336699970000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4107097206 | May 12 01:54:36 PM PDT 24 | May 12 02:24:56 PM PDT 24 | 336371790000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3661702385 | May 12 01:54:37 PM PDT 24 | May 12 02:24:36 PM PDT 24 | 336723210000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2943705759 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1380850000 ps |
| CPU time | 4.72 seconds |
| Started | May 12 01:53:05 PM PDT 24 |
| Finished | May 12 01:53:16 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-6f84a630-6f24-4473-a830-37cbf42eb2f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2943705759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2943705759 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.95136469 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336454030000 ps |
| CPU time | 726.64 seconds |
| Started | May 12 01:52:28 PM PDT 24 |
| Finished | May 12 02:22:18 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-cf4afbe1-1ba0-4726-aa3f-cbd4fb5158b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=95136469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.95136469 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2970144896 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336586630000 ps |
| CPU time | 910.23 seconds |
| Started | May 12 01:54:24 PM PDT 24 |
| Finished | May 12 02:31:53 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-647a58ab-8e8c-4aec-a948-1d761325fdea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2970144896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2970144896 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1064759483 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1472190000 ps |
| CPU time | 3.99 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:30 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-3a6425b9-422e-4eb2-8e2b-4038f77eff1e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1064759483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1064759483 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3770418039 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336805030000 ps |
| CPU time | 783.06 seconds |
| Started | May 12 01:52:16 PM PDT 24 |
| Finished | May 12 02:24:18 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-f0ce5a09-9401-4131-81f2-6e4ce6e75593 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3770418039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3770418039 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.204298048 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336802350000 ps |
| CPU time | 768.83 seconds |
| Started | May 12 01:52:17 PM PDT 24 |
| Finished | May 12 02:23:26 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-2a806a07-7258-4319-80d7-362657a46254 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=204298048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.204298048 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2219716411 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336969590000 ps |
| CPU time | 762.29 seconds |
| Started | May 12 01:52:24 PM PDT 24 |
| Finished | May 12 02:23:29 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-f146cfef-96e2-4b1d-b9cc-ea8351e73da6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2219716411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2219716411 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.776526377 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336614050000 ps |
| CPU time | 880.06 seconds |
| Started | May 12 01:52:27 PM PDT 24 |
| Finished | May 12 02:29:39 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-c36259d8-c287-4933-be80-23642e0a5ec9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=776526377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.776526377 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.509561822 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336923370000 ps |
| CPU time | 925.88 seconds |
| Started | May 12 01:52:27 PM PDT 24 |
| Finished | May 12 02:30:48 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-fe99fbea-eaa9-4f8f-9ff4-ec8c27e4f6c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=509561822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.509561822 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4291940203 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336477290000 ps |
| CPU time | 788.44 seconds |
| Started | May 12 01:52:29 PM PDT 24 |
| Finished | May 12 02:25:00 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-b8dd0df1-341e-4654-b739-a72a6f0164d2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4291940203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4291940203 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2558025397 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336620270000 ps |
| CPU time | 764.72 seconds |
| Started | May 12 01:52:30 PM PDT 24 |
| Finished | May 12 02:23:46 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-ebb497d1-0f17-4f50-967c-fac3dcd61f0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2558025397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2558025397 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3250231628 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 337085430000 ps |
| CPU time | 720.19 seconds |
| Started | May 12 01:52:34 PM PDT 24 |
| Finished | May 12 02:22:14 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-92ede42f-9d65-4a45-a241-282fa393ff61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3250231628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3250231628 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1489117174 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336692110000 ps |
| CPU time | 884.72 seconds |
| Started | May 12 01:52:34 PM PDT 24 |
| Finished | May 12 02:27:59 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-f1faff3b-2c97-4b72-a680-a07ab389ba74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1489117174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1489117174 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3611093867 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336890170000 ps |
| CPU time | 808.17 seconds |
| Started | May 12 01:52:36 PM PDT 24 |
| Finished | May 12 02:25:09 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-cd948bca-25d5-4e74-98e4-0a1b7ae8d582 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3611093867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3611093867 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3034442548 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336940050000 ps |
| CPU time | 808.11 seconds |
| Started | May 12 01:52:37 PM PDT 24 |
| Finished | May 12 02:25:20 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-c978639e-3467-436d-b1d0-51ec36786c6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3034442548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3034442548 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1968400327 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336622430000 ps |
| CPU time | 844.08 seconds |
| Started | May 12 01:52:20 PM PDT 24 |
| Finished | May 12 02:26:39 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-6511d654-6e4d-4aa3-adae-92cfefc7d8e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1968400327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1968400327 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2903204561 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336472930000 ps |
| CPU time | 823.23 seconds |
| Started | May 12 01:52:38 PM PDT 24 |
| Finished | May 12 02:25:36 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-afaba2f7-719b-43f9-ac32-8c83fa6bb847 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2903204561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2903204561 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1208550154 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336444910000 ps |
| CPU time | 792.35 seconds |
| Started | May 12 01:52:39 PM PDT 24 |
| Finished | May 12 02:25:09 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-ec5d226a-be7d-42c6-862f-1a0f2a45e6ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1208550154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1208550154 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1696317110 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336811970000 ps |
| CPU time | 824.57 seconds |
| Started | May 12 01:52:38 PM PDT 24 |
| Finished | May 12 02:26:32 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-6c0c3c28-6ed1-4133-bd50-ac8d09d5046e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1696317110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1696317110 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2102245708 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336748890000 ps |
| CPU time | 767.62 seconds |
| Started | May 12 01:52:38 PM PDT 24 |
| Finished | May 12 02:24:05 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-a0773d52-6cc1-439e-b157-50b0de59e443 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2102245708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2102245708 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.663779633 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336934450000 ps |
| CPU time | 816.72 seconds |
| Started | May 12 01:52:38 PM PDT 24 |
| Finished | May 12 02:25:36 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-158f9497-cfeb-4ece-bdf2-52493c6d4d81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=663779633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.663779633 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.863000405 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336732670000 ps |
| CPU time | 939.64 seconds |
| Started | May 12 01:52:44 PM PDT 24 |
| Finished | May 12 02:31:38 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-c9d3ab3c-4fc9-434a-9c09-1ee8ba2acd52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=863000405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.863000405 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2379275227 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336750930000 ps |
| CPU time | 724.85 seconds |
| Started | May 12 01:52:41 PM PDT 24 |
| Finished | May 12 02:23:05 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-f7c4132d-6f81-412e-aeb0-2b5a150f66ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2379275227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2379275227 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3944961394 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336835770000 ps |
| CPU time | 774.55 seconds |
| Started | May 12 01:52:41 PM PDT 24 |
| Finished | May 12 02:24:13 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-39e7caf8-7607-4fd1-9352-46a58787c5c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3944961394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3944961394 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.967600391 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336908010000 ps |
| CPU time | 943.13 seconds |
| Started | May 12 01:52:44 PM PDT 24 |
| Finished | May 12 02:31:40 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-4dda2ee6-3319-4a3b-af71-bd9c1803aac9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=967600391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.967600391 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3376469911 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 337025030000 ps |
| CPU time | 826.44 seconds |
| Started | May 12 01:52:41 PM PDT 24 |
| Finished | May 12 02:26:42 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-86183c22-e51a-4dfd-aacc-be964b165b48 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3376469911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3376469911 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.810818131 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336721830000 ps |
| CPU time | 869.29 seconds |
| Started | May 12 01:52:22 PM PDT 24 |
| Finished | May 12 02:28:23 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-bc63a8d0-0ef6-4681-bfc5-45b833b1cc4b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=810818131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.810818131 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3232836401 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336302990000 ps |
| CPU time | 694.75 seconds |
| Started | May 12 01:52:42 PM PDT 24 |
| Finished | May 12 02:21:00 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-6229b054-544c-4140-b0a0-0e903423036c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3232836401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3232836401 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3199513938 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336687650000 ps |
| CPU time | 778.02 seconds |
| Started | May 12 01:52:42 PM PDT 24 |
| Finished | May 12 02:24:54 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-53db16bc-868d-41f3-b7c7-0425976d566b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3199513938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3199513938 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3546443389 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336543370000 ps |
| CPU time | 985.61 seconds |
| Started | May 12 01:52:45 PM PDT 24 |
| Finished | May 12 02:32:39 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-4b73f49b-5a6a-4896-8e94-5df370a67802 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3546443389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3546443389 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1376105750 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336484350000 ps |
| CPU time | 898.81 seconds |
| Started | May 12 01:52:48 PM PDT 24 |
| Finished | May 12 02:30:35 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-d3e01d10-d490-440b-b1b4-28d610ba52f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1376105750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1376105750 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3595581197 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336861210000 ps |
| CPU time | 846.47 seconds |
| Started | May 12 01:52:45 PM PDT 24 |
| Finished | May 12 02:27:29 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-3a72dd8b-d555-45d1-87b1-2f6f4c44d8ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3595581197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3595581197 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1794646959 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336951050000 ps |
| CPU time | 903.1 seconds |
| Started | May 12 01:52:48 PM PDT 24 |
| Finished | May 12 02:30:41 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-2045e73a-914c-49bb-bc35-c0773c7ac508 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1794646959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1794646959 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3924508683 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336879750000 ps |
| CPU time | 900.07 seconds |
| Started | May 12 01:52:49 PM PDT 24 |
| Finished | May 12 02:30:36 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-69e5139d-42cd-4e4a-9fc4-2d20b761f869 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3924508683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3924508683 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2029838299 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336539370000 ps |
| CPU time | 847.03 seconds |
| Started | May 12 01:52:47 PM PDT 24 |
| Finished | May 12 02:27:22 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-70e4b1c0-bbef-4f75-a9fd-785a31fad5c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2029838299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2029838299 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.963102832 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336836850000 ps |
| CPU time | 774.97 seconds |
| Started | May 12 01:52:47 PM PDT 24 |
| Finished | May 12 02:24:18 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-d2538733-9828-4f4c-aa8c-0659bcb645fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=963102832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.963102832 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.441096545 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336407730000 ps |
| CPU time | 835.38 seconds |
| Started | May 12 01:52:48 PM PDT 24 |
| Finished | May 12 02:26:27 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-fd253879-e049-434f-9c34-7329da46cf3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=441096545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.441096545 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1196495403 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336916690000 ps |
| CPU time | 893.59 seconds |
| Started | May 12 01:52:21 PM PDT 24 |
| Finished | May 12 02:28:54 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-60d72e05-5543-43c5-a315-4907d5dc19a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1196495403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1196495403 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2478646114 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 337005910000 ps |
| CPU time | 1020.69 seconds |
| Started | May 12 01:52:52 PM PDT 24 |
| Finished | May 12 02:35:34 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-dd9a08a1-e736-4871-94be-96ebedd9a857 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2478646114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2478646114 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1441102901 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336593650000 ps |
| CPU time | 823.45 seconds |
| Started | May 12 01:52:52 PM PDT 24 |
| Finished | May 12 02:26:13 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-7eb0642a-95fb-424b-bab3-87f4fa46f291 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1441102901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1441102901 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3151867909 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 337022370000 ps |
| CPU time | 850.25 seconds |
| Started | May 12 01:52:51 PM PDT 24 |
| Finished | May 12 02:27:04 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-fa2e88ea-f4f8-4392-a65c-c77350368cae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3151867909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3151867909 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2639503905 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336942930000 ps |
| CPU time | 842.77 seconds |
| Started | May 12 01:52:52 PM PDT 24 |
| Finished | May 12 02:27:23 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-c9351eaa-b018-4cb2-8f54-228f23879152 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2639503905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2639503905 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.493096399 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336518450000 ps |
| CPU time | 780.58 seconds |
| Started | May 12 01:52:55 PM PDT 24 |
| Finished | May 12 02:25:22 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-c2e994f2-9e71-4e61-8a37-c7407e74dc05 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=493096399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.493096399 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.114242798 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336367490000 ps |
| CPU time | 874.89 seconds |
| Started | May 12 01:52:55 PM PDT 24 |
| Finished | May 12 02:28:59 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-2308c6be-9e5f-49f0-8289-53c61e5dcaff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=114242798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.114242798 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3888848384 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336545050000 ps |
| CPU time | 791.51 seconds |
| Started | May 12 01:53:00 PM PDT 24 |
| Finished | May 12 02:25:48 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-30ca7b02-3ff3-4a7c-af34-5aa7205780da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3888848384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3888848384 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.782584540 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336676350000 ps |
| CPU time | 862.81 seconds |
| Started | May 12 01:52:59 PM PDT 24 |
| Finished | May 12 02:27:41 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-2705177e-79c2-4e08-a37e-5e97e1b50636 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=782584540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.782584540 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.260171460 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336818110000 ps |
| CPU time | 738.18 seconds |
| Started | May 12 01:53:04 PM PDT 24 |
| Finished | May 12 02:23:15 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-0083294f-0dd8-4dfb-8bbd-d5ff125fea2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=260171460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.260171460 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2778678532 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336945490000 ps |
| CPU time | 897.2 seconds |
| Started | May 12 01:53:13 PM PDT 24 |
| Finished | May 12 02:30:55 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-59976fa0-ce1e-477c-906d-386db55c6c72 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2778678532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2778678532 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2767605179 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336932170000 ps |
| CPU time | 843.68 seconds |
| Started | May 12 01:52:22 PM PDT 24 |
| Finished | May 12 02:26:55 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-0f81d453-b746-436e-83c6-2456a41199e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2767605179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2767605179 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.360122646 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336775050000 ps |
| CPU time | 878.86 seconds |
| Started | May 12 01:52:22 PM PDT 24 |
| Finished | May 12 02:28:50 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-00f68e56-85d9-4b30-8ad5-02398c34c2ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=360122646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.360122646 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4085254546 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 337026030000 ps |
| CPU time | 880.44 seconds |
| Started | May 12 01:52:24 PM PDT 24 |
| Finished | May 12 02:29:33 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-65497c22-65eb-4313-95d0-3742321ff093 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4085254546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4085254546 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1254703055 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336337370000 ps |
| CPU time | 765.51 seconds |
| Started | May 12 01:52:24 PM PDT 24 |
| Finished | May 12 02:23:36 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-b4963da2-2306-4e7b-8333-40abf209c6ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1254703055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1254703055 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2222800048 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 337016150000 ps |
| CPU time | 998.56 seconds |
| Started | May 12 01:52:25 PM PDT 24 |
| Finished | May 12 02:32:51 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-97a7c613-9b8c-4d0f-84d9-a17486f74722 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2222800048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2222800048 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4249057459 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336980150000 ps |
| CPU time | 830.02 seconds |
| Started | May 12 01:54:07 PM PDT 24 |
| Finished | May 12 02:28:09 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-7436c0f4-2d56-4519-a8f6-5d93f96d3e09 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4249057459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4249057459 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2841857502 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336531930000 ps |
| CPU time | 795.77 seconds |
| Started | May 12 01:54:06 PM PDT 24 |
| Finished | May 12 02:26:13 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-965108b5-ea5b-4c8d-afda-a8e45f9ddaee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2841857502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2841857502 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1219689195 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336804210000 ps |
| CPU time | 811.09 seconds |
| Started | May 12 01:54:22 PM PDT 24 |
| Finished | May 12 02:27:03 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-37a414af-dca9-4fd9-a8ae-ef4483e3243f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1219689195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1219689195 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.526243066 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336751250000 ps |
| CPU time | 831.08 seconds |
| Started | May 12 01:54:21 PM PDT 24 |
| Finished | May 12 02:28:40 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-0c8e6cfe-0fbd-49b7-b803-a4e14698296c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=526243066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.526243066 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3937407501 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336982510000 ps |
| CPU time | 872.59 seconds |
| Started | May 12 01:54:20 PM PDT 24 |
| Finished | May 12 02:28:52 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-8ecc14c0-2137-4c59-b79a-af5d66a23201 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3937407501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3937407501 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1771019837 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336722190000 ps |
| CPU time | 928.6 seconds |
| Started | May 12 01:54:22 PM PDT 24 |
| Finished | May 12 02:32:06 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-4d557eac-8b74-4297-a315-24aede852e1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1771019837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1771019837 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4237573197 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336636130000 ps |
| CPU time | 764.81 seconds |
| Started | May 12 01:54:20 PM PDT 24 |
| Finished | May 12 02:25:35 PM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-a825fe11-8385-49af-94c4-052cdcf3a1f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4237573197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4237573197 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.605120698 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336870750000 ps |
| CPU time | 927.03 seconds |
| Started | May 12 01:54:22 PM PDT 24 |
| Finished | May 12 02:31:47 PM PDT 24 |
| Peak memory | 160628 kb |
| Host | smart-06b54425-8e2e-4b5c-a99c-4d76a16969fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=605120698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.605120698 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.710569948 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336566210000 ps |
| CPU time | 827.75 seconds |
| Started | May 12 01:54:23 PM PDT 24 |
| Finished | May 12 02:28:34 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-0853ad38-0e1e-4506-bbdf-4101735e0dc0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=710569948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.710569948 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.393464480 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336844410000 ps |
| CPU time | 860.72 seconds |
| Started | May 12 01:54:28 PM PDT 24 |
| Finished | May 12 02:30:17 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-f0f2e1b4-aa46-4047-911e-399bf222f8fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=393464480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.393464480 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.770948376 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336442130000 ps |
| CPU time | 777.81 seconds |
| Started | May 12 01:54:28 PM PDT 24 |
| Finished | May 12 02:26:02 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-bd2b9ce2-708e-49f9-bd49-2b7d690b4c95 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=770948376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.770948376 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1031543000 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336562550000 ps |
| CPU time | 1016.83 seconds |
| Started | May 12 01:54:15 PM PDT 24 |
| Finished | May 12 02:36:58 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-dfa2bf80-efe3-45f7-bc80-2000c8bc4ede |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1031543000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1031543000 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2177050716 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336978530000 ps |
| CPU time | 762.84 seconds |
| Started | May 12 01:54:27 PM PDT 24 |
| Finished | May 12 02:25:33 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-8bd6b0ac-7a5a-46f1-a524-acbb7c1368b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2177050716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2177050716 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3311154452 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336975850000 ps |
| CPU time | 957.25 seconds |
| Started | May 12 01:54:27 PM PDT 24 |
| Finished | May 12 02:33:45 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-0017b61f-2dfc-4e13-92e8-a6c2213d6d38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3311154452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3311154452 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3637732348 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336463490000 ps |
| CPU time | 1009.61 seconds |
| Started | May 12 01:54:28 PM PDT 24 |
| Finished | May 12 02:37:03 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-387f07ff-b16d-4ccd-ab3b-560a3c1d97e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3637732348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3637732348 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1944023821 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336403190000 ps |
| CPU time | 781.07 seconds |
| Started | May 12 01:54:28 PM PDT 24 |
| Finished | May 12 02:26:06 PM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-f79574a0-dd42-449a-a573-8884c416fedc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1944023821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1944023821 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3319785028 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336793110000 ps |
| CPU time | 835.59 seconds |
| Started | May 12 01:54:30 PM PDT 24 |
| Finished | May 12 02:27:54 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-52a236c2-b087-418e-9c8a-4a35c90650ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3319785028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3319785028 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3601779275 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336468510000 ps |
| CPU time | 839.91 seconds |
| Started | May 12 01:54:31 PM PDT 24 |
| Finished | May 12 02:28:43 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-6b6b1449-8460-43a5-9fe9-81c017f52dec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3601779275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3601779275 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1711654931 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336537110000 ps |
| CPU time | 720.55 seconds |
| Started | May 12 01:54:31 PM PDT 24 |
| Finished | May 12 02:24:02 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-eb1f17dd-0c0c-4b23-b771-6b45683afba2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1711654931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1711654931 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3747632156 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336566030000 ps |
| CPU time | 822.52 seconds |
| Started | May 12 01:54:31 PM PDT 24 |
| Finished | May 12 02:28:25 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-703d24f6-1ed9-4cb4-a91b-e925c5c92bcc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3747632156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3747632156 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1076874 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336982730000 ps |
| CPU time | 803.62 seconds |
| Started | May 12 01:54:37 PM PDT 24 |
| Finished | May 12 02:27:40 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-c9b28c1d-c015-46bf-a40f-3ffff4edc797 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1076874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1076874 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.759962538 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336699970000 ps |
| CPU time | 800.29 seconds |
| Started | May 12 01:54:34 PM PDT 24 |
| Finished | May 12 02:27:32 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-26d61a0a-0284-4f72-a2dd-0a6e7a5eecad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=759962538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.759962538 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1461644403 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336878850000 ps |
| CPU time | 825.15 seconds |
| Started | May 12 01:54:16 PM PDT 24 |
| Finished | May 12 02:27:39 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-924e7848-cc7d-4aba-aa95-7d8deeef0008 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1461644403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1461644403 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3063618356 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336695550000 ps |
| CPU time | 917.92 seconds |
| Started | May 12 01:54:37 PM PDT 24 |
| Finished | May 12 02:32:38 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-bed6ca29-543a-49f7-b8d0-8dc41a07c4d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3063618356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3063618356 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3258557540 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336806750000 ps |
| CPU time | 730.47 seconds |
| Started | May 12 01:54:34 PM PDT 24 |
| Finished | May 12 02:24:33 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-cc6b0cb5-dfc9-4177-834b-c82835f9dddb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3258557540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3258557540 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.397328974 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336995810000 ps |
| CPU time | 912.45 seconds |
| Started | May 12 01:54:34 PM PDT 24 |
| Finished | May 12 02:31:42 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-045f561c-5028-4dc8-b472-4be9e1a453ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=397328974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.397328974 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3661702385 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336723210000 ps |
| CPU time | 732.3 seconds |
| Started | May 12 01:54:37 PM PDT 24 |
| Finished | May 12 02:24:36 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-281d32f2-6c8b-4ea6-9cd7-ce1f2fcdfe61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3661702385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3661702385 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4107097206 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336371790000 ps |
| CPU time | 738.42 seconds |
| Started | May 12 01:54:36 PM PDT 24 |
| Finished | May 12 02:24:56 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-f2af6883-766b-418f-b190-624a71ac46a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4107097206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.4107097206 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.542914684 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336731990000 ps |
| CPU time | 784.23 seconds |
| Started | May 12 01:54:38 PM PDT 24 |
| Finished | May 12 02:27:07 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-de894244-2b7d-4ac7-b6d0-f6072442fc05 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=542914684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.542914684 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1576104732 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336911770000 ps |
| CPU time | 615.37 seconds |
| Started | May 12 01:54:34 PM PDT 24 |
| Finished | May 12 02:20:06 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-113b7962-2550-45bf-8de8-f4ddf3130f5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1576104732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1576104732 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2746914658 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336619430000 ps |
| CPU time | 788.34 seconds |
| Started | May 12 01:54:38 PM PDT 24 |
| Finished | May 12 02:27:18 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-3a4d06e2-4e1a-4234-9fcc-458585c02b17 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2746914658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2746914658 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3410145741 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336492590000 ps |
| CPU time | 757.66 seconds |
| Started | May 12 01:54:38 PM PDT 24 |
| Finished | May 12 02:25:41 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-0186bc09-b3b3-4fbb-8f6b-c6bb8bddd310 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3410145741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3410145741 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.782020127 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336755750000 ps |
| CPU time | 1017.17 seconds |
| Started | May 12 01:54:40 PM PDT 24 |
| Finished | May 12 02:37:18 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-8af7ce74-36a1-49b5-affb-69d760203a6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=782020127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.782020127 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4231300270 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336923330000 ps |
| CPU time | 820.17 seconds |
| Started | May 12 01:54:16 PM PDT 24 |
| Finished | May 12 02:27:51 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-c7f736ab-a56f-43c2-9a46-9f36edcc69ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4231300270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.4231300270 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.879890279 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336582570000 ps |
| CPU time | 752.68 seconds |
| Started | May 12 01:54:41 PM PDT 24 |
| Finished | May 12 02:25:32 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-efb3ceeb-6f6f-4d1d-afaa-8de372457799 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=879890279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.879890279 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1491922869 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336262630000 ps |
| CPU time | 869.73 seconds |
| Started | May 12 01:54:39 PM PDT 24 |
| Finished | May 12 02:31:20 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-eead42eb-881b-41c0-9483-148590d10d41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1491922869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1491922869 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.763068673 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336340410000 ps |
| CPU time | 762.63 seconds |
| Started | May 12 01:54:38 PM PDT 24 |
| Finished | May 12 02:25:59 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-163d4787-381b-42d4-9f89-215512b17198 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=763068673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.763068673 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3091838371 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336446290000 ps |
| CPU time | 903.26 seconds |
| Started | May 12 01:54:38 PM PDT 24 |
| Finished | May 12 02:32:19 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-e271257a-05f1-4838-833d-398d2867955d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3091838371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3091838371 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1931175229 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336662930000 ps |
| CPU time | 761.88 seconds |
| Started | May 12 01:54:41 PM PDT 24 |
| Finished | May 12 02:25:45 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-bdf8ba17-33f5-4929-8724-c7b35d2f63d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1931175229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1931175229 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3178981531 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336793630000 ps |
| CPU time | 839.62 seconds |
| Started | May 12 01:54:42 PM PDT 24 |
| Finished | May 12 02:28:44 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-7b35c46d-1cb6-43ab-9bbf-c839f6b9b48c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3178981531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3178981531 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.719757607 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336693850000 ps |
| CPU time | 824 seconds |
| Started | May 12 01:54:42 PM PDT 24 |
| Finished | May 12 02:27:35 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-da3d0db2-61e2-4f7f-8745-880ef5fa0105 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=719757607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.719757607 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.940076746 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336701930000 ps |
| CPU time | 912.6 seconds |
| Started | May 12 01:54:42 PM PDT 24 |
| Finished | May 12 02:33:04 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-36648a31-32a3-4e11-af08-58ac9d3ab4db |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=940076746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.940076746 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1547798990 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336682270000 ps |
| CPU time | 732.24 seconds |
| Started | May 12 01:54:44 PM PDT 24 |
| Finished | May 12 02:24:56 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-42f797e8-6191-45a3-96dc-b66290cf7ab8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1547798990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1547798990 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.981649266 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336918750000 ps |
| CPU time | 871.06 seconds |
| Started | May 12 01:54:42 PM PDT 24 |
| Finished | May 12 02:31:25 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-42f19ef2-62cc-45f0-b386-abb70f361af9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=981649266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.981649266 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3090278485 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336644250000 ps |
| CPU time | 955.46 seconds |
| Started | May 12 01:54:15 PM PDT 24 |
| Finished | May 12 02:33:27 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-64fa9c1d-6886-42a4-abbc-e02757524dbf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3090278485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3090278485 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2903095410 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 337144850000 ps |
| CPU time | 852.58 seconds |
| Started | May 12 01:54:14 PM PDT 24 |
| Finished | May 12 02:29:04 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-235f7239-f5e6-4034-a139-0a48a0cd58e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2903095410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2903095410 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3669029814 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336554630000 ps |
| CPU time | 736.88 seconds |
| Started | May 12 01:54:16 PM PDT 24 |
| Finished | May 12 02:25:09 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-7f972366-a5e0-4e7b-ac00-3854543633b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3669029814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3669029814 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2519196386 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336940950000 ps |
| CPU time | 767.58 seconds |
| Started | May 12 01:54:17 PM PDT 24 |
| Finished | May 12 02:25:45 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-4d71cf85-525c-44b5-9b33-9d67014fff70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2519196386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2519196386 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2671296082 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336445450000 ps |
| CPU time | 753.96 seconds |
| Started | May 12 01:54:17 PM PDT 24 |
| Finished | May 12 02:25:22 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-278f63d8-22ff-454a-a079-643a36319011 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2671296082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2671296082 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3356130643 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1441710000 ps |
| CPU time | 4.94 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-a439674c-5646-4094-9fff-fec415815de6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3356130643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3356130643 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2980773964 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1439830000 ps |
| CPU time | 3.6 seconds |
| Started | May 12 01:46:13 PM PDT 24 |
| Finished | May 12 01:46:21 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-fe27c5b4-2e01-4e3d-8688-2c3d150fcee4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2980773964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2980773964 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.37700768 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1453770000 ps |
| CPU time | 4.65 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-0ed30850-19ad-492a-9068-6d464619a96e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=37700768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.37700768 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2881250475 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1437790000 ps |
| CPU time | 4.47 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-cfb4ba24-6793-4def-847d-986722b14b1e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2881250475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2881250475 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.17043861 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1489230000 ps |
| CPU time | 4.29 seconds |
| Started | May 12 01:46:16 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-ff6e8e9b-30af-41ca-b6bb-2b38b380d88e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=17043861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.17043861 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1679955017 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1541250000 ps |
| CPU time | 4.78 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-4085b2aa-2d7b-49ae-8228-5abf8c2209d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1679955017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1679955017 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3867844006 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1568490000 ps |
| CPU time | 4.23 seconds |
| Started | May 12 01:46:13 PM PDT 24 |
| Finished | May 12 01:46:23 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-b413477f-8487-44f6-911c-6c8ad72dbdb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3867844006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3867844006 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3898792868 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1226190000 ps |
| CPU time | 4.39 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-f4fc5967-a31a-4646-83a0-b15fbb3481e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3898792868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3898792868 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2948233723 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1531210000 ps |
| CPU time | 5.66 seconds |
| Started | May 12 01:46:18 PM PDT 24 |
| Finished | May 12 01:46:31 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-47d07e9f-4017-4858-bb3e-8e9cece6785e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2948233723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2948233723 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.125197707 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1417350000 ps |
| CPU time | 4.68 seconds |
| Started | May 12 01:46:14 PM PDT 24 |
| Finished | May 12 01:46:24 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-b6479e8c-aacc-40e3-9fcb-523c7cc318d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=125197707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.125197707 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.422798870 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1571350000 ps |
| CPU time | 5.74 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:31 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-a86dbd3e-777c-44be-bd4f-7fd39b42754d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=422798870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.422798870 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1840209653 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1471230000 ps |
| CPU time | 4.81 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-5bd3f7e6-d4a3-4893-8a45-731cd08d5d91 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1840209653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1840209653 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2614851046 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1589890000 ps |
| CPU time | 4.59 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-f31ecf42-3546-4f69-add6-54e42b31b747 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2614851046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2614851046 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3878388764 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1486010000 ps |
| CPU time | 4.92 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-d78cd2ee-439e-40f2-868a-876665da0d7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3878388764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3878388764 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3460982346 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1454550000 ps |
| CPU time | 3.71 seconds |
| Started | May 12 01:46:12 PM PDT 24 |
| Finished | May 12 01:46:21 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-9055f317-4331-4f38-a1db-87f5114bce23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3460982346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3460982346 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3422433081 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1431590000 ps |
| CPU time | 4.8 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-97bda1bc-044f-4951-8a25-51cfc92352b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3422433081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3422433081 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1333135439 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1427270000 ps |
| CPU time | 4.6 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-3c72b7fa-a3f2-49dc-add4-3d58a574833d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1333135439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1333135439 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2653788513 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1204490000 ps |
| CPU time | 4.4 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-7c6db299-95ff-4f3e-9554-793c657e4406 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2653788513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2653788513 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2385815284 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1450970000 ps |
| CPU time | 4.39 seconds |
| Started | May 12 01:45:59 PM PDT 24 |
| Finished | May 12 01:46:09 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-e651206a-f5c7-4301-8590-16705269c6bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2385815284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2385815284 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1162067451 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1527090000 ps |
| CPU time | 4.37 seconds |
| Started | May 12 01:46:16 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-e4c2ca85-1686-4e2f-938f-92e65dad1505 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1162067451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1162067451 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1878380251 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1286790000 ps |
| CPU time | 4.38 seconds |
| Started | May 12 01:46:14 PM PDT 24 |
| Finished | May 12 01:46:24 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-85513dae-9b50-4ed3-a7d9-964cc9e3e7b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1878380251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1878380251 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2332561034 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1514410000 ps |
| CPU time | 4.96 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-9e534bc7-46b4-4bce-a870-7a6a46ab5aad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2332561034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2332561034 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2648408395 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1560250000 ps |
| CPU time | 4.26 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:25 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-d655fa86-2d73-4a5d-a3ce-20ef4cc263c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2648408395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2648408395 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2802188256 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1406830000 ps |
| CPU time | 4.61 seconds |
| Started | May 12 01:46:16 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-b82bb44a-0c55-47de-8cd8-df2741f64f4e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2802188256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2802188256 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.671067133 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1338690000 ps |
| CPU time | 4.41 seconds |
| Started | May 12 01:46:16 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-686cb9d8-9f19-480c-be1b-a93c1bf101dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=671067133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.671067133 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1194973659 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1464030000 ps |
| CPU time | 3.17 seconds |
| Started | May 12 01:46:01 PM PDT 24 |
| Finished | May 12 01:46:08 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-4b71b146-1f80-4899-b82a-400c850eed7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1194973659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1194973659 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1772871418 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1297650000 ps |
| CPU time | 3.82 seconds |
| Started | May 12 01:46:16 PM PDT 24 |
| Finished | May 12 01:46:25 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-007ddb6b-0047-4bcd-9e8f-93ee6c36f20f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1772871418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1772871418 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3029546994 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1515910000 ps |
| CPU time | 4.33 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-cef79936-76c4-4036-8ee3-b502329babaa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3029546994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3029546994 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.839350285 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1426210000 ps |
| CPU time | 3.93 seconds |
| Started | May 12 01:46:18 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-4a21103e-1e64-4d77-8aa2-5c608f92e840 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=839350285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.839350285 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3142957964 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1371030000 ps |
| CPU time | 3.42 seconds |
| Started | May 12 01:46:18 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-06d17321-977e-440b-b3fc-6e78f131667f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3142957964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3142957964 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2806447512 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1505870000 ps |
| CPU time | 4.8 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-e928f37e-b096-4a82-aaa6-d1f4e43bf073 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2806447512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2806447512 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3968993024 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1508930000 ps |
| CPU time | 4.54 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-95d5185d-38cd-4f23-9c0d-9b235af53f45 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3968993024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3968993024 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2074021712 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1573130000 ps |
| CPU time | 4.49 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-023eaa8b-f7e0-4446-ae79-bc6b5c6e535d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2074021712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2074021712 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3428094904 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1573930000 ps |
| CPU time | 4.95 seconds |
| Started | May 12 01:46:14 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-cb065f3c-afd4-4f83-8486-8af579e91a5d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3428094904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3428094904 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2153347692 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1548510000 ps |
| CPU time | 4.8 seconds |
| Started | May 12 01:46:15 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-3a85467e-9cea-4766-bb6e-1aa1995fd4c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2153347692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2153347692 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1964935931 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1616090000 ps |
| CPU time | 5.58 seconds |
| Started | May 12 01:46:16 PM PDT 24 |
| Finished | May 12 01:46:29 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-a982041d-ea7e-41b0-99ed-d101219ef014 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1964935931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1964935931 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1490847481 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1272750000 ps |
| CPU time | 4.14 seconds |
| Started | May 12 01:46:18 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-70f7e8f7-e928-4841-a1dc-3b3a8ff10d8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1490847481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1490847481 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1568134492 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1350690000 ps |
| CPU time | 4.26 seconds |
| Started | May 12 01:46:18 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-81ada64c-2dae-4a40-891b-de5871913b2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1568134492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1568134492 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1345293132 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1412390000 ps |
| CPU time | 2.99 seconds |
| Started | May 12 01:46:17 PM PDT 24 |
| Finished | May 12 01:46:24 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-427a4e2b-1f0f-4d02-a7b9-5b857328d2f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1345293132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1345293132 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2400223873 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1524610000 ps |
| CPU time | 5.54 seconds |
| Started | May 12 01:46:23 PM PDT 24 |
| Finished | May 12 01:46:38 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-b7b5d601-e16f-4355-a532-8faae71db00f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2400223873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2400223873 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1534874050 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1367330000 ps |
| CPU time | 3.02 seconds |
| Started | May 12 01:46:20 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-eeec8ca2-ba0a-4af9-98e9-df4bb1b1d486 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1534874050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1534874050 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.770184811 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1109790000 ps |
| CPU time | 2.76 seconds |
| Started | May 12 01:46:20 PM PDT 24 |
| Finished | May 12 01:46:27 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-f76008e1-9852-462a-9dba-d1f360e2ed50 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=770184811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.770184811 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.412386527 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1454410000 ps |
| CPU time | 4.4 seconds |
| Started | May 12 01:46:18 PM PDT 24 |
| Finished | May 12 01:46:28 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-5c465624-4bb3-4883-8062-7408b29df679 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=412386527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.412386527 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3021114662 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1555530000 ps |
| CPU time | 4.08 seconds |
| Started | May 12 01:46:08 PM PDT 24 |
| Finished | May 12 01:46:18 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-3f76a9ee-ffe7-45c8-b2f1-b9706ec4b1a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3021114662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3021114662 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2771088988 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1288430000 ps |
| CPU time | 4.25 seconds |
| Started | May 12 01:46:12 PM PDT 24 |
| Finished | May 12 01:46:21 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-c7130604-7730-448a-9449-4f5324debe7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2771088988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2771088988 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2466787792 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1467330000 ps |
| CPU time | 3.41 seconds |
| Started | May 12 01:46:12 PM PDT 24 |
| Finished | May 12 01:46:20 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-af9eca25-3a61-4282-8dc9-2ddbe01a3e0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2466787792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2466787792 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3129960747 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1564530000 ps |
| CPU time | 4.8 seconds |
| Started | May 12 01:46:11 PM PDT 24 |
| Finished | May 12 01:46:22 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-ee3735d2-8b41-4f9b-94ea-82ff517569e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3129960747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3129960747 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1818787293 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1637270000 ps |
| CPU time | 5.08 seconds |
| Started | May 12 01:46:14 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-30364d06-b803-4ba1-acc4-9ef58436f65a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1818787293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1818787293 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.712307462 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1505290000 ps |
| CPU time | 4.84 seconds |
| Started | May 12 01:46:14 PM PDT 24 |
| Finished | May 12 01:46:26 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-3230bd7b-2a3a-4173-bea8-8cc1a85a5661 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=712307462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.712307462 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.984133380 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1302730000 ps |
| CPU time | 4.88 seconds |
| Started | May 12 01:53:05 PM PDT 24 |
| Finished | May 12 01:53:17 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-0b464d3e-3823-49b6-93ef-708e34044e4c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=984133380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.984133380 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.338274883 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1400190000 ps |
| CPU time | 4.14 seconds |
| Started | May 12 01:53:13 PM PDT 24 |
| Finished | May 12 01:53:23 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-bcd7cabb-74ee-492b-b167-c1780a609441 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=338274883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.338274883 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4059297182 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1528850000 ps |
| CPU time | 3.82 seconds |
| Started | May 12 01:53:17 PM PDT 24 |
| Finished | May 12 01:53:26 PM PDT 24 |
| Peak memory | 164688 kb |
| Host | smart-b14982d9-66cf-4b88-b667-d6514617dc75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4059297182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.4059297182 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2195891376 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1527810000 ps |
| CPU time | 6.2 seconds |
| Started | May 12 01:53:19 PM PDT 24 |
| Finished | May 12 01:53:33 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-aa4ee166-4ea7-4ee3-ba98-62f6bf9585d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2195891376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2195891376 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2336445000 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1463830000 ps |
| CPU time | 3.92 seconds |
| Started | May 12 01:53:21 PM PDT 24 |
| Finished | May 12 01:53:30 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-b45d4de6-bd97-42e1-867b-9977ac575487 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2336445000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2336445000 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.96150921 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1443070000 ps |
| CPU time | 3.3 seconds |
| Started | May 12 01:53:24 PM PDT 24 |
| Finished | May 12 01:53:32 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-ca6a2646-dcbd-4892-b1b5-9c9dc1e43155 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=96150921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.96150921 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.503496690 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1284590000 ps |
| CPU time | 5.07 seconds |
| Started | May 12 01:53:29 PM PDT 24 |
| Finished | May 12 01:53:41 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-a9a5dfff-344d-4e4d-a83e-79c69c65b7f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=503496690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.503496690 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1282941290 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1416010000 ps |
| CPU time | 4.4 seconds |
| Started | May 12 01:53:30 PM PDT 24 |
| Finished | May 12 01:53:39 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-7971f152-5480-45fe-a81b-09d89c32c115 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1282941290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1282941290 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.956587044 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1436530000 ps |
| CPU time | 6.63 seconds |
| Started | May 12 01:53:32 PM PDT 24 |
| Finished | May 12 01:53:46 PM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-aa770ca0-6861-4b39-8907-d3114bd42e84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=956587044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.956587044 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1340605884 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1523890000 ps |
| CPU time | 3.34 seconds |
| Started | May 12 01:53:34 PM PDT 24 |
| Finished | May 12 01:53:42 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-5ddbc784-14fd-4415-98a2-75a2f94b4a8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1340605884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1340605884 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1419756882 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1364510000 ps |
| CPU time | 4.09 seconds |
| Started | May 12 01:53:40 PM PDT 24 |
| Finished | May 12 01:53:49 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-50647732-890d-4362-a17b-4dc7c8311378 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1419756882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1419756882 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.874655668 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1358310000 ps |
| CPU time | 3.37 seconds |
| Started | May 12 01:53:03 PM PDT 24 |
| Finished | May 12 01:53:11 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-706087d0-9167-4d86-899c-e80e958c49a2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=874655668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.874655668 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3735410662 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1475410000 ps |
| CPU time | 5.44 seconds |
| Started | May 12 01:53:43 PM PDT 24 |
| Finished | May 12 01:53:56 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-c55e00c1-1840-44a9-b57a-1f5bdf7d8f23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3735410662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3735410662 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.131547739 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1448710000 ps |
| CPU time | 5.1 seconds |
| Started | May 12 01:53:42 PM PDT 24 |
| Finished | May 12 01:53:53 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-d44e3832-dab8-4a3f-9805-261377f60524 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=131547739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.131547739 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3504698201 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1562530000 ps |
| CPU time | 6.67 seconds |
| Started | May 12 01:53:44 PM PDT 24 |
| Finished | May 12 01:53:58 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-989b5212-5244-43d2-8057-422ee550dc1a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3504698201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3504698201 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2576918716 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1251290000 ps |
| CPU time | 5.12 seconds |
| Started | May 12 01:53:45 PM PDT 24 |
| Finished | May 12 01:53:56 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-2efea10d-c75e-4b6e-b50a-0f141dad9ded |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2576918716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2576918716 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2820368503 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1299930000 ps |
| CPU time | 4.39 seconds |
| Started | May 12 01:53:48 PM PDT 24 |
| Finished | May 12 01:53:58 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-82b2432d-4738-4926-80b3-a4f5ea16f7ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2820368503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2820368503 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2382552976 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1523010000 ps |
| CPU time | 3.59 seconds |
| Started | May 12 01:53:45 PM PDT 24 |
| Finished | May 12 01:53:53 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-04dcf778-8ea3-4381-a21c-759f7f4b3ceb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2382552976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2382552976 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3600444786 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1518070000 ps |
| CPU time | 5.64 seconds |
| Started | May 12 01:53:49 PM PDT 24 |
| Finished | May 12 01:54:02 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-2681739d-83bf-4fc4-8ef2-3ffbe21e211e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3600444786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3600444786 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3557352859 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1513290000 ps |
| CPU time | 4.59 seconds |
| Started | May 12 01:53:49 PM PDT 24 |
| Finished | May 12 01:53:59 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-6b8bad52-8133-4e56-b3b6-589c4887cf0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3557352859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3557352859 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1694540859 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1595110000 ps |
| CPU time | 6.47 seconds |
| Started | May 12 01:53:52 PM PDT 24 |
| Finished | May 12 01:54:06 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-c66af940-15f1-43b3-a238-66256f205948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1694540859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1694540859 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3638303421 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1543130000 ps |
| CPU time | 5.23 seconds |
| Started | May 12 01:53:53 PM PDT 24 |
| Finished | May 12 01:54:05 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-bd162aef-419e-4f85-890f-b4d6d337403a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3638303421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3638303421 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1178089666 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1250190000 ps |
| CPU time | 4.33 seconds |
| Started | May 12 01:53:06 PM PDT 24 |
| Finished | May 12 01:53:16 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-571c9818-1e5a-426e-b245-7a8693faa0bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1178089666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1178089666 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2152649222 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1500990000 ps |
| CPU time | 3.64 seconds |
| Started | May 12 01:53:52 PM PDT 24 |
| Finished | May 12 01:54:00 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-4d4400b1-6bae-42a7-b504-0e98ee68362e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2152649222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2152649222 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1715175006 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1401690000 ps |
| CPU time | 4.14 seconds |
| Started | May 12 01:53:53 PM PDT 24 |
| Finished | May 12 01:54:02 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-de161e56-a91c-473b-9f08-d0472ecae4d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1715175006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1715175006 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.315414081 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1435970000 ps |
| CPU time | 4.66 seconds |
| Started | May 12 01:53:53 PM PDT 24 |
| Finished | May 12 01:54:04 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-19776f7e-4d7f-40b1-a5da-f6f0f04093fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=315414081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.315414081 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2648949760 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1511670000 ps |
| CPU time | 3.57 seconds |
| Started | May 12 01:53:52 PM PDT 24 |
| Finished | May 12 01:54:00 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-cefe2106-cae1-4913-83ef-25a863bfb4d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2648949760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2648949760 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.463326112 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1416470000 ps |
| CPU time | 5.28 seconds |
| Started | May 12 01:53:54 PM PDT 24 |
| Finished | May 12 01:54:07 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-6fcd734e-f23c-462c-ad67-b554764dbbd1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=463326112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.463326112 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3895922332 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1342370000 ps |
| CPU time | 4.73 seconds |
| Started | May 12 01:53:54 PM PDT 24 |
| Finished | May 12 01:54:05 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-d4e31386-7b5a-40f2-870a-67827ca2f404 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3895922332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3895922332 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2232154111 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1323750000 ps |
| CPU time | 5.53 seconds |
| Started | May 12 01:53:56 PM PDT 24 |
| Finished | May 12 01:54:08 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-42f867b8-b5e6-4a1b-b9cd-aff43acb238d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2232154111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2232154111 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1764091849 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1495170000 ps |
| CPU time | 5.4 seconds |
| Started | May 12 01:53:57 PM PDT 24 |
| Finished | May 12 01:54:10 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-541c2d26-233f-435f-aa8d-79688e752930 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1764091849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1764091849 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2332108116 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1465990000 ps |
| CPU time | 3.66 seconds |
| Started | May 12 01:53:56 PM PDT 24 |
| Finished | May 12 01:54:05 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-326b8e97-b7da-4460-acd8-7e3920f9a25a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2332108116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2332108116 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.149773662 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1493410000 ps |
| CPU time | 4.88 seconds |
| Started | May 12 01:53:56 PM PDT 24 |
| Finished | May 12 01:54:07 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-d90856bf-0144-4486-81bf-858d58b1158d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=149773662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.149773662 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1680639179 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1564970000 ps |
| CPU time | 3.65 seconds |
| Started | May 12 01:53:08 PM PDT 24 |
| Finished | May 12 01:53:16 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-89ddf08b-dbe9-4ba9-89fd-57ec58363fdc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1680639179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1680639179 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.263505086 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1450950000 ps |
| CPU time | 3.91 seconds |
| Started | May 12 01:54:00 PM PDT 24 |
| Finished | May 12 01:54:09 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-943dc260-bd1a-4a30-a5df-9dd460f38302 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=263505086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.263505086 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.35404776 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1448970000 ps |
| CPU time | 4.99 seconds |
| Started | May 12 01:54:00 PM PDT 24 |
| Finished | May 12 01:54:12 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-68c03a3d-e380-4439-b61e-df93004dba4a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=35404776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.35404776 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.215393759 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1451690000 ps |
| CPU time | 4.01 seconds |
| Started | May 12 01:53:59 PM PDT 24 |
| Finished | May 12 01:54:08 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-1a67ee34-b929-498b-9a2a-d8c16fc5e8f0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=215393759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.215393759 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.134819552 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1576970000 ps |
| CPU time | 4.52 seconds |
| Started | May 12 01:53:59 PM PDT 24 |
| Finished | May 12 01:54:10 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-0412308c-b191-4209-b5ae-045370d0e203 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=134819552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.134819552 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2367103722 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1440810000 ps |
| CPU time | 3.32 seconds |
| Started | May 12 01:54:03 PM PDT 24 |
| Finished | May 12 01:54:11 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-375c6ccb-85e8-47b8-b01e-a24d65f29d07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2367103722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2367103722 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2551169789 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1220770000 ps |
| CPU time | 5.79 seconds |
| Started | May 12 01:54:04 PM PDT 24 |
| Finished | May 12 01:54:16 PM PDT 24 |
| Peak memory | 164688 kb |
| Host | smart-9e641338-f66d-4b0c-9170-ee86697685f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2551169789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2551169789 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2853928431 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1559990000 ps |
| CPU time | 5.63 seconds |
| Started | May 12 01:54:04 PM PDT 24 |
| Finished | May 12 01:54:18 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-90c094f1-5ded-4f0a-a9bb-6b8efe077ac8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2853928431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2853928431 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1475542030 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1484470000 ps |
| CPU time | 3.8 seconds |
| Started | May 12 01:54:03 PM PDT 24 |
| Finished | May 12 01:54:11 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-9a5d7e92-1cdb-4a50-bcec-dc33d26e243d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1475542030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1475542030 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.502484085 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1531990000 ps |
| CPU time | 3.55 seconds |
| Started | May 12 01:54:06 PM PDT 24 |
| Finished | May 12 01:54:14 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-a4bd9d54-97cf-4141-a1f9-cacb480abb37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=502484085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.502484085 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2780729897 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1494430000 ps |
| CPU time | 5.07 seconds |
| Started | May 12 01:54:08 PM PDT 24 |
| Finished | May 12 01:54:20 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-35339fe9-406d-44e8-a59a-0cfbc2dbefa3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2780729897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2780729897 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1140221750 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1461390000 ps |
| CPU time | 4.58 seconds |
| Started | May 12 01:53:10 PM PDT 24 |
| Finished | May 12 01:53:21 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-6e6be423-f5d1-490d-903a-c667e1bdfd65 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1140221750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1140221750 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2944889844 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1278210000 ps |
| CPU time | 3.9 seconds |
| Started | May 12 01:53:10 PM PDT 24 |
| Finished | May 12 01:53:20 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-6c11dfa5-8f46-47ac-83a4-19742724f00a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2944889844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2944889844 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.716779763 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1488390000 ps |
| CPU time | 4.75 seconds |
| Started | May 12 01:53:10 PM PDT 24 |
| Finished | May 12 01:53:21 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-c79bd738-2692-4898-8774-d2ab48701950 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=716779763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.716779763 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1539829516 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1547930000 ps |
| CPU time | 6.58 seconds |
| Started | May 12 01:53:10 PM PDT 24 |
| Finished | May 12 01:53:23 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-2de23c0d-9b27-4565-adb6-07075697a01f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1539829516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1539829516 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3084177586 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1568050000 ps |
| CPU time | 5.49 seconds |
| Started | May 12 01:53:14 PM PDT 24 |
| Finished | May 12 01:53:27 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-2312b30c-6da7-4e2e-8eb9-1f2477761713 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3084177586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3084177586 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |