| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.727387620 | ||
| 96.81 | 9.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 47.50 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1012907892 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3111403139 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3270454378 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.357473890 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3566144721 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3602596075 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1945598508 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3209703061 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1194165610 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.652429030 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3528911980 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1936906790 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3050355460 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.101203765 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.937651949 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1224826573 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2126679082 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4076065068 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1523906291 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1032790400 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3443017914 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.123024082 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2289632596 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4061412244 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3987373999 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2700118672 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.752096608 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1094756663 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1102397884 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2104619052 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1113623504 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1710028601 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1430740441 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.982780208 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.148376688 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3330511600 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1753407983 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3223198324 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1434941846 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2589903989 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.629335456 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4282635843 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3747618795 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.696337057 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3093407784 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2826960811 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1421203869 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3001294322 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3877208129 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3115698293 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3262624870 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1604435299 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1897977524 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2306408476 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3042205235 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4122423292 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1892149713 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.951503641 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4182988858 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2106897608 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4150393381 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2734469327 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.276470781 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1090968157 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1194345689 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.570863610 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3842936860 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1314670492 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.715429277 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2570944393 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3825170160 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4074184040 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3201323581 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2355995980 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2802919664 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2439759651 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.306298388 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2822010334 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4088192441 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.207128447 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3825981846 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4107682749 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2627858981 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1223186351 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2037103949 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2345265988 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2123975248 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.350342470 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.679073010 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.282978788 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.744898389 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1769633780 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1523514798 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1952995447 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2587481057 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3015815027 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.328600877 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3976080287 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2087283736 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1121640669 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1856898514 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2620758857 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2149174321 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2501449554 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1369769802 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1668698153 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2314561160 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3835936867 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3554054 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4137278395 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2378266010 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1081918392 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2570220312 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2339484997 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2170772944 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1456315205 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2317758009 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4063306683 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3492785065 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2183196504 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3342059899 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2951396681 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1616683674 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2230263747 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3742815665 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1677827284 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.924689851 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3053394837 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3974203601 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1823684227 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2025208608 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.518029469 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1000773742 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.592748681 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3213490750 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3142415355 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.777688003 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.273210522 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4210991756 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.295375060 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2569399792 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4225586691 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2804269251 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2388660704 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.662144079 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.313026681 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1721960289 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3747654354 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2531297723 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2075043003 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.145334724 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4046808419 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1793328841 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.43546587 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3122322400 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.792358350 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3503314809 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.17160605 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2997526532 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.350900784 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2119484172 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3557095590 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.380108366 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1406388848 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1316034922 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1194500951 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1475023090 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.396671005 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3934350621 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2650718400 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.436312828 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.22709022 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.21762174 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3176817201 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2017310534 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2089499312 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1647209842 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2370962683 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2916235517 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3450848433 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3150002047 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1745022066 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.223705066 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.289864900 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2202660983 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3886007069 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2006276121 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4085880583 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.338045771 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2962524034 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3535204942 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2576953189 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2442660890 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1680241706 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3099986206 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3875985786 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2951299453 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3928751416 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3767603364 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.145334724 | May 14 01:35:57 PM PDT 24 | May 14 01:36:11 PM PDT 24 | 1467990000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2006276121 | May 14 01:36:21 PM PDT 24 | May 14 01:36:32 PM PDT 24 | 1428030000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3928751416 | May 14 01:35:57 PM PDT 24 | May 14 01:36:11 PM PDT 24 | 1596370000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1647209842 | May 14 01:36:20 PM PDT 24 | May 14 01:36:28 PM PDT 24 | 1188170000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2119484172 | May 14 01:36:05 PM PDT 24 | May 14 01:36:17 PM PDT 24 | 1514570000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2962524034 | May 14 01:36:32 PM PDT 24 | May 14 01:36:43 PM PDT 24 | 1469470000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.43546587 | May 14 01:36:03 PM PDT 24 | May 14 01:36:12 PM PDT 24 | 1290390000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1316034922 | May 14 01:36:18 PM PDT 24 | May 14 01:36:27 PM PDT 24 | 1452850000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.396671005 | May 14 01:36:21 PM PDT 24 | May 14 01:36:35 PM PDT 24 | 1554310000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.727387620 | May 14 01:35:56 PM PDT 24 | May 14 01:36:11 PM PDT 24 | 1566570000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3535204942 | May 14 01:36:32 PM PDT 24 | May 14 01:36:44 PM PDT 24 | 1437470000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3934350621 | May 14 01:36:22 PM PDT 24 | May 14 01:36:33 PM PDT 24 | 1395530000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2370962683 | May 14 01:36:23 PM PDT 24 | May 14 01:36:33 PM PDT 24 | 1197170000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.22709022 | May 14 01:36:22 PM PDT 24 | May 14 01:36:35 PM PDT 24 | 1469630000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1745022066 | May 14 01:36:22 PM PDT 24 | May 14 01:36:36 PM PDT 24 | 1596750000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2997526532 | May 14 01:36:07 PM PDT 24 | May 14 01:36:17 PM PDT 24 | 1381830000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2951299453 | May 14 01:36:00 PM PDT 24 | May 14 01:36:11 PM PDT 24 | 1434550000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1793328841 | May 14 01:35:56 PM PDT 24 | May 14 01:36:09 PM PDT 24 | 1474610000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2089499312 | May 14 01:36:22 PM PDT 24 | May 14 01:36:36 PM PDT 24 | 1432570000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3176817201 | May 14 01:36:21 PM PDT 24 | May 14 01:36:33 PM PDT 24 | 1385470000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2576953189 | May 14 01:36:32 PM PDT 24 | May 14 01:36:45 PM PDT 24 | 1526430000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3875985786 | May 14 01:35:57 PM PDT 24 | May 14 01:36:11 PM PDT 24 | 1586910000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3503314809 | May 14 01:35:59 PM PDT 24 | May 14 01:36:12 PM PDT 24 | 1519690000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2442660890 | May 14 01:36:34 PM PDT 24 | May 14 01:36:44 PM PDT 24 | 1364890000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.17160605 | May 14 01:36:03 PM PDT 24 | May 14 01:36:13 PM PDT 24 | 1452010000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3450848433 | May 14 01:36:22 PM PDT 24 | May 14 01:36:31 PM PDT 24 | 1223390000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.380108366 | May 14 01:36:13 PM PDT 24 | May 14 01:36:22 PM PDT 24 | 1298610000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1406388848 | May 14 01:36:13 PM PDT 24 | May 14 01:36:24 PM PDT 24 | 1407890000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2202660983 | May 14 01:36:21 PM PDT 24 | May 14 01:36:34 PM PDT 24 | 1431930000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3886007069 | May 14 01:36:21 PM PDT 24 | May 14 01:36:33 PM PDT 24 | 1327190000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1194500951 | May 14 01:36:20 PM PDT 24 | May 14 01:36:31 PM PDT 24 | 1523130000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2916235517 | May 14 01:36:22 PM PDT 24 | May 14 01:36:36 PM PDT 24 | 1597010000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3099986206 | May 14 01:35:57 PM PDT 24 | May 14 01:36:09 PM PDT 24 | 1409490000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1475023090 | May 14 01:36:22 PM PDT 24 | May 14 01:36:35 PM PDT 24 | 1528310000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2650718400 | May 14 01:36:20 PM PDT 24 | May 14 01:36:32 PM PDT 24 | 1558090000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2017310534 | May 14 01:36:21 PM PDT 24 | May 14 01:36:34 PM PDT 24 | 1487930000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.350900784 | May 14 01:36:06 PM PDT 24 | May 14 01:36:18 PM PDT 24 | 1431750000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4046808419 | May 14 01:35:57 PM PDT 24 | May 14 01:36:10 PM PDT 24 | 1464050000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.223705066 | May 14 01:36:21 PM PDT 24 | May 14 01:36:34 PM PDT 24 | 1371910000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3557095590 | May 14 01:35:57 PM PDT 24 | May 14 01:36:09 PM PDT 24 | 1476190000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3122322400 | May 14 01:35:59 PM PDT 24 | May 14 01:36:13 PM PDT 24 | 1593110000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3767603364 | May 14 01:35:57 PM PDT 24 | May 14 01:36:09 PM PDT 24 | 1184670000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4085880583 | May 14 01:36:33 PM PDT 24 | May 14 01:36:44 PM PDT 24 | 1325830000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.436312828 | May 14 01:36:22 PM PDT 24 | May 14 01:36:33 PM PDT 24 | 1363830000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.289864900 | May 14 01:35:55 PM PDT 24 | May 14 01:36:08 PM PDT 24 | 1362350000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.338045771 | May 14 01:36:35 PM PDT 24 | May 14 01:36:47 PM PDT 24 | 1236610000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3150002047 | May 14 01:36:23 PM PDT 24 | May 14 01:36:34 PM PDT 24 | 1246150000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.21762174 | May 14 01:35:55 PM PDT 24 | May 14 01:36:10 PM PDT 24 | 1597210000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.792358350 | May 14 01:35:58 PM PDT 24 | May 14 01:36:09 PM PDT 24 | 1409130000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1680241706 | May 14 01:36:32 PM PDT 24 | May 14 01:36:42 PM PDT 24 | 1299010000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3001294322 | May 14 01:16:51 PM PDT 24 | May 14 01:51:59 PM PDT 24 | 336483050000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3987373999 | May 14 01:16:55 PM PDT 24 | May 14 01:53:45 PM PDT 24 | 336359430000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1094756663 | May 14 01:17:09 PM PDT 24 | May 14 01:53:58 PM PDT 24 | 336858530000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1012907892 | May 14 01:16:53 PM PDT 24 | May 14 01:47:22 PM PDT 24 | 336360590000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.123024082 | May 14 01:16:54 PM PDT 24 | May 14 01:55:19 PM PDT 24 | 336811030000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4061412244 | May 14 01:16:58 PM PDT 24 | May 14 01:51:23 PM PDT 24 | 336803690000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3093407784 | May 14 01:16:57 PM PDT 24 | May 14 01:49:25 PM PDT 24 | 336744490000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.752096608 | May 14 01:17:00 PM PDT 24 | May 14 01:55:56 PM PDT 24 | 336422770000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2589903989 | May 14 01:16:59 PM PDT 24 | May 14 01:47:25 PM PDT 24 | 336383130000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1032790400 | May 14 01:17:05 PM PDT 24 | May 14 01:54:03 PM PDT 24 | 336321910000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3223198324 | May 14 01:16:58 PM PDT 24 | May 14 01:56:17 PM PDT 24 | 337098550000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1102397884 | May 14 01:16:57 PM PDT 24 | May 14 01:57:16 PM PDT 24 | 336853730000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1523906291 | May 14 01:16:56 PM PDT 24 | May 14 01:51:12 PM PDT 24 | 336958690000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3115698293 | May 14 01:17:10 PM PDT 24 | May 14 01:51:22 PM PDT 24 | 336364910000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3877208129 | May 14 01:17:02 PM PDT 24 | May 14 01:52:11 PM PDT 24 | 336440090000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2826960811 | May 14 01:16:57 PM PDT 24 | May 14 01:57:20 PM PDT 24 | 336402330000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.101203765 | May 14 01:17:07 PM PDT 24 | May 14 01:50:20 PM PDT 24 | 336464830000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2700118672 | May 14 01:16:56 PM PDT 24 | May 14 02:00:32 PM PDT 24 | 336411050000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4076065068 | May 14 01:16:58 PM PDT 24 | May 14 01:48:12 PM PDT 24 | 336362150000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1936906790 | May 14 01:16:52 PM PDT 24 | May 14 01:50:41 PM PDT 24 | 336568010000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3262624870 | May 14 01:17:03 PM PDT 24 | May 14 01:49:05 PM PDT 24 | 336737450000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1945598508 | May 14 01:16:58 PM PDT 24 | May 14 01:53:37 PM PDT 24 | 336336650000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.357473890 | May 14 01:16:53 PM PDT 24 | May 14 01:56:37 PM PDT 24 | 336766550000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3330511600 | May 14 01:16:55 PM PDT 24 | May 14 02:00:34 PM PDT 24 | 336425010000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1753407983 | May 14 01:17:08 PM PDT 24 | May 14 01:52:50 PM PDT 24 | 336385010000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3602596075 | May 14 01:17:03 PM PDT 24 | May 14 01:49:08 PM PDT 24 | 336924510000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3270454378 | May 14 01:16:46 PM PDT 24 | May 14 01:41:51 PM PDT 24 | 337047030000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.937651949 | May 14 01:16:47 PM PDT 24 | May 14 01:46:07 PM PDT 24 | 336584010000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.982780208 | May 14 01:17:12 PM PDT 24 | May 14 01:52:13 PM PDT 24 | 336490230000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2104619052 | May 14 01:16:53 PM PDT 24 | May 14 01:47:15 PM PDT 24 | 336704830000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3566144721 | May 14 01:16:56 PM PDT 24 | May 14 01:53:22 PM PDT 24 | 336848350000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.629335456 | May 14 01:17:03 PM PDT 24 | May 14 01:52:17 PM PDT 24 | 336790490000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4282635843 | May 14 01:17:01 PM PDT 24 | May 14 01:55:51 PM PDT 24 | 336657230000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3747618795 | May 14 01:16:54 PM PDT 24 | May 14 01:49:48 PM PDT 24 | 336565950000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1421203869 | May 14 01:16:54 PM PDT 24 | May 14 01:58:26 PM PDT 24 | 336639770000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3050355460 | May 14 01:17:01 PM PDT 24 | May 14 01:51:59 PM PDT 24 | 336357230000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3209703061 | May 14 01:16:58 PM PDT 24 | May 14 01:52:11 PM PDT 24 | 337020790000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2126679082 | May 14 01:16:55 PM PDT 24 | May 14 02:01:03 PM PDT 24 | 336989130000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1224826573 | May 14 01:16:56 PM PDT 24 | May 14 01:53:24 PM PDT 24 | 336928330000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2289632596 | May 14 01:16:55 PM PDT 24 | May 14 01:49:30 PM PDT 24 | 336626550000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1194165610 | May 14 01:17:11 PM PDT 24 | May 14 01:55:16 PM PDT 24 | 336450450000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.696337057 | May 14 01:16:55 PM PDT 24 | May 14 01:53:50 PM PDT 24 | 336568070000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1430740441 | May 14 01:16:54 PM PDT 24 | May 14 01:53:52 PM PDT 24 | 337045110000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1113623504 | May 14 01:17:00 PM PDT 24 | May 14 01:52:10 PM PDT 24 | 336650650000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3528911980 | May 14 01:17:01 PM PDT 24 | May 14 01:50:53 PM PDT 24 | 336958130000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.148376688 | May 14 01:17:00 PM PDT 24 | May 14 01:56:38 PM PDT 24 | 336446190000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.652429030 | May 14 01:16:53 PM PDT 24 | May 14 01:58:08 PM PDT 24 | 336776690000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1710028601 | May 14 01:17:01 PM PDT 24 | May 14 01:54:26 PM PDT 24 | 336449110000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3443017914 | May 14 01:16:51 PM PDT 24 | May 14 01:52:15 PM PDT 24 | 336511230000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1434941846 | May 14 01:16:57 PM PDT 24 | May 14 01:57:16 PM PDT 24 | 336604270000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3492785065 | May 14 01:17:13 PM PDT 24 | May 14 01:17:26 PM PDT 24 | 1532530000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4137278395 | May 14 01:17:08 PM PDT 24 | May 14 01:17:18 PM PDT 24 | 1283130000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1616683674 | May 14 01:17:06 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 1400070000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2531297723 | May 14 01:16:55 PM PDT 24 | May 14 01:17:06 PM PDT 24 | 1303150000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.273210522 | May 14 01:17:03 PM PDT 24 | May 14 01:17:14 PM PDT 24 | 1270750000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2149174321 | May 14 01:17:01 PM PDT 24 | May 14 01:17:12 PM PDT 24 | 1339690000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1856898514 | May 14 01:17:10 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 1220870000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.518029469 | May 14 01:17:06 PM PDT 24 | May 14 01:17:16 PM PDT 24 | 1178150000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2570220312 | May 14 01:16:56 PM PDT 24 | May 14 01:17:12 PM PDT 24 | 1472490000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3053394837 | May 14 01:17:03 PM PDT 24 | May 14 01:17:17 PM PDT 24 | 1505010000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2170772944 | May 14 01:17:14 PM PDT 24 | May 14 01:17:23 PM PDT 24 | 1215070000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.777688003 | May 14 01:17:15 PM PDT 24 | May 14 01:17:24 PM PDT 24 | 1386590000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2951396681 | May 14 01:17:05 PM PDT 24 | May 14 01:17:17 PM PDT 24 | 1336570000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2230263747 | May 14 01:16:51 PM PDT 24 | May 14 01:17:00 PM PDT 24 | 1478890000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1369769802 | May 14 01:16:56 PM PDT 24 | May 14 01:17:12 PM PDT 24 | 1451870000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2378266010 | May 14 01:17:02 PM PDT 24 | May 14 01:17:14 PM PDT 24 | 1502470000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2804269251 | May 14 01:17:06 PM PDT 24 | May 14 01:17:21 PM PDT 24 | 1430470000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2620758857 | May 14 01:16:56 PM PDT 24 | May 14 01:17:10 PM PDT 24 | 1503890000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3742815665 | May 14 01:17:05 PM PDT 24 | May 14 01:17:18 PM PDT 24 | 1554050000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4210991756 | May 14 01:17:11 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 1439970000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3554054 | May 14 01:17:01 PM PDT 24 | May 14 01:17:09 PM PDT 24 | 1163850000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4225586691 | May 14 01:17:05 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 1513210000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1081918392 | May 14 01:17:14 PM PDT 24 | May 14 01:17:26 PM PDT 24 | 1462050000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2314561160 | May 14 01:16:57 PM PDT 24 | May 14 01:17:09 PM PDT 24 | 1522190000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3974203601 | May 14 01:17:06 PM PDT 24 | May 14 01:17:18 PM PDT 24 | 1172330000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.592748681 | May 14 01:17:17 PM PDT 24 | May 14 01:17:29 PM PDT 24 | 1392230000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3747654354 | May 14 01:16:55 PM PDT 24 | May 14 01:17:11 PM PDT 24 | 1313750000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2025208608 | May 14 01:17:02 PM PDT 24 | May 14 01:17:12 PM PDT 24 | 1403350000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2183196504 | May 14 01:17:07 PM PDT 24 | May 14 01:17:20 PM PDT 24 | 1510570000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.295375060 | May 14 01:17:06 PM PDT 24 | May 14 01:17:17 PM PDT 24 | 1431790000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2569399792 | May 14 01:17:06 PM PDT 24 | May 14 01:17:17 PM PDT 24 | 1243150000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1677827284 | May 14 01:17:05 PM PDT 24 | May 14 01:17:17 PM PDT 24 | 1301530000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3342059899 | May 14 01:17:15 PM PDT 24 | May 14 01:17:25 PM PDT 24 | 1436250000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.924689851 | May 14 01:17:13 PM PDT 24 | May 14 01:17:25 PM PDT 24 | 1611170000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1721960289 | May 14 01:17:01 PM PDT 24 | May 14 01:17:15 PM PDT 24 | 1561830000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1456315205 | May 14 01:17:03 PM PDT 24 | May 14 01:17:16 PM PDT 24 | 1315310000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3213490750 | May 14 01:16:59 PM PDT 24 | May 14 01:17:10 PM PDT 24 | 1478030000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2501449554 | May 14 01:17:10 PM PDT 24 | May 14 01:17:18 PM PDT 24 | 1478870000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2317758009 | May 14 01:17:12 PM PDT 24 | May 14 01:17:24 PM PDT 24 | 1423870000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3835936867 | May 14 01:16:57 PM PDT 24 | May 14 01:17:10 PM PDT 24 | 1415210000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.662144079 | May 14 01:17:03 PM PDT 24 | May 14 01:17:14 PM PDT 24 | 1361510000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1668698153 | May 14 01:16:55 PM PDT 24 | May 14 01:17:09 PM PDT 24 | 1508950000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.313026681 | May 14 01:16:54 PM PDT 24 | May 14 01:17:07 PM PDT 24 | 1476010000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4063306683 | May 14 01:17:02 PM PDT 24 | May 14 01:17:11 PM PDT 24 | 1287370000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3142415355 | May 14 01:17:15 PM PDT 24 | May 14 01:17:27 PM PDT 24 | 1365690000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1823684227 | May 14 01:17:15 PM PDT 24 | May 14 01:17:21 PM PDT 24 | 1045770000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2388660704 | May 14 01:17:10 PM PDT 24 | May 14 01:17:22 PM PDT 24 | 1620790000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2075043003 | May 14 01:17:10 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 1524250000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2339484997 | May 14 01:17:06 PM PDT 24 | May 14 01:17:18 PM PDT 24 | 1578670000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1000773742 | May 14 01:17:06 PM PDT 24 | May 14 01:17:19 PM PDT 24 | 1436230000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1314670492 | May 14 01:17:20 PM PDT 24 | May 14 01:47:45 PM PDT 24 | 337002070000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2627858981 | May 14 01:17:18 PM PDT 24 | May 14 02:01:05 PM PDT 24 | 336792290000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.306298388 | May 14 01:17:29 PM PDT 24 | May 14 01:54:08 PM PDT 24 | 336326870000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4122423292 | May 14 01:17:24 PM PDT 24 | May 14 01:52:21 PM PDT 24 | 336636770000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3111403139 | May 14 01:17:06 PM PDT 24 | May 14 01:57:17 PM PDT 24 | 336393610000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2587481057 | May 14 01:17:16 PM PDT 24 | May 14 01:53:45 PM PDT 24 | 336555970000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.282978788 | May 14 01:17:20 PM PDT 24 | May 14 01:51:29 PM PDT 24 | 336796130000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4088192441 | May 14 01:17:23 PM PDT 24 | May 14 01:52:08 PM PDT 24 | 336912910000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.328600877 | May 14 01:17:06 PM PDT 24 | May 14 01:52:49 PM PDT 24 | 336440090000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.951503641 | May 14 01:17:18 PM PDT 24 | May 14 01:54:08 PM PDT 24 | 336561150000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4150393381 | May 14 01:17:19 PM PDT 24 | May 14 01:46:54 PM PDT 24 | 336736930000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.744898389 | May 14 01:17:29 PM PDT 24 | May 14 01:54:34 PM PDT 24 | 337070010000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3825170160 | May 14 01:17:18 PM PDT 24 | May 14 01:53:34 PM PDT 24 | 336703690000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.276470781 | May 14 01:17:06 PM PDT 24 | May 14 01:53:35 PM PDT 24 | 336733610000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3842936860 | May 14 01:17:23 PM PDT 24 | May 14 01:51:39 PM PDT 24 | 336531050000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3015815027 | May 14 01:17:05 PM PDT 24 | May 14 01:53:26 PM PDT 24 | 336500910000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2037103949 | May 14 01:17:16 PM PDT 24 | May 14 01:49:22 PM PDT 24 | 336907530000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2087283736 | May 14 01:17:06 PM PDT 24 | May 14 01:53:43 PM PDT 24 | 336900550000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3201323581 | May 14 01:17:19 PM PDT 24 | May 14 01:50:02 PM PDT 24 | 336571730000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1897977524 | May 14 01:17:15 PM PDT 24 | May 14 01:55:58 PM PDT 24 | 336948890000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.350342470 | May 14 01:17:24 PM PDT 24 | May 14 01:56:34 PM PDT 24 | 337012950000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4182988858 | May 14 01:17:22 PM PDT 24 | May 14 01:56:06 PM PDT 24 | 336984110000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2822010334 | May 14 01:17:15 PM PDT 24 | May 14 01:52:39 PM PDT 24 | 336975070000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4074184040 | May 14 01:17:25 PM PDT 24 | May 14 01:47:02 PM PDT 24 | 336607370000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3042205235 | May 14 01:17:24 PM PDT 24 | May 14 01:50:08 PM PDT 24 | 336515510000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1194345689 | May 14 01:17:19 PM PDT 24 | May 14 01:49:26 PM PDT 24 | 337014990000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2734469327 | May 14 01:17:25 PM PDT 24 | May 14 01:56:00 PM PDT 24 | 336697330000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.207128447 | May 14 01:17:21 PM PDT 24 | May 14 01:56:24 PM PDT 24 | 336533630000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2345265988 | May 14 01:17:25 PM PDT 24 | May 14 01:55:46 PM PDT 24 | 336805290000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2570944393 | May 14 01:17:20 PM PDT 24 | May 14 01:50:35 PM PDT 24 | 336424290000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.570863610 | May 14 01:17:24 PM PDT 24 | May 14 01:51:56 PM PDT 24 | 336417710000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3976080287 | May 14 01:17:11 PM PDT 24 | May 14 01:56:18 PM PDT 24 | 336544730000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2355995980 | May 14 01:17:14 PM PDT 24 | May 14 01:53:12 PM PDT 24 | 336898490000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1223186351 | May 14 01:17:16 PM PDT 24 | May 14 01:50:44 PM PDT 24 | 336825850000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1121640669 | May 14 01:17:23 PM PDT 24 | May 14 01:52:31 PM PDT 24 | 337081050000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.715429277 | May 14 01:17:19 PM PDT 24 | May 14 01:51:43 PM PDT 24 | 337004250000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2306408476 | May 14 01:17:24 PM PDT 24 | May 14 01:49:34 PM PDT 24 | 336978630000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1892149713 | May 14 01:17:23 PM PDT 24 | May 14 01:52:03 PM PDT 24 | 336501130000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2802919664 | May 14 01:17:25 PM PDT 24 | May 14 01:55:53 PM PDT 24 | 336408510000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4107682749 | May 14 01:17:20 PM PDT 24 | May 14 01:49:45 PM PDT 24 | 337006950000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2439759651 | May 14 01:17:15 PM PDT 24 | May 14 01:48:03 PM PDT 24 | 336993730000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.679073010 | May 14 01:17:24 PM PDT 24 | May 14 01:51:51 PM PDT 24 | 336864870000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1952995447 | May 14 01:17:20 PM PDT 24 | May 14 01:52:26 PM PDT 24 | 336633130000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1523514798 | May 14 01:17:24 PM PDT 24 | May 14 01:58:22 PM PDT 24 | 336845070000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2123975248 | May 14 01:17:20 PM PDT 24 | May 14 01:58:15 PM PDT 24 | 336354090000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2106897608 | May 14 01:17:15 PM PDT 24 | May 14 01:47:20 PM PDT 24 | 337087050000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1769633780 | May 14 01:17:23 PM PDT 24 | May 14 01:58:10 PM PDT 24 | 336385510000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1604435299 | May 14 01:17:13 PM PDT 24 | May 14 01:50:35 PM PDT 24 | 336439770000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3825981846 | May 14 01:17:19 PM PDT 24 | May 14 01:54:50 PM PDT 24 | 336924210000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1090968157 | May 14 01:17:18 PM PDT 24 | May 14 01:57:37 PM PDT 24 | 336781550000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.727387620 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1566570000 ps |
| CPU time | 5.27 seconds |
| Started | May 14 01:35:56 PM PDT 24 |
| Finished | May 14 01:36:11 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-9ddd4f27-4cf8-47c2-b96a-868953a10e97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=727387620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.727387620 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1012907892 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336360590000 ps |
| CPU time | 752.24 seconds |
| Started | May 14 01:16:53 PM PDT 24 |
| Finished | May 14 01:47:22 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-908bba13-6709-41e5-bd3e-c1160ea56fce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1012907892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1012907892 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3111403139 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336393610000 ps |
| CPU time | 941.34 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:57:17 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-3c0afb82-0ca0-42c0-a6a4-1d28624ff6ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3111403139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3111403139 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3270454378 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 337047030000 ps |
| CPU time | 592.23 seconds |
| Started | May 14 01:16:46 PM PDT 24 |
| Finished | May 14 01:41:51 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-2b37217d-7669-423b-be86-daa6481547d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3270454378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3270454378 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.357473890 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336766550000 ps |
| CPU time | 917.57 seconds |
| Started | May 14 01:16:53 PM PDT 24 |
| Finished | May 14 01:56:37 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-f6d3672c-4470-40b6-b7f7-4d7c38d5ba6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=357473890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.357473890 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3566144721 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336848350000 ps |
| CPU time | 884.88 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 01:53:22 PM PDT 24 |
| Peak memory | 160612 kb |
| Host | smart-660426dd-cab2-4469-b63d-4754e77465a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3566144721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3566144721 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3602596075 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336924510000 ps |
| CPU time | 789.19 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:49:08 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-1ac7a7c8-4eed-4428-bde8-89a832860692 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3602596075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3602596075 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1945598508 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336336650000 ps |
| CPU time | 913.09 seconds |
| Started | May 14 01:16:58 PM PDT 24 |
| Finished | May 14 01:53:37 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-4ff9d3b9-beb4-4f05-9f54-be3cc32b478a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1945598508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1945598508 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3209703061 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 337020790000 ps |
| CPU time | 872.31 seconds |
| Started | May 14 01:16:58 PM PDT 24 |
| Finished | May 14 01:52:11 PM PDT 24 |
| Peak memory | 160920 kb |
| Host | smart-daf10058-ecc7-4809-82c4-12e8a6b3fe71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3209703061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3209703061 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1194165610 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336450450000 ps |
| CPU time | 918.26 seconds |
| Started | May 14 01:17:11 PM PDT 24 |
| Finished | May 14 01:55:16 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-01b84581-aae3-48de-88fd-afe3e6983088 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1194165610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1194165610 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.652429030 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336776690000 ps |
| CPU time | 996.12 seconds |
| Started | May 14 01:16:53 PM PDT 24 |
| Finished | May 14 01:58:08 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-1c357b09-b1ed-4a2b-bbbc-b089c997882e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=652429030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.652429030 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3528911980 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336958130000 ps |
| CPU time | 828.8 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:50:53 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-ccc41f62-debb-4b58-84c4-d638816552ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3528911980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3528911980 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1936906790 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 336568010000 ps |
| CPU time | 841.48 seconds |
| Started | May 14 01:16:52 PM PDT 24 |
| Finished | May 14 01:50:41 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-5a2865b9-b2da-4737-9094-207638ead0a2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1936906790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1936906790 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3050355460 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336357230000 ps |
| CPU time | 844.81 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:51:59 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-8077656b-b22c-4641-934e-7a565eb01296 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3050355460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3050355460 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.101203765 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 336464830000 ps |
| CPU time | 828.81 seconds |
| Started | May 14 01:17:07 PM PDT 24 |
| Finished | May 14 01:50:20 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-377836c9-e81e-4dd6-be99-4bd9b768e62b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=101203765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.101203765 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.937651949 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336584010000 ps |
| CPU time | 716.27 seconds |
| Started | May 14 01:16:47 PM PDT 24 |
| Finished | May 14 01:46:07 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-2ef83472-d73c-4573-8733-44f9daa924c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=937651949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.937651949 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1224826573 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336928330000 ps |
| CPU time | 884.99 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 01:53:24 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-cc541e3f-55bb-488c-a93f-9cf36718a67c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1224826573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1224826573 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2126679082 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336989130000 ps |
| CPU time | 1058.31 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 02:01:03 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-f09edaf7-6605-4724-903a-bdceff57998d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2126679082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2126679082 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4076065068 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 336362150000 ps |
| CPU time | 766.07 seconds |
| Started | May 14 01:16:58 PM PDT 24 |
| Finished | May 14 01:48:12 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-118e422c-3ced-4b76-a9ef-d17621f94a80 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4076065068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4076065068 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1523906291 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336958690000 ps |
| CPU time | 841.74 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 01:51:12 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-d23d4b40-216b-4e33-829c-dd4c609db155 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1523906291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1523906291 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1032790400 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336321910000 ps |
| CPU time | 898.49 seconds |
| Started | May 14 01:17:05 PM PDT 24 |
| Finished | May 14 01:54:03 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-fb94cbe3-c951-48b2-8cea-4e5baac9f8a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1032790400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1032790400 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3443017914 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336511230000 ps |
| CPU time | 859.12 seconds |
| Started | May 14 01:16:51 PM PDT 24 |
| Finished | May 14 01:52:15 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-e70ce287-c008-4e06-85a0-59f803cc8225 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3443017914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3443017914 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.123024082 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336811030000 ps |
| CPU time | 928.24 seconds |
| Started | May 14 01:16:54 PM PDT 24 |
| Finished | May 14 01:55:19 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-77f80d25-4c7f-4425-afb0-8ea09bd9b9cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=123024082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.123024082 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2289632596 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336626550000 ps |
| CPU time | 811.45 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 01:49:30 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-ec4f80b6-1be4-47e6-b790-bcedc92eb5ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2289632596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2289632596 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.4061412244 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336803690000 ps |
| CPU time | 843.2 seconds |
| Started | May 14 01:16:58 PM PDT 24 |
| Finished | May 14 01:51:23 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-f3b91dd3-a4ab-4dc3-bb68-b9dc4afb6efd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4061412244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.4061412244 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3987373999 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 336359430000 ps |
| CPU time | 892.89 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 01:53:45 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-9e4ea231-8ed9-4898-8319-40d76ffe24e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3987373999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3987373999 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2700118672 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336411050000 ps |
| CPU time | 1039.2 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 02:00:32 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-340e76c9-9a48-41ba-b0ec-4b934b51bf86 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2700118672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2700118672 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.752096608 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336422770000 ps |
| CPU time | 929.83 seconds |
| Started | May 14 01:17:00 PM PDT 24 |
| Finished | May 14 01:55:56 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-9c09e5ef-a293-4053-811e-0c0ff4475aca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=752096608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.752096608 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1094756663 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 336858530000 ps |
| CPU time | 898.44 seconds |
| Started | May 14 01:17:09 PM PDT 24 |
| Finished | May 14 01:53:58 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-0f5c0aea-b7ed-4307-bf79-7c3e1e39f3df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1094756663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1094756663 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1102397884 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336853730000 ps |
| CPU time | 960.15 seconds |
| Started | May 14 01:16:57 PM PDT 24 |
| Finished | May 14 01:57:16 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-b42db7f8-3163-475c-a3ad-0971a2a5ac4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1102397884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1102397884 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2104619052 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336704830000 ps |
| CPU time | 742.36 seconds |
| Started | May 14 01:16:53 PM PDT 24 |
| Finished | May 14 01:47:15 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-be0147df-82c2-4796-b3bf-91b5b63501a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2104619052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2104619052 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1113623504 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336650650000 ps |
| CPU time | 855.32 seconds |
| Started | May 14 01:17:00 PM PDT 24 |
| Finished | May 14 01:52:10 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-d67cd766-a6c1-4931-a399-ff2bef7bbc16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1113623504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1113623504 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1710028601 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336449110000 ps |
| CPU time | 913.24 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:54:26 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-b5746358-8666-4c92-9422-5241c7d2c974 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1710028601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1710028601 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1430740441 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 337045110000 ps |
| CPU time | 898.35 seconds |
| Started | May 14 01:16:54 PM PDT 24 |
| Finished | May 14 01:53:52 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-56ee2580-b390-4b5f-93ad-9373fc49b9ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1430740441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1430740441 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.982780208 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336490230000 ps |
| CPU time | 846.22 seconds |
| Started | May 14 01:17:12 PM PDT 24 |
| Finished | May 14 01:52:13 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-5897620f-89eb-4c4c-a7cb-f1ce1d9e95dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=982780208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.982780208 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.148376688 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336446190000 ps |
| CPU time | 919.83 seconds |
| Started | May 14 01:17:00 PM PDT 24 |
| Finished | May 14 01:56:38 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-34374511-f04d-4674-a13d-d80a04fa01e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=148376688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.148376688 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3330511600 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336425010000 ps |
| CPU time | 1042.9 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 02:00:34 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-c11b89ae-f114-4497-9907-aaf55666e867 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3330511600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3330511600 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1753407983 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336385010000 ps |
| CPU time | 876.77 seconds |
| Started | May 14 01:17:08 PM PDT 24 |
| Finished | May 14 01:52:50 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-e506e297-3fee-45a9-a7e7-8209f8b4b73f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1753407983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1753407983 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3223198324 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 337098550000 ps |
| CPU time | 946.58 seconds |
| Started | May 14 01:16:58 PM PDT 24 |
| Finished | May 14 01:56:17 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-9ede8eb0-3f11-4175-8dc2-16f4a8c7e286 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3223198324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3223198324 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1434941846 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336604270000 ps |
| CPU time | 951.52 seconds |
| Started | May 14 01:16:57 PM PDT 24 |
| Finished | May 14 01:57:16 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-063f29f4-fcdf-4c4f-9675-579dcd182b71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1434941846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1434941846 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2589903989 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336383130000 ps |
| CPU time | 744.37 seconds |
| Started | May 14 01:16:59 PM PDT 24 |
| Finished | May 14 01:47:25 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-27ed95f7-f224-4b14-a22b-021b8fb1c24d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2589903989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2589903989 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.629335456 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336790490000 ps |
| CPU time | 869.13 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:52:17 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-185af663-0565-4645-9634-01b68d0da1d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=629335456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.629335456 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4282635843 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336657230000 ps |
| CPU time | 942.19 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:55:51 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-e0daaae4-6041-46fc-9cf0-65c35659e283 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4282635843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4282635843 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3747618795 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336565950000 ps |
| CPU time | 822.69 seconds |
| Started | May 14 01:16:54 PM PDT 24 |
| Finished | May 14 01:49:48 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-796889de-5fa5-47c7-9b8a-df84dd6782e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3747618795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3747618795 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.696337057 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336568070000 ps |
| CPU time | 894.57 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 01:53:50 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-873da35e-08f3-4aa4-b901-76bc7d2142a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=696337057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.696337057 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3093407784 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336744490000 ps |
| CPU time | 809.15 seconds |
| Started | May 14 01:16:57 PM PDT 24 |
| Finished | May 14 01:49:25 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-4da5921e-ad78-4e6a-8213-ed8b56e012a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3093407784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3093407784 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2826960811 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336402330000 ps |
| CPU time | 953.07 seconds |
| Started | May 14 01:16:57 PM PDT 24 |
| Finished | May 14 01:57:20 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-58dca0cc-5220-4a1a-8dff-f1d5555ca474 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2826960811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2826960811 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1421203869 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336639770000 ps |
| CPU time | 1019.51 seconds |
| Started | May 14 01:16:54 PM PDT 24 |
| Finished | May 14 01:58:26 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-d26ed24f-9cdd-4f64-9bcb-1a65b7ee9283 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1421203869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1421203869 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3001294322 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 336483050000 ps |
| CPU time | 852.36 seconds |
| Started | May 14 01:16:51 PM PDT 24 |
| Finished | May 14 01:51:59 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-87e231f0-0016-40a3-b8ff-caa51e3deca4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3001294322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3001294322 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3877208129 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 336440090000 ps |
| CPU time | 847.23 seconds |
| Started | May 14 01:17:02 PM PDT 24 |
| Finished | May 14 01:52:11 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-e396ab9c-2067-4ab3-ad9b-534798e83aed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3877208129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3877208129 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3115698293 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 336364910000 ps |
| CPU time | 812.65 seconds |
| Started | May 14 01:17:10 PM PDT 24 |
| Finished | May 14 01:51:22 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-15f52221-43c3-4a67-af77-da769d5fd630 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3115698293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3115698293 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3262624870 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336737450000 ps |
| CPU time | 807.35 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:49:05 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-37240b2c-8970-4a70-bc3b-1928c7a16a5a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3262624870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3262624870 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1604435299 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336439770000 ps |
| CPU time | 832.43 seconds |
| Started | May 14 01:17:13 PM PDT 24 |
| Finished | May 14 01:50:35 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-c1526f2b-b252-41cb-a57a-21df65a9940d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1604435299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1604435299 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1897977524 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336948890000 ps |
| CPU time | 937.18 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:55:58 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-5f77e80a-37f0-45c5-a536-309983ab7a45 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1897977524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1897977524 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2306408476 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336978630000 ps |
| CPU time | 799.84 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:49:34 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-3e3407bc-1507-47eb-ad96-6803f9369769 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2306408476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2306408476 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3042205235 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336515510000 ps |
| CPU time | 806.04 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:50:08 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-601d0d36-7027-435a-8366-48e4e568f299 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3042205235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3042205235 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4122423292 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336636770000 ps |
| CPU time | 842.67 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:52:21 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-b9622c54-a032-4799-b63c-e70d1f50db50 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4122423292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4122423292 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1892149713 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336501130000 ps |
| CPU time | 829.46 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:52:03 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-400cbf99-2687-45fc-8f9f-a2b3556ef1ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1892149713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1892149713 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.951503641 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336561150000 ps |
| CPU time | 896.02 seconds |
| Started | May 14 01:17:18 PM PDT 24 |
| Finished | May 14 01:54:08 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-f2988921-b943-4345-8c77-224cf57fba1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=951503641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.951503641 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4182988858 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336984110000 ps |
| CPU time | 922.82 seconds |
| Started | May 14 01:17:22 PM PDT 24 |
| Finished | May 14 01:56:06 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-bcccacf2-cd2c-44e1-93a5-e195167ae053 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4182988858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.4182988858 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2106897608 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 337087050000 ps |
| CPU time | 741.77 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:47:20 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-6c1bb5e0-3385-463e-aad9-aba84300549a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2106897608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2106897608 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.4150393381 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336736930000 ps |
| CPU time | 725.79 seconds |
| Started | May 14 01:17:19 PM PDT 24 |
| Finished | May 14 01:46:54 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-f20f2a54-fc37-4c75-afb7-3bfc60813278 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4150393381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.4150393381 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2734469327 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336697330000 ps |
| CPU time | 889.31 seconds |
| Started | May 14 01:17:25 PM PDT 24 |
| Finished | May 14 01:56:00 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-2dd26081-d59e-428b-8bff-44e852614039 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2734469327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2734469327 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.276470781 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336733610000 ps |
| CPU time | 885.47 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:53:35 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-95499933-2d9f-42fb-af3e-0e3eb82c65a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=276470781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.276470781 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1090968157 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336781550000 ps |
| CPU time | 965.98 seconds |
| Started | May 14 01:17:18 PM PDT 24 |
| Finished | May 14 01:57:37 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-3aab15ed-8e44-4835-914a-d12368046fd6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1090968157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1090968157 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1194345689 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337014990000 ps |
| CPU time | 795.21 seconds |
| Started | May 14 01:17:19 PM PDT 24 |
| Finished | May 14 01:49:26 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-f7042682-208e-4bcb-845a-7db02433650b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1194345689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1194345689 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.570863610 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336417710000 ps |
| CPU time | 835.96 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:51:56 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-9772c11f-c23e-4fe2-a7f9-241009cbccc8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=570863610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.570863610 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3842936860 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336531050000 ps |
| CPU time | 844.62 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:51:39 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-62397fd1-b8c8-48d7-9c0c-a078633956b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3842936860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3842936860 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1314670492 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 337002070000 ps |
| CPU time | 748.9 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:47:45 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-84fba37d-59e2-4c9a-9b50-9708dddd085f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1314670492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1314670492 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.715429277 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 337004250000 ps |
| CPU time | 836.65 seconds |
| Started | May 14 01:17:19 PM PDT 24 |
| Finished | May 14 01:51:43 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-07355615-8ee0-45ee-8fc0-97976f3f73e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=715429277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.715429277 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2570944393 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336424290000 ps |
| CPU time | 824.16 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:50:35 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-aea5e886-a115-4c5b-bacb-565959eb5a27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2570944393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2570944393 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3825170160 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336703690000 ps |
| CPU time | 886.67 seconds |
| Started | May 14 01:17:18 PM PDT 24 |
| Finished | May 14 01:53:34 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-63ba8aec-49f0-4cbb-979a-7765fb3eb9ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3825170160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3825170160 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4074184040 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336607370000 ps |
| CPU time | 731.93 seconds |
| Started | May 14 01:17:25 PM PDT 24 |
| Finished | May 14 01:47:02 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-a964367e-ad8b-48e3-b10f-b0e2f7f17711 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4074184040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.4074184040 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3201323581 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336571730000 ps |
| CPU time | 804.45 seconds |
| Started | May 14 01:17:19 PM PDT 24 |
| Finished | May 14 01:50:02 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-2e8fb98f-56b8-45fe-b44c-e23b08c00a25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3201323581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3201323581 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2355995980 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336898490000 ps |
| CPU time | 880.77 seconds |
| Started | May 14 01:17:14 PM PDT 24 |
| Finished | May 14 01:53:12 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-661bfb0c-07e4-4973-bd63-d23be9418665 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2355995980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2355995980 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2802919664 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336408510000 ps |
| CPU time | 928.56 seconds |
| Started | May 14 01:17:25 PM PDT 24 |
| Finished | May 14 01:55:53 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-90ecd2dc-625c-40c5-89ec-60b0b297dacb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2802919664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2802919664 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2439759651 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336993730000 ps |
| CPU time | 759.88 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:48:03 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-016a79b7-e140-4f60-9051-681f8609825b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2439759651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2439759651 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.306298388 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336326870000 ps |
| CPU time | 888.34 seconds |
| Started | May 14 01:17:29 PM PDT 24 |
| Finished | May 14 01:54:08 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-db07b80b-7d72-400b-943c-261f8d50f2e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=306298388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.306298388 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2822010334 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336975070000 ps |
| CPU time | 865.41 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:52:39 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-b2021fd4-a723-459f-b341-1788b3dbc94f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2822010334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2822010334 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4088192441 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 336912910000 ps |
| CPU time | 840.56 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:52:08 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-3dca494a-dfd8-48d2-a3ac-5e2579a54641 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4088192441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.4088192441 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.207128447 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336533630000 ps |
| CPU time | 930.04 seconds |
| Started | May 14 01:17:21 PM PDT 24 |
| Finished | May 14 01:56:24 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-e8030f29-58c5-4dfa-a61e-42fbc89ad9eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=207128447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.207128447 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3825981846 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336924210000 ps |
| CPU time | 896.48 seconds |
| Started | May 14 01:17:19 PM PDT 24 |
| Finished | May 14 01:54:50 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-ecd7d8ae-6d1e-4417-9860-11a40e28043c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3825981846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3825981846 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4107682749 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 337006950000 ps |
| CPU time | 801.01 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:49:45 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-bfff4df4-983f-4c82-9a4a-c9e88d90a841 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4107682749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4107682749 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2627858981 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336792290000 ps |
| CPU time | 1042.37 seconds |
| Started | May 14 01:17:18 PM PDT 24 |
| Finished | May 14 02:01:05 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-c82948cc-66a7-440d-9df1-f37271e8a931 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2627858981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2627858981 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1223186351 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336825850000 ps |
| CPU time | 830.03 seconds |
| Started | May 14 01:17:16 PM PDT 24 |
| Finished | May 14 01:50:44 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-ac834fb1-7127-4a05-999f-3d3a582135ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1223186351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1223186351 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2037103949 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336907530000 ps |
| CPU time | 796.72 seconds |
| Started | May 14 01:17:16 PM PDT 24 |
| Finished | May 14 01:49:22 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-2bd1191a-1920-49f6-8e78-6597802e5074 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2037103949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2037103949 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2345265988 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336805290000 ps |
| CPU time | 907.43 seconds |
| Started | May 14 01:17:25 PM PDT 24 |
| Finished | May 14 01:55:46 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-27e4ecff-1662-4602-8fcf-da570b6d56f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2345265988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2345265988 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2123975248 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336354090000 ps |
| CPU time | 1005.15 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:58:15 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-f90ce7e3-e4c3-43f2-9fa9-84f4d29f02ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2123975248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2123975248 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.350342470 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 337012950000 ps |
| CPU time | 907.48 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:56:34 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-c8ca88ce-9f61-4acf-bcb3-58ba26461a96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=350342470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.350342470 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.679073010 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336864870000 ps |
| CPU time | 847.45 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:51:51 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-cea00782-149b-48a6-83dc-07d6d4bc6fbd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=679073010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.679073010 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.282978788 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 336796130000 ps |
| CPU time | 838.32 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:51:29 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-66fc89a5-bbd1-4d44-9c00-d2c02953d8a2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=282978788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.282978788 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.744898389 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 337070010000 ps |
| CPU time | 896.76 seconds |
| Started | May 14 01:17:29 PM PDT 24 |
| Finished | May 14 01:54:34 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-2e048aa0-a616-4a5d-b75d-7ea79dba31f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=744898389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.744898389 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1769633780 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336385510000 ps |
| CPU time | 989.04 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:58:10 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-45e69090-ee12-48ef-a6cc-f079288ae498 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1769633780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1769633780 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1523514798 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336845070000 ps |
| CPU time | 983.11 seconds |
| Started | May 14 01:17:24 PM PDT 24 |
| Finished | May 14 01:58:22 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-2819fc8f-cecd-43ad-b114-8e2af6fd8f8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1523514798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1523514798 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1952995447 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336633130000 ps |
| CPU time | 856.53 seconds |
| Started | May 14 01:17:20 PM PDT 24 |
| Finished | May 14 01:52:26 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-b7c86094-6b1b-4d71-8a8f-54cd0aad347f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1952995447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1952995447 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2587481057 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336555970000 ps |
| CPU time | 877.75 seconds |
| Started | May 14 01:17:16 PM PDT 24 |
| Finished | May 14 01:53:45 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-c1b0ca57-7197-4ff3-ba88-37fc1b82b781 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2587481057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2587481057 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3015815027 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336500910000 ps |
| CPU time | 890.32 seconds |
| Started | May 14 01:17:05 PM PDT 24 |
| Finished | May 14 01:53:26 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-90c7faca-00a4-4be2-ac0f-b049e6da8e10 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3015815027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3015815027 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.328600877 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 336440090000 ps |
| CPU time | 882.24 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:52:49 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-8348b2f3-ac81-45dc-adec-80c392fb5b52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=328600877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.328600877 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3976080287 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336544730000 ps |
| CPU time | 931.91 seconds |
| Started | May 14 01:17:11 PM PDT 24 |
| Finished | May 14 01:56:18 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-94324b1b-d350-409c-b20d-7fff1334fa62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3976080287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3976080287 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2087283736 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336900550000 ps |
| CPU time | 892.59 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:53:43 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-d83db1c7-a911-4f1f-af63-9f5c8099fc41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2087283736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2087283736 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1121640669 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 337081050000 ps |
| CPU time | 846.03 seconds |
| Started | May 14 01:17:23 PM PDT 24 |
| Finished | May 14 01:52:31 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-a4b890a7-2829-4751-9d3d-ca05291c812e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1121640669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1121640669 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1856898514 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1220870000 ps |
| CPU time | 3.91 seconds |
| Started | May 14 01:17:10 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-8d06a43c-e235-4f75-8e15-4ed9d1434358 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1856898514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1856898514 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2620758857 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1503890000 ps |
| CPU time | 4.1 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 01:17:10 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-1afcb790-2c0e-498e-95dc-963ae9eb407a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2620758857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2620758857 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2149174321 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1339690000 ps |
| CPU time | 3.3 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:17:12 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-74226ca9-e55f-4838-8b25-6393c3a7e261 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2149174321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2149174321 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2501449554 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1478870000 ps |
| CPU time | 3.01 seconds |
| Started | May 14 01:17:10 PM PDT 24 |
| Finished | May 14 01:17:18 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-2cad76f4-cb6a-4d90-803a-c5513c75634f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2501449554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2501449554 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1369769802 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1451870000 ps |
| CPU time | 5.38 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 01:17:12 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-39f8c34d-2596-4776-8bab-be7f4b2a9f0e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1369769802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1369769802 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1668698153 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1508950000 ps |
| CPU time | 4.34 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 01:17:09 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-62ba07dc-4980-449d-ad1f-f52830d8272b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1668698153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1668698153 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2314561160 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1522190000 ps |
| CPU time | 3.45 seconds |
| Started | May 14 01:16:57 PM PDT 24 |
| Finished | May 14 01:17:09 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-8744c674-22c4-4dc9-a7eb-8741cf5b2e3c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2314561160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2314561160 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3835936867 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1415210000 ps |
| CPU time | 3.82 seconds |
| Started | May 14 01:16:57 PM PDT 24 |
| Finished | May 14 01:17:10 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-9ef57e2e-0526-4d49-915f-924d06907450 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3835936867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3835936867 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3554054 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1163850000 ps |
| CPU time | 2.57 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:17:09 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-26d49ad4-64af-43cb-a3b8-dd7212db9b36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3554054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3554054 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4137278395 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1283130000 ps |
| CPU time | 3.8 seconds |
| Started | May 14 01:17:08 PM PDT 24 |
| Finished | May 14 01:17:18 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-6a332e26-6492-4ce8-aaae-ceda5299086f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4137278395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4137278395 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2378266010 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1502470000 ps |
| CPU time | 3.82 seconds |
| Started | May 14 01:17:02 PM PDT 24 |
| Finished | May 14 01:17:14 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-ee5879f9-229c-4103-8485-a118e71bb4a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2378266010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2378266010 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1081918392 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1462050000 ps |
| CPU time | 4.64 seconds |
| Started | May 14 01:17:14 PM PDT 24 |
| Finished | May 14 01:17:26 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-d01bf6b2-ee77-4555-b031-1bdb2713f57d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1081918392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1081918392 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2570220312 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1472490000 ps |
| CPU time | 4.59 seconds |
| Started | May 14 01:16:56 PM PDT 24 |
| Finished | May 14 01:17:12 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-09140c67-0862-49c5-a72b-18fc81859ef4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2570220312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2570220312 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2339484997 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1578670000 ps |
| CPU time | 4.29 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:18 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-75ca19d2-b0f5-40c5-88a6-311dc142240d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2339484997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2339484997 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2170772944 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1215070000 ps |
| CPU time | 3.46 seconds |
| Started | May 14 01:17:14 PM PDT 24 |
| Finished | May 14 01:17:23 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-a7c0f2d7-2816-4b8c-9f4b-b273659993f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2170772944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2170772944 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1456315205 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1315310000 ps |
| CPU time | 4.54 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:17:16 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-415adc05-2bbf-4e0e-a187-dbc48a623888 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1456315205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1456315205 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2317758009 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1423870000 ps |
| CPU time | 5.07 seconds |
| Started | May 14 01:17:12 PM PDT 24 |
| Finished | May 14 01:17:24 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-44e5f227-6083-47c8-85eb-4816cec66a04 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2317758009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2317758009 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4063306683 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1287370000 ps |
| CPU time | 2.85 seconds |
| Started | May 14 01:17:02 PM PDT 24 |
| Finished | May 14 01:17:11 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-23ec8928-d72a-4b71-8ba7-e201736d669a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4063306683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4063306683 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3492785065 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1532530000 ps |
| CPU time | 5.63 seconds |
| Started | May 14 01:17:13 PM PDT 24 |
| Finished | May 14 01:17:26 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-70273ee7-c1ba-4eb4-99cf-dc70db02422c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3492785065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3492785065 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2183196504 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1510570000 ps |
| CPU time | 5.29 seconds |
| Started | May 14 01:17:07 PM PDT 24 |
| Finished | May 14 01:17:20 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-5fc45f36-d861-4b89-a84d-2d7b0a052051 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2183196504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2183196504 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3342059899 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1436250000 ps |
| CPU time | 3.88 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:17:25 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-ec476c06-cb0c-4b03-9e8a-cceeae8cdb61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3342059899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3342059899 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2951396681 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1336570000 ps |
| CPU time | 4.14 seconds |
| Started | May 14 01:17:05 PM PDT 24 |
| Finished | May 14 01:17:17 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-32ac3397-5237-44fc-ad51-f7b0dcc3b545 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2951396681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2951396681 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1616683674 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1400070000 ps |
| CPU time | 4.77 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-66ad394c-c785-48ef-b9ad-f62e7de0b64d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1616683674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1616683674 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2230263747 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1478890000 ps |
| CPU time | 2.81 seconds |
| Started | May 14 01:16:51 PM PDT 24 |
| Finished | May 14 01:17:00 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-017e1e15-80cb-49c6-b44b-f68665849bb0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2230263747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2230263747 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3742815665 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1554050000 ps |
| CPU time | 4.91 seconds |
| Started | May 14 01:17:05 PM PDT 24 |
| Finished | May 14 01:17:18 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-ec8afd6d-2e5d-422b-854c-5fa0fd81f2c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3742815665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3742815665 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1677827284 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1301530000 ps |
| CPU time | 4.21 seconds |
| Started | May 14 01:17:05 PM PDT 24 |
| Finished | May 14 01:17:17 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-1a744c09-2f32-439b-8abb-5c2dfa54d21c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1677827284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1677827284 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.924689851 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1611170000 ps |
| CPU time | 4.95 seconds |
| Started | May 14 01:17:13 PM PDT 24 |
| Finished | May 14 01:17:25 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-c1aea553-4c28-4ce3-bf8d-f1fe8903bdef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=924689851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.924689851 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3053394837 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1505010000 ps |
| CPU time | 4.88 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:17:17 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-3f98f225-af07-461a-bbe1-030b18ec3ea4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3053394837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3053394837 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3974203601 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1172330000 ps |
| CPU time | 4.58 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:18 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-58e74506-63a3-4256-a912-7aa13f0bcda6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3974203601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3974203601 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1823684227 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1045770000 ps |
| CPU time | 2.39 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:17:21 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-34a3fd2f-ca90-4079-9aae-56ed395b2f94 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1823684227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1823684227 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2025208608 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1403350000 ps |
| CPU time | 3.5 seconds |
| Started | May 14 01:17:02 PM PDT 24 |
| Finished | May 14 01:17:12 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-d55ed466-b8cc-4827-b3ee-7b4db533d1a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2025208608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2025208608 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.518029469 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1178150000 ps |
| CPU time | 3.57 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:16 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-d1fa52e5-64a5-45ad-ac70-860e6f047c81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=518029469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.518029469 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1000773742 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1436230000 ps |
| CPU time | 4.6 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-5199a9ce-1862-4b32-acad-5ade8ae177b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1000773742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1000773742 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.592748681 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1392230000 ps |
| CPU time | 4.49 seconds |
| Started | May 14 01:17:17 PM PDT 24 |
| Finished | May 14 01:17:29 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-b32ba5b5-cd76-4238-8580-50931fb043b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=592748681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.592748681 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3213490750 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1478030000 ps |
| CPU time | 3.18 seconds |
| Started | May 14 01:16:59 PM PDT 24 |
| Finished | May 14 01:17:10 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-eec032d3-b037-4737-b6c7-b6381a0c7022 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3213490750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3213490750 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3142415355 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1365690000 ps |
| CPU time | 4.32 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:17:27 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-bca2550b-fc60-407a-8456-48e0dfd0ac12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3142415355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3142415355 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.777688003 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1386590000 ps |
| CPU time | 3.6 seconds |
| Started | May 14 01:17:15 PM PDT 24 |
| Finished | May 14 01:17:24 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-e1f29e9b-8b7b-44fc-a0cf-b888cc4ce36f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=777688003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.777688003 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.273210522 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1270750000 ps |
| CPU time | 3.81 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:17:14 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-caaefe3c-9af3-49f0-b47a-6c74afdafd67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=273210522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.273210522 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4210991756 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1439970000 ps |
| CPU time | 2.92 seconds |
| Started | May 14 01:17:11 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-8c1c31ea-e7cf-4950-ac36-3b3057f49156 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4210991756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.4210991756 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.295375060 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1431790000 ps |
| CPU time | 3.97 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:17 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-91b4848f-5f42-440b-bd4b-b99caa7c9a41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=295375060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.295375060 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2569399792 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1243150000 ps |
| CPU time | 3.83 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:17 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-ef67fe98-aa9d-4aa5-a091-d042f0f9dd4a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2569399792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2569399792 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4225586691 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1513210000 ps |
| CPU time | 4.98 seconds |
| Started | May 14 01:17:05 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-db1bcc1d-c0d6-4026-b941-fca83be5f294 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4225586691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4225586691 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2804269251 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1430470000 ps |
| CPU time | 5.23 seconds |
| Started | May 14 01:17:06 PM PDT 24 |
| Finished | May 14 01:17:21 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-7f43a781-2f68-4aa6-b960-65c8bd153306 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2804269251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2804269251 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2388660704 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1620790000 ps |
| CPU time | 5.03 seconds |
| Started | May 14 01:17:10 PM PDT 24 |
| Finished | May 14 01:17:22 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-ae14f652-55d2-4cbc-ae2c-e3c884283289 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2388660704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2388660704 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.662144079 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1361510000 ps |
| CPU time | 3.43 seconds |
| Started | May 14 01:17:03 PM PDT 24 |
| Finished | May 14 01:17:14 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-54724e6a-39da-4921-9f06-b0a4d546ec11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=662144079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.662144079 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.313026681 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1476010000 ps |
| CPU time | 3.26 seconds |
| Started | May 14 01:16:54 PM PDT 24 |
| Finished | May 14 01:17:07 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-e30561be-0f86-401d-9ff3-dd8ad67c3d3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=313026681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.313026681 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1721960289 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1561830000 ps |
| CPU time | 4.94 seconds |
| Started | May 14 01:17:01 PM PDT 24 |
| Finished | May 14 01:17:15 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-f5471c97-fe25-4b2a-aff5-5a2b7fed30c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1721960289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1721960289 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3747654354 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1313750000 ps |
| CPU time | 4.76 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 01:17:11 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-dde019a5-54a6-4ae6-935b-96262dfe0d6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3747654354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3747654354 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2531297723 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1303150000 ps |
| CPU time | 2.55 seconds |
| Started | May 14 01:16:55 PM PDT 24 |
| Finished | May 14 01:17:06 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-64d2cf86-ea55-4011-8917-6dbfcbf5d03c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2531297723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2531297723 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2075043003 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1524250000 ps |
| CPU time | 3.16 seconds |
| Started | May 14 01:17:10 PM PDT 24 |
| Finished | May 14 01:17:19 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-38184698-f59c-4649-a2cb-7e864559b088 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2075043003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2075043003 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.145334724 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1467990000 ps |
| CPU time | 4.79 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:11 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-89b004ac-357b-4af5-bdae-181481ca7a56 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=145334724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.145334724 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4046808419 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1464050000 ps |
| CPU time | 4.67 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:10 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-d561a790-824d-4c4e-a445-3c81fd0d8d7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4046808419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4046808419 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1793328841 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1474610000 ps |
| CPU time | 4.65 seconds |
| Started | May 14 01:35:56 PM PDT 24 |
| Finished | May 14 01:36:09 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-87243b4b-f2fd-4026-ae20-c1035ae45712 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1793328841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1793328841 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.43546587 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1290390000 ps |
| CPU time | 3.71 seconds |
| Started | May 14 01:36:03 PM PDT 24 |
| Finished | May 14 01:36:12 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-502a6bdc-db1f-4a19-8196-bb79ad607f24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=43546587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.43546587 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3122322400 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1593110000 ps |
| CPU time | 5.38 seconds |
| Started | May 14 01:35:59 PM PDT 24 |
| Finished | May 14 01:36:13 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-1ff8695b-3b93-4d4f-89c8-e880320ba044 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3122322400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3122322400 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.792358350 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1409130000 ps |
| CPU time | 3.75 seconds |
| Started | May 14 01:35:58 PM PDT 24 |
| Finished | May 14 01:36:09 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-5a0b57b6-bda6-4a23-9f5c-3ce5121bf6e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=792358350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.792358350 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3503314809 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1519690000 ps |
| CPU time | 5.1 seconds |
| Started | May 14 01:35:59 PM PDT 24 |
| Finished | May 14 01:36:12 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-aa63f2d9-c928-4407-9394-546ca2d87135 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3503314809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3503314809 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.17160605 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1452010000 ps |
| CPU time | 4.2 seconds |
| Started | May 14 01:36:03 PM PDT 24 |
| Finished | May 14 01:36:13 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-2d2d7a44-349f-481e-93a3-28e00131a97a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=17160605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.17160605 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2997526532 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1381830000 ps |
| CPU time | 4.29 seconds |
| Started | May 14 01:36:07 PM PDT 24 |
| Finished | May 14 01:36:17 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-bdfd7249-2311-4cd5-9999-f497ad54045e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2997526532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2997526532 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.350900784 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1431750000 ps |
| CPU time | 4.93 seconds |
| Started | May 14 01:36:06 PM PDT 24 |
| Finished | May 14 01:36:18 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-244019fb-abc2-4ae3-a290-e30c02dd6c99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=350900784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.350900784 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2119484172 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1514570000 ps |
| CPU time | 5.31 seconds |
| Started | May 14 01:36:05 PM PDT 24 |
| Finished | May 14 01:36:17 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-c8b37866-1517-4a7b-88d9-d755b810e3a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2119484172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2119484172 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3557095590 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1476190000 ps |
| CPU time | 4.34 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:09 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-1a8b896d-9109-4d0d-9bed-96d355c98e53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3557095590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3557095590 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.380108366 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1298610000 ps |
| CPU time | 3.93 seconds |
| Started | May 14 01:36:13 PM PDT 24 |
| Finished | May 14 01:36:22 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-9e84909a-edf1-4b30-b502-98ed3c141988 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=380108366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.380108366 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1406388848 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1407890000 ps |
| CPU time | 4.74 seconds |
| Started | May 14 01:36:13 PM PDT 24 |
| Finished | May 14 01:36:24 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-e5535417-6738-4f6e-87f9-ccf7f5eb2fdc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1406388848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1406388848 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1316034922 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1452850000 ps |
| CPU time | 4.02 seconds |
| Started | May 14 01:36:18 PM PDT 24 |
| Finished | May 14 01:36:27 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-06e3d4bd-760b-4386-b197-97883863e786 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1316034922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1316034922 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1194500951 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1523130000 ps |
| CPU time | 3.91 seconds |
| Started | May 14 01:36:20 PM PDT 24 |
| Finished | May 14 01:36:31 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-352ace12-d6b2-45bb-aed4-cabff2ebb33a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1194500951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1194500951 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1475023090 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1528310000 ps |
| CPU time | 5.08 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:35 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-244fd8cc-bd86-4563-9e5d-e56f319cc811 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1475023090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1475023090 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.396671005 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1554310000 ps |
| CPU time | 5.7 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:35 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-2d865e61-81dc-4a73-b516-4c9c69d2d81e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=396671005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.396671005 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3934350621 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1395530000 ps |
| CPU time | 4.44 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:33 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-7ac3df9e-4999-4923-ad6c-99c8fab8f0de |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3934350621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3934350621 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2650718400 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1558090000 ps |
| CPU time | 4.63 seconds |
| Started | May 14 01:36:20 PM PDT 24 |
| Finished | May 14 01:36:32 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-ad8268e0-4f9d-4ff9-ba7a-dcab8bfb04e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2650718400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2650718400 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.436312828 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1363830000 ps |
| CPU time | 4.04 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:33 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-d0ca2401-feeb-498a-9b68-b423ceeed948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=436312828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.436312828 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.22709022 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1469630000 ps |
| CPU time | 5.36 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:35 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-f25c8bef-ab6a-4eb2-9555-90f6b6f16eb2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=22709022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.22709022 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.21762174 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1597210000 ps |
| CPU time | 5.03 seconds |
| Started | May 14 01:35:55 PM PDT 24 |
| Finished | May 14 01:36:10 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-4b69bef0-321f-4e32-9afa-fa6fac81d5f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=21762174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.21762174 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3176817201 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1385470000 ps |
| CPU time | 4.72 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:33 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-c4564581-fe84-4e1c-951b-7ce974951ec3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3176817201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3176817201 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2017310534 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1487930000 ps |
| CPU time | 5.11 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:34 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-bf07fff2-c2a3-46a1-b393-d156d3c3547c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2017310534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2017310534 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2089499312 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1432570000 ps |
| CPU time | 5.24 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:36 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-74757dfb-00b2-4469-a0ab-ec028ff8528e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2089499312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2089499312 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1647209842 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1188170000 ps |
| CPU time | 3.43 seconds |
| Started | May 14 01:36:20 PM PDT 24 |
| Finished | May 14 01:36:28 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-b56a45bc-9ec2-47fd-b58b-946b0ac4c320 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1647209842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1647209842 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2370962683 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1197170000 ps |
| CPU time | 4.2 seconds |
| Started | May 14 01:36:23 PM PDT 24 |
| Finished | May 14 01:36:33 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-38aa864f-48c7-4676-883c-83e03f0e0a1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2370962683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2370962683 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2916235517 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1597010000 ps |
| CPU time | 5.41 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:36 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-9091c618-5516-4ea5-a771-ae25e732f432 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2916235517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2916235517 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3450848433 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1223390000 ps |
| CPU time | 3.55 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:31 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-d07f2f75-7f27-414a-bc78-8e09884298be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3450848433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3450848433 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3150002047 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1246150000 ps |
| CPU time | 4.28 seconds |
| Started | May 14 01:36:23 PM PDT 24 |
| Finished | May 14 01:36:34 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-bd1b46ac-d0fd-4089-a998-32d9211f3447 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3150002047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3150002047 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1745022066 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1596750000 ps |
| CPU time | 5.09 seconds |
| Started | May 14 01:36:22 PM PDT 24 |
| Finished | May 14 01:36:36 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-0d6d9202-c4d7-432b-b067-04640e4c7b14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1745022066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1745022066 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.223705066 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1371910000 ps |
| CPU time | 4.5 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:34 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-3bb55d09-3696-494c-91e9-85f87c934c0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=223705066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.223705066 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.289864900 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1362350000 ps |
| CPU time | 4.67 seconds |
| Started | May 14 01:35:55 PM PDT 24 |
| Finished | May 14 01:36:08 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-64adaef9-383d-4ff8-8425-d1bb662219d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=289864900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.289864900 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2202660983 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1431930000 ps |
| CPU time | 4.76 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:34 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-f4287489-d002-48d5-af4f-b1023fc581ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2202660983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2202660983 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3886007069 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1327190000 ps |
| CPU time | 4.44 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:33 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-3ee44516-6848-4b6a-8ef3-50cf6e0dc145 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3886007069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3886007069 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2006276121 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1428030000 ps |
| CPU time | 3.83 seconds |
| Started | May 14 01:36:21 PM PDT 24 |
| Finished | May 14 01:36:32 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-0f553a30-710d-4bc5-9f24-7f5140942be2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2006276121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2006276121 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4085880583 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1325830000 ps |
| CPU time | 3.71 seconds |
| Started | May 14 01:36:33 PM PDT 24 |
| Finished | May 14 01:36:44 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-fc9cac63-c52d-42a2-a096-edd8ef81e927 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4085880583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4085880583 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.338045771 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1236610000 ps |
| CPU time | 4.18 seconds |
| Started | May 14 01:36:35 PM PDT 24 |
| Finished | May 14 01:36:47 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-b5766350-c17f-4f79-9ed5-d2060dfed629 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=338045771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.338045771 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2962524034 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1469470000 ps |
| CPU time | 4.55 seconds |
| Started | May 14 01:36:32 PM PDT 24 |
| Finished | May 14 01:36:43 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-b340029f-b3c4-4621-afdd-12f420a3dcdb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2962524034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2962524034 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3535204942 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1437470000 ps |
| CPU time | 4.7 seconds |
| Started | May 14 01:36:32 PM PDT 24 |
| Finished | May 14 01:36:44 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-72418bb3-6605-4862-a6ad-9bf3e3e3fa8e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3535204942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3535204942 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2576953189 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1526430000 ps |
| CPU time | 4.8 seconds |
| Started | May 14 01:36:32 PM PDT 24 |
| Finished | May 14 01:36:45 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-03784a13-34f0-43ef-a32c-01b2b0d2a752 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2576953189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2576953189 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2442660890 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1364890000 ps |
| CPU time | 3.63 seconds |
| Started | May 14 01:36:34 PM PDT 24 |
| Finished | May 14 01:36:44 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-8dbf23e2-4fee-46d4-bfd1-6800935507db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2442660890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2442660890 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1680241706 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1299010000 ps |
| CPU time | 4.26 seconds |
| Started | May 14 01:36:32 PM PDT 24 |
| Finished | May 14 01:36:42 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-bc06cad8-2f41-4db4-ae39-0d74d6bb8291 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1680241706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1680241706 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3099986206 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1409490000 ps |
| CPU time | 4.48 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:09 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-b7273113-5fe0-4039-99e1-f890f194a8c3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3099986206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3099986206 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3875985786 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1586910000 ps |
| CPU time | 4.88 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:11 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-870b375f-b9d7-42db-a58d-924289139c99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3875985786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3875985786 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2951299453 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1434550000 ps |
| CPU time | 4.72 seconds |
| Started | May 14 01:36:00 PM PDT 24 |
| Finished | May 14 01:36:11 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-0e9d085c-7a08-4100-8449-862cede37b0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2951299453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2951299453 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3928751416 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1596370000 ps |
| CPU time | 5.33 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:11 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-0f74dd33-4511-43f4-8f9d-689336fbccfb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3928751416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3928751416 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3767603364 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1184670000 ps |
| CPU time | 4.45 seconds |
| Started | May 14 01:35:57 PM PDT 24 |
| Finished | May 14 01:36:09 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-f78670a5-1edb-490f-b876-79bac84f6a85 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3767603364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3767603364 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |