| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3099752206 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3384324000 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.72108538 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3704781289 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1892232738 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.670782896 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.633686434 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3031641038 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1054427466 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1337196183 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3668486448 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1617896868 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3704488275 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3874627736 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2653540220 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4025507195 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2709477895 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3957022311 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.918916241 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3592423249 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4274732982 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1308272261 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3705731824 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1605325392 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1498713552 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1734945273 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2060660717 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3311908304 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.301182285 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3953716301 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1501122189 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2202326335 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2305642933 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.196986088 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1393451605 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1896543088 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.380837104 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2528067197 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2540692318 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.14979361 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2355058092 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1778531995 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2201779165 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3491345679 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1474443018 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1598750890 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3273377870 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3112137792 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1662133115 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1797230621 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1351435115 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1824701901 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.875704277 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3654981588 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.667504049 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2643120522 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1834024369 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3758910877 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.428278221 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4109946493 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2531904439 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.441099053 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2174106959 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3318131610 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3526595956 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2692888560 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.245398809 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3325756824 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3271347683 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2601798053 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1189048489 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1299099007 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4016777067 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2358719682 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4100806075 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.311684552 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2596584444 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4031407331 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.298095750 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.692124932 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.259057840 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3531289327 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3240766518 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3103581625 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2704030482 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3947462304 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1444877965 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3657352511 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3963918594 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3417116012 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2943172215 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2618510829 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.27830508 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1193874347 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2130252132 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2742811468 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3455375922 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2399250559 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.468155420 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.474002921 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.979866250 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2128463673 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3173946061 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1477213466 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.284776226 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3630141016 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3859803002 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1138783620 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.649902671 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2456220689 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1654436024 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1319502693 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1783393224 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1078697074 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1572142042 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1927494500 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.553837245 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1694378574 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3860018218 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3912364080 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2447550272 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3753559168 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3424588313 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3407800618 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3911364739 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.182608122 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.746650106 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2781142056 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2707537666 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.385038300 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3511954722 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.760823497 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1222964855 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2050383137 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2049640591 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3526812517 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3480563300 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3794514808 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.426593851 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.541466692 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.919563194 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3610077062 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1753393612 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3262593773 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.176755197 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.118572269 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1285556385 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2041531363 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3876671626 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3838560129 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3563383303 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.191557254 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.572634115 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1120041643 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.945849116 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2920214142 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3193346178 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2706626833 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2232404220 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.21085273 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.844633025 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1317097385 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.644020837 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2164439291 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4066310934 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.563023995 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2867690469 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3444060715 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4277893241 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1546046611 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1167436238 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.422738674 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3601924836 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1167120041 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3062219576 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3227755974 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.899193071 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.804381567 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1985948139 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4020250986 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.761466320 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2361403168 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3721036717 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.457959829 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.585846234 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1765589514 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.680252207 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1490705680 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2211613516 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2411683972 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.234819701 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1445023968 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2179095556 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3526921526 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4286927295 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3738276572 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3451981585 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3677357631 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3927549442 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3186609933 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3227755974 | May 19 01:18:00 PM PDT 24 | May 19 01:18:10 PM PDT 24 | 1108010000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.585846234 | May 19 01:17:57 PM PDT 24 | May 19 01:18:07 PM PDT 24 | 1482450000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3601924836 | May 19 01:17:59 PM PDT 24 | May 19 01:18:10 PM PDT 24 | 1210750000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3099752206 | May 19 01:18:01 PM PDT 24 | May 19 01:18:13 PM PDT 24 | 1575570000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1317097385 | May 19 01:18:01 PM PDT 24 | May 19 01:18:13 PM PDT 24 | 1406530000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3927549442 | May 19 01:17:55 PM PDT 24 | May 19 01:18:04 PM PDT 24 | 1209330000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.563023995 | May 19 01:18:00 PM PDT 24 | May 19 01:18:12 PM PDT 24 | 1375850000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.761466320 | May 19 01:18:08 PM PDT 24 | May 19 01:18:22 PM PDT 24 | 1550130000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2361403168 | May 19 01:18:07 PM PDT 24 | May 19 01:18:18 PM PDT 24 | 1485110000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3677357631 | May 19 01:17:53 PM PDT 24 | May 19 01:18:05 PM PDT 24 | 1563190000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2232404220 | May 19 01:18:00 PM PDT 24 | May 19 01:18:11 PM PDT 24 | 1359930000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3186609933 | May 19 01:17:59 PM PDT 24 | May 19 01:18:11 PM PDT 24 | 1577830000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4020250986 | May 19 01:18:07 PM PDT 24 | May 19 01:18:17 PM PDT 24 | 1365210000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2706626833 | May 19 01:18:00 PM PDT 24 | May 19 01:18:12 PM PDT 24 | 1542490000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3193346178 | May 19 01:18:03 PM PDT 24 | May 19 01:18:15 PM PDT 24 | 1497190000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.21085273 | May 19 01:17:59 PM PDT 24 | May 19 01:18:09 PM PDT 24 | 1508030000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.457959829 | May 19 01:18:10 PM PDT 24 | May 19 01:18:20 PM PDT 24 | 1360050000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3738276572 | May 19 01:17:56 PM PDT 24 | May 19 01:18:07 PM PDT 24 | 1314710000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1167120041 | May 19 01:17:53 PM PDT 24 | May 19 01:18:06 PM PDT 24 | 1605310000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.804381567 | May 19 01:18:07 PM PDT 24 | May 19 01:18:17 PM PDT 24 | 1409790000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.572634115 | May 19 01:17:56 PM PDT 24 | May 19 01:18:09 PM PDT 24 | 1415790000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2164439291 | May 19 01:18:01 PM PDT 24 | May 19 01:18:09 PM PDT 24 | 1240390000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1490705680 | May 19 01:18:05 PM PDT 24 | May 19 01:18:15 PM PDT 24 | 1119610000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.644020837 | May 19 01:17:54 PM PDT 24 | May 19 01:18:05 PM PDT 24 | 1459850000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1765589514 | May 19 01:18:06 PM PDT 24 | May 19 01:18:16 PM PDT 24 | 1477370000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4277893241 | May 19 01:18:02 PM PDT 24 | May 19 01:18:15 PM PDT 24 | 1441130000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4286927295 | May 19 01:18:09 PM PDT 24 | May 19 01:18:19 PM PDT 24 | 1385250000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.680252207 | May 19 01:18:04 PM PDT 24 | May 19 01:18:17 PM PDT 24 | 1538210000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.844633025 | May 19 01:18:01 PM PDT 24 | May 19 01:18:12 PM PDT 24 | 1365930000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2211613516 | May 19 01:18:07 PM PDT 24 | May 19 01:18:21 PM PDT 24 | 1586410000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.945849116 | May 19 01:18:02 PM PDT 24 | May 19 01:18:14 PM PDT 24 | 1363310000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1167436238 | May 19 01:18:01 PM PDT 24 | May 19 01:18:14 PM PDT 24 | 1309770000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4066310934 | May 19 01:18:01 PM PDT 24 | May 19 01:18:11 PM PDT 24 | 1077850000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1445023968 | May 19 01:18:06 PM PDT 24 | May 19 01:18:16 PM PDT 24 | 1540190000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1546046611 | May 19 01:18:03 PM PDT 24 | May 19 01:18:13 PM PDT 24 | 1399510000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.191557254 | May 19 01:17:54 PM PDT 24 | May 19 01:18:06 PM PDT 24 | 1510970000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1120041643 | May 19 01:17:59 PM PDT 24 | May 19 01:18:11 PM PDT 24 | 1552390000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3721036717 | May 19 01:18:06 PM PDT 24 | May 19 01:18:15 PM PDT 24 | 1284050000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3451981585 | May 19 01:17:54 PM PDT 24 | May 19 01:18:07 PM PDT 24 | 1581770000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2179095556 | May 19 01:18:08 PM PDT 24 | May 19 01:18:18 PM PDT 24 | 1480990000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3444060715 | May 19 01:18:04 PM PDT 24 | May 19 01:18:12 PM PDT 24 | 1067110000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2867690469 | May 19 01:18:02 PM PDT 24 | May 19 01:18:15 PM PDT 24 | 1509370000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2920214142 | May 19 01:18:01 PM PDT 24 | May 19 01:18:10 PM PDT 24 | 1416510000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3062219576 | May 19 01:18:02 PM PDT 24 | May 19 01:18:12 PM PDT 24 | 1422630000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.899193071 | May 19 01:18:06 PM PDT 24 | May 19 01:18:15 PM PDT 24 | 1303370000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.422738674 | May 19 01:18:00 PM PDT 24 | May 19 01:18:12 PM PDT 24 | 1502450000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3526921526 | May 19 01:18:07 PM PDT 24 | May 19 01:18:17 PM PDT 24 | 1421550000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.234819701 | May 19 01:18:06 PM PDT 24 | May 19 01:18:18 PM PDT 24 | 1549790000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2411683972 | May 19 01:18:08 PM PDT 24 | May 19 01:18:20 PM PDT 24 | 1440070000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1985948139 | May 19 01:18:05 PM PDT 24 | May 19 01:18:17 PM PDT 24 | 1434550000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1572142042 | May 19 01:17:30 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1506110000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2781142056 | May 19 01:17:32 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1471790000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2447550272 | May 19 01:17:33 PM PDT 24 | May 19 01:17:47 PM PDT 24 | 1405810000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3511954722 | May 19 01:17:33 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1421150000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3704781289 | May 19 01:17:29 PM PDT 24 | May 19 01:17:37 PM PDT 24 | 1439970000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1753393612 | May 19 01:17:39 PM PDT 24 | May 19 01:17:53 PM PDT 24 | 1491370000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1927494500 | May 19 01:17:31 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1364870000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.746650106 | May 19 01:17:33 PM PDT 24 | May 19 01:17:46 PM PDT 24 | 1438250000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3860018218 | May 19 01:17:30 PM PDT 24 | May 19 01:17:40 PM PDT 24 | 1481190000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3912364080 | May 19 01:17:31 PM PDT 24 | May 19 01:17:42 PM PDT 24 | 1503690000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1477213466 | May 19 01:17:31 PM PDT 24 | May 19 01:17:40 PM PDT 24 | 1175350000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1654436024 | May 19 01:17:29 PM PDT 24 | May 19 01:17:37 PM PDT 24 | 1391870000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2707537666 | May 19 01:17:33 PM PDT 24 | May 19 01:17:45 PM PDT 24 | 1471830000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2041531363 | May 19 01:17:33 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1430790000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3630141016 | May 19 01:17:30 PM PDT 24 | May 19 01:17:39 PM PDT 24 | 1346530000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3526812517 | May 19 01:17:28 PM PDT 24 | May 19 01:17:40 PM PDT 24 | 1403190000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1285556385 | May 19 01:17:30 PM PDT 24 | May 19 01:17:38 PM PDT 24 | 1447890000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.541466692 | May 19 01:17:33 PM PDT 24 | May 19 01:17:46 PM PDT 24 | 1419310000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3876671626 | May 19 01:17:29 PM PDT 24 | May 19 01:17:40 PM PDT 24 | 1571770000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.182608122 | May 19 01:17:32 PM PDT 24 | May 19 01:17:44 PM PDT 24 | 1487370000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3262593773 | May 19 01:17:39 PM PDT 24 | May 19 01:17:51 PM PDT 24 | 1517750000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3480563300 | May 19 01:17:33 PM PDT 24 | May 19 01:17:46 PM PDT 24 | 1540990000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1319502693 | May 19 01:17:31 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1526830000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.760823497 | May 19 01:17:32 PM PDT 24 | May 19 01:17:42 PM PDT 24 | 1539370000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.176755197 | May 19 01:17:40 PM PDT 24 | May 19 01:17:53 PM PDT 24 | 1480190000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3424588313 | May 19 01:17:32 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1459350000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.426593851 | May 19 01:17:33 PM PDT 24 | May 19 01:17:42 PM PDT 24 | 1389430000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3911364739 | May 19 01:17:31 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1285270000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3407800618 | May 19 01:17:33 PM PDT 24 | May 19 01:17:44 PM PDT 24 | 1407330000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2049640591 | May 19 01:17:33 PM PDT 24 | May 19 01:17:49 PM PDT 24 | 1552950000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.385038300 | May 19 01:17:32 PM PDT 24 | May 19 01:17:44 PM PDT 24 | 1510710000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3563383303 | May 19 01:17:29 PM PDT 24 | May 19 01:17:40 PM PDT 24 | 1555390000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1078697074 | May 19 01:17:30 PM PDT 24 | May 19 01:17:41 PM PDT 24 | 1318610000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3859803002 | May 19 01:17:31 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1495630000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.284776226 | May 19 01:17:29 PM PDT 24 | May 19 01:17:39 PM PDT 24 | 1453570000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3173946061 | May 19 01:17:28 PM PDT 24 | May 19 01:17:37 PM PDT 24 | 1498590000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.649902671 | May 19 01:17:33 PM PDT 24 | May 19 01:17:46 PM PDT 24 | 1544990000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1783393224 | May 19 01:17:29 PM PDT 24 | May 19 01:17:37 PM PDT 24 | 1378530000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1138783620 | May 19 01:17:29 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1506970000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3753559168 | May 19 01:17:33 PM PDT 24 | May 19 01:17:46 PM PDT 24 | 1267510000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1222964855 | May 19 01:17:33 PM PDT 24 | May 19 01:17:46 PM PDT 24 | 1470370000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.919563194 | May 19 01:17:32 PM PDT 24 | May 19 01:17:40 PM PDT 24 | 1442330000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.553837245 | May 19 01:17:33 PM PDT 24 | May 19 01:17:45 PM PDT 24 | 1540510000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3610077062 | May 19 01:17:33 PM PDT 24 | May 19 01:17:42 PM PDT 24 | 1399210000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.118572269 | May 19 01:17:41 PM PDT 24 | May 19 01:17:51 PM PDT 24 | 1384790000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2050383137 | May 19 01:17:33 PM PDT 24 | May 19 01:17:44 PM PDT 24 | 1271590000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3838560129 | May 19 01:17:32 PM PDT 24 | May 19 01:17:45 PM PDT 24 | 1534090000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2456220689 | May 19 01:17:31 PM PDT 24 | May 19 01:17:41 PM PDT 24 | 1468170000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1694378574 | May 19 01:17:32 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1427270000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3794514808 | May 19 01:17:32 PM PDT 24 | May 19 01:17:43 PM PDT 24 | 1556450000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3384324000 | May 19 01:17:41 PM PDT 24 | May 19 01:44:02 PM PDT 24 | 336772430000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3704488275 | May 19 01:17:43 PM PDT 24 | May 19 01:47:33 PM PDT 24 | 336629270000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.380837104 | May 19 01:17:50 PM PDT 24 | May 19 01:50:26 PM PDT 24 | 336634930000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4274732982 | May 19 01:17:44 PM PDT 24 | May 19 01:48:00 PM PDT 24 | 337048890000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1474443018 | May 19 01:17:50 PM PDT 24 | May 19 01:50:26 PM PDT 24 | 336776810000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1498713552 | May 19 01:17:43 PM PDT 24 | May 19 01:49:35 PM PDT 24 | 336838450000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1337196183 | May 19 01:17:40 PM PDT 24 | May 19 01:52:21 PM PDT 24 | 336746910000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3112137792 | May 19 01:17:54 PM PDT 24 | May 19 01:48:16 PM PDT 24 | 336493890000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4025507195 | May 19 01:17:41 PM PDT 24 | May 19 01:47:00 PM PDT 24 | 336614750000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3273377870 | May 19 01:17:50 PM PDT 24 | May 19 01:45:15 PM PDT 24 | 336451910000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1501122189 | May 19 01:17:47 PM PDT 24 | May 19 01:47:41 PM PDT 24 | 337074790000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1054427466 | May 19 01:17:41 PM PDT 24 | May 19 01:48:37 PM PDT 24 | 336472990000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3031641038 | May 19 01:17:38 PM PDT 24 | May 19 01:54:36 PM PDT 24 | 336424850000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3705731824 | May 19 01:17:43 PM PDT 24 | May 19 01:48:14 PM PDT 24 | 336961330000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3592423249 | May 19 01:17:47 PM PDT 24 | May 19 01:58:20 PM PDT 24 | 336853330000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1605325392 | May 19 01:17:46 PM PDT 24 | May 19 01:46:55 PM PDT 24 | 337078690000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2653540220 | May 19 01:17:44 PM PDT 24 | May 19 01:55:26 PM PDT 24 | 336945590000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.633686434 | May 19 01:17:41 PM PDT 24 | May 19 01:47:42 PM PDT 24 | 337103490000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2305642933 | May 19 01:17:48 PM PDT 24 | May 19 01:51:28 PM PDT 24 | 336451570000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2060660717 | May 19 01:17:39 PM PDT 24 | May 19 01:53:30 PM PDT 24 | 336847350000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1662133115 | May 19 01:17:41 PM PDT 24 | May 19 01:47:29 PM PDT 24 | 336627910000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1778531995 | May 19 01:17:51 PM PDT 24 | May 19 01:53:26 PM PDT 24 | 336826950000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2201779165 | May 19 01:17:50 PM PDT 24 | May 19 01:58:49 PM PDT 24 | 336997690000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1734945273 | May 19 01:17:46 PM PDT 24 | May 19 01:48:29 PM PDT 24 | 336357870000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1896543088 | May 19 01:17:50 PM PDT 24 | May 19 01:50:22 PM PDT 24 | 336335190000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1308272261 | May 19 01:17:46 PM PDT 24 | May 19 01:58:42 PM PDT 24 | 336800190000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3491345679 | May 19 01:17:50 PM PDT 24 | May 19 01:51:44 PM PDT 24 | 336675250000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3668486448 | May 19 01:17:38 PM PDT 24 | May 19 01:51:18 PM PDT 24 | 336932690000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1617896868 | May 19 01:17:38 PM PDT 24 | May 19 01:55:07 PM PDT 24 | 336855350000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.918916241 | May 19 01:17:44 PM PDT 24 | May 19 01:50:10 PM PDT 24 | 336799730000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1393451605 | May 19 01:17:46 PM PDT 24 | May 19 01:48:11 PM PDT 24 | 336350570000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3953716301 | May 19 01:17:44 PM PDT 24 | May 19 01:53:35 PM PDT 24 | 336396590000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.14979361 | May 19 01:17:49 PM PDT 24 | May 19 01:59:01 PM PDT 24 | 336690430000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1824701901 | May 19 01:17:40 PM PDT 24 | May 19 01:47:00 PM PDT 24 | 336525110000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2528067197 | May 19 01:17:42 PM PDT 24 | May 19 01:51:04 PM PDT 24 | 336907330000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2202326335 | May 19 01:17:44 PM PDT 24 | May 19 01:49:35 PM PDT 24 | 337065150000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1351435115 | May 19 01:17:40 PM PDT 24 | May 19 01:49:57 PM PDT 24 | 336399450000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1598750890 | May 19 01:17:50 PM PDT 24 | May 19 01:59:30 PM PDT 24 | 336910210000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2709477895 | May 19 01:17:44 PM PDT 24 | May 19 01:45:23 PM PDT 24 | 336528070000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3957022311 | May 19 01:17:47 PM PDT 24 | May 19 01:50:44 PM PDT 24 | 337024210000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3874627736 | May 19 01:17:44 PM PDT 24 | May 19 01:47:57 PM PDT 24 | 336758250000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1892232738 | May 19 01:17:39 PM PDT 24 | May 19 01:54:26 PM PDT 24 | 336672910000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2355058092 | May 19 01:17:52 PM PDT 24 | May 19 01:58:29 PM PDT 24 | 336762210000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1797230621 | May 19 01:17:40 PM PDT 24 | May 19 01:52:38 PM PDT 24 | 337019690000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.875704277 | May 19 01:17:39 PM PDT 24 | May 19 01:50:15 PM PDT 24 | 336699310000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3311908304 | May 19 01:17:44 PM PDT 24 | May 19 01:51:15 PM PDT 24 | 336515070000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.670782896 | May 19 01:17:39 PM PDT 24 | May 19 01:51:47 PM PDT 24 | 336893370000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2540692318 | May 19 01:17:50 PM PDT 24 | May 19 01:49:43 PM PDT 24 | 336726410000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.196986088 | May 19 01:17:43 PM PDT 24 | May 19 01:54:54 PM PDT 24 | 336389710000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.301182285 | May 19 01:17:45 PM PDT 24 | May 19 01:47:28 PM PDT 24 | 336475430000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.667504049 | May 19 01:25:26 PM PDT 24 | May 19 02:05:39 PM PDT 24 | 336455850000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.72108538 | May 19 01:25:22 PM PDT 24 | May 19 01:58:04 PM PDT 24 | 336344970000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3271347683 | May 19 01:25:25 PM PDT 24 | May 19 01:57:18 PM PDT 24 | 337039510000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3963918594 | May 19 01:25:26 PM PDT 24 | May 19 01:59:50 PM PDT 24 | 336934310000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2130252132 | May 19 01:25:26 PM PDT 24 | May 19 01:53:56 PM PDT 24 | 337080930000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2692888560 | May 19 01:25:21 PM PDT 24 | May 19 01:55:43 PM PDT 24 | 336471710000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2643120522 | May 19 01:25:19 PM PDT 24 | May 19 01:57:40 PM PDT 24 | 336596310000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.692124932 | May 19 01:25:27 PM PDT 24 | May 19 01:57:48 PM PDT 24 | 336488270000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3947462304 | May 19 01:25:26 PM PDT 24 | May 19 01:56:40 PM PDT 24 | 336841550000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.27830508 | May 19 01:25:26 PM PDT 24 | May 19 01:58:40 PM PDT 24 | 336970690000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3526595956 | May 19 01:25:21 PM PDT 24 | May 19 01:54:13 PM PDT 24 | 336350330000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1193874347 | May 19 01:25:28 PM PDT 24 | May 19 01:54:57 PM PDT 24 | 336759390000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2943172215 | May 19 01:25:27 PM PDT 24 | May 19 02:01:34 PM PDT 24 | 336614170000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.468155420 | May 19 01:25:21 PM PDT 24 | May 19 01:55:02 PM PDT 24 | 336686670000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1189048489 | May 19 01:25:25 PM PDT 24 | May 19 01:59:23 PM PDT 24 | 337029070000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2128463673 | May 19 01:25:21 PM PDT 24 | May 19 01:57:49 PM PDT 24 | 336474950000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.311684552 | May 19 01:25:24 PM PDT 24 | May 19 01:55:03 PM PDT 24 | 336424510000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2531904439 | May 19 01:25:22 PM PDT 24 | May 19 01:53:52 PM PDT 24 | 336922850000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3417116012 | May 19 01:25:25 PM PDT 24 | May 19 02:03:46 PM PDT 24 | 336731850000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2618510829 | May 19 01:25:27 PM PDT 24 | May 19 02:01:37 PM PDT 24 | 336720350000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1834024369 | May 19 01:25:23 PM PDT 24 | May 19 02:05:38 PM PDT 24 | 336977490000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.259057840 | May 19 01:25:26 PM PDT 24 | May 19 02:05:35 PM PDT 24 | 336315870000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4109946493 | May 19 01:25:20 PM PDT 24 | May 19 01:55:10 PM PDT 24 | 336508290000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2174106959 | May 19 01:25:25 PM PDT 24 | May 19 02:01:29 PM PDT 24 | 336859530000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4100806075 | May 19 01:25:26 PM PDT 24 | May 19 02:01:20 PM PDT 24 | 337054690000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2742811468 | May 19 01:25:35 PM PDT 24 | May 19 01:51:43 PM PDT 24 | 336687590000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3318131610 | May 19 01:25:26 PM PDT 24 | May 19 02:05:55 PM PDT 24 | 336784150000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2596584444 | May 19 01:25:28 PM PDT 24 | May 19 01:57:52 PM PDT 24 | 337096810000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3657352511 | May 19 01:25:27 PM PDT 24 | May 19 01:57:11 PM PDT 24 | 337106070000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3103581625 | May 19 01:25:28 PM PDT 24 | May 19 01:51:57 PM PDT 24 | 336773270000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.474002921 | May 19 01:25:21 PM PDT 24 | May 19 01:56:13 PM PDT 24 | 336599090000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.979866250 | May 19 01:25:22 PM PDT 24 | May 19 01:56:40 PM PDT 24 | 336939830000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.441099053 | May 19 01:25:22 PM PDT 24 | May 19 01:55:37 PM PDT 24 | 336341210000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4016777067 | May 19 01:25:26 PM PDT 24 | May 19 01:54:09 PM PDT 24 | 336531450000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.428278221 | May 19 01:25:20 PM PDT 24 | May 19 01:52:02 PM PDT 24 | 336413010000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.298095750 | May 19 01:25:28 PM PDT 24 | May 19 01:56:31 PM PDT 24 | 336577010000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3325756824 | May 19 01:25:28 PM PDT 24 | May 19 01:53:50 PM PDT 24 | 336349330000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3758910877 | May 19 01:25:25 PM PDT 24 | May 19 02:06:06 PM PDT 24 | 337120910000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3240766518 | May 19 01:25:28 PM PDT 24 | May 19 01:55:46 PM PDT 24 | 336419530000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3455375922 | May 19 01:25:31 PM PDT 24 | May 19 01:55:53 PM PDT 24 | 336725430000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2601798053 | May 19 01:25:27 PM PDT 24 | May 19 01:57:58 PM PDT 24 | 336901610000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.245398809 | May 19 01:25:25 PM PDT 24 | May 19 02:01:25 PM PDT 24 | 336836510000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4031407331 | May 19 01:25:28 PM PDT 24 | May 19 01:53:58 PM PDT 24 | 336844090000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2704030482 | May 19 01:25:25 PM PDT 24 | May 19 01:48:23 PM PDT 24 | 337027470000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3531289327 | May 19 01:25:28 PM PDT 24 | May 19 02:07:56 PM PDT 24 | 336794390000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2399250559 | May 19 01:25:26 PM PDT 24 | May 19 02:05:49 PM PDT 24 | 336600450000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1444877965 | May 19 01:25:21 PM PDT 24 | May 19 01:59:52 PM PDT 24 | 336420250000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3654981588 | May 19 01:25:26 PM PDT 24 | May 19 02:06:04 PM PDT 24 | 336920470000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1299099007 | May 19 01:25:27 PM PDT 24 | May 19 01:58:07 PM PDT 24 | 336920210000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2358719682 | May 19 01:25:28 PM PDT 24 | May 19 02:07:45 PM PDT 24 | 336815330000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3099752206 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1575570000 ps |
| CPU time | 5.47 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:13 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-ec213c6e-a99f-43e2-a218-60906682c972 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3099752206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3099752206 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3384324000 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336772430000 ps |
| CPU time | 640.34 seconds |
| Started | May 19 01:17:41 PM PDT 24 |
| Finished | May 19 01:44:02 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-a84e5b94-f560-4d50-95d0-32a792e4f273 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3384324000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3384324000 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.72108538 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336344970000 ps |
| CPU time | 811.7 seconds |
| Started | May 19 01:25:22 PM PDT 24 |
| Finished | May 19 01:58:04 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-6bad1f06-9d04-4977-a303-f604b6c13ae0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=72108538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.72108538 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3704781289 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1439970000 ps |
| CPU time | 2.98 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:37 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-d0519357-1270-4234-b7c6-dea49203f46c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3704781289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3704781289 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1892232738 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336672910000 ps |
| CPU time | 888.23 seconds |
| Started | May 19 01:17:39 PM PDT 24 |
| Finished | May 19 01:54:26 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-6e6226de-197b-4d3b-8ff1-f92d084fc194 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1892232738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1892232738 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.670782896 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336893370000 ps |
| CPU time | 837.72 seconds |
| Started | May 19 01:17:39 PM PDT 24 |
| Finished | May 19 01:51:47 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-1b447244-6bef-45a9-b07f-0149c1985641 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=670782896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.670782896 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.633686434 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 337103490000 ps |
| CPU time | 745.18 seconds |
| Started | May 19 01:17:41 PM PDT 24 |
| Finished | May 19 01:47:42 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-338e8d72-753f-46bb-bdb1-5689159fa9e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=633686434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.633686434 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3031641038 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336424850000 ps |
| CPU time | 907.19 seconds |
| Started | May 19 01:17:38 PM PDT 24 |
| Finished | May 19 01:54:36 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-304ba091-7794-4e71-b650-add0fb395bd4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3031641038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3031641038 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1054427466 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336472990000 ps |
| CPU time | 764.8 seconds |
| Started | May 19 01:17:41 PM PDT 24 |
| Finished | May 19 01:48:37 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-4b059f19-063b-43f2-8b47-c10cabc9a52e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1054427466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1054427466 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1337196183 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336746910000 ps |
| CPU time | 849.26 seconds |
| Started | May 19 01:17:40 PM PDT 24 |
| Finished | May 19 01:52:21 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-0ffa1015-466b-4413-8708-e5f979d5ebec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1337196183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1337196183 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3668486448 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336932690000 ps |
| CPU time | 830.74 seconds |
| Started | May 19 01:17:38 PM PDT 24 |
| Finished | May 19 01:51:18 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-415a9b4c-1d9d-4dfe-99fc-203bdc2281e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3668486448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3668486448 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1617896868 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336855350000 ps |
| CPU time | 921.84 seconds |
| Started | May 19 01:17:38 PM PDT 24 |
| Finished | May 19 01:55:07 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-656d9ea3-2258-4e1d-b9f6-993b938acc96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1617896868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1617896868 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3704488275 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336629270000 ps |
| CPU time | 731.22 seconds |
| Started | May 19 01:17:43 PM PDT 24 |
| Finished | May 19 01:47:33 PM PDT 24 |
| Peak memory | 160904 kb |
| Host | smart-68f98257-ab3f-41b7-9652-88c1e35cdfbf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3704488275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3704488275 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3874627736 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336758250000 ps |
| CPU time | 739.78 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:47:57 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-5ad3e292-236f-4e72-9995-a69b20f63d47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3874627736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3874627736 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2653540220 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336945590000 ps |
| CPU time | 924.01 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:55:26 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-e017a127-50c7-4a3d-96d9-68c64d8b41ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2653540220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2653540220 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4025507195 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336614750000 ps |
| CPU time | 719.21 seconds |
| Started | May 19 01:17:41 PM PDT 24 |
| Finished | May 19 01:47:00 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-ecfc562e-54e9-4875-8d12-9c5db210519e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4025507195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.4025507195 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2709477895 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336528070000 ps |
| CPU time | 672.11 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:45:23 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-db562f45-e138-45b3-986e-248d87fdadea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2709477895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2709477895 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3957022311 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 337024210000 ps |
| CPU time | 790.87 seconds |
| Started | May 19 01:17:47 PM PDT 24 |
| Finished | May 19 01:50:44 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-6ca32fe1-b842-47df-a9b8-88927f0596f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3957022311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3957022311 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.918916241 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336799730000 ps |
| CPU time | 803 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:50:10 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-e79d2268-2e8f-47a6-b3b1-9e51f399571d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=918916241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.918916241 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3592423249 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336853330000 ps |
| CPU time | 980.8 seconds |
| Started | May 19 01:17:47 PM PDT 24 |
| Finished | May 19 01:58:20 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-a3acfba7-9771-4d9b-ad6a-498629092d75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3592423249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3592423249 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4274732982 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 337048890000 ps |
| CPU time | 746.37 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:48:00 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-e51a0d02-3b49-4cba-a752-3dea0eccbe46 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4274732982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.4274732982 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1308272261 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336800190000 ps |
| CPU time | 967.29 seconds |
| Started | May 19 01:17:46 PM PDT 24 |
| Finished | May 19 01:58:42 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-c6ef8a29-a712-41c1-9b00-68c603dad8fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1308272261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1308272261 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3705731824 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336961330000 ps |
| CPU time | 752.74 seconds |
| Started | May 19 01:17:43 PM PDT 24 |
| Finished | May 19 01:48:14 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-536ce690-0645-4d8d-9b9f-271080a3b21c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3705731824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3705731824 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1605325392 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 337078690000 ps |
| CPU time | 717.89 seconds |
| Started | May 19 01:17:46 PM PDT 24 |
| Finished | May 19 01:46:55 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-98091a49-ace3-46c5-b02a-270ed5da1080 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1605325392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1605325392 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1498713552 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336838450000 ps |
| CPU time | 797.05 seconds |
| Started | May 19 01:17:43 PM PDT 24 |
| Finished | May 19 01:49:35 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-9b4ef6be-5e4f-430a-85fe-1aaffb702d5a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1498713552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1498713552 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1734945273 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336357870000 ps |
| CPU time | 743.94 seconds |
| Started | May 19 01:17:46 PM PDT 24 |
| Finished | May 19 01:48:29 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-a209c76a-764e-4a17-8821-b5f47478b78b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1734945273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1734945273 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2060660717 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336847350000 ps |
| CPU time | 876.4 seconds |
| Started | May 19 01:17:39 PM PDT 24 |
| Finished | May 19 01:53:30 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-fcdac9e4-87ec-4696-a204-0d6504902a7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2060660717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2060660717 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3311908304 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336515070000 ps |
| CPU time | 817.15 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:51:15 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-4e57de1f-792c-47cf-a121-a58b6891e2ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3311908304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3311908304 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.301182285 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336475430000 ps |
| CPU time | 726.65 seconds |
| Started | May 19 01:17:45 PM PDT 24 |
| Finished | May 19 01:47:28 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-3360a408-1b4a-417f-b0a0-746c0ceb6816 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=301182285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.301182285 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3953716301 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336396590000 ps |
| CPU time | 877.78 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:53:35 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-2abc7f2c-a6f4-47c4-b6ff-2ec71c300553 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3953716301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3953716301 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1501122189 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 337074790000 ps |
| CPU time | 739.56 seconds |
| Started | May 19 01:17:47 PM PDT 24 |
| Finished | May 19 01:47:41 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-ac998eb0-321e-4a2c-92ab-370ea85a9f77 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1501122189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1501122189 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2202326335 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 337065150000 ps |
| CPU time | 788.33 seconds |
| Started | May 19 01:17:44 PM PDT 24 |
| Finished | May 19 01:49:35 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-8622daeb-00a7-464e-a45e-644f535e38a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2202326335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2202326335 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2305642933 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336451570000 ps |
| CPU time | 809.26 seconds |
| Started | May 19 01:17:48 PM PDT 24 |
| Finished | May 19 01:51:28 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-d29da5d7-5f23-4729-aa8b-27f9fdf84353 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2305642933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2305642933 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.196986088 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336389710000 ps |
| CPU time | 899.77 seconds |
| Started | May 19 01:17:43 PM PDT 24 |
| Finished | May 19 01:54:54 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-af5688c1-5f53-4695-913c-0454b92b3cb8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=196986088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.196986088 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1393451605 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336350570000 ps |
| CPU time | 734.58 seconds |
| Started | May 19 01:17:46 PM PDT 24 |
| Finished | May 19 01:48:11 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-f2a01d59-3232-4fae-a25f-cd05aa9069f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1393451605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1393451605 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1896543088 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336335190000 ps |
| CPU time | 799.01 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:50:22 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-d5ff3ce1-c581-4a09-a569-2b597c281e3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1896543088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1896543088 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.380837104 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336634930000 ps |
| CPU time | 806.11 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:50:26 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-6de5236b-c80c-4d09-82a6-43399c0ad93d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=380837104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.380837104 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2528067197 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336907330000 ps |
| CPU time | 813.42 seconds |
| Started | May 19 01:17:42 PM PDT 24 |
| Finished | May 19 01:51:04 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-8ea4d3a6-c24c-48ad-80b1-c46001f41761 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2528067197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2528067197 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2540692318 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336726410000 ps |
| CPU time | 788.18 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:49:43 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-15baf78d-7e6b-442e-bbf0-023afcd6e4a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2540692318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2540692318 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.14979361 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336690430000 ps |
| CPU time | 1002.93 seconds |
| Started | May 19 01:17:49 PM PDT 24 |
| Finished | May 19 01:59:01 PM PDT 24 |
| Peak memory | 160920 kb |
| Host | smart-5a2d7f17-6d5a-4973-b502-bcda6af79f81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=14979361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.14979361 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2355058092 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336762210000 ps |
| CPU time | 975.97 seconds |
| Started | May 19 01:17:52 PM PDT 24 |
| Finished | May 19 01:58:29 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-19e6acca-ed22-4ab3-8bd1-e84144235043 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2355058092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2355058092 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1778531995 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336826950000 ps |
| CPU time | 868.88 seconds |
| Started | May 19 01:17:51 PM PDT 24 |
| Finished | May 19 01:53:26 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-add38c82-5021-4dc1-a50f-4e7bcf060fd6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1778531995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1778531995 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2201779165 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336997690000 ps |
| CPU time | 966.69 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:58:49 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-0910ae63-8d2d-4eb7-aa18-a854dc6a08dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2201779165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2201779165 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3491345679 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336675250000 ps |
| CPU time | 814.27 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:51:44 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-073b715e-2a1f-480e-9b78-f6f503887b14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3491345679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3491345679 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1474443018 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336776810000 ps |
| CPU time | 800.49 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:50:26 PM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-37a65d96-6b4d-46f6-8a81-2a31bea726c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1474443018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1474443018 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1598750890 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336910210000 ps |
| CPU time | 973.36 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:59:30 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-ca94a3cb-8cb0-41e1-9fbf-bc0c6d789672 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1598750890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1598750890 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3273377870 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336451910000 ps |
| CPU time | 650.57 seconds |
| Started | May 19 01:17:50 PM PDT 24 |
| Finished | May 19 01:45:15 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-d53cf88f-9385-4148-b7ba-e60876e2305b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3273377870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3273377870 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3112137792 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336493890000 ps |
| CPU time | 746.87 seconds |
| Started | May 19 01:17:54 PM PDT 24 |
| Finished | May 19 01:48:16 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-62299950-5b79-4166-9c7b-0c5c806e02dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3112137792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3112137792 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1662133115 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336627910000 ps |
| CPU time | 739.83 seconds |
| Started | May 19 01:17:41 PM PDT 24 |
| Finished | May 19 01:47:29 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-836fa521-068e-412d-a570-0cf8f4b09ca6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1662133115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1662133115 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1797230621 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 337019690000 ps |
| CPU time | 859.73 seconds |
| Started | May 19 01:17:40 PM PDT 24 |
| Finished | May 19 01:52:38 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-2bb0c21f-cdf3-4409-976b-81ff37bf04ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1797230621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1797230621 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1351435115 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336399450000 ps |
| CPU time | 794.25 seconds |
| Started | May 19 01:17:40 PM PDT 24 |
| Finished | May 19 01:49:57 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-edc1db32-7256-4e07-8dab-b3841616581d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1351435115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1351435115 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1824701901 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336525110000 ps |
| CPU time | 727.69 seconds |
| Started | May 19 01:17:40 PM PDT 24 |
| Finished | May 19 01:47:00 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-c70bd8ac-f810-4525-8607-65ed8e63aa21 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1824701901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1824701901 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.875704277 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336699310000 ps |
| CPU time | 800.81 seconds |
| Started | May 19 01:17:39 PM PDT 24 |
| Finished | May 19 01:50:15 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-1b561e82-f1df-4035-a746-33309070953f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=875704277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.875704277 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3654981588 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336920470000 ps |
| CPU time | 967.56 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 02:06:04 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-de7a14ae-ffd4-4da8-b221-f88d3e68dd8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3654981588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3654981588 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.667504049 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336455850000 ps |
| CPU time | 945.06 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 02:05:39 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-10d70ed1-e4f1-4696-842d-16e3c24d2598 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=667504049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.667504049 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2643120522 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336596310000 ps |
| CPU time | 797.92 seconds |
| Started | May 19 01:25:19 PM PDT 24 |
| Finished | May 19 01:57:40 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-941a58e1-6413-4c76-bdc3-f16257bcdb8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2643120522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2643120522 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1834024369 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336977490000 ps |
| CPU time | 978.63 seconds |
| Started | May 19 01:25:23 PM PDT 24 |
| Finished | May 19 02:05:38 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-cf084b15-f6aa-47ed-9ac8-7edfa9c5d892 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1834024369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1834024369 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3758910877 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 337120910000 ps |
| CPU time | 973.09 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 02:06:06 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-242284b2-2a71-4e53-bb88-973e1d804bdf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3758910877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3758910877 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.428278221 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336413010000 ps |
| CPU time | 641.76 seconds |
| Started | May 19 01:25:20 PM PDT 24 |
| Finished | May 19 01:52:02 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-747db4ee-3f60-4037-9818-62a7f19b043d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=428278221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.428278221 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4109946493 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336508290000 ps |
| CPU time | 732.03 seconds |
| Started | May 19 01:25:20 PM PDT 24 |
| Finished | May 19 01:55:10 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-75dc833b-607b-4495-abc9-37a15ddb3738 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4109946493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4109946493 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2531904439 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336922850000 ps |
| CPU time | 685.45 seconds |
| Started | May 19 01:25:22 PM PDT 24 |
| Finished | May 19 01:53:52 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-143f5d68-9bc5-45ae-94ca-f220f686c59a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2531904439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2531904439 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.441099053 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336341210000 ps |
| CPU time | 735.6 seconds |
| Started | May 19 01:25:22 PM PDT 24 |
| Finished | May 19 01:55:37 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-fb806870-60ab-43b3-8e02-da6793f5af04 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=441099053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.441099053 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2174106959 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336859530000 ps |
| CPU time | 882.72 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 02:01:29 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-4916cebf-400c-47d9-80d2-a5fc90684f7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2174106959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2174106959 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3318131610 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336784150000 ps |
| CPU time | 965.11 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 02:05:55 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-d8732d70-b7ba-4327-8551-ce1dc7a52c8e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3318131610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3318131610 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3526595956 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336350330000 ps |
| CPU time | 703.27 seconds |
| Started | May 19 01:25:21 PM PDT 24 |
| Finished | May 19 01:54:13 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-474c56c8-a404-4a17-9be9-23dff9509739 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3526595956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3526595956 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2692888560 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336471710000 ps |
| CPU time | 736.17 seconds |
| Started | May 19 01:25:21 PM PDT 24 |
| Finished | May 19 01:55:43 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-f560293d-ac34-4250-8c60-90e65d933bb0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2692888560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2692888560 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.245398809 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336836510000 ps |
| CPU time | 877.52 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 02:01:25 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-bdf74225-9fb4-4032-8b2e-d4f7f162af3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=245398809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.245398809 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3325756824 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336349330000 ps |
| CPU time | 692.95 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:53:50 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-27aa347f-c864-4663-a49f-1cca420f41c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3325756824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3325756824 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3271347683 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 337039510000 ps |
| CPU time | 771.22 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 01:57:18 PM PDT 24 |
| Peak memory | 160896 kb |
| Host | smart-7a117f59-fca9-498c-a139-8baf12b605b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3271347683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3271347683 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2601798053 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336901610000 ps |
| CPU time | 787.93 seconds |
| Started | May 19 01:25:27 PM PDT 24 |
| Finished | May 19 01:57:58 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-8ac282cc-1117-480a-88f7-c99da141c6d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2601798053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2601798053 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1189048489 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 337029070000 ps |
| CPU time | 826.82 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 01:59:23 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-1ccafa3c-a97a-4ce0-b548-35986abd6232 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1189048489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1189048489 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1299099007 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336920210000 ps |
| CPU time | 786.89 seconds |
| Started | May 19 01:25:27 PM PDT 24 |
| Finished | May 19 01:58:07 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-2bc74e5e-922a-41b8-9f4a-51c8d48b3224 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1299099007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1299099007 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4016777067 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336531450000 ps |
| CPU time | 702.29 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 01:54:09 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-c0626b5d-8a9e-4d7a-bbaf-09a86ade5f47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4016777067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4016777067 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2358719682 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336815330000 ps |
| CPU time | 1014.76 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 02:07:45 PM PDT 24 |
| Peak memory | 160940 kb |
| Host | smart-10b48de1-74c6-4343-9dcb-62e10a667334 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2358719682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2358719682 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4100806075 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 337054690000 ps |
| CPU time | 876.64 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 02:01:20 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-1207bb98-4f6d-4e0a-95b5-f47c085929ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4100806075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4100806075 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.311684552 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336424510000 ps |
| CPU time | 729.5 seconds |
| Started | May 19 01:25:24 PM PDT 24 |
| Finished | May 19 01:55:03 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-8707b426-9c31-4add-a5bf-888a37c04bee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=311684552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.311684552 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2596584444 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 337096810000 ps |
| CPU time | 784.17 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:57:52 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-42264c45-34d8-4a06-a598-7a2d7d59800e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2596584444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2596584444 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4031407331 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336844090000 ps |
| CPU time | 696.83 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:53:58 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-3a7ab7ab-3b06-4cb5-a962-7e57a2a27239 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4031407331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4031407331 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.298095750 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336577010000 ps |
| CPU time | 761.39 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:56:31 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-9fc7f51c-d16c-4a3f-9025-8918f95597f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=298095750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.298095750 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.692124932 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336488270000 ps |
| CPU time | 787.71 seconds |
| Started | May 19 01:25:27 PM PDT 24 |
| Finished | May 19 01:57:48 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-85645665-a213-4ef0-85a1-b98e965c0316 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=692124932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.692124932 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.259057840 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336315870000 ps |
| CPU time | 966.13 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 02:05:35 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-fa186276-88c6-439c-83d2-fa93b109ce6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=259057840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.259057840 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3531289327 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336794390000 ps |
| CPU time | 1027.87 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 02:07:56 PM PDT 24 |
| Peak memory | 160940 kb |
| Host | smart-05bd0238-7ad3-443e-8d64-75bef9a9c468 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3531289327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3531289327 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3240766518 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336419530000 ps |
| CPU time | 749.87 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:55:46 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-943de8ea-8033-4903-b821-7a6b157cd8ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3240766518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3240766518 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3103581625 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336773270000 ps |
| CPU time | 638.36 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:51:57 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-a24b3971-e612-4248-8744-edc99b57483a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3103581625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3103581625 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2704030482 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 337027470000 ps |
| CPU time | 536.5 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 01:48:23 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-202a397d-a5f2-41b1-bcaa-7a8ee15cc3f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2704030482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2704030482 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3947462304 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336841550000 ps |
| CPU time | 755.53 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 01:56:40 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-a6477b6a-cba3-4f7e-a253-3ed0b79fe1c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3947462304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3947462304 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1444877965 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336420250000 ps |
| CPU time | 832.18 seconds |
| Started | May 19 01:25:21 PM PDT 24 |
| Finished | May 19 01:59:52 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-149a4f78-cf8a-46c5-82f7-87ac60325708 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1444877965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1444877965 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3657352511 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 337106070000 ps |
| CPU time | 775.89 seconds |
| Started | May 19 01:25:27 PM PDT 24 |
| Finished | May 19 01:57:11 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-47890fcd-04df-4158-9eb8-19a3f8a062be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3657352511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3657352511 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3963918594 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336934310000 ps |
| CPU time | 837.48 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 01:59:50 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-225b0cd1-3042-4a71-9852-6ba510840331 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3963918594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3963918594 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3417116012 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336731850000 ps |
| CPU time | 905.39 seconds |
| Started | May 19 01:25:25 PM PDT 24 |
| Finished | May 19 02:03:46 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-a4d79051-1078-4b85-885f-ba60c290da70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3417116012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3417116012 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2943172215 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336614170000 ps |
| CPU time | 877.92 seconds |
| Started | May 19 01:25:27 PM PDT 24 |
| Finished | May 19 02:01:34 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-635d38ee-79b7-47b0-907c-8192a18759c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2943172215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2943172215 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2618510829 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336720350000 ps |
| CPU time | 874.84 seconds |
| Started | May 19 01:25:27 PM PDT 24 |
| Finished | May 19 02:01:37 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-77b3dfe5-bce2-49ba-9708-536538c20152 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2618510829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2618510829 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.27830508 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336970690000 ps |
| CPU time | 821.96 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 01:58:40 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-14c7ed24-832c-40a7-9f8b-6b8f3bc5706a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=27830508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.27830508 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1193874347 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336759390000 ps |
| CPU time | 721.08 seconds |
| Started | May 19 01:25:28 PM PDT 24 |
| Finished | May 19 01:54:57 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-eb263832-b7ec-4489-9a84-86130e7fe239 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1193874347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1193874347 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2130252132 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 337080930000 ps |
| CPU time | 693.83 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 01:53:56 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-3855fa0b-3594-4129-9640-f1bda5e0f6e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2130252132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2130252132 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2742811468 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336687590000 ps |
| CPU time | 622.75 seconds |
| Started | May 19 01:25:35 PM PDT 24 |
| Finished | May 19 01:51:43 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-cf8ca78b-95f4-47af-8a41-d1a25a5f80d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2742811468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2742811468 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3455375922 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336725430000 ps |
| CPU time | 739.34 seconds |
| Started | May 19 01:25:31 PM PDT 24 |
| Finished | May 19 01:55:53 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-a595bcdc-b313-4962-b179-906220f73129 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3455375922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3455375922 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2399250559 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336600450000 ps |
| CPU time | 961.9 seconds |
| Started | May 19 01:25:26 PM PDT 24 |
| Finished | May 19 02:05:49 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-fbd201c3-c250-43be-bbf5-eeba91ad4fcd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2399250559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2399250559 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.468155420 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336686670000 ps |
| CPU time | 720.56 seconds |
| Started | May 19 01:25:21 PM PDT 24 |
| Finished | May 19 01:55:02 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-f2cf8b72-28de-411b-ae77-c97bd12c129e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=468155420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.468155420 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.474002921 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336599090000 ps |
| CPU time | 755.85 seconds |
| Started | May 19 01:25:21 PM PDT 24 |
| Finished | May 19 01:56:13 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-5c60f48d-995f-488a-b88c-56b73c2b5dfd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=474002921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.474002921 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.979866250 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336939830000 ps |
| CPU time | 761.55 seconds |
| Started | May 19 01:25:22 PM PDT 24 |
| Finished | May 19 01:56:40 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-18053884-c9f9-42b6-bbc4-7e773d3098aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=979866250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.979866250 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2128463673 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336474950000 ps |
| CPU time | 790.39 seconds |
| Started | May 19 01:25:21 PM PDT 24 |
| Finished | May 19 01:57:49 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-3a74c349-c7c4-480a-9dbf-15883da68d4d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2128463673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2128463673 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3173946061 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1498590000 ps |
| CPU time | 3.58 seconds |
| Started | May 19 01:17:28 PM PDT 24 |
| Finished | May 19 01:17:37 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-3639c81a-6d1f-41a3-95bd-804a9e0a875b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3173946061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3173946061 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1477213466 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1175350000 ps |
| CPU time | 3.36 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:40 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-f42dc938-ae66-4747-9af5-47acd3011270 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1477213466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1477213466 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.284776226 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1453570000 ps |
| CPU time | 3.97 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:39 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-60d206bf-fab3-4c75-abc6-df2487c31cfe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=284776226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.284776226 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3630141016 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1346530000 ps |
| CPU time | 3.69 seconds |
| Started | May 19 01:17:30 PM PDT 24 |
| Finished | May 19 01:17:39 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-1b8d0e61-01df-49ca-bbfa-a627ef11379c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3630141016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3630141016 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3859803002 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1495630000 ps |
| CPU time | 5.18 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-e11274f4-2ab3-4421-8d2c-6b007877fcc3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3859803002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3859803002 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1138783620 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1506970000 ps |
| CPU time | 6.29 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-7e5255eb-cf24-43e5-8e38-c6c64f5df5f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1138783620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1138783620 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.649902671 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1544990000 ps |
| CPU time | 4.92 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:46 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-ae264ceb-521a-4d73-8983-d3ba7ac234d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=649902671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.649902671 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2456220689 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1468170000 ps |
| CPU time | 3.92 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:41 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-1d608ab0-1ed7-4aea-9bb9-38a361e94ba2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2456220689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2456220689 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1654436024 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1391870000 ps |
| CPU time | 3.08 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:37 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-20773537-36eb-43c7-ba91-4adfd233a142 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1654436024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1654436024 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1319502693 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1526830000 ps |
| CPU time | 5.04 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-c3c971b7-3523-410b-b9f9-f3fd15c9d7dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1319502693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1319502693 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1783393224 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1378530000 ps |
| CPU time | 2.8 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:37 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-cd0d93ed-fe4b-4ac0-b0c8-e899787bdc8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1783393224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1783393224 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1078697074 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1318610000 ps |
| CPU time | 4.9 seconds |
| Started | May 19 01:17:30 PM PDT 24 |
| Finished | May 19 01:17:41 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-a16c3924-0d52-4700-973c-09f392db9aee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1078697074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1078697074 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1572142042 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1506110000 ps |
| CPU time | 5.66 seconds |
| Started | May 19 01:17:30 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-0a9ba67d-c99c-450d-beff-fd94ae7afb11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1572142042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1572142042 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1927494500 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1364870000 ps |
| CPU time | 5.32 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164492 kb |
| Host | smart-5c516d9f-0478-49e2-bdb1-b8fd0d148b0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1927494500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1927494500 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.553837245 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1540510000 ps |
| CPU time | 4.55 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:45 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-872d2625-b92a-4f63-939d-8d497362f65f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=553837245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.553837245 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1694378574 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1427270000 ps |
| CPU time | 3.9 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-9f200de2-ad3d-44cf-a850-8d7d69e2b69d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1694378574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1694378574 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3860018218 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1481190000 ps |
| CPU time | 3.88 seconds |
| Started | May 19 01:17:30 PM PDT 24 |
| Finished | May 19 01:17:40 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-c6dd5943-ebb1-4b00-b25c-a60a114b5a59 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3860018218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3860018218 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3912364080 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1503690000 ps |
| CPU time | 4.69 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:42 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-c3ea363c-3275-472c-88b4-591bd7592f12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3912364080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3912364080 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2447550272 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1405810000 ps |
| CPU time | 5.36 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:47 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-82043b00-f867-4330-9d94-98e1be1deccc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2447550272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2447550272 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3753559168 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1267510000 ps |
| CPU time | 5.55 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:46 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-33f0412b-2088-4d48-8b1a-4a4aeb1f27b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3753559168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3753559168 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3424588313 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1459350000 ps |
| CPU time | 4.33 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-94b8ca70-a02a-451f-b860-cc8c370de120 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3424588313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3424588313 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3407800618 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1407330000 ps |
| CPU time | 4.01 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:44 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-5ef6b7af-9823-4101-8014-ea5603a947ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3407800618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3407800618 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3911364739 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1285270000 ps |
| CPU time | 5.12 seconds |
| Started | May 19 01:17:31 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164552 kb |
| Host | smart-106f3448-54eb-4ce0-98cf-27e2b3d48b09 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3911364739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3911364739 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.182608122 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1487370000 ps |
| CPU time | 4.74 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:44 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-9e75e7b9-2d96-4f28-9a23-07cd9e510222 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=182608122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.182608122 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.746650106 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1438250000 ps |
| CPU time | 4.81 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:46 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-1ec87300-ce03-4ce8-9659-ad8781d84962 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=746650106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.746650106 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2781142056 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1471790000 ps |
| CPU time | 4.47 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-0da024b1-900e-461d-bc72-085c4c9b332f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2781142056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2781142056 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2707537666 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1471830000 ps |
| CPU time | 4.47 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:45 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-8b31c50a-a1d3-4f89-80bb-44410b8b4829 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2707537666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2707537666 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.385038300 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1510710000 ps |
| CPU time | 4.62 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:44 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-5bd2ea19-5597-4a85-b46a-f096a36baa45 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=385038300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.385038300 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3511954722 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1421150000 ps |
| CPU time | 3.3 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-8d5ce49c-074a-43dc-8e7b-602759ea5bbf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3511954722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3511954722 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.760823497 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1539370000 ps |
| CPU time | 3.46 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:42 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-ef197f45-82ff-4ad1-b172-9c57ef379194 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=760823497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.760823497 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1222964855 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1470370000 ps |
| CPU time | 4.92 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:46 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-59e332a5-78a8-4fb8-91fc-cbbdc07e5d48 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1222964855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1222964855 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2050383137 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1271590000 ps |
| CPU time | 4.19 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:44 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-664722f8-8a8c-4dde-8faa-a7175a46c7fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2050383137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2050383137 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2049640591 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1552950000 ps |
| CPU time | 6.67 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:49 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-d71a616c-0e15-4d9e-af98-49c80bbf855f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2049640591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2049640591 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3526812517 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1403190000 ps |
| CPU time | 5.48 seconds |
| Started | May 19 01:17:28 PM PDT 24 |
| Finished | May 19 01:17:40 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-42ba2639-238b-4696-a2e9-cbbf553b54f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3526812517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3526812517 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3480563300 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1540990000 ps |
| CPU time | 4.79 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:46 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-5a68f8bc-1bc1-4178-ac26-16a24447e8e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3480563300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3480563300 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3794514808 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1556450000 ps |
| CPU time | 3.57 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-e1d21fd1-14e9-4a4c-9c59-424d853699e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3794514808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3794514808 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.426593851 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1389430000 ps |
| CPU time | 3.22 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:42 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-bd09d005-62b0-4653-848f-4383958dd85f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=426593851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.426593851 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.541466692 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1419310000 ps |
| CPU time | 4.8 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:46 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-b7231258-d076-4ea3-a50c-66781f5093cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=541466692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.541466692 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.919563194 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1442330000 ps |
| CPU time | 3.41 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:40 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-80a4dacf-2c31-47ea-a128-9a99e8c6e97a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=919563194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.919563194 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3610077062 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1399210000 ps |
| CPU time | 2.82 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:42 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-c0a46835-f301-4918-ba4d-524052885c6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3610077062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3610077062 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1753393612 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1491370000 ps |
| CPU time | 5.47 seconds |
| Started | May 19 01:17:39 PM PDT 24 |
| Finished | May 19 01:17:53 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-febe0f1c-bad8-4fce-8bbd-9edc2bf53e47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1753393612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1753393612 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3262593773 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1517750000 ps |
| CPU time | 4.83 seconds |
| Started | May 19 01:17:39 PM PDT 24 |
| Finished | May 19 01:17:51 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-c5d047af-dd23-433e-a15e-908ceb36f4a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3262593773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3262593773 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.176755197 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1480190000 ps |
| CPU time | 5.79 seconds |
| Started | May 19 01:17:40 PM PDT 24 |
| Finished | May 19 01:17:53 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-cfe2e975-3937-4d32-8fd0-d476ed561e65 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=176755197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.176755197 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.118572269 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1384790000 ps |
| CPU time | 3.98 seconds |
| Started | May 19 01:17:41 PM PDT 24 |
| Finished | May 19 01:17:51 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-34311e8e-e3f6-4ba2-b985-7b9f304a02dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=118572269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.118572269 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1285556385 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1447890000 ps |
| CPU time | 3.21 seconds |
| Started | May 19 01:17:30 PM PDT 24 |
| Finished | May 19 01:17:38 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-b413f3fd-a1cc-42da-99de-8f4719b38dcc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1285556385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1285556385 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2041531363 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1430790000 ps |
| CPU time | 3.88 seconds |
| Started | May 19 01:17:33 PM PDT 24 |
| Finished | May 19 01:17:43 PM PDT 24 |
| Peak memory | 165032 kb |
| Host | smart-8b055ad4-d893-49ca-b425-83a40aa0cc3f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2041531363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2041531363 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3876671626 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1571770000 ps |
| CPU time | 4.37 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:40 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-f0e5bf00-e63f-4639-9336-305837bf3f9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3876671626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3876671626 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3838560129 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1534090000 ps |
| CPU time | 4.7 seconds |
| Started | May 19 01:17:32 PM PDT 24 |
| Finished | May 19 01:17:45 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-4241b0c8-483c-4b2b-a3d9-0740c417b520 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3838560129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3838560129 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3563383303 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1555390000 ps |
| CPU time | 4.34 seconds |
| Started | May 19 01:17:29 PM PDT 24 |
| Finished | May 19 01:17:40 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-36bde413-2091-48a5-a58b-7eaffa24cbc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3563383303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3563383303 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.191557254 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1510970000 ps |
| CPU time | 5.52 seconds |
| Started | May 19 01:17:54 PM PDT 24 |
| Finished | May 19 01:18:06 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-84c4352e-b8bc-40d7-880b-5ec257e8ac0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=191557254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.191557254 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.572634115 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1415790000 ps |
| CPU time | 5.68 seconds |
| Started | May 19 01:17:56 PM PDT 24 |
| Finished | May 19 01:18:09 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-13901bcc-d73f-40bb-87fe-ff067e4ac7bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=572634115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.572634115 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1120041643 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1552390000 ps |
| CPU time | 5.22 seconds |
| Started | May 19 01:17:59 PM PDT 24 |
| Finished | May 19 01:18:11 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-941a7f83-f26c-447a-8339-228694dc36b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1120041643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1120041643 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.945849116 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1363310000 ps |
| CPU time | 5.39 seconds |
| Started | May 19 01:18:02 PM PDT 24 |
| Finished | May 19 01:18:14 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-3be81a45-d59e-4735-b86f-6a6306104286 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=945849116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.945849116 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2920214142 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1416510000 ps |
| CPU time | 3.68 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:10 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-9efcfa50-b781-403a-a7d6-a234abd6cafa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2920214142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2920214142 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3193346178 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1497190000 ps |
| CPU time | 5.28 seconds |
| Started | May 19 01:18:03 PM PDT 24 |
| Finished | May 19 01:18:15 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-fd13b4a6-2fd6-49fc-a20d-58fea6e0e7a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3193346178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3193346178 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2706626833 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1542490000 ps |
| CPU time | 4.89 seconds |
| Started | May 19 01:18:00 PM PDT 24 |
| Finished | May 19 01:18:12 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-4b30dfe3-1d72-46ae-8252-76df47165298 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2706626833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2706626833 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2232404220 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1359930000 ps |
| CPU time | 4.57 seconds |
| Started | May 19 01:18:00 PM PDT 24 |
| Finished | May 19 01:18:11 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-12cad1a0-263b-4a51-8857-9ce7820d8953 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2232404220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2232404220 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.21085273 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1508030000 ps |
| CPU time | 4.3 seconds |
| Started | May 19 01:17:59 PM PDT 24 |
| Finished | May 19 01:18:09 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-7905f899-10e2-49ba-a527-5ac592b8b77b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=21085273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.21085273 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.844633025 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1365930000 ps |
| CPU time | 4.73 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:12 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-cf160f87-fdb0-434f-b786-94eb9a87ddcc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=844633025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.844633025 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1317097385 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1406530000 ps |
| CPU time | 4.87 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:13 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-bdeaa236-9ae5-448e-8889-8312094fd10b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1317097385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1317097385 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.644020837 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1459850000 ps |
| CPU time | 4.59 seconds |
| Started | May 19 01:17:54 PM PDT 24 |
| Finished | May 19 01:18:05 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-f39e38b2-6094-48d1-822c-5bd10a6e8154 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=644020837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.644020837 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2164439291 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1240390000 ps |
| CPU time | 3.18 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:09 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-38079f17-b0c7-4b1f-b23b-33ceeba3f8e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2164439291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2164439291 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4066310934 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1077850000 ps |
| CPU time | 3.94 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:11 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-e6ae7429-2659-405c-afb4-d1802e4605d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4066310934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.4066310934 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.563023995 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1375850000 ps |
| CPU time | 4.79 seconds |
| Started | May 19 01:18:00 PM PDT 24 |
| Finished | May 19 01:18:12 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-d3b771db-eded-4798-b6db-d10dec5694dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=563023995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.563023995 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2867690469 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1509370000 ps |
| CPU time | 5.59 seconds |
| Started | May 19 01:18:02 PM PDT 24 |
| Finished | May 19 01:18:15 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-6d211335-879a-4003-9510-bb4ff757e146 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2867690469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2867690469 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3444060715 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1067110000 ps |
| CPU time | 3.54 seconds |
| Started | May 19 01:18:04 PM PDT 24 |
| Finished | May 19 01:18:12 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-18561254-733e-41b6-80c7-da0e99ead0ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3444060715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3444060715 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4277893241 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1441130000 ps |
| CPU time | 6.11 seconds |
| Started | May 19 01:18:02 PM PDT 24 |
| Finished | May 19 01:18:15 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-239569d1-f4b3-4f75-9402-7ec62fb3a7fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4277893241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4277893241 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1546046611 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1399510000 ps |
| CPU time | 4.31 seconds |
| Started | May 19 01:18:03 PM PDT 24 |
| Finished | May 19 01:18:13 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-a4e5df1d-7905-4bc2-8468-fe348f0a8d39 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1546046611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1546046611 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1167436238 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1309770000 ps |
| CPU time | 5.09 seconds |
| Started | May 19 01:18:01 PM PDT 24 |
| Finished | May 19 01:18:14 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-9676f363-57b3-4cb9-a1cd-8c24fa882fa9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1167436238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1167436238 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.422738674 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1502450000 ps |
| CPU time | 5.51 seconds |
| Started | May 19 01:18:00 PM PDT 24 |
| Finished | May 19 01:18:12 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-6a0dfad8-45be-4c7d-8bc5-3d54bd2ff621 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=422738674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.422738674 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3601924836 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1210750000 ps |
| CPU time | 4.56 seconds |
| Started | May 19 01:17:59 PM PDT 24 |
| Finished | May 19 01:18:10 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-576077fc-d7fb-48a2-bfb3-1581097a912b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3601924836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3601924836 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1167120041 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1605310000 ps |
| CPU time | 5.6 seconds |
| Started | May 19 01:17:53 PM PDT 24 |
| Finished | May 19 01:18:06 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-399f6a52-224f-4b56-bef9-121239cdca5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1167120041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1167120041 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3062219576 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1422630000 ps |
| CPU time | 4.23 seconds |
| Started | May 19 01:18:02 PM PDT 24 |
| Finished | May 19 01:18:12 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-c51b8594-e631-45ba-8473-d86d75cc0015 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3062219576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3062219576 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3227755974 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1108010000 ps |
| CPU time | 4.09 seconds |
| Started | May 19 01:18:00 PM PDT 24 |
| Finished | May 19 01:18:10 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-3770b556-8168-4086-a613-cb6f6f09312d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3227755974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3227755974 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.899193071 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1303370000 ps |
| CPU time | 3.92 seconds |
| Started | May 19 01:18:06 PM PDT 24 |
| Finished | May 19 01:18:15 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-8bea6ca5-bcb8-4834-a8f7-ed101128eca3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=899193071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.899193071 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.804381567 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1409790000 ps |
| CPU time | 4.03 seconds |
| Started | May 19 01:18:07 PM PDT 24 |
| Finished | May 19 01:18:17 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-283c25d7-efef-43f6-953e-811ec59aa08d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=804381567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.804381567 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1985948139 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1434550000 ps |
| CPU time | 4.81 seconds |
| Started | May 19 01:18:05 PM PDT 24 |
| Finished | May 19 01:18:17 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-645edcb9-1b58-48ae-82cc-09d042554dbb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1985948139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1985948139 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4020250986 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1365210000 ps |
| CPU time | 4.62 seconds |
| Started | May 19 01:18:07 PM PDT 24 |
| Finished | May 19 01:18:17 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-01a9b8ef-1ca2-452b-ab1e-a9abc05e3611 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4020250986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.4020250986 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.761466320 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1550130000 ps |
| CPU time | 5.87 seconds |
| Started | May 19 01:18:08 PM PDT 24 |
| Finished | May 19 01:18:22 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-9321383a-935e-42a9-9e25-77eaf5d75193 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=761466320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.761466320 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2361403168 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1485110000 ps |
| CPU time | 4.54 seconds |
| Started | May 19 01:18:07 PM PDT 24 |
| Finished | May 19 01:18:18 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-d95e156f-f793-4c76-8ca5-9821076943d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2361403168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2361403168 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3721036717 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1284050000 ps |
| CPU time | 3.71 seconds |
| Started | May 19 01:18:06 PM PDT 24 |
| Finished | May 19 01:18:15 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-6e145aae-1eb6-44b7-baed-b1b8d641d1e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3721036717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3721036717 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.457959829 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1360050000 ps |
| CPU time | 3.85 seconds |
| Started | May 19 01:18:10 PM PDT 24 |
| Finished | May 19 01:18:20 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-1454bbe8-9c43-4a49-80a2-ba87dcc30706 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=457959829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.457959829 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.585846234 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1482450000 ps |
| CPU time | 4.3 seconds |
| Started | May 19 01:17:57 PM PDT 24 |
| Finished | May 19 01:18:07 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-f4b53934-94c1-47eb-b17d-f9a8c15565dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=585846234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.585846234 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1765589514 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1477370000 ps |
| CPU time | 4.2 seconds |
| Started | May 19 01:18:06 PM PDT 24 |
| Finished | May 19 01:18:16 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-6dde6f67-e83a-4f0c-8022-7f2ec4793b31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1765589514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1765589514 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.680252207 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1538210000 ps |
| CPU time | 5.7 seconds |
| Started | May 19 01:18:04 PM PDT 24 |
| Finished | May 19 01:18:17 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-72b858bc-0845-4e0e-93f6-c2e1447fdf8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=680252207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.680252207 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1490705680 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1119610000 ps |
| CPU time | 4.39 seconds |
| Started | May 19 01:18:05 PM PDT 24 |
| Finished | May 19 01:18:15 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-647a7865-33bd-43fc-9280-4aa2fe9e8f15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1490705680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1490705680 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2211613516 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1586410000 ps |
| CPU time | 5.72 seconds |
| Started | May 19 01:18:07 PM PDT 24 |
| Finished | May 19 01:18:21 PM PDT 24 |
| Peak memory | 165000 kb |
| Host | smart-53706cb8-ad21-4252-9ffd-a5f5acea8916 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2211613516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2211613516 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2411683972 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1440070000 ps |
| CPU time | 5.32 seconds |
| Started | May 19 01:18:08 PM PDT 24 |
| Finished | May 19 01:18:20 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-1537d6ac-bac5-43cd-ad28-9066b9cd87b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2411683972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2411683972 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.234819701 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1549790000 ps |
| CPU time | 5.2 seconds |
| Started | May 19 01:18:06 PM PDT 24 |
| Finished | May 19 01:18:18 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-ae877fe6-4e1c-4df9-9c4e-8546d3e4cc2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=234819701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.234819701 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1445023968 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1540190000 ps |
| CPU time | 4.37 seconds |
| Started | May 19 01:18:06 PM PDT 24 |
| Finished | May 19 01:18:16 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-06d6a485-98c2-498f-92de-f7aa8ad1fc28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1445023968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1445023968 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2179095556 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1480990000 ps |
| CPU time | 4.03 seconds |
| Started | May 19 01:18:08 PM PDT 24 |
| Finished | May 19 01:18:18 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-4a0af8bb-1762-4f10-a9c6-34251dca66ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2179095556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2179095556 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3526921526 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1421550000 ps |
| CPU time | 4.48 seconds |
| Started | May 19 01:18:07 PM PDT 24 |
| Finished | May 19 01:18:17 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-94df1ccb-143e-489a-8077-e3f8682265b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3526921526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3526921526 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4286927295 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1385250000 ps |
| CPU time | 3.66 seconds |
| Started | May 19 01:18:09 PM PDT 24 |
| Finished | May 19 01:18:19 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-533028c6-9c6c-4f7c-acbb-4ff1d2a327f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4286927295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4286927295 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3738276572 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1314710000 ps |
| CPU time | 4.71 seconds |
| Started | May 19 01:17:56 PM PDT 24 |
| Finished | May 19 01:18:07 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-8c84acc1-bec5-42a0-90e3-4b5cafbde7cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3738276572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3738276572 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3451981585 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1581770000 ps |
| CPU time | 5.58 seconds |
| Started | May 19 01:17:54 PM PDT 24 |
| Finished | May 19 01:18:07 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-3b10fca4-9856-4f1a-a2a0-6cd166e3cab1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3451981585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3451981585 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3677357631 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1563190000 ps |
| CPU time | 5.2 seconds |
| Started | May 19 01:17:53 PM PDT 24 |
| Finished | May 19 01:18:05 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-32f29522-4f30-435a-8e13-9f97dcfa11d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3677357631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3677357631 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3927549442 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1209330000 ps |
| CPU time | 4.19 seconds |
| Started | May 19 01:17:55 PM PDT 24 |
| Finished | May 19 01:18:04 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-d117c390-b10f-48c1-addf-6e2f7fb8d690 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3927549442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3927549442 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3186609933 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1577830000 ps |
| CPU time | 5.6 seconds |
| Started | May 19 01:17:59 PM PDT 24 |
| Finished | May 19 01:18:11 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-bc08364a-8132-48d5-96cc-44db56273363 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3186609933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3186609933 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |