| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2681465807 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2743695151 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1317793493 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3530418090 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1644897158 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.845105018 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4270647065 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2069279627 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3277773858 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.774936438 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1163986001 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3180351250 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3657834266 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2083119178 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2021240979 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.945035425 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3005376042 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3208640917 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1029498145 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.47023703 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.163433914 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.840213836 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1821920700 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.551964892 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.405915340 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.159869369 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2554161110 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4208926113 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2168320437 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3288099596 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1867782822 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1791615675 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2523145943 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2180341489 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1815917875 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.972693439 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.243500061 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4216860699 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1085435282 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2021494800 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4220555125 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4146162057 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.688099763 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4184798386 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3301233058 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1944755438 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1059180853 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1936231659 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3334792489 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3829678647 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2727807700 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4262650231 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1626975214 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2796360426 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3874487034 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.908104232 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.301540108 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.355970514 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3681449314 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3376048390 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1025836588 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.381757264 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3971184114 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2787404068 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3959127515 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3081609790 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4051318798 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2150576492 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.108588447 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3755844090 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2545243919 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2695793858 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.89163391 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1399229620 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1477857809 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1782389393 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1465214830 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3426029854 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.279481957 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3065521356 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2624441195 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2546104017 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.281655266 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3447568487 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2604026507 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3152616776 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3097492087 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.197617797 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3690941198 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2291906565 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.802585316 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3346103939 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4021111822 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3222293534 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.17900381 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1771887925 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1034536277 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1940206 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3791582419 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2945274919 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.583286108 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.452239420 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3052346074 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1276800584 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.714697839 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4869898 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1840421710 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2769786201 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.709108734 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.395373574 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1154377425 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3608954433 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3335356807 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2413842513 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1911212554 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4005521390 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1560181790 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3149431507 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.934436322 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.903889362 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.211704751 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1962031583 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.701754043 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2367237006 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1367540689 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.711608628 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4179060552 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1305131784 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2655249089 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.470645314 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2553489521 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1231817996 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1593289050 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2605874042 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2211853888 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1585532997 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2617172739 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1313750291 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.736508761 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1020527216 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1591429140 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.339770754 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1102671303 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1751615354 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2647212658 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1143735206 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.252687005 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2752061831 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.921549260 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1419737761 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.156830494 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1906928518 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4112561764 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2140821185 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2480696486 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2447666087 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3384397659 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1120126131 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1175005099 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.135182331 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3222299006 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.178838782 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2975255486 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1567931394 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1451615999 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3661591335 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2597848753 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1697291949 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1376316566 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.303390746 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2696278976 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3793086115 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.158050703 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3396605839 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3665788274 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3570757637 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3663581633 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2553386507 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4058438015 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1519004546 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3736379225 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1953415589 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1683965257 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3930953588 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3332003923 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1316316295 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3355115849 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3285152465 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3471992915 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2156882157 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.170160309 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.534445770 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3085955293 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.260890447 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1276251278 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.710509802 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3845911836 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.837731313 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.531809556 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.562854339 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2480696486 | May 21 01:03:11 PM PDT 24 | May 21 01:03:24 PM PDT 24 | 1431470000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.260890447 | May 21 01:03:24 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 1440390000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1376316566 | May 21 01:03:17 PM PDT 24 | May 21 01:03:30 PM PDT 24 | 1277290000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1316316295 | May 21 01:03:25 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 1447730000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2975255486 | May 21 01:03:10 PM PDT 24 | May 21 01:03:21 PM PDT 24 | 1380510000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3930953588 | May 21 01:03:27 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 1542390000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1519004546 | May 21 01:03:24 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 1563790000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2681465807 | May 21 01:03:07 PM PDT 24 | May 21 01:03:18 PM PDT 24 | 1501910000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2156882157 | May 21 01:03:25 PM PDT 24 | May 21 01:03:38 PM PDT 24 | 1444450000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.303390746 | May 21 01:03:17 PM PDT 24 | May 21 01:03:27 PM PDT 24 | 1560530000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3285152465 | May 21 01:03:25 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 1426630000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2696278976 | May 21 01:03:18 PM PDT 24 | May 21 01:03:29 PM PDT 24 | 1485690000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3570757637 | May 21 01:03:17 PM PDT 24 | May 21 01:03:30 PM PDT 24 | 1499150000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1906928518 | May 21 01:03:04 PM PDT 24 | May 21 01:03:19 PM PDT 24 | 1531250000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3845911836 | May 21 01:03:14 PM PDT 24 | May 21 01:03:26 PM PDT 24 | 1543310000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3471992915 | May 21 01:03:26 PM PDT 24 | May 21 01:03:33 PM PDT 24 | 1337090000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.562854339 | May 21 01:03:10 PM PDT 24 | May 21 01:03:22 PM PDT 24 | 1420330000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1953415589 | May 21 01:03:25 PM PDT 24 | May 21 01:03:33 PM PDT 24 | 1465070000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1683965257 | May 21 01:03:25 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 1423750000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3085955293 | May 21 01:03:23 PM PDT 24 | May 21 01:03:30 PM PDT 24 | 1306970000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2553386507 | May 21 01:03:26 PM PDT 24 | May 21 01:03:37 PM PDT 24 | 1552650000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1567931394 | May 21 01:03:19 PM PDT 24 | May 21 01:03:29 PM PDT 24 | 1521110000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3332003923 | May 21 01:03:11 PM PDT 24 | May 21 01:03:25 PM PDT 24 | 1610850000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.158050703 | May 21 01:03:18 PM PDT 24 | May 21 01:03:27 PM PDT 24 | 1611290000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.531809556 | May 21 01:03:13 PM PDT 24 | May 21 01:03:23 PM PDT 24 | 1318570000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.178838782 | May 21 01:03:19 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 1307850000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2447666087 | May 21 01:03:11 PM PDT 24 | May 21 01:03:21 PM PDT 24 | 1424530000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3793086115 | May 21 01:03:18 PM PDT 24 | May 21 01:03:26 PM PDT 24 | 1291210000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.170160309 | May 21 01:03:25 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 1478570000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3384397659 | May 21 01:03:14 PM PDT 24 | May 21 01:03:26 PM PDT 24 | 1609170000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1175005099 | May 21 01:03:17 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 1548690000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1120126131 | May 21 01:03:10 PM PDT 24 | May 21 01:03:17 PM PDT 24 | 1391470000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3736379225 | May 21 01:03:26 PM PDT 24 | May 21 01:03:34 PM PDT 24 | 1412630000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.135182331 | May 21 01:03:19 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 1324450000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1697291949 | May 21 01:03:17 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 1543650000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3665788274 | May 21 01:03:17 PM PDT 24 | May 21 01:03:27 PM PDT 24 | 1420470000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4112561764 | May 21 01:03:09 PM PDT 24 | May 21 01:03:18 PM PDT 24 | 1599610000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3396605839 | May 21 01:03:11 PM PDT 24 | May 21 01:03:20 PM PDT 24 | 1326950000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3661591335 | May 21 01:03:17 PM PDT 24 | May 21 01:03:29 PM PDT 24 | 1381250000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2140821185 | May 21 01:03:10 PM PDT 24 | May 21 01:03:24 PM PDT 24 | 1427610000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2597848753 | May 21 01:03:17 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 1246110000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3355115849 | May 21 01:03:24 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 1444550000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3663581633 | May 21 01:03:26 PM PDT 24 | May 21 01:03:40 PM PDT 24 | 1531190000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.534445770 | May 21 01:03:25 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 1178570000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3222299006 | May 21 01:03:16 PM PDT 24 | May 21 01:03:28 PM PDT 24 | 1402930000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1276251278 | May 21 01:03:26 PM PDT 24 | May 21 01:03:35 PM PDT 24 | 1518810000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1451615999 | May 21 01:03:16 PM PDT 24 | May 21 01:03:25 PM PDT 24 | 1607790000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.837731313 | May 21 01:03:12 PM PDT 24 | May 21 01:03:23 PM PDT 24 | 1551470000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.710509802 | May 21 01:03:12 PM PDT 24 | May 21 01:03:23 PM PDT 24 | 1554650000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4058438015 | May 21 01:03:24 PM PDT 24 | May 21 01:03:36 PM PDT 24 | 1296930000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1313750291 | May 21 01:29:25 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1286730000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1154377425 | May 21 01:29:24 PM PDT 24 | May 21 01:29:34 PM PDT 24 | 1326330000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.395373574 | May 21 01:29:26 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1289070000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2367237006 | May 21 01:29:24 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1456770000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.701754043 | May 21 01:29:25 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1558030000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.714697839 | May 21 01:29:25 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1381250000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2752061831 | May 21 01:29:23 PM PDT 24 | May 21 01:29:32 PM PDT 24 | 1407670000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.252687005 | May 21 01:29:22 PM PDT 24 | May 21 01:29:33 PM PDT 24 | 1347170000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2605874042 | May 21 01:29:25 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1549410000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3530418090 | May 21 01:29:26 PM PDT 24 | May 21 01:29:38 PM PDT 24 | 1434910000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1591429140 | May 21 01:29:32 PM PDT 24 | May 21 01:29:44 PM PDT 24 | 1387670000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2647212658 | May 21 01:29:31 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1389550000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3149431507 | May 21 01:29:24 PM PDT 24 | May 21 01:29:35 PM PDT 24 | 1497930000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.709108734 | May 21 01:29:26 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1611550000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1962031583 | May 21 01:29:25 PM PDT 24 | May 21 01:29:38 PM PDT 24 | 1486230000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.339770754 | May 21 01:29:35 PM PDT 24 | May 21 01:29:48 PM PDT 24 | 1537430000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1020527216 | May 21 01:29:33 PM PDT 24 | May 21 01:29:46 PM PDT 24 | 1545690000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.156830494 | May 21 01:29:28 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1177930000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.736508761 | May 21 01:29:25 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1449150000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.903889362 | May 21 01:29:26 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1526450000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3052346074 | May 21 01:29:22 PM PDT 24 | May 21 01:29:35 PM PDT 24 | 1478190000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2211853888 | May 21 01:29:26 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1466730000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1143735206 | May 21 01:29:33 PM PDT 24 | May 21 01:29:46 PM PDT 24 | 1426150000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4179060552 | May 21 01:29:25 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1465350000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2655249089 | May 21 01:29:25 PM PDT 24 | May 21 01:29:38 PM PDT 24 | 1418710000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.211704751 | May 21 01:29:25 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1558890000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2553489521 | May 21 01:29:25 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1533870000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4005521390 | May 21 01:29:23 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1484550000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2617172739 | May 21 01:29:27 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1448170000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1593289050 | May 21 01:29:24 PM PDT 24 | May 21 01:29:35 PM PDT 24 | 1507910000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3335356807 | May 21 01:29:24 PM PDT 24 | May 21 01:29:33 PM PDT 24 | 1432510000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1305131784 | May 21 01:29:25 PM PDT 24 | May 21 01:29:40 PM PDT 24 | 1562970000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1585532997 | May 21 01:29:21 PM PDT 24 | May 21 01:29:30 PM PDT 24 | 1469390000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1840421710 | May 21 01:29:22 PM PDT 24 | May 21 01:29:32 PM PDT 24 | 1212430000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4869898 | May 21 01:29:25 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1417290000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1560181790 | May 21 01:29:25 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1477270000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1102671303 | May 21 01:29:33 PM PDT 24 | May 21 01:29:42 PM PDT 24 | 1185930000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1419737761 | May 21 01:29:23 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1509350000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2413842513 | May 21 01:29:25 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1394850000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.934436322 | May 21 01:29:27 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1425690000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2769786201 | May 21 01:29:24 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1412850000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1367540689 | May 21 01:29:24 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1583170000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.711608628 | May 21 01:29:25 PM PDT 24 | May 21 01:29:39 PM PDT 24 | 1413990000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1231817996 | May 21 01:29:25 PM PDT 24 | May 21 01:29:36 PM PDT 24 | 1375930000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1751615354 | May 21 01:29:35 PM PDT 24 | May 21 01:29:49 PM PDT 24 | 1384450000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3608954433 | May 21 01:29:25 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1488170000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1276800584 | May 21 01:29:25 PM PDT 24 | May 21 01:29:41 PM PDT 24 | 1522150000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1911212554 | May 21 01:29:25 PM PDT 24 | May 21 01:29:35 PM PDT 24 | 1439810000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.921549260 | May 21 01:29:23 PM PDT 24 | May 21 01:29:37 PM PDT 24 | 1522190000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.470645314 | May 21 01:29:24 PM PDT 24 | May 21 01:29:38 PM PDT 24 | 1548290000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1029498145 | May 21 01:29:31 PM PDT 24 | May 21 01:56:23 PM PDT 24 | 336800230000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2083119178 | May 21 01:29:34 PM PDT 24 | May 21 02:07:19 PM PDT 24 | 336883170000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3208640917 | May 21 01:29:34 PM PDT 24 | May 21 02:07:11 PM PDT 24 | 336417110000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2523145943 | May 21 01:29:40 PM PDT 24 | May 21 01:56:13 PM PDT 24 | 336615950000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1626975214 | May 21 01:29:33 PM PDT 24 | May 21 02:04:08 PM PDT 24 | 336433910000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3334792489 | May 21 01:29:33 PM PDT 24 | May 21 01:59:06 PM PDT 24 | 336454270000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.945035425 | May 21 01:29:35 PM PDT 24 | May 21 02:01:24 PM PDT 24 | 336427850000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1867782822 | May 21 01:29:38 PM PDT 24 | May 21 02:00:37 PM PDT 24 | 336572530000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1821920700 | May 21 01:29:37 PM PDT 24 | May 21 02:04:06 PM PDT 24 | 336565990000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2743695151 | May 21 01:29:35 PM PDT 24 | May 21 02:02:57 PM PDT 24 | 336765270000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3301233058 | May 21 01:29:36 PM PDT 24 | May 21 02:01:08 PM PDT 24 | 336369030000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2554161110 | May 21 01:29:34 PM PDT 24 | May 21 02:01:14 PM PDT 24 | 336325950000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4216860699 | May 21 01:29:33 PM PDT 24 | May 21 02:05:38 PM PDT 24 | 336600870000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4262650231 | May 21 01:29:31 PM PDT 24 | May 21 01:59:31 PM PDT 24 | 336953070000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3829678647 | May 21 01:29:33 PM PDT 24 | May 21 02:00:52 PM PDT 24 | 336992650000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4208926113 | May 21 01:29:41 PM PDT 24 | May 21 02:04:12 PM PDT 24 | 336294030000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.243500061 | May 21 01:29:35 PM PDT 24 | May 21 02:05:44 PM PDT 24 | 336580430000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.405915340 | May 21 01:29:38 PM PDT 24 | May 21 02:02:03 PM PDT 24 | 336625530000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1944755438 | May 21 01:29:38 PM PDT 24 | May 21 02:01:10 PM PDT 24 | 336595730000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4220555125 | May 21 01:29:37 PM PDT 24 | May 21 02:03:33 PM PDT 24 | 336814510000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3657834266 | May 21 01:29:36 PM PDT 24 | May 21 02:00:11 PM PDT 24 | 336688770000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.163433914 | May 21 01:29:37 PM PDT 24 | May 21 02:02:41 PM PDT 24 | 336955710000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3005376042 | May 21 01:29:34 PM PDT 24 | May 21 02:05:30 PM PDT 24 | 336576250000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1085435282 | May 21 01:29:36 PM PDT 24 | May 21 01:57:22 PM PDT 24 | 336720630000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2727807700 | May 21 01:29:35 PM PDT 24 | May 21 02:00:50 PM PDT 24 | 337061450000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2168320437 | May 21 01:29:36 PM PDT 24 | May 21 02:00:59 PM PDT 24 | 336732370000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.972693439 | May 21 01:29:39 PM PDT 24 | May 21 02:01:52 PM PDT 24 | 336510270000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.47023703 | May 21 01:29:31 PM PDT 24 | May 21 02:00:03 PM PDT 24 | 336435670000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3288099596 | May 21 01:29:41 PM PDT 24 | May 21 02:05:21 PM PDT 24 | 336685430000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1815917875 | May 21 01:29:39 PM PDT 24 | May 21 02:03:27 PM PDT 24 | 336301450000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.774936438 | May 21 01:29:31 PM PDT 24 | May 21 01:59:04 PM PDT 24 | 336401190000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2021240979 | May 21 01:29:31 PM PDT 24 | May 21 02:00:39 PM PDT 24 | 337146930000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.159869369 | May 21 01:29:40 PM PDT 24 | May 21 02:01:41 PM PDT 24 | 336986770000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4146162057 | May 21 01:29:38 PM PDT 24 | May 21 02:03:30 PM PDT 24 | 336706490000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4270647065 | May 21 01:29:33 PM PDT 24 | May 21 02:01:43 PM PDT 24 | 336438510000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.840213836 | May 21 01:29:41 PM PDT 24 | May 21 02:03:28 PM PDT 24 | 336581910000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2069279627 | May 21 01:29:34 PM PDT 24 | May 21 02:01:10 PM PDT 24 | 336411150000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.845105018 | May 21 01:29:33 PM PDT 24 | May 21 02:00:17 PM PDT 24 | 336804070000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1936231659 | May 21 01:29:38 PM PDT 24 | May 21 02:05:25 PM PDT 24 | 337090410000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4184798386 | May 21 01:29:46 PM PDT 24 | May 21 02:05:47 PM PDT 24 | 336635690000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1059180853 | May 21 01:29:38 PM PDT 24 | May 21 02:04:02 PM PDT 24 | 336843930000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3277773858 | May 21 01:29:35 PM PDT 24 | May 21 02:06:52 PM PDT 24 | 336790750000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2180341489 | May 21 01:29:50 PM PDT 24 | May 21 01:58:37 PM PDT 24 | 336765450000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.551964892 | May 21 01:29:40 PM PDT 24 | May 21 02:02:17 PM PDT 24 | 336906970000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.688099763 | May 21 01:29:37 PM PDT 24 | May 21 02:00:34 PM PDT 24 | 337109070000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1644897158 | May 21 01:29:34 PM PDT 24 | May 21 02:07:06 PM PDT 24 | 336726450000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3180351250 | May 21 01:29:35 PM PDT 24 | May 21 02:02:49 PM PDT 24 | 337098450000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1791615675 | May 21 01:29:40 PM PDT 24 | May 21 02:04:24 PM PDT 24 | 336873630000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1163986001 | May 21 01:29:32 PM PDT 24 | May 21 02:03:42 PM PDT 24 | 336597750000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2021494800 | May 21 01:29:39 PM PDT 24 | May 21 01:59:46 PM PDT 24 | 336467530000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1317793493 | May 21 01:29:43 PM PDT 24 | May 21 02:08:39 PM PDT 24 | 337006170000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2546104017 | May 21 01:29:44 PM PDT 24 | May 21 02:03:00 PM PDT 24 | 336949670000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.802585316 | May 21 01:29:45 PM PDT 24 | May 21 01:58:29 PM PDT 24 | 336751330000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2545243919 | May 21 01:29:46 PM PDT 24 | May 21 01:57:18 PM PDT 24 | 336442250000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3065521356 | May 21 01:29:52 PM PDT 24 | May 21 02:05:08 PM PDT 24 | 336692110000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3690941198 | May 21 01:29:51 PM PDT 24 | May 21 02:05:34 PM PDT 24 | 336343850000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.197617797 | May 21 01:29:44 PM PDT 24 | May 21 02:00:59 PM PDT 24 | 337004310000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2945274919 | May 21 01:29:48 PM PDT 24 | May 21 02:05:39 PM PDT 24 | 336879250000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.279481957 | May 21 01:29:49 PM PDT 24 | May 21 02:05:25 PM PDT 24 | 336760230000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.281655266 | May 21 01:29:52 PM PDT 24 | May 21 02:05:18 PM PDT 24 | 336864490000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4021111822 | May 21 01:29:45 PM PDT 24 | May 21 02:04:01 PM PDT 24 | 336973410000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.355970514 | May 21 01:29:41 PM PDT 24 | May 21 02:07:45 PM PDT 24 | 336804910000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2150576492 | May 21 01:29:42 PM PDT 24 | May 21 02:06:56 PM PDT 24 | 336633330000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2787404068 | May 21 01:29:40 PM PDT 24 | May 21 02:03:56 PM PDT 24 | 336921930000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2695793858 | May 21 01:29:45 PM PDT 24 | May 21 01:59:13 PM PDT 24 | 336443990000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.108588447 | May 21 01:29:41 PM PDT 24 | May 21 02:08:16 PM PDT 24 | 336605590000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1465214830 | May 21 01:29:44 PM PDT 24 | May 21 02:01:38 PM PDT 24 | 336636550000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3971184114 | May 21 01:29:48 PM PDT 24 | May 21 02:06:18 PM PDT 24 | 336396290000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1940206 | May 21 01:29:38 PM PDT 24 | May 21 02:01:00 PM PDT 24 | 336393270000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3222293534 | May 21 01:29:47 PM PDT 24 | May 21 02:07:49 PM PDT 24 | 336457010000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.583286108 | May 21 01:29:41 PM PDT 24 | May 21 02:05:42 PM PDT 24 | 336496370000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2796360426 | May 21 01:29:41 PM PDT 24 | May 21 02:08:03 PM PDT 24 | 336786210000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3874487034 | May 21 01:29:39 PM PDT 24 | May 21 02:00:37 PM PDT 24 | 336893010000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.89163391 | May 21 01:29:44 PM PDT 24 | May 21 02:03:26 PM PDT 24 | 336359390000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2291906565 | May 21 01:29:44 PM PDT 24 | May 21 02:02:29 PM PDT 24 | 336953110000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3081609790 | May 21 01:29:48 PM PDT 24 | May 21 02:06:12 PM PDT 24 | 336351690000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.908104232 | May 21 01:29:39 PM PDT 24 | May 21 02:01:20 PM PDT 24 | 336605170000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3755844090 | May 21 01:29:43 PM PDT 24 | May 21 02:08:54 PM PDT 24 | 336780790000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1034536277 | May 21 01:29:44 PM PDT 24 | May 21 02:03:07 PM PDT 24 | 336380550000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2624441195 | May 21 01:29:50 PM PDT 24 | May 21 02:04:44 PM PDT 24 | 336687290000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3791582419 | May 21 01:29:39 PM PDT 24 | May 21 02:03:55 PM PDT 24 | 336920270000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3447568487 | May 21 01:29:44 PM PDT 24 | May 21 01:59:58 PM PDT 24 | 336748110000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.381757264 | May 21 01:29:40 PM PDT 24 | May 21 01:58:55 PM PDT 24 | 337106090000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3346103939 | May 21 01:29:47 PM PDT 24 | May 21 02:06:44 PM PDT 24 | 336581250000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1782389393 | May 21 01:29:38 PM PDT 24 | May 21 02:04:22 PM PDT 24 | 336477030000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3152616776 | May 21 01:29:46 PM PDT 24 | May 21 02:07:07 PM PDT 24 | 336835610000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.452239420 | May 21 01:29:35 PM PDT 24 | May 21 02:00:24 PM PDT 24 | 336847650000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1771887925 | May 21 01:29:49 PM PDT 24 | May 21 02:06:41 PM PDT 24 | 336835250000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3681449314 | May 21 01:29:48 PM PDT 24 | May 21 02:05:54 PM PDT 24 | 337018330000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3426029854 | May 21 01:29:45 PM PDT 24 | May 21 01:58:47 PM PDT 24 | 336913370000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1477857809 | May 21 01:29:42 PM PDT 24 | May 21 02:00:37 PM PDT 24 | 337046670000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.301540108 | May 21 01:29:41 PM PDT 24 | May 21 02:05:13 PM PDT 24 | 337152950000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3376048390 | May 21 01:29:40 PM PDT 24 | May 21 02:01:45 PM PDT 24 | 336907270000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1025836588 | May 21 01:29:39 PM PDT 24 | May 21 02:02:47 PM PDT 24 | 336803610000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2604026507 | May 21 01:29:48 PM PDT 24 | May 21 02:05:27 PM PDT 24 | 336921750000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4051318798 | May 21 01:29:39 PM PDT 24 | May 21 01:58:08 PM PDT 24 | 337069310000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3097492087 | May 21 01:29:42 PM PDT 24 | May 21 02:08:17 PM PDT 24 | 336510310000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1399229620 | May 21 01:29:45 PM PDT 24 | May 21 02:03:36 PM PDT 24 | 336480090000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.17900381 | May 21 01:29:47 PM PDT 24 | May 21 02:06:23 PM PDT 24 | 336949130000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3959127515 | May 21 01:29:44 PM PDT 24 | May 21 02:03:03 PM PDT 24 | 336312550000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2681465807 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1501910000 ps |
| CPU time | 4.53 seconds |
| Started | May 21 01:03:07 PM PDT 24 |
| Finished | May 21 01:03:18 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-232a77a3-28c2-41de-9950-3368b70fb7b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2681465807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2681465807 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2743695151 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336765270000 ps |
| CPU time | 795.66 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:02:57 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-8430114e-76fb-4518-b8d2-20c0d21483af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2743695151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2743695151 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1317793493 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 337006170000 ps |
| CPU time | 917.14 seconds |
| Started | May 21 01:29:43 PM PDT 24 |
| Finished | May 21 02:08:39 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-b98527e5-0217-4df9-b623-9da8e2b3641f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1317793493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1317793493 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3530418090 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1434910000 ps |
| CPU time | 4.71 seconds |
| Started | May 21 01:29:26 PM PDT 24 |
| Finished | May 21 01:29:38 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-036e5b33-c9f4-4f95-9b71-18a30d52f4c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3530418090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3530418090 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1644897158 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336726450000 ps |
| CPU time | 899.84 seconds |
| Started | May 21 01:29:34 PM PDT 24 |
| Finished | May 21 02:07:06 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-52b0b51a-2f05-48d2-8342-26dcdcf3ce76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1644897158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1644897158 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.845105018 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336804070000 ps |
| CPU time | 763.85 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 02:00:17 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-48262b57-9d02-43c1-83be-fe31dbc1ebbd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=845105018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.845105018 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4270647065 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336438510000 ps |
| CPU time | 783.05 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 02:01:43 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-36a8bd5f-616e-4104-bbc4-9ad60e85d1b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4270647065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.4270647065 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2069279627 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336411150000 ps |
| CPU time | 768.48 seconds |
| Started | May 21 01:29:34 PM PDT 24 |
| Finished | May 21 02:01:10 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-da8a96dd-ae2c-4af9-9860-a9257346e18e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2069279627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2069279627 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3277773858 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336790750000 ps |
| CPU time | 902.84 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:06:52 PM PDT 24 |
| Peak memory | 160864 kb |
| Host | smart-5931e774-faf1-4892-94f3-9fad47f23339 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3277773858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3277773858 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.774936438 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336401190000 ps |
| CPU time | 716.45 seconds |
| Started | May 21 01:29:31 PM PDT 24 |
| Finished | May 21 01:59:04 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-eab2155e-7dc2-472a-8406-f601c35ddcdc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=774936438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.774936438 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1163986001 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336597750000 ps |
| CPU time | 832.26 seconds |
| Started | May 21 01:29:32 PM PDT 24 |
| Finished | May 21 02:03:42 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-db722b36-9f54-4d05-a60b-0fe7dfea0286 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1163986001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1163986001 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3180351250 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 337098450000 ps |
| CPU time | 790.52 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:02:49 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-facc2602-a366-420c-97f6-97f8dcc71677 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3180351250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3180351250 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3657834266 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336688770000 ps |
| CPU time | 755.93 seconds |
| Started | May 21 01:29:36 PM PDT 24 |
| Finished | May 21 02:00:11 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-03d907ab-4db1-4e95-8c60-1f8648a88323 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3657834266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3657834266 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2083119178 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336883170000 ps |
| CPU time | 905.75 seconds |
| Started | May 21 01:29:34 PM PDT 24 |
| Finished | May 21 02:07:19 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-b5aa87b8-e420-4d50-a116-cb4b7159141a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2083119178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2083119178 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2021240979 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 337146930000 ps |
| CPU time | 780.22 seconds |
| Started | May 21 01:29:31 PM PDT 24 |
| Finished | May 21 02:00:39 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-74028d7d-27e7-444c-a70d-9f8796d10b98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2021240979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2021240979 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.945035425 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336427850000 ps |
| CPU time | 768.74 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:01:24 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-a089f1bf-a73e-4ff8-a846-c1e0d40e91dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=945035425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.945035425 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3005376042 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336576250000 ps |
| CPU time | 865.21 seconds |
| Started | May 21 01:29:34 PM PDT 24 |
| Finished | May 21 02:05:30 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-d84a0442-99a5-4540-8793-e5a02b1aec61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3005376042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3005376042 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3208640917 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336417110000 ps |
| CPU time | 896.61 seconds |
| Started | May 21 01:29:34 PM PDT 24 |
| Finished | May 21 02:07:11 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-c51663d5-7382-4d26-85fb-9a8a46aee8ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3208640917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3208640917 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1029498145 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336800230000 ps |
| CPU time | 653.45 seconds |
| Started | May 21 01:29:31 PM PDT 24 |
| Finished | May 21 01:56:23 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-caac2a70-e585-4e25-9a66-49f6977bc3f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1029498145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1029498145 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.47023703 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336435670000 ps |
| CPU time | 749.45 seconds |
| Started | May 21 01:29:31 PM PDT 24 |
| Finished | May 21 02:00:03 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-c6bd410d-c5ac-4b3a-9ed6-8721a365db7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=47023703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.47023703 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.163433914 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336955710000 ps |
| CPU time | 790.88 seconds |
| Started | May 21 01:29:37 PM PDT 24 |
| Finished | May 21 02:02:41 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-46bed8fd-9458-45bd-9b1d-ef7a079f37be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=163433914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.163433914 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.840213836 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336581910000 ps |
| CPU time | 805.02 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:03:28 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-f19ecd2a-0ee7-4300-9b55-ba6c3415e422 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=840213836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.840213836 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1821920700 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336565990000 ps |
| CPU time | 845.97 seconds |
| Started | May 21 01:29:37 PM PDT 24 |
| Finished | May 21 02:04:06 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-d13e729b-8c41-4fea-8e1c-8d98d91e0f2f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1821920700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1821920700 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.551964892 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336906970000 ps |
| CPU time | 796.21 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 02:02:17 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-6a45e723-af15-4569-a869-79ca5e81edca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=551964892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.551964892 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.405915340 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336625530000 ps |
| CPU time | 795.44 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:02:03 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-7b587104-8878-4604-b874-85a884c5bfbb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=405915340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.405915340 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.159869369 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336986770000 ps |
| CPU time | 762.8 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 02:01:41 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-53681712-bbad-455a-8f56-2a6288248dda |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=159869369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.159869369 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2554161110 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336325950000 ps |
| CPU time | 772.9 seconds |
| Started | May 21 01:29:34 PM PDT 24 |
| Finished | May 21 02:01:14 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-726fc490-0d51-4b17-8665-2a3ad7922c76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2554161110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2554161110 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4208926113 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336294030000 ps |
| CPU time | 852 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:04:12 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-0f876590-0371-4e0a-8dce-cabc4fefde15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4208926113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4208926113 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2168320437 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336732370000 ps |
| CPU time | 764.22 seconds |
| Started | May 21 01:29:36 PM PDT 24 |
| Finished | May 21 02:00:59 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-31905783-faa0-4a52-95b8-93bc788d7e5d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2168320437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2168320437 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3288099596 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336685430000 ps |
| CPU time | 872.32 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:05:21 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-07e19e1c-d099-41dc-8504-80e2d2b1dd9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3288099596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3288099596 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1867782822 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336572530000 ps |
| CPU time | 759.32 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:00:37 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-345fca3d-e642-4985-bbd1-76784efd30bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1867782822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1867782822 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1791615675 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336873630000 ps |
| CPU time | 816.46 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 02:04:24 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-b14ce77f-0847-4e95-835e-70630ea2b23d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1791615675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1791615675 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2523145943 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336615950000 ps |
| CPU time | 644.56 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 01:56:13 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-74995b08-aa14-4a2a-bfc5-81eb2aee2e0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2523145943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2523145943 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2180341489 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336765450000 ps |
| CPU time | 700.56 seconds |
| Started | May 21 01:29:50 PM PDT 24 |
| Finished | May 21 01:58:37 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-80c589fe-cd43-437a-841f-6a0116cea016 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2180341489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2180341489 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1815917875 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336301450000 ps |
| CPU time | 792.7 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 02:03:27 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-5aa1b3d8-7d4a-4d10-b2e4-fc20cc09175c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1815917875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1815917875 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.972693439 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336510270000 ps |
| CPU time | 783.28 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 02:01:52 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-6016fe08-a149-4259-af0c-26f05ff359a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=972693439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.972693439 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.243500061 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336580430000 ps |
| CPU time | 883.35 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:05:44 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-0092fc40-c07e-460d-a84c-432dfc41a5ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=243500061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.243500061 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4216860699 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336600870000 ps |
| CPU time | 883.82 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 02:05:38 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-0d1ee05f-57b2-4351-9b1f-96da92244fa6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4216860699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4216860699 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1085435282 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336720630000 ps |
| CPU time | 683.24 seconds |
| Started | May 21 01:29:36 PM PDT 24 |
| Finished | May 21 01:57:22 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-4a1b56fb-a5d2-4aef-8006-0ff227af5c9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1085435282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1085435282 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2021494800 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336467530000 ps |
| CPU time | 728.77 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 01:59:46 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-015666b8-28e0-40be-94e6-467b5086bb7e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2021494800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2021494800 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.4220555125 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336814510000 ps |
| CPU time | 832.83 seconds |
| Started | May 21 01:29:37 PM PDT 24 |
| Finished | May 21 02:03:33 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-4df16cd9-a028-4f34-b0c7-9224d59a3b3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4220555125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.4220555125 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4146162057 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336706490000 ps |
| CPU time | 827.57 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:03:30 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-207cc51c-8fdd-4f54-ad9f-c0a9b1362dac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4146162057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.4146162057 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.688099763 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 337109070000 ps |
| CPU time | 758.98 seconds |
| Started | May 21 01:29:37 PM PDT 24 |
| Finished | May 21 02:00:34 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-b6b8fa52-7d4d-4b4c-a3a5-a9424a4b73cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=688099763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.688099763 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4184798386 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336635690000 ps |
| CPU time | 854.17 seconds |
| Started | May 21 01:29:46 PM PDT 24 |
| Finished | May 21 02:05:47 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-1cf0d499-c50c-456a-8808-6bb171ecb233 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4184798386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4184798386 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3301233058 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336369030000 ps |
| CPU time | 773.46 seconds |
| Started | May 21 01:29:36 PM PDT 24 |
| Finished | May 21 02:01:08 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-305e5cc3-11b9-478f-8a60-5ffce6d66065 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3301233058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3301233058 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1944755438 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336595730000 ps |
| CPU time | 774.8 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:01:10 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-e2eab087-f5d3-4048-9b6f-a3de17a408d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1944755438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1944755438 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1059180853 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336843930000 ps |
| CPU time | 841.67 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:04:02 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-447ecf35-65b7-4524-a4be-5911ec8512a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1059180853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1059180853 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1936231659 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 337090410000 ps |
| CPU time | 851.33 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:05:25 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-120be4a2-60ef-4a8a-a949-c90d56431985 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1936231659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1936231659 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3334792489 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336454270000 ps |
| CPU time | 717.48 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 01:59:06 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-a322a8a2-ce83-4f98-80ba-b2063c4370fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3334792489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3334792489 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3829678647 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336992650000 ps |
| CPU time | 763.75 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 02:00:52 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-8e9e2ede-c3ad-4d59-b7ba-95f2ba5bc208 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3829678647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3829678647 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2727807700 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 337061450000 ps |
| CPU time | 757.33 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:00:50 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-a2626111-21a3-4ec4-b119-20742734e7cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2727807700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2727807700 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.4262650231 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336953070000 ps |
| CPU time | 726.49 seconds |
| Started | May 21 01:29:31 PM PDT 24 |
| Finished | May 21 01:59:31 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-889818ae-ff78-4a97-ae07-ad0f9fad045f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4262650231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.4262650231 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1626975214 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336433910000 ps |
| CPU time | 854.73 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 02:04:08 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-b5e244b8-9aa6-4ea2-8183-a4331f827ef9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1626975214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1626975214 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2796360426 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336786210000 ps |
| CPU time | 912.64 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:08:03 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-6d209e88-c47b-4c2b-9a40-d02d098d77aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2796360426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2796360426 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3874487034 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336893010000 ps |
| CPU time | 738.17 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 02:00:37 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-ff2a54b7-77f4-4963-8a94-07f355ef41b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3874487034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3874487034 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.908104232 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336605170000 ps |
| CPU time | 763.43 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 02:01:20 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-f56c28cb-5330-4228-81cc-60d1ec2382a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=908104232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.908104232 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.301540108 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 337152950000 ps |
| CPU time | 863.26 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:05:13 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-c147a84e-8e98-44f2-ab21-de3b1bd53238 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=301540108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.301540108 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.355970514 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336804910000 ps |
| CPU time | 904.87 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:07:45 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-45a3496d-6cea-46b6-8c65-3d5f49e5507c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=355970514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.355970514 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3681449314 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 337018330000 ps |
| CPU time | 852.29 seconds |
| Started | May 21 01:29:48 PM PDT 24 |
| Finished | May 21 02:05:54 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-511bf0cc-9c2a-4166-a55b-c95884343db3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3681449314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3681449314 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3376048390 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336907270000 ps |
| CPU time | 777.93 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 02:01:45 PM PDT 24 |
| Peak memory | 160856 kb |
| Host | smart-594922e4-cb3c-4e31-9512-4790afee1f2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3376048390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3376048390 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1025836588 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336803610000 ps |
| CPU time | 808.05 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 02:02:47 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-00c1eb7f-bec9-4b6b-af79-e3929ad4894d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1025836588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1025836588 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.381757264 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 337106090000 ps |
| CPU time | 711.16 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 01:58:55 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-cd1650c2-89a3-49b0-98e0-df2db5329896 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=381757264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.381757264 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3971184114 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336396290000 ps |
| CPU time | 864.48 seconds |
| Started | May 21 01:29:48 PM PDT 24 |
| Finished | May 21 02:06:18 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-332252e1-cba6-49a9-8f2b-4c800a114e77 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3971184114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3971184114 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2787404068 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336921930000 ps |
| CPU time | 807.78 seconds |
| Started | May 21 01:29:40 PM PDT 24 |
| Finished | May 21 02:03:56 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-1cc94c2e-dcf7-453a-bbe8-b9235bc00d55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2787404068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2787404068 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3959127515 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336312550000 ps |
| CPU time | 808.37 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:03:03 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-6eee7b7f-940a-46f7-bd2f-0a21f1a395d2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3959127515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3959127515 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3081609790 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336351690000 ps |
| CPU time | 860.16 seconds |
| Started | May 21 01:29:48 PM PDT 24 |
| Finished | May 21 02:06:12 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-5a19229b-088f-4019-94f4-88c4dd4b3c0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3081609790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3081609790 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4051318798 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 337069310000 ps |
| CPU time | 698.96 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 01:58:08 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-d6c77fab-f264-4cbb-92db-0011994e8490 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4051318798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4051318798 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2150576492 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336633330000 ps |
| CPU time | 896.84 seconds |
| Started | May 21 01:29:42 PM PDT 24 |
| Finished | May 21 02:06:56 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-cc331861-3f4f-44b6-9e0d-814a91b7004b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2150576492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2150576492 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.108588447 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336605590000 ps |
| CPU time | 917.95 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:08:16 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-58e0487f-d895-4ccb-858a-46ad84c22edf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=108588447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.108588447 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3755844090 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336780790000 ps |
| CPU time | 927.3 seconds |
| Started | May 21 01:29:43 PM PDT 24 |
| Finished | May 21 02:08:54 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-9c1f2f95-90e5-4f87-97aa-46e8153f4055 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3755844090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3755844090 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2545243919 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336442250000 ps |
| CPU time | 668.87 seconds |
| Started | May 21 01:29:46 PM PDT 24 |
| Finished | May 21 01:57:18 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-fd5c7661-3b6c-4c4a-b36a-855e31f52d1e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2545243919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2545243919 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2695793858 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336443990000 ps |
| CPU time | 712.84 seconds |
| Started | May 21 01:29:45 PM PDT 24 |
| Finished | May 21 01:59:13 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-179b95af-8293-4ccf-8202-a36a9917229f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2695793858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2695793858 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.89163391 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336359390000 ps |
| CPU time | 817 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:03:26 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-d3cd4ac5-a71c-414d-a488-46af8fedb357 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=89163391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.89163391 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1399229620 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336480090000 ps |
| CPU time | 830.14 seconds |
| Started | May 21 01:29:45 PM PDT 24 |
| Finished | May 21 02:03:36 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-61dc8dfe-ac04-46e0-b76f-447dabd2c440 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1399229620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1399229620 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1477857809 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 337046670000 ps |
| CPU time | 760.79 seconds |
| Started | May 21 01:29:42 PM PDT 24 |
| Finished | May 21 02:00:37 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-070b2f29-6aa1-4b3e-909c-3549056c3a14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1477857809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1477857809 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1782389393 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336477030000 ps |
| CPU time | 817.06 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:04:22 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-fdce1b53-ea67-4835-a95f-641e3faf0361 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1782389393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1782389393 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1465214830 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336636550000 ps |
| CPU time | 768.08 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:01:38 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-26a22c8d-b7b3-435a-99fa-559d7e2872f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1465214830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1465214830 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3426029854 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336913370000 ps |
| CPU time | 705.07 seconds |
| Started | May 21 01:29:45 PM PDT 24 |
| Finished | May 21 01:58:47 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-0bd11065-4411-4cb6-9578-c6f7f845f2ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3426029854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3426029854 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.279481957 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336760230000 ps |
| CPU time | 847.12 seconds |
| Started | May 21 01:29:49 PM PDT 24 |
| Finished | May 21 02:05:25 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-9b891c78-9823-4018-8107-587ce5b78d37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=279481957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.279481957 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3065521356 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336692110000 ps |
| CPU time | 847.12 seconds |
| Started | May 21 01:29:52 PM PDT 24 |
| Finished | May 21 02:05:08 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-01d98290-1a06-44d2-ab63-52a1a0a6b47c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3065521356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3065521356 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2624441195 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336687290000 ps |
| CPU time | 822.96 seconds |
| Started | May 21 01:29:50 PM PDT 24 |
| Finished | May 21 02:04:44 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-cac0ad54-3fd6-4e0c-b079-48d75a22367e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2624441195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2624441195 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2546104017 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336949670000 ps |
| CPU time | 814.3 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:03:00 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-65b80ee8-a80b-4bb1-8c7c-6d9d8b3a2c7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2546104017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2546104017 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.281655266 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336864490000 ps |
| CPU time | 849.17 seconds |
| Started | May 21 01:29:52 PM PDT 24 |
| Finished | May 21 02:05:18 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-05b4947d-ef48-4bc8-94e5-cb7e7054f83c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=281655266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.281655266 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3447568487 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336748110000 ps |
| CPU time | 745.31 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 01:59:58 PM PDT 24 |
| Peak memory | 160856 kb |
| Host | smart-95ed9712-e9ea-4d74-a79e-809ce765720a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3447568487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3447568487 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2604026507 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336921750000 ps |
| CPU time | 844.46 seconds |
| Started | May 21 01:29:48 PM PDT 24 |
| Finished | May 21 02:05:27 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-ea759273-0d31-4e5e-a084-6a4e70f7b8bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2604026507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2604026507 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3152616776 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336835610000 ps |
| CPU time | 898.47 seconds |
| Started | May 21 01:29:46 PM PDT 24 |
| Finished | May 21 02:07:07 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-8e88bf98-aaf3-4253-baca-e21fc6f9390b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3152616776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3152616776 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3097492087 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336510310000 ps |
| CPU time | 914.27 seconds |
| Started | May 21 01:29:42 PM PDT 24 |
| Finished | May 21 02:08:17 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-a82dad84-68e6-459c-bb31-a9a531c250e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3097492087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3097492087 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.197617797 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 337004310000 ps |
| CPU time | 742.91 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:00:59 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-0d8069e0-0525-4ab3-b279-38e94f3742be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=197617797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.197617797 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3690941198 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336343850000 ps |
| CPU time | 861.15 seconds |
| Started | May 21 01:29:51 PM PDT 24 |
| Finished | May 21 02:05:34 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-c79695fb-6cc7-4fad-9b7a-1eca0cd4e8a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3690941198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3690941198 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2291906565 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336953110000 ps |
| CPU time | 806.56 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:02:29 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-0c14f8a7-2b60-467b-ab86-6226790b710e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2291906565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2291906565 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.802585316 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336751330000 ps |
| CPU time | 698.85 seconds |
| Started | May 21 01:29:45 PM PDT 24 |
| Finished | May 21 01:58:29 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-70823b38-e191-409f-addc-5c4fded5c84b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=802585316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.802585316 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3346103939 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336581250000 ps |
| CPU time | 879.08 seconds |
| Started | May 21 01:29:47 PM PDT 24 |
| Finished | May 21 02:06:44 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-dfca1ca1-36df-4212-943a-319983956220 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3346103939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3346103939 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.4021111822 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336973410000 ps |
| CPU time | 805.91 seconds |
| Started | May 21 01:29:45 PM PDT 24 |
| Finished | May 21 02:04:01 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-426af5a7-b942-4485-9a35-a89b1e33f100 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4021111822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.4021111822 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3222293534 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336457010000 ps |
| CPU time | 907.3 seconds |
| Started | May 21 01:29:47 PM PDT 24 |
| Finished | May 21 02:07:49 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-caf560b8-404f-455b-ac8c-a43baa210297 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3222293534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3222293534 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.17900381 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336949130000 ps |
| CPU time | 867.37 seconds |
| Started | May 21 01:29:47 PM PDT 24 |
| Finished | May 21 02:06:23 PM PDT 24 |
| Peak memory | 160652 kb |
| Host | smart-17c323f7-5a25-42f5-a292-4bbb3e0893da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=17900381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.17900381 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1771887925 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336835250000 ps |
| CPU time | 880.5 seconds |
| Started | May 21 01:29:49 PM PDT 24 |
| Finished | May 21 02:06:41 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-ca0cbcd1-caee-4626-b2ad-b55bde58fcd3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1771887925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1771887925 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1034536277 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336380550000 ps |
| CPU time | 812.84 seconds |
| Started | May 21 01:29:44 PM PDT 24 |
| Finished | May 21 02:03:07 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-c94c677e-dfca-4c40-a5f9-3297ebc3c6ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1034536277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1034536277 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1940206 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336393270000 ps |
| CPU time | 754.15 seconds |
| Started | May 21 01:29:38 PM PDT 24 |
| Finished | May 21 02:01:00 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-43bb47fc-f3b4-4205-970f-bcd36b202263 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1940206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1940206 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3791582419 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336920270000 ps |
| CPU time | 802.12 seconds |
| Started | May 21 01:29:39 PM PDT 24 |
| Finished | May 21 02:03:55 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-4987c842-208d-4827-a355-6bb0ead646d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3791582419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3791582419 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2945274919 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336879250000 ps |
| CPU time | 839.45 seconds |
| Started | May 21 01:29:48 PM PDT 24 |
| Finished | May 21 02:05:39 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-7e5657fa-c4b9-46dd-805d-5eb83c632d04 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2945274919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2945274919 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.583286108 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336496370000 ps |
| CPU time | 864.51 seconds |
| Started | May 21 01:29:41 PM PDT 24 |
| Finished | May 21 02:05:42 PM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-88a5c48f-dfce-4e4e-b90c-9675634367ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=583286108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.583286108 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.452239420 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336847650000 ps |
| CPU time | 745.49 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 02:00:24 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-9735eef6-4723-4b08-9450-42a8400b60aa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=452239420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.452239420 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3052346074 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1478190000 ps |
| CPU time | 4.95 seconds |
| Started | May 21 01:29:22 PM PDT 24 |
| Finished | May 21 01:29:35 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-a73e7c00-79ea-41fa-8f6a-e371fd7923bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3052346074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3052346074 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1276800584 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1522150000 ps |
| CPU time | 6.14 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:41 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-c6bca03f-393c-45a5-9827-63eb46d3cb79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1276800584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1276800584 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.714697839 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1381250000 ps |
| CPU time | 4.52 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-42cfeab5-7c62-418c-a644-aebd5357ab63 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=714697839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.714697839 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4869898 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1417290000 ps |
| CPU time | 5.43 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-947b8a18-0276-4998-b6e0-60b84243938b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4869898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.4869898 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1840421710 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1212430000 ps |
| CPU time | 4.15 seconds |
| Started | May 21 01:29:22 PM PDT 24 |
| Finished | May 21 01:29:32 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-91f32f49-d2bf-43a9-bd4c-53b55cae0d08 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1840421710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1840421710 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2769786201 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1412850000 ps |
| CPU time | 6.57 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-c7574614-5fd7-4c74-8c75-64f1e99e144d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2769786201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2769786201 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.709108734 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1611550000 ps |
| CPU time | 5.08 seconds |
| Started | May 21 01:29:26 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-45c4d7de-2ea6-4278-bfa6-dfbe77452b35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=709108734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.709108734 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.395373574 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1289070000 ps |
| CPU time | 3.83 seconds |
| Started | May 21 01:29:26 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-9de6c0af-3898-4b53-a00f-e6a08510f675 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=395373574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.395373574 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1154377425 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1326330000 ps |
| CPU time | 4.27 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:34 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-f7da2d2f-4e7c-4516-9380-407a4afd6d84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1154377425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1154377425 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3608954433 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1488170000 ps |
| CPU time | 4.77 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-64685500-d40e-4d50-9a80-f7c6364230e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3608954433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3608954433 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3335356807 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1432510000 ps |
| CPU time | 3.92 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:33 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-baec538b-173b-46e4-993c-2bdcfbedafdf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3335356807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3335356807 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2413842513 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1394850000 ps |
| CPU time | 4.46 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-65606c11-296b-44fb-92af-d12454b56084 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2413842513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2413842513 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1911212554 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1439810000 ps |
| CPU time | 3.49 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:35 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-36e316cc-4249-49ef-bab9-1755545be681 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1911212554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1911212554 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4005521390 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1484550000 ps |
| CPU time | 5.26 seconds |
| Started | May 21 01:29:23 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-d4e4210d-22e8-4751-81ec-6ea7b95a051f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4005521390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4005521390 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1560181790 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1477270000 ps |
| CPU time | 3.78 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-7f548cb5-f3f2-4159-9156-8ab6205e140f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1560181790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1560181790 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3149431507 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1497930000 ps |
| CPU time | 4.28 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:35 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-3218d1c8-b0a4-4425-97a2-f10ec5f9aaba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3149431507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3149431507 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.934436322 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1425690000 ps |
| CPU time | 4.6 seconds |
| Started | May 21 01:29:27 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-851fe7e3-9c09-4cc0-8e02-2eddef468773 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=934436322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.934436322 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.903889362 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1526450000 ps |
| CPU time | 5.19 seconds |
| Started | May 21 01:29:26 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-b5c18b5f-0b13-4e27-98cf-ab2527e35948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=903889362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.903889362 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.211704751 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1558890000 ps |
| CPU time | 4.9 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-7e96584d-ad62-4e38-8581-741fc4153c5e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=211704751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.211704751 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1962031583 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1486230000 ps |
| CPU time | 4.8 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:38 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-de2e8c41-72eb-4495-b1b5-db94f552c5cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1962031583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1962031583 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.701754043 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1558030000 ps |
| CPU time | 5.11 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-570acb32-8a59-4cd7-96e2-37c38ac5bcbe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=701754043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.701754043 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2367237006 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1456770000 ps |
| CPU time | 5.22 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-45aaa004-1458-4df8-b93f-1e74aa82e24e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2367237006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2367237006 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1367540689 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1583170000 ps |
| CPU time | 5.11 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-91357be6-a188-4f29-8664-ac090c5c9e64 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1367540689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1367540689 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.711608628 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1413990000 ps |
| CPU time | 5.11 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-0ec78f8b-e015-4571-8b23-ae0ebacc2fd5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=711608628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.711608628 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4179060552 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1465350000 ps |
| CPU time | 4.06 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-980a93b1-aac9-47f8-8822-d4ea6ed80125 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4179060552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4179060552 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1305131784 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1562970000 ps |
| CPU time | 5.48 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:40 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-ab7b3ed3-858e-4344-b7fb-025262fa32fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1305131784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1305131784 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2655249089 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1418710000 ps |
| CPU time | 5.12 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:38 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-af563d3e-3317-47da-b146-79a0d98609a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2655249089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2655249089 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.470645314 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1548290000 ps |
| CPU time | 4.9 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:38 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-d0ef6cf0-e14d-414f-a1a7-d50298dce613 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=470645314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.470645314 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2553489521 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1533870000 ps |
| CPU time | 5.46 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-f15f197a-d5f9-49dd-94ba-8304b3851df5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2553489521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2553489521 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1231817996 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1375930000 ps |
| CPU time | 4.1 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-25ae22df-d198-48c4-88bd-743c8e3fcdec |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1231817996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1231817996 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1593289050 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1507910000 ps |
| CPU time | 4.48 seconds |
| Started | May 21 01:29:24 PM PDT 24 |
| Finished | May 21 01:29:35 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-1de8acde-6b0a-43c9-a3f0-ff192fcfe244 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1593289050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1593289050 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2605874042 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1549410000 ps |
| CPU time | 4.48 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-f593e96e-3a0d-48a9-adf7-a43acb8fba74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2605874042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2605874042 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2211853888 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1466730000 ps |
| CPU time | 4.18 seconds |
| Started | May 21 01:29:26 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164532 kb |
| Host | smart-713d8fee-3284-4f9b-8817-8d8d0d05d37f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2211853888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2211853888 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1585532997 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1469390000 ps |
| CPU time | 3.7 seconds |
| Started | May 21 01:29:21 PM PDT 24 |
| Finished | May 21 01:29:30 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-0e489975-73f0-4a4e-8c53-41f23882a997 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1585532997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1585532997 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2617172739 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1448170000 ps |
| CPU time | 4.22 seconds |
| Started | May 21 01:29:27 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-94d2a822-6ce7-43f4-9cde-ea4792cc5c51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2617172739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2617172739 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1313750291 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1286730000 ps |
| CPU time | 4.33 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-7c228d4f-02d1-40ef-a459-58e29a8c5882 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1313750291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1313750291 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.736508761 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1449150000 ps |
| CPU time | 5.39 seconds |
| Started | May 21 01:29:25 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-ef2493b5-fefc-4122-b6de-2d2cd291ebda |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=736508761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.736508761 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1020527216 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1545690000 ps |
| CPU time | 5.19 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 01:29:46 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-4a90fe64-5bd3-454c-96a1-d6678409f0ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1020527216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1020527216 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1591429140 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1387670000 ps |
| CPU time | 4.18 seconds |
| Started | May 21 01:29:32 PM PDT 24 |
| Finished | May 21 01:29:44 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-8c9e5b59-ff2d-4218-bc8e-05a94bb8a622 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1591429140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1591429140 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.339770754 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1537430000 ps |
| CPU time | 4.35 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 01:29:48 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-2b4b998d-6aa8-4994-83c1-6418f84430db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=339770754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.339770754 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1102671303 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1185930000 ps |
| CPU time | 3.5 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 01:29:42 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-2c83142c-403a-4f74-8744-7749a9f678c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1102671303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1102671303 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1751615354 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1384450000 ps |
| CPU time | 4.89 seconds |
| Started | May 21 01:29:35 PM PDT 24 |
| Finished | May 21 01:29:49 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-3028e7ec-e528-4958-a13b-496e9cdd61a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1751615354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1751615354 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2647212658 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1389550000 ps |
| CPU time | 3.66 seconds |
| Started | May 21 01:29:31 PM PDT 24 |
| Finished | May 21 01:29:39 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-5a3d6e91-4e18-4893-b93e-797fa7739546 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2647212658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2647212658 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1143735206 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1426150000 ps |
| CPU time | 4.67 seconds |
| Started | May 21 01:29:33 PM PDT 24 |
| Finished | May 21 01:29:46 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-41f7845c-0ff9-4615-9588-e4753815ba89 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1143735206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1143735206 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.252687005 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1347170000 ps |
| CPU time | 4.64 seconds |
| Started | May 21 01:29:22 PM PDT 24 |
| Finished | May 21 01:29:33 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-cd2dcd88-6346-4630-89ec-c5a5dc100a3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=252687005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.252687005 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2752061831 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1407670000 ps |
| CPU time | 3.37 seconds |
| Started | May 21 01:29:23 PM PDT 24 |
| Finished | May 21 01:29:32 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-1cb0adea-abba-424f-9394-779d176f92b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2752061831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2752061831 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.921549260 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1522190000 ps |
| CPU time | 6.26 seconds |
| Started | May 21 01:29:23 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-8bf4c86b-9dff-4383-9ca2-23d9131df310 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=921549260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.921549260 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1419737761 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1509350000 ps |
| CPU time | 5.38 seconds |
| Started | May 21 01:29:23 PM PDT 24 |
| Finished | May 21 01:29:36 PM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-61b81cae-7d15-43c7-b0e6-6849119e454d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1419737761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1419737761 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.156830494 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1177930000 ps |
| CPU time | 4.03 seconds |
| Started | May 21 01:29:28 PM PDT 24 |
| Finished | May 21 01:29:37 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-df80d72c-60ac-434a-9db1-4dbfaedede9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=156830494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.156830494 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1906928518 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1531250000 ps |
| CPU time | 6.62 seconds |
| Started | May 21 01:03:04 PM PDT 24 |
| Finished | May 21 01:03:19 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-247086bf-e722-4c9f-a3f4-9bb1ae343c6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1906928518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1906928518 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4112561764 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1599610000 ps |
| CPU time | 3.42 seconds |
| Started | May 21 01:03:09 PM PDT 24 |
| Finished | May 21 01:03:18 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-d6635c4b-3488-47e2-ba59-a138e1d33aa4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4112561764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4112561764 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2140821185 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1427610000 ps |
| CPU time | 6.36 seconds |
| Started | May 21 01:03:10 PM PDT 24 |
| Finished | May 21 01:03:24 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-68dc405f-9809-4408-8403-783772338c62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2140821185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2140821185 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2480696486 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1431470000 ps |
| CPU time | 5.89 seconds |
| Started | May 21 01:03:11 PM PDT 24 |
| Finished | May 21 01:03:24 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-99736963-7c7b-4824-b362-6abb9fc3f6b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2480696486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2480696486 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2447666087 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1424530000 ps |
| CPU time | 4.54 seconds |
| Started | May 21 01:03:11 PM PDT 24 |
| Finished | May 21 01:03:21 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-00637697-fec3-4998-8293-f3727a731d55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2447666087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2447666087 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3384397659 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1609170000 ps |
| CPU time | 5.07 seconds |
| Started | May 21 01:03:14 PM PDT 24 |
| Finished | May 21 01:03:26 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-423a29d6-d129-4164-b0b0-cdd27e63508c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3384397659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3384397659 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1120126131 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1391470000 ps |
| CPU time | 3.27 seconds |
| Started | May 21 01:03:10 PM PDT 24 |
| Finished | May 21 01:03:17 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-9a411110-6744-4cb0-a4a8-dc5ac0f40f01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1120126131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1120126131 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1175005099 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1548690000 ps |
| CPU time | 5.01 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-c835c913-e27c-4562-9201-01c5e5f7431b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1175005099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1175005099 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.135182331 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1324450000 ps |
| CPU time | 3.89 seconds |
| Started | May 21 01:03:19 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-003f1e66-82b7-4bc9-b16f-5c2fa39f05dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=135182331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.135182331 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3222299006 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1402930000 ps |
| CPU time | 5.39 seconds |
| Started | May 21 01:03:16 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-1e7a0e8b-7de2-4cc0-86eb-9063e0e74d57 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3222299006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3222299006 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.178838782 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1307850000 ps |
| CPU time | 3.76 seconds |
| Started | May 21 01:03:19 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-6a04f387-1db7-4222-b6f1-6a6406e9024f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=178838782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.178838782 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2975255486 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1380510000 ps |
| CPU time | 4.69 seconds |
| Started | May 21 01:03:10 PM PDT 24 |
| Finished | May 21 01:03:21 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-36be91be-f41b-4647-9415-e20b9542770a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2975255486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2975255486 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1567931394 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1521110000 ps |
| CPU time | 4.47 seconds |
| Started | May 21 01:03:19 PM PDT 24 |
| Finished | May 21 01:03:29 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-bbda0403-cff6-4ee2-98eb-0d4bdf813506 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1567931394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1567931394 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1451615999 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1607790000 ps |
| CPU time | 3.82 seconds |
| Started | May 21 01:03:16 PM PDT 24 |
| Finished | May 21 01:03:25 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-9a8b21e3-e022-467d-b6d5-fb4d1ba97990 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1451615999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1451615999 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3661591335 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1381250000 ps |
| CPU time | 5.37 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:29 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-437c3804-9d26-44c2-80d2-16150d4964f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3661591335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3661591335 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2597848753 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1246110000 ps |
| CPU time | 4.65 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-16f7e387-3165-48ac-8cf0-c202a609b942 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2597848753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2597848753 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1697291949 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1543650000 ps |
| CPU time | 5.02 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:28 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-b16ab4a2-e29d-4628-91de-5d5e8cbb6e9b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1697291949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1697291949 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1376316566 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1277290000 ps |
| CPU time | 5.84 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:30 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-04111965-ed45-4d4b-9e81-f92f27b9075f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1376316566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1376316566 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.303390746 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1560530000 ps |
| CPU time | 4.12 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:27 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-7024f0bc-1e62-4432-b759-ac6b393ddb1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=303390746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.303390746 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2696278976 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1485690000 ps |
| CPU time | 4.7 seconds |
| Started | May 21 01:03:18 PM PDT 24 |
| Finished | May 21 01:03:29 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-fcbf01a4-5e61-4003-87fc-12e5d15957ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2696278976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2696278976 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3793086115 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1291210000 ps |
| CPU time | 3.75 seconds |
| Started | May 21 01:03:18 PM PDT 24 |
| Finished | May 21 01:03:26 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-56fa8d1f-420c-4490-a749-aac13487965c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3793086115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3793086115 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.158050703 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1611290000 ps |
| CPU time | 3.55 seconds |
| Started | May 21 01:03:18 PM PDT 24 |
| Finished | May 21 01:03:27 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-087c0fe9-32a2-44ef-8377-2bf3b82b1287 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=158050703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.158050703 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3396605839 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1326950000 ps |
| CPU time | 3.61 seconds |
| Started | May 21 01:03:11 PM PDT 24 |
| Finished | May 21 01:03:20 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-ce48fb89-26ba-43e1-b677-e8ce23dd01d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3396605839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3396605839 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3665788274 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1420470000 ps |
| CPU time | 3.98 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:27 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-714d167d-09c4-4e24-967a-8b43d574dfe1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3665788274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3665788274 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3570757637 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1499150000 ps |
| CPU time | 5.82 seconds |
| Started | May 21 01:03:17 PM PDT 24 |
| Finished | May 21 01:03:30 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-9470d61d-e44a-4a0e-8ded-7bf04dc47b24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3570757637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3570757637 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3663581633 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1531190000 ps |
| CPU time | 5.37 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-d35d993d-ddb4-4ec9-ba3d-bf41a8fd5859 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3663581633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3663581633 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2553386507 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1552650000 ps |
| CPU time | 4.54 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:37 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-5e7bd03f-315f-4bde-94df-b7aa042737db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2553386507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2553386507 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.4058438015 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1296930000 ps |
| CPU time | 5.35 seconds |
| Started | May 21 01:03:24 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-f577e9c6-6c62-43ef-be1d-fed269d33956 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4058438015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.4058438015 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1519004546 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1563790000 ps |
| CPU time | 6.74 seconds |
| Started | May 21 01:03:24 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-0b54e670-fcbe-49f0-a987-7876b274744f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1519004546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1519004546 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3736379225 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1412630000 ps |
| CPU time | 3.05 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-6f7a4d74-7ca3-485e-b59a-0497d231dee6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3736379225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3736379225 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1953415589 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1465070000 ps |
| CPU time | 3.33 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:33 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-cc55d56f-bf75-4fe2-8a7b-81a2e4b30e2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1953415589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1953415589 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1683965257 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1423750000 ps |
| CPU time | 6.45 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-45ca3c67-f188-40ab-ae13-6701d87a469b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1683965257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1683965257 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3930953588 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1542390000 ps |
| CPU time | 5.27 seconds |
| Started | May 21 01:03:27 PM PDT 24 |
| Finished | May 21 01:03:40 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-841275b0-b624-479c-b6f2-4e830eb099d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3930953588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3930953588 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3332003923 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1610850000 ps |
| CPU time | 6.12 seconds |
| Started | May 21 01:03:11 PM PDT 24 |
| Finished | May 21 01:03:25 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-e0318c5a-2a5a-406d-809d-50069557088d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3332003923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3332003923 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1316316295 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1447730000 ps |
| CPU time | 4.56 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-320d042c-6f93-4839-987b-f3cbe3efcc6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1316316295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1316316295 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3355115849 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1444550000 ps |
| CPU time | 4.67 seconds |
| Started | May 21 01:03:24 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-f131e3b9-d0f5-45c6-9629-208d04a9ee3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3355115849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3355115849 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3285152465 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1426630000 ps |
| CPU time | 4.08 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-ce10501a-e647-40b2-92e4-b5eec16f49c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3285152465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3285152465 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3471992915 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1337090000 ps |
| CPU time | 2.86 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:33 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-81ac375b-62dc-4c09-8e4c-de6502a3640d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3471992915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3471992915 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2156882157 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1444450000 ps |
| CPU time | 5.48 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:38 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-859c18f1-6937-4fd5-abec-be63cb43bb8e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2156882157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2156882157 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.170160309 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1478570000 ps |
| CPU time | 4.38 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-a1069087-08e3-44b4-83ac-5df45b330abe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=170160309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.170160309 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.534445770 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1178570000 ps |
| CPU time | 5.07 seconds |
| Started | May 21 01:03:25 PM PDT 24 |
| Finished | May 21 01:03:36 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-9ac0e01e-fa08-4572-b97a-ba5d2884deff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=534445770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.534445770 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3085955293 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1306970000 ps |
| CPU time | 3.13 seconds |
| Started | May 21 01:03:23 PM PDT 24 |
| Finished | May 21 01:03:30 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-438a4b87-bfac-4b42-8bc0-8cc681b521e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3085955293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3085955293 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.260890447 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1440390000 ps |
| CPU time | 4.47 seconds |
| Started | May 21 01:03:24 PM PDT 24 |
| Finished | May 21 01:03:34 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-9ee668aa-633c-40dc-b08b-aed58e524477 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=260890447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.260890447 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1276251278 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1518810000 ps |
| CPU time | 3.55 seconds |
| Started | May 21 01:03:26 PM PDT 24 |
| Finished | May 21 01:03:35 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-90e99265-8583-4e45-a0da-7195ac7a0dd9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1276251278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1276251278 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.710509802 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1554650000 ps |
| CPU time | 4.83 seconds |
| Started | May 21 01:03:12 PM PDT 24 |
| Finished | May 21 01:03:23 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-9832c63c-c760-4803-a934-80259ec8c41e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=710509802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.710509802 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3845911836 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1543310000 ps |
| CPU time | 4.97 seconds |
| Started | May 21 01:03:14 PM PDT 24 |
| Finished | May 21 01:03:26 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-6b34e2f1-c590-4a2f-9a30-261d62206459 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3845911836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3845911836 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.837731313 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1551470000 ps |
| CPU time | 4.69 seconds |
| Started | May 21 01:03:12 PM PDT 24 |
| Finished | May 21 01:03:23 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-69ee7c54-2bb3-49de-97d9-ade3f81dd2fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=837731313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.837731313 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.531809556 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1318570000 ps |
| CPU time | 4.41 seconds |
| Started | May 21 01:03:13 PM PDT 24 |
| Finished | May 21 01:03:23 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-6115acb5-bc27-48d6-8316-fe24a5cf609b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=531809556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.531809556 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.562854339 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1420330000 ps |
| CPU time | 5.4 seconds |
| Started | May 21 01:03:10 PM PDT 24 |
| Finished | May 21 01:03:22 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-90225fbe-4abe-4e54-b233-afb25fe4cde1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=562854339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.562854339 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
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