| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1937905515 | ||
| 96.81 | 9.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 47.50 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2598681037 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3265574483 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.946464111 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2796285480 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1895182215 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1636159493 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1575162473 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.719205380 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2953355724 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3032018358 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3934818736 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1779852651 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.719472845 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3496972157 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1921926077 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3215192210 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1722332153 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.150061300 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2609243038 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1919840552 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2711109951 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.985631563 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.473747827 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.451492390 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.401715274 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2157139442 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3496500741 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2642303984 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3382420015 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.362622830 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.825866942 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3482436234 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.207571025 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3872619509 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.237018129 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4198392920 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.696606403 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1808322439 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2613783154 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1593547303 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3208337873 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3421443630 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2038972251 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2197520570 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2369079592 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3383772291 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2857076610 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4009414795 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.684553489 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2041605939 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1796927382 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2790581138 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1237910619 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1837043438 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.837732085 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1073223591 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1774411097 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.440746184 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1128896477 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3520079522 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3743046121 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1125591031 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3103350702 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.892159168 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1571558524 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.237364737 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.740118287 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.981773695 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1222472537 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.99942103 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2132635325 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3126118777 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1201534302 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1940018080 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2203785633 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3867590415 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4159318964 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.191307827 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2872078078 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2671022592 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3478727697 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.273295488 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3328678293 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.6868264 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.758744468 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1244811773 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2664010211 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3746889573 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3986840473 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1313376770 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2272199631 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2777443548 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3123612496 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2992824092 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4261199262 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3393237271 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4070445707 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.403198806 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1482060327 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2812885902 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3524983255 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3381655007 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2869428367 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.825013320 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1809230447 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4006414096 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1084509594 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3989909455 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.748920395 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.376920515 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1642802826 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4175637926 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3460889207 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3919900543 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.448163341 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3360003392 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3330096108 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2189607244 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1665315080 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2901069703 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3662761847 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2034463530 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1003169208 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2095380536 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2475191144 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1421907256 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.502764485 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3204945149 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.895601325 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3908585242 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4185083527 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3795838813 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2838305943 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1890938407 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3264920701 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2180721049 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2200827664 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2762209602 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3670802547 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.32287377 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3432999928 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.338993120 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1320182606 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3289052501 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.30918349 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.532117129 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.57326569 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.535092715 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3469607827 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1596991499 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1230991713 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3370168652 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3554997109 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4110285569 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2580537282 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2131253986 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1178998421 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1309142561 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4023906227 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.536993278 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2956816020 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.71577334 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1998932152 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1906560706 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3176871752 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4004456292 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3787874333 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.71332 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2336038327 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3674475528 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1067680753 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1712325154 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2540005513 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2413352476 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.309597186 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.890375827 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2693120284 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2663371021 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3547619723 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2211500973 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.868100170 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4168399008 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2124490239 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2604657580 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.661470624 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1544561056 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.426728318 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3580256244 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4205845402 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3851857434 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2105072811 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.408775920 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.809183135 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1795472050 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3741782978 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2175020521 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1266416421 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2534565700 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1965978552 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3554997109 | May 23 03:21:08 PM PDT 24 | May 23 03:21:31 PM PDT 24 | 1608530000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2663371021 | May 23 03:21:25 PM PDT 24 | May 23 03:21:43 PM PDT 24 | 1412930000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1937905515 | May 23 03:21:11 PM PDT 24 | May 23 03:21:34 PM PDT 24 | 1505350000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1067680753 | May 23 03:21:25 PM PDT 24 | May 23 03:21:43 PM PDT 24 | 1385350000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1906560706 | May 23 03:21:21 PM PDT 24 | May 23 03:21:36 PM PDT 24 | 1453190000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2211500973 | May 23 03:21:22 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1612230000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3787874333 | May 23 03:21:25 PM PDT 24 | May 23 03:21:41 PM PDT 24 | 1509370000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.408775920 | May 23 03:21:21 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1496590000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2693120284 | May 23 03:21:25 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1554490000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.868100170 | May 23 03:21:21 PM PDT 24 | May 23 03:21:36 PM PDT 24 | 1481590000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3851857434 | May 23 03:21:20 PM PDT 24 | May 23 03:21:40 PM PDT 24 | 1629030000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2175020521 | May 23 03:21:10 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1568190000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1309142561 | May 23 03:21:08 PM PDT 24 | May 23 03:21:30 PM PDT 24 | 1562650000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2413352476 | May 23 03:21:25 PM PDT 24 | May 23 03:21:40 PM PDT 24 | 1550970000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.426728318 | May 23 03:21:21 PM PDT 24 | May 23 03:21:38 PM PDT 24 | 1407270000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.309597186 | May 23 03:21:22 PM PDT 24 | May 23 03:21:36 PM PDT 24 | 1526250000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2131253986 | May 23 03:21:07 PM PDT 24 | May 23 03:21:30 PM PDT 24 | 1495630000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3580256244 | May 23 03:21:30 PM PDT 24 | May 23 03:21:41 PM PDT 24 | 1527450000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2604657580 | May 23 03:21:10 PM PDT 24 | May 23 03:21:32 PM PDT 24 | 1641230000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4168399008 | May 23 03:21:22 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1469450000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1965978552 | May 23 03:21:10 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1486990000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2956816020 | May 23 03:21:28 PM PDT 24 | May 23 03:21:42 PM PDT 24 | 1568090000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3370168652 | May 23 03:21:06 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1466210000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.536993278 | May 23 03:21:08 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1172270000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2580537282 | May 23 03:21:08 PM PDT 24 | May 23 03:21:30 PM PDT 24 | 1360710000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.890375827 | May 23 03:21:26 PM PDT 24 | May 23 03:21:43 PM PDT 24 | 1539230000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3547619723 | May 23 03:21:27 PM PDT 24 | May 23 03:21:41 PM PDT 24 | 1497970000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1544561056 | May 23 03:21:22 PM PDT 24 | May 23 03:21:36 PM PDT 24 | 1503610000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3741782978 | May 23 03:21:08 PM PDT 24 | May 23 03:21:29 PM PDT 24 | 1495330000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4023906227 | May 23 03:21:08 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1179970000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2105072811 | May 23 03:21:26 PM PDT 24 | May 23 03:21:44 PM PDT 24 | 1515630000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4004456292 | May 23 03:21:21 PM PDT 24 | May 23 03:21:34 PM PDT 24 | 1426550000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2336038327 | May 23 03:21:25 PM PDT 24 | May 23 03:21:43 PM PDT 24 | 1420850000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1266416421 | May 23 03:21:10 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1447810000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2534565700 | May 23 03:21:10 PM PDT 24 | May 23 03:21:35 PM PDT 24 | 1626270000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1795472050 | May 23 03:21:25 PM PDT 24 | May 23 03:21:37 PM PDT 24 | 1426150000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3674475528 | May 23 03:21:22 PM PDT 24 | May 23 03:21:36 PM PDT 24 | 1456070000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4110285569 | May 23 03:21:11 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1389150000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.71577334 | May 23 03:21:08 PM PDT 24 | May 23 03:21:29 PM PDT 24 | 1486710000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.661470624 | May 23 03:21:21 PM PDT 24 | May 23 03:21:35 PM PDT 24 | 1441890000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1712325154 | May 23 03:21:25 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1484130000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2124490239 | May 23 03:21:25 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1376690000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.71332 | May 23 03:21:22 PM PDT 24 | May 23 03:21:39 PM PDT 24 | 1510830000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2540005513 | May 23 03:21:08 PM PDT 24 | May 23 03:21:29 PM PDT 24 | 1482670000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1998932152 | May 23 03:21:29 PM PDT 24 | May 23 03:21:40 PM PDT 24 | 1355290000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1230991713 | May 23 03:21:11 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1450050000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4205845402 | May 23 03:21:24 PM PDT 24 | May 23 03:21:38 PM PDT 24 | 1321830000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.809183135 | May 23 03:21:27 PM PDT 24 | May 23 03:21:41 PM PDT 24 | 1377750000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1178998421 | May 23 03:21:07 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1080990000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3176871752 | May 23 03:21:20 PM PDT 24 | May 23 03:21:37 PM PDT 24 | 1434890000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3382420015 | May 23 01:14:46 PM PDT 24 | May 23 01:46:11 PM PDT 24 | 336894010000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.451492390 | May 23 01:14:43 PM PDT 24 | May 23 01:43:57 PM PDT 24 | 337026910000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1921926077 | May 23 01:14:43 PM PDT 24 | May 23 01:43:03 PM PDT 24 | 337129870000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.985631563 | May 23 01:14:43 PM PDT 24 | May 23 01:47:31 PM PDT 24 | 336419990000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.684553489 | May 23 01:14:45 PM PDT 24 | May 23 01:48:31 PM PDT 24 | 336561790000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2711109951 | May 23 01:14:46 PM PDT 24 | May 23 01:46:19 PM PDT 24 | 337063050000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2038972251 | May 23 01:14:58 PM PDT 24 | May 23 01:51:04 PM PDT 24 | 336803170000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3496500741 | May 23 01:14:43 PM PDT 24 | May 23 01:47:10 PM PDT 24 | 336536330000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2598681037 | May 23 01:14:43 PM PDT 24 | May 23 01:47:39 PM PDT 24 | 337107470000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.696606403 | May 23 01:15:00 PM PDT 24 | May 23 01:40:46 PM PDT 24 | 336453310000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.719205380 | May 23 01:14:42 PM PDT 24 | May 23 01:44:22 PM PDT 24 | 336696790000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.719472845 | May 23 01:14:54 PM PDT 24 | May 23 01:50:16 PM PDT 24 | 336627570000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.825866942 | May 23 01:14:45 PM PDT 24 | May 23 01:50:54 PM PDT 24 | 336609670000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.150061300 | May 23 01:14:42 PM PDT 24 | May 23 01:45:09 PM PDT 24 | 337184210000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1593547303 | May 23 01:15:15 PM PDT 24 | May 23 01:49:16 PM PDT 24 | 336967670000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3872619509 | May 23 01:14:57 PM PDT 24 | May 23 01:41:57 PM PDT 24 | 336369170000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1636159493 | May 23 01:14:43 PM PDT 24 | May 23 01:50:50 PM PDT 24 | 336511470000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2609243038 | May 23 01:14:46 PM PDT 24 | May 23 01:46:29 PM PDT 24 | 336938330000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3934818736 | May 23 01:14:41 PM PDT 24 | May 23 01:48:50 PM PDT 24 | 336674430000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1808322439 | May 23 01:14:59 PM PDT 24 | May 23 01:47:59 PM PDT 24 | 337009830000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1722332153 | May 23 01:14:41 PM PDT 24 | May 23 01:44:29 PM PDT 24 | 336523150000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2197520570 | May 23 01:14:56 PM PDT 24 | May 23 01:47:41 PM PDT 24 | 336554850000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.237018129 | May 23 01:15:01 PM PDT 24 | May 23 01:43:40 PM PDT 24 | 336992990000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3421443630 | May 23 01:15:01 PM PDT 24 | May 23 01:49:53 PM PDT 24 | 337011210000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3215192210 | May 23 01:14:45 PM PDT 24 | May 23 01:45:45 PM PDT 24 | 336356190000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2613783154 | May 23 01:15:02 PM PDT 24 | May 23 01:48:34 PM PDT 24 | 336544290000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.362622830 | May 23 01:14:44 PM PDT 24 | May 23 01:48:38 PM PDT 24 | 336592750000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1575162473 | May 23 01:14:45 PM PDT 24 | May 23 01:45:43 PM PDT 24 | 336637690000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1895182215 | May 23 01:14:46 PM PDT 24 | May 23 01:47:11 PM PDT 24 | 336879190000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2369079592 | May 23 01:14:57 PM PDT 24 | May 23 01:45:30 PM PDT 24 | 336557670000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4198392920 | May 23 01:14:44 PM PDT 24 | May 23 01:44:08 PM PDT 24 | 336484390000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2796285480 | May 23 01:14:43 PM PDT 24 | May 23 01:46:30 PM PDT 24 | 336576230000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3383772291 | May 23 01:14:57 PM PDT 24 | May 23 01:48:26 PM PDT 24 | 336612610000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2041605939 | May 23 01:14:43 PM PDT 24 | May 23 01:41:57 PM PDT 24 | 336826010000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.946464111 | May 23 01:14:42 PM PDT 24 | May 23 01:46:38 PM PDT 24 | 337121530000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3496972157 | May 23 01:14:44 PM PDT 24 | May 23 01:45:39 PM PDT 24 | 337047910000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.401715274 | May 23 01:14:42 PM PDT 24 | May 23 01:46:54 PM PDT 24 | 336314990000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2953355724 | May 23 01:14:46 PM PDT 24 | May 23 01:48:33 PM PDT 24 | 337021190000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2857076610 | May 23 01:14:43 PM PDT 24 | May 23 01:48:53 PM PDT 24 | 337101550000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.473747827 | May 23 01:14:43 PM PDT 24 | May 23 01:44:24 PM PDT 24 | 336535010000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3208337873 | May 23 01:14:59 PM PDT 24 | May 23 01:43:03 PM PDT 24 | 336540890000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1919840552 | May 23 01:14:43 PM PDT 24 | May 23 01:41:50 PM PDT 24 | 336735930000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3482436234 | May 23 01:14:45 PM PDT 24 | May 23 01:41:22 PM PDT 24 | 336850510000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4009414795 | May 23 01:14:45 PM PDT 24 | May 23 01:46:28 PM PDT 24 | 336669470000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.207571025 | May 23 01:14:59 PM PDT 24 | May 23 01:46:05 PM PDT 24 | 336494250000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3032018358 | May 23 01:14:42 PM PDT 24 | May 23 01:50:08 PM PDT 24 | 337071130000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1779852651 | May 23 01:14:44 PM PDT 24 | May 23 01:51:02 PM PDT 24 | 336756090000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1796927382 | May 23 01:14:41 PM PDT 24 | May 23 01:44:52 PM PDT 24 | 337008550000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2157139442 | May 23 01:14:42 PM PDT 24 | May 23 01:45:40 PM PDT 24 | 336553930000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2642303984 | May 23 01:14:44 PM PDT 24 | May 23 01:43:05 PM PDT 24 | 336521310000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2189607244 | May 23 03:21:06 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1542610000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1320182606 | May 23 03:21:09 PM PDT 24 | May 23 03:21:32 PM PDT 24 | 1379310000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3264920701 | May 23 03:21:04 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1544050000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1809230447 | May 23 03:21:05 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1396450000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.535092715 | May 23 03:21:04 PM PDT 24 | May 23 03:21:21 PM PDT 24 | 1562310000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3908585242 | May 23 03:21:07 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1507170000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.30918349 | May 23 03:21:10 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1439810000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.448163341 | May 23 03:21:06 PM PDT 24 | May 23 03:21:24 PM PDT 24 | 1578810000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3460889207 | May 23 03:21:03 PM PDT 24 | May 23 03:21:20 PM PDT 24 | 1373210000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3662761847 | May 23 03:21:08 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1331890000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2762209602 | May 23 03:21:10 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1541150000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3289052501 | May 23 03:21:08 PM PDT 24 | May 23 03:21:29 PM PDT 24 | 1488390000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.502764485 | May 23 03:21:07 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1195070000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1642802826 | May 23 03:21:07 PM PDT 24 | May 23 03:21:31 PM PDT 24 | 1532250000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3432999928 | May 23 03:21:07 PM PDT 24 | May 23 03:21:32 PM PDT 24 | 1589490000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3670802547 | May 23 03:21:08 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1453890000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3204945149 | May 23 03:21:07 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1562390000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1665315080 | May 23 03:21:05 PM PDT 24 | May 23 03:21:23 PM PDT 24 | 1439330000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4185083527 | May 23 03:21:05 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1433190000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.32287377 | May 23 03:21:08 PM PDT 24 | May 23 03:21:29 PM PDT 24 | 1583950000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1003169208 | May 23 03:20:57 PM PDT 24 | May 23 03:21:14 PM PDT 24 | 1579950000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1890938407 | May 23 03:21:07 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1489490000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3989909455 | May 23 03:21:04 PM PDT 24 | May 23 03:21:19 PM PDT 24 | 1428270000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.825013320 | May 23 03:21:05 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1475590000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3919900543 | May 23 03:21:08 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1283630000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3524983255 | May 23 03:21:05 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1469750000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3469607827 | May 23 03:21:08 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1499130000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2095380536 | May 23 03:21:06 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1441010000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3360003392 | May 23 03:21:07 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1599530000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4006414096 | May 23 03:21:06 PM PDT 24 | May 23 03:21:23 PM PDT 24 | 1453390000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3795838813 | May 23 03:21:09 PM PDT 24 | May 23 03:21:33 PM PDT 24 | 1507590000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3330096108 | May 23 03:21:07 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1491550000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2180721049 | May 23 03:21:06 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1491190000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2200827664 | May 23 03:21:09 PM PDT 24 | May 23 03:21:29 PM PDT 24 | 1405870000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.895601325 | May 23 03:21:06 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1486370000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2901069703 | May 23 03:21:07 PM PDT 24 | May 23 03:21:28 PM PDT 24 | 1418550000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2034463530 | May 23 03:21:07 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1422430000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1596991499 | May 23 03:21:08 PM PDT 24 | May 23 03:21:32 PM PDT 24 | 1525870000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2475191144 | May 23 03:21:05 PM PDT 24 | May 23 03:21:25 PM PDT 24 | 1567190000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2838305943 | May 23 03:21:07 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1406770000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1421907256 | May 23 03:21:06 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1487790000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.532117129 | May 23 03:21:05 PM PDT 24 | May 23 03:21:25 PM PDT 24 | 1490730000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1084509594 | May 23 03:21:05 PM PDT 24 | May 23 03:21:25 PM PDT 24 | 1457150000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4175637926 | May 23 03:21:08 PM PDT 24 | May 23 03:21:27 PM PDT 24 | 1243130000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3381655007 | May 23 03:21:04 PM PDT 24 | May 23 03:21:24 PM PDT 24 | 1534510000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.338993120 | May 23 03:21:07 PM PDT 24 | May 23 03:21:31 PM PDT 24 | 1443910000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.57326569 | May 23 03:21:04 PM PDT 24 | May 23 03:21:20 PM PDT 24 | 1364290000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.748920395 | May 23 03:21:05 PM PDT 24 | May 23 03:21:23 PM PDT 24 | 1500490000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2869428367 | May 23 03:21:06 PM PDT 24 | May 23 03:21:30 PM PDT 24 | 1555370000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.376920515 | May 23 03:21:05 PM PDT 24 | May 23 03:21:26 PM PDT 24 | 1549390000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3123612496 | May 23 02:58:00 PM PDT 24 | May 23 03:32:45 PM PDT 24 | 336780190000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2203785633 | May 23 02:58:04 PM PDT 24 | May 23 03:29:26 PM PDT 24 | 336758290000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2777443548 | May 23 02:57:58 PM PDT 24 | May 23 03:25:22 PM PDT 24 | 337055950000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1940018080 | May 23 02:57:51 PM PDT 24 | May 23 03:35:57 PM PDT 24 | 336756570000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3265574483 | May 23 02:58:00 PM PDT 24 | May 23 03:28:22 PM PDT 24 | 336690410000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.981773695 | May 23 02:58:00 PM PDT 24 | May 23 03:37:39 PM PDT 24 | 336964630000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2812885902 | May 23 02:57:59 PM PDT 24 | May 23 03:29:48 PM PDT 24 | 336324890000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1128896477 | May 23 02:58:00 PM PDT 24 | May 23 03:31:56 PM PDT 24 | 336965110000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.99942103 | May 23 02:58:04 PM PDT 24 | May 23 03:29:31 PM PDT 24 | 336696430000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1313376770 | May 23 02:57:59 PM PDT 24 | May 23 03:25:23 PM PDT 24 | 336833710000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4261199262 | May 23 02:58:00 PM PDT 24 | May 23 03:27:25 PM PDT 24 | 336387770000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3867590415 | May 23 02:58:03 PM PDT 24 | May 23 03:33:28 PM PDT 24 | 336891450000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3478727697 | May 23 02:58:04 PM PDT 24 | May 23 03:33:27 PM PDT 24 | 336602310000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3126118777 | May 23 02:58:02 PM PDT 24 | May 23 03:32:57 PM PDT 24 | 336428330000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2671022592 | May 23 02:58:04 PM PDT 24 | May 23 03:33:16 PM PDT 24 | 336447470000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1571558524 | May 23 02:57:59 PM PDT 24 | May 23 03:31:40 PM PDT 24 | 336632850000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3743046121 | May 23 02:57:59 PM PDT 24 | May 23 03:27:00 PM PDT 24 | 336396390000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.440746184 | May 23 02:58:00 PM PDT 24 | May 23 03:26:35 PM PDT 24 | 337085430000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1125591031 | May 23 02:58:01 PM PDT 24 | May 23 03:29:27 PM PDT 24 | 336843310000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1073223591 | May 23 02:58:00 PM PDT 24 | May 23 03:24:37 PM PDT 24 | 337035050000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1482060327 | May 23 02:58:01 PM PDT 24 | May 23 03:31:12 PM PDT 24 | 336496710000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2992824092 | May 23 02:58:01 PM PDT 24 | May 23 03:33:52 PM PDT 24 | 337099310000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1237910619 | May 23 02:57:50 PM PDT 24 | May 23 03:36:49 PM PDT 24 | 336608590000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.837732085 | May 23 02:58:01 PM PDT 24 | May 23 03:35:23 PM PDT 24 | 336684070000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2132635325 | May 23 02:58:01 PM PDT 24 | May 23 03:27:23 PM PDT 24 | 337023050000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.6868264 | May 23 02:58:04 PM PDT 24 | May 23 03:27:11 PM PDT 24 | 336646510000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3328678293 | May 23 02:58:04 PM PDT 24 | May 23 03:31:18 PM PDT 24 | 336440850000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1774411097 | May 23 02:58:04 PM PDT 24 | May 23 03:34:14 PM PDT 24 | 337057490000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.892159168 | May 23 02:58:01 PM PDT 24 | May 23 03:29:33 PM PDT 24 | 336515150000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1244811773 | May 23 02:58:03 PM PDT 24 | May 23 03:31:14 PM PDT 24 | 336880450000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3393237271 | May 23 02:57:51 PM PDT 24 | May 23 03:37:03 PM PDT 24 | 336928910000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3746889573 | May 23 02:58:00 PM PDT 24 | May 23 03:27:41 PM PDT 24 | 336341630000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2790581138 | May 23 02:57:48 PM PDT 24 | May 23 03:35:16 PM PDT 24 | 336555650000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.740118287 | May 23 02:58:00 PM PDT 24 | May 23 03:31:58 PM PDT 24 | 336606890000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2272199631 | May 23 02:58:02 PM PDT 24 | May 23 03:33:42 PM PDT 24 | 336784250000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1201534302 | May 23 02:58:01 PM PDT 24 | May 23 03:31:42 PM PDT 24 | 336770050000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3986840473 | May 23 02:58:00 PM PDT 24 | May 23 03:37:28 PM PDT 24 | 336672370000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1222472537 | May 23 02:58:00 PM PDT 24 | May 23 03:24:21 PM PDT 24 | 336739370000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3103350702 | May 23 02:57:48 PM PDT 24 | May 23 03:35:00 PM PDT 24 | 336438450000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.758744468 | May 23 02:57:50 PM PDT 24 | May 23 03:36:47 PM PDT 24 | 337044490000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.191307827 | May 23 02:58:03 PM PDT 24 | May 23 03:32:56 PM PDT 24 | 336990850000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.237364737 | May 23 02:58:04 PM PDT 24 | May 23 03:34:09 PM PDT 24 | 336888490000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4070445707 | May 23 02:57:59 PM PDT 24 | May 23 03:27:03 PM PDT 24 | 337120530000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2872078078 | May 23 02:58:03 PM PDT 24 | May 23 03:26:04 PM PDT 24 | 336714370000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1837043438 | May 23 02:58:00 PM PDT 24 | May 23 03:26:39 PM PDT 24 | 337130850000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2664010211 | May 23 02:58:06 PM PDT 24 | May 23 03:26:59 PM PDT 24 | 337114710000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.273295488 | May 23 02:58:05 PM PDT 24 | May 23 03:31:10 PM PDT 24 | 336754090000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.403198806 | May 23 02:57:59 PM PDT 24 | May 23 03:30:47 PM PDT 24 | 336307530000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4159318964 | May 23 02:58:04 PM PDT 24 | May 23 03:29:37 PM PDT 24 | 336583810000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3520079522 | May 23 02:58:00 PM PDT 24 | May 23 03:29:47 PM PDT 24 | 336705870000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1937905515 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1505350000 ps |
| CPU time | 5.03 seconds |
| Started | May 23 03:21:11 PM PDT 24 |
| Finished | May 23 03:21:34 PM PDT 24 |
| Peak memory | 164596 kb |
| Host | smart-450e0b2d-2846-49ca-a821-635300efd3af |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1937905515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1937905515 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2598681037 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 337107470000 ps |
| CPU time | 804.41 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:47:39 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-abf39a4c-0bba-477d-b55c-b0508659d301 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2598681037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2598681037 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3265574483 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336690410000 ps |
| CPU time | 736.59 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:28:22 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-5955c472-56d7-41df-ba52-024d3ac67063 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3265574483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3265574483 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.946464111 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 337121530000 ps |
| CPU time | 781.31 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:46:38 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-0f46cb76-3aff-4bd9-8878-14975d3da34f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=946464111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.946464111 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2796285480 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336576230000 ps |
| CPU time | 779.61 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:46:30 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-228c3587-366f-4db2-868b-9bea55841de4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2796285480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2796285480 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1895182215 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336879190000 ps |
| CPU time | 805.09 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:47:11 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-fef50e0f-d9dd-42f6-9f17-459a00ee1716 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1895182215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1895182215 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1636159493 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 336511470000 ps |
| CPU time | 878.06 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:50:50 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-f23516e8-4972-4885-a832-9db757620464 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1636159493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1636159493 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1575162473 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336637690000 ps |
| CPU time | 761.51 seconds |
| Started | May 23 01:14:45 PM PDT 24 |
| Finished | May 23 01:45:43 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-c9708f4f-89a1-4ffb-b83e-2bebbc0091fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1575162473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1575162473 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.719205380 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 336696790000 ps |
| CPU time | 721.73 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:44:22 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-8e6632ed-b8b3-4b29-81ac-b74e6080ff03 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=719205380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.719205380 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2953355724 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 337021190000 ps |
| CPU time | 822.24 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:48:33 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-a8f53b00-9fe4-41dc-bfcc-f4afed1cecdf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2953355724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2953355724 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3032018358 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 337071130000 ps |
| CPU time | 858.39 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:50:08 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-963b5122-bb75-4648-ab28-46288425c54c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3032018358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3032018358 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3934818736 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 336674430000 ps |
| CPU time | 830.05 seconds |
| Started | May 23 01:14:41 PM PDT 24 |
| Finished | May 23 01:48:50 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-10e8f47a-2fe2-4950-bfc8-2165e3b539da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3934818736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3934818736 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1779852651 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336756090000 ps |
| CPU time | 889.22 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:51:02 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-94a72ea4-895b-43b6-98bc-0e25783eec80 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1779852651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1779852651 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.719472845 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336627570000 ps |
| CPU time | 862.5 seconds |
| Started | May 23 01:14:54 PM PDT 24 |
| Finished | May 23 01:50:16 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-c0b8f76e-6eff-4339-80a5-01e518dcf6a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=719472845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.719472845 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3496972157 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 337047910000 ps |
| CPU time | 766.51 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:45:39 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-a0c0ec62-9cd3-41ac-988c-e8bbc712077e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3496972157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3496972157 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1921926077 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 337129870000 ps |
| CPU time | 693.46 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:43:03 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-dd513365-ace9-4020-a3a8-0d58e1dc0aad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1921926077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1921926077 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3215192210 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336356190000 ps |
| CPU time | 756.28 seconds |
| Started | May 23 01:14:45 PM PDT 24 |
| Finished | May 23 01:45:45 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-6ab9233f-8486-4785-916e-970a8076b1da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3215192210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3215192210 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1722332153 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336523150000 ps |
| CPU time | 731.13 seconds |
| Started | May 23 01:14:41 PM PDT 24 |
| Finished | May 23 01:44:29 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-807c1ce9-a19e-413c-8558-fbd680677a32 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1722332153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1722332153 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.150061300 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 337184210000 ps |
| CPU time | 746.09 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:45:09 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-b2c765a9-f53e-4bec-a481-6464d24f266f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=150061300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.150061300 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2609243038 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336938330000 ps |
| CPU time | 785.76 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:46:29 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-77a1b900-5ac3-4c3c-9b31-309a194a028e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2609243038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2609243038 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1919840552 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336735930000 ps |
| CPU time | 654.65 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:41:50 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-47716161-f9cf-498e-b6d4-c1c29c57d58e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1919840552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1919840552 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2711109951 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 337063050000 ps |
| CPU time | 779.82 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:46:19 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-fd45183b-2067-4071-87d9-c11a477a7210 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2711109951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2711109951 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.985631563 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336419990000 ps |
| CPU time | 810.47 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:47:31 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-bf162610-8365-4f07-9051-b92c82ac429b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=985631563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.985631563 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.473747827 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336535010000 ps |
| CPU time | 722.24 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:44:24 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-56c9558b-01b6-49a5-a292-7326d211b561 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=473747827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.473747827 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.451492390 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 337026910000 ps |
| CPU time | 711.37 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:43:57 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-45e8faf5-4019-4d91-974c-267531c7f9f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=451492390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.451492390 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.401715274 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336314990000 ps |
| CPU time | 793.56 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:46:54 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-1c84b41d-3d86-4274-8858-28b41915269d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=401715274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.401715274 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2157139442 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336553930000 ps |
| CPU time | 756.19 seconds |
| Started | May 23 01:14:42 PM PDT 24 |
| Finished | May 23 01:45:40 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-7d416cb7-39b9-4f2c-a035-247daefee2fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2157139442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2157139442 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3496500741 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336536330000 ps |
| CPU time | 800.29 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:47:10 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-035d6604-3422-49e3-992a-cb12a96701ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3496500741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3496500741 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2642303984 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336521310000 ps |
| CPU time | 689.11 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:43:05 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-031a497e-96ca-4212-9e61-66fb7c912ed0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2642303984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2642303984 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3382420015 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 336894010000 ps |
| CPU time | 770.63 seconds |
| Started | May 23 01:14:46 PM PDT 24 |
| Finished | May 23 01:46:11 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-06ebecf2-6ca0-4fc1-9ac9-3567f455f1a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3382420015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3382420015 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.362622830 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336592750000 ps |
| CPU time | 827.85 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:48:38 PM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-ad0f2764-8e0e-491b-a91d-301ecfd447a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=362622830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.362622830 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.825866942 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336609670000 ps |
| CPU time | 881.15 seconds |
| Started | May 23 01:14:45 PM PDT 24 |
| Finished | May 23 01:50:54 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-1d51b79c-66af-4354-8a0f-ef68b4f23393 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=825866942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.825866942 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3482436234 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336850510000 ps |
| CPU time | 643.1 seconds |
| Started | May 23 01:14:45 PM PDT 24 |
| Finished | May 23 01:41:22 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-fe9fa19f-4878-4ec1-a378-ceb479c30755 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3482436234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3482436234 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.207571025 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336494250000 ps |
| CPU time | 765.3 seconds |
| Started | May 23 01:14:59 PM PDT 24 |
| Finished | May 23 01:46:05 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-9873602e-9e56-435e-b871-ddbd2ada2364 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=207571025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.207571025 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3872619509 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336369170000 ps |
| CPU time | 650.3 seconds |
| Started | May 23 01:14:57 PM PDT 24 |
| Finished | May 23 01:41:57 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-8497c1f1-0704-4700-8718-5e0c4e1f19cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3872619509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3872619509 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.237018129 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336992990000 ps |
| CPU time | 708.59 seconds |
| Started | May 23 01:15:01 PM PDT 24 |
| Finished | May 23 01:43:40 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-f0878b6e-adeb-4637-82ff-7d352da5612d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=237018129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.237018129 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4198392920 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336484390000 ps |
| CPU time | 712.84 seconds |
| Started | May 23 01:14:44 PM PDT 24 |
| Finished | May 23 01:44:08 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-3534401e-eeda-4255-82c6-a9a688b818cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4198392920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4198392920 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.696606403 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336453310000 ps |
| CPU time | 611.74 seconds |
| Started | May 23 01:15:00 PM PDT 24 |
| Finished | May 23 01:40:46 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-c90410c7-0fa8-4e86-9d9b-f9176689c7de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=696606403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.696606403 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1808322439 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 337009830000 ps |
| CPU time | 814 seconds |
| Started | May 23 01:14:59 PM PDT 24 |
| Finished | May 23 01:47:59 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-403b9140-afe7-4b92-ac78-a2f9e5c4d83c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1808322439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1808322439 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2613783154 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336544290000 ps |
| CPU time | 814.65 seconds |
| Started | May 23 01:15:02 PM PDT 24 |
| Finished | May 23 01:48:34 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-20d036f0-6916-4355-a783-b6914d01ec0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2613783154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2613783154 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1593547303 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 336967670000 ps |
| CPU time | 821.21 seconds |
| Started | May 23 01:15:15 PM PDT 24 |
| Finished | May 23 01:49:16 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-6f0f72fe-e914-46ab-be2b-a582f9f93e84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1593547303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1593547303 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3208337873 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336540890000 ps |
| CPU time | 677.57 seconds |
| Started | May 23 01:14:59 PM PDT 24 |
| Finished | May 23 01:43:03 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-a451e1ac-4558-4534-98ed-080f73f18b26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3208337873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3208337873 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3421443630 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 337011210000 ps |
| CPU time | 840.61 seconds |
| Started | May 23 01:15:01 PM PDT 24 |
| Finished | May 23 01:49:53 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-117a10bc-e566-47db-b92d-bc4597c473b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3421443630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3421443630 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2038972251 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336803170000 ps |
| CPU time | 878.2 seconds |
| Started | May 23 01:14:58 PM PDT 24 |
| Finished | May 23 01:51:04 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-6c3b0011-699f-479d-a764-941415614022 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2038972251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2038972251 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2197520570 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336554850000 ps |
| CPU time | 817.12 seconds |
| Started | May 23 01:14:56 PM PDT 24 |
| Finished | May 23 01:47:41 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-a837db7e-4299-457e-b4e2-263d7471014a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2197520570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2197520570 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2369079592 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336557670000 ps |
| CPU time | 742.52 seconds |
| Started | May 23 01:14:57 PM PDT 24 |
| Finished | May 23 01:45:30 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-e7b4193c-a110-47d3-a251-62e7a3a1c91a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2369079592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2369079592 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3383772291 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336612610000 ps |
| CPU time | 812.13 seconds |
| Started | May 23 01:14:57 PM PDT 24 |
| Finished | May 23 01:48:26 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-fed6b76a-98c7-4ea3-ae80-92ca9c40fd82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3383772291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3383772291 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2857076610 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 337101550000 ps |
| CPU time | 824.25 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:48:53 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-63274b8a-265d-442c-b662-990b498d6335 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2857076610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2857076610 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4009414795 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336669470000 ps |
| CPU time | 790.31 seconds |
| Started | May 23 01:14:45 PM PDT 24 |
| Finished | May 23 01:46:28 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-e506a96d-df5a-4b02-83e4-f2c2e8c35836 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4009414795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4009414795 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.684553489 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336561790000 ps |
| CPU time | 825.03 seconds |
| Started | May 23 01:14:45 PM PDT 24 |
| Finished | May 23 01:48:31 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-e73e2fcf-f9ac-4402-a7f2-93d2fac586db |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=684553489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.684553489 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2041605939 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336826010000 ps |
| CPU time | 648.51 seconds |
| Started | May 23 01:14:43 PM PDT 24 |
| Finished | May 23 01:41:57 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-93cfc42c-b7c6-442c-96c7-e45d38a78229 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2041605939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2041605939 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1796927382 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 337008550000 ps |
| CPU time | 743.95 seconds |
| Started | May 23 01:14:41 PM PDT 24 |
| Finished | May 23 01:44:52 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-55f48610-b02d-4eb0-9498-d1945a88362d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1796927382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1796927382 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2790581138 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336555650000 ps |
| CPU time | 889.05 seconds |
| Started | May 23 02:57:48 PM PDT 24 |
| Finished | May 23 03:35:16 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-2af8da7f-2e6b-4919-bed6-b71e311f2fa2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2790581138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2790581138 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1237910619 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336608590000 ps |
| CPU time | 918.95 seconds |
| Started | May 23 02:57:50 PM PDT 24 |
| Finished | May 23 03:36:49 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-142a2f75-694a-4b6a-b097-4049c2233ad5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1237910619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1237910619 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1837043438 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337130850000 ps |
| CPU time | 693.71 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:26:39 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-48b15be6-d447-49bd-b834-5e7301a40dbf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1837043438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1837043438 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.837732085 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336684070000 ps |
| CPU time | 886 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:35:23 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-b0a60275-b6b1-439b-a065-7b8e35c3f266 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=837732085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.837732085 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1073223591 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 337035050000 ps |
| CPU time | 642.25 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:24:37 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-99ed465c-a218-4dff-8907-400654a4ddcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1073223591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1073223591 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1774411097 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 337057490000 ps |
| CPU time | 867.29 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:34:14 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-a31a4c8d-7eaf-4aa8-91d5-ee07161fc5ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1774411097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1774411097 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.440746184 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 337085430000 ps |
| CPU time | 696.67 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:26:35 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-ba5e19c8-fdc0-472e-b9ae-055a6263abc8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=440746184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.440746184 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1128896477 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 336965110000 ps |
| CPU time | 836.38 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:31:56 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-3c7ea4ef-f70e-48f3-af64-569cc960ab61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1128896477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1128896477 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3520079522 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336705870000 ps |
| CPU time | 778.69 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:29:47 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-83c6d165-bb33-44de-ae70-d7b8df4fd306 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3520079522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3520079522 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3743046121 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336396390000 ps |
| CPU time | 695.69 seconds |
| Started | May 23 02:57:59 PM PDT 24 |
| Finished | May 23 03:27:00 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-5eddd211-c381-460e-a58e-9d3abb2d92fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3743046121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3743046121 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1125591031 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336843310000 ps |
| CPU time | 774.03 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:29:27 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-34347278-bdb5-4f58-acfd-009e57db1d3e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1125591031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1125591031 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3103350702 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336438450000 ps |
| CPU time | 882.38 seconds |
| Started | May 23 02:57:48 PM PDT 24 |
| Finished | May 23 03:35:00 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-618c327c-ad00-425c-91c2-9f11331dc90a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3103350702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3103350702 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.892159168 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336515150000 ps |
| CPU time | 763.42 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:29:33 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-bd6634db-f24e-44c7-9180-c79315c32496 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=892159168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.892159168 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1571558524 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336632850000 ps |
| CPU time | 831.93 seconds |
| Started | May 23 02:57:59 PM PDT 24 |
| Finished | May 23 03:31:40 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-0ffe15e5-3445-4e0a-b104-b7530f147bac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1571558524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1571558524 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.237364737 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336888490000 ps |
| CPU time | 862.81 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:34:09 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-9108e16c-1624-4bef-a07c-531bcbfb4749 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=237364737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.237364737 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.740118287 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336606890000 ps |
| CPU time | 837.18 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:31:58 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-1ab62af1-c3ef-4321-b875-4cdbfda4a0a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=740118287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.740118287 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.981773695 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336964630000 ps |
| CPU time | 954.38 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:37:39 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-e5edbc62-ede2-4ef1-85a1-479f89c8591b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=981773695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.981773695 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1222472537 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336739370000 ps |
| CPU time | 631.13 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:24:21 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-cdbda287-a7f8-4cf1-9ae8-ed5a5131c3c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1222472537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1222472537 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.99942103 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 336696430000 ps |
| CPU time | 761.36 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:29:31 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-37561643-1575-4262-81e1-865b11cb3da8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=99942103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.99942103 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2132635325 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 337023050000 ps |
| CPU time | 717.4 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:27:23 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-785c27fa-20d2-4846-a06d-3237493363d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2132635325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2132635325 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3126118777 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336428330000 ps |
| CPU time | 866.05 seconds |
| Started | May 23 02:58:02 PM PDT 24 |
| Finished | May 23 03:32:57 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-26b478ae-e3ef-4687-b848-e648f010351c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3126118777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3126118777 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1201534302 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336770050000 ps |
| CPU time | 829.74 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:31:42 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-00bf4caa-f422-4897-9e64-bbc1c1ad67be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1201534302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1201534302 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1940018080 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336756570000 ps |
| CPU time | 888.9 seconds |
| Started | May 23 02:57:51 PM PDT 24 |
| Finished | May 23 03:35:57 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-4a48fcbf-e33e-49fe-ae2f-7f80f49708b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1940018080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1940018080 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2203785633 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336758290000 ps |
| CPU time | 760.62 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:29:26 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-b455afae-a694-411e-a491-40cdd1f6e3b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2203785633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2203785633 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3867590415 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336891450000 ps |
| CPU time | 857.39 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 03:33:28 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-50dcc845-b69b-457f-be48-75f7594afe78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3867590415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3867590415 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4159318964 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336583810000 ps |
| CPU time | 766.73 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:29:37 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-9419301b-ff0e-410a-b8f4-0c6d34e2f22e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4159318964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4159318964 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.191307827 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336990850000 ps |
| CPU time | 867.55 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 03:32:56 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-22d9239d-5cba-4694-a9e6-9318084d16af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=191307827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.191307827 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2872078078 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336714370000 ps |
| CPU time | 669.67 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 03:26:04 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-6c6b27a8-a25c-4c02-ac8b-bae559d90d58 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2872078078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2872078078 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2671022592 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336447470000 ps |
| CPU time | 845.35 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:33:16 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-72315739-4fa1-45ec-971d-20b081c98f93 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2671022592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2671022592 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3478727697 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336602310000 ps |
| CPU time | 853.85 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:33:27 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-3f9a752e-3a0c-49e5-aa66-25e5c00af2e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3478727697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3478727697 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.273295488 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336754090000 ps |
| CPU time | 799.72 seconds |
| Started | May 23 02:58:05 PM PDT 24 |
| Finished | May 23 03:31:10 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-79a39a13-4d50-42bb-ba9b-c01a837ba519 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=273295488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.273295488 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3328678293 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336440850000 ps |
| CPU time | 792.9 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:31:18 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-5998419a-f3a6-4ebe-84f8-8514c960145d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3328678293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3328678293 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.6868264 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336646510000 ps |
| CPU time | 688.42 seconds |
| Started | May 23 02:58:04 PM PDT 24 |
| Finished | May 23 03:27:11 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-09a20f48-a83e-4a5e-9f03-68a4c183814b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=6868264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.6868264 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.758744468 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 337044490000 ps |
| CPU time | 920.34 seconds |
| Started | May 23 02:57:50 PM PDT 24 |
| Finished | May 23 03:36:47 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-f436ecba-5c96-4721-af69-38eea22ecc96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=758744468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.758744468 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1244811773 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336880450000 ps |
| CPU time | 794.37 seconds |
| Started | May 23 02:58:03 PM PDT 24 |
| Finished | May 23 03:31:14 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-93f76d00-f2f0-4260-b77b-804e0972800d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1244811773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1244811773 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2664010211 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 337114710000 ps |
| CPU time | 689.25 seconds |
| Started | May 23 02:58:06 PM PDT 24 |
| Finished | May 23 03:26:59 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-2b609762-35b4-44ca-9e2f-1bf74dc75c61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2664010211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2664010211 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3746889573 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336341630000 ps |
| CPU time | 727.03 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:27:41 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-70ff71c4-5146-4f18-a859-2d0fa016bab1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3746889573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3746889573 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3986840473 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336672370000 ps |
| CPU time | 955.55 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:37:28 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-bd64dae9-5635-4233-843e-13e6a8b9a356 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3986840473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3986840473 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1313376770 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336833710000 ps |
| CPU time | 659.4 seconds |
| Started | May 23 02:57:59 PM PDT 24 |
| Finished | May 23 03:25:23 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-e5d54fe7-657c-4f80-bcec-25b343fec136 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1313376770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1313376770 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2272199631 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336784250000 ps |
| CPU time | 864.88 seconds |
| Started | May 23 02:58:02 PM PDT 24 |
| Finished | May 23 03:33:42 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-3e2993e3-08e9-4ef3-b3e2-a1775fe89b36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2272199631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2272199631 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2777443548 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337055950000 ps |
| CPU time | 662.34 seconds |
| Started | May 23 02:57:58 PM PDT 24 |
| Finished | May 23 03:25:22 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-71a032ee-a9d3-4085-8b70-a9516f419003 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2777443548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2777443548 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3123612496 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336780190000 ps |
| CPU time | 855.49 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:32:45 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-c1ee3433-209c-47a2-afd7-7037c51ede26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3123612496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3123612496 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2992824092 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 337099310000 ps |
| CPU time | 866.09 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:33:52 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-2ec532b8-dfd1-4834-a0a6-332cca698569 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2992824092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2992824092 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4261199262 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336387770000 ps |
| CPU time | 717.02 seconds |
| Started | May 23 02:58:00 PM PDT 24 |
| Finished | May 23 03:27:25 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-5f382aef-5f11-45ac-a179-da822af2eb34 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4261199262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.4261199262 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3393237271 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336928910000 ps |
| CPU time | 923.58 seconds |
| Started | May 23 02:57:51 PM PDT 24 |
| Finished | May 23 03:37:03 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-13d61af1-630f-42ce-b431-85155a749bd8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3393237271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3393237271 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4070445707 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 337120530000 ps |
| CPU time | 708.92 seconds |
| Started | May 23 02:57:59 PM PDT 24 |
| Finished | May 23 03:27:03 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-a7b64ef0-4257-4615-a2bf-d750f7462836 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4070445707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.4070445707 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.403198806 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336307530000 ps |
| CPU time | 811.71 seconds |
| Started | May 23 02:57:59 PM PDT 24 |
| Finished | May 23 03:30:47 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-96b71634-c2b1-47af-ba80-6b084cb8ff62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=403198806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.403198806 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1482060327 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336496710000 ps |
| CPU time | 812.04 seconds |
| Started | May 23 02:58:01 PM PDT 24 |
| Finished | May 23 03:31:12 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-0de4fb0e-aad0-40f5-94fa-5775e2eca216 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1482060327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1482060327 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2812885902 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 336324890000 ps |
| CPU time | 774.26 seconds |
| Started | May 23 02:57:59 PM PDT 24 |
| Finished | May 23 03:29:48 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-5c81f43f-bf68-49b6-a0e7-cdaaf092b4ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2812885902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2812885902 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3524983255 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1469750000 ps |
| CPU time | 5.14 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-806aec16-7e3f-433d-8636-20cfaebf4832 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3524983255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3524983255 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3381655007 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1534510000 ps |
| CPU time | 5.36 seconds |
| Started | May 23 03:21:04 PM PDT 24 |
| Finished | May 23 03:21:24 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-60202724-b3f0-4406-a00a-015c47667b2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3381655007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3381655007 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2869428367 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1555370000 ps |
| CPU time | 5.64 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:30 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-dbdb4908-0a01-4dd2-9716-aa2a839c1896 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2869428367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2869428367 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.825013320 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1475590000 ps |
| CPU time | 5.08 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-592c3532-b1f1-4bae-9858-7ebf4565290c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=825013320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.825013320 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1809230447 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1396450000 ps |
| CPU time | 6.24 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-d4ade0c3-c57a-4483-9ebe-4bff263abaca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1809230447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1809230447 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4006414096 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1453390000 ps |
| CPU time | 3.66 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:23 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-1d8a1012-9b22-4e92-a81b-b06365f4a5ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4006414096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4006414096 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1084509594 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1457150000 ps |
| CPU time | 4.82 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:25 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-25a66d22-c478-4aa3-8a73-f00580c361ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1084509594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1084509594 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3989909455 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1428270000 ps |
| CPU time | 3.78 seconds |
| Started | May 23 03:21:04 PM PDT 24 |
| Finished | May 23 03:21:19 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-752c857f-6d92-4f56-8f47-5b4cb7261cb3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3989909455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3989909455 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.748920395 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1500490000 ps |
| CPU time | 4.52 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:23 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-7b02fe5b-5885-43a9-985a-d43fa80ee6db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=748920395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.748920395 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.376920515 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1549390000 ps |
| CPU time | 5.34 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-01ffa37b-a9ca-46b2-8225-27174b6ff999 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=376920515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.376920515 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1642802826 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1532250000 ps |
| CPU time | 5.36 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:31 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-e54fa333-61c5-4ee3-b986-9af3509f1d53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1642802826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1642802826 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4175637926 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1243130000 ps |
| CPU time | 3.37 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-10ff3dfa-ea30-41eb-865f-77c9cda27c37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4175637926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.4175637926 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3460889207 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1373210000 ps |
| CPU time | 4.85 seconds |
| Started | May 23 03:21:03 PM PDT 24 |
| Finished | May 23 03:21:20 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-35eb81d4-876c-4c1f-94de-bb45be938236 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3460889207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3460889207 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3919900543 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1283630000 ps |
| CPU time | 3.15 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-685ad85b-cdb6-47fa-a173-6e0b0849b128 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3919900543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3919900543 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.448163341 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1578810000 ps |
| CPU time | 3.87 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:24 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-fb996936-07f8-46a0-b59e-c13211cfc70f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=448163341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.448163341 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3360003392 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1599530000 ps |
| CPU time | 4.97 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-25305665-17cc-425e-8c12-15c9ea594794 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3360003392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3360003392 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3330096108 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1491550000 ps |
| CPU time | 4.81 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-3daba95f-e5bd-43e2-a5a8-a6c2f1a3b900 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3330096108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3330096108 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2189607244 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1542610000 ps |
| CPU time | 5.54 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-158dc1b4-38f6-4386-b588-3c2ad0bb6246 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2189607244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2189607244 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1665315080 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1439330000 ps |
| CPU time | 4.26 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:23 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-856ad807-38a2-4e26-9712-08b70ac7ff90 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1665315080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1665315080 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2901069703 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1418550000 ps |
| CPU time | 4.83 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-3fe0d538-cc5d-4972-acc6-f1f23408398a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2901069703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2901069703 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3662761847 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1331890000 ps |
| CPU time | 3.6 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-3c1871e5-be09-4cf5-bc22-f64f647f0f22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3662761847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3662761847 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2034463530 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1422430000 ps |
| CPU time | 4.54 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-52b402ff-cc82-4b24-9d16-3aa0caaab8ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2034463530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2034463530 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1003169208 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1579950000 ps |
| CPU time | 4.99 seconds |
| Started | May 23 03:20:57 PM PDT 24 |
| Finished | May 23 03:21:14 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-be7515eb-29aa-49a2-9b58-484419e0cf7f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1003169208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1003169208 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2095380536 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1441010000 ps |
| CPU time | 4.94 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-8588a7b2-8ced-4ffd-a404-7b5f0fd4b908 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2095380536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2095380536 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2475191144 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1567190000 ps |
| CPU time | 4.89 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:25 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-4138e0bf-d0b5-43eb-81d9-21e945258a0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2475191144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2475191144 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1421907256 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1487790000 ps |
| CPU time | 4.93 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-3243bbb6-18d5-4851-88cc-c8979b3f7b0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1421907256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1421907256 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.502764485 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1195070000 ps |
| CPU time | 4.37 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-8650baf0-6777-4b2c-b1c5-fc04ca3e022d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=502764485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.502764485 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3204945149 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1562390000 ps |
| CPU time | 4.94 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-3e1e8b2c-be44-4e01-92b9-d941e5180bca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3204945149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3204945149 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.895601325 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1486370000 ps |
| CPU time | 5.05 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-30ed288b-c2ed-4c61-9a4b-274f32d46e36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=895601325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.895601325 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3908585242 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1507170000 ps |
| CPU time | 4.84 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164728 kb |
| Host | smart-70668b9e-4fb2-4578-abf9-cf438573140b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3908585242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3908585242 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4185083527 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1433190000 ps |
| CPU time | 4.76 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-5e577555-f456-4fdc-8a93-8396eb5f7cc0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4185083527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.4185083527 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3795838813 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1507590000 ps |
| CPU time | 5.63 seconds |
| Started | May 23 03:21:09 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-375fdd71-8cf1-46a2-b9ca-b784d8c81403 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3795838813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3795838813 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2838305943 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1406770000 ps |
| CPU time | 4.45 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-29c61edc-999b-40e2-bf42-452ba1e68667 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2838305943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2838305943 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1890938407 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1489490000 ps |
| CPU time | 4.84 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-e37e7622-15cc-438d-a6e9-1daf5b2e61a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1890938407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1890938407 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3264920701 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1544050000 ps |
| CPU time | 6.83 seconds |
| Started | May 23 03:21:04 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-874c3bc3-6c2e-4745-a876-71b8d067e373 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3264920701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3264920701 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2180721049 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1491190000 ps |
| CPU time | 4.94 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-ac6a246f-e50f-450c-ad36-79d0db7e2127 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2180721049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2180721049 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2200827664 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1405870000 ps |
| CPU time | 4.36 seconds |
| Started | May 23 03:21:09 PM PDT 24 |
| Finished | May 23 03:21:29 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-b55e1764-361b-4576-836b-25d1fb328981 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2200827664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2200827664 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2762209602 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1541150000 ps |
| CPU time | 5.26 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-bb2d13aa-96c7-4d1c-8265-51b07e3c3e15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2762209602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2762209602 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3670802547 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1453890000 ps |
| CPU time | 3.95 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:28 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-3780aa82-678c-492e-95ab-dec0b1f8dd4c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3670802547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3670802547 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.32287377 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1583950000 ps |
| CPU time | 4.41 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:29 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-63256916-c188-4d04-8468-ae270bc500b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=32287377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.32287377 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3432999928 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1589490000 ps |
| CPU time | 5.88 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:32 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-db33bf9e-0dc7-45b5-a849-bc3ada47eea8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3432999928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3432999928 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.338993120 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1443910000 ps |
| CPU time | 5.62 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:31 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-c22e6120-bef6-42a2-b404-3cb7301eb05a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=338993120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.338993120 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1320182606 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1379310000 ps |
| CPU time | 4.76 seconds |
| Started | May 23 03:21:09 PM PDT 24 |
| Finished | May 23 03:21:32 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-7bde62c4-3272-4349-828d-92d6d55e70d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1320182606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1320182606 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3289052501 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1488390000 ps |
| CPU time | 4.12 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:29 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-e52a4920-e0d5-4487-905e-08974bc062d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3289052501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3289052501 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.30918349 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1439810000 ps |
| CPU time | 5.27 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-88b5573d-2218-404b-9a65-e9af609d9bc6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=30918349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.30918349 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.532117129 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1490730000 ps |
| CPU time | 4.8 seconds |
| Started | May 23 03:21:05 PM PDT 24 |
| Finished | May 23 03:21:25 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-18ce55cb-16f0-4793-8a8d-a02778a55ef3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=532117129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.532117129 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.57326569 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1364290000 ps |
| CPU time | 4.62 seconds |
| Started | May 23 03:21:04 PM PDT 24 |
| Finished | May 23 03:21:20 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-fe5de594-b896-4e27-8f8b-e548d8d56b38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=57326569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.57326569 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.535092715 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1562310000 ps |
| CPU time | 5.35 seconds |
| Started | May 23 03:21:04 PM PDT 24 |
| Finished | May 23 03:21:21 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-50df486c-9671-45da-84b0-7e64bbcb6e9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=535092715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.535092715 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3469607827 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1499130000 ps |
| CPU time | 3.66 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-846755ff-2cfb-4700-b028-fd3a9365d697 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3469607827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3469607827 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1596991499 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1525870000 ps |
| CPU time | 5.63 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:32 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-3f8ee829-cc19-41ad-9824-81f07ff5d185 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1596991499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1596991499 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1230991713 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1450050000 ps |
| CPU time | 4.83 seconds |
| Started | May 23 03:21:11 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-596b0412-25fa-44e2-8eeb-8da26a26f2c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1230991713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1230991713 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3370168652 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1466210000 ps |
| CPU time | 4.82 seconds |
| Started | May 23 03:21:06 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-9d4dea3e-c2c2-435a-83b1-3310779d28f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3370168652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3370168652 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3554997109 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1608530000 ps |
| CPU time | 4.91 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:31 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-f95ddd48-4acb-4b39-bf86-a49f0f558fe2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3554997109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3554997109 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4110285569 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1389150000 ps |
| CPU time | 4.79 seconds |
| Started | May 23 03:21:11 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-af18d2a3-36a6-4081-be56-343669da2ba5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4110285569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.4110285569 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2580537282 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1360710000 ps |
| CPU time | 4.37 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:30 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-d68e0619-ee74-4a1d-9813-398c6b632963 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2580537282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2580537282 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2131253986 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1495630000 ps |
| CPU time | 5.92 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:30 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-36849414-f99f-4fa6-a729-8d55f3905c8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2131253986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2131253986 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1178998421 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1080990000 ps |
| CPU time | 3.41 seconds |
| Started | May 23 03:21:07 PM PDT 24 |
| Finished | May 23 03:21:26 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-6ae4eba7-c772-451f-9c3c-9ece0f2fa6ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1178998421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1178998421 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1309142561 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1562650000 ps |
| CPU time | 4.77 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:30 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-cbbcd754-2255-4e0c-9cb9-0315a32f44e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1309142561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1309142561 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.4023906227 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1179970000 ps |
| CPU time | 3.44 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-011511d0-c299-4b9e-9fd2-9c5dc6a8eaef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4023906227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.4023906227 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.536993278 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1172270000 ps |
| CPU time | 3.58 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:27 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-b1c480ed-9963-4ea6-822a-1000aab5d268 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=536993278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.536993278 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2956816020 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1568090000 ps |
| CPU time | 4.51 seconds |
| Started | May 23 03:21:28 PM PDT 24 |
| Finished | May 23 03:21:42 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-b70e13a8-e0f7-431f-ba86-8eb052f197d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2956816020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2956816020 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.71577334 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1486710000 ps |
| CPU time | 4.27 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:29 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-ef2c3fdf-ec91-4d83-a8d8-977075e9f6b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=71577334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.71577334 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1998932152 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1355290000 ps |
| CPU time | 3.5 seconds |
| Started | May 23 03:21:29 PM PDT 24 |
| Finished | May 23 03:21:40 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-cca59ea5-2297-4510-85ad-c91f5c0d7aba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1998932152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1998932152 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1906560706 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1453190000 ps |
| CPU time | 3.89 seconds |
| Started | May 23 03:21:21 PM PDT 24 |
| Finished | May 23 03:21:36 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-4672b412-e323-4642-a89d-43aa76099831 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1906560706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1906560706 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3176871752 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1434890000 ps |
| CPU time | 4.87 seconds |
| Started | May 23 03:21:20 PM PDT 24 |
| Finished | May 23 03:21:37 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-edc4f29b-6e7c-4906-8f7c-30c9c4e705d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3176871752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3176871752 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4004456292 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1426550000 ps |
| CPU time | 3.17 seconds |
| Started | May 23 03:21:21 PM PDT 24 |
| Finished | May 23 03:21:34 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-1765d597-68f8-4949-9c0b-3622e955e345 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4004456292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4004456292 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3787874333 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1509370000 ps |
| CPU time | 4.68 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:41 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-55b0f1e4-841c-4f20-be1f-6fc1ffaeae02 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3787874333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3787874333 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.71332 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1510830000 ps |
| CPU time | 5.48 seconds |
| Started | May 23 03:21:22 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-79e91bbc-1257-4a18-ad1e-e4f491e86022 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=71332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.71332 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2336038327 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1420850000 ps |
| CPU time | 5.44 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:43 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-5248a7c1-b71a-4880-b6cc-202a994ef4d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2336038327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2336038327 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3674475528 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1456070000 ps |
| CPU time | 3.73 seconds |
| Started | May 23 03:21:22 PM PDT 24 |
| Finished | May 23 03:21:36 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-8810f874-3f30-45c9-bd5e-ae05310cc5ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3674475528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3674475528 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1067680753 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1385350000 ps |
| CPU time | 5.26 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:43 PM PDT 24 |
| Peak memory | 164732 kb |
| Host | smart-039370ec-8cf6-4bdf-9270-feef3158bc0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1067680753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1067680753 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1712325154 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1484130000 ps |
| CPU time | 4.06 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-6b63405c-81e3-42ad-9d94-dadb27b248bc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1712325154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1712325154 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2540005513 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1482670000 ps |
| CPU time | 4.04 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:29 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-8629d064-4555-4faa-8534-1eecd00b47da |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2540005513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2540005513 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2413352476 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1550970000 ps |
| CPU time | 4.46 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:40 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-86c6e3b6-40e6-4350-a5f7-4cd9d69366e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2413352476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2413352476 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.309597186 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1526250000 ps |
| CPU time | 3.59 seconds |
| Started | May 23 03:21:22 PM PDT 24 |
| Finished | May 23 03:21:36 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-999478a0-d3e0-4cea-828a-61669eb6d3b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=309597186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.309597186 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.890375827 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1539230000 ps |
| CPU time | 5.9 seconds |
| Started | May 23 03:21:26 PM PDT 24 |
| Finished | May 23 03:21:43 PM PDT 24 |
| Peak memory | 165000 kb |
| Host | smart-6dde5a8e-f6ee-4c23-9d62-ce4bdcd8beef |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=890375827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.890375827 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2693120284 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1554490000 ps |
| CPU time | 4.04 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-0283db0e-e16a-4545-ba9c-37a7536cbf96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2693120284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2693120284 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2663371021 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1412930000 ps |
| CPU time | 5.35 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:43 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-b9ec7ddd-0b1b-4582-b148-00f44a9f013c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2663371021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2663371021 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3547619723 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1497970000 ps |
| CPU time | 4.3 seconds |
| Started | May 23 03:21:27 PM PDT 24 |
| Finished | May 23 03:21:41 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-d0ec1b09-f373-4b00-b110-c4dd022e6639 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3547619723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3547619723 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2211500973 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1612230000 ps |
| CPU time | 5.04 seconds |
| Started | May 23 03:21:22 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-47148fbe-371c-459b-93e3-74db703ddc51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2211500973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2211500973 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.868100170 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1481590000 ps |
| CPU time | 4.05 seconds |
| Started | May 23 03:21:21 PM PDT 24 |
| Finished | May 23 03:21:36 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-103872dd-48e8-42af-a4d4-311881808d3b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=868100170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.868100170 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4168399008 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1469450000 ps |
| CPU time | 5.15 seconds |
| Started | May 23 03:21:22 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-49155058-16af-4c39-ab57-3d81ad5aec18 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4168399008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.4168399008 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2124490239 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1376690000 ps |
| CPU time | 4.31 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-9df3d04a-70d1-4c78-997a-93f8f050a802 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2124490239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2124490239 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2604657580 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1641230000 ps |
| CPU time | 4.83 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:32 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-51c1681e-cc0d-4e6b-b9d7-a83bf32c4221 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2604657580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2604657580 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.661470624 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1441890000 ps |
| CPU time | 3.71 seconds |
| Started | May 23 03:21:21 PM PDT 24 |
| Finished | May 23 03:21:35 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-7ad986c9-bdd7-432e-9b2e-29018b16c4be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=661470624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.661470624 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1544561056 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1503610000 ps |
| CPU time | 3.58 seconds |
| Started | May 23 03:21:22 PM PDT 24 |
| Finished | May 23 03:21:36 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-6756d515-31cf-410c-afc4-b931b4dd2bb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1544561056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1544561056 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.426728318 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1407270000 ps |
| CPU time | 4.62 seconds |
| Started | May 23 03:21:21 PM PDT 24 |
| Finished | May 23 03:21:38 PM PDT 24 |
| Peak memory | 164996 kb |
| Host | smart-2da4dde1-a8ce-49d8-846a-903b388ee1e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=426728318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.426728318 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3580256244 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1527450000 ps |
| CPU time | 3.23 seconds |
| Started | May 23 03:21:30 PM PDT 24 |
| Finished | May 23 03:21:41 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-117b8637-f0d0-43cb-ae84-c14b0fc44d8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3580256244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3580256244 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4205845402 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1321830000 ps |
| CPU time | 3.86 seconds |
| Started | May 23 03:21:24 PM PDT 24 |
| Finished | May 23 03:21:38 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-eedc4bc0-e9e3-4f64-9f98-36553f7e0dcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4205845402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4205845402 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3851857434 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1629030000 ps |
| CPU time | 5.95 seconds |
| Started | May 23 03:21:20 PM PDT 24 |
| Finished | May 23 03:21:40 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-33cf7bd0-ccec-4fc3-837c-99becf3ea1c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3851857434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3851857434 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2105072811 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1515630000 ps |
| CPU time | 6.13 seconds |
| Started | May 23 03:21:26 PM PDT 24 |
| Finished | May 23 03:21:44 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-b0c103f6-93e7-49e7-bb3e-ee099865317b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2105072811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2105072811 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.408775920 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1496590000 ps |
| CPU time | 5.23 seconds |
| Started | May 23 03:21:21 PM PDT 24 |
| Finished | May 23 03:21:39 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-0001d750-7aa6-407a-a3f7-3b70c30d42a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=408775920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.408775920 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.809183135 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1377750000 ps |
| CPU time | 4.04 seconds |
| Started | May 23 03:21:27 PM PDT 24 |
| Finished | May 23 03:21:41 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-0066efae-462c-4fbc-8ed7-7dabfc73d895 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=809183135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.809183135 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1795472050 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1426150000 ps |
| CPU time | 3.16 seconds |
| Started | May 23 03:21:25 PM PDT 24 |
| Finished | May 23 03:21:37 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-7128339c-d9c8-4c86-a9df-a27cd6a4787b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1795472050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1795472050 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3741782978 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1495330000 ps |
| CPU time | 4.49 seconds |
| Started | May 23 03:21:08 PM PDT 24 |
| Finished | May 23 03:21:29 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-e9ae4c71-879f-4d6a-bf5e-4f4b9071a6e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3741782978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3741782978 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2175020521 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1568190000 ps |
| CPU time | 5.56 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-da07021a-0739-47ee-bc48-278f1183a328 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2175020521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2175020521 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1266416421 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1447810000 ps |
| CPU time | 5.38 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-c3e9fcb4-192d-46ac-afa3-e6a5355e707a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1266416421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1266416421 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2534565700 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1626270000 ps |
| CPU time | 5.6 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:35 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-e9add625-b131-4f93-8c42-72d85fc5319b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2534565700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2534565700 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1965978552 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1486990000 ps |
| CPU time | 5.38 seconds |
| Started | May 23 03:21:10 PM PDT 24 |
| Finished | May 23 03:21:33 PM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-8e930e9c-82eb-4f46-90e9-af8e5838724c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1965978552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1965978552 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
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