| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1129600012 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3251979669 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2143480180 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.807807348 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.827042372 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.926346003 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3307601462 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3669382640 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1577397198 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1445237854 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.176696201 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1627626431 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1947668330 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3513868274 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4279639329 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.872465383 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3001695299 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1733165094 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2361817379 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2806858490 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.948176033 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.512445653 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4120571521 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2812863078 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1073017063 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1978006137 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1186479893 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2760801795 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2768237316 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4213925209 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2953249417 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2578257793 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.883304356 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2203186281 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1494199319 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1159349276 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1224273251 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1172653825 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3383570732 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.461880133 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2197062306 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.838402445 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4003191226 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3045211979 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3393802157 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1585448602 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2318986075 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.642812931 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1051404907 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.699659365 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4101899483 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2157027499 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.251312199 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1270886143 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1957080630 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2679763708 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.157117523 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1306210933 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2002715027 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2634488568 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.854047576 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2952964348 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3120249898 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2420126279 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3524396280 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.793390538 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3661756537 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.487723574 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3775608975 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2063920907 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.878879277 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2098033445 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2788293775 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1017351846 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4240390199 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.22952076 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.539249806 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3524793589 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2592552080 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3908186858 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1155044087 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1707936625 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4084218078 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3807267717 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2507018496 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.118713930 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2456642639 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1743871889 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1000922377 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3954154373 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3291055998 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1276676227 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2980003643 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.861807797 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3309479434 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2743867644 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2380901998 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2231268449 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3689985901 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.593378723 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1382942821 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1980989253 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2081708978 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2369463525 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.322789666 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2270760703 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3023482278 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.811623225 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2089336159 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2982644648 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2548889987 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1348985752 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4605247 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1569452216 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.159722177 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1251802839 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.391388327 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.93103195 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.311612666 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2309983989 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3439014114 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.459524138 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2827686310 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.35817767 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.930713934 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3258298263 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2681943940 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2041919640 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1153543455 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3088869723 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2820157433 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1660522865 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.20903293 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3809062266 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1720438956 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.129113397 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.791597068 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1755480095 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2597946194 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3184251986 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1705161896 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1367771573 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.890174013 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3416344158 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.123413214 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2316722598 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1498393245 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1539305030 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3102184413 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3457516728 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2843523509 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.502494102 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1790782107 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3584702538 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1192277577 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.478641152 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2419266060 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2588213835 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3736877557 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1444272846 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3416765792 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2499179672 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2729794579 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4051876733 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.437476775 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1559245830 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3436196005 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1408194765 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1324118301 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3814114987 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3867538678 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2978777815 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2394074566 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1989125480 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.952561832 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.114488013 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3882826119 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1574314132 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1881723816 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1683859538 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.159875179 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.179798659 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2890201610 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.298135450 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3723370922 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2971015972 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1838546431 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1487696018 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.950870765 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4149125408 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1549932635 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2802828372 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.448498662 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2906981625 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.813557556 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.648055494 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.344045501 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1395478084 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2967454670 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.638086416 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3814114987 | May 28 01:09:33 PM PDT 24 | May 28 01:09:46 PM PDT 24 | 1361590000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1408194765 | May 28 01:09:31 PM PDT 24 | May 28 01:09:43 PM PDT 24 | 1519150000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1129600012 | May 28 01:09:35 PM PDT 24 | May 28 01:09:49 PM PDT 24 | 1514410000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.159875179 | May 28 01:09:27 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1412610000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.813557556 | May 28 01:09:44 PM PDT 24 | May 28 01:09:56 PM PDT 24 | 1458910000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2499179672 | May 28 01:09:14 PM PDT 24 | May 28 01:09:28 PM PDT 24 | 1262690000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1487696018 | May 28 01:09:20 PM PDT 24 | May 28 01:09:36 PM PDT 24 | 1264430000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1324118301 | May 28 01:09:32 PM PDT 24 | May 28 01:09:44 PM PDT 24 | 1270550000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1395478084 | May 28 01:09:19 PM PDT 24 | May 28 01:09:38 PM PDT 24 | 1543630000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.114488013 | May 28 01:09:23 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1583110000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.344045501 | May 28 01:09:17 PM PDT 24 | May 28 01:09:32 PM PDT 24 | 1497170000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2890201610 | May 28 01:09:24 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1488550000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.179798659 | May 28 01:09:21 PM PDT 24 | May 28 01:09:38 PM PDT 24 | 1379110000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1192277577 | May 28 01:09:35 PM PDT 24 | May 28 01:09:47 PM PDT 24 | 1294810000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1549932635 | May 28 01:09:21 PM PDT 24 | May 28 01:09:38 PM PDT 24 | 1533630000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1790782107 | May 28 01:09:36 PM PDT 24 | May 28 01:09:48 PM PDT 24 | 1329750000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.502494102 | May 28 01:09:36 PM PDT 24 | May 28 01:09:48 PM PDT 24 | 1515670000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.478641152 | May 28 01:09:23 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1424850000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.950870765 | May 28 01:09:23 PM PDT 24 | May 28 01:09:42 PM PDT 24 | 1573790000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.952561832 | May 28 01:09:33 PM PDT 24 | May 28 01:09:46 PM PDT 24 | 1467490000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1444272846 | May 28 01:09:26 PM PDT 24 | May 28 01:09:38 PM PDT 24 | 1232170000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1559245830 | May 28 01:09:24 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1231310000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1989125480 | May 28 01:09:23 PM PDT 24 | May 28 01:09:38 PM PDT 24 | 1285990000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2802828372 | May 28 01:09:18 PM PDT 24 | May 28 01:09:33 PM PDT 24 | 1421850000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4051876733 | May 28 01:09:18 PM PDT 24 | May 28 01:09:37 PM PDT 24 | 1545410000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.437476775 | May 28 01:09:22 PM PDT 24 | May 28 01:09:37 PM PDT 24 | 1428550000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2967454670 | May 28 01:09:46 PM PDT 24 | May 28 01:09:57 PM PDT 24 | 1285310000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2906981625 | May 28 01:09:28 PM PDT 24 | May 28 01:09:42 PM PDT 24 | 1519510000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2394074566 | May 28 01:09:27 PM PDT 24 | May 28 01:09:43 PM PDT 24 | 1397630000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1574314132 | May 28 01:09:31 PM PDT 24 | May 28 01:09:45 PM PDT 24 | 1510430000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3436196005 | May 28 01:09:28 PM PDT 24 | May 28 01:09:43 PM PDT 24 | 1589190000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2978777815 | May 28 01:09:28 PM PDT 24 | May 28 01:09:43 PM PDT 24 | 1451010000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1683859538 | May 28 01:09:20 PM PDT 24 | May 28 01:09:34 PM PDT 24 | 1535610000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2971015972 | May 28 01:09:22 PM PDT 24 | May 28 01:09:38 PM PDT 24 | 1357310000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3736877557 | May 28 01:09:38 PM PDT 24 | May 28 01:09:48 PM PDT 24 | 1490830000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1838546431 | May 28 01:09:34 PM PDT 24 | May 28 01:09:44 PM PDT 24 | 1222390000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3882826119 | May 28 01:09:24 PM PDT 24 | May 28 01:09:39 PM PDT 24 | 1590070000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.648055494 | May 28 01:09:27 PM PDT 24 | May 28 01:09:46 PM PDT 24 | 1458190000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2419266060 | May 28 01:09:31 PM PDT 24 | May 28 01:09:45 PM PDT 24 | 1427910000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.638086416 | May 28 01:09:21 PM PDT 24 | May 28 01:09:36 PM PDT 24 | 1364870000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2588213835 | May 28 01:09:23 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1562090000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4149125408 | May 28 01:09:12 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 1594110000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2729794579 | May 28 01:09:20 PM PDT 24 | May 28 01:09:37 PM PDT 24 | 1328370000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1881723816 | May 28 01:09:24 PM PDT 24 | May 28 01:09:39 PM PDT 24 | 1402130000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.298135450 | May 28 01:09:30 PM PDT 24 | May 28 01:09:44 PM PDT 24 | 1493710000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3416765792 | May 28 01:09:25 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 1436870000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.448498662 | May 28 01:09:27 PM PDT 24 | May 28 01:09:43 PM PDT 24 | 1496890000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3867538678 | May 28 01:09:30 PM PDT 24 | May 28 01:09:44 PM PDT 24 | 1503710000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3723370922 | May 28 01:09:23 PM PDT 24 | May 28 01:09:36 PM PDT 24 | 1191150000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3584702538 | May 28 01:09:22 PM PDT 24 | May 28 01:09:39 PM PDT 24 | 1547830000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.807807348 | May 28 01:08:53 PM PDT 24 | May 28 01:09:06 PM PDT 24 | 1510830000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1153543455 | May 28 01:09:04 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 1530230000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1251802839 | May 28 01:09:06 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 1569750000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.459524138 | May 28 01:09:04 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 1544790000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.791597068 | May 28 01:08:59 PM PDT 24 | May 28 01:09:11 PM PDT 24 | 1569550000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3416344158 | May 28 01:08:48 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 1515150000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1498393245 | May 28 01:08:51 PM PDT 24 | May 28 01:09:01 PM PDT 24 | 1508890000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2820157433 | May 28 01:08:59 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 1538250000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1660522865 | May 28 01:08:51 PM PDT 24 | May 28 01:09:00 PM PDT 24 | 1492250000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.129113397 | May 28 01:09:08 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 1472710000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2548889987 | May 28 01:09:04 PM PDT 24 | May 28 01:09:16 PM PDT 24 | 1425790000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.35817767 | May 28 01:09:07 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 1514330000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2827686310 | May 28 01:08:57 PM PDT 24 | May 28 01:09:10 PM PDT 24 | 1260650000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4605247 | May 28 01:08:59 PM PDT 24 | May 28 01:09:13 PM PDT 24 | 1613050000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1367771573 | May 28 01:09:04 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 1609790000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1755480095 | May 28 01:08:57 PM PDT 24 | May 28 01:09:09 PM PDT 24 | 1456590000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.391388327 | May 28 01:08:50 PM PDT 24 | May 28 01:09:00 PM PDT 24 | 1444730000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1705161896 | May 28 01:09:06 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 1425870000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3102184413 | May 28 01:08:54 PM PDT 24 | May 28 01:09:06 PM PDT 24 | 1434670000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.930713934 | May 28 01:08:52 PM PDT 24 | May 28 01:09:03 PM PDT 24 | 1192930000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.93103195 | May 28 01:08:52 PM PDT 24 | May 28 01:09:04 PM PDT 24 | 1266150000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1539305030 | May 28 01:09:00 PM PDT 24 | May 28 01:09:11 PM PDT 24 | 1499810000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2982644648 | May 28 01:09:03 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 1531210000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2081708978 | May 28 01:09:10 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 1411550000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2270760703 | May 28 01:08:56 PM PDT 24 | May 28 01:09:09 PM PDT 24 | 1359130000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2316722598 | May 28 01:08:51 PM PDT 24 | May 28 01:09:02 PM PDT 24 | 1485710000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.311612666 | May 28 01:08:49 PM PDT 24 | May 28 01:08:58 PM PDT 24 | 1302850000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3439014114 | May 28 01:09:14 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 1468130000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1348985752 | May 28 01:08:54 PM PDT 24 | May 28 01:09:07 PM PDT 24 | 1241410000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2681943940 | May 28 01:09:01 PM PDT 24 | May 28 01:09:13 PM PDT 24 | 1417510000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2843523509 | May 28 01:08:56 PM PDT 24 | May 28 01:09:09 PM PDT 24 | 1453570000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3023482278 | May 28 01:09:11 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 1488170000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2041919640 | May 28 01:09:04 PM PDT 24 | May 28 01:09:15 PM PDT 24 | 1422690000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.159722177 | May 28 01:08:50 PM PDT 24 | May 28 01:09:03 PM PDT 24 | 1346170000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.20903293 | May 28 01:09:00 PM PDT 24 | May 28 01:09:11 PM PDT 24 | 1488170000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1720438956 | May 28 01:08:45 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 1526110000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2089336159 | May 28 01:08:55 PM PDT 24 | May 28 01:09:07 PM PDT 24 | 1538370000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3258298263 | May 28 01:09:01 PM PDT 24 | May 28 01:09:15 PM PDT 24 | 1477670000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3457516728 | May 28 01:08:54 PM PDT 24 | May 28 01:09:09 PM PDT 24 | 1560790000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3184251986 | May 28 01:08:52 PM PDT 24 | May 28 01:09:05 PM PDT 24 | 1426230000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2369463525 | May 28 01:09:04 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 1451230000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3809062266 | May 28 01:09:13 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 1553270000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2597946194 | May 28 01:09:07 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 1466490000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.811623225 | May 28 01:08:53 PM PDT 24 | May 28 01:09:05 PM PDT 24 | 1583230000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.890174013 | May 28 01:08:57 PM PDT 24 | May 28 01:09:08 PM PDT 24 | 1215550000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.123413214 | May 28 01:09:03 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 1623810000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2309983989 | May 28 01:08:53 PM PDT 24 | May 28 01:09:07 PM PDT 24 | 1488730000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.322789666 | May 28 01:09:10 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 1280130000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3088869723 | May 28 01:08:51 PM PDT 24 | May 28 01:09:04 PM PDT 24 | 1572350000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1569452216 | May 28 01:09:00 PM PDT 24 | May 28 01:09:10 PM PDT 24 | 1411630000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2002715027 | May 28 12:48:15 PM PDT 24 | May 28 01:13:16 PM PDT 24 | 337196430000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2743867644 | May 28 12:48:32 PM PDT 24 | May 28 01:17:56 PM PDT 24 | 336955570000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2507018496 | May 28 12:48:17 PM PDT 24 | May 28 01:18:02 PM PDT 24 | 336719890000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.593378723 | May 28 12:48:59 PM PDT 24 | May 28 01:15:00 PM PDT 24 | 336925150000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2788293775 | May 28 12:48:12 PM PDT 24 | May 28 01:15:02 PM PDT 24 | 336661250000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1276676227 | May 28 12:46:15 PM PDT 24 | May 28 01:13:45 PM PDT 24 | 336539290000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2231268449 | May 28 12:48:08 PM PDT 24 | May 28 01:21:22 PM PDT 24 | 336838790000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3251979669 | May 28 12:48:06 PM PDT 24 | May 28 01:12:15 PM PDT 24 | 337055370000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1743871889 | May 28 12:45:26 PM PDT 24 | May 28 01:13:06 PM PDT 24 | 336780910000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3524793589 | May 28 12:48:57 PM PDT 24 | May 28 01:23:49 PM PDT 24 | 337038410000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2380901998 | May 28 12:48:44 PM PDT 24 | May 28 01:17:47 PM PDT 24 | 336795030000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1000922377 | May 28 12:45:08 PM PDT 24 | May 28 01:18:04 PM PDT 24 | 336456430000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3524396280 | May 28 12:48:32 PM PDT 24 | May 28 01:18:02 PM PDT 24 | 336402830000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2980003643 | May 28 12:45:14 PM PDT 24 | May 28 01:14:53 PM PDT 24 | 336908390000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3291055998 | May 28 12:48:30 PM PDT 24 | May 28 01:21:25 PM PDT 24 | 336764570000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.854047576 | May 28 12:49:20 PM PDT 24 | May 28 01:18:07 PM PDT 24 | 336505950000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.487723574 | May 28 12:46:53 PM PDT 24 | May 28 01:15:50 PM PDT 24 | 336880570000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4084218078 | May 28 12:48:18 PM PDT 24 | May 28 01:10:37 PM PDT 24 | 336641610000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3954154373 | May 28 12:48:30 PM PDT 24 | May 28 01:21:30 PM PDT 24 | 336962110000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3120249898 | May 28 12:47:22 PM PDT 24 | May 28 01:23:12 PM PDT 24 | 336722790000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3661756537 | May 28 12:46:50 PM PDT 24 | May 28 01:18:02 PM PDT 24 | 337047050000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2063920907 | May 28 12:46:54 PM PDT 24 | May 28 01:24:37 PM PDT 24 | 336381930000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3309479434 | May 28 12:48:59 PM PDT 24 | May 28 01:20:53 PM PDT 24 | 336611310000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.878879277 | May 28 12:48:12 PM PDT 24 | May 28 01:15:15 PM PDT 24 | 336853210000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2679763708 | May 28 12:46:08 PM PDT 24 | May 28 01:14:57 PM PDT 24 | 336562270000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.861807797 | May 28 12:48:58 PM PDT 24 | May 28 01:21:11 PM PDT 24 | 337080470000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1957080630 | May 28 12:45:49 PM PDT 24 | May 28 01:18:03 PM PDT 24 | 336588850000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2634488568 | May 28 12:45:03 PM PDT 24 | May 28 01:21:06 PM PDT 24 | 336545070000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3689985901 | May 28 12:48:08 PM PDT 24 | May 28 01:21:28 PM PDT 24 | 336679270000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1382942821 | May 28 12:48:12 PM PDT 24 | May 28 01:12:51 PM PDT 24 | 336658430000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4240390199 | May 28 12:46:08 PM PDT 24 | May 28 01:14:53 PM PDT 24 | 337099350000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2420126279 | May 28 12:49:20 PM PDT 24 | May 28 01:14:25 PM PDT 24 | 337050990000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2098033445 | May 28 12:48:14 PM PDT 24 | May 28 01:17:01 PM PDT 24 | 336884670000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1270886143 | May 28 12:48:58 PM PDT 24 | May 28 01:21:42 PM PDT 24 | 337068290000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3775608975 | May 28 12:45:53 PM PDT 24 | May 28 01:10:55 PM PDT 24 | 336449030000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1155044087 | May 28 12:45:06 PM PDT 24 | May 28 01:14:58 PM PDT 24 | 336829790000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3807267717 | May 28 12:49:01 PM PDT 24 | May 28 01:14:23 PM PDT 24 | 336373610000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1306210933 | May 28 12:49:09 PM PDT 24 | May 28 01:19:24 PM PDT 24 | 336996770000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3908186858 | May 28 12:48:24 PM PDT 24 | May 28 01:12:07 PM PDT 24 | 336506770000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.793390538 | May 28 12:47:42 PM PDT 24 | May 28 01:23:25 PM PDT 24 | 336847230000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1707936625 | May 28 12:48:25 PM PDT 24 | May 28 01:16:42 PM PDT 24 | 336820830000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1017351846 | May 28 12:46:53 PM PDT 24 | May 28 01:25:24 PM PDT 24 | 336832430000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.539249806 | May 28 12:48:14 PM PDT 24 | May 28 01:16:35 PM PDT 24 | 337093670000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.22952076 | May 28 12:48:08 PM PDT 24 | May 28 01:20:08 PM PDT 24 | 336885230000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.118713930 | May 28 12:48:17 PM PDT 24 | May 28 01:17:31 PM PDT 24 | 337022430000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.157117523 | May 28 12:46:53 PM PDT 24 | May 28 01:15:44 PM PDT 24 | 336792990000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2456642639 | May 28 12:44:33 PM PDT 24 | May 28 01:22:51 PM PDT 24 | 336634370000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2952964348 | May 28 12:46:18 PM PDT 24 | May 28 01:21:37 PM PDT 24 | 336828090000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2592552080 | May 28 12:48:57 PM PDT 24 | May 28 01:24:03 PM PDT 24 | 336963210000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1980989253 | May 28 12:44:49 PM PDT 24 | May 28 01:21:14 PM PDT 24 | 336977210000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4120571521 | May 28 01:09:43 PM PDT 24 | May 28 01:40:50 PM PDT 24 | 336489690000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.461880133 | May 28 01:09:30 PM PDT 24 | May 28 01:39:18 PM PDT 24 | 336511550000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1585448602 | May 28 01:09:44 PM PDT 24 | May 28 01:47:59 PM PDT 24 | 337018070000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2143480180 | May 28 01:09:25 PM PDT 24 | May 28 01:41:32 PM PDT 24 | 336586110000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.699659365 | May 28 01:09:30 PM PDT 24 | May 28 01:43:20 PM PDT 24 | 336457530000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3383570732 | May 28 01:09:36 PM PDT 24 | May 28 01:41:59 PM PDT 24 | 336594190000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3393802157 | May 28 01:09:30 PM PDT 24 | May 28 01:43:53 PM PDT 24 | 336709890000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1978006137 | May 28 01:09:44 PM PDT 24 | May 28 01:41:20 PM PDT 24 | 337059370000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1159349276 | May 28 01:09:33 PM PDT 24 | May 28 01:44:08 PM PDT 24 | 336766170000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4213925209 | May 28 01:09:51 PM PDT 24 | May 28 01:45:05 PM PDT 24 | 336468870000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1494199319 | May 28 01:09:37 PM PDT 24 | May 28 01:43:24 PM PDT 24 | 336711890000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.642812931 | May 28 01:09:43 PM PDT 24 | May 28 01:44:23 PM PDT 24 | 336401750000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4003191226 | May 28 01:09:35 PM PDT 24 | May 28 01:42:16 PM PDT 24 | 336477110000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2318986075 | May 28 01:09:44 PM PDT 24 | May 28 01:40:22 PM PDT 24 | 336952210000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2768237316 | May 28 01:09:32 PM PDT 24 | May 28 01:44:21 PM PDT 24 | 336791410000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2760801795 | May 28 01:09:30 PM PDT 24 | May 28 01:43:34 PM PDT 24 | 336820850000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4279639329 | May 28 01:09:37 PM PDT 24 | May 28 01:34:18 PM PDT 24 | 336454590000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.883304356 | May 28 01:09:44 PM PDT 24 | May 28 01:39:35 PM PDT 24 | 336582730000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1577397198 | May 28 01:09:45 PM PDT 24 | May 28 01:35:16 PM PDT 24 | 336798410000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.838402445 | May 28 01:09:42 PM PDT 24 | May 28 01:42:29 PM PDT 24 | 336795870000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2812863078 | May 28 01:09:31 PM PDT 24 | May 28 01:37:58 PM PDT 24 | 336994770000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1733165094 | May 28 01:09:34 PM PDT 24 | May 28 01:34:57 PM PDT 24 | 336577830000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2203186281 | May 28 01:09:36 PM PDT 24 | May 28 01:43:50 PM PDT 24 | 336886370000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1073017063 | May 28 01:09:33 PM PDT 24 | May 28 01:45:26 PM PDT 24 | 336369590000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3307601462 | May 28 01:09:30 PM PDT 24 | May 28 01:45:31 PM PDT 24 | 336990370000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.827042372 | May 28 01:09:30 PM PDT 24 | May 28 01:38:50 PM PDT 24 | 336761570000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.948176033 | May 28 01:09:50 PM PDT 24 | May 28 01:43:45 PM PDT 24 | 336393090000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1445237854 | May 28 01:09:35 PM PDT 24 | May 28 01:42:15 PM PDT 24 | 336850370000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.926346003 | May 28 01:09:24 PM PDT 24 | May 28 01:46:09 PM PDT 24 | 337098330000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1172653825 | May 28 01:09:32 PM PDT 24 | May 28 01:46:40 PM PDT 24 | 336925750000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1947668330 | May 28 01:09:32 PM PDT 24 | May 28 01:43:36 PM PDT 24 | 336667150000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1627626431 | May 28 01:09:26 PM PDT 24 | May 28 01:38:38 PM PDT 24 | 337131790000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.251312199 | May 28 01:09:35 PM PDT 24 | May 28 01:39:26 PM PDT 24 | 336845890000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2953249417 | May 28 01:09:39 PM PDT 24 | May 28 01:39:48 PM PDT 24 | 336534590000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3001695299 | May 28 01:09:40 PM PDT 24 | May 28 01:40:06 PM PDT 24 | 336676730000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1051404907 | May 28 01:09:35 PM PDT 24 | May 28 01:40:23 PM PDT 24 | 336678470000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2806858490 | May 28 01:09:37 PM PDT 24 | May 28 01:42:49 PM PDT 24 | 336430670000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2197062306 | May 28 01:09:39 PM PDT 24 | May 28 01:37:33 PM PDT 24 | 337136190000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2157027499 | May 28 01:09:54 PM PDT 24 | May 28 01:43:00 PM PDT 24 | 336441870000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2361817379 | May 28 01:09:28 PM PDT 24 | May 28 01:43:30 PM PDT 24 | 336614310000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2578257793 | May 28 01:09:31 PM PDT 24 | May 28 01:38:43 PM PDT 24 | 337106070000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.512445653 | May 28 01:09:34 PM PDT 24 | May 28 01:47:26 PM PDT 24 | 337145810000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3045211979 | May 28 01:09:33 PM PDT 24 | May 28 01:43:33 PM PDT 24 | 336512970000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.872465383 | May 28 01:09:26 PM PDT 24 | May 28 01:45:04 PM PDT 24 | 336588730000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.176696201 | May 28 01:09:35 PM PDT 24 | May 28 01:39:52 PM PDT 24 | 336412810000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3669382640 | May 28 01:09:43 PM PDT 24 | May 28 01:39:58 PM PDT 24 | 336603590000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3513868274 | May 28 01:09:49 PM PDT 24 | May 28 01:48:07 PM PDT 24 | 336723410000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1186479893 | May 28 01:09:29 PM PDT 24 | May 28 01:43:52 PM PDT 24 | 336604710000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1224273251 | May 28 01:09:32 PM PDT 24 | May 28 01:43:45 PM PDT 24 | 336442390000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4101899483 | May 28 01:09:34 PM PDT 24 | May 28 01:46:55 PM PDT 24 | 337109210000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1129600012 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1514410000 ps |
| CPU time | 4.55 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:09:49 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-5e3cc9f5-7db5-4224-8134-9b47dc37a510 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1129600012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1129600012 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3251979669 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 337055370000 ps |
| CPU time | 584.37 seconds |
| Started | May 28 12:48:06 PM PDT 24 |
| Finished | May 28 01:12:15 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-98b5a6f3-52c8-4274-b34f-2243a68172bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3251979669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3251979669 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2143480180 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336586110000 ps |
| CPU time | 785.5 seconds |
| Started | May 28 01:09:25 PM PDT 24 |
| Finished | May 28 01:41:32 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-991a2623-09da-4c19-827d-78471e259a7d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2143480180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2143480180 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.807807348 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1510830000 ps |
| CPU time | 4.22 seconds |
| Started | May 28 01:08:53 PM PDT 24 |
| Finished | May 28 01:09:06 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-6be896dd-cc97-4336-9c23-665a2f46cc49 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=807807348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.807807348 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.827042372 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336761570000 ps |
| CPU time | 714.67 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:38:50 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-5de7ed8c-3ad0-4f7f-9e87-a978664eed6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=827042372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.827042372 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.926346003 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 337098330000 ps |
| CPU time | 890.49 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:46:09 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-5622649a-6747-4a5a-b7c4-b895ef557225 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=926346003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.926346003 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3307601462 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336990370000 ps |
| CPU time | 866.36 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:45:31 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-58187745-af0b-4b16-a67a-7bf1bc62d110 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3307601462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3307601462 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3669382640 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336603590000 ps |
| CPU time | 751.82 seconds |
| Started | May 28 01:09:43 PM PDT 24 |
| Finished | May 28 01:39:58 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-cd7195e0-1dd7-4178-80ea-1a046db018ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3669382640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3669382640 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1577397198 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336798410000 ps |
| CPU time | 612.16 seconds |
| Started | May 28 01:09:45 PM PDT 24 |
| Finished | May 28 01:35:16 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-8a849c56-67a1-4049-b7ad-d5247254d8c0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1577397198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1577397198 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1445237854 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336850370000 ps |
| CPU time | 806.34 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:42:15 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-22b36f4c-ab9f-4e61-be81-950e9dcf7823 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1445237854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1445237854 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.176696201 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336412810000 ps |
| CPU time | 733.5 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:39:52 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-02c35f1c-1aa0-47f1-8f44-272f734b01a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=176696201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.176696201 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1627626431 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 337131790000 ps |
| CPU time | 708.63 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:38:38 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-14df2d86-57bb-470c-b391-3d70f73c979b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1627626431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1627626431 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1947668330 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336667150000 ps |
| CPU time | 822.93 seconds |
| Started | May 28 01:09:32 PM PDT 24 |
| Finished | May 28 01:43:36 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-24807339-5e7d-486d-90f3-dd8872d1134b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1947668330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1947668330 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3513868274 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336723410000 ps |
| CPU time | 904.7 seconds |
| Started | May 28 01:09:49 PM PDT 24 |
| Finished | May 28 01:48:07 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-80218511-5868-4290-b62a-0369fb1b128f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3513868274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3513868274 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.4279639329 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336454590000 ps |
| CPU time | 585.27 seconds |
| Started | May 28 01:09:37 PM PDT 24 |
| Finished | May 28 01:34:18 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-f41bcad1-61f4-4d31-be99-9a9ca2fcde12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4279639329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.4279639329 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.872465383 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336588730000 ps |
| CPU time | 864.56 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:45:04 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-bed5d5f2-cbd4-4bb9-86ef-dc0760944bfa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=872465383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.872465383 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3001695299 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336676730000 ps |
| CPU time | 740.95 seconds |
| Started | May 28 01:09:40 PM PDT 24 |
| Finished | May 28 01:40:06 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-1b5a5ab1-697e-4100-955e-93f01f4251cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3001695299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3001695299 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1733165094 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336577830000 ps |
| CPU time | 610.8 seconds |
| Started | May 28 01:09:34 PM PDT 24 |
| Finished | May 28 01:34:57 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-7289486a-1ce4-4acc-9ec7-df28fb80ac0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1733165094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1733165094 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2361817379 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336614310000 ps |
| CPU time | 830.02 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:43:30 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-2f82baea-7754-4bab-a932-838b801c9743 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2361817379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2361817379 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2806858490 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336430670000 ps |
| CPU time | 803.65 seconds |
| Started | May 28 01:09:37 PM PDT 24 |
| Finished | May 28 01:42:49 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-3bab8a65-2dd8-48ed-9440-83e22b9bac02 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2806858490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2806858490 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.948176033 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336393090000 ps |
| CPU time | 837.05 seconds |
| Started | May 28 01:09:50 PM PDT 24 |
| Finished | May 28 01:43:45 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-046d2487-13a9-4e25-9d33-868888fd87bc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=948176033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.948176033 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.512445653 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 337145810000 ps |
| CPU time | 891.51 seconds |
| Started | May 28 01:09:34 PM PDT 24 |
| Finished | May 28 01:47:26 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-65d5b338-7eaf-482b-b28b-16c0934c31b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=512445653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.512445653 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4120571521 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336489690000 ps |
| CPU time | 774.76 seconds |
| Started | May 28 01:09:43 PM PDT 24 |
| Finished | May 28 01:40:50 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-ac5a5204-354b-4ecb-944a-a4d7e200025a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4120571521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.4120571521 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2812863078 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336994770000 ps |
| CPU time | 698.16 seconds |
| Started | May 28 01:09:31 PM PDT 24 |
| Finished | May 28 01:37:58 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-d48e650a-d255-427e-adf0-2c6027c9abd4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2812863078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2812863078 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1073017063 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336369590000 ps |
| CPU time | 863.7 seconds |
| Started | May 28 01:09:33 PM PDT 24 |
| Finished | May 28 01:45:26 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-51388a4b-9a1b-46e6-aa6b-84e240f355a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1073017063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1073017063 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1978006137 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 337059370000 ps |
| CPU time | 769.27 seconds |
| Started | May 28 01:09:44 PM PDT 24 |
| Finished | May 28 01:41:20 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-7c9e6198-a80f-4e40-ada8-01efc8a4df87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1978006137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1978006137 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1186479893 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336604710000 ps |
| CPU time | 836.91 seconds |
| Started | May 28 01:09:29 PM PDT 24 |
| Finished | May 28 01:43:52 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-c824408a-4f13-4b6c-ae9d-9df0c6613e14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1186479893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1186479893 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2760801795 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336820850000 ps |
| CPU time | 832.29 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:43:34 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-fbd66eb7-e0fa-4968-bd57-36c4dbc003f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2760801795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2760801795 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2768237316 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336791410000 ps |
| CPU time | 847.06 seconds |
| Started | May 28 01:09:32 PM PDT 24 |
| Finished | May 28 01:44:21 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-ac1ceb6a-a36b-4a22-ade6-007059328875 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2768237316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2768237316 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4213925209 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336468870000 ps |
| CPU time | 868.16 seconds |
| Started | May 28 01:09:51 PM PDT 24 |
| Finished | May 28 01:45:05 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-140dded7-efd1-444e-b65b-024861e09ddf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4213925209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4213925209 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2953249417 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336534590000 ps |
| CPU time | 731.14 seconds |
| Started | May 28 01:09:39 PM PDT 24 |
| Finished | May 28 01:39:48 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-b36e2092-4722-4b51-9669-90a4ebdaaf5a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2953249417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2953249417 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2578257793 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 337106070000 ps |
| CPU time | 718.76 seconds |
| Started | May 28 01:09:31 PM PDT 24 |
| Finished | May 28 01:38:43 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-046fbe5d-3cda-4ec9-989a-8c8ab36ad327 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2578257793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2578257793 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.883304356 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336582730000 ps |
| CPU time | 728.78 seconds |
| Started | May 28 01:09:44 PM PDT 24 |
| Finished | May 28 01:39:35 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-42f8f4b0-66e5-4706-9a14-cbcc7aff695f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=883304356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.883304356 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2203186281 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336886370000 ps |
| CPU time | 839.15 seconds |
| Started | May 28 01:09:36 PM PDT 24 |
| Finished | May 28 01:43:50 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-760cf08c-89e0-447c-932c-b19b413033d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2203186281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2203186281 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1494199319 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336711890000 ps |
| CPU time | 821.54 seconds |
| Started | May 28 01:09:37 PM PDT 24 |
| Finished | May 28 01:43:24 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-830b0e75-6761-496b-a8f4-60b3069cc7f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1494199319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1494199319 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1159349276 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336766170000 ps |
| CPU time | 854.78 seconds |
| Started | May 28 01:09:33 PM PDT 24 |
| Finished | May 28 01:44:08 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-d85b18dc-5d8a-4472-acdd-3e4456556afa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1159349276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1159349276 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1224273251 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336442390000 ps |
| CPU time | 838.59 seconds |
| Started | May 28 01:09:32 PM PDT 24 |
| Finished | May 28 01:43:45 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-9aeeb20d-01b3-4b94-9bc6-bdebb8c51b8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1224273251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1224273251 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1172653825 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336925750000 ps |
| CPU time | 886.78 seconds |
| Started | May 28 01:09:32 PM PDT 24 |
| Finished | May 28 01:46:40 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-6b007566-7df6-4005-a059-bd86246e3646 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1172653825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1172653825 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3383570732 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336594190000 ps |
| CPU time | 795.2 seconds |
| Started | May 28 01:09:36 PM PDT 24 |
| Finished | May 28 01:41:59 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-ff13704b-09c7-4cc9-a869-e67f7050921f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3383570732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3383570732 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.461880133 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336511550000 ps |
| CPU time | 741.85 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:39:18 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-8ab88e48-7f33-4d7d-b5d3-8b690f240131 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=461880133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.461880133 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2197062306 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 337136190000 ps |
| CPU time | 670.77 seconds |
| Started | May 28 01:09:39 PM PDT 24 |
| Finished | May 28 01:37:33 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-a2e145e1-bebb-4b0a-806b-fa47cf2dc743 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2197062306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2197062306 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.838402445 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336795870000 ps |
| CPU time | 804.46 seconds |
| Started | May 28 01:09:42 PM PDT 24 |
| Finished | May 28 01:42:29 PM PDT 24 |
| Peak memory | 160752 kb |
| Host | smart-4c40dd95-5538-47c9-b3e7-ef11200bbbcc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=838402445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.838402445 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4003191226 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336477110000 ps |
| CPU time | 801.15 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:42:16 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-081c51bf-d935-4cd6-b17b-75b9fc03ac0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4003191226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.4003191226 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3045211979 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336512970000 ps |
| CPU time | 826.49 seconds |
| Started | May 28 01:09:33 PM PDT 24 |
| Finished | May 28 01:43:33 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-901d92f4-49d8-4966-904c-3d51245a9bdc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3045211979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3045211979 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3393802157 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336709890000 ps |
| CPU time | 844.68 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:43:53 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-bff4db4c-644e-4235-a1f3-cd793ecd548f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3393802157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3393802157 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1585448602 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 337018070000 ps |
| CPU time | 911.83 seconds |
| Started | May 28 01:09:44 PM PDT 24 |
| Finished | May 28 01:47:59 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-cd4d4c03-f61a-4254-b035-8d5055ce42dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1585448602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1585448602 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2318986075 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336952210000 ps |
| CPU time | 746.81 seconds |
| Started | May 28 01:09:44 PM PDT 24 |
| Finished | May 28 01:40:22 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-f5bc11a4-dffa-4ecf-b7f9-e85a17ab722a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2318986075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2318986075 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.642812931 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336401750000 ps |
| CPU time | 841.06 seconds |
| Started | May 28 01:09:43 PM PDT 24 |
| Finished | May 28 01:44:23 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-8efc9084-8f3c-4fee-ae5f-a38ddf7b83ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=642812931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.642812931 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1051404907 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336678470000 ps |
| CPU time | 762.87 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:40:23 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-291db7b3-0523-4fcf-b785-da7742d5f02e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1051404907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1051404907 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.699659365 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336457530000 ps |
| CPU time | 828.82 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:43:20 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-2fd4b955-4262-4858-8172-422654c406c3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=699659365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.699659365 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.4101899483 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 337109210000 ps |
| CPU time | 907.84 seconds |
| Started | May 28 01:09:34 PM PDT 24 |
| Finished | May 28 01:46:55 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-c1d0906f-18da-40cc-9d47-99d9670a5fbe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4101899483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.4101899483 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2157027499 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336441870000 ps |
| CPU time | 804.95 seconds |
| Started | May 28 01:09:54 PM PDT 24 |
| Finished | May 28 01:43:00 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-cac4e66c-2bcf-405c-a951-9fa88bb5514a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2157027499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2157027499 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.251312199 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336845890000 ps |
| CPU time | 735.99 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:39:26 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-ee16a4ad-d616-4eff-abd1-54e8446d04be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=251312199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.251312199 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1270886143 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 337068290000 ps |
| CPU time | 798.79 seconds |
| Started | May 28 12:48:58 PM PDT 24 |
| Finished | May 28 01:21:42 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-4d8ecc45-351f-4a0a-9137-cb0393e2aaa2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1270886143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1270886143 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1957080630 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336588850000 ps |
| CPU time | 784.12 seconds |
| Started | May 28 12:45:49 PM PDT 24 |
| Finished | May 28 01:18:03 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-cbbf95d1-ffae-4f97-9bc1-3fea42ca0d8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1957080630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1957080630 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2679763708 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336562270000 ps |
| CPU time | 708.61 seconds |
| Started | May 28 12:46:08 PM PDT 24 |
| Finished | May 28 01:14:57 PM PDT 24 |
| Peak memory | 159440 kb |
| Host | smart-ea019cda-7b6b-497e-bb76-4b3e5d60fb6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2679763708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2679763708 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.157117523 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336792990000 ps |
| CPU time | 706.52 seconds |
| Started | May 28 12:46:53 PM PDT 24 |
| Finished | May 28 01:15:44 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-b991558d-2337-446e-a330-73e89ad51457 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=157117523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.157117523 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1306210933 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336996770000 ps |
| CPU time | 720 seconds |
| Started | May 28 12:49:09 PM PDT 24 |
| Finished | May 28 01:19:24 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-fee0da6f-c0f1-4ed7-87a3-8ea3933ab46f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1306210933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1306210933 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2002715027 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 337196430000 ps |
| CPU time | 602.57 seconds |
| Started | May 28 12:48:15 PM PDT 24 |
| Finished | May 28 01:13:16 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-2931e448-9a51-4f92-b02c-f7cd848c43a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2002715027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2002715027 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2634488568 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336545070000 ps |
| CPU time | 875.37 seconds |
| Started | May 28 12:45:03 PM PDT 24 |
| Finished | May 28 01:21:06 PM PDT 24 |
| Peak memory | 160548 kb |
| Host | smart-5e497a2b-665a-45fb-b871-19f6505f1370 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2634488568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2634488568 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.854047576 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336505950000 ps |
| CPU time | 691.15 seconds |
| Started | May 28 12:49:20 PM PDT 24 |
| Finished | May 28 01:18:07 PM PDT 24 |
| Peak memory | 159764 kb |
| Host | smart-03d56445-cf40-45ea-9c95-d5ebb244c092 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=854047576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.854047576 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2952964348 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336828090000 ps |
| CPU time | 857.49 seconds |
| Started | May 28 12:46:18 PM PDT 24 |
| Finished | May 28 01:21:37 PM PDT 24 |
| Peak memory | 160548 kb |
| Host | smart-3f4aff98-f7c2-4302-bdf4-6db9f23a46bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2952964348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2952964348 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3120249898 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336722790000 ps |
| CPU time | 882.4 seconds |
| Started | May 28 12:47:22 PM PDT 24 |
| Finished | May 28 01:23:12 PM PDT 24 |
| Peak memory | 160920 kb |
| Host | smart-5d35a398-69ff-4d65-980c-66191e49d5d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3120249898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3120249898 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2420126279 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 337050990000 ps |
| CPU time | 605.82 seconds |
| Started | May 28 12:49:20 PM PDT 24 |
| Finished | May 28 01:14:25 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-81deb7d3-7fb3-4b6b-913f-748bf59f2e54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2420126279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2420126279 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3524396280 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336402830000 ps |
| CPU time | 717.87 seconds |
| Started | May 28 12:48:32 PM PDT 24 |
| Finished | May 28 01:18:02 PM PDT 24 |
| Peak memory | 159292 kb |
| Host | smart-02fa00c0-2c34-46fa-9a28-e7129840659d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3524396280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3524396280 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.793390538 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336847230000 ps |
| CPU time | 874.64 seconds |
| Started | May 28 12:47:42 PM PDT 24 |
| Finished | May 28 01:23:25 PM PDT 24 |
| Peak memory | 160916 kb |
| Host | smart-5b858b34-2745-4845-96da-9b122045a12f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=793390538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.793390538 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3661756537 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 337047050000 ps |
| CPU time | 763.96 seconds |
| Started | May 28 12:46:50 PM PDT 24 |
| Finished | May 28 01:18:02 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-fcb68de1-8f15-4c38-90f5-77ba82e60c54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3661756537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3661756537 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.487723574 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336880570000 ps |
| CPU time | 709.63 seconds |
| Started | May 28 12:46:53 PM PDT 24 |
| Finished | May 28 01:15:50 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-409c85b6-590c-43cd-8c12-75b228ba3b48 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=487723574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.487723574 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3775608975 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336449030000 ps |
| CPU time | 599.09 seconds |
| Started | May 28 12:45:53 PM PDT 24 |
| Finished | May 28 01:10:55 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-96069013-6d90-4374-bf77-c70c5c4064b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3775608975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3775608975 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2063920907 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336381930000 ps |
| CPU time | 907.2 seconds |
| Started | May 28 12:46:54 PM PDT 24 |
| Finished | May 28 01:24:37 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-01d23b4d-af90-43ea-85c9-cd0340394cd9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2063920907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2063920907 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.878879277 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336853210000 ps |
| CPU time | 655.39 seconds |
| Started | May 28 12:48:12 PM PDT 24 |
| Finished | May 28 01:15:15 PM PDT 24 |
| Peak memory | 159696 kb |
| Host | smart-def56701-650e-46f7-ba1d-24d5d95401f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=878879277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.878879277 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2098033445 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336884670000 ps |
| CPU time | 698.35 seconds |
| Started | May 28 12:48:14 PM PDT 24 |
| Finished | May 28 01:17:01 PM PDT 24 |
| Peak memory | 159712 kb |
| Host | smart-aa33e6d2-702b-4d1e-889f-29b3b8f51957 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2098033445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2098033445 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2788293775 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336661250000 ps |
| CPU time | 657.67 seconds |
| Started | May 28 12:48:12 PM PDT 24 |
| Finished | May 28 01:15:02 PM PDT 24 |
| Peak memory | 159612 kb |
| Host | smart-d825100c-8fdb-49f8-ad1d-ccf8e6f648c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2788293775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2788293775 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1017351846 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336832430000 ps |
| CPU time | 931.06 seconds |
| Started | May 28 12:46:53 PM PDT 24 |
| Finished | May 28 01:25:24 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-4737a4a8-3f44-42bc-b2d0-3471d4ef6c98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1017351846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1017351846 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4240390199 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 337099350000 ps |
| CPU time | 706.1 seconds |
| Started | May 28 12:46:08 PM PDT 24 |
| Finished | May 28 01:14:53 PM PDT 24 |
| Peak memory | 159384 kb |
| Host | smart-a72c5679-be82-4a8a-b910-4c9ce13f6be9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4240390199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4240390199 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.22952076 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336885230000 ps |
| CPU time | 767.03 seconds |
| Started | May 28 12:48:08 PM PDT 24 |
| Finished | May 28 01:20:08 PM PDT 24 |
| Peak memory | 159008 kb |
| Host | smart-a881724d-a4cf-4757-b17f-0eddd3e2cdf9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=22952076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.22952076 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.539249806 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 337093670000 ps |
| CPU time | 691.9 seconds |
| Started | May 28 12:48:14 PM PDT 24 |
| Finished | May 28 01:16:35 PM PDT 24 |
| Peak memory | 159960 kb |
| Host | smart-7bf95056-9db8-40e8-84c2-eeaa932f5e76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=539249806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.539249806 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3524793589 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337038410000 ps |
| CPU time | 847.43 seconds |
| Started | May 28 12:48:57 PM PDT 24 |
| Finished | May 28 01:23:49 PM PDT 24 |
| Peak memory | 160172 kb |
| Host | smart-47a1fbdc-9512-4d73-9167-e42b47dda646 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3524793589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3524793589 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2592552080 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336963210000 ps |
| CPU time | 851.89 seconds |
| Started | May 28 12:48:57 PM PDT 24 |
| Finished | May 28 01:24:03 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-3de570da-12e1-4c16-9e82-da1e67a15d20 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2592552080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2592552080 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3908186858 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336506770000 ps |
| CPU time | 567.91 seconds |
| Started | May 28 12:48:24 PM PDT 24 |
| Finished | May 28 01:12:07 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-8eacfa65-abf9-4f7e-9a1b-45090b2d8d84 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3908186858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3908186858 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1155044087 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336829790000 ps |
| CPU time | 733.59 seconds |
| Started | May 28 12:45:06 PM PDT 24 |
| Finished | May 28 01:14:58 PM PDT 24 |
| Peak memory | 160616 kb |
| Host | smart-c746d2e5-a700-4c70-b75f-5994c2d52c70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1155044087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1155044087 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1707936625 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336820830000 ps |
| CPU time | 671.44 seconds |
| Started | May 28 12:48:25 PM PDT 24 |
| Finished | May 28 01:16:42 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-58a143eb-74ee-41d2-bac6-c61e06e2424d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1707936625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1707936625 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4084218078 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336641610000 ps |
| CPU time | 535.27 seconds |
| Started | May 28 12:48:18 PM PDT 24 |
| Finished | May 28 01:10:37 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-fe013033-fc80-4748-84c5-23fb8e4de282 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4084218078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.4084218078 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3807267717 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336373610000 ps |
| CPU time | 608.8 seconds |
| Started | May 28 12:49:01 PM PDT 24 |
| Finished | May 28 01:14:23 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-f542b1c2-901d-4cb4-8e3e-963388721ae2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3807267717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3807267717 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2507018496 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336719890000 ps |
| CPU time | 718.49 seconds |
| Started | May 28 12:48:17 PM PDT 24 |
| Finished | May 28 01:18:02 PM PDT 24 |
| Peak memory | 159560 kb |
| Host | smart-2e771e36-e018-4be1-9857-64dd9a3de6fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2507018496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2507018496 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.118713930 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 337022430000 ps |
| CPU time | 703.35 seconds |
| Started | May 28 12:48:17 PM PDT 24 |
| Finished | May 28 01:17:31 PM PDT 24 |
| Peak memory | 160324 kb |
| Host | smart-36f7f29b-a72f-4ae1-8479-8cbe3d97df6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=118713930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.118713930 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2456642639 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336634370000 ps |
| CPU time | 928.1 seconds |
| Started | May 28 12:44:33 PM PDT 24 |
| Finished | May 28 01:22:51 PM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-4b195613-446d-4313-baaa-b31e30bb052a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2456642639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2456642639 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1743871889 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336780910000 ps |
| CPU time | 684.33 seconds |
| Started | May 28 12:45:26 PM PDT 24 |
| Finished | May 28 01:13:06 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-6df221e8-25c5-42f1-a12e-b896b54959ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1743871889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1743871889 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1000922377 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336456430000 ps |
| CPU time | 807.48 seconds |
| Started | May 28 12:45:08 PM PDT 24 |
| Finished | May 28 01:18:04 PM PDT 24 |
| Peak memory | 160636 kb |
| Host | smart-5594e31d-1c16-495a-954c-c2a42dba8204 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1000922377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1000922377 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3954154373 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336962110000 ps |
| CPU time | 801.51 seconds |
| Started | May 28 12:48:30 PM PDT 24 |
| Finished | May 28 01:21:30 PM PDT 24 |
| Peak memory | 159452 kb |
| Host | smart-cc2f3fb0-dcd1-4ddc-9817-af8e72ffb014 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3954154373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3954154373 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3291055998 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336764570000 ps |
| CPU time | 805.68 seconds |
| Started | May 28 12:48:30 PM PDT 24 |
| Finished | May 28 01:21:25 PM PDT 24 |
| Peak memory | 159384 kb |
| Host | smart-f2d18184-9687-4806-ab9f-187c8a18f2ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3291055998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3291055998 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1276676227 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336539290000 ps |
| CPU time | 670.18 seconds |
| Started | May 28 12:46:15 PM PDT 24 |
| Finished | May 28 01:13:45 PM PDT 24 |
| Peak memory | 160264 kb |
| Host | smart-07c03131-94ee-48a5-956b-b1d72a60f172 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1276676227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1276676227 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2980003643 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336908390000 ps |
| CPU time | 726.01 seconds |
| Started | May 28 12:45:14 PM PDT 24 |
| Finished | May 28 01:14:53 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-71d8c65d-165d-4d19-bdf1-7ccdd17afcea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2980003643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2980003643 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.861807797 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 337080470000 ps |
| CPU time | 791.79 seconds |
| Started | May 28 12:48:58 PM PDT 24 |
| Finished | May 28 01:21:11 PM PDT 24 |
| Peak memory | 160260 kb |
| Host | smart-c6f454ca-dbc4-46df-8f33-937f7963e431 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=861807797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.861807797 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3309479434 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336611310000 ps |
| CPU time | 774.82 seconds |
| Started | May 28 12:48:59 PM PDT 24 |
| Finished | May 28 01:20:53 PM PDT 24 |
| Peak memory | 160264 kb |
| Host | smart-053f1874-d76d-4157-8c97-2b1ab6d07fcd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3309479434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3309479434 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2743867644 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336955570000 ps |
| CPU time | 714.33 seconds |
| Started | May 28 12:48:32 PM PDT 24 |
| Finished | May 28 01:17:56 PM PDT 24 |
| Peak memory | 159196 kb |
| Host | smart-4e5f45aa-8864-4fbb-8add-d3465dd9e429 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2743867644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2743867644 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2380901998 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336795030000 ps |
| CPU time | 710.45 seconds |
| Started | May 28 12:48:44 PM PDT 24 |
| Finished | May 28 01:17:47 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-2ee93c82-bd50-4b56-8150-cfce3513fb0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2380901998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2380901998 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2231268449 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336838790000 ps |
| CPU time | 804.77 seconds |
| Started | May 28 12:48:08 PM PDT 24 |
| Finished | May 28 01:21:22 PM PDT 24 |
| Peak memory | 159028 kb |
| Host | smart-ec9425e2-009d-4122-9bfe-9180296f76a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2231268449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2231268449 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3689985901 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336679270000 ps |
| CPU time | 802.79 seconds |
| Started | May 28 12:48:08 PM PDT 24 |
| Finished | May 28 01:21:28 PM PDT 24 |
| Peak memory | 159576 kb |
| Host | smart-67fbc147-b9f6-4c2c-bfd9-31b146f96962 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3689985901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3689985901 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.593378723 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336925150000 ps |
| CPU time | 612.82 seconds |
| Started | May 28 12:48:59 PM PDT 24 |
| Finished | May 28 01:15:00 PM PDT 24 |
| Peak memory | 159740 kb |
| Host | smart-6633f6b8-84e3-453e-ae4c-165dcb04a1a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=593378723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.593378723 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1382942821 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336658430000 ps |
| CPU time | 584.6 seconds |
| Started | May 28 12:48:12 PM PDT 24 |
| Finished | May 28 01:12:51 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-969faa41-ba0d-42e3-bbe1-30f8370a9ef0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1382942821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1382942821 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1980989253 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336977210000 ps |
| CPU time | 883.81 seconds |
| Started | May 28 12:44:49 PM PDT 24 |
| Finished | May 28 01:21:14 PM PDT 24 |
| Peak memory | 160492 kb |
| Host | smart-f1eb6dd0-eeb9-4ed5-bc93-7060c8970532 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1980989253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1980989253 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2081708978 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1411550000 ps |
| CPU time | 3.34 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-7c811451-8ec3-4a9f-87e3-b7330e9af4be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2081708978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2081708978 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2369463525 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1451230000 ps |
| CPU time | 4.33 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-d3bf4a05-2d14-4722-b461-a7a9336a6b14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2369463525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2369463525 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.322789666 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1280130000 ps |
| CPU time | 3.88 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-55a376d4-8aa4-4495-b6d7-ffe4f7c4b3b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=322789666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.322789666 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2270760703 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1359130000 ps |
| CPU time | 4.5 seconds |
| Started | May 28 01:08:56 PM PDT 24 |
| Finished | May 28 01:09:09 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-39f87bbd-7e63-4636-a565-6db7c754adfc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2270760703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2270760703 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3023482278 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1488170000 ps |
| CPU time | 4.32 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-12f600af-a136-484a-ad19-cd11262e0826 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3023482278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3023482278 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.811623225 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1583230000 ps |
| CPU time | 3.93 seconds |
| Started | May 28 01:08:53 PM PDT 24 |
| Finished | May 28 01:09:05 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-35b28ff3-b623-424b-a7d7-32371e9f193f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=811623225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.811623225 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2089336159 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1538370000 ps |
| CPU time | 3.7 seconds |
| Started | May 28 01:08:55 PM PDT 24 |
| Finished | May 28 01:09:07 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-3b769d91-b4bf-495a-86e0-07c652292fd4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2089336159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2089336159 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2982644648 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1531210000 ps |
| CPU time | 4.73 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-cbf3eab0-a428-4fb6-944c-2a5772ba98df |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2982644648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2982644648 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2548889987 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1425790000 ps |
| CPU time | 3.25 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:16 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-a0df2924-a943-4a54-9131-5b9b9eea962e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2548889987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2548889987 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1348985752 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1241410000 ps |
| CPU time | 4.19 seconds |
| Started | May 28 01:08:54 PM PDT 24 |
| Finished | May 28 01:09:07 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-471942df-80eb-47f5-ab96-3f2a0f631546 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1348985752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1348985752 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4605247 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1613050000 ps |
| CPU time | 4.73 seconds |
| Started | May 28 01:08:59 PM PDT 24 |
| Finished | May 28 01:09:13 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-ce61e569-90e8-4984-995f-ec98df81445c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4605247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4605247 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1569452216 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1411630000 ps |
| CPU time | 3.11 seconds |
| Started | May 28 01:09:00 PM PDT 24 |
| Finished | May 28 01:09:10 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-6edff396-23e6-48dc-bfe1-d6f12e906ffd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1569452216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1569452216 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.159722177 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1346170000 ps |
| CPU time | 5.65 seconds |
| Started | May 28 01:08:50 PM PDT 24 |
| Finished | May 28 01:09:03 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-3532f78b-99a6-4cc7-9bb9-78b6c9afab6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=159722177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.159722177 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1251802839 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1569750000 ps |
| CPU time | 5.39 seconds |
| Started | May 28 01:09:06 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-3b6c38ba-f17e-437c-907c-908f55a52c08 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1251802839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1251802839 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.391388327 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1444730000 ps |
| CPU time | 3.65 seconds |
| Started | May 28 01:08:50 PM PDT 24 |
| Finished | May 28 01:09:00 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-baa81726-2ff7-4bb9-929d-7fff2296fcc9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=391388327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.391388327 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.93103195 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1266150000 ps |
| CPU time | 3.89 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:09:04 PM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-f44b1388-771d-4e04-ad77-f94c9bbb23c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=93103195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.93103195 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.311612666 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1302850000 ps |
| CPU time | 3.5 seconds |
| Started | May 28 01:08:49 PM PDT 24 |
| Finished | May 28 01:08:58 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-d48fe370-9c24-4042-84d0-0171708c8726 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=311612666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.311612666 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2309983989 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1488730000 ps |
| CPU time | 4.36 seconds |
| Started | May 28 01:08:53 PM PDT 24 |
| Finished | May 28 01:09:07 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-665fb2b9-cafb-4ac3-b486-754b7fc7bdf6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2309983989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2309983989 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3439014114 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1468130000 ps |
| CPU time | 3.22 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-8d78ad2e-b6a7-42de-8034-a6482d8be0ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3439014114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3439014114 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.459524138 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1544790000 ps |
| CPU time | 3.61 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-a469cf0a-15a1-4f39-b362-8cecbadf883a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=459524138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.459524138 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2827686310 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1260650000 ps |
| CPU time | 4.55 seconds |
| Started | May 28 01:08:57 PM PDT 24 |
| Finished | May 28 01:09:10 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-e5f6a905-a0e6-441f-ab57-7512edf0e197 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2827686310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2827686310 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.35817767 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1514330000 ps |
| CPU time | 4.61 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-d8f928b7-9307-47d7-9025-f21c7e881073 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=35817767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.35817767 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.930713934 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1192930000 ps |
| CPU time | 3.42 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:09:03 PM PDT 24 |
| Peak memory | 164732 kb |
| Host | smart-ec898297-43bc-47e8-9e92-bb59a5abc647 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=930713934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.930713934 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3258298263 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1477670000 ps |
| CPU time | 4.81 seconds |
| Started | May 28 01:09:01 PM PDT 24 |
| Finished | May 28 01:09:15 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-f80a617c-8a2a-4305-8741-c194dfd324fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3258298263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3258298263 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2681943940 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1417510000 ps |
| CPU time | 4.09 seconds |
| Started | May 28 01:09:01 PM PDT 24 |
| Finished | May 28 01:09:13 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-614bf1c7-47b1-47ba-b528-110df63aaa4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2681943940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2681943940 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2041919640 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1422690000 ps |
| CPU time | 3.09 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:15 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-d7f6a35f-c0be-425f-a9a0-18bc66abc244 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2041919640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2041919640 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1153543455 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1530230000 ps |
| CPU time | 4.16 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-1c9aa74b-5233-4002-b047-b96e4f2dadbf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1153543455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1153543455 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3088869723 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1572350000 ps |
| CPU time | 4.15 seconds |
| Started | May 28 01:08:51 PM PDT 24 |
| Finished | May 28 01:09:04 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-757857c3-c1db-419e-b962-72a73b626100 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3088869723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3088869723 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2820157433 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1538250000 ps |
| CPU time | 4.38 seconds |
| Started | May 28 01:08:59 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-7df808f3-f51a-4189-a501-c2bcc576f075 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2820157433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2820157433 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1660522865 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1492250000 ps |
| CPU time | 3.26 seconds |
| Started | May 28 01:08:51 PM PDT 24 |
| Finished | May 28 01:09:00 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-1109f331-6661-4a23-af4b-d0738f9f52bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1660522865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1660522865 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.20903293 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1488170000 ps |
| CPU time | 3.22 seconds |
| Started | May 28 01:09:00 PM PDT 24 |
| Finished | May 28 01:09:11 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-ee1b76ca-3636-40d2-a6d9-28617297b9a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=20903293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.20903293 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3809062266 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1553270000 ps |
| CPU time | 3.51 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-0e5d4724-2a00-4df9-bebe-1ecc850b2c14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3809062266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3809062266 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1720438956 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1526110000 ps |
| CPU time | 4.27 seconds |
| Started | May 28 01:08:45 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-8b556125-5188-4277-9e21-f94e068f4978 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1720438956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1720438956 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.129113397 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1472710000 ps |
| CPU time | 3.25 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-54f375b0-1220-4371-8f90-f22d02bd9d55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=129113397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.129113397 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.791597068 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1569550000 ps |
| CPU time | 3.95 seconds |
| Started | May 28 01:08:59 PM PDT 24 |
| Finished | May 28 01:09:11 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-3cfa53f6-9606-4b55-9598-acd34f134cc4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=791597068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.791597068 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1755480095 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1456590000 ps |
| CPU time | 3.99 seconds |
| Started | May 28 01:08:57 PM PDT 24 |
| Finished | May 28 01:09:09 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-5c7840ee-a99c-41a2-a9d3-de3b9325eb50 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1755480095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1755480095 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2597946194 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1466490000 ps |
| CPU time | 2.98 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-407d1ef4-608a-42fb-bd58-f5c414809fdf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2597946194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2597946194 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3184251986 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1426230000 ps |
| CPU time | 4.43 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:09:05 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-da13b3c5-70ab-4b09-96c6-528b28d81254 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3184251986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3184251986 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1705161896 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1425870000 ps |
| CPU time | 3.25 seconds |
| Started | May 28 01:09:06 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-c4199c05-0c08-4fb7-993d-b4689ef74f41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1705161896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1705161896 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1367771573 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1609790000 ps |
| CPU time | 3.63 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-6b15bb62-50b6-43ea-a2bc-f3b633fcbfc1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1367771573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1367771573 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.890174013 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1215550000 ps |
| CPU time | 3.75 seconds |
| Started | May 28 01:08:57 PM PDT 24 |
| Finished | May 28 01:09:08 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-e8f41e4e-308a-43c3-bc3b-15d576add35d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=890174013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.890174013 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3416344158 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1515150000 ps |
| CPU time | 3.65 seconds |
| Started | May 28 01:08:48 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-a72ff5a9-6c2e-4277-83b1-403093cd72b4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3416344158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3416344158 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.123413214 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1623810000 ps |
| CPU time | 4.87 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-c75589a3-7324-4793-a615-faada934a577 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=123413214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.123413214 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2316722598 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1485710000 ps |
| CPU time | 3.52 seconds |
| Started | May 28 01:08:51 PM PDT 24 |
| Finished | May 28 01:09:02 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-8b83cc22-98da-4636-acae-94aead98dd19 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2316722598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2316722598 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1498393245 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1508890000 ps |
| CPU time | 3.6 seconds |
| Started | May 28 01:08:51 PM PDT 24 |
| Finished | May 28 01:09:01 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-d3ba22e9-05e7-4f6e-bbe1-995d99f45cd5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1498393245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1498393245 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1539305030 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1499810000 ps |
| CPU time | 3.65 seconds |
| Started | May 28 01:09:00 PM PDT 24 |
| Finished | May 28 01:09:11 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-92ab1887-150d-44d4-8434-bd460958fc06 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1539305030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1539305030 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3102184413 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1434670000 ps |
| CPU time | 3.53 seconds |
| Started | May 28 01:08:54 PM PDT 24 |
| Finished | May 28 01:09:06 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-e8b16ffe-b891-4552-9607-b563f559fd6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3102184413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3102184413 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3457516728 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1560790000 ps |
| CPU time | 5.41 seconds |
| Started | May 28 01:08:54 PM PDT 24 |
| Finished | May 28 01:09:09 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-38c56474-2d3a-4f35-a146-635b2d10e9ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3457516728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3457516728 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2843523509 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1453570000 ps |
| CPU time | 4.03 seconds |
| Started | May 28 01:08:56 PM PDT 24 |
| Finished | May 28 01:09:09 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-f98463b5-a54e-4531-aad0-b487ba992ea9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2843523509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2843523509 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.502494102 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1515670000 ps |
| CPU time | 3.55 seconds |
| Started | May 28 01:09:36 PM PDT 24 |
| Finished | May 28 01:09:48 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-2774950a-63e9-4804-94a3-14c2c539bc8c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=502494102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.502494102 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1790782107 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1329750000 ps |
| CPU time | 3.84 seconds |
| Started | May 28 01:09:36 PM PDT 24 |
| Finished | May 28 01:09:48 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-b7883ec7-2cd7-4df3-835f-8535dda259dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1790782107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1790782107 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3584702538 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1547830000 ps |
| CPU time | 4.79 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:39 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-1a60b91e-a8c1-4b27-b458-ccfc31f2ade4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3584702538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3584702538 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1192277577 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1294810000 ps |
| CPU time | 3.76 seconds |
| Started | May 28 01:09:35 PM PDT 24 |
| Finished | May 28 01:09:47 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-5f2f0ff1-cd7a-44c6-af6a-f8fb0697e973 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1192277577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1192277577 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.478641152 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1424850000 ps |
| CPU time | 4.32 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-c3a0c3ab-be0c-4655-a47f-71e1cd828c41 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=478641152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.478641152 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2419266060 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1427910000 ps |
| CPU time | 4.68 seconds |
| Started | May 28 01:09:31 PM PDT 24 |
| Finished | May 28 01:09:45 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-061226c3-c518-4d67-852c-094aa4a566de |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2419266060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2419266060 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2588213835 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1562090000 ps |
| CPU time | 4.4 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-943690ab-45ef-4287-9bac-73bd5d701ead |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2588213835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2588213835 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3736877557 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1490830000 ps |
| CPU time | 3.29 seconds |
| Started | May 28 01:09:38 PM PDT 24 |
| Finished | May 28 01:09:48 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-7901f31c-66d9-47bc-8a49-cc8f06c7e1df |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3736877557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3736877557 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1444272846 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1232170000 ps |
| CPU time | 3.03 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:09:38 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-57d2dcf4-c814-4d9b-8e50-8dbd707336ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1444272846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1444272846 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3416765792 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1436870000 ps |
| CPU time | 3.81 seconds |
| Started | May 28 01:09:25 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-124e67aa-3547-4666-97cf-99bfad8777a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3416765792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3416765792 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2499179672 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1262690000 ps |
| CPU time | 2.82 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:28 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-8cc3ff5e-72e6-4780-9361-e1f009f01b8c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2499179672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2499179672 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2729794579 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1328370000 ps |
| CPU time | 4.08 seconds |
| Started | May 28 01:09:20 PM PDT 24 |
| Finished | May 28 01:09:37 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-15043411-3a75-4345-8727-3460aa6f4728 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2729794579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2729794579 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4051876733 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1545410000 ps |
| CPU time | 4.86 seconds |
| Started | May 28 01:09:18 PM PDT 24 |
| Finished | May 28 01:09:37 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-2876873c-9451-4cff-bcdb-2111344cfe39 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4051876733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4051876733 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.437476775 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1428550000 ps |
| CPU time | 3.6 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:37 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-7dc00de2-e0ea-4a99-945f-c9b3464886a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=437476775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.437476775 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1559245830 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1231310000 ps |
| CPU time | 4.31 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-ff17188c-f2d8-4b9b-ace0-d6eed87b47fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1559245830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1559245830 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3436196005 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1589190000 ps |
| CPU time | 4.63 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:09:43 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-f4038c36-b01f-469c-b1e8-6d68c41d0f71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3436196005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3436196005 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1408194765 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1519150000 ps |
| CPU time | 3.64 seconds |
| Started | May 28 01:09:31 PM PDT 24 |
| Finished | May 28 01:09:43 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-83392f2b-b005-428d-bf09-19e722126cea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1408194765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1408194765 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1324118301 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1270550000 ps |
| CPU time | 3.61 seconds |
| Started | May 28 01:09:32 PM PDT 24 |
| Finished | May 28 01:09:44 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-2de87e03-334d-4b72-b6a9-54f07519d71e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1324118301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1324118301 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3814114987 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1361590000 ps |
| CPU time | 3.9 seconds |
| Started | May 28 01:09:33 PM PDT 24 |
| Finished | May 28 01:09:46 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-716d23ec-25a1-4c5d-aa86-6d843e7b0637 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3814114987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3814114987 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3867538678 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1503710000 ps |
| CPU time | 4.43 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:09:44 PM PDT 24 |
| Peak memory | 164596 kb |
| Host | smart-4b334318-1b32-4c51-9793-822799949b01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3867538678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3867538678 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2978777815 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1451010000 ps |
| CPU time | 4.3 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:09:43 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-1cd6f9a1-56ea-4d4e-95ce-61a32234e3b4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2978777815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2978777815 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2394074566 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1397630000 ps |
| CPU time | 4.52 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:43 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-dd94e019-4174-4264-97da-32623659de1f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2394074566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2394074566 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1989125480 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1285990000 ps |
| CPU time | 3.77 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:38 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-3bb289f0-6522-4825-bd97-a589bc4a8d2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1989125480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1989125480 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.952561832 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1467490000 ps |
| CPU time | 4.27 seconds |
| Started | May 28 01:09:33 PM PDT 24 |
| Finished | May 28 01:09:46 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-d4bcfada-488e-416b-baa4-3b5c347bca36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=952561832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.952561832 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.114488013 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1583110000 ps |
| CPU time | 4.5 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-02d7dd44-9bf8-4b2f-8feb-da831fd6a66b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=114488013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.114488013 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3882826119 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1590070000 ps |
| CPU time | 3.79 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:09:39 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-14486792-a7a9-4786-a1a4-98389e39b333 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3882826119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3882826119 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1574314132 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1510430000 ps |
| CPU time | 4.43 seconds |
| Started | May 28 01:09:31 PM PDT 24 |
| Finished | May 28 01:09:45 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-115e7944-5592-4e9f-b0bf-8872a8140976 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1574314132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1574314132 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1881723816 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1402130000 ps |
| CPU time | 4.06 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:09:39 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-77f08d12-7d64-4b9c-a1c0-f000e3b30eb6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1881723816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1881723816 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1683859538 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1535610000 ps |
| CPU time | 3.16 seconds |
| Started | May 28 01:09:20 PM PDT 24 |
| Finished | May 28 01:09:34 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-9084ca7a-4a7b-4078-b85b-b243133c264c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1683859538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1683859538 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.159875179 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1412610000 ps |
| CPU time | 3.53 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-d32eeaaa-b73b-450d-9450-3a1122eb2e22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=159875179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.159875179 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.179798659 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1379110000 ps |
| CPU time | 4.29 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:38 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-65b73d7b-fa6d-4a0d-ac1e-cc97f0149c0d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=179798659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.179798659 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2890201610 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1488550000 ps |
| CPU time | 4.28 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-7409702b-d9e1-4b3c-8743-b11a231362cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2890201610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2890201610 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.298135450 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1493710000 ps |
| CPU time | 4.38 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:09:44 PM PDT 24 |
| Peak memory | 164612 kb |
| Host | smart-6e8a95ac-b868-4476-a6fb-8011e2c7d9f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=298135450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.298135450 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3723370922 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1191150000 ps |
| CPU time | 2.5 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:36 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-8c3c59d3-bb56-4678-ae21-fd610369fb96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3723370922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3723370922 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2971015972 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1357310000 ps |
| CPU time | 4.24 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:38 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-00d0844c-520f-4b12-b253-db5841a5e514 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2971015972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2971015972 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1838546431 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1222390000 ps |
| CPU time | 3.02 seconds |
| Started | May 28 01:09:34 PM PDT 24 |
| Finished | May 28 01:09:44 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-6b45b3d4-0890-4f72-afdc-20d63c2cad8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1838546431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1838546431 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1487696018 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1264430000 ps |
| CPU time | 3.77 seconds |
| Started | May 28 01:09:20 PM PDT 24 |
| Finished | May 28 01:09:36 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-d0d3f810-28f0-4bd9-bbfa-61340849451b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1487696018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1487696018 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.950870765 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1573790000 ps |
| CPU time | 5.32 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:42 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-3fd908db-3594-42c5-a43c-e4d0d3a0a5e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=950870765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.950870765 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4149125408 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1594110000 ps |
| CPU time | 3.4 seconds |
| Started | May 28 01:09:12 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-7d49cdda-728d-47b9-9520-3ba513df615b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4149125408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4149125408 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1549932635 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1533630000 ps |
| CPU time | 4.59 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:38 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-f50407a6-891b-428a-9549-8e402c845789 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1549932635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1549932635 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2802828372 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1421850000 ps |
| CPU time | 2.95 seconds |
| Started | May 28 01:09:18 PM PDT 24 |
| Finished | May 28 01:09:33 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-d9e05d9f-f442-4c1e-9ccd-586b1c86fba8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2802828372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2802828372 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.448498662 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1496890000 ps |
| CPU time | 4.89 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:43 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-0db1beca-ed9b-4ef8-adf2-5d5f225c7906 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=448498662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.448498662 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2906981625 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1519510000 ps |
| CPU time | 3.88 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:09:42 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-cdf51543-d664-4d1c-9d02-e77e9579f102 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2906981625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2906981625 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.813557556 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1458910000 ps |
| CPU time | 4.2 seconds |
| Started | May 28 01:09:44 PM PDT 24 |
| Finished | May 28 01:09:56 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-cf3c8d77-bb4b-4b3a-9b3f-5b8c08a45249 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=813557556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.813557556 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.648055494 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1458190000 ps |
| CPU time | 4.85 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:46 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-528acb74-64d9-409b-aaee-8b905224f8a2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=648055494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.648055494 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.344045501 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1497170000 ps |
| CPU time | 3.01 seconds |
| Started | May 28 01:09:17 PM PDT 24 |
| Finished | May 28 01:09:32 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-c89a1379-48b6-46ee-a97d-b2cca54b0941 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=344045501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.344045501 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1395478084 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1543630000 ps |
| CPU time | 5.1 seconds |
| Started | May 28 01:09:19 PM PDT 24 |
| Finished | May 28 01:09:38 PM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-be7993cc-553b-4517-86b9-b3b4f13f0355 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1395478084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1395478084 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2967454670 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1285310000 ps |
| CPU time | 2.6 seconds |
| Started | May 28 01:09:46 PM PDT 24 |
| Finished | May 28 01:09:57 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-dd8a64e8-c5df-4098-bbfe-5f4ab018ea9b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2967454670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2967454670 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.638086416 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1364870000 ps |
| CPU time | 3.48 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:36 PM PDT 24 |
| Peak memory | 164804 kb |
| Host | smart-26622d4c-5133-40db-8160-094a2a4e9dd0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=638086416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.638086416 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
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