Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1914743745
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2240815954
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2829264929
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.43438011

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1874683925
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1083950472
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4246245577
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2933029791
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1022816930
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3849483275
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2771982004
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2292180402
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4248280678
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3962804094
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.620184125
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3127943742
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3435774452
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2135473342
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1447994175
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3024603262
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3768050971
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.610129054
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.994240911
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1444474425
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1691988062
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2849523528
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4091299017
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2846843463
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3275211961
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.736830558
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1752787064
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3236565350
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.725595093
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1476924426
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1463004674
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.629237731
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2594349366
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3722664653
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3484142817
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3111356367
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2115046980
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2435140165
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1292095417
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3075325619
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1952086502
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2028839233
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4144167357
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.35984010
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2454685628
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3810138478
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.953053553
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1988344974
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4177490316
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2520978844
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.313561588
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3020715861
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2449093666
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1058908038
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.778755489
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3621992970
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3114506621
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.491069608
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3356411496
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.275480571
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4215502401
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1009623559
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3310880051
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1305842815
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1050792221
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.300566180
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1449448269
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1041461041
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1299400798
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2712085904
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3267330868
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2776635993
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4182778354
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2413623131
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2737659525
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.20301249
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3531957942
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1518442236
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2589423153
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2060540041
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2648523817
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3351130061
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2511662806
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4094276820
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1464940544
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2365579283
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.865468710
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.464841843
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.848239059
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2635173324
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2459602296
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.733075767
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2949828046
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2562739648
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1532257722
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1656612069
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4245265786
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.915306389
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4287937634
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2382756801
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2912196318
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1491208701
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.494400178
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2447609342
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.25704902
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3598985766
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4248847084
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4223080126
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2551206309
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4091307439
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3931202536
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3289453434
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2610165773
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.805234201
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2070093024
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.754472182
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.759951391
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3588574802
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3434479164
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4236757745
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.974858874
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2679379999
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.113973334
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3697049726
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2247377439
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3413490111
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1315274326
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3937213711
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4016681133
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.188168462
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3669049915
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2666730623
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1616806852
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3751230521
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.391838624
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2852641856
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2643744103
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3723965311
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.292846406
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.723990446
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.605129792
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3209546050
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3936512509
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.197154448
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1725666021
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.703355279
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1643778373
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3079867770
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4201641097
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.484521823
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.379661693
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.941721715
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1419795515
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.149963466
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1124837573
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.33011917
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.500540973
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3824453707
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4158225178
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.262650156
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.530770041
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2996453751
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1019894599
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3251833504
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3027579824
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4063457774
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3876898066
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.899085042
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4092709528
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.816933367
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.893193569
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.568516760
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.792118366
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3996918878
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3205706906
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.341000930
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2132649156
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1961782582
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1673705912
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1184273363
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3957688266
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2782048692
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1879417542
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.196623751
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2022577657
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1522238281
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3985240821
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1092025883
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1452489008
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2846536336
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2125675656
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.435784129
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4220518077
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3241862679
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.785002969
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.464665929



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.500540973 May 30 02:05:30 PM PDT 24 May 30 02:05:41 PM PDT 24 1354950000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.435784129 May 30 02:05:30 PM PDT 24 May 30 02:05:42 PM PDT 24 1445410000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.792118366 May 30 02:05:29 PM PDT 24 May 30 02:05:39 PM PDT 24 1211030000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1914743745 May 30 02:05:29 PM PDT 24 May 30 02:05:40 PM PDT 24 1569310000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3824453707 May 30 02:05:29 PM PDT 24 May 30 02:05:43 PM PDT 24 1556510000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.464665929 May 30 02:05:28 PM PDT 24 May 30 02:05:41 PM PDT 24 1582470000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3205706906 May 30 02:05:31 PM PDT 24 May 30 02:05:44 PM PDT 24 1571350000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4063457774 May 30 02:05:29 PM PDT 24 May 30 02:05:40 PM PDT 24 1423650000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.379661693 May 30 02:05:30 PM PDT 24 May 30 02:05:42 PM PDT 24 1452130000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1092025883 May 30 02:05:28 PM PDT 24 May 30 02:05:40 PM PDT 24 1445050000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.816933367 May 30 02:05:29 PM PDT 24 May 30 02:05:41 PM PDT 24 1400350000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.262650156 May 30 02:05:32 PM PDT 24 May 30 02:05:44 PM PDT 24 1410650000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.196623751 May 30 02:05:29 PM PDT 24 May 30 02:05:41 PM PDT 24 1517970000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3251833504 May 30 02:05:32 PM PDT 24 May 30 02:05:45 PM PDT 24 1529090000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.893193569 May 30 02:05:28 PM PDT 24 May 30 02:05:39 PM PDT 24 1400470000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.568516760 May 30 02:05:28 PM PDT 24 May 30 02:05:40 PM PDT 24 1343990000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3996918878 May 30 02:05:33 PM PDT 24 May 30 02:05:47 PM PDT 24 1603570000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4158225178 May 30 02:05:28 PM PDT 24 May 30 02:05:42 PM PDT 24 1497250000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3241862679 May 30 02:05:28 PM PDT 24 May 30 02:05:41 PM PDT 24 1515670000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.149963466 May 30 02:05:27 PM PDT 24 May 30 02:05:40 PM PDT 24 1411310000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.484521823 May 30 02:05:28 PM PDT 24 May 30 02:05:40 PM PDT 24 1292250000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1184273363 May 30 02:05:33 PM PDT 24 May 30 02:05:46 PM PDT 24 1482270000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4220518077 May 30 02:05:32 PM PDT 24 May 30 02:05:47 PM PDT 24 1570830000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2846536336 May 30 02:05:30 PM PDT 24 May 30 02:05:43 PM PDT 24 1429830000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3876898066 May 30 02:05:32 PM PDT 24 May 30 02:05:45 PM PDT 24 1454470000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1019894599 May 30 02:05:33 PM PDT 24 May 30 02:05:46 PM PDT 24 1472670000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3027579824 May 30 02:05:32 PM PDT 24 May 30 02:05:46 PM PDT 24 1578830000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4092709528 May 30 02:05:28 PM PDT 24 May 30 02:05:41 PM PDT 24 1537970000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.33011917 May 30 02:05:30 PM PDT 24 May 30 02:05:43 PM PDT 24 1519550000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2782048692 May 30 02:05:29 PM PDT 24 May 30 02:05:40 PM PDT 24 1428490000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2132649156 May 30 02:05:32 PM PDT 24 May 30 02:05:44 PM PDT 24 1382390000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.899085042 May 30 02:05:33 PM PDT 24 May 30 02:05:46 PM PDT 24 1501170000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2125675656 May 30 02:05:28 PM PDT 24 May 30 02:05:41 PM PDT 24 1335110000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.530770041 May 30 02:05:32 PM PDT 24 May 30 02:05:44 PM PDT 24 1540410000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1522238281 May 30 02:05:29 PM PDT 24 May 30 02:05:39 PM PDT 24 1194130000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2022577657 May 30 02:05:33 PM PDT 24 May 30 02:05:47 PM PDT 24 1539310000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3985240821 May 30 02:05:29 PM PDT 24 May 30 02:05:41 PM PDT 24 1473310000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1452489008 May 30 02:05:27 PM PDT 24 May 30 02:05:42 PM PDT 24 1506210000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1419795515 May 30 02:05:29 PM PDT 24 May 30 02:05:40 PM PDT 24 1302050000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1124837573 May 30 02:05:28 PM PDT 24 May 30 02:05:41 PM PDT 24 1610390000 ps
T71 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3079867770 May 30 02:05:29 PM PDT 24 May 30 02:05:43 PM PDT 24 1491970000 ps
T72 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.341000930 May 30 02:05:34 PM PDT 24 May 30 02:05:45 PM PDT 24 1349770000 ps
T73 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1961782582 May 30 02:05:31 PM PDT 24 May 30 02:05:46 PM PDT 24 1493270000 ps
T74 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.941721715 May 30 02:05:32 PM PDT 24 May 30 02:05:43 PM PDT 24 1331710000 ps
T75 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3957688266 May 30 02:05:29 PM PDT 24 May 30 02:05:41 PM PDT 24 1386050000 ps
T76 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.785002969 May 30 02:05:29 PM PDT 24 May 30 02:05:41 PM PDT 24 1366130000 ps
T77 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2996453751 May 30 02:05:32 PM PDT 24 May 30 02:05:42 PM PDT 24 1151290000 ps
T78 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1673705912 May 30 02:05:31 PM PDT 24 May 30 02:05:46 PM PDT 24 1541910000 ps
T79 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1879417542 May 30 02:05:31 PM PDT 24 May 30 02:05:46 PM PDT 24 1599830000 ps
T80 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4201641097 May 30 02:05:29 PM PDT 24 May 30 02:05:40 PM PDT 24 1264710000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4223080126 May 30 01:50:41 PM PDT 24 May 30 01:50:53 PM PDT 24 1506290000 ps
T5 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.605129792 May 30 01:50:44 PM PDT 24 May 30 01:50:55 PM PDT 24 1579450000 ps
T6 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3434479164 May 30 01:50:40 PM PDT 24 May 30 01:50:55 PM PDT 24 1522630000 ps
T24 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4248847084 May 30 01:50:40 PM PDT 24 May 30 01:50:52 PM PDT 24 1450170000 ps
T25 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.43438011 May 30 01:50:37 PM PDT 24 May 30 01:50:45 PM PDT 24 1320290000 ps
T26 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2679379999 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1334570000 ps
T27 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2666730623 May 30 01:50:40 PM PDT 24 May 30 01:50:52 PM PDT 24 1412670000 ps
T28 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.197154448 May 30 01:50:40 PM PDT 24 May 30 01:50:52 PM PDT 24 1557730000 ps
T29 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1725666021 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1441090000 ps
T30 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.188168462 May 30 01:50:40 PM PDT 24 May 30 01:50:52 PM PDT 24 1532650000 ps
T81 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4236757745 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1276390000 ps
T82 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3937213711 May 30 01:50:38 PM PDT 24 May 30 01:50:51 PM PDT 24 1295090000 ps
T83 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3697049726 May 30 01:50:38 PM PDT 24 May 30 01:50:50 PM PDT 24 1215410000 ps
T84 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2912196318 May 30 01:50:40 PM PDT 24 May 30 01:50:54 PM PDT 24 1494710000 ps
T85 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.113973334 May 30 01:50:38 PM PDT 24 May 30 01:50:52 PM PDT 24 1433230000 ps
T86 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2551206309 May 30 01:50:38 PM PDT 24 May 30 01:50:50 PM PDT 24 1393270000 ps
T87 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.805234201 May 30 01:50:39 PM PDT 24 May 30 01:50:53 PM PDT 24 1583210000 ps
T88 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.703355279 May 30 01:50:38 PM PDT 24 May 30 01:50:50 PM PDT 24 1538330000 ps
T89 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2610165773 May 30 01:50:40 PM PDT 24 May 30 01:50:54 PM PDT 24 1542410000 ps
T90 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2247377439 May 30 01:50:38 PM PDT 24 May 30 01:50:53 PM PDT 24 1539910000 ps
T91 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.292846406 May 30 01:50:44 PM PDT 24 May 30 01:50:54 PM PDT 24 1360310000 ps
T92 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4287937634 May 30 01:50:41 PM PDT 24 May 30 01:50:52 PM PDT 24 1422990000 ps
T93 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3413490111 May 30 01:50:39 PM PDT 24 May 30 01:50:52 PM PDT 24 1556710000 ps
T94 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2382756801 May 30 01:50:39 PM PDT 24 May 30 01:50:52 PM PDT 24 1443950000 ps
T95 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1315274326 May 30 01:50:39 PM PDT 24 May 30 01:50:49 PM PDT 24 1261090000 ps
T96 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.25704902 May 30 01:50:41 PM PDT 24 May 30 01:50:52 PM PDT 24 1482090000 ps
T97 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3289453434 May 30 01:50:41 PM PDT 24 May 30 01:50:53 PM PDT 24 1548050000 ps
T98 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1616806852 May 30 01:50:39 PM PDT 24 May 30 01:50:50 PM PDT 24 1452810000 ps
T99 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2852641856 May 30 01:50:41 PM PDT 24 May 30 01:50:52 PM PDT 24 1526070000 ps
T100 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4091307439 May 30 01:50:40 PM PDT 24 May 30 01:50:52 PM PDT 24 1631730000 ps
T101 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2643744103 May 30 01:50:39 PM PDT 24 May 30 01:50:53 PM PDT 24 1382930000 ps
T102 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3751230521 May 30 01:50:41 PM PDT 24 May 30 01:50:53 PM PDT 24 1415250000 ps
T103 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3723965311 May 30 01:50:41 PM PDT 24 May 30 01:50:54 PM PDT 24 1503530000 ps
T104 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3669049915 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1508750000 ps
T105 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.759951391 May 30 01:50:38 PM PDT 24 May 30 01:50:49 PM PDT 24 1410990000 ps
T106 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1643778373 May 30 01:50:38 PM PDT 24 May 30 01:50:52 PM PDT 24 1649450000 ps
T107 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.754472182 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1623630000 ps
T108 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2447609342 May 30 01:50:38 PM PDT 24 May 30 01:50:50 PM PDT 24 1436590000 ps
T109 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.974858874 May 30 01:50:41 PM PDT 24 May 30 01:50:52 PM PDT 24 1508670000 ps
T110 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4016681133 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1341970000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3931202536 May 30 01:50:41 PM PDT 24 May 30 01:50:52 PM PDT 24 1410690000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3588574802 May 30 01:50:40 PM PDT 24 May 30 01:50:53 PM PDT 24 1442950000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2070093024 May 30 01:50:40 PM PDT 24 May 30 01:50:53 PM PDT 24 1415310000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1491208701 May 30 01:50:39 PM PDT 24 May 30 01:50:50 PM PDT 24 1177390000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3598985766 May 30 01:50:39 PM PDT 24 May 30 01:50:55 PM PDT 24 1504130000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3209546050 May 30 01:50:43 PM PDT 24 May 30 01:50:52 PM PDT 24 1393970000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.494400178 May 30 01:50:40 PM PDT 24 May 30 01:50:51 PM PDT 24 1293150000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3936512509 May 30 01:50:37 PM PDT 24 May 30 01:50:46 PM PDT 24 1218170000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.391838624 May 30 01:50:40 PM PDT 24 May 30 01:50:53 PM PDT 24 1524410000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.723990446 May 30 01:50:41 PM PDT 24 May 30 01:50:54 PM PDT 24 1505890000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4182778354 May 30 02:05:27 PM PDT 24 May 30 02:32:06 PM PDT 24 336661470000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1532257722 May 30 02:05:16 PM PDT 24 May 30 02:47:04 PM PDT 24 336936410000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1050792221 May 30 02:05:26 PM PDT 24 May 30 02:34:36 PM PDT 24 336439030000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2949828046 May 30 02:05:27 PM PDT 24 May 30 02:41:33 PM PDT 24 336541090000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1449448269 May 30 02:05:24 PM PDT 24 May 30 02:32:22 PM PDT 24 336688650000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.491069608 May 30 02:05:27 PM PDT 24 May 30 02:36:25 PM PDT 24 336885530000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3310880051 May 30 02:05:27 PM PDT 24 May 30 02:37:37 PM PDT 24 336444170000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.865468710 May 30 02:05:29 PM PDT 24 May 30 02:45:07 PM PDT 24 336965190000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2240815954 May 30 02:05:30 PM PDT 24 May 30 02:41:55 PM PDT 24 337076190000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.915306389 May 30 02:05:27 PM PDT 24 May 30 02:35:50 PM PDT 24 336936910000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2520978844 May 30 02:05:15 PM PDT 24 May 30 02:47:05 PM PDT 24 336459390000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.778755489 May 30 02:05:29 PM PDT 24 May 30 02:44:50 PM PDT 24 336671170000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3621992970 May 30 02:05:25 PM PDT 24 May 30 02:38:51 PM PDT 24 336385910000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3351130061 May 30 02:05:27 PM PDT 24 May 30 02:34:17 PM PDT 24 336953610000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4245265786 May 30 02:05:29 PM PDT 24 May 30 02:34:33 PM PDT 24 336840770000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.733075767 May 30 02:05:30 PM PDT 24 May 30 02:44:42 PM PDT 24 336882470000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1464940544 May 30 02:05:26 PM PDT 24 May 30 02:37:18 PM PDT 24 336801230000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2449093666 May 30 02:05:31 PM PDT 24 May 30 02:38:27 PM PDT 24 336619730000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.464841843 May 30 02:05:29 PM PDT 24 May 30 02:44:19 PM PDT 24 336671910000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1305842815 May 30 02:05:30 PM PDT 24 May 30 02:37:20 PM PDT 24 336637570000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4215502401 May 30 02:05:14 PM PDT 24 May 30 02:37:05 PM PDT 24 336752370000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1518442236 May 30 02:05:30 PM PDT 24 May 30 02:40:15 PM PDT 24 336541650000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2737659525 May 30 02:05:30 PM PDT 24 May 30 02:41:52 PM PDT 24 336698350000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.313561588 May 30 02:05:14 PM PDT 24 May 30 02:37:41 PM PDT 24 336419610000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3114506621 May 30 02:05:29 PM PDT 24 May 30 02:45:09 PM PDT 24 336587290000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2648523817 May 30 02:05:28 PM PDT 24 May 30 02:35:59 PM PDT 24 336584110000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2365579283 May 30 02:05:31 PM PDT 24 May 30 02:40:50 PM PDT 24 336668990000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.848239059 May 30 02:05:27 PM PDT 24 May 30 02:40:39 PM PDT 24 336728370000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2060540041 May 30 02:05:24 PM PDT 24 May 30 02:36:45 PM PDT 24 337007650000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2776635993 May 30 02:05:14 PM PDT 24 May 30 02:37:26 PM PDT 24 336401130000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1656612069 May 30 02:05:27 PM PDT 24 May 30 02:36:07 PM PDT 24 336542890000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1299400798 May 30 02:05:29 PM PDT 24 May 30 02:40:00 PM PDT 24 336547850000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3356411496 May 30 02:05:28 PM PDT 24 May 30 02:45:06 PM PDT 24 336736090000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4094276820 May 30 02:05:27 PM PDT 24 May 30 02:39:28 PM PDT 24 336513370000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.20301249 May 30 02:05:30 PM PDT 24 May 30 02:41:55 PM PDT 24 336442050000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1009623559 May 30 02:05:25 PM PDT 24 May 30 02:35:55 PM PDT 24 336355090000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2589423153 May 30 02:05:30 PM PDT 24 May 30 02:40:46 PM PDT 24 336978770000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.300566180 May 30 02:05:27 PM PDT 24 May 30 02:36:53 PM PDT 24 336495170000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3531957942 May 30 02:05:24 PM PDT 24 May 30 02:41:08 PM PDT 24 337030250000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3267330868 May 30 02:05:29 PM PDT 24 May 30 02:36:06 PM PDT 24 337024450000 ps
T151 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1041461041 May 30 02:05:31 PM PDT 24 May 30 02:40:19 PM PDT 24 336973430000 ps
T152 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2562739648 May 30 02:05:15 PM PDT 24 May 30 02:37:14 PM PDT 24 336738950000 ps
T153 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3020715861 May 30 02:05:28 PM PDT 24 May 30 02:47:17 PM PDT 24 336440950000 ps
T154 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2511662806 May 30 02:05:13 PM PDT 24 May 30 02:39:46 PM PDT 24 336763050000 ps
T155 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2635173324 May 30 02:05:27 PM PDT 24 May 30 02:41:24 PM PDT 24 336456730000 ps
T156 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2413623131 May 30 02:05:30 PM PDT 24 May 30 02:41:57 PM PDT 24 336826390000 ps
T157 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2712085904 May 30 02:05:28 PM PDT 24 May 30 02:39:42 PM PDT 24 337017790000 ps
T158 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1058908038 May 30 02:05:26 PM PDT 24 May 30 02:36:36 PM PDT 24 336839530000 ps
T159 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.275480571 May 30 02:05:31 PM PDT 24 May 30 02:37:56 PM PDT 24 336498110000 ps
T160 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2459602296 May 30 02:05:30 PM PDT 24 May 30 02:44:46 PM PDT 24 337006410000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.953053553 May 30 02:05:32 PM PDT 24 May 30 02:41:19 PM PDT 24 336502910000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2028839233 May 30 02:05:37 PM PDT 24 May 30 02:38:04 PM PDT 24 336322210000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2454685628 May 30 02:05:32 PM PDT 24 May 30 02:41:01 PM PDT 24 336913790000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2115046980 May 30 02:05:38 PM PDT 24 May 30 02:39:22 PM PDT 24 336801150000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3435774452 May 30 02:05:30 PM PDT 24 May 30 02:40:39 PM PDT 24 337034830000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2849523528 May 30 02:05:45 PM PDT 24 May 30 02:40:51 PM PDT 24 336857170000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3275211961 May 30 02:05:37 PM PDT 24 May 30 02:34:43 PM PDT 24 336734410000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.620184125 May 30 02:05:30 PM PDT 24 May 30 02:41:07 PM PDT 24 336644250000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2829264929 May 30 02:05:30 PM PDT 24 May 30 02:37:26 PM PDT 24 336655230000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2135473342 May 30 02:05:40 PM PDT 24 May 30 02:36:45 PM PDT 24 336957390000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1463004674 May 30 02:05:43 PM PDT 24 May 30 02:41:59 PM PDT 24 336785750000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3484142817 May 30 02:05:39 PM PDT 24 May 30 02:38:40 PM PDT 24 336483150000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1476924426 May 30 02:05:39 PM PDT 24 May 30 02:29:49 PM PDT 24 336594650000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.725595093 May 30 02:05:42 PM PDT 24 May 30 02:36:44 PM PDT 24 336982610000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2292180402 May 30 02:05:31 PM PDT 24 May 30 02:40:46 PM PDT 24 336895830000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.610129054 May 30 02:05:43 PM PDT 24 May 30 02:41:49 PM PDT 24 336422830000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3127943742 May 30 02:05:27 PM PDT 24 May 30 02:36:13 PM PDT 24 336440830000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2435140165 May 30 02:05:42 PM PDT 24 May 30 02:42:02 PM PDT 24 336902210000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.35984010 May 30 02:05:38 PM PDT 24 May 30 02:40:04 PM PDT 24 336798970000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.629237731 May 30 02:05:42 PM PDT 24 May 30 02:37:35 PM PDT 24 336823030000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3722664653 May 30 02:05:28 PM PDT 24 May 30 02:36:26 PM PDT 24 336321430000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1447994175 May 30 02:05:43 PM PDT 24 May 30 02:42:11 PM PDT 24 336531930000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2846843463 May 30 02:05:37 PM PDT 24 May 30 02:39:00 PM PDT 24 336400510000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1022816930 May 30 02:05:30 PM PDT 24 May 30 02:41:20 PM PDT 24 336864750000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1444474425 May 30 02:05:46 PM PDT 24 May 30 02:40:52 PM PDT 24 336494010000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1874683925 May 30 02:05:32 PM PDT 24 May 30 02:41:27 PM PDT 24 337025730000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1752787064 May 30 02:05:38 PM PDT 24 May 30 02:40:14 PM PDT 24 337125070000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4091299017 May 30 02:05:27 PM PDT 24 May 30 02:37:07 PM PDT 24 336953030000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2933029791 May 30 02:05:30 PM PDT 24 May 30 02:41:33 PM PDT 24 336697870000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1988344974 May 30 02:05:30 PM PDT 24 May 30 02:38:55 PM PDT 24 336637550000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3768050971 May 30 02:05:36 PM PDT 24 May 30 02:37:54 PM PDT 24 336566150000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3111356367 May 30 02:05:39 PM PDT 24 May 30 02:41:27 PM PDT 24 337024130000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.994240911 May 30 02:05:41 PM PDT 24 May 30 02:37:44 PM PDT 24 336590850000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1292095417 May 30 02:05:39 PM PDT 24 May 30 02:37:58 PM PDT 24 336670510000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.736830558 May 30 02:05:43 PM PDT 24 May 30 02:37:04 PM PDT 24 336635190000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1691988062 May 30 02:05:42 PM PDT 24 May 30 02:36:43 PM PDT 24 336660690000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4246245577 May 30 02:05:27 PM PDT 24 May 30 02:36:39 PM PDT 24 336656530000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4248280678 May 30 02:05:30 PM PDT 24 May 30 02:38:36 PM PDT 24 336432810000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3849483275 May 30 02:05:27 PM PDT 24 May 30 02:36:59 PM PDT 24 336472170000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3024603262 May 30 02:05:36 PM PDT 24 May 30 02:41:17 PM PDT 24 337029090000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3810138478 May 30 02:05:29 PM PDT 24 May 30 02:32:45 PM PDT 24 336295890000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4177490316 May 30 02:05:29 PM PDT 24 May 30 02:33:18 PM PDT 24 337085510000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4144167357 May 30 02:05:45 PM PDT 24 May 30 02:40:54 PM PDT 24 336712990000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3236565350 May 30 02:05:43 PM PDT 24 May 30 02:39:57 PM PDT 24 336854030000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2594349366 May 30 02:05:38 PM PDT 24 May 30 02:37:57 PM PDT 24 336707750000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1083950472 May 30 02:05:30 PM PDT 24 May 30 02:39:06 PM PDT 24 336824870000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3962804094 May 30 02:05:31 PM PDT 24 May 30 02:36:39 PM PDT 24 336745550000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1952086502 May 30 02:05:44 PM PDT 24 May 30 02:39:57 PM PDT 24 336965990000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2771982004 May 30 02:05:30 PM PDT 24 May 30 02:41:05 PM PDT 24 336552190000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3075325619 May 30 02:05:44 PM PDT 24 May 30 02:40:54 PM PDT 24 336624870000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1914743745
Short name T7
Test name
Test status
Simulation time 1569310000 ps
CPU time 4.29 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164872 kb
Host smart-bf2ca92f-5c28-4d07-aec3-fd610b235be3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1914743745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1914743745
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2240815954
Short name T22
Test name
Test status
Simulation time 337076190000 ps
CPU time 888.16 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:55 PM PDT 24
Peak memory 160824 kb
Host smart-ca478aa9-eb53-4659-bc16-3e3fa3e2548e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2240815954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2240815954
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2829264929
Short name T39
Test name
Test status
Simulation time 336655230000 ps
CPU time 779.01 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:37:26 PM PDT 24
Peak memory 160816 kb
Host smart-b3fd1d68-4c95-40ee-82d4-aa8f9377e2c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2829264929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2829264929
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.43438011
Short name T25
Test name
Test status
Simulation time 1320290000 ps
CPU time 3.35 seconds
Started May 30 01:50:37 PM PDT 24
Finished May 30 01:50:45 PM PDT 24
Peak memory 164832 kb
Host smart-32edd052-3f72-4f45-851f-c1f83a015d5e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=43438011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.43438011
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1874683925
Short name T176
Test name
Test status
Simulation time 337025730000 ps
CPU time 873.46 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:41:27 PM PDT 24
Peak memory 160800 kb
Host smart-cbf4a080-df9c-4ddf-b223-911669e31196
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1874683925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1874683925
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1083950472
Short name T196
Test name
Test status
Simulation time 336824870000 ps
CPU time 805.32 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:39:06 PM PDT 24
Peak memory 160824 kb
Host smart-6bf503fa-db7d-44b6-a2f2-ee79755fd3c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1083950472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1083950472
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4246245577
Short name T187
Test name
Test status
Simulation time 336656530000 ps
CPU time 748.68 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:36:39 PM PDT 24
Peak memory 160800 kb
Host smart-f65f5015-3151-4c14-ac9f-bf7aab7b6d32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4246245577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.4246245577
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2933029791
Short name T179
Test name
Test status
Simulation time 336697870000 ps
CPU time 852.67 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:33 PM PDT 24
Peak memory 160824 kb
Host smart-3dc943af-153b-47f8-b929-59f2138758a7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933029791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2933029791
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1022816930
Short name T174
Test name
Test status
Simulation time 336864750000 ps
CPU time 849.2 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:20 PM PDT 24
Peak memory 160824 kb
Host smart-54126d53-7ee4-4f08-bc27-289f87b08ff4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1022816930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1022816930
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3849483275
Short name T189
Test name
Test status
Simulation time 336472170000 ps
CPU time 760.72 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:36:59 PM PDT 24
Peak memory 160800 kb
Host smart-0dd7f3ca-2a84-4f0e-ae1c-d9a81c3ebb83
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3849483275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3849483275
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2771982004
Short name T199
Test name
Test status
Simulation time 336552190000 ps
CPU time 845.03 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:05 PM PDT 24
Peak memory 160824 kb
Host smart-a85b2a84-e4cf-49ed-b054-3d2b8ab0f6ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2771982004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2771982004
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2292180402
Short name T165
Test name
Test status
Simulation time 336895830000 ps
CPU time 850.74 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:40:46 PM PDT 24
Peak memory 160796 kb
Host smart-60615de7-cca8-4e26-8ad8-b6f0cc945a19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292180402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2292180402
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4248280678
Short name T188
Test name
Test status
Simulation time 336432810000 ps
CPU time 788.51 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:38:36 PM PDT 24
Peak memory 160824 kb
Host smart-f53a372c-55ae-4bbd-9b46-3d16caf2853c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4248280678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4248280678
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3962804094
Short name T197
Test name
Test status
Simulation time 336745550000 ps
CPU time 766.07 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:36:39 PM PDT 24
Peak memory 160748 kb
Host smart-61297ead-4a2a-418e-ad1f-a4ce546e732f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3962804094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3962804094
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.620184125
Short name T38
Test name
Test status
Simulation time 336644250000 ps
CPU time 863.04 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:07 PM PDT 24
Peak memory 160792 kb
Host smart-63cc0566-2dd0-414e-8b6f-31cd26370a4f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=620184125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.620184125
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3127943742
Short name T167
Test name
Test status
Simulation time 336440830000 ps
CPU time 751.93 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:36:13 PM PDT 24
Peak memory 160792 kb
Host smart-a503600d-6911-4dde-bb28-1a2b9f50a4ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3127943742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3127943742
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3435774452
Short name T35
Test name
Test status
Simulation time 337034830000 ps
CPU time 870.56 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:40:39 PM PDT 24
Peak memory 160804 kb
Host smart-f72c8627-ab1d-401e-b7b4-22ffbe4cb890
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3435774452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3435774452
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2135473342
Short name T40
Test name
Test status
Simulation time 336957390000 ps
CPU time 764.71 seconds
Started May 30 02:05:40 PM PDT 24
Finished May 30 02:36:45 PM PDT 24
Peak memory 160824 kb
Host smart-18923c55-ee71-4e21-8235-ee465be5111a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2135473342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2135473342
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1447994175
Short name T172
Test name
Test status
Simulation time 336531930000 ps
CPU time 872.94 seconds
Started May 30 02:05:43 PM PDT 24
Finished May 30 02:42:11 PM PDT 24
Peak memory 160824 kb
Host smart-12e13ed7-486a-4578-bfd6-23085ffbe0dc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1447994175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1447994175
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3024603262
Short name T190
Test name
Test status
Simulation time 337029090000 ps
CPU time 875.06 seconds
Started May 30 02:05:36 PM PDT 24
Finished May 30 02:41:17 PM PDT 24
Peak memory 160780 kb
Host smart-58982004-e89e-49cc-9221-7f8bba153793
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3024603262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3024603262
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3768050971
Short name T181
Test name
Test status
Simulation time 336566150000 ps
CPU time 798.26 seconds
Started May 30 02:05:36 PM PDT 24
Finished May 30 02:37:54 PM PDT 24
Peak memory 160792 kb
Host smart-5cf1457e-033f-4bee-8194-3b549f7f1943
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3768050971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3768050971
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.610129054
Short name T166
Test name
Test status
Simulation time 336422830000 ps
CPU time 859.4 seconds
Started May 30 02:05:43 PM PDT 24
Finished May 30 02:41:49 PM PDT 24
Peak memory 160820 kb
Host smart-aa0fb0e7-363f-4b9b-8de2-26bad99d32c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=610129054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.610129054
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.994240911
Short name T183
Test name
Test status
Simulation time 336590850000 ps
CPU time 790.12 seconds
Started May 30 02:05:41 PM PDT 24
Finished May 30 02:37:44 PM PDT 24
Peak memory 160820 kb
Host smart-205a6ffe-f76d-40ca-a438-0fb77f4fde51
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=994240911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.994240911
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1444474425
Short name T175
Test name
Test status
Simulation time 336494010000 ps
CPU time 854.45 seconds
Started May 30 02:05:46 PM PDT 24
Finished May 30 02:40:52 PM PDT 24
Peak memory 160820 kb
Host smart-3add5858-824a-454c-a95f-658c8df4abec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1444474425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1444474425
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1691988062
Short name T186
Test name
Test status
Simulation time 336660690000 ps
CPU time 747.93 seconds
Started May 30 02:05:42 PM PDT 24
Finished May 30 02:36:43 PM PDT 24
Peak memory 160800 kb
Host smart-91c5729f-a40f-44cd-b399-47aa97f9cc06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1691988062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1691988062
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2849523528
Short name T36
Test name
Test status
Simulation time 336857170000 ps
CPU time 852.98 seconds
Started May 30 02:05:45 PM PDT 24
Finished May 30 02:40:51 PM PDT 24
Peak memory 160820 kb
Host smart-5799f7a6-aa92-4805-b1bb-68ef355aebe6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2849523528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2849523528
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.4091299017
Short name T178
Test name
Test status
Simulation time 336953030000 ps
CPU time 759.16 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:37:07 PM PDT 24
Peak memory 160792 kb
Host smart-6add7086-fa28-44f4-aead-02d5de1fed70
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4091299017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.4091299017
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2846843463
Short name T173
Test name
Test status
Simulation time 336400510000 ps
CPU time 829.15 seconds
Started May 30 02:05:37 PM PDT 24
Finished May 30 02:39:00 PM PDT 24
Peak memory 160800 kb
Host smart-9819eb41-964c-4e95-adb7-114e622f89f7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2846843463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2846843463
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3275211961
Short name T37
Test name
Test status
Simulation time 336734410000 ps
CPU time 709.41 seconds
Started May 30 02:05:37 PM PDT 24
Finished May 30 02:34:43 PM PDT 24
Peak memory 160800 kb
Host smart-b3c7d856-3820-483b-9fed-8dff845a994b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3275211961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3275211961
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.736830558
Short name T185
Test name
Test status
Simulation time 336635190000 ps
CPU time 754.86 seconds
Started May 30 02:05:43 PM PDT 24
Finished May 30 02:37:04 PM PDT 24
Peak memory 160796 kb
Host smart-7a046c86-ada8-420d-8758-88b197cca2da
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=736830558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.736830558
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1752787064
Short name T177
Test name
Test status
Simulation time 337125070000 ps
CPU time 855.06 seconds
Started May 30 02:05:38 PM PDT 24
Finished May 30 02:40:14 PM PDT 24
Peak memory 160816 kb
Host smart-09a31251-1eaf-446c-ad3a-a7b24576c152
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1752787064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1752787064
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3236565350
Short name T194
Test name
Test status
Simulation time 336854030000 ps
CPU time 851.19 seconds
Started May 30 02:05:43 PM PDT 24
Finished May 30 02:39:57 PM PDT 24
Peak memory 160860 kb
Host smart-19fed192-5e4f-4500-a63e-c1c73ea77d28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3236565350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3236565350
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.725595093
Short name T164
Test name
Test status
Simulation time 336982610000 ps
CPU time 751.25 seconds
Started May 30 02:05:42 PM PDT 24
Finished May 30 02:36:44 PM PDT 24
Peak memory 160796 kb
Host smart-b1f32157-72a1-4213-ace5-12a206cd93d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=725595093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.725595093
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1476924426
Short name T163
Test name
Test status
Simulation time 336594650000 ps
CPU time 565.88 seconds
Started May 30 02:05:39 PM PDT 24
Finished May 30 02:29:49 PM PDT 24
Peak memory 160780 kb
Host smart-17931a9c-4315-4dcc-b5a9-c59a66e0986e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1476924426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1476924426
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1463004674
Short name T161
Test name
Test status
Simulation time 336785750000 ps
CPU time 859.27 seconds
Started May 30 02:05:43 PM PDT 24
Finished May 30 02:41:59 PM PDT 24
Peak memory 160824 kb
Host smart-efaf60a8-e7c4-4ea3-a5c2-3fc592bcb9a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1463004674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1463004674
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.629237731
Short name T170
Test name
Test status
Simulation time 336823030000 ps
CPU time 783.03 seconds
Started May 30 02:05:42 PM PDT 24
Finished May 30 02:37:35 PM PDT 24
Peak memory 160820 kb
Host smart-04b2cd76-c023-4226-bd02-1e1f07791b15
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=629237731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.629237731
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2594349366
Short name T195
Test name
Test status
Simulation time 336707750000 ps
CPU time 788.27 seconds
Started May 30 02:05:38 PM PDT 24
Finished May 30 02:37:57 PM PDT 24
Peak memory 160836 kb
Host smart-c75ac550-1ca2-488a-a825-6e21ca366194
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2594349366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2594349366
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3722664653
Short name T171
Test name
Test status
Simulation time 336321430000 ps
CPU time 753.1 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:36:26 PM PDT 24
Peak memory 160792 kb
Host smart-3ca2e902-c8c0-4fb7-b622-ec1cd8e1c366
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3722664653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3722664653
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3484142817
Short name T162
Test name
Test status
Simulation time 336483150000 ps
CPU time 802.25 seconds
Started May 30 02:05:39 PM PDT 24
Finished May 30 02:38:40 PM PDT 24
Peak memory 160836 kb
Host smart-6e6785b7-c030-4ce3-a38a-5121b46a1002
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3484142817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3484142817
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3111356367
Short name T182
Test name
Test status
Simulation time 337024130000 ps
CPU time 865.62 seconds
Started May 30 02:05:39 PM PDT 24
Finished May 30 02:41:27 PM PDT 24
Peak memory 160796 kb
Host smart-f5403b07-cdf9-4096-8f8d-f0a53bf35666
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111356367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3111356367
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2115046980
Short name T34
Test name
Test status
Simulation time 336801150000 ps
CPU time 836.45 seconds
Started May 30 02:05:38 PM PDT 24
Finished May 30 02:39:22 PM PDT 24
Peak memory 160804 kb
Host smart-ebc697c3-6669-4593-a277-59adfa8b0d89
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2115046980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2115046980
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2435140165
Short name T168
Test name
Test status
Simulation time 336902210000 ps
CPU time 863.8 seconds
Started May 30 02:05:42 PM PDT 24
Finished May 30 02:42:02 PM PDT 24
Peak memory 160824 kb
Host smart-6e0f7cf0-b5ef-4ba3-8324-e9ad02b61b93
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2435140165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2435140165
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1292095417
Short name T184
Test name
Test status
Simulation time 336670510000 ps
CPU time 789.29 seconds
Started May 30 02:05:39 PM PDT 24
Finished May 30 02:37:58 PM PDT 24
Peak memory 160836 kb
Host smart-5d13e485-8738-4373-8516-ce51f859eca8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1292095417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1292095417
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3075325619
Short name T200
Test name
Test status
Simulation time 336624870000 ps
CPU time 856.52 seconds
Started May 30 02:05:44 PM PDT 24
Finished May 30 02:40:54 PM PDT 24
Peak memory 160820 kb
Host smart-d5287e63-d370-4275-8460-3efd3660a7da
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3075325619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3075325619
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1952086502
Short name T198
Test name
Test status
Simulation time 336965990000 ps
CPU time 845.29 seconds
Started May 30 02:05:44 PM PDT 24
Finished May 30 02:39:57 PM PDT 24
Peak memory 160860 kb
Host smart-6f82f2be-3857-4270-9bb4-1cac017cea99
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1952086502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1952086502
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2028839233
Short name T32
Test name
Test status
Simulation time 336322210000 ps
CPU time 801.73 seconds
Started May 30 02:05:37 PM PDT 24
Finished May 30 02:38:04 PM PDT 24
Peak memory 160792 kb
Host smart-9c88b6d3-d50e-4d7e-8c92-c7a83636bba7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2028839233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2028839233
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4144167357
Short name T193
Test name
Test status
Simulation time 336712990000 ps
CPU time 854.65 seconds
Started May 30 02:05:45 PM PDT 24
Finished May 30 02:40:54 PM PDT 24
Peak memory 160820 kb
Host smart-55de709c-9487-48d4-9db5-f82056f4c699
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4144167357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4144167357
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.35984010
Short name T169
Test name
Test status
Simulation time 336798970000 ps
CPU time 851.22 seconds
Started May 30 02:05:38 PM PDT 24
Finished May 30 02:40:04 PM PDT 24
Peak memory 160792 kb
Host smart-3b825e3a-204f-4a9d-872f-670153c714e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=35984010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.35984010
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2454685628
Short name T33
Test name
Test status
Simulation time 336913790000 ps
CPU time 859.05 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:41:01 PM PDT 24
Peak memory 160800 kb
Host smart-eead277d-5684-4d3a-b435-5c678affa70c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2454685628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2454685628
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3810138478
Short name T191
Test name
Test status
Simulation time 336295890000 ps
CPU time 657.29 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:32:45 PM PDT 24
Peak memory 160808 kb
Host smart-059a0bb8-16a8-45ca-880c-15a76495f5dd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3810138478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3810138478
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.953053553
Short name T31
Test name
Test status
Simulation time 336502910000 ps
CPU time 869.62 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:41:19 PM PDT 24
Peak memory 160780 kb
Host smart-ca1e6386-67fe-4227-8ca7-69c985087b4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=953053553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.953053553
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1988344974
Short name T180
Test name
Test status
Simulation time 336637550000 ps
CPU time 809.96 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:38:55 PM PDT 24
Peak memory 160816 kb
Host smart-8fb3bf86-2a0f-4de8-94b8-ee65f6cf589f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1988344974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1988344974
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4177490316
Short name T192
Test name
Test status
Simulation time 337085510000 ps
CPU time 670.01 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:33:18 PM PDT 24
Peak memory 160808 kb
Host smart-f87e845a-dfe1-450f-850f-09efdcfcb1ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4177490316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.4177490316
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2520978844
Short name T121
Test name
Test status
Simulation time 336459390000 ps
CPU time 1023.9 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:47:05 PM PDT 24
Peak memory 160748 kb
Host smart-fbee5a07-6dd6-4581-8037-37a2564a7484
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2520978844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2520978844
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.313561588
Short name T134
Test name
Test status
Simulation time 336419610000 ps
CPU time 792.39 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:37:41 PM PDT 24
Peak memory 160800 kb
Host smart-9d9b3981-6352-4a78-930c-dcea8132829d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=313561588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.313561588
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3020715861
Short name T153
Test name
Test status
Simulation time 336440950000 ps
CPU time 1015.68 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:47:17 PM PDT 24
Peak memory 160772 kb
Host smart-da9d474d-6515-486f-817b-aa5cf8481e3b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3020715861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3020715861
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2449093666
Short name T128
Test name
Test status
Simulation time 336619730000 ps
CPU time 809.3 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:38:27 PM PDT 24
Peak memory 160740 kb
Host smart-6992cde1-09ad-48a5-8e5c-570df012b595
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2449093666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2449093666
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1058908038
Short name T158
Test name
Test status
Simulation time 336839530000 ps
CPU time 763.07 seconds
Started May 30 02:05:26 PM PDT 24
Finished May 30 02:36:36 PM PDT 24
Peak memory 160824 kb
Host smart-c9c6b60f-30e3-4946-8891-a8b5ce10f708
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1058908038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1058908038
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.778755489
Short name T122
Test name
Test status
Simulation time 336671170000 ps
CPU time 928.15 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:44:50 PM PDT 24
Peak memory 160764 kb
Host smart-9f094542-c87c-40fb-90ca-4e1d7a15a432
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=778755489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.778755489
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3621992970
Short name T123
Test name
Test status
Simulation time 336385910000 ps
CPU time 827.58 seconds
Started May 30 02:05:25 PM PDT 24
Finished May 30 02:38:51 PM PDT 24
Peak memory 160796 kb
Host smart-292f87c9-cd2a-41a9-8f4e-5e824cefeaf9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621992970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3621992970
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3114506621
Short name T135
Test name
Test status
Simulation time 336587290000 ps
CPU time 937.12 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:45:09 PM PDT 24
Peak memory 160768 kb
Host smart-43f79fe1-a201-4680-a098-c19fc957d51d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3114506621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3114506621
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.491069608
Short name T19
Test name
Test status
Simulation time 336885530000 ps
CPU time 759.64 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:36:25 PM PDT 24
Peak memory 160820 kb
Host smart-3f8eb1bc-ff2d-45c5-952c-5d22cff7e8b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=491069608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.491069608
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3356411496
Short name T143
Test name
Test status
Simulation time 336736090000 ps
CPU time 932.34 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:45:06 PM PDT 24
Peak memory 160768 kb
Host smart-251e6155-abe8-420d-8bdf-5d5a8900a44d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3356411496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3356411496
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.275480571
Short name T159
Test name
Test status
Simulation time 336498110000 ps
CPU time 791.63 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:37:56 PM PDT 24
Peak memory 160736 kb
Host smart-e86c31f1-c5ee-4d63-be91-52f93f95312d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=275480571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.275480571
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4215502401
Short name T131
Test name
Test status
Simulation time 336752370000 ps
CPU time 772.88 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:37:05 PM PDT 24
Peak memory 160820 kb
Host smart-3c23bcf4-e391-45e1-8947-2bbd68f375f8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4215502401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.4215502401
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1009623559
Short name T146
Test name
Test status
Simulation time 336355090000 ps
CPU time 747.56 seconds
Started May 30 02:05:25 PM PDT 24
Finished May 30 02:35:55 PM PDT 24
Peak memory 160704 kb
Host smart-6e2407f0-54c3-40f5-bebe-fbdb46809961
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1009623559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1009623559
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3310880051
Short name T20
Test name
Test status
Simulation time 336444170000 ps
CPU time 779.55 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:37:37 PM PDT 24
Peak memory 160828 kb
Host smart-fc665192-a101-4f33-8e78-19ac6761a7d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3310880051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3310880051
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1305842815
Short name T130
Test name
Test status
Simulation time 336637570000 ps
CPU time 773.76 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:37:20 PM PDT 24
Peak memory 160828 kb
Host smart-d4a7ddcd-e9c9-46c9-aaa2-535d1f43754a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1305842815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1305842815
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1050792221
Short name T16
Test name
Test status
Simulation time 336439030000 ps
CPU time 708.71 seconds
Started May 30 02:05:26 PM PDT 24
Finished May 30 02:34:36 PM PDT 24
Peak memory 160816 kb
Host smart-35695cd5-ca0b-46ac-a470-5f4d14337c03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1050792221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1050792221
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.300566180
Short name T148
Test name
Test status
Simulation time 336495170000 ps
CPU time 772.94 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:36:53 PM PDT 24
Peak memory 160824 kb
Host smart-571f9a4b-bd6b-4bb8-82fd-dcb978aed016
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300566180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.300566180
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1449448269
Short name T18
Test name
Test status
Simulation time 336688650000 ps
CPU time 649.04 seconds
Started May 30 02:05:24 PM PDT 24
Finished May 30 02:32:22 PM PDT 24
Peak memory 160800 kb
Host smart-3f4b801c-7f65-495c-b608-bb3d773eaa99
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1449448269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1449448269
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1041461041
Short name T151
Test name
Test status
Simulation time 336973430000 ps
CPU time 834.63 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:40:19 PM PDT 24
Peak memory 160808 kb
Host smart-324a4cde-5151-4ec2-9dfc-3b501a1ae3e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1041461041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1041461041
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1299400798
Short name T142
Test name
Test status
Simulation time 336547850000 ps
CPU time 847.45 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:40:00 PM PDT 24
Peak memory 160804 kb
Host smart-eecf0afe-2a62-40c1-b6c0-a2c6a65375a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1299400798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1299400798
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2712085904
Short name T157
Test name
Test status
Simulation time 337017790000 ps
CPU time 844.05 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:39:42 PM PDT 24
Peak memory 160804 kb
Host smart-68d607f8-3c1a-4276-828f-825b1b1b2acf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2712085904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2712085904
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3267330868
Short name T150
Test name
Test status
Simulation time 337024450000 ps
CPU time 754.67 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:36:06 PM PDT 24
Peak memory 160820 kb
Host smart-fec557f9-06e3-40a3-b0da-0c7643ae08dc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3267330868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3267330868
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2776635993
Short name T140
Test name
Test status
Simulation time 336401130000 ps
CPU time 782.35 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:37:26 PM PDT 24
Peak memory 160820 kb
Host smart-6e900ac4-c532-4371-a561-cdcc5849c514
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2776635993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2776635993
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.4182778354
Short name T14
Test name
Test status
Simulation time 336661470000 ps
CPU time 643.43 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:32:06 PM PDT 24
Peak memory 160824 kb
Host smart-b5331c44-30b2-464d-ae68-b9be0a23af43
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4182778354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.4182778354
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2413623131
Short name T156
Test name
Test status
Simulation time 336826390000 ps
CPU time 888.19 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:57 PM PDT 24
Peak memory 160824 kb
Host smart-449309cf-661f-4e2a-b283-283072601e4e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2413623131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2413623131
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2737659525
Short name T133
Test name
Test status
Simulation time 336698350000 ps
CPU time 884.01 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:52 PM PDT 24
Peak memory 160824 kb
Host smart-06d67dd2-94f5-4f34-bc76-5f6cf6369ce6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2737659525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2737659525
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.20301249
Short name T145
Test name
Test status
Simulation time 336442050000 ps
CPU time 888.12 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:41:55 PM PDT 24
Peak memory 160800 kb
Host smart-68869422-31ce-41fc-8ce2-2db8e811f415
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=20301249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.20301249
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3531957942
Short name T149
Test name
Test status
Simulation time 337030250000 ps
CPU time 889.87 seconds
Started May 30 02:05:24 PM PDT 24
Finished May 30 02:41:08 PM PDT 24
Peak memory 160784 kb
Host smart-98513d20-b725-4244-ad1a-f536e259be20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3531957942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3531957942
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1518442236
Short name T132
Test name
Test status
Simulation time 336541650000 ps
CPU time 832.11 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:40:15 PM PDT 24
Peak memory 160808 kb
Host smart-05895650-963b-4c47-b650-0a5881b41a23
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1518442236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1518442236
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2589423153
Short name T147
Test name
Test status
Simulation time 336978770000 ps
CPU time 836.18 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:40:46 PM PDT 24
Peak memory 160808 kb
Host smart-1b6f8b34-f1ed-40ea-9b2d-aa8a6f52808c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2589423153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2589423153
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2060540041
Short name T139
Test name
Test status
Simulation time 337007650000 ps
CPU time 770.99 seconds
Started May 30 02:05:24 PM PDT 24
Finished May 30 02:36:45 PM PDT 24
Peak memory 160768 kb
Host smart-f01ea65c-38c0-46a6-8754-995886cd8ebd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2060540041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2060540041
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2648523817
Short name T136
Test name
Test status
Simulation time 336584110000 ps
CPU time 746.04 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:35:59 PM PDT 24
Peak memory 160820 kb
Host smart-d68fabc0-3f7f-4a22-ad43-61150df586bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2648523817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2648523817
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3351130061
Short name T124
Test name
Test status
Simulation time 336953610000 ps
CPU time 703.07 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:34:17 PM PDT 24
Peak memory 160812 kb
Host smart-ead048e6-a81c-4388-ab4d-e66da9628438
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3351130061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3351130061
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2511662806
Short name T154
Test name
Test status
Simulation time 336763050000 ps
CPU time 854.64 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:39:46 PM PDT 24
Peak memory 160796 kb
Host smart-253a7eb2-9c9a-4878-8630-16671da58c75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2511662806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2511662806
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4094276820
Short name T144
Test name
Test status
Simulation time 336513370000 ps
CPU time 844.89 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:39:28 PM PDT 24
Peak memory 160816 kb
Host smart-3608485b-da2a-470e-aac4-173d8295bb3a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4094276820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4094276820
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1464940544
Short name T127
Test name
Test status
Simulation time 336801230000 ps
CPU time 795.08 seconds
Started May 30 02:05:26 PM PDT 24
Finished May 30 02:37:18 PM PDT 24
Peak memory 160808 kb
Host smart-ab751ee1-15fa-4580-8180-8c2087567665
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1464940544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1464940544
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2365579283
Short name T137
Test name
Test status
Simulation time 336668990000 ps
CPU time 835.94 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:40:50 PM PDT 24
Peak memory 160808 kb
Host smart-ecb9cf5e-a128-4d9f-829f-eb947ea298a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2365579283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2365579283
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.865468710
Short name T21
Test name
Test status
Simulation time 336965190000 ps
CPU time 932.38 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:45:07 PM PDT 24
Peak memory 160764 kb
Host smart-d7db0d84-04fe-4e2d-9fe6-7480dfdf4e03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=865468710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.865468710
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.464841843
Short name T129
Test name
Test status
Simulation time 336671910000 ps
CPU time 932.66 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:44:19 PM PDT 24
Peak memory 160836 kb
Host smart-79074293-a6a6-47a2-b9b4-20a1dcda4d1d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=464841843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.464841843
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.848239059
Short name T138
Test name
Test status
Simulation time 336728370000 ps
CPU time 868.29 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:40:39 PM PDT 24
Peak memory 160804 kb
Host smart-1c3549d6-6905-456f-b144-84cbdb64537d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=848239059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.848239059
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2635173324
Short name T155
Test name
Test status
Simulation time 336456730000 ps
CPU time 884.84 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:41:24 PM PDT 24
Peak memory 160828 kb
Host smart-ea22ccad-d807-4c53-9ea6-f00bc72028e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2635173324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2635173324
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2459602296
Short name T160
Test name
Test status
Simulation time 337006410000 ps
CPU time 942.28 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:44:46 PM PDT 24
Peak memory 160840 kb
Host smart-69786c13-0c6f-4ce8-9476-0cc07b908ef3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2459602296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2459602296
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.733075767
Short name T126
Test name
Test status
Simulation time 336882470000 ps
CPU time 942.97 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:44:42 PM PDT 24
Peak memory 160836 kb
Host smart-34084261-1e42-4c12-9ffb-428695d82669
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=733075767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.733075767
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2949828046
Short name T17
Test name
Test status
Simulation time 336541090000 ps
CPU time 887.78 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:41:33 PM PDT 24
Peak memory 160828 kb
Host smart-a5933ff7-b444-4227-a81a-100901fda383
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2949828046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2949828046
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2562739648
Short name T152
Test name
Test status
Simulation time 336738950000 ps
CPU time 782.37 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:37:14 PM PDT 24
Peak memory 160820 kb
Host smart-83f1f979-98ae-4b83-b9f0-d228cd75d2bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2562739648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2562739648
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1532257722
Short name T15
Test name
Test status
Simulation time 336936410000 ps
CPU time 1013.67 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:47:04 PM PDT 24
Peak memory 160764 kb
Host smart-fa84da6e-b754-4483-87c0-a5b06aaddb75
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1532257722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1532257722
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1656612069
Short name T141
Test name
Test status
Simulation time 336542890000 ps
CPU time 749.31 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:36:07 PM PDT 24
Peak memory 160800 kb
Host smart-d0af9f19-5565-499e-9b2a-83a026be7935
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1656612069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1656612069
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4245265786
Short name T125
Test name
Test status
Simulation time 336840770000 ps
CPU time 706.63 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:34:33 PM PDT 24
Peak memory 160732 kb
Host smart-a6211eb5-40f4-490b-a940-866619dbe938
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4245265786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.4245265786
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.915306389
Short name T23
Test name
Test status
Simulation time 336936910000 ps
CPU time 731.62 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:35:50 PM PDT 24
Peak memory 160800 kb
Host smart-3d3353a1-4482-4e1e-ac35-bd25a250aae9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=915306389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.915306389
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4287937634
Short name T92
Test name
Test status
Simulation time 1422990000 ps
CPU time 4.23 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164904 kb
Host smart-c677f56a-f8d9-4601-9b2c-936e6926f079
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4287937634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4287937634
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2382756801
Short name T94
Test name
Test status
Simulation time 1443950000 ps
CPU time 5.38 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164904 kb
Host smart-6555633f-3d18-4c10-a5f3-f80a3c8803b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2382756801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2382756801
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2912196318
Short name T84
Test name
Test status
Simulation time 1494710000 ps
CPU time 5.53 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:54 PM PDT 24
Peak memory 164904 kb
Host smart-d9ae003a-7bb0-4331-bfe2-286d427c20d6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2912196318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2912196318
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1491208701
Short name T114
Test name
Test status
Simulation time 1177390000 ps
CPU time 4.38 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 164588 kb
Host smart-1cb1b257-e456-4b71-b080-38580beec524
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1491208701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1491208701
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.494400178
Short name T117
Test name
Test status
Simulation time 1293150000 ps
CPU time 3.81 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164860 kb
Host smart-3cde2c75-a75c-4fad-bce5-cd30efbe5c53
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=494400178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.494400178
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2447609342
Short name T108
Test name
Test status
Simulation time 1436590000 ps
CPU time 4.83 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 164824 kb
Host smart-1ce7d023-6f12-4038-a34d-61d07851fdad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2447609342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2447609342
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.25704902
Short name T96
Test name
Test status
Simulation time 1482090000 ps
CPU time 4.53 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164768 kb
Host smart-b0f2a3d6-074c-4a55-9d7d-8fcbd7e4e8dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25704902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.25704902
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3598985766
Short name T115
Test name
Test status
Simulation time 1504130000 ps
CPU time 6.54 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:55 PM PDT 24
Peak memory 164868 kb
Host smart-1207ec7d-22be-4b8b-9f90-93d087671cfa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598985766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3598985766
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4248847084
Short name T24
Test name
Test status
Simulation time 1450170000 ps
CPU time 4.81 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164876 kb
Host smart-fc134f04-2a6c-406e-ab8f-ca7d4a696d06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248847084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4248847084
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4223080126
Short name T4
Test name
Test status
Simulation time 1506290000 ps
CPU time 4.61 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164864 kb
Host smart-6d8a5169-a37d-459c-ac25-ae8e3f247f6f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4223080126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4223080126
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2551206309
Short name T86
Test name
Test status
Simulation time 1393270000 ps
CPU time 5.93 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 164884 kb
Host smart-8141c02c-57c8-4951-ac0a-2618925a1e9a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2551206309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2551206309
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4091307439
Short name T100
Test name
Test status
Simulation time 1631730000 ps
CPU time 4.47 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164904 kb
Host smart-3edc7b87-d72f-4384-a82a-45f70efb63b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4091307439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4091307439
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3931202536
Short name T111
Test name
Test status
Simulation time 1410690000 ps
CPU time 4.03 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164872 kb
Host smart-1aa21a84-33f9-4db5-abdd-02a09f66b955
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3931202536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3931202536
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3289453434
Short name T97
Test name
Test status
Simulation time 1548050000 ps
CPU time 4.81 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164864 kb
Host smart-52b459f0-3245-499e-a5fc-fbe5e2ef3006
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3289453434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3289453434
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2610165773
Short name T89
Test name
Test status
Simulation time 1542410000 ps
CPU time 5.05 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:54 PM PDT 24
Peak memory 165020 kb
Host smart-02ff6e81-81ff-425f-b683-3ed2d502863e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610165773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2610165773
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.805234201
Short name T87
Test name
Test status
Simulation time 1583210000 ps
CPU time 5.28 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 165016 kb
Host smart-897a5719-c5a8-434b-8da6-a759b839f622
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=805234201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.805234201
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2070093024
Short name T113
Test name
Test status
Simulation time 1415310000 ps
CPU time 5.2 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164904 kb
Host smart-614a8f01-3ece-4380-87f5-2089deecf336
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2070093024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2070093024
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.754472182
Short name T107
Test name
Test status
Simulation time 1623630000 ps
CPU time 4.07 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164776 kb
Host smart-10a96cbd-0485-4c9b-a1bd-b0e050c24a8c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754472182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.754472182
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.759951391
Short name T105
Test name
Test status
Simulation time 1410990000 ps
CPU time 4.62 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:49 PM PDT 24
Peak memory 164816 kb
Host smart-ccf49dc0-3e6b-4ed9-b195-fd9a20cc2b43
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=759951391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.759951391
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3588574802
Short name T112
Test name
Test status
Simulation time 1442950000 ps
CPU time 4.73 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 165020 kb
Host smart-b1589c21-9d45-41cc-96b2-5085652131c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3588574802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3588574802
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3434479164
Short name T6
Test name
Test status
Simulation time 1522630000 ps
CPU time 6.68 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:55 PM PDT 24
Peak memory 164872 kb
Host smart-239ab248-389a-49d8-8db7-b4d55239a9cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3434479164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3434479164
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4236757745
Short name T81
Test name
Test status
Simulation time 1276390000 ps
CPU time 4.24 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164876 kb
Host smart-532d528a-d35e-4382-b3d9-513f3876828a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236757745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4236757745
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.974858874
Short name T109
Test name
Test status
Simulation time 1508670000 ps
CPU time 4.25 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164852 kb
Host smart-eef6bbd3-5d42-40ba-9539-9ed0e96492d1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974858874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.974858874
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2679379999
Short name T26
Test name
Test status
Simulation time 1334570000 ps
CPU time 4.24 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164868 kb
Host smart-1dbaea79-eabb-4236-95c6-9ed5aa3619f5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2679379999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2679379999
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.113973334
Short name T85
Test name
Test status
Simulation time 1433230000 ps
CPU time 4.99 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164856 kb
Host smart-890b36e2-331c-4f2b-97dd-32b4bfb1322c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113973334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.113973334
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3697049726
Short name T83
Test name
Test status
Simulation time 1215410000 ps
CPU time 4.87 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 164848 kb
Host smart-e6acb60c-94cf-40eb-a689-a9214d79d5d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3697049726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3697049726
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2247377439
Short name T90
Test name
Test status
Simulation time 1539910000 ps
CPU time 6.84 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164860 kb
Host smart-5d093a28-31a4-45e3-931f-d8be9a130000
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2247377439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2247377439
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3413490111
Short name T93
Test name
Test status
Simulation time 1556710000 ps
CPU time 5.17 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164908 kb
Host smart-8a601a59-6b34-4413-a1f9-f1d0bdad36e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3413490111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3413490111
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1315274326
Short name T95
Test name
Test status
Simulation time 1261090000 ps
CPU time 4.06 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:49 PM PDT 24
Peak memory 164864 kb
Host smart-f0fc2c67-3a7e-4249-bffa-1f618c0c28f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1315274326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1315274326
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3937213711
Short name T82
Test name
Test status
Simulation time 1295090000 ps
CPU time 4.75 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164864 kb
Host smart-932c5155-8cc9-4fc4-9ef3-017059b031c3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3937213711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3937213711
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4016681133
Short name T110
Test name
Test status
Simulation time 1341970000 ps
CPU time 4.5 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164872 kb
Host smart-42c14d3a-65fa-40ef-84a3-5b7283cf89e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4016681133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4016681133
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.188168462
Short name T30
Test name
Test status
Simulation time 1532650000 ps
CPU time 5.22 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164864 kb
Host smart-1fdf740a-8757-4988-919f-54593108167c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=188168462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.188168462
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3669049915
Short name T104
Test name
Test status
Simulation time 1508750000 ps
CPU time 4.6 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164784 kb
Host smart-87016fa0-3fb8-4bb3-8845-4a2bead01dd9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669049915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3669049915
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2666730623
Short name T27
Test name
Test status
Simulation time 1412670000 ps
CPU time 4.92 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164908 kb
Host smart-ab15df56-ea23-4667-9aec-0520d7398bf7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2666730623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2666730623
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1616806852
Short name T98
Test name
Test status
Simulation time 1452810000 ps
CPU time 4.7 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 164876 kb
Host smart-9620d589-54d7-4a22-8248-b21db73eb7bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1616806852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1616806852
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3751230521
Short name T102
Test name
Test status
Simulation time 1415250000 ps
CPU time 4.48 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164864 kb
Host smart-2bb7df5c-cc68-4284-9302-bd243c78c561
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3751230521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3751230521
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.391838624
Short name T119
Test name
Test status
Simulation time 1524410000 ps
CPU time 5.24 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164900 kb
Host smart-cdc1a30d-e809-4c95-9b05-b21ed398987c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=391838624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.391838624
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2852641856
Short name T99
Test name
Test status
Simulation time 1526070000 ps
CPU time 4.75 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164868 kb
Host smart-42836ae1-00d6-49bf-82f8-d6b3f278902f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2852641856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2852641856
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2643744103
Short name T101
Test name
Test status
Simulation time 1382930000 ps
CPU time 6.28 seconds
Started May 30 01:50:39 PM PDT 24
Finished May 30 01:50:53 PM PDT 24
Peak memory 164844 kb
Host smart-b2c29f8e-d6b3-4467-882e-eaf208cddde6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2643744103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2643744103
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3723965311
Short name T103
Test name
Test status
Simulation time 1503530000 ps
CPU time 4.83 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:54 PM PDT 24
Peak memory 164900 kb
Host smart-96e95150-0574-41ca-aa66-85f5c8225167
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3723965311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3723965311
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.292846406
Short name T91
Test name
Test status
Simulation time 1360310000 ps
CPU time 4.16 seconds
Started May 30 01:50:44 PM PDT 24
Finished May 30 01:50:54 PM PDT 24
Peak memory 164836 kb
Host smart-06482bb7-d847-412b-86bb-9507385d9bd9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=292846406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.292846406
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.723990446
Short name T120
Test name
Test status
Simulation time 1505890000 ps
CPU time 4.86 seconds
Started May 30 01:50:41 PM PDT 24
Finished May 30 01:50:54 PM PDT 24
Peak memory 164892 kb
Host smart-e63bebfa-f9ab-4113-a051-911c1e95f961
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=723990446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.723990446
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.605129792
Short name T5
Test name
Test status
Simulation time 1579450000 ps
CPU time 4.81 seconds
Started May 30 01:50:44 PM PDT 24
Finished May 30 01:50:55 PM PDT 24
Peak memory 164836 kb
Host smart-646ec5e5-4f26-4c78-91f6-cd23778a9b14
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605129792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.605129792
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3209546050
Short name T116
Test name
Test status
Simulation time 1393970000 ps
CPU time 3.44 seconds
Started May 30 01:50:43 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164868 kb
Host smart-f102abea-bf70-4932-a449-9d37a80eae1b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3209546050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3209546050
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3936512509
Short name T118
Test name
Test status
Simulation time 1218170000 ps
CPU time 3.87 seconds
Started May 30 01:50:37 PM PDT 24
Finished May 30 01:50:46 PM PDT 24
Peak memory 164884 kb
Host smart-6fe0ea81-d3ba-4689-a9e9-ef660962b389
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3936512509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3936512509
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.197154448
Short name T28
Test name
Test status
Simulation time 1557730000 ps
CPU time 4.72 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164888 kb
Host smart-c2ab7323-f0e4-4da6-998b-231eeeeb9423
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=197154448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.197154448
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1725666021
Short name T29
Test name
Test status
Simulation time 1441090000 ps
CPU time 4.91 seconds
Started May 30 01:50:40 PM PDT 24
Finished May 30 01:50:51 PM PDT 24
Peak memory 164848 kb
Host smart-614a9b76-17ea-46da-945b-670fa699790d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1725666021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1725666021
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.703355279
Short name T88
Test name
Test status
Simulation time 1538330000 ps
CPU time 4.84 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 164848 kb
Host smart-a5861393-8b52-44e0-9d9c-aa7ddca1cf98
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=703355279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.703355279
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1643778373
Short name T106
Test name
Test status
Simulation time 1649450000 ps
CPU time 5.32 seconds
Started May 30 01:50:38 PM PDT 24
Finished May 30 01:50:52 PM PDT 24
Peak memory 164876 kb
Host smart-cab517be-9b26-427b-a244-8e3114524f57
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1643778373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1643778373
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3079867770
Short name T71
Test name
Test status
Simulation time 1491970000 ps
CPU time 5.4 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:43 PM PDT 24
Peak memory 164912 kb
Host smart-09130ee0-25ad-41f4-88b1-70e31a6f0278
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3079867770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3079867770
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4201641097
Short name T80
Test name
Test status
Simulation time 1264710000 ps
CPU time 4.01 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164896 kb
Host smart-d4047cdb-5db3-4eba-8923-9fe3fbfca758
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201641097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4201641097
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.484521823
Short name T51
Test name
Test status
Simulation time 1292250000 ps
CPU time 4.33 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164896 kb
Host smart-8d6e6a09-0240-4658-94a4-929b9c6aa0da
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484521823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.484521823
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.379661693
Short name T12
Test name
Test status
Simulation time 1452130000 ps
CPU time 4.56 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:05:42 PM PDT 24
Peak memory 164856 kb
Host smart-d8a080d3-3ee4-4086-b58e-31fdceac27fc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=379661693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.379661693
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.941721715
Short name T74
Test name
Test status
Simulation time 1331710000 ps
CPU time 4.46 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:43 PM PDT 24
Peak memory 164572 kb
Host smart-1a1468b9-6712-4da3-9247-3ec69462ba6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=941721715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.941721715
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1419795515
Short name T69
Test name
Test status
Simulation time 1302050000 ps
CPU time 4.34 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164868 kb
Host smart-f5f7a657-7885-41f8-9882-0d71fb20644c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1419795515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1419795515
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.149963466
Short name T50
Test name
Test status
Simulation time 1411310000 ps
CPU time 4.99 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164880 kb
Host smart-7a598578-b6e7-419b-8804-9d25090b1e85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=149963466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.149963466
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1124837573
Short name T70
Test name
Test status
Simulation time 1610390000 ps
CPU time 4.79 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164888 kb
Host smart-22c0cbfe-36f5-48b9-937e-366357b436e8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124837573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1124837573
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.33011917
Short name T59
Test name
Test status
Simulation time 1519550000 ps
CPU time 5.23 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:05:43 PM PDT 24
Peak memory 164892 kb
Host smart-ec189910-73b6-44ed-b741-39b7d8fa2647
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33011917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.33011917
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.500540973
Short name T1
Test name
Test status
Simulation time 1354950000 ps
CPU time 4.23 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164860 kb
Host smart-c09a34cf-60eb-4133-80d9-59b5d159911b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=500540973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.500540973
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3824453707
Short name T8
Test name
Test status
Simulation time 1556510000 ps
CPU time 5.13 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:43 PM PDT 24
Peak memory 164900 kb
Host smart-a6a3f6e4-eccf-43d2-8338-69d2870eb410
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3824453707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3824453707
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4158225178
Short name T48
Test name
Test status
Simulation time 1497250000 ps
CPU time 5.84 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:42 PM PDT 24
Peak memory 164904 kb
Host smart-6f02934e-5a12-47c8-b982-0ef7a981349b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4158225178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4158225178
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.262650156
Short name T42
Test name
Test status
Simulation time 1410650000 ps
CPU time 4.81 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:44 PM PDT 24
Peak memory 164832 kb
Host smart-4c8d6644-5ed8-4516-918e-3e7afc893fbd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=262650156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.262650156
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.530770041
Short name T64
Test name
Test status
Simulation time 1540410000 ps
CPU time 4.97 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:44 PM PDT 24
Peak memory 164832 kb
Host smart-6045adf6-f4df-4434-bdfd-3831c5c97262
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=530770041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.530770041
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2996453751
Short name T77
Test name
Test status
Simulation time 1151290000 ps
CPU time 3.9 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:42 PM PDT 24
Peak memory 164548 kb
Host smart-9d2d5043-a7ee-487d-86f0-3f11aef92b7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2996453751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2996453751
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1019894599
Short name T56
Test name
Test status
Simulation time 1472670000 ps
CPU time 5.02 seconds
Started May 30 02:05:33 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164824 kb
Host smart-81f21a14-0afb-4b9f-9382-680021b51274
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1019894599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1019894599
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3251833504
Short name T44
Test name
Test status
Simulation time 1529090000 ps
CPU time 5.04 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:45 PM PDT 24
Peak memory 164852 kb
Host smart-693db11d-8684-4f19-a3bb-6a7ba129e370
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3251833504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3251833504
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3027579824
Short name T57
Test name
Test status
Simulation time 1578830000 ps
CPU time 5.31 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164852 kb
Host smart-d056e4ec-aa43-443b-aee2-3414993bb2cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3027579824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3027579824
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4063457774
Short name T11
Test name
Test status
Simulation time 1423650000 ps
CPU time 4.04 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164900 kb
Host smart-3adf9875-eff2-4168-97a7-0ae3f881805c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4063457774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4063457774
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3876898066
Short name T55
Test name
Test status
Simulation time 1454470000 ps
CPU time 4.92 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:45 PM PDT 24
Peak memory 164852 kb
Host smart-37f2edfd-6d8e-4020-bb9b-f357414517c3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876898066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3876898066
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.899085042
Short name T62
Test name
Test status
Simulation time 1501170000 ps
CPU time 5.05 seconds
Started May 30 02:05:33 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164768 kb
Host smart-20fa573a-58e0-4764-af68-9ef3438a46c7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899085042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.899085042
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4092709528
Short name T58
Test name
Test status
Simulation time 1537970000 ps
CPU time 5.17 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164908 kb
Host smart-a6f5deb2-a27d-4f88-9f0f-36bff77c824f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092709528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.4092709528
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.816933367
Short name T41
Test name
Test status
Simulation time 1400350000 ps
CPU time 4.22 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164856 kb
Host smart-e83f8044-0da6-4d2c-988b-7454740f291b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=816933367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.816933367
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.893193569
Short name T45
Test name
Test status
Simulation time 1400470000 ps
CPU time 4.37 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:39 PM PDT 24
Peak memory 164896 kb
Host smart-44b67bff-7cd0-4650-a372-1eb2530455ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=893193569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.893193569
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.568516760
Short name T46
Test name
Test status
Simulation time 1343990000 ps
CPU time 4.78 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164900 kb
Host smart-dac440e6-fcdb-4c21-b00e-b9c675c2fe71
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=568516760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.568516760
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.792118366
Short name T3
Test name
Test status
Simulation time 1211030000 ps
CPU time 3.89 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:39 PM PDT 24
Peak memory 164896 kb
Host smart-bec5e7c1-3600-4c48-ad2b-cd54739f652f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=792118366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.792118366
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3996918878
Short name T47
Test name
Test status
Simulation time 1603570000 ps
CPU time 5.52 seconds
Started May 30 02:05:33 PM PDT 24
Finished May 30 02:05:47 PM PDT 24
Peak memory 164868 kb
Host smart-1edab42e-197a-496b-8b9e-4a8c38c2403c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996918878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3996918878
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3205706906
Short name T10
Test name
Test status
Simulation time 1571350000 ps
CPU time 5.21 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:05:44 PM PDT 24
Peak memory 164852 kb
Host smart-c8cf1b0e-19d3-410a-94bf-df27ea5f2b59
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205706906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3205706906
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.341000930
Short name T72
Test name
Test status
Simulation time 1349770000 ps
CPU time 4.94 seconds
Started May 30 02:05:34 PM PDT 24
Finished May 30 02:05:45 PM PDT 24
Peak memory 164860 kb
Host smart-894e8396-e3d5-4fb7-8127-b0a21dcd6c32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=341000930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.341000930
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2132649156
Short name T61
Test name
Test status
Simulation time 1382390000 ps
CPU time 4.67 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:44 PM PDT 24
Peak memory 164852 kb
Host smart-7dadb1c4-bb84-42cd-a6a1-b1caabd9490b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132649156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2132649156
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1961782582
Short name T73
Test name
Test status
Simulation time 1493270000 ps
CPU time 5.72 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164844 kb
Host smart-c266521c-3d20-4fa2-a441-9ae44326966e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961782582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1961782582
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1673705912
Short name T78
Test name
Test status
Simulation time 1541910000 ps
CPU time 6.06 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164844 kb
Host smart-701eccda-7852-41a9-bb1a-81526a0494e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1673705912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1673705912
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1184273363
Short name T52
Test name
Test status
Simulation time 1482270000 ps
CPU time 5.17 seconds
Started May 30 02:05:33 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164868 kb
Host smart-63213ce7-e297-4a94-babc-3aa06925c903
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1184273363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1184273363
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3957688266
Short name T75
Test name
Test status
Simulation time 1386050000 ps
CPU time 4.63 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164864 kb
Host smart-819661cb-0fd3-490d-8538-54373b66c3ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3957688266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3957688266
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2782048692
Short name T60
Test name
Test status
Simulation time 1428490000 ps
CPU time 4.01 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164912 kb
Host smart-484deb04-2d8a-4d9b-b36c-f7300fc985ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2782048692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2782048692
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1879417542
Short name T79
Test name
Test status
Simulation time 1599830000 ps
CPU time 6.14 seconds
Started May 30 02:05:31 PM PDT 24
Finished May 30 02:05:46 PM PDT 24
Peak memory 164844 kb
Host smart-3c185bea-7902-4816-a134-a0d832f94ee6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1879417542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1879417542
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.196623751
Short name T43
Test name
Test status
Simulation time 1517970000 ps
CPU time 4.38 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164904 kb
Host smart-e6f4f25b-296b-45c4-aa04-da5b27d5139d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196623751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.196623751
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2022577657
Short name T66
Test name
Test status
Simulation time 1539310000 ps
CPU time 5.69 seconds
Started May 30 02:05:33 PM PDT 24
Finished May 30 02:05:47 PM PDT 24
Peak memory 164848 kb
Host smart-4001f727-3e6d-4403-80a3-5be5a1d5d971
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022577657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2022577657
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1522238281
Short name T65
Test name
Test status
Simulation time 1194130000 ps
CPU time 3.65 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:39 PM PDT 24
Peak memory 164872 kb
Host smart-1c4b29e2-170d-4291-a7bb-a634eb4a6459
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522238281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1522238281
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3985240821
Short name T67
Test name
Test status
Simulation time 1473310000 ps
CPU time 4.31 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164872 kb
Host smart-e0ddb34d-995c-4c11-b043-d763b9e20aee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3985240821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3985240821
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1092025883
Short name T13
Test name
Test status
Simulation time 1445050000 ps
CPU time 4.74 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:40 PM PDT 24
Peak memory 164864 kb
Host smart-77658129-61e0-4b37-a302-2734e4e34ac6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092025883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1092025883
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1452489008
Short name T68
Test name
Test status
Simulation time 1506210000 ps
CPU time 5.93 seconds
Started May 30 02:05:27 PM PDT 24
Finished May 30 02:05:42 PM PDT 24
Peak memory 164904 kb
Host smart-4352ee22-606d-4249-9c64-2981cc5ee581
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452489008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1452489008
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2846536336
Short name T54
Test name
Test status
Simulation time 1429830000 ps
CPU time 5.51 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:05:43 PM PDT 24
Peak memory 164880 kb
Host smart-cbf8b828-dcc4-47cb-851d-072ef12c3f07
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2846536336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2846536336
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2125675656
Short name T63
Test name
Test status
Simulation time 1335110000 ps
CPU time 5.33 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164904 kb
Host smart-306a18b4-9534-440f-8e55-ddc8659036a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2125675656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2125675656
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.435784129
Short name T2
Test name
Test status
Simulation time 1445410000 ps
CPU time 4.7 seconds
Started May 30 02:05:30 PM PDT 24
Finished May 30 02:05:42 PM PDT 24
Peak memory 164888 kb
Host smart-8e439f38-c0dc-4dc1-9b80-52fc8c7d90fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=435784129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.435784129
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4220518077
Short name T53
Test name
Test status
Simulation time 1570830000 ps
CPU time 6.05 seconds
Started May 30 02:05:32 PM PDT 24
Finished May 30 02:05:47 PM PDT 24
Peak memory 164892 kb
Host smart-a60f5ced-f597-449b-8229-c907b245da1c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4220518077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.4220518077
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3241862679
Short name T49
Test name
Test status
Simulation time 1515670000 ps
CPU time 4.91 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164904 kb
Host smart-d022e635-9c74-4a6d-989c-d00529d8c4f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3241862679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3241862679
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.785002969
Short name T76
Test name
Test status
Simulation time 1366130000 ps
CPU time 4.41 seconds
Started May 30 02:05:29 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164888 kb
Host smart-ff0caa7d-9e2a-4d9b-938d-6f55af485cf7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=785002969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.785002969
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.464665929
Short name T9
Test name
Test status
Simulation time 1582470000 ps
CPU time 4.98 seconds
Started May 30 02:05:28 PM PDT 24
Finished May 30 02:05:41 PM PDT 24
Peak memory 164848 kb
Host smart-b51c228c-076a-47fc-b485-f4449bd3f9f8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=464665929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.464665929
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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