Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3008615639
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4207306827
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3407645590

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.444424947
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3419643484
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4143950627
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.221011110
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.986112752
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1465071186
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3485164152
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1292755608
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1915388357
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2870644451
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2750808747
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.677870715
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1944464135
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2091706512
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1513763390
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1801553606
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1816458249
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2338594287
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3877289633
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2621106832
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4136958170
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2605310639
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2568424768
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.146562169
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2606372157
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4078265818
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.357972811
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3695961627
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2155694989
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.45437112
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2524267264
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.794455780
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.922343196
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1990284446
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3979434067
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.622830307
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3678243349
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1215034743
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2155114290
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2456636131
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1507376417
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2017014946
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4077501344
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4206745573
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1160095381
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.349273700
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1133135121
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3328963684
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1742297952
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1667368349
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1929765510
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3736535761
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3822870607
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2933540249
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1026429953
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.813529164
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2081455412
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3392002230
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.238614090
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2751492779
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2920236154
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1056072618
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3340552406
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1372868129
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2096194894
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.207280864
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3285687127
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3085718967
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3166722894
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.395519167
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2545646600
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3349165412
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1829121408
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3723952556
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.55937072
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.87218231
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.181907407
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3916704714
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1800603052
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2128002370
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.563445049
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.168475875
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4071235488
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1173387515
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.655466454
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2962640618
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.280406620
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3555859245
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2501118258
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3604834605
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.253358977
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1366244274
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.427407676
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.602294438
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3809254662
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.506162321
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4057874688
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2405240816
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1450556016
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2024047019
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2619491494
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1418198853
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3831527331
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1376916479
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1159800717
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4024749810
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1177483157
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.959834485
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2648064754
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1405477139
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.781189241
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1495113915
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1795423242
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.913571670
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3351185983
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2407614298
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1781370275
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1984768101
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2808782909
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1637366435
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1495260921
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3898969107
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3262983573
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2468747523
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1806866193
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3800454825
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3262756233
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.768610963
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.669772144
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3792409745
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1008348767
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.475700815
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1538983546
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.676670225
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.388428567
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.793988267
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2242079640
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4095170169
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1737221018
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3075803842
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3295577525
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1151697616
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3986159427
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3872464908
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1947814418
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1468617710
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.143299891
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2293720076
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.818999841
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2035255057
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2532976387
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2036621064
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3105028823
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1250888259
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.71103546
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.665034912
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1817718551
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3637452108
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1505543433
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1878814452
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.202066960
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1826217560
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3331808985
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1756099738
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1571508903
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.720701001
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1851293572
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4152985533
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.124732911
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1650773931
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.249333594
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1397255742
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1008598676
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3386199991
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4024142159
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1334783542
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1230480730
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.620207885
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2564854257
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3940137146
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.57627984
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2997974669
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3946736533
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3663928931
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2422036393
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1785339947
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3297509858
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2916518825
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4040271988
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2552161442
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.943636942
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1067590049
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4047903892
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1300052023
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2754627931
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3405411126
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3977730051



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1650773931 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1576010000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1397255742 Jun 02 01:45:48 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1466950000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1008598676 Jun 02 01:45:48 PM PDT 24 Jun 02 01:45:55 PM PDT 24 1227970000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.818999841 Jun 02 01:45:46 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1416370000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2552161442 Jun 02 01:45:49 PM PDT 24 Jun 02 01:46:01 PM PDT 24 1535250000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2916518825 Jun 02 01:45:50 PM PDT 24 Jun 02 01:46:01 PM PDT 24 1488350000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.943636942 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1391430000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2997974669 Jun 02 01:45:45 PM PDT 24 Jun 02 01:45:57 PM PDT 24 1439470000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3008615639 Jun 02 01:45:42 PM PDT 24 Jun 02 01:45:52 PM PDT 24 1361050000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2422036393 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1494210000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1756099738 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:57 PM PDT 24 1268730000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3331808985 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1551170000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4040271988 Jun 02 01:45:50 PM PDT 24 Jun 02 01:46:00 PM PDT 24 1564910000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2754627931 Jun 02 01:45:44 PM PDT 24 Jun 02 01:45:53 PM PDT 24 1298310000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1851293572 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:57 PM PDT 24 1318850000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1250888259 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:54 PM PDT 24 1142110000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.249333594 Jun 02 01:45:43 PM PDT 24 Jun 02 01:45:51 PM PDT 24 1493970000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1817718551 Jun 02 01:45:44 PM PDT 24 Jun 02 01:45:55 PM PDT 24 1383310000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1505543433 Jun 02 01:45:49 PM PDT 24 Jun 02 01:46:02 PM PDT 24 1480290000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3405411126 Jun 02 01:45:44 PM PDT 24 Jun 02 01:45:53 PM PDT 24 1589070000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.57627984 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1205150000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1826217560 Jun 02 01:45:46 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1601830000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1300052023 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1466770000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1230480730 Jun 02 01:45:48 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1511290000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3946736533 Jun 02 01:45:51 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1212950000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3977730051 Jun 02 01:45:42 PM PDT 24 Jun 02 01:45:49 PM PDT 24 1356550000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2532976387 Jun 02 01:45:42 PM PDT 24 Jun 02 01:45:54 PM PDT 24 1382870000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.620207885 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1454690000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3637452108 Jun 02 01:45:44 PM PDT 24 Jun 02 01:45:54 PM PDT 24 1467010000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.202066960 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1503950000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.71103546 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1346010000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3940137146 Jun 02 01:45:48 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1510990000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1878814452 Jun 02 01:45:42 PM PDT 24 Jun 02 01:45:53 PM PDT 24 1460050000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.665034912 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:55 PM PDT 24 1310650000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1334783542 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:57 PM PDT 24 1482070000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3105028823 Jun 02 01:45:48 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1442730000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2036621064 Jun 02 01:45:42 PM PDT 24 Jun 02 01:45:51 PM PDT 24 1624550000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4047903892 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1515950000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2564854257 Jun 02 01:45:50 PM PDT 24 Jun 02 01:46:03 PM PDT 24 1589190000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4024142159 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1437830000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.720701001 Jun 02 01:45:50 PM PDT 24 Jun 02 01:46:00 PM PDT 24 1553950000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1067590049 Jun 02 01:45:46 PM PDT 24 Jun 02 01:45:56 PM PDT 24 1547670000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1785339947 Jun 02 01:45:49 PM PDT 24 Jun 02 01:46:02 PM PDT 24 1523210000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1571508903 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:58 PM PDT 24 1494050000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3386199991 Jun 02 01:45:48 PM PDT 24 Jun 02 01:46:00 PM PDT 24 1516370000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.124732911 Jun 02 01:45:51 PM PDT 24 Jun 02 01:46:01 PM PDT 24 1515430000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2035255057 Jun 02 01:45:45 PM PDT 24 Jun 02 01:45:55 PM PDT 24 1254970000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3663928931 Jun 02 01:45:47 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1514970000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4152985533 Jun 02 01:45:48 PM PDT 24 Jun 02 01:45:59 PM PDT 24 1379430000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3297509858 Jun 02 01:45:49 PM PDT 24 Jun 02 01:45:57 PM PDT 24 1307830000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1513763390 Jun 02 02:00:57 PM PDT 24 Jun 02 02:41:22 PM PDT 24 336647610000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1465071186 Jun 02 02:00:46 PM PDT 24 Jun 02 02:29:47 PM PDT 24 336488290000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4078265818 Jun 02 02:00:53 PM PDT 24 Jun 02 02:37:23 PM PDT 24 336429290000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2621106832 Jun 02 02:00:50 PM PDT 24 Jun 02 02:33:48 PM PDT 24 336643930000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1292755608 Jun 02 02:00:50 PM PDT 24 Jun 02 02:41:11 PM PDT 24 336736150000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2750808747 Jun 02 02:00:50 PM PDT 24 Jun 02 02:35:06 PM PDT 24 336933270000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.349273700 Jun 02 02:00:45 PM PDT 24 Jun 02 02:36:35 PM PDT 24 337044930000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1944464135 Jun 02 02:00:57 PM PDT 24 Jun 02 02:41:16 PM PDT 24 336658990000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4207306827 Jun 02 02:00:46 PM PDT 24 Jun 02 02:37:51 PM PDT 24 336911150000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.677870715 Jun 02 02:00:40 PM PDT 24 Jun 02 02:37:06 PM PDT 24 337059030000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.357972811 Jun 02 02:00:53 PM PDT 24 Jun 02 02:33:03 PM PDT 24 336993790000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3877289633 Jun 02 02:00:57 PM PDT 24 Jun 02 02:41:01 PM PDT 24 336633410000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1915388357 Jun 02 02:00:45 PM PDT 24 Jun 02 02:40:55 PM PDT 24 336577190000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2017014946 Jun 02 02:00:51 PM PDT 24 Jun 02 02:35:22 PM PDT 24 337045290000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.444424947 Jun 02 02:00:39 PM PDT 24 Jun 02 02:36:17 PM PDT 24 336342670000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.986112752 Jun 02 02:00:46 PM PDT 24 Jun 02 02:36:08 PM PDT 24 337031030000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2155114290 Jun 02 02:00:51 PM PDT 24 Jun 02 02:38:09 PM PDT 24 336345710000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1742297952 Jun 02 02:00:45 PM PDT 24 Jun 02 02:35:13 PM PDT 24 336336210000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1801553606 Jun 02 02:00:52 PM PDT 24 Jun 02 02:35:00 PM PDT 24 336851190000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3695961627 Jun 02 02:00:52 PM PDT 24 Jun 02 02:34:24 PM PDT 24 336696290000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.45437112 Jun 02 02:00:57 PM PDT 24 Jun 02 02:41:32 PM PDT 24 337034990000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.922343196 Jun 02 02:00:51 PM PDT 24 Jun 02 02:34:37 PM PDT 24 336992370000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3678243349 Jun 02 02:00:51 PM PDT 24 Jun 02 02:36:24 PM PDT 24 336771610000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4077501344 Jun 02 02:00:52 PM PDT 24 Jun 02 02:32:25 PM PDT 24 336613790000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1990284446 Jun 02 02:00:45 PM PDT 24 Jun 02 02:37:26 PM PDT 24 336932070000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.622830307 Jun 02 02:00:53 PM PDT 24 Jun 02 02:37:26 PM PDT 24 336876490000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1133135121 Jun 02 02:00:46 PM PDT 24 Jun 02 02:31:18 PM PDT 24 336862390000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1507376417 Jun 02 02:00:52 PM PDT 24 Jun 02 02:36:25 PM PDT 24 336560430000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3419643484 Jun 02 02:00:40 PM PDT 24 Jun 02 02:35:01 PM PDT 24 337056670000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4143950627 Jun 02 02:00:45 PM PDT 24 Jun 02 02:34:05 PM PDT 24 336829110000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3328963684 Jun 02 02:00:44 PM PDT 24 Jun 02 02:32:03 PM PDT 24 336766630000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2524267264 Jun 02 02:00:52 PM PDT 24 Jun 02 02:41:19 PM PDT 24 337054670000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4136958170 Jun 02 02:00:50 PM PDT 24 Jun 02 02:41:10 PM PDT 24 336598970000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2606372157 Jun 02 02:00:57 PM PDT 24 Jun 02 02:41:27 PM PDT 24 336407090000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1215034743 Jun 02 02:00:51 PM PDT 24 Jun 02 02:34:09 PM PDT 24 336960630000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2456636131 Jun 02 02:00:52 PM PDT 24 Jun 02 02:36:36 PM PDT 24 336689890000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2568424768 Jun 02 02:00:51 PM PDT 24 Jun 02 02:41:02 PM PDT 24 336985110000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1160095381 Jun 02 02:00:49 PM PDT 24 Jun 02 02:41:16 PM PDT 24 336772630000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1816458249 Jun 02 02:00:50 PM PDT 24 Jun 02 02:31:27 PM PDT 24 336664190000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3979434067 Jun 02 02:00:52 PM PDT 24 Jun 02 02:36:09 PM PDT 24 337073090000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.146562169 Jun 02 02:00:51 PM PDT 24 Jun 02 02:34:36 PM PDT 24 336753550000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2155694989 Jun 02 02:00:53 PM PDT 24 Jun 02 02:34:16 PM PDT 24 336598410000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3485164152 Jun 02 02:00:45 PM PDT 24 Jun 02 02:40:21 PM PDT 24 337067330000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2338594287 Jun 02 02:00:52 PM PDT 24 Jun 02 02:34:13 PM PDT 24 336856110000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4206745573 Jun 02 02:00:50 PM PDT 24 Jun 02 02:26:41 PM PDT 24 336948570000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2605310639 Jun 02 02:00:51 PM PDT 24 Jun 02 02:35:44 PM PDT 24 336765270000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.794455780 Jun 02 02:00:52 PM PDT 24 Jun 02 02:36:43 PM PDT 24 336348890000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2091706512 Jun 02 02:00:50 PM PDT 24 Jun 02 02:35:24 PM PDT 24 336551190000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2870644451 Jun 02 02:00:56 PM PDT 24 Jun 02 02:41:14 PM PDT 24 336862050000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.221011110 Jun 02 02:00:50 PM PDT 24 Jun 02 02:41:07 PM PDT 24 336915710000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3872464908 Jun 02 02:08:45 PM PDT 24 Jun 02 02:08:54 PM PDT 24 1427410000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1795423242 Jun 02 02:08:55 PM PDT 24 Jun 02 02:09:07 PM PDT 24 1367670000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2242079640 Jun 02 02:09:06 PM PDT 24 Jun 02 02:09:18 PM PDT 24 1455670000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1947814418 Jun 02 02:08:45 PM PDT 24 Jun 02 02:08:55 PM PDT 24 1323830000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1984768101 Jun 02 02:08:59 PM PDT 24 Jun 02 02:09:11 PM PDT 24 1476210000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.676670225 Jun 02 02:09:04 PM PDT 24 Jun 02 02:09:16 PM PDT 24 1446310000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2808782909 Jun 02 02:09:00 PM PDT 24 Jun 02 02:09:13 PM PDT 24 1530290000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3831527331 Jun 02 02:08:51 PM PDT 24 Jun 02 02:09:02 PM PDT 24 1202010000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2407614298 Jun 02 02:08:57 PM PDT 24 Jun 02 02:09:10 PM PDT 24 1476410000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1405477139 Jun 02 02:08:54 PM PDT 24 Jun 02 02:09:07 PM PDT 24 1497870000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.475700815 Jun 02 02:09:05 PM PDT 24 Jun 02 02:09:16 PM PDT 24 1194290000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1781370275 Jun 02 02:09:01 PM PDT 24 Jun 02 02:09:10 PM PDT 24 1257730000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.388428567 Jun 02 02:09:04 PM PDT 24 Jun 02 02:09:19 PM PDT 24 1513770000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2619491494 Jun 02 02:08:48 PM PDT 24 Jun 02 02:08:56 PM PDT 24 1361210000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1637366435 Jun 02 02:08:58 PM PDT 24 Jun 02 02:09:13 PM PDT 24 1511910000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1495113915 Jun 02 02:08:54 PM PDT 24 Jun 02 02:09:06 PM PDT 24 1399230000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.143299891 Jun 02 02:08:49 PM PDT 24 Jun 02 02:08:58 PM PDT 24 1363070000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1450556016 Jun 02 02:08:44 PM PDT 24 Jun 02 02:08:54 PM PDT 24 1508550000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2293720076 Jun 02 02:08:50 PM PDT 24 Jun 02 02:09:03 PM PDT 24 1403950000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1418198853 Jun 02 02:08:49 PM PDT 24 Jun 02 02:09:01 PM PDT 24 1389510000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2468747523 Jun 02 02:08:59 PM PDT 24 Jun 02 02:09:08 PM PDT 24 1606490000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1008348767 Jun 02 02:09:05 PM PDT 24 Jun 02 02:09:15 PM PDT 24 1537970000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1151697616 Jun 02 02:09:14 PM PDT 24 Jun 02 02:09:25 PM PDT 24 1416330000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1806866193 Jun 02 02:09:01 PM PDT 24 Jun 02 02:09:12 PM PDT 24 1577570000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4024749810 Jun 02 02:08:50 PM PDT 24 Jun 02 02:09:04 PM PDT 24 1530030000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3792409745 Jun 02 02:09:05 PM PDT 24 Jun 02 02:09:19 PM PDT 24 1534270000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1177483157 Jun 02 02:08:54 PM PDT 24 Jun 02 02:09:07 PM PDT 24 1532350000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2024047019 Jun 02 02:08:48 PM PDT 24 Jun 02 02:09:00 PM PDT 24 1507290000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3295577525 Jun 02 02:09:14 PM PDT 24 Jun 02 02:09:26 PM PDT 24 1544590000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.768610963 Jun 02 02:08:59 PM PDT 24 Jun 02 02:09:11 PM PDT 24 1549770000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4095170169 Jun 02 02:09:09 PM PDT 24 Jun 02 02:09:21 PM PDT 24 1434550000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3262983573 Jun 02 02:09:02 PM PDT 24 Jun 02 02:09:12 PM PDT 24 1380410000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2648064754 Jun 02 02:08:54 PM PDT 24 Jun 02 02:09:05 PM PDT 24 1315550000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1737221018 Jun 02 02:09:16 PM PDT 24 Jun 02 02:09:31 PM PDT 24 1540390000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3075803842 Jun 02 02:09:16 PM PDT 24 Jun 02 02:09:30 PM PDT 24 1471790000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3800454825 Jun 02 02:08:59 PM PDT 24 Jun 02 02:09:08 PM PDT 24 1589550000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.913571670 Jun 02 02:08:53 PM PDT 24 Jun 02 02:09:03 PM PDT 24 1203050000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1159800717 Jun 02 02:08:48 PM PDT 24 Jun 02 02:08:58 PM PDT 24 1448170000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.793988267 Jun 02 02:09:04 PM PDT 24 Jun 02 02:09:17 PM PDT 24 1367870000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1468617710 Jun 02 02:08:49 PM PDT 24 Jun 02 02:09:01 PM PDT 24 1529850000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.781189241 Jun 02 02:08:45 PM PDT 24 Jun 02 02:08:57 PM PDT 24 1575310000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1538983546 Jun 02 02:08:44 PM PDT 24 Jun 02 02:08:56 PM PDT 24 1515970000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.959834485 Jun 02 02:08:55 PM PDT 24 Jun 02 02:09:10 PM PDT 24 1626190000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3351185983 Jun 02 02:08:55 PM PDT 24 Jun 02 02:09:09 PM PDT 24 1601250000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3898969107 Jun 02 02:08:46 PM PDT 24 Jun 02 02:08:54 PM PDT 24 1326290000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.669772144 Jun 02 02:09:05 PM PDT 24 Jun 02 02:09:14 PM PDT 24 1493450000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1376916479 Jun 02 02:08:48 PM PDT 24 Jun 02 02:08:56 PM PDT 24 1361010000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3986159427 Jun 02 02:09:13 PM PDT 24 Jun 02 02:09:25 PM PDT 24 1346190000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3262756233 Jun 02 02:09:03 PM PDT 24 Jun 02 02:09:13 PM PDT 24 1443290000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1495260921 Jun 02 02:09:00 PM PDT 24 Jun 02 02:09:12 PM PDT 24 1415690000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3085718967 Jun 02 02:09:30 PM PDT 24 Jun 02 02:43:03 PM PDT 24 336801110000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.55937072 Jun 02 02:09:29 PM PDT 24 Jun 02 02:43:24 PM PDT 24 336571770000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1829121408 Jun 02 02:09:32 PM PDT 24 Jun 02 02:41:45 PM PDT 24 336422170000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3407645590 Jun 02 02:09:20 PM PDT 24 Jun 02 02:42:39 PM PDT 24 336523010000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1056072618 Jun 02 02:09:25 PM PDT 24 Jun 02 02:41:40 PM PDT 24 336590750000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2920236154 Jun 02 02:09:17 PM PDT 24 Jun 02 02:46:49 PM PDT 24 336709190000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.395519167 Jun 02 02:09:30 PM PDT 24 Jun 02 02:44:18 PM PDT 24 336834250000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3916704714 Jun 02 02:09:31 PM PDT 24 Jun 02 02:37:27 PM PDT 24 336959990000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.207280864 Jun 02 02:09:30 PM PDT 24 Jun 02 02:40:45 PM PDT 24 336601350000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2096194894 Jun 02 02:09:29 PM PDT 24 Jun 02 02:42:29 PM PDT 24 337127170000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2933540249 Jun 02 02:09:19 PM PDT 24 Jun 02 02:40:38 PM PDT 24 337069970000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1366244274 Jun 02 02:09:35 PM PDT 24 Jun 02 02:43:11 PM PDT 24 336987270000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3736535761 Jun 02 02:09:19 PM PDT 24 Jun 02 02:42:32 PM PDT 24 337088410000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.168475875 Jun 02 02:09:34 PM PDT 24 Jun 02 02:40:48 PM PDT 24 336475430000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3555859245 Jun 02 02:09:36 PM PDT 24 Jun 02 02:41:34 PM PDT 24 336567050000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1667368349 Jun 02 02:09:16 PM PDT 24 Jun 02 02:42:18 PM PDT 24 337016970000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4071235488 Jun 02 02:09:15 PM PDT 24 Jun 02 02:44:18 PM PDT 24 336606010000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3285687127 Jun 02 02:09:30 PM PDT 24 Jun 02 02:41:42 PM PDT 24 336597790000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.427407676 Jun 02 02:09:35 PM PDT 24 Jun 02 02:44:36 PM PDT 24 336434790000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3349165412 Jun 02 02:09:17 PM PDT 24 Jun 02 02:46:30 PM PDT 24 336884470000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.253358977 Jun 02 02:09:33 PM PDT 24 Jun 02 02:42:21 PM PDT 24 336494090000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1800603052 Jun 02 02:09:35 PM PDT 24 Jun 02 02:41:47 PM PDT 24 336698310000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1929765510 Jun 02 02:09:17 PM PDT 24 Jun 02 02:42:13 PM PDT 24 336523370000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.280406620 Jun 02 02:09:37 PM PDT 24 Jun 02 02:43:45 PM PDT 24 336417850000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.238614090 Jun 02 02:09:26 PM PDT 24 Jun 02 02:42:01 PM PDT 24 336665610000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2545646600 Jun 02 02:09:29 PM PDT 24 Jun 02 02:42:22 PM PDT 24 336969010000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2405240816 Jun 02 02:09:22 PM PDT 24 Jun 02 02:43:12 PM PDT 24 336549550000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2081455412 Jun 02 02:09:27 PM PDT 24 Jun 02 02:43:26 PM PDT 24 336701110000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3822870607 Jun 02 02:09:20 PM PDT 24 Jun 02 02:40:32 PM PDT 24 336485350000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.655466454 Jun 02 02:09:34 PM PDT 24 Jun 02 02:39:21 PM PDT 24 336821930000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.506162321 Jun 02 02:09:19 PM PDT 24 Jun 02 02:40:05 PM PDT 24 336469150000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.563445049 Jun 02 02:09:34 PM PDT 24 Jun 02 02:41:20 PM PDT 24 336915650000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2501118258 Jun 02 02:09:36 PM PDT 24 Jun 02 02:41:08 PM PDT 24 336760090000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3809254662 Jun 02 02:09:20 PM PDT 24 Jun 02 02:38:27 PM PDT 24 337054150000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3166722894 Jun 02 02:09:31 PM PDT 24 Jun 02 02:44:54 PM PDT 24 336449690000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3392002230 Jun 02 02:09:26 PM PDT 24 Jun 02 02:48:24 PM PDT 24 336985630000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4057874688 Jun 02 02:09:20 PM PDT 24 Jun 02 02:44:57 PM PDT 24 336467790000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.181907407 Jun 02 02:09:31 PM PDT 24 Jun 02 02:43:24 PM PDT 24 336624010000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3340552406 Jun 02 02:09:25 PM PDT 24 Jun 02 02:42:36 PM PDT 24 336637350000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3604834605 Jun 02 02:09:34 PM PDT 24 Jun 02 02:42:26 PM PDT 24 336823990000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1173387515 Jun 02 02:09:36 PM PDT 24 Jun 02 02:43:42 PM PDT 24 336879910000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1372868129 Jun 02 02:09:27 PM PDT 24 Jun 02 02:44:44 PM PDT 24 336478570000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.813529164 Jun 02 02:09:28 PM PDT 24 Jun 02 02:44:39 PM PDT 24 336585590000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2751492779 Jun 02 02:09:26 PM PDT 24 Jun 02 02:43:32 PM PDT 24 337061330000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2962640618 Jun 02 02:09:34 PM PDT 24 Jun 02 02:42:08 PM PDT 24 336767190000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2128002370 Jun 02 02:09:36 PM PDT 24 Jun 02 02:43:42 PM PDT 24 336358570000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3723952556 Jun 02 02:09:31 PM PDT 24 Jun 02 02:44:35 PM PDT 24 336440290000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1026429953 Jun 02 02:09:26 PM PDT 24 Jun 02 02:44:05 PM PDT 24 336963670000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.87218231 Jun 02 02:09:31 PM PDT 24 Jun 02 02:44:17 PM PDT 24 336962850000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.602294438 Jun 02 02:09:20 PM PDT 24 Jun 02 02:41:11 PM PDT 24 336882350000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3008615639
Short name T12
Test name
Test status
Simulation time 1361050000 ps
CPU time 4.38 seconds
Started Jun 02 01:45:42 PM PDT 24
Finished Jun 02 01:45:52 PM PDT 24
Peak memory 164876 kb
Host smart-b8c2e1bf-e090-432b-ad1e-c221f8006489
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008615639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3008615639
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4207306827
Short name T19
Test name
Test status
Simulation time 336911150000 ps
CPU time 907.01 seconds
Started Jun 02 02:00:46 PM PDT 24
Finished Jun 02 02:37:51 PM PDT 24
Peak memory 160772 kb
Host smart-8957a8b1-f408-4bb4-97d6-ae2b2e1c540d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4207306827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4207306827
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3407645590
Short name T24
Test name
Test status
Simulation time 336523010000 ps
CPU time 814.66 seconds
Started Jun 02 02:09:20 PM PDT 24
Finished Jun 02 02:42:39 PM PDT 24
Peak memory 160780 kb
Host smart-ba8a5253-6b6d-4a20-a118-c2607c8dc729
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3407645590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3407645590
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.444424947
Short name T75
Test name
Test status
Simulation time 336342670000 ps
CPU time 867.8 seconds
Started Jun 02 02:00:39 PM PDT 24
Finished Jun 02 02:36:17 PM PDT 24
Peak memory 160780 kb
Host smart-c5ef094e-440f-466b-bd60-1f559baa4244
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=444424947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.444424947
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3419643484
Short name T89
Test name
Test status
Simulation time 337056670000 ps
CPU time 847.14 seconds
Started Jun 02 02:00:40 PM PDT 24
Finished Jun 02 02:35:01 PM PDT 24
Peak memory 160788 kb
Host smart-3358742e-5d6c-4808-8951-7cd6cec3b459
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3419643484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3419643484
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.4143950627
Short name T90
Test name
Test status
Simulation time 336829110000 ps
CPU time 829.29 seconds
Started Jun 02 02:00:45 PM PDT 24
Finished Jun 02 02:34:05 PM PDT 24
Peak memory 160812 kb
Host smart-66f55ba6-0b1d-4f80-be3e-82498707ef88
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143950627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.4143950627
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.221011110
Short name T110
Test name
Test status
Simulation time 336915710000 ps
CPU time 943.38 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:41:07 PM PDT 24
Peak memory 160748 kb
Host smart-d70e11f6-2e53-4201-a410-8bf2dd39c582
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=221011110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.221011110
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.986112752
Short name T76
Test name
Test status
Simulation time 337031030000 ps
CPU time 845.47 seconds
Started Jun 02 02:00:46 PM PDT 24
Finished Jun 02 02:36:08 PM PDT 24
Peak memory 160768 kb
Host smart-365836bf-bdbe-452c-83b6-086436432677
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=986112752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.986112752
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1465071186
Short name T5
Test name
Test status
Simulation time 336488290000 ps
CPU time 703.14 seconds
Started Jun 02 02:00:46 PM PDT 24
Finished Jun 02 02:29:47 PM PDT 24
Peak memory 160752 kb
Host smart-f4a519aa-1a23-498a-8ced-baeff4dda95b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1465071186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1465071186
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3485164152
Short name T103
Test name
Test status
Simulation time 337067330000 ps
CPU time 978.41 seconds
Started Jun 02 02:00:45 PM PDT 24
Finished Jun 02 02:40:21 PM PDT 24
Peak memory 160784 kb
Host smart-347b234d-84e5-43c0-be67-f24b4e0e8fb8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3485164152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3485164152
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1292755608
Short name T15
Test name
Test status
Simulation time 336736150000 ps
CPU time 967.09 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:41:11 PM PDT 24
Peak memory 160752 kb
Host smart-920723e9-bb85-4fda-9029-c06d417c3a9c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1292755608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1292755608
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1915388357
Short name T73
Test name
Test status
Simulation time 336577190000 ps
CPU time 979.57 seconds
Started Jun 02 02:00:45 PM PDT 24
Finished Jun 02 02:40:55 PM PDT 24
Peak memory 160796 kb
Host smart-2427db25-9a39-4aea-89bc-5b4d2fd0ec4f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1915388357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1915388357
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2870644451
Short name T109
Test name
Test status
Simulation time 336862050000 ps
CPU time 965.17 seconds
Started Jun 02 02:00:56 PM PDT 24
Finished Jun 02 02:41:14 PM PDT 24
Peak memory 160752 kb
Host smart-8762ff13-6d50-4b02-8e18-2c6429b8ae0c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2870644451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2870644451
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2750808747
Short name T16
Test name
Test status
Simulation time 336933270000 ps
CPU time 856.45 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:35:06 PM PDT 24
Peak memory 160784 kb
Host smart-adb0390e-b644-4e60-b9f6-88523622bd55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2750808747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2750808747
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.677870715
Short name T20
Test name
Test status
Simulation time 337059030000 ps
CPU time 878.35 seconds
Started Jun 02 02:00:40 PM PDT 24
Finished Jun 02 02:37:06 PM PDT 24
Peak memory 160764 kb
Host smart-78bc7ea9-9fef-465a-9315-10961a859f10
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=677870715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.677870715
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1944464135
Short name T18
Test name
Test status
Simulation time 336658990000 ps
CPU time 964.22 seconds
Started Jun 02 02:00:57 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 160752 kb
Host smart-c54cca9e-5d2f-4335-bca0-b806dd27eb2f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1944464135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1944464135
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2091706512
Short name T108
Test name
Test status
Simulation time 336551190000 ps
CPU time 854.14 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:35:24 PM PDT 24
Peak memory 160768 kb
Host smart-c1c25279-af5c-4b78-af20-dacd8d698bc9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2091706512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2091706512
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1513763390
Short name T4
Test name
Test status
Simulation time 336647610000 ps
CPU time 968.81 seconds
Started Jun 02 02:00:57 PM PDT 24
Finished Jun 02 02:41:22 PM PDT 24
Peak memory 160752 kb
Host smart-643c8b11-ccdf-455f-8e73-bf46472d4a51
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1513763390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1513763390
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1801553606
Short name T79
Test name
Test status
Simulation time 336851190000 ps
CPU time 834.82 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:35:00 PM PDT 24
Peak memory 160800 kb
Host smart-7f266148-a1c4-40ef-920b-006c0647cb08
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1801553606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1801553606
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1816458249
Short name T99
Test name
Test status
Simulation time 336664190000 ps
CPU time 752.13 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:31:27 PM PDT 24
Peak memory 160784 kb
Host smart-9b24e3df-1b0c-40ea-b0b4-b836d693f4ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1816458249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1816458249
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2338594287
Short name T104
Test name
Test status
Simulation time 336856110000 ps
CPU time 817.93 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:34:13 PM PDT 24
Peak memory 160788 kb
Host smart-dfd83915-e48c-4d0a-bafa-253c5cbd982d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2338594287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2338594287
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3877289633
Short name T72
Test name
Test status
Simulation time 336633410000 ps
CPU time 970.49 seconds
Started Jun 02 02:00:57 PM PDT 24
Finished Jun 02 02:41:01 PM PDT 24
Peak memory 160752 kb
Host smart-1417c7a8-a699-42e7-91f4-8a320eface0b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3877289633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3877289633
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2621106832
Short name T14
Test name
Test status
Simulation time 336643930000 ps
CPU time 813.72 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:33:48 PM PDT 24
Peak memory 160744 kb
Host smart-f235ccb1-fd30-4205-80f5-f44fec5c91e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2621106832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2621106832
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.4136958170
Short name T93
Test name
Test status
Simulation time 336598970000 ps
CPU time 980.22 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:41:10 PM PDT 24
Peak memory 160796 kb
Host smart-d7b5fefa-1f0d-4413-88d9-30ac38fc5e2e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4136958170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.4136958170
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2605310639
Short name T106
Test name
Test status
Simulation time 336765270000 ps
CPU time 859.95 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:35:44 PM PDT 24
Peak memory 160804 kb
Host smart-11251e37-c0cf-43a3-b2e7-15dd2ec7ce07
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2605310639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2605310639
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2568424768
Short name T97
Test name
Test status
Simulation time 336985110000 ps
CPU time 940.38 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:41:02 PM PDT 24
Peak memory 160744 kb
Host smart-10ad9808-6b96-43d3-b528-11e5f47af58b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2568424768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2568424768
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.146562169
Short name T101
Test name
Test status
Simulation time 336753550000 ps
CPU time 825.37 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:34:36 PM PDT 24
Peak memory 160776 kb
Host smart-c38f6245-7f41-49ff-90fc-736dfa672795
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=146562169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.146562169
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2606372157
Short name T94
Test name
Test status
Simulation time 336407090000 ps
CPU time 962.63 seconds
Started Jun 02 02:00:57 PM PDT 24
Finished Jun 02 02:41:27 PM PDT 24
Peak memory 160752 kb
Host smart-55029597-1190-40cd-b23f-e1af148ecc51
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2606372157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2606372157
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4078265818
Short name T6
Test name
Test status
Simulation time 336429290000 ps
CPU time 871.54 seconds
Started Jun 02 02:00:53 PM PDT 24
Finished Jun 02 02:37:23 PM PDT 24
Peak memory 160792 kb
Host smart-5ee1d107-29f8-4491-86de-e199460685c0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4078265818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4078265818
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.357972811
Short name T71
Test name
Test status
Simulation time 336993790000 ps
CPU time 783.85 seconds
Started Jun 02 02:00:53 PM PDT 24
Finished Jun 02 02:33:03 PM PDT 24
Peak memory 160748 kb
Host smart-97819a2f-db90-4cc5-82ce-a9fd7f81009b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=357972811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.357972811
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3695961627
Short name T80
Test name
Test status
Simulation time 336696290000 ps
CPU time 815.86 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:34:24 PM PDT 24
Peak memory 160796 kb
Host smart-e0e947d0-f2cf-4934-aae3-47be6bc00f47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3695961627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3695961627
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2155694989
Short name T102
Test name
Test status
Simulation time 336598410000 ps
CPU time 807.66 seconds
Started Jun 02 02:00:53 PM PDT 24
Finished Jun 02 02:34:16 PM PDT 24
Peak memory 160796 kb
Host smart-c96c6d7d-516e-4d82-896a-7123f497b189
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2155694989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2155694989
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.45437112
Short name T81
Test name
Test status
Simulation time 337034990000 ps
CPU time 966.06 seconds
Started Jun 02 02:00:57 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 160728 kb
Host smart-9929ffce-eb09-4031-89d9-fa2de6b16fb0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=45437112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.45437112
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2524267264
Short name T92
Test name
Test status
Simulation time 337054670000 ps
CPU time 955.68 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:41:19 PM PDT 24
Peak memory 160752 kb
Host smart-da8c3547-3b36-41d7-862b-7e60a85b57ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2524267264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2524267264
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.794455780
Short name T107
Test name
Test status
Simulation time 336348890000 ps
CPU time 859.6 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:36:43 PM PDT 24
Peak memory 160724 kb
Host smart-e15616dc-c339-4712-b80e-67b6c12f4bfc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=794455780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.794455780
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.922343196
Short name T82
Test name
Test status
Simulation time 336992370000 ps
CPU time 834.96 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:34:37 PM PDT 24
Peak memory 160876 kb
Host smart-b244ff8f-3353-4f22-9ed1-88aa590bdb7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=922343196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.922343196
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1990284446
Short name T85
Test name
Test status
Simulation time 336932070000 ps
CPU time 904.31 seconds
Started Jun 02 02:00:45 PM PDT 24
Finished Jun 02 02:37:26 PM PDT 24
Peak memory 160808 kb
Host smart-eaa1d3cc-534c-48db-be8a-33bfc23fb83f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1990284446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1990284446
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3979434067
Short name T100
Test name
Test status
Simulation time 337073090000 ps
CPU time 859.87 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:36:09 PM PDT 24
Peak memory 160804 kb
Host smart-16cd8477-ab48-43aa-b340-631ab51b00de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3979434067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3979434067
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.622830307
Short name T86
Test name
Test status
Simulation time 336876490000 ps
CPU time 887.76 seconds
Started Jun 02 02:00:53 PM PDT 24
Finished Jun 02 02:37:26 PM PDT 24
Peak memory 160788 kb
Host smart-98eb5a20-b21c-4aa0-8679-fec10bfc8ce2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622830307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.622830307
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3678243349
Short name T83
Test name
Test status
Simulation time 336771610000 ps
CPU time 879.26 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:36:24 PM PDT 24
Peak memory 160932 kb
Host smart-259a7e28-c334-43ac-aee6-ee45cc03b2b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3678243349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3678243349
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1215034743
Short name T95
Test name
Test status
Simulation time 336960630000 ps
CPU time 824.9 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:34:09 PM PDT 24
Peak memory 160804 kb
Host smart-22643fc5-1682-46d4-917c-c0ac39ea43fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1215034743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.1215034743
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2155114290
Short name T77
Test name
Test status
Simulation time 336345710000 ps
CPU time 946.55 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:38:09 PM PDT 24
Peak memory 160800 kb
Host smart-b33881ae-91ad-4268-b55a-ac2244a642f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2155114290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2155114290
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2456636131
Short name T96
Test name
Test status
Simulation time 336689890000 ps
CPU time 873.78 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:36:36 PM PDT 24
Peak memory 160772 kb
Host smart-fed8ee2c-b392-48ee-aa68-82778915f8ea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2456636131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2456636131
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1507376417
Short name T88
Test name
Test status
Simulation time 336560430000 ps
CPU time 862.28 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:36:25 PM PDT 24
Peak memory 160784 kb
Host smart-b6ba9bab-1075-45bf-bb7a-da98ba56be2a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1507376417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1507376417
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2017014946
Short name T74
Test name
Test status
Simulation time 337045290000 ps
CPU time 849.93 seconds
Started Jun 02 02:00:51 PM PDT 24
Finished Jun 02 02:35:22 PM PDT 24
Peak memory 160748 kb
Host smart-6a668906-ee78-485d-9f6d-dea490aa40a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2017014946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2017014946
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.4077501344
Short name T84
Test name
Test status
Simulation time 336613790000 ps
CPU time 766.94 seconds
Started Jun 02 02:00:52 PM PDT 24
Finished Jun 02 02:32:25 PM PDT 24
Peak memory 160752 kb
Host smart-4a7550e9-4731-4b97-bccd-cadd402af01c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4077501344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.4077501344
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4206745573
Short name T105
Test name
Test status
Simulation time 336948570000 ps
CPU time 624.93 seconds
Started Jun 02 02:00:50 PM PDT 24
Finished Jun 02 02:26:41 PM PDT 24
Peak memory 160820 kb
Host smart-736e1648-b461-4cb4-bf0a-939e96d778ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4206745573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4206745573
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1160095381
Short name T98
Test name
Test status
Simulation time 336772630000 ps
CPU time 958.13 seconds
Started Jun 02 02:00:49 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 160744 kb
Host smart-09bf8137-eaf0-4d60-a44b-3e8e4acf4aa1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1160095381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1160095381
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.349273700
Short name T17
Test name
Test status
Simulation time 337044930000 ps
CPU time 866.07 seconds
Started Jun 02 02:00:45 PM PDT 24
Finished Jun 02 02:36:35 PM PDT 24
Peak memory 160700 kb
Host smart-e098babb-444f-449f-9552-2148c9ddf668
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=349273700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.349273700
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1133135121
Short name T87
Test name
Test status
Simulation time 336862390000 ps
CPU time 751.16 seconds
Started Jun 02 02:00:46 PM PDT 24
Finished Jun 02 02:31:18 PM PDT 24
Peak memory 160788 kb
Host smart-5c4b2771-781f-457f-99b7-c949fa171906
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1133135121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1133135121
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3328963684
Short name T91
Test name
Test status
Simulation time 336766630000 ps
CPU time 761.86 seconds
Started Jun 02 02:00:44 PM PDT 24
Finished Jun 02 02:32:03 PM PDT 24
Peak memory 160800 kb
Host smart-a27a3803-7f2d-4cb7-9c0e-201141be54e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328963684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3328963684
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1742297952
Short name T78
Test name
Test status
Simulation time 336336210000 ps
CPU time 842.83 seconds
Started Jun 02 02:00:45 PM PDT 24
Finished Jun 02 02:35:13 PM PDT 24
Peak memory 160772 kb
Host smart-228f57d7-1b55-4182-b7a3-9ea0a1d69892
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1742297952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1742297952
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1667368349
Short name T166
Test name
Test status
Simulation time 337016970000 ps
CPU time 808.98 seconds
Started Jun 02 02:09:16 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 160796 kb
Host smart-3704dd64-44d9-4583-bb73-b19c530e2c2c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1667368349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1667368349
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1929765510
Short name T173
Test name
Test status
Simulation time 336523370000 ps
CPU time 803.47 seconds
Started Jun 02 02:09:17 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 160796 kb
Host smart-a3c2069f-3d28-48b9-be52-ff465b19150e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1929765510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1929765510
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3736535761
Short name T163
Test name
Test status
Simulation time 337088410000 ps
CPU time 811.6 seconds
Started Jun 02 02:09:19 PM PDT 24
Finished Jun 02 02:42:32 PM PDT 24
Peak memory 160804 kb
Host smart-072f1300-0186-4ed4-b142-cfe3e3d82f4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3736535761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3736535761
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3822870607
Short name T179
Test name
Test status
Simulation time 336485350000 ps
CPU time 772.84 seconds
Started Jun 02 02:09:20 PM PDT 24
Finished Jun 02 02:40:32 PM PDT 24
Peak memory 160808 kb
Host smart-361afe30-c916-4836-8a40-e44cad77c07d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3822870607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3822870607
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2933540249
Short name T161
Test name
Test status
Simulation time 337069970000 ps
CPU time 759.95 seconds
Started Jun 02 02:09:19 PM PDT 24
Finished Jun 02 02:40:38 PM PDT 24
Peak memory 160752 kb
Host smart-80a72c85-09c7-4420-ae78-b9a537f4256b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2933540249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2933540249
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1026429953
Short name T198
Test name
Test status
Simulation time 336963670000 ps
CPU time 841.46 seconds
Started Jun 02 02:09:26 PM PDT 24
Finished Jun 02 02:44:05 PM PDT 24
Peak memory 160884 kb
Host smart-c4f24f97-c775-4d8c-8709-cd2b09cadf9a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1026429953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1026429953
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.813529164
Short name T193
Test name
Test status
Simulation time 336585590000 ps
CPU time 867.68 seconds
Started Jun 02 02:09:28 PM PDT 24
Finished Jun 02 02:44:39 PM PDT 24
Peak memory 160800 kb
Host smart-358fbcb1-dc5a-467d-bf63-353317664137
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=813529164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.813529164
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2081455412
Short name T178
Test name
Test status
Simulation time 336701110000 ps
CPU time 825.7 seconds
Started Jun 02 02:09:27 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 160820 kb
Host smart-f52759ca-777b-43a0-995e-718cc1312630
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2081455412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2081455412
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3392002230
Short name T186
Test name
Test status
Simulation time 336985630000 ps
CPU time 970.01 seconds
Started Jun 02 02:09:26 PM PDT 24
Finished Jun 02 02:48:24 PM PDT 24
Peak memory 160788 kb
Host smart-cfa86fac-0b5a-47d1-bb50-7ddff3d6862e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3392002230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3392002230
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.238614090
Short name T175
Test name
Test status
Simulation time 336665610000 ps
CPU time 793.87 seconds
Started Jun 02 02:09:26 PM PDT 24
Finished Jun 02 02:42:01 PM PDT 24
Peak memory 160788 kb
Host smart-98b6a3a4-0d6a-4ee9-acfd-cd8f32c5ef67
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=238614090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.238614090
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2751492779
Short name T194
Test name
Test status
Simulation time 337061330000 ps
CPU time 840.09 seconds
Started Jun 02 02:09:26 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 160800 kb
Host smart-ad4ab005-fbf3-41ef-9ea0-38cdb73c297f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2751492779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2751492779
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2920236154
Short name T26
Test name
Test status
Simulation time 336709190000 ps
CPU time 914.18 seconds
Started Jun 02 02:09:17 PM PDT 24
Finished Jun 02 02:46:49 PM PDT 24
Peak memory 160768 kb
Host smart-26851d5b-b611-4ebf-ae77-d24877188ac7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2920236154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2920236154
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1056072618
Short name T25
Test name
Test status
Simulation time 336590750000 ps
CPU time 778.37 seconds
Started Jun 02 02:09:25 PM PDT 24
Finished Jun 02 02:41:40 PM PDT 24
Peak memory 160820 kb
Host smart-adec0c72-32d7-4246-9dd0-88deec1dc023
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1056072618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1056072618
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3340552406
Short name T189
Test name
Test status
Simulation time 336637350000 ps
CPU time 832.87 seconds
Started Jun 02 02:09:25 PM PDT 24
Finished Jun 02 02:42:36 PM PDT 24
Peak memory 160804 kb
Host smart-f31bbe96-a06e-4128-a136-dd8e8085a50b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3340552406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3340552406
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1372868129
Short name T192
Test name
Test status
Simulation time 336478570000 ps
CPU time 854.6 seconds
Started Jun 02 02:09:27 PM PDT 24
Finished Jun 02 02:44:44 PM PDT 24
Peak memory 160776 kb
Host smart-27f20a16-be3e-4e14-8759-1b30397b6cb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1372868129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1372868129
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2096194894
Short name T30
Test name
Test status
Simulation time 337127170000 ps
CPU time 819.95 seconds
Started Jun 02 02:09:29 PM PDT 24
Finished Jun 02 02:42:29 PM PDT 24
Peak memory 160776 kb
Host smart-f4c31a6d-f783-4338-922b-7f8bf32f50d0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2096194894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2096194894
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.207280864
Short name T29
Test name
Test status
Simulation time 336601350000 ps
CPU time 774.92 seconds
Started Jun 02 02:09:30 PM PDT 24
Finished Jun 02 02:40:45 PM PDT 24
Peak memory 160816 kb
Host smart-8f5d203d-46c5-4d3a-8611-fbbb0196a1f6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=207280864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.207280864
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3285687127
Short name T168
Test name
Test status
Simulation time 336597790000 ps
CPU time 781.79 seconds
Started Jun 02 02:09:30 PM PDT 24
Finished Jun 02 02:41:42 PM PDT 24
Peak memory 160820 kb
Host smart-c8545295-3b45-4ba9-89e1-481e18402df4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3285687127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3285687127
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3085718967
Short name T21
Test name
Test status
Simulation time 336801110000 ps
CPU time 819.73 seconds
Started Jun 02 02:09:30 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 160820 kb
Host smart-907c7925-75ff-4fff-bfb0-aa8ebad4e574
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3085718967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3085718967
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3166722894
Short name T185
Test name
Test status
Simulation time 336449690000 ps
CPU time 875 seconds
Started Jun 02 02:09:31 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 160808 kb
Host smart-95d354e6-5961-4890-9ed3-2f5693218b58
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3166722894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3166722894
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.395519167
Short name T27
Test name
Test status
Simulation time 336834250000 ps
CPU time 852.08 seconds
Started Jun 02 02:09:30 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 160804 kb
Host smart-7158e186-7395-4279-af5b-69224b6fc0f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395519167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.395519167
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2545646600
Short name T176
Test name
Test status
Simulation time 336969010000 ps
CPU time 815.69 seconds
Started Jun 02 02:09:29 PM PDT 24
Finished Jun 02 02:42:22 PM PDT 24
Peak memory 160776 kb
Host smart-1dcb72e0-6049-430a-a437-7f07b2a0bcee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2545646600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2545646600
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3349165412
Short name T170
Test name
Test status
Simulation time 336884470000 ps
CPU time 905.73 seconds
Started Jun 02 02:09:17 PM PDT 24
Finished Jun 02 02:46:30 PM PDT 24
Peak memory 160768 kb
Host smart-44049027-71ef-41aa-ac17-5e2cdc072ea4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3349165412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3349165412
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1829121408
Short name T23
Test name
Test status
Simulation time 336422170000 ps
CPU time 795.11 seconds
Started Jun 02 02:09:32 PM PDT 24
Finished Jun 02 02:41:45 PM PDT 24
Peak memory 160808 kb
Host smart-f9c7d214-51fb-426d-a9e7-ad8d828c1b72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1829121408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1829121408
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3723952556
Short name T197
Test name
Test status
Simulation time 336440290000 ps
CPU time 853.04 seconds
Started Jun 02 02:09:31 PM PDT 24
Finished Jun 02 02:44:35 PM PDT 24
Peak memory 160808 kb
Host smart-7b9a25f7-c4ff-4a99-8d34-19ef948db1e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3723952556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3723952556
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.55937072
Short name T22
Test name
Test status
Simulation time 336571770000 ps
CPU time 834.65 seconds
Started Jun 02 02:09:29 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 160780 kb
Host smart-8e408b6d-f82d-4df9-a921-10a93120a5a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=55937072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.55937072
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.87218231
Short name T199
Test name
Test status
Simulation time 336962850000 ps
CPU time 838.3 seconds
Started Jun 02 02:09:31 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 160708 kb
Host smart-bae5c31e-dd18-46c2-9fd2-b64d67aaa5ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=87218231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.87218231
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.181907407
Short name T188
Test name
Test status
Simulation time 336624010000 ps
CPU time 826.17 seconds
Started Jun 02 02:09:31 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 160780 kb
Host smart-8de35b1a-72f3-4843-92c3-5fa52f17e879
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=181907407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.181907407
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3916704714
Short name T28
Test name
Test status
Simulation time 336959990000 ps
CPU time 667.72 seconds
Started Jun 02 02:09:31 PM PDT 24
Finished Jun 02 02:37:27 PM PDT 24
Peak memory 160812 kb
Host smart-d52cf0d2-623d-41ff-bbf2-017b9903f376
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3916704714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3916704714
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1800603052
Short name T172
Test name
Test status
Simulation time 336698310000 ps
CPU time 770.19 seconds
Started Jun 02 02:09:35 PM PDT 24
Finished Jun 02 02:41:47 PM PDT 24
Peak memory 160820 kb
Host smart-b9526a98-5a0e-44e5-83e4-fed854b55526
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1800603052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1800603052
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2128002370
Short name T196
Test name
Test status
Simulation time 336358570000 ps
CPU time 848.7 seconds
Started Jun 02 02:09:36 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 160752 kb
Host smart-b0b9298e-5df5-486f-a5b9-21b9b12b0979
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2128002370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2128002370
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.563445049
Short name T182
Test name
Test status
Simulation time 336915650000 ps
CPU time 774.62 seconds
Started Jun 02 02:09:34 PM PDT 24
Finished Jun 02 02:41:20 PM PDT 24
Peak memory 160768 kb
Host smart-7f7cb39a-6da3-49d0-b99d-7bcc19e9007a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=563445049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.563445049
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.168475875
Short name T164
Test name
Test status
Simulation time 336475430000 ps
CPU time 770.77 seconds
Started Jun 02 02:09:34 PM PDT 24
Finished Jun 02 02:40:48 PM PDT 24
Peak memory 160784 kb
Host smart-c1424c0b-3516-4592-a747-06bc8aed60dd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=168475875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.168475875
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.4071235488
Short name T167
Test name
Test status
Simulation time 336606010000 ps
CPU time 856.72 seconds
Started Jun 02 02:09:15 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 160872 kb
Host smart-95eb8dfe-60dd-4951-9be0-316004a6de11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4071235488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.4071235488
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1173387515
Short name T191
Test name
Test status
Simulation time 336879910000 ps
CPU time 825.46 seconds
Started Jun 02 02:09:36 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 160820 kb
Host smart-d5bc5e9e-6f8b-441a-b5e2-b5fc5ade322c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1173387515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1173387515
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.655466454
Short name T180
Test name
Test status
Simulation time 336821930000 ps
CPU time 731.07 seconds
Started Jun 02 02:09:34 PM PDT 24
Finished Jun 02 02:39:21 PM PDT 24
Peak memory 160808 kb
Host smart-eaeafd7f-5f08-49d7-9427-cd21bf9dc63e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=655466454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.655466454
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2962640618
Short name T195
Test name
Test status
Simulation time 336767190000 ps
CPU time 800.18 seconds
Started Jun 02 02:09:34 PM PDT 24
Finished Jun 02 02:42:08 PM PDT 24
Peak memory 160808 kb
Host smart-513a3ded-1463-4a65-8def-226e739a8fde
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2962640618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2962640618
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.280406620
Short name T174
Test name
Test status
Simulation time 336417850000 ps
CPU time 825.8 seconds
Started Jun 02 02:09:37 PM PDT 24
Finished Jun 02 02:43:45 PM PDT 24
Peak memory 160816 kb
Host smart-4ceffb4a-5bb1-4510-8f53-da1448579de7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=280406620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.280406620
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3555859245
Short name T165
Test name
Test status
Simulation time 336567050000 ps
CPU time 769.25 seconds
Started Jun 02 02:09:36 PM PDT 24
Finished Jun 02 02:41:34 PM PDT 24
Peak memory 160752 kb
Host smart-0d533d1f-63cc-4e35-815e-7134deeb69db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3555859245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3555859245
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2501118258
Short name T183
Test name
Test status
Simulation time 336760090000 ps
CPU time 753.58 seconds
Started Jun 02 02:09:36 PM PDT 24
Finished Jun 02 02:41:08 PM PDT 24
Peak memory 160752 kb
Host smart-56edd2dc-f712-4147-9e61-d704326738e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2501118258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2501118258
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3604834605
Short name T190
Test name
Test status
Simulation time 336823990000 ps
CPU time 815.66 seconds
Started Jun 02 02:09:34 PM PDT 24
Finished Jun 02 02:42:26 PM PDT 24
Peak memory 160808 kb
Host smart-eacf5364-dce7-498e-9f34-c76c6ee39cf0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3604834605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3604834605
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.253358977
Short name T171
Test name
Test status
Simulation time 336494090000 ps
CPU time 806.28 seconds
Started Jun 02 02:09:33 PM PDT 24
Finished Jun 02 02:42:21 PM PDT 24
Peak memory 160880 kb
Host smart-5d952112-07a7-499c-a5e0-dcb2e5197c9b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=253358977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.253358977
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1366244274
Short name T162
Test name
Test status
Simulation time 336987270000 ps
CPU time 831.81 seconds
Started Jun 02 02:09:35 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 160752 kb
Host smart-032a3b29-fbf4-4931-b3aa-308171884149
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1366244274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1366244274
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.427407676
Short name T169
Test name
Test status
Simulation time 336434790000 ps
CPU time 855.36 seconds
Started Jun 02 02:09:35 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 160772 kb
Host smart-d3f08702-cc2f-4d8e-a9f9-26895873eaf2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=427407676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.427407676
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.602294438
Short name T200
Test name
Test status
Simulation time 336882350000 ps
CPU time 769.05 seconds
Started Jun 02 02:09:20 PM PDT 24
Finished Jun 02 02:41:11 PM PDT 24
Peak memory 160724 kb
Host smart-a0b32e0a-ea37-4fed-8a3e-46b065e935f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=602294438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.602294438
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3809254662
Short name T184
Test name
Test status
Simulation time 337054150000 ps
CPU time 708.65 seconds
Started Jun 02 02:09:20 PM PDT 24
Finished Jun 02 02:38:27 PM PDT 24
Peak memory 160800 kb
Host smart-6e15ffe2-4863-4508-8ece-db53ae6a0858
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3809254662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3809254662
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.506162321
Short name T181
Test name
Test status
Simulation time 336469150000 ps
CPU time 753.57 seconds
Started Jun 02 02:09:19 PM PDT 24
Finished Jun 02 02:40:05 PM PDT 24
Peak memory 160796 kb
Host smart-5a2414e2-6e84-43d4-add0-a207baad90f3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=506162321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.506162321
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4057874688
Short name T187
Test name
Test status
Simulation time 336467790000 ps
CPU time 875.67 seconds
Started Jun 02 02:09:20 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 160796 kb
Host smart-8cb14f55-360e-43d3-bf01-41f3bc7edf3e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4057874688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.4057874688
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2405240816
Short name T177
Test name
Test status
Simulation time 336549550000 ps
CPU time 831.49 seconds
Started Jun 02 02:09:22 PM PDT 24
Finished Jun 02 02:43:12 PM PDT 24
Peak memory 160772 kb
Host smart-22106f3a-3ae8-41f0-8aa5-bbf1553da641
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2405240816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2405240816
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1450556016
Short name T128
Test name
Test status
Simulation time 1508550000 ps
CPU time 4.62 seconds
Started Jun 02 02:08:44 PM PDT 24
Finished Jun 02 02:08:54 PM PDT 24
Peak memory 164868 kb
Host smart-20913adb-ba7f-4408-a8a1-7c075053388b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1450556016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1450556016
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2024047019
Short name T138
Test name
Test status
Simulation time 1507290000 ps
CPU time 5.25 seconds
Started Jun 02 02:08:48 PM PDT 24
Finished Jun 02 02:09:00 PM PDT 24
Peak memory 164840 kb
Host smart-5c8fe141-bf48-475a-a3a5-c8378be70a8b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2024047019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2024047019
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2619491494
Short name T124
Test name
Test status
Simulation time 1361210000 ps
CPU time 3.56 seconds
Started Jun 02 02:08:48 PM PDT 24
Finished Jun 02 02:08:56 PM PDT 24
Peak memory 164856 kb
Host smart-9aa0ae85-6b81-4ff8-9d17-53d0afc55d27
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619491494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2619491494
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1418198853
Short name T130
Test name
Test status
Simulation time 1389510000 ps
CPU time 4.78 seconds
Started Jun 02 02:08:49 PM PDT 24
Finished Jun 02 02:09:01 PM PDT 24
Peak memory 164868 kb
Host smart-cf8e5be0-fdec-4a86-ab95-75d03131ea19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1418198853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1418198853
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3831527331
Short name T118
Test name
Test status
Simulation time 1202010000 ps
CPU time 4.48 seconds
Started Jun 02 02:08:51 PM PDT 24
Finished Jun 02 02:09:02 PM PDT 24
Peak memory 164840 kb
Host smart-a178329d-710c-46c4-8dae-0c3cda479212
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3831527331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3831527331
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1376916479
Short name T157
Test name
Test status
Simulation time 1361010000 ps
CPU time 3.76 seconds
Started Jun 02 02:08:48 PM PDT 24
Finished Jun 02 02:08:56 PM PDT 24
Peak memory 164848 kb
Host smart-2e17e8a8-4d0e-4dff-87d1-76be2ed0ba93
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1376916479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1376916479
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1159800717
Short name T148
Test name
Test status
Simulation time 1448170000 ps
CPU time 4.38 seconds
Started Jun 02 02:08:48 PM PDT 24
Finished Jun 02 02:08:58 PM PDT 24
Peak memory 164888 kb
Host smart-ad92392c-e592-4873-8909-1d0c1a88adf7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159800717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1159800717
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4024749810
Short name T135
Test name
Test status
Simulation time 1530030000 ps
CPU time 6.09 seconds
Started Jun 02 02:08:50 PM PDT 24
Finished Jun 02 02:09:04 PM PDT 24
Peak memory 164832 kb
Host smart-d2638a52-2470-4c34-8e9c-6f642b9e303f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024749810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4024749810
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1177483157
Short name T137
Test name
Test status
Simulation time 1532350000 ps
CPU time 5.53 seconds
Started Jun 02 02:08:54 PM PDT 24
Finished Jun 02 02:09:07 PM PDT 24
Peak memory 164928 kb
Host smart-9dadcd6b-2233-404d-b543-572200861027
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177483157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1177483157
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.959834485
Short name T153
Test name
Test status
Simulation time 1626190000 ps
CPU time 6.77 seconds
Started Jun 02 02:08:55 PM PDT 24
Finished Jun 02 02:09:10 PM PDT 24
Peak memory 164876 kb
Host smart-b742ed60-c8b4-40a6-894e-b2a6d0974759
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=959834485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.959834485
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2648064754
Short name T143
Test name
Test status
Simulation time 1315550000 ps
CPU time 4.65 seconds
Started Jun 02 02:08:54 PM PDT 24
Finished Jun 02 02:09:05 PM PDT 24
Peak memory 164832 kb
Host smart-6fb361d7-d7f9-4b24-8f11-7399802074ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648064754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2648064754
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1405477139
Short name T120
Test name
Test status
Simulation time 1497870000 ps
CPU time 5.79 seconds
Started Jun 02 02:08:54 PM PDT 24
Finished Jun 02 02:09:07 PM PDT 24
Peak memory 164884 kb
Host smart-3a2dad80-3a7e-4ce2-a78a-f044637b1d37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1405477139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1405477139
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.781189241
Short name T151
Test name
Test status
Simulation time 1575310000 ps
CPU time 5.1 seconds
Started Jun 02 02:08:45 PM PDT 24
Finished Jun 02 02:08:57 PM PDT 24
Peak memory 164872 kb
Host smart-a3cad6df-dea7-4a23-9203-0c534d7207f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=781189241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.781189241
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1495113915
Short name T126
Test name
Test status
Simulation time 1399230000 ps
CPU time 5.07 seconds
Started Jun 02 02:08:54 PM PDT 24
Finished Jun 02 02:09:06 PM PDT 24
Peak memory 164828 kb
Host smart-2c3c448e-3230-47a6-8283-e077e20fb370
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495113915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1495113915
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1795423242
Short name T112
Test name
Test status
Simulation time 1367670000 ps
CPU time 5.53 seconds
Started Jun 02 02:08:55 PM PDT 24
Finished Jun 02 02:09:07 PM PDT 24
Peak memory 165056 kb
Host smart-c232e61b-3a6c-4e53-b8f4-171b41f2bf4a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1795423242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1795423242
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.913571670
Short name T147
Test name
Test status
Simulation time 1203050000 ps
CPU time 4.21 seconds
Started Jun 02 02:08:53 PM PDT 24
Finished Jun 02 02:09:03 PM PDT 24
Peak memory 164848 kb
Host smart-74d5725b-3b6b-47e2-bccd-d44d34a4772d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=913571670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.913571670
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3351185983
Short name T154
Test name
Test status
Simulation time 1601250000 ps
CPU time 5.78 seconds
Started Jun 02 02:08:55 PM PDT 24
Finished Jun 02 02:09:09 PM PDT 24
Peak memory 164872 kb
Host smart-91dee1a3-73ff-430a-bc44-c549192ca7e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351185983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3351185983
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2407614298
Short name T119
Test name
Test status
Simulation time 1476410000 ps
CPU time 5.58 seconds
Started Jun 02 02:08:57 PM PDT 24
Finished Jun 02 02:09:10 PM PDT 24
Peak memory 164900 kb
Host smart-69f54204-a0bc-42e4-94a2-1b7696133738
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2407614298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2407614298
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1781370275
Short name T122
Test name
Test status
Simulation time 1257730000 ps
CPU time 4.04 seconds
Started Jun 02 02:09:01 PM PDT 24
Finished Jun 02 02:09:10 PM PDT 24
Peak memory 164864 kb
Host smart-98202f66-fa70-4e10-a5a7-a71eb8ab5570
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781370275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1781370275
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1984768101
Short name T115
Test name
Test status
Simulation time 1476210000 ps
CPU time 5.46 seconds
Started Jun 02 02:08:59 PM PDT 24
Finished Jun 02 02:09:11 PM PDT 24
Peak memory 164852 kb
Host smart-2632d313-b71c-4bf0-8929-37df4f8c0b4b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1984768101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1984768101
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2808782909
Short name T117
Test name
Test status
Simulation time 1530290000 ps
CPU time 5.54 seconds
Started Jun 02 02:09:00 PM PDT 24
Finished Jun 02 02:09:13 PM PDT 24
Peak memory 164888 kb
Host smart-ddae9ea8-2601-4080-a239-7d45c4cee0a8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2808782909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2808782909
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1637366435
Short name T125
Test name
Test status
Simulation time 1511910000 ps
CPU time 6.94 seconds
Started Jun 02 02:08:58 PM PDT 24
Finished Jun 02 02:09:13 PM PDT 24
Peak memory 164888 kb
Host smart-18a3c867-8803-4502-a40e-4b89922cd3ca
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1637366435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1637366435
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1495260921
Short name T160
Test name
Test status
Simulation time 1415690000 ps
CPU time 5.8 seconds
Started Jun 02 02:09:00 PM PDT 24
Finished Jun 02 02:09:12 PM PDT 24
Peak memory 164860 kb
Host smart-3535c9c8-745a-417a-9af1-b25b3dca1c05
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495260921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1495260921
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3898969107
Short name T155
Test name
Test status
Simulation time 1326290000 ps
CPU time 3.5 seconds
Started Jun 02 02:08:46 PM PDT 24
Finished Jun 02 02:08:54 PM PDT 24
Peak memory 164888 kb
Host smart-118d6cc0-3d3f-4f31-ab4e-6b9ed7b15ac8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3898969107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3898969107
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3262983573
Short name T142
Test name
Test status
Simulation time 1380410000 ps
CPU time 4.4 seconds
Started Jun 02 02:09:02 PM PDT 24
Finished Jun 02 02:09:12 PM PDT 24
Peak memory 164900 kb
Host smart-1da29957-83e4-46b1-bc92-52384b8f8680
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3262983573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3262983573
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2468747523
Short name T131
Test name
Test status
Simulation time 1606490000 ps
CPU time 4.03 seconds
Started Jun 02 02:08:59 PM PDT 24
Finished Jun 02 02:09:08 PM PDT 24
Peak memory 164880 kb
Host smart-5c320345-23b2-414d-bbd4-0345a0cb72e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468747523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2468747523
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1806866193
Short name T134
Test name
Test status
Simulation time 1577570000 ps
CPU time 4.87 seconds
Started Jun 02 02:09:01 PM PDT 24
Finished Jun 02 02:09:12 PM PDT 24
Peak memory 164900 kb
Host smart-69ce4aa7-8bae-4da2-8866-1c9f21a52811
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1806866193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1806866193
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3800454825
Short name T146
Test name
Test status
Simulation time 1589550000 ps
CPU time 3.69 seconds
Started Jun 02 02:08:59 PM PDT 24
Finished Jun 02 02:09:08 PM PDT 24
Peak memory 164884 kb
Host smart-6d0d6c35-ac8b-472e-8ce1-31efa05f617d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3800454825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3800454825
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3262756233
Short name T159
Test name
Test status
Simulation time 1443290000 ps
CPU time 4.59 seconds
Started Jun 02 02:09:03 PM PDT 24
Finished Jun 02 02:09:13 PM PDT 24
Peak memory 164824 kb
Host smart-c48db63a-8533-4890-819a-c5da8662e6ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3262756233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3262756233
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.768610963
Short name T140
Test name
Test status
Simulation time 1549770000 ps
CPU time 5.28 seconds
Started Jun 02 02:08:59 PM PDT 24
Finished Jun 02 02:09:11 PM PDT 24
Peak memory 164840 kb
Host smart-9e81848b-c69b-41d8-a629-ba9c2e27f861
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=768610963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.768610963
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.669772144
Short name T156
Test name
Test status
Simulation time 1493450000 ps
CPU time 4.47 seconds
Started Jun 02 02:09:05 PM PDT 24
Finished Jun 02 02:09:14 PM PDT 24
Peak memory 164876 kb
Host smart-da98892b-6b74-43b4-ad90-54e8a4a78996
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=669772144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.669772144
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3792409745
Short name T136
Test name
Test status
Simulation time 1534270000 ps
CPU time 5.7 seconds
Started Jun 02 02:09:05 PM PDT 24
Finished Jun 02 02:09:19 PM PDT 24
Peak memory 165056 kb
Host smart-2e9bfd7d-6ef8-4b46-a454-b1875514a0fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3792409745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3792409745
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1008348767
Short name T132
Test name
Test status
Simulation time 1537970000 ps
CPU time 4.16 seconds
Started Jun 02 02:09:05 PM PDT 24
Finished Jun 02 02:09:15 PM PDT 24
Peak memory 164852 kb
Host smart-38e41db1-4898-4394-9bd6-63eae273cd06
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008348767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1008348767
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.475700815
Short name T121
Test name
Test status
Simulation time 1194290000 ps
CPU time 4.76 seconds
Started Jun 02 02:09:05 PM PDT 24
Finished Jun 02 02:09:16 PM PDT 24
Peak memory 164892 kb
Host smart-7d57b726-cdb7-47ee-af02-d81b5f9fa479
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=475700815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.475700815
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1538983546
Short name T152
Test name
Test status
Simulation time 1515970000 ps
CPU time 4.99 seconds
Started Jun 02 02:08:44 PM PDT 24
Finished Jun 02 02:08:56 PM PDT 24
Peak memory 164840 kb
Host smart-0b84b5bc-da28-4339-b889-e5d90d40e232
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1538983546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1538983546
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.676670225
Short name T116
Test name
Test status
Simulation time 1446310000 ps
CPU time 5.48 seconds
Started Jun 02 02:09:04 PM PDT 24
Finished Jun 02 02:09:16 PM PDT 24
Peak memory 164820 kb
Host smart-44fc995f-ed8e-427c-a732-2bddc02285df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=676670225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.676670225
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.388428567
Short name T123
Test name
Test status
Simulation time 1513770000 ps
CPU time 6.84 seconds
Started Jun 02 02:09:04 PM PDT 24
Finished Jun 02 02:09:19 PM PDT 24
Peak memory 164840 kb
Host smart-39ccfdc3-3ac2-4a86-98bd-57b377532e1e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388428567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.388428567
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.793988267
Short name T149
Test name
Test status
Simulation time 1367870000 ps
CPU time 5.47 seconds
Started Jun 02 02:09:04 PM PDT 24
Finished Jun 02 02:09:17 PM PDT 24
Peak memory 164860 kb
Host smart-6e172265-c82c-4dcf-98ce-b05a4cba3332
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793988267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.793988267
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2242079640
Short name T113
Test name
Test status
Simulation time 1455670000 ps
CPU time 5.51 seconds
Started Jun 02 02:09:06 PM PDT 24
Finished Jun 02 02:09:18 PM PDT 24
Peak memory 164900 kb
Host smart-2ee280fe-464b-4396-bb56-16744e8083a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242079640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2242079640
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.4095170169
Short name T141
Test name
Test status
Simulation time 1434550000 ps
CPU time 4.78 seconds
Started Jun 02 02:09:09 PM PDT 24
Finished Jun 02 02:09:21 PM PDT 24
Peak memory 164888 kb
Host smart-9814218b-4b75-488c-97bd-056a4c092333
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4095170169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.4095170169
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1737221018
Short name T144
Test name
Test status
Simulation time 1540390000 ps
CPU time 6.04 seconds
Started Jun 02 02:09:16 PM PDT 24
Finished Jun 02 02:09:31 PM PDT 24
Peak memory 164876 kb
Host smart-c32ccd36-cec3-4d5d-bbd2-5260d9b27b9f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1737221018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1737221018
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.3075803842
Short name T145
Test name
Test status
Simulation time 1471790000 ps
CPU time 5.65 seconds
Started Jun 02 02:09:16 PM PDT 24
Finished Jun 02 02:09:30 PM PDT 24
Peak memory 164876 kb
Host smart-80919974-f0c9-4c25-a002-7a2c91ee9643
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075803842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.3075803842
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3295577525
Short name T139
Test name
Test status
Simulation time 1544590000 ps
CPU time 5.21 seconds
Started Jun 02 02:09:14 PM PDT 24
Finished Jun 02 02:09:26 PM PDT 24
Peak memory 164872 kb
Host smart-2eead3bb-750f-43c1-82c5-6d0753691648
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3295577525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3295577525
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1151697616
Short name T133
Test name
Test status
Simulation time 1416330000 ps
CPU time 4.71 seconds
Started Jun 02 02:09:14 PM PDT 24
Finished Jun 02 02:09:25 PM PDT 24
Peak memory 164880 kb
Host smart-6ca477c9-0417-47a0-ae33-be1d3986a741
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1151697616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1151697616
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3986159427
Short name T158
Test name
Test status
Simulation time 1346190000 ps
CPU time 4.82 seconds
Started Jun 02 02:09:13 PM PDT 24
Finished Jun 02 02:09:25 PM PDT 24
Peak memory 164876 kb
Host smart-6cc05a9c-08fc-41c5-8874-7d198f5d3180
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986159427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3986159427
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3872464908
Short name T111
Test name
Test status
Simulation time 1427410000 ps
CPU time 3.62 seconds
Started Jun 02 02:08:45 PM PDT 24
Finished Jun 02 02:08:54 PM PDT 24
Peak memory 164848 kb
Host smart-861c2d5d-ab68-46ee-9b98-e16346849e36
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3872464908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3872464908
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1947814418
Short name T114
Test name
Test status
Simulation time 1323830000 ps
CPU time 4.48 seconds
Started Jun 02 02:08:45 PM PDT 24
Finished Jun 02 02:08:55 PM PDT 24
Peak memory 164888 kb
Host smart-85420155-0286-461a-9e20-de7df9796234
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947814418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1947814418
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1468617710
Short name T150
Test name
Test status
Simulation time 1529850000 ps
CPU time 5.12 seconds
Started Jun 02 02:08:49 PM PDT 24
Finished Jun 02 02:09:01 PM PDT 24
Peak memory 164884 kb
Host smart-b095c2a6-909c-413c-8727-5f575096fd72
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1468617710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1468617710
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.143299891
Short name T127
Test name
Test status
Simulation time 1363070000 ps
CPU time 4.16 seconds
Started Jun 02 02:08:49 PM PDT 24
Finished Jun 02 02:08:58 PM PDT 24
Peak memory 164848 kb
Host smart-67b3790d-0e7d-49bd-9a6e-351c18f86d13
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=143299891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.143299891
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2293720076
Short name T129
Test name
Test status
Simulation time 1403950000 ps
CPU time 5.55 seconds
Started Jun 02 02:08:50 PM PDT 24
Finished Jun 02 02:09:03 PM PDT 24
Peak memory 164832 kb
Host smart-0d55db57-bcac-4a23-9ed9-b78123a72038
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2293720076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2293720076
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.818999841
Short name T7
Test name
Test status
Simulation time 1416370000 ps
CPU time 5.27 seconds
Started Jun 02 01:45:46 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164816 kb
Host smart-fe93bb5f-ff79-434b-97e8-17f031d05441
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=818999841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.818999841
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2035255057
Short name T67
Test name
Test status
Simulation time 1254970000 ps
CPU time 4.86 seconds
Started Jun 02 01:45:45 PM PDT 24
Finished Jun 02 01:45:55 PM PDT 24
Peak memory 164868 kb
Host smart-1874ac5d-ac34-41c7-bfb0-3f89d8dbbed9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2035255057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2035255057
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2532976387
Short name T47
Test name
Test status
Simulation time 1382870000 ps
CPU time 5.26 seconds
Started Jun 02 01:45:42 PM PDT 24
Finished Jun 02 01:45:54 PM PDT 24
Peak memory 164888 kb
Host smart-a3d2e646-5ead-4023-b231-6adc584e2d46
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2532976387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2532976387
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2036621064
Short name T57
Test name
Test status
Simulation time 1624550000 ps
CPU time 3.57 seconds
Started Jun 02 01:45:42 PM PDT 24
Finished Jun 02 01:45:51 PM PDT 24
Peak memory 164892 kb
Host smart-cc5ae493-325e-45f8-b6fd-9457d765cac9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2036621064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2036621064
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3105028823
Short name T56
Test name
Test status
Simulation time 1442730000 ps
CPU time 3.77 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164892 kb
Host smart-5c4f4d83-e058-42a2-a25f-b077952c4969
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105028823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3105028823
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1250888259
Short name T36
Test name
Test status
Simulation time 1142110000 ps
CPU time 3.02 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:54 PM PDT 24
Peak memory 164572 kb
Host smart-d581a88a-6129-48d5-aadf-12d4046da851
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1250888259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1250888259
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.71103546
Short name T51
Test name
Test status
Simulation time 1346010000 ps
CPU time 3.69 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164872 kb
Host smart-eedda2a7-5629-4c5b-9a44-8daf53137a67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=71103546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.71103546
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.665034912
Short name T54
Test name
Test status
Simulation time 1310650000 ps
CPU time 3.36 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:55 PM PDT 24
Peak memory 164532 kb
Host smart-0b2f8548-627e-405d-b1a5-9e4e86496481
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=665034912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.665034912
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1817718551
Short name T38
Test name
Test status
Simulation time 1383310000 ps
CPU time 4.9 seconds
Started Jun 02 01:45:44 PM PDT 24
Finished Jun 02 01:45:55 PM PDT 24
Peak memory 164928 kb
Host smart-98a9ef55-501d-450b-8a0a-5956cc6edf03
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1817718551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1817718551
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3637452108
Short name T49
Test name
Test status
Simulation time 1467010000 ps
CPU time 4.77 seconds
Started Jun 02 01:45:44 PM PDT 24
Finished Jun 02 01:45:54 PM PDT 24
Peak memory 164824 kb
Host smart-7dd2decb-9144-48d7-a369-3190580bec18
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3637452108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3637452108
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1505543433
Short name T39
Test name
Test status
Simulation time 1480290000 ps
CPU time 5.6 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:46:02 PM PDT 24
Peak memory 164900 kb
Host smart-bbacf22b-978d-4b05-973f-a0cfffb7acd4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505543433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1505543433
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1878814452
Short name T53
Test name
Test status
Simulation time 1460050000 ps
CPU time 4.62 seconds
Started Jun 02 01:45:42 PM PDT 24
Finished Jun 02 01:45:53 PM PDT 24
Peak memory 164880 kb
Host smart-f76dcc93-ecd8-42cc-8bb7-3ac37df2dd4c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1878814452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1878814452
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.202066960
Short name T50
Test name
Test status
Simulation time 1503950000 ps
CPU time 3.21 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164880 kb
Host smart-1b1f00a5-ec7c-46cf-87fe-e945c09e1592
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202066960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.202066960
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1826217560
Short name T42
Test name
Test status
Simulation time 1601830000 ps
CPU time 4.14 seconds
Started Jun 02 01:45:46 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164880 kb
Host smart-64cf28c5-59db-4cf3-abb8-215e016397f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1826217560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1826217560
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3331808985
Short name T32
Test name
Test status
Simulation time 1551170000 ps
CPU time 4.52 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164868 kb
Host smart-63590f30-65e2-433c-8f8c-43e910e5e495
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3331808985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3331808985
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1756099738
Short name T31
Test name
Test status
Simulation time 1268730000 ps
CPU time 3.2 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:57 PM PDT 24
Peak memory 164884 kb
Host smart-065bb160-aaf0-4399-a422-0ecf6af1a82b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1756099738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1756099738
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1571508903
Short name T64
Test name
Test status
Simulation time 1494050000 ps
CPU time 3.87 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164864 kb
Host smart-c08b9f5d-c7a8-44d1-b0c2-3391d0556f2f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571508903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1571508903
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.720701001
Short name T61
Test name
Test status
Simulation time 1553950000 ps
CPU time 4.39 seconds
Started Jun 02 01:45:50 PM PDT 24
Finished Jun 02 01:46:00 PM PDT 24
Peak memory 164840 kb
Host smart-3608743d-092b-4044-a79f-b4808a51efd3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=720701001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.720701001
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1851293572
Short name T35
Test name
Test status
Simulation time 1318850000 ps
CPU time 3.45 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:57 PM PDT 24
Peak memory 164876 kb
Host smart-93462929-1de1-448d-aa95-e9ce63812edd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1851293572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1851293572
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4152985533
Short name T69
Test name
Test status
Simulation time 1379430000 ps
CPU time 4.6 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164928 kb
Host smart-6e6a7ff9-044c-4255-88b6-890e0e231591
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152985533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4152985533
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.124732911
Short name T66
Test name
Test status
Simulation time 1515430000 ps
CPU time 4.34 seconds
Started Jun 02 01:45:51 PM PDT 24
Finished Jun 02 01:46:01 PM PDT 24
Peak memory 164824 kb
Host smart-9c5056ac-7da5-42cd-af3a-d83991ad3b64
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124732911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.124732911
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1650773931
Short name T1
Test name
Test status
Simulation time 1576010000 ps
CPU time 4.2 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164860 kb
Host smart-4db9d3fc-7a85-4d00-b60c-408e596d9838
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1650773931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1650773931
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.249333594
Short name T37
Test name
Test status
Simulation time 1493970000 ps
CPU time 3.1 seconds
Started Jun 02 01:45:43 PM PDT 24
Finished Jun 02 01:45:51 PM PDT 24
Peak memory 164884 kb
Host smart-ebf571a3-7db4-4c3c-937c-24a30390b55a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=249333594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.249333594
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1397255742
Short name T2
Test name
Test status
Simulation time 1466950000 ps
CPU time 3.25 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164892 kb
Host smart-1aa65598-cba0-4b8d-b038-58031becc17f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1397255742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1397255742
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1008598676
Short name T3
Test name
Test status
Simulation time 1227970000 ps
CPU time 2.95 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:45:55 PM PDT 24
Peak memory 164836 kb
Host smart-41f3cada-5e2b-421f-babf-ffec6495a678
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1008598676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1008598676
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3386199991
Short name T65
Test name
Test status
Simulation time 1516370000 ps
CPU time 5.18 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:46:00 PM PDT 24
Peak memory 164928 kb
Host smart-26324a67-96ae-4aba-9bb3-ef875b175514
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3386199991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3386199991
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4024142159
Short name T60
Test name
Test status
Simulation time 1437830000 ps
CPU time 3.76 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164880 kb
Host smart-67b67b0d-c314-4c35-91bf-b6632062653f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024142159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4024142159
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1334783542
Short name T55
Test name
Test status
Simulation time 1482070000 ps
CPU time 4.17 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:57 PM PDT 24
Peak memory 164876 kb
Host smart-df1a0554-f3da-484e-8c70-d6f878908f53
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1334783542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1334783542
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1230480730
Short name T44
Test name
Test status
Simulation time 1511290000 ps
CPU time 4.34 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164840 kb
Host smart-62205540-4c3a-42a3-8a54-671a5d43772f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1230480730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1230480730
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.620207885
Short name T48
Test name
Test status
Simulation time 1454690000 ps
CPU time 4.22 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164832 kb
Host smart-86666f65-010e-4840-b64a-e0474de914e1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=620207885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.620207885
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2564854257
Short name T59
Test name
Test status
Simulation time 1589190000 ps
CPU time 5.73 seconds
Started Jun 02 01:45:50 PM PDT 24
Finished Jun 02 01:46:03 PM PDT 24
Peak memory 164832 kb
Host smart-828928d1-cae7-4a0a-adae-570a96d35060
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2564854257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2564854257
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3940137146
Short name T52
Test name
Test status
Simulation time 1510990000 ps
CPU time 4.31 seconds
Started Jun 02 01:45:48 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164876 kb
Host smart-f28904d7-be21-4d15-91b5-4d5579166f75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3940137146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3940137146
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.57627984
Short name T41
Test name
Test status
Simulation time 1205150000 ps
CPU time 4.27 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164860 kb
Host smart-4fbb66e7-7ebf-4ee2-bfe2-4adfc8561fb2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=57627984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.57627984
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2997974669
Short name T11
Test name
Test status
Simulation time 1439470000 ps
CPU time 5.43 seconds
Started Jun 02 01:45:45 PM PDT 24
Finished Jun 02 01:45:57 PM PDT 24
Peak memory 164832 kb
Host smart-ce38a96b-469d-494e-8027-ef036b6c2742
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997974669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2997974669
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3946736533
Short name T45
Test name
Test status
Simulation time 1212950000 ps
CPU time 3.75 seconds
Started Jun 02 01:45:51 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164888 kb
Host smart-c0ff5b0e-05a8-4d93-9d86-3fdbe2774713
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946736533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3946736533
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3663928931
Short name T68
Test name
Test status
Simulation time 1514970000 ps
CPU time 5.15 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:59 PM PDT 24
Peak memory 164864 kb
Host smart-394a9bb2-033f-4b77-85cf-ae8098fd36f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3663928931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3663928931
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2422036393
Short name T13
Test name
Test status
Simulation time 1494210000 ps
CPU time 3.84 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164860 kb
Host smart-db78edf8-8542-47b1-ae22-ec4d6344f076
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2422036393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2422036393
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1785339947
Short name T63
Test name
Test status
Simulation time 1523210000 ps
CPU time 5.57 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:46:02 PM PDT 24
Peak memory 164896 kb
Host smart-2a2b745b-1025-4a33-974c-d54e634f33c0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1785339947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1785339947
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3297509858
Short name T70
Test name
Test status
Simulation time 1307830000 ps
CPU time 3.38 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:57 PM PDT 24
Peak memory 164864 kb
Host smart-d5fd1e7a-c79d-4553-9ee3-5e44f1aa82a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297509858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3297509858
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2916518825
Short name T9
Test name
Test status
Simulation time 1488350000 ps
CPU time 4.72 seconds
Started Jun 02 01:45:50 PM PDT 24
Finished Jun 02 01:46:01 PM PDT 24
Peak memory 164876 kb
Host smart-12e48348-d5ab-4cd5-95a4-49cf335e73d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2916518825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2916518825
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4040271988
Short name T33
Test name
Test status
Simulation time 1564910000 ps
CPU time 4.41 seconds
Started Jun 02 01:45:50 PM PDT 24
Finished Jun 02 01:46:00 PM PDT 24
Peak memory 164848 kb
Host smart-8f38a2c5-af71-4e30-83ef-4ac95c7b13c0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040271988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4040271988
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2552161442
Short name T8
Test name
Test status
Simulation time 1535250000 ps
CPU time 5.04 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:46:01 PM PDT 24
Peak memory 164852 kb
Host smart-97fe62f0-0ba8-499e-8800-11804a3302c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552161442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2552161442
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.943636942
Short name T10
Test name
Test status
Simulation time 1391430000 ps
CPU time 3.94 seconds
Started Jun 02 01:45:49 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164852 kb
Host smart-b977dc49-6204-4512-b2ca-3a33ffb5a1a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=943636942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.943636942
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1067590049
Short name T62
Test name
Test status
Simulation time 1547670000 ps
CPU time 4.05 seconds
Started Jun 02 01:45:46 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164872 kb
Host smart-0249b670-9e38-453f-8cb3-9844a2845d81
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1067590049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1067590049
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.4047903892
Short name T58
Test name
Test status
Simulation time 1515950000 ps
CPU time 4.48 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:58 PM PDT 24
Peak memory 164860 kb
Host smart-dccff36d-83b0-424c-ac87-5ba3eb137528
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4047903892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.4047903892
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1300052023
Short name T43
Test name
Test status
Simulation time 1466770000 ps
CPU time 3.76 seconds
Started Jun 02 01:45:47 PM PDT 24
Finished Jun 02 01:45:56 PM PDT 24
Peak memory 164888 kb
Host smart-f12cc203-d429-4ee1-965e-a4016e7b655f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1300052023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1300052023
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2754627931
Short name T34
Test name
Test status
Simulation time 1298310000 ps
CPU time 4.12 seconds
Started Jun 02 01:45:44 PM PDT 24
Finished Jun 02 01:45:53 PM PDT 24
Peak memory 164836 kb
Host smart-2e370e3f-df10-4f94-bb08-0f4fbdf7e4cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2754627931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2754627931
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3405411126
Short name T40
Test name
Test status
Simulation time 1589070000 ps
CPU time 3.92 seconds
Started Jun 02 01:45:44 PM PDT 24
Finished Jun 02 01:45:53 PM PDT 24
Peak memory 164888 kb
Host smart-f4dfad70-f7a9-4e43-ba2d-2a21dd6aa7a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3405411126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3405411126
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3977730051
Short name T46
Test name
Test status
Simulation time 1356550000 ps
CPU time 3.05 seconds
Started Jun 02 01:45:42 PM PDT 24
Finished Jun 02 01:45:49 PM PDT 24
Peak memory 164840 kb
Host smart-98a62f1b-0e95-4b85-bc62-2c7722977ac0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977730051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3977730051
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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