Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3428897508
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.549584214
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1757499375

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2050337151
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.909087037
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2947074715
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4168868794
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2092167798
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3012634237
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3953545762
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.783922943
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1170207781
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2258456923
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2971391990
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.992197305
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2530761890
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.237856799
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3902645777
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.461957753
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4000795113
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3727811742
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3656385968
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2607317872
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3761135126
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2304933342
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3467699254
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2972743235
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3327558339
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1275554790
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2905997879
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3119990524
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1099886976
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.416356603
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1886422695
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1948745522
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2055309614
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3228020783
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3111456706
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3299445464
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3060566114
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.634707668
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.999337480
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3687490373
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1431345303
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3716239943
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2875510336
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1234807917
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2007278400
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3689762141
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3506641588
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3299641908
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1314086005
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2627764688
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.446714591
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.25524902
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4167454746
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3553425495
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2264949564
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4022195204
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3315935696
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1395628825
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3532365984
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.10418828
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3798959325
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3820209253
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.306028622
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1712937532
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1788392980
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2893973440
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.845437791
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2032842670
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1596951302
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2103158525
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1129314710
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2913883229
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3513308616
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1828971654
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3468214537
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2729935203
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.985625132
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2204593818
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.969055296
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2775324399
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1715141266
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2871249476
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2276470784
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.230312852
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1016184216
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3415097267
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.982017451
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3435107264
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.152537209
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1384444292
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2064707502
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1949671498
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1459332307
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3955602623
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.55189561
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.551119192
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1760749455
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3783351322
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1754164535
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3413966206
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2236069056
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.879146652
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4108104275
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3194850054
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3490230768
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3598067562
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1398854381
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3609427688
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3422634094
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1447521423
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.886084021
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2740271611
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.933311282
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3079786824
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1018234546
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3049202781
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2516900517
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4241248774
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1298780036
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2703889652
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1012853671
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3742244791
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4285650646
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4114558962
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1832350085
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1701559991
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1722669595
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2216786898
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.133020279
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4286677703
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1045637626
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4235378846
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2062943338
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1686554539
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.738043318
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2520911627
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3400779468
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2701997853
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3711811800
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.207836954
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.905935878
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1964149831
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2900785850
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.254886336
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3814391991
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3788887781
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3407412161
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2758020729
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1606119321
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3498951871
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1480579715
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2646215016
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3868827347
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3371769159
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1336963743
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2383280389
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3276531913
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2888994166
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4232647410
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1855573293
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.140220932
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1482863179
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2451811309
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2900696746
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1722545822
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3705121399
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1901295444
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4260116966
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.406168794
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2275210152
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3362066406
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3728461403
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3981052880
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3136273646
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3117875011
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1694665358
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.540311293
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1836141078
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.77024799
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2246174594
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2318011961
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.491032423
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1140881257
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1119402940
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3924398557
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3554895381
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.629718908
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3636491589
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2398417597
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4289691198
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3578140958
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.880066005
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1870311738
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2993731596
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.865810138
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2023612719
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.200356553



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3924398557 Jun 04 12:18:48 PM PDT 24 Jun 04 12:19:01 PM PDT 24 1467450000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2023612719 Jun 04 12:17:35 PM PDT 24 Jun 04 12:17:45 PM PDT 24 1577690000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1870311738 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:56 PM PDT 24 1477130000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1336963743 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:55 PM PDT 24 1562430000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1855573293 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1592710000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3428897508 Jun 04 12:17:54 PM PDT 24 Jun 04 12:18:06 PM PDT 24 1517390000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3117875011 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:55 PM PDT 24 1405730000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1694665358 Jun 04 12:22:28 PM PDT 24 Jun 04 12:22:36 PM PDT 24 1569410000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1606119321 Jun 04 12:17:50 PM PDT 24 Jun 04 12:17:59 PM PDT 24 1426510000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4232647410 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1387010000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1722545822 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:56 PM PDT 24 1468070000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3371769159 Jun 04 12:18:46 PM PDT 24 Jun 04 12:18:55 PM PDT 24 1505250000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2646215016 Jun 04 12:17:40 PM PDT 24 Jun 04 12:17:53 PM PDT 24 1568250000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2993731596 Jun 04 12:17:35 PM PDT 24 Jun 04 12:17:44 PM PDT 24 1519770000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3136273646 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1364630000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.629718908 Jun 04 12:17:49 PM PDT 24 Jun 04 12:17:59 PM PDT 24 1430390000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.880066005 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:55 PM PDT 24 1327170000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3276531913 Jun 04 12:22:27 PM PDT 24 Jun 04 12:22:39 PM PDT 24 1438750000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2888994166 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1455570000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1140881257 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:55 PM PDT 24 1450210000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.77024799 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1371410000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1119402940 Jun 04 12:17:49 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1319450000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.200356553 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:59 PM PDT 24 1504550000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.406168794 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1390370000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1901295444 Jun 04 12:17:37 PM PDT 24 Jun 04 12:17:52 PM PDT 24 1597770000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2900696746 Jun 04 12:17:37 PM PDT 24 Jun 04 12:17:51 PM PDT 24 1597650000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3868827347 Jun 04 12:17:39 PM PDT 24 Jun 04 12:17:52 PM PDT 24 1539410000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2451811309 Jun 04 12:18:22 PM PDT 24 Jun 04 12:18:31 PM PDT 24 1483750000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2383280389 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1390950000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3578140958 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1531390000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1836141078 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:59 PM PDT 24 1499550000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3362066406 Jun 04 12:17:39 PM PDT 24 Jun 04 12:17:52 PM PDT 24 1549890000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.491032423 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1464670000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2246174594 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1609830000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4289691198 Jun 04 12:17:37 PM PDT 24 Jun 04 12:17:50 PM PDT 24 1450550000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.140220932 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:56 PM PDT 24 1492790000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4260116966 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:55 PM PDT 24 1491770000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2398417597 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:56 PM PDT 24 1395070000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3705121399 Jun 04 12:17:38 PM PDT 24 Jun 04 12:17:51 PM PDT 24 1449730000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2318011961 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1364110000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.540311293 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:55 PM PDT 24 1493250000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3636491589 Jun 04 12:17:39 PM PDT 24 Jun 04 12:17:52 PM PDT 24 1611430000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.865810138 Jun 04 12:20:37 PM PDT 24 Jun 04 12:20:45 PM PDT 24 1597850000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3728461403 Jun 04 12:17:45 PM PDT 24 Jun 04 12:17:56 PM PDT 24 1417410000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3498951871 Jun 04 12:17:49 PM PDT 24 Jun 04 12:17:59 PM PDT 24 1601790000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3981052880 Jun 04 12:17:50 PM PDT 24 Jun 04 12:18:00 PM PDT 24 1611630000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3554895381 Jun 04 12:17:47 PM PDT 24 Jun 04 12:17:58 PM PDT 24 1336330000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2275210152 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1588490000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1480579715 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:57 PM PDT 24 1612150000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1482863179 Jun 04 12:17:46 PM PDT 24 Jun 04 12:17:56 PM PDT 24 1406530000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2905997879 Jun 04 12:22:28 PM PDT 24 Jun 04 12:56:49 PM PDT 24 336850950000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.999337480 Jun 04 12:17:38 PM PDT 24 Jun 04 12:59:22 PM PDT 24 336719270000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3228020783 Jun 04 12:22:15 PM PDT 24 Jun 04 12:51:13 PM PDT 24 336522050000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2875510336 Jun 04 12:18:55 PM PDT 24 Jun 04 12:56:11 PM PDT 24 336768070000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2304933342 Jun 04 12:21:00 PM PDT 24 Jun 04 12:57:05 PM PDT 24 336823950000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3299641908 Jun 04 12:18:02 PM PDT 24 Jun 04 12:55:58 PM PDT 24 336687990000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3953545762 Jun 04 12:17:45 PM PDT 24 Jun 04 12:47:36 PM PDT 24 336419070000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3727811742 Jun 04 12:23:27 PM PDT 24 Jun 04 12:48:59 PM PDT 24 336602710000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.416356603 Jun 04 12:20:45 PM PDT 24 Jun 04 01:01:29 PM PDT 24 336990290000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.549584214 Jun 04 12:17:45 PM PDT 24 Jun 04 12:48:12 PM PDT 24 336541490000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2607317872 Jun 04 12:24:13 PM PDT 24 Jun 04 12:51:01 PM PDT 24 337059470000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1431345303 Jun 04 12:22:28 PM PDT 24 Jun 04 01:08:33 PM PDT 24 336433310000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2007278400 Jun 04 12:17:45 PM PDT 24 Jun 04 12:56:07 PM PDT 24 336392610000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3687490373 Jun 04 12:23:56 PM PDT 24 Jun 04 12:58:10 PM PDT 24 336977730000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2971391990 Jun 04 12:22:15 PM PDT 24 Jun 04 12:51:43 PM PDT 24 337192410000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2258456923 Jun 04 12:17:44 PM PDT 24 Jun 04 12:47:25 PM PDT 24 336864250000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2055309614 Jun 04 12:23:32 PM PDT 24 Jun 04 12:57:17 PM PDT 24 336748190000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3327558339 Jun 04 12:22:37 PM PDT 24 Jun 04 12:49:35 PM PDT 24 336382750000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.909087037 Jun 04 12:18:48 PM PDT 24 Jun 04 12:57:31 PM PDT 24 336969030000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.461957753 Jun 04 12:22:27 PM PDT 24 Jun 04 12:58:50 PM PDT 24 336617750000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2050337151 Jun 04 12:18:01 PM PDT 24 Jun 04 12:54:57 PM PDT 24 336645650000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4168868794 Jun 04 12:17:45 PM PDT 24 Jun 04 12:48:33 PM PDT 24 336743330000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1275554790 Jun 04 12:21:05 PM PDT 24 Jun 04 12:53:54 PM PDT 24 336849970000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4000795113 Jun 04 12:21:55 PM PDT 24 Jun 04 01:04:50 PM PDT 24 337058750000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1234807917 Jun 04 12:23:56 PM PDT 24 Jun 04 12:59:03 PM PDT 24 336401630000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1948745522 Jun 04 12:23:32 PM PDT 24 Jun 04 12:56:53 PM PDT 24 336341230000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1099886976 Jun 04 12:17:39 PM PDT 24 Jun 04 01:04:50 PM PDT 24 337035510000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3902645777 Jun 04 12:21:19 PM PDT 24 Jun 04 12:53:20 PM PDT 24 337141710000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3689762141 Jun 04 12:18:03 PM PDT 24 Jun 04 12:55:43 PM PDT 24 336702430000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2092167798 Jun 04 12:21:19 PM PDT 24 Jun 04 12:55:13 PM PDT 24 336606930000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2972743235 Jun 04 12:22:30 PM PDT 24 Jun 04 12:56:16 PM PDT 24 337052150000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3467699254 Jun 04 12:17:47 PM PDT 24 Jun 04 12:51:15 PM PDT 24 336858110000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1314086005 Jun 04 12:17:46 PM PDT 24 Jun 04 12:46:01 PM PDT 24 337058450000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3060566114 Jun 04 12:23:33 PM PDT 24 Jun 04 12:58:11 PM PDT 24 336448070000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.634707668 Jun 04 12:23:29 PM PDT 24 Jun 04 12:57:00 PM PDT 24 336296650000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.783922943 Jun 04 12:22:27 PM PDT 24 Jun 04 12:59:03 PM PDT 24 336917150000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.992197305 Jun 04 12:17:45 PM PDT 24 Jun 04 12:55:14 PM PDT 24 336790990000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3111456706 Jun 04 12:23:55 PM PDT 24 Jun 04 12:59:25 PM PDT 24 336917830000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3761135126 Jun 04 12:22:37 PM PDT 24 Jun 04 12:49:21 PM PDT 24 336886410000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3506641588 Jun 04 12:17:46 PM PDT 24 Jun 04 12:47:47 PM PDT 24 336441630000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2530761890 Jun 04 12:18:48 PM PDT 24 Jun 04 12:56:44 PM PDT 24 336579750000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2947074715 Jun 04 12:17:45 PM PDT 24 Jun 04 12:55:31 PM PDT 24 336825610000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3716239943 Jun 04 12:19:22 PM PDT 24 Jun 04 01:00:56 PM PDT 24 337103090000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3656385968 Jun 04 12:23:19 PM PDT 24 Jun 04 12:48:51 PM PDT 24 336960630000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3299445464 Jun 04 12:23:38 PM PDT 24 Jun 04 12:49:50 PM PDT 24 336727330000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1170207781 Jun 04 12:18:48 PM PDT 24 Jun 04 12:57:16 PM PDT 24 336637110000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3012634237 Jun 04 12:21:18 PM PDT 24 Jun 04 12:55:28 PM PDT 24 336385970000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.237856799 Jun 04 12:22:27 PM PDT 24 Jun 04 12:58:28 PM PDT 24 336617190000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3119990524 Jun 04 12:23:41 PM PDT 24 Jun 04 12:51:05 PM PDT 24 336581430000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1886422695 Jun 04 12:21:55 PM PDT 24 Jun 04 12:52:46 PM PDT 24 336681790000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.254886336 Jun 04 12:45:03 PM PDT 24 Jun 04 12:45:13 PM PDT 24 1556090000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1012853671 Jun 04 12:45:25 PM PDT 24 Jun 04 12:45:35 PM PDT 24 1241850000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3422634094 Jun 04 12:45:14 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1619390000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.879146652 Jun 04 12:45:04 PM PDT 24 Jun 04 12:45:14 PM PDT 24 1560910000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1447521423 Jun 04 12:45:09 PM PDT 24 Jun 04 12:45:19 PM PDT 24 1546270000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1964149831 Jun 04 12:45:12 PM PDT 24 Jun 04 12:45:22 PM PDT 24 1514110000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4286677703 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:28 PM PDT 24 1572710000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2520911627 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1422330000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3609427688 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1464610000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3711811800 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:27 PM PDT 24 1585170000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1722669595 Jun 04 12:45:13 PM PDT 24 Jun 04 12:45:24 PM PDT 24 1638230000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2516900517 Jun 04 12:45:10 PM PDT 24 Jun 04 12:45:22 PM PDT 24 1558470000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1686554539 Jun 04 12:45:12 PM PDT 24 Jun 04 12:45:21 PM PDT 24 1501370000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1754164535 Jun 04 12:45:07 PM PDT 24 Jun 04 12:45:15 PM PDT 24 1226850000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1398854381 Jun 04 12:45:11 PM PDT 24 Jun 04 12:45:19 PM PDT 24 1467530000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4285650646 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1421930000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3194850054 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:27 PM PDT 24 1498590000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1018234546 Jun 04 12:45:12 PM PDT 24 Jun 04 12:45:22 PM PDT 24 1557590000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3742244791 Jun 04 12:45:03 PM PDT 24 Jun 04 12:45:14 PM PDT 24 1555690000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2236069056 Jun 04 12:45:04 PM PDT 24 Jun 04 12:45:14 PM PDT 24 1502910000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.738043318 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:25 PM PDT 24 1549570000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1298780036 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1409070000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.133020279 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:25 PM PDT 24 1311470000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4114558962 Jun 04 12:45:11 PM PDT 24 Jun 04 12:45:22 PM PDT 24 1598490000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4235378846 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1562450000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2062943338 Jun 04 12:45:10 PM PDT 24 Jun 04 12:45:20 PM PDT 24 1408010000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4108104275 Jun 04 12:45:12 PM PDT 24 Jun 04 12:45:24 PM PDT 24 1441110000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.886084021 Jun 04 12:45:08 PM PDT 24 Jun 04 12:45:20 PM PDT 24 1520810000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2758020729 Jun 04 12:45:03 PM PDT 24 Jun 04 12:45:12 PM PDT 24 1417150000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1701559991 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:27 PM PDT 24 1418750000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3788887781 Jun 04 12:45:03 PM PDT 24 Jun 04 12:45:13 PM PDT 24 1425430000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3598067562 Jun 04 12:45:14 PM PDT 24 Jun 04 12:45:23 PM PDT 24 1575930000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3413966206 Jun 04 12:45:04 PM PDT 24 Jun 04 12:45:16 PM PDT 24 1596570000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.933311282 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:25 PM PDT 24 1419590000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3490230768 Jun 04 12:45:10 PM PDT 24 Jun 04 12:45:20 PM PDT 24 1532690000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.905935878 Jun 04 12:45:09 PM PDT 24 Jun 04 12:45:21 PM PDT 24 1516330000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.207836954 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:24 PM PDT 24 1251090000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3079786824 Jun 04 12:45:12 PM PDT 24 Jun 04 12:45:26 PM PDT 24 1528230000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2900785850 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:24 PM PDT 24 1447710000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2740271611 Jun 04 12:45:11 PM PDT 24 Jun 04 12:45:22 PM PDT 24 1556290000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3407412161 Jun 04 12:45:09 PM PDT 24 Jun 04 12:45:20 PM PDT 24 1504950000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2703889652 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:27 PM PDT 24 1314990000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1045637626 Jun 04 12:45:10 PM PDT 24 Jun 04 12:45:20 PM PDT 24 1554910000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3400779468 Jun 04 12:45:13 PM PDT 24 Jun 04 12:45:22 PM PDT 24 1542350000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4241248774 Jun 04 12:45:14 PM PDT 24 Jun 04 12:45:24 PM PDT 24 1532890000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3814391991 Jun 04 12:45:06 PM PDT 24 Jun 04 12:45:18 PM PDT 24 1572150000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1832350085 Jun 04 12:45:11 PM PDT 24 Jun 04 12:45:18 PM PDT 24 1231930000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3049202781 Jun 04 12:45:13 PM PDT 24 Jun 04 12:45:23 PM PDT 24 1401950000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2216786898 Jun 04 12:45:14 PM PDT 24 Jun 04 12:45:25 PM PDT 24 1544170000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2701997853 Jun 04 12:45:12 PM PDT 24 Jun 04 12:45:21 PM PDT 24 1625450000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2276470784 Jun 04 12:24:00 PM PDT 24 Jun 04 12:49:17 PM PDT 24 337108550000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2775324399 Jun 04 12:17:54 PM PDT 24 Jun 04 01:02:28 PM PDT 24 336736250000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1715141266 Jun 04 12:23:33 PM PDT 24 Jun 04 12:58:33 PM PDT 24 337030030000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4167454746 Jun 04 12:18:56 PM PDT 24 Jun 04 01:02:17 PM PDT 24 336747110000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.25524902 Jun 04 12:18:40 PM PDT 24 Jun 04 01:04:53 PM PDT 24 336812870000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1757499375 Jun 04 12:23:56 PM PDT 24 Jun 04 12:58:22 PM PDT 24 336286830000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1016184216 Jun 04 12:23:29 PM PDT 24 Jun 04 12:56:59 PM PDT 24 336946090000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2893973440 Jun 04 12:21:51 PM PDT 24 Jun 04 01:00:51 PM PDT 24 336724990000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3532365984 Jun 04 12:22:30 PM PDT 24 Jun 04 12:55:29 PM PDT 24 336913150000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2729935203 Jun 04 12:23:14 PM PDT 24 Jun 04 12:52:44 PM PDT 24 336652510000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3783351322 Jun 04 12:18:40 PM PDT 24 Jun 04 01:05:31 PM PDT 24 336876110000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1788392980 Jun 04 12:18:48 PM PDT 24 Jun 04 12:57:16 PM PDT 24 336970530000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1129314710 Jun 04 12:19:20 PM PDT 24 Jun 04 01:03:11 PM PDT 24 336438890000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2871249476 Jun 04 12:17:37 PM PDT 24 Jun 04 01:01:25 PM PDT 24 336421150000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.230312852 Jun 04 12:17:49 PM PDT 24 Jun 04 01:01:48 PM PDT 24 336826330000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1949671498 Jun 04 12:23:47 PM PDT 24 Jun 04 12:58:20 PM PDT 24 336438030000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.982017451 Jun 04 12:18:10 PM PDT 24 Jun 04 01:04:37 PM PDT 24 336349430000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2913883229 Jun 04 12:22:05 PM PDT 24 Jun 04 01:08:18 PM PDT 24 336778330000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4022195204 Jun 04 12:18:40 PM PDT 24 Jun 04 01:04:17 PM PDT 24 336485890000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.969055296 Jun 04 12:17:45 PM PDT 24 Jun 04 12:55:42 PM PDT 24 336816170000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1596951302 Jun 04 12:18:46 PM PDT 24 Jun 04 12:49:18 PM PDT 24 337168050000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.551119192 Jun 04 12:18:09 PM PDT 24 Jun 04 01:04:48 PM PDT 24 336491590000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3468214537 Jun 04 12:17:52 PM PDT 24 Jun 04 12:59:36 PM PDT 24 337086490000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3955602623 Jun 04 12:18:09 PM PDT 24 Jun 04 01:04:30 PM PDT 24 336955410000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.306028622 Jun 04 12:22:28 PM PDT 24 Jun 04 12:56:49 PM PDT 24 336510450000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3315935696 Jun 04 12:22:27 PM PDT 24 Jun 04 12:58:56 PM PDT 24 336512230000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3553425495 Jun 04 12:18:49 PM PDT 24 Jun 04 12:56:10 PM PDT 24 336700250000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.845437791 Jun 04 12:21:19 PM PDT 24 Jun 04 12:55:23 PM PDT 24 336751330000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3798959325 Jun 04 12:22:27 PM PDT 24 Jun 04 12:58:35 PM PDT 24 336412790000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2204593818 Jun 04 12:23:56 PM PDT 24 Jun 04 12:59:14 PM PDT 24 336934190000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.446714591 Jun 04 12:18:24 PM PDT 24 Jun 04 01:02:51 PM PDT 24 336763050000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2264949564 Jun 04 12:22:28 PM PDT 24 Jun 04 12:58:26 PM PDT 24 336847170000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.55189561 Jun 04 12:19:31 PM PDT 24 Jun 04 12:52:02 PM PDT 24 336386730000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2627764688 Jun 04 12:23:30 PM PDT 24 Jun 04 12:57:48 PM PDT 24 336468990000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3820209253 Jun 04 12:17:52 PM PDT 24 Jun 04 01:02:26 PM PDT 24 336732630000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1712937532 Jun 04 12:18:49 PM PDT 24 Jun 04 12:56:27 PM PDT 24 336842170000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2103158525 Jun 04 12:23:34 PM PDT 24 Jun 04 12:50:49 PM PDT 24 336471790000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.10418828 Jun 04 12:18:49 PM PDT 24 Jun 04 12:56:20 PM PDT 24 336590930000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3415097267 Jun 04 12:23:30 PM PDT 24 Jun 04 12:57:02 PM PDT 24 336340890000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3435107264 Jun 04 12:23:55 PM PDT 24 Jun 04 12:58:29 PM PDT 24 336828110000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2032842670 Jun 04 12:22:37 PM PDT 24 Jun 04 12:49:32 PM PDT 24 337013510000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3513308616 Jun 04 12:17:47 PM PDT 24 Jun 04 12:51:07 PM PDT 24 337017170000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1459332307 Jun 04 12:22:33 PM PDT 24 Jun 04 01:00:41 PM PDT 24 336328490000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.985625132 Jun 04 12:23:56 PM PDT 24 Jun 04 12:58:27 PM PDT 24 336510230000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.152537209 Jun 04 12:22:00 PM PDT 24 Jun 04 01:00:24 PM PDT 24 336474230000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1395628825 Jun 04 12:22:28 PM PDT 24 Jun 04 12:56:49 PM PDT 24 336441470000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2064707502 Jun 04 12:23:56 PM PDT 24 Jun 04 12:59:14 PM PDT 24 336728890000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1828971654 Jun 04 12:23:14 PM PDT 24 Jun 04 12:52:40 PM PDT 24 336613150000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1760749455 Jun 04 12:18:40 PM PDT 24 Jun 04 01:05:30 PM PDT 24 336632690000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1384444292 Jun 04 12:17:47 PM PDT 24 Jun 04 12:51:07 PM PDT 24 336904150000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3428897508
Short name T9
Test name
Test status
Simulation time 1517390000 ps
CPU time 4.64 seconds
Started Jun 04 12:17:54 PM PDT 24
Finished Jun 04 12:18:06 PM PDT 24
Peak memory 164944 kb
Host smart-d6f55ba3-bb91-45cf-a37d-b1691c211056
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3428897508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3428897508
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.549584214
Short name T20
Test name
Test status
Simulation time 336541490000 ps
CPU time 736.15 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 160152 kb
Host smart-720637f8-593b-4970-bac4-8f9eb1baefc8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=549584214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.549584214
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1757499375
Short name T26
Test name
Test status
Simulation time 336286830000 ps
CPU time 818.81 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:58:22 PM PDT 24
Peak memory 160440 kb
Host smart-6f14a9ff-07da-43c1-8c19-b9884fe9d467
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1757499375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1757499375
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2050337151
Short name T81
Test name
Test status
Simulation time 336645650000 ps
CPU time 881.98 seconds
Started Jun 04 12:18:01 PM PDT 24
Finished Jun 04 12:54:57 PM PDT 24
Peak memory 160820 kb
Host smart-16c12eb6-a4e1-4d30-9961-bd30b004c87d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2050337151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2050337151
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.909087037
Short name T79
Test name
Test status
Simulation time 336969030000 ps
CPU time 940.23 seconds
Started Jun 04 12:18:48 PM PDT 24
Finished Jun 04 12:57:31 PM PDT 24
Peak memory 158480 kb
Host smart-725b14d5-45ea-49b4-a0c5-4bd0a41d5ab5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=909087037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.909087037
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2947074715
Short name T102
Test name
Test status
Simulation time 336825610000 ps
CPU time 914.64 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:55:31 PM PDT 24
Peak memory 160120 kb
Host smart-995f076d-1d8e-468e-91af-507d1cbaad60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2947074715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2947074715
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4168868794
Short name T82
Test name
Test status
Simulation time 336743330000 ps
CPU time 740.4 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:48:33 PM PDT 24
Peak memory 160212 kb
Host smart-b895ceab-fed6-44fc-b980-cd4eb1b038c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4168868794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4168868794
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2092167798
Short name T90
Test name
Test status
Simulation time 336606930000 ps
CPU time 830.87 seconds
Started Jun 04 12:21:19 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 160640 kb
Host smart-5b84071d-bd4e-46c7-aeaa-85ff935ef115
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2092167798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2092167798
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3012634237
Short name T107
Test name
Test status
Simulation time 336385970000 ps
CPU time 835.34 seconds
Started Jun 04 12:21:18 PM PDT 24
Finished Jun 04 12:55:28 PM PDT 24
Peak memory 160640 kb
Host smart-f0017d9f-a6e0-43a1-b10a-bbf485be3335
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3012634237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3012634237
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3953545762
Short name T17
Test name
Test status
Simulation time 336419070000 ps
CPU time 711.41 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:47:36 PM PDT 24
Peak memory 160156 kb
Host smart-ff284c6a-8f81-4aaa-be44-84fb8788c7a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3953545762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3953545762
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.783922943
Short name T96
Test name
Test status
Simulation time 336917150000 ps
CPU time 859.04 seconds
Started Jun 04 12:22:27 PM PDT 24
Finished Jun 04 12:59:03 PM PDT 24
Peak memory 158612 kb
Host smart-a0d08502-2ca9-4d09-bc1c-5e72b64d0904
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=783922943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.783922943
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1170207781
Short name T106
Test name
Test status
Simulation time 336637110000 ps
CPU time 928.83 seconds
Started Jun 04 12:18:48 PM PDT 24
Finished Jun 04 12:57:16 PM PDT 24
Peak memory 158512 kb
Host smart-1159be77-642c-462e-a7b2-f2b7bd623f0a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1170207781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1170207781
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2258456923
Short name T76
Test name
Test status
Simulation time 336864250000 ps
CPU time 722.04 seconds
Started Jun 04 12:17:44 PM PDT 24
Finished Jun 04 12:47:25 PM PDT 24
Peak memory 159736 kb
Host smart-1d1733ff-6837-4844-a23c-9a6d729c5a0b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2258456923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2258456923
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2971391990
Short name T75
Test name
Test status
Simulation time 337192410000 ps
CPU time 703.28 seconds
Started Jun 04 12:22:15 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 158996 kb
Host smart-0c8fe04c-de9b-4ff9-8b9c-414c3e588c0c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2971391990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2971391990
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.992197305
Short name T97
Test name
Test status
Simulation time 336790990000 ps
CPU time 907.77 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 159620 kb
Host smart-c7396951-8094-43a3-b4af-1c199b6fe8af
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=992197305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.992197305
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2530761890
Short name T101
Test name
Test status
Simulation time 336579750000 ps
CPU time 914.63 seconds
Started Jun 04 12:18:48 PM PDT 24
Finished Jun 04 12:56:44 PM PDT 24
Peak memory 158784 kb
Host smart-f94e5ee6-b345-4512-a7d3-8f25eb9a4519
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2530761890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2530761890
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.237856799
Short name T108
Test name
Test status
Simulation time 336617190000 ps
CPU time 838.82 seconds
Started Jun 04 12:22:27 PM PDT 24
Finished Jun 04 12:58:28 PM PDT 24
Peak memory 158772 kb
Host smart-50a7790f-beab-4503-9dd4-09670f519f84
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=237856799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.237856799
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3902645777
Short name T88
Test name
Test status
Simulation time 337141710000 ps
CPU time 780.37 seconds
Started Jun 04 12:21:19 PM PDT 24
Finished Jun 04 12:53:20 PM PDT 24
Peak memory 160640 kb
Host smart-ef3d5968-7988-4389-98d8-b6af24e7de12
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3902645777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3902645777
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.461957753
Short name T80
Test name
Test status
Simulation time 336617750000 ps
CPU time 850.66 seconds
Started Jun 04 12:22:27 PM PDT 24
Finished Jun 04 12:58:50 PM PDT 24
Peak memory 158432 kb
Host smart-1cf8ca3b-32c9-4bc1-b9a1-bb9651043785
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=461957753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.461957753
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4000795113
Short name T84
Test name
Test status
Simulation time 337058750000 ps
CPU time 1052.91 seconds
Started Jun 04 12:21:55 PM PDT 24
Finished Jun 04 01:04:50 PM PDT 24
Peak memory 160648 kb
Host smart-02f68e55-a611-4b31-b745-41c655c12e3e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4000795113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.4000795113
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3727811742
Short name T18
Test name
Test status
Simulation time 336602710000 ps
CPU time 632.19 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:48:59 PM PDT 24
Peak memory 160616 kb
Host smart-7b9e3962-ac79-4ee6-89f6-19d731db0856
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3727811742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3727811742
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3656385968
Short name T104
Test name
Test status
Simulation time 336960630000 ps
CPU time 616.6 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 160628 kb
Host smart-4fa5a993-c05d-4670-a1db-f2368221b02b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3656385968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3656385968
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2607317872
Short name T71
Test name
Test status
Simulation time 337059470000 ps
CPU time 658.82 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:51:01 PM PDT 24
Peak memory 160300 kb
Host smart-4e338fbd-35a1-4e6b-be35-03c7843ac46d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2607317872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2607317872
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3761135126
Short name T99
Test name
Test status
Simulation time 336886410000 ps
CPU time 643.17 seconds
Started Jun 04 12:22:37 PM PDT 24
Finished Jun 04 12:49:21 PM PDT 24
Peak memory 160596 kb
Host smart-f455ae10-abc2-44d2-bb16-b6bb50b76b69
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3761135126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3761135126
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2304933342
Short name T15
Test name
Test status
Simulation time 336823950000 ps
CPU time 866.57 seconds
Started Jun 04 12:21:00 PM PDT 24
Finished Jun 04 12:57:05 PM PDT 24
Peak memory 160640 kb
Host smart-4a4ab4d6-5416-4b17-9808-e09775fcae81
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2304933342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2304933342
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3467699254
Short name T92
Test name
Test status
Simulation time 336858110000 ps
CPU time 814.42 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 160692 kb
Host smart-23b9449b-c99d-47a1-9973-dd3eec507b62
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3467699254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3467699254
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2972743235
Short name T91
Test name
Test status
Simulation time 337052150000 ps
CPU time 814.37 seconds
Started Jun 04 12:22:30 PM PDT 24
Finished Jun 04 12:56:16 PM PDT 24
Peak memory 160436 kb
Host smart-c5c4548f-be8f-48a6-be41-1dddfbec2777
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2972743235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2972743235
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3327558339
Short name T78
Test name
Test status
Simulation time 336382750000 ps
CPU time 643.5 seconds
Started Jun 04 12:22:37 PM PDT 24
Finished Jun 04 12:49:35 PM PDT 24
Peak memory 160628 kb
Host smart-f880e2a2-6ecc-4d31-81be-847cc6d0d664
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3327558339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3327558339
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1275554790
Short name T83
Test name
Test status
Simulation time 336849970000 ps
CPU time 798.47 seconds
Started Jun 04 12:21:05 PM PDT 24
Finished Jun 04 12:53:54 PM PDT 24
Peak memory 160776 kb
Host smart-630e2bb2-4bb5-4627-b9d5-e74e83e3d66c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1275554790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1275554790
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2905997879
Short name T5
Test name
Test status
Simulation time 336850950000 ps
CPU time 827.07 seconds
Started Jun 04 12:22:28 PM PDT 24
Finished Jun 04 12:56:49 PM PDT 24
Peak memory 158696 kb
Host smart-5ff23169-c88e-4c02-8c63-18eee37a4be9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2905997879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2905997879
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3119990524
Short name T109
Test name
Test status
Simulation time 336581430000 ps
CPU time 674.08 seconds
Started Jun 04 12:23:41 PM PDT 24
Finished Jun 04 12:51:05 PM PDT 24
Peak memory 160636 kb
Host smart-42ba4fe0-7248-4b8b-b53e-8e2347cc12e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3119990524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3119990524
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1099886976
Short name T87
Test name
Test status
Simulation time 337035510000 ps
CPU time 1139.31 seconds
Started Jun 04 12:17:39 PM PDT 24
Finished Jun 04 01:04:50 PM PDT 24
Peak memory 160464 kb
Host smart-44ffe62c-64ef-49d6-bfbe-b5030a367b76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1099886976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1099886976
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.416356603
Short name T19
Test name
Test status
Simulation time 336990290000 ps
CPU time 976.66 seconds
Started Jun 04 12:20:45 PM PDT 24
Finished Jun 04 01:01:29 PM PDT 24
Peak memory 160648 kb
Host smart-e8fb3370-7182-46a7-b3d3-8cc0ab08ee79
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=416356603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.416356603
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1886422695
Short name T110
Test name
Test status
Simulation time 336681790000 ps
CPU time 756.54 seconds
Started Jun 04 12:21:55 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 160680 kb
Host smart-f6697f6a-790f-4c74-bf0f-e9c3a0db5390
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1886422695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1886422695
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1948745522
Short name T86
Test name
Test status
Simulation time 336341230000 ps
CPU time 772.11 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:56:53 PM PDT 24
Peak memory 159000 kb
Host smart-f75adb72-0b86-4688-8f09-cf480e296970
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1948745522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1948745522
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2055309614
Short name T77
Test name
Test status
Simulation time 336748190000 ps
CPU time 791.91 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:57:17 PM PDT 24
Peak memory 159092 kb
Host smart-843c7351-d92a-476a-a3ff-726ad8a9eae6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2055309614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2055309614
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3228020783
Short name T7
Test name
Test status
Simulation time 336522050000 ps
CPU time 690.19 seconds
Started Jun 04 12:22:15 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 159536 kb
Host smart-c6167bb8-2869-4dcc-9f8c-df7eb626f5fa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3228020783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3228020783
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3111456706
Short name T98
Test name
Test status
Simulation time 336917830000 ps
CPU time 854.57 seconds
Started Jun 04 12:23:55 PM PDT 24
Finished Jun 04 12:59:25 PM PDT 24
Peak memory 160260 kb
Host smart-5f636f87-2793-4bb1-9b6e-a83a1cfa1fab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3111456706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3111456706
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3299445464
Short name T105
Test name
Test status
Simulation time 336727330000 ps
CPU time 643.35 seconds
Started Jun 04 12:23:38 PM PDT 24
Finished Jun 04 12:49:50 PM PDT 24
Peak memory 159600 kb
Host smart-40c84ecc-561a-432f-829a-f30a1dd5eb15
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3299445464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3299445464
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3060566114
Short name T94
Test name
Test status
Simulation time 336448070000 ps
CPU time 814.83 seconds
Started Jun 04 12:23:33 PM PDT 24
Finished Jun 04 12:58:11 PM PDT 24
Peak memory 160240 kb
Host smart-5db94fb3-4ef1-44d7-b7bf-6e6e87bf7c74
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3060566114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3060566114
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.634707668
Short name T95
Test name
Test status
Simulation time 336296650000 ps
CPU time 791.97 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:57:00 PM PDT 24
Peak memory 160324 kb
Host smart-ad8e4303-999f-4c6f-9d9e-657811c08463
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=634707668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.634707668
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.999337480
Short name T6
Test name
Test status
Simulation time 336719270000 ps
CPU time 1010.04 seconds
Started Jun 04 12:17:38 PM PDT 24
Finished Jun 04 12:59:22 PM PDT 24
Peak memory 160496 kb
Host smart-947c8d6e-5781-485b-9689-3cf475dc6296
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=999337480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.999337480
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3687490373
Short name T74
Test name
Test status
Simulation time 336977730000 ps
CPU time 801.06 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:58:10 PM PDT 24
Peak memory 160444 kb
Host smart-e9befcb3-1379-449f-9e1d-84da226bed68
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3687490373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3687490373
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1431345303
Short name T72
Test name
Test status
Simulation time 336433310000 ps
CPU time 1098.2 seconds
Started Jun 04 12:22:28 PM PDT 24
Finished Jun 04 01:08:33 PM PDT 24
Peak memory 160612 kb
Host smart-d79c9878-dd2c-4dc1-a676-8c448701dc6f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1431345303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1431345303
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3716239943
Short name T103
Test name
Test status
Simulation time 337103090000 ps
CPU time 996.75 seconds
Started Jun 04 12:19:22 PM PDT 24
Finished Jun 04 01:00:56 PM PDT 24
Peak memory 160652 kb
Host smart-d88e4ddc-4dea-499f-986a-4fcc619a933b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3716239943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3716239943
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2875510336
Short name T14
Test name
Test status
Simulation time 336768070000 ps
CPU time 893.26 seconds
Started Jun 04 12:18:55 PM PDT 24
Finished Jun 04 12:56:11 PM PDT 24
Peak memory 160832 kb
Host smart-62a767a1-4018-4303-98c9-1369d95b91aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2875510336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2875510336
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1234807917
Short name T85
Test name
Test status
Simulation time 336401630000 ps
CPU time 842.32 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:59:03 PM PDT 24
Peak memory 160444 kb
Host smart-e217cc2a-cbef-434d-a5ab-8517eb1a2f47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1234807917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1234807917
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2007278400
Short name T73
Test name
Test status
Simulation time 336392610000 ps
CPU time 929.21 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:56:07 PM PDT 24
Peak memory 160112 kb
Host smart-e864152a-66d0-45c2-9107-07b9eab970c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2007278400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2007278400
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3689762141
Short name T89
Test name
Test status
Simulation time 336702430000 ps
CPU time 920.91 seconds
Started Jun 04 12:18:03 PM PDT 24
Finished Jun 04 12:55:43 PM PDT 24
Peak memory 160820 kb
Host smart-e84cd57c-7f4e-44cc-862b-d1ed945e8c09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3689762141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3689762141
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3506641588
Short name T100
Test name
Test status
Simulation time 336441630000 ps
CPU time 719.42 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 160148 kb
Host smart-9f645db7-782a-421e-9bf4-5dd6db4021f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3506641588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3506641588
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3299641908
Short name T16
Test name
Test status
Simulation time 336687990000 ps
CPU time 912.7 seconds
Started Jun 04 12:18:02 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 160820 kb
Host smart-4450464b-fcbe-44d9-937b-a8f283a208a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3299641908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3299641908
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1314086005
Short name T93
Test name
Test status
Simulation time 337058450000 ps
CPU time 690.76 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:46:01 PM PDT 24
Peak memory 160204 kb
Host smart-9a7b1aea-fc97-4b39-8596-6bb4c0212602
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1314086005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1314086005
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2627764688
Short name T184
Test name
Test status
Simulation time 336468990000 ps
CPU time 815.78 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:57:48 PM PDT 24
Peak memory 160348 kb
Host smart-1c0cc0a2-c313-40ab-967f-f32d40c1fc11
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2627764688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2627764688
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.446714591
Short name T181
Test name
Test status
Simulation time 336763050000 ps
CPU time 1060.71 seconds
Started Jun 04 12:18:24 PM PDT 24
Finished Jun 04 01:02:51 PM PDT 24
Peak memory 160648 kb
Host smart-eb53a962-5067-45cc-8111-5d81e437111a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=446714591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.446714591
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.25524902
Short name T25
Test name
Test status
Simulation time 336812870000 ps
CPU time 1086.72 seconds
Started Jun 04 12:18:40 PM PDT 24
Finished Jun 04 01:04:53 PM PDT 24
Peak memory 160416 kb
Host smart-04e3fc30-814f-4057-a1cd-48e4873f58ed
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=25524902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.25524902
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4167454746
Short name T24
Test name
Test status
Simulation time 336747110000 ps
CPU time 1032.68 seconds
Started Jun 04 12:18:56 PM PDT 24
Finished Jun 04 01:02:17 PM PDT 24
Peak memory 160652 kb
Host smart-9e561027-b76a-4554-992b-9c0f7a57a83a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4167454746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4167454746
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3553425495
Short name T177
Test name
Test status
Simulation time 336700250000 ps
CPU time 895.79 seconds
Started Jun 04 12:18:49 PM PDT 24
Finished Jun 04 12:56:10 PM PDT 24
Peak memory 159996 kb
Host smart-bc49b9c0-67bb-46da-8cac-7aafd4c4878d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3553425495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3553425495
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2264949564
Short name T182
Test name
Test status
Simulation time 336847170000 ps
CPU time 853.15 seconds
Started Jun 04 12:22:28 PM PDT 24
Finished Jun 04 12:58:26 PM PDT 24
Peak memory 160096 kb
Host smart-cf56d0f8-79d8-4ab5-9e1d-4233d5cb663a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2264949564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2264949564
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4022195204
Short name T169
Test name
Test status
Simulation time 336485890000 ps
CPU time 1063.77 seconds
Started Jun 04 12:18:40 PM PDT 24
Finished Jun 04 01:04:17 PM PDT 24
Peak memory 160612 kb
Host smart-3606242e-c005-4905-95dc-1af436cf57d3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4022195204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4022195204
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3315935696
Short name T176
Test name
Test status
Simulation time 336512230000 ps
CPU time 852.96 seconds
Started Jun 04 12:22:27 PM PDT 24
Finished Jun 04 12:58:56 PM PDT 24
Peak memory 158352 kb
Host smart-9a516467-8fd1-4494-8908-d30003d70399
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3315935696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3315935696
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1395628825
Short name T196
Test name
Test status
Simulation time 336441470000 ps
CPU time 819.52 seconds
Started Jun 04 12:22:28 PM PDT 24
Finished Jun 04 12:56:49 PM PDT 24
Peak memory 158524 kb
Host smart-ceab9ca9-a3d0-4e9f-b546-2ae35d1fd4c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1395628825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1395628825
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3532365984
Short name T29
Test name
Test status
Simulation time 336913150000 ps
CPU time 791.88 seconds
Started Jun 04 12:22:30 PM PDT 24
Finished Jun 04 12:55:29 PM PDT 24
Peak memory 160440 kb
Host smart-6497ec71-8468-4945-b55d-0bb1a3deecca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3532365984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3532365984
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.10418828
Short name T188
Test name
Test status
Simulation time 336590930000 ps
CPU time 906.75 seconds
Started Jun 04 12:18:49 PM PDT 24
Finished Jun 04 12:56:20 PM PDT 24
Peak memory 160100 kb
Host smart-610e2faf-2a39-422f-b654-c0d9bc96ac02
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=10418828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.10418828
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3798959325
Short name T179
Test name
Test status
Simulation time 336412790000 ps
CPU time 847.79 seconds
Started Jun 04 12:22:27 PM PDT 24
Finished Jun 04 12:58:35 PM PDT 24
Peak memory 159736 kb
Host smart-dee8b015-c712-46b7-a747-afccd4376daf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3798959325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3798959325
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3820209253
Short name T185
Test name
Test status
Simulation time 336732630000 ps
CPU time 1063.37 seconds
Started Jun 04 12:17:52 PM PDT 24
Finished Jun 04 01:02:26 PM PDT 24
Peak memory 160504 kb
Host smart-2fbab846-9985-4de0-8c97-e0e1c2b903ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3820209253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3820209253
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.306028622
Short name T175
Test name
Test status
Simulation time 336510450000 ps
CPU time 826.53 seconds
Started Jun 04 12:22:28 PM PDT 24
Finished Jun 04 12:56:49 PM PDT 24
Peak memory 158820 kb
Host smart-26141011-1936-40f9-8ea2-7927e0625399
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=306028622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.306028622
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1712937532
Short name T186
Test name
Test status
Simulation time 336842170000 ps
CPU time 912.29 seconds
Started Jun 04 12:18:49 PM PDT 24
Finished Jun 04 12:56:27 PM PDT 24
Peak memory 160060 kb
Host smart-91a57dd0-26cd-4fb2-816c-af8341da3033
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1712937532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1712937532
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1788392980
Short name T162
Test name
Test status
Simulation time 336970530000 ps
CPU time 928.98 seconds
Started Jun 04 12:18:48 PM PDT 24
Finished Jun 04 12:57:16 PM PDT 24
Peak memory 158708 kb
Host smart-a4cc0f0c-1d30-495a-a070-98c3e2afdf91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1788392980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1788392980
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2893973440
Short name T28
Test name
Test status
Simulation time 336724990000 ps
CPU time 968.76 seconds
Started Jun 04 12:21:51 PM PDT 24
Finished Jun 04 01:00:51 PM PDT 24
Peak memory 160636 kb
Host smart-263162d7-107b-4db1-9acc-3a78eb52a450
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2893973440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2893973440
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.845437791
Short name T178
Test name
Test status
Simulation time 336751330000 ps
CPU time 830.7 seconds
Started Jun 04 12:21:19 PM PDT 24
Finished Jun 04 12:55:23 PM PDT 24
Peak memory 160640 kb
Host smart-3ffbf135-1211-4ed4-8638-57fd37798f88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=845437791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.845437791
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2032842670
Short name T191
Test name
Test status
Simulation time 337013510000 ps
CPU time 646.93 seconds
Started Jun 04 12:22:37 PM PDT 24
Finished Jun 04 12:49:32 PM PDT 24
Peak memory 160636 kb
Host smart-5bfeda78-241e-4511-ae20-cbcdcb308494
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2032842670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2032842670
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1596951302
Short name T171
Test name
Test status
Simulation time 337168050000 ps
CPU time 732.65 seconds
Started Jun 04 12:18:46 PM PDT 24
Finished Jun 04 12:49:18 PM PDT 24
Peak memory 160680 kb
Host smart-d62902ed-8970-4c0a-9f52-39da2eeaa78a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1596951302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1596951302
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2103158525
Short name T187
Test name
Test status
Simulation time 336471790000 ps
CPU time 678.36 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:50:49 PM PDT 24
Peak memory 160720 kb
Host smart-4508fb04-681e-4255-b0e1-c69db2b01fd3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2103158525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2103158525
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1129314710
Short name T163
Test name
Test status
Simulation time 336438890000 ps
CPU time 1047.83 seconds
Started Jun 04 12:19:20 PM PDT 24
Finished Jun 04 01:03:11 PM PDT 24
Peak memory 160652 kb
Host smart-e081260c-48e3-40dd-a960-f02231e0800c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1129314710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1129314710
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2913883229
Short name T168
Test name
Test status
Simulation time 336778330000 ps
CPU time 1097.73 seconds
Started Jun 04 12:22:05 PM PDT 24
Finished Jun 04 01:08:18 PM PDT 24
Peak memory 160604 kb
Host smart-90f66e23-d183-4016-acd8-a4a921da6f59
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2913883229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2913883229
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3513308616
Short name T192
Test name
Test status
Simulation time 337017170000 ps
CPU time 797 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 160704 kb
Host smart-ad34ddcf-28f1-4687-a69a-77966a9865a8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3513308616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3513308616
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1828971654
Short name T198
Test name
Test status
Simulation time 336613150000 ps
CPU time 708.48 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:52:40 PM PDT 24
Peak memory 159608 kb
Host smart-65414108-aadf-400f-84e9-99687b58f550
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1828971654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1828971654
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3468214537
Short name T173
Test name
Test status
Simulation time 337086490000 ps
CPU time 1002.92 seconds
Started Jun 04 12:17:52 PM PDT 24
Finished Jun 04 12:59:36 PM PDT 24
Peak memory 160504 kb
Host smart-afe8cbbd-2ba7-4b07-8cd2-a7aeb4906a9c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3468214537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3468214537
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2729935203
Short name T30
Test name
Test status
Simulation time 336652510000 ps
CPU time 711.73 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:52:44 PM PDT 24
Peak memory 158944 kb
Host smart-01c85e86-9d22-4911-9d56-034eaa9a26d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729935203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2729935203
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.985625132
Short name T194
Test name
Test status
Simulation time 336510230000 ps
CPU time 825.81 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:58:27 PM PDT 24
Peak memory 160260 kb
Host smart-64717ed4-53c2-49d4-9c40-6760ccc34175
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=985625132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.985625132
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2204593818
Short name T180
Test name
Test status
Simulation time 336934190000 ps
CPU time 850.57 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:59:14 PM PDT 24
Peak memory 160448 kb
Host smart-2436c554-3be8-437a-8d9a-b5ee9c6f20c6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2204593818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2204593818
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.969055296
Short name T170
Test name
Test status
Simulation time 336816170000 ps
CPU time 926.18 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:55:42 PM PDT 24
Peak memory 159184 kb
Host smart-76cb4537-ec22-4fe5-b018-16314697ac21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=969055296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.969055296
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2775324399
Short name T22
Test name
Test status
Simulation time 336736250000 ps
CPU time 1066.1 seconds
Started Jun 04 12:17:54 PM PDT 24
Finished Jun 04 01:02:28 PM PDT 24
Peak memory 160504 kb
Host smart-76bbabf3-6c03-4215-a848-1174db8a1e63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2775324399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2775324399
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1715141266
Short name T23
Test name
Test status
Simulation time 337030030000 ps
CPU time 826.99 seconds
Started Jun 04 12:23:33 PM PDT 24
Finished Jun 04 12:58:33 PM PDT 24
Peak memory 160244 kb
Host smart-9641a13b-5d70-47f9-b247-373602b11ee6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1715141266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1715141266
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2871249476
Short name T164
Test name
Test status
Simulation time 336421150000 ps
CPU time 1078.68 seconds
Started Jun 04 12:17:37 PM PDT 24
Finished Jun 04 01:01:25 PM PDT 24
Peak memory 160504 kb
Host smart-8c9e87b8-9494-46bd-bc90-413bf3cc3da8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2871249476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2871249476
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2276470784
Short name T21
Test name
Test status
Simulation time 337108550000 ps
CPU time 616.12 seconds
Started Jun 04 12:24:00 PM PDT 24
Finished Jun 04 12:49:17 PM PDT 24
Peak memory 159516 kb
Host smart-2f959805-4b85-4808-88c9-4b10f9e466c6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2276470784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2276470784
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.230312852
Short name T165
Test name
Test status
Simulation time 336826330000 ps
CPU time 1048.14 seconds
Started Jun 04 12:17:49 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 160500 kb
Host smart-6635b1bc-ded4-455f-abeb-ca3b0c77cc88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=230312852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.230312852
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1016184216
Short name T27
Test name
Test status
Simulation time 336946090000 ps
CPU time 800.65 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:56:59 PM PDT 24
Peak memory 159660 kb
Host smart-17caa83e-ceb1-43d8-bca8-e4532c86120d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1016184216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1016184216
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3415097267
Short name T189
Test name
Test status
Simulation time 336340890000 ps
CPU time 793.6 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:57:02 PM PDT 24
Peak memory 160364 kb
Host smart-5744ff01-4616-4ae9-8f03-973c343c87f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3415097267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3415097267
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.982017451
Short name T167
Test name
Test status
Simulation time 336349430000 ps
CPU time 1071.27 seconds
Started Jun 04 12:18:10 PM PDT 24
Finished Jun 04 01:04:37 PM PDT 24
Peak memory 160608 kb
Host smart-c0f758ac-1fc6-430e-8673-b7730b7362b2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=982017451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.982017451
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3435107264
Short name T190
Test name
Test status
Simulation time 336828110000 ps
CPU time 836.61 seconds
Started Jun 04 12:23:55 PM PDT 24
Finished Jun 04 12:58:29 PM PDT 24
Peak memory 160264 kb
Host smart-354a0e08-4958-45aa-9351-9d965e90ce0b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3435107264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3435107264
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.152537209
Short name T195
Test name
Test status
Simulation time 336474230000 ps
CPU time 934.02 seconds
Started Jun 04 12:22:00 PM PDT 24
Finished Jun 04 01:00:24 PM PDT 24
Peak memory 160828 kb
Host smart-9f132708-2e63-433e-a24e-fbd60c8698c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=152537209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.152537209
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1384444292
Short name T200
Test name
Test status
Simulation time 336904150000 ps
CPU time 813.83 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 160704 kb
Host smart-dd7656b3-d87d-4982-81a4-3d60f948f448
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1384444292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1384444292
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2064707502
Short name T197
Test name
Test status
Simulation time 336728890000 ps
CPU time 846.98 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:59:14 PM PDT 24
Peak memory 160448 kb
Host smart-abd48098-9b10-48e3-98f9-a67ab2a326f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2064707502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2064707502
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1949671498
Short name T166
Test name
Test status
Simulation time 336438030000 ps
CPU time 821.26 seconds
Started Jun 04 12:23:47 PM PDT 24
Finished Jun 04 12:58:20 PM PDT 24
Peak memory 159768 kb
Host smart-5989a6e4-483c-4c34-bd5b-1c8116524d41
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1949671498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1949671498
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1459332307
Short name T193
Test name
Test status
Simulation time 336328490000 ps
CPU time 931.96 seconds
Started Jun 04 12:22:33 PM PDT 24
Finished Jun 04 01:00:41 PM PDT 24
Peak memory 160836 kb
Host smart-1320a5c5-0f5b-4f77-950b-72175cd30733
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1459332307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1459332307
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3955602623
Short name T174
Test name
Test status
Simulation time 336955410000 ps
CPU time 1064.98 seconds
Started Jun 04 12:18:09 PM PDT 24
Finished Jun 04 01:04:30 PM PDT 24
Peak memory 160604 kb
Host smart-79117b6a-cc38-436c-bceb-5dd939706f54
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3955602623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3955602623
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.55189561
Short name T183
Test name
Test status
Simulation time 336386730000 ps
CPU time 790.44 seconds
Started Jun 04 12:19:31 PM PDT 24
Finished Jun 04 12:52:02 PM PDT 24
Peak memory 160772 kb
Host smart-a93d2df1-b0af-4b7b-add4-43c953140ca3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=55189561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.55189561
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.551119192
Short name T172
Test name
Test status
Simulation time 336491590000 ps
CPU time 1096.57 seconds
Started Jun 04 12:18:09 PM PDT 24
Finished Jun 04 01:04:48 PM PDT 24
Peak memory 160608 kb
Host smart-8c962791-2e29-40b0-a7b0-7ef4c83ba0d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=551119192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.551119192
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1760749455
Short name T199
Test name
Test status
Simulation time 336632690000 ps
CPU time 1119.58 seconds
Started Jun 04 12:18:40 PM PDT 24
Finished Jun 04 01:05:30 PM PDT 24
Peak memory 160412 kb
Host smart-6b001a4c-51bf-41b8-9226-187fdfe1ece7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1760749455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1760749455
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3783351322
Short name T161
Test name
Test status
Simulation time 336876110000 ps
CPU time 1119.21 seconds
Started Jun 04 12:18:40 PM PDT 24
Finished Jun 04 01:05:31 PM PDT 24
Peak memory 160500 kb
Host smart-c42cfc1f-5e55-4284-a31e-c0dd28ae0cd1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783351322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3783351322
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1754164535
Short name T124
Test name
Test status
Simulation time 1226850000 ps
CPU time 3.48 seconds
Started Jun 04 12:45:07 PM PDT 24
Finished Jun 04 12:45:15 PM PDT 24
Peak memory 164836 kb
Host smart-002b263e-b3c9-43c8-94d6-b8a1b73860f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1754164535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1754164535
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3413966206
Short name T143
Test name
Test status
Simulation time 1596570000 ps
CPU time 4.83 seconds
Started Jun 04 12:45:04 PM PDT 24
Finished Jun 04 12:45:16 PM PDT 24
Peak memory 164696 kb
Host smart-a3745127-8cd0-4cc4-8026-24dc2ab07397
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3413966206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3413966206
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2236069056
Short name T130
Test name
Test status
Simulation time 1502910000 ps
CPU time 3.83 seconds
Started Jun 04 12:45:04 PM PDT 24
Finished Jun 04 12:45:14 PM PDT 24
Peak memory 164772 kb
Host smart-3a6f8f16-4a8e-4f97-be31-3d2c7297014f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236069056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2236069056
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.879146652
Short name T114
Test name
Test status
Simulation time 1560910000 ps
CPU time 4.06 seconds
Started Jun 04 12:45:04 PM PDT 24
Finished Jun 04 12:45:14 PM PDT 24
Peak memory 164780 kb
Host smart-f1fc7909-412f-4129-9b6b-a790f251f1ec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=879146652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.879146652
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4108104275
Short name T137
Test name
Test status
Simulation time 1441110000 ps
CPU time 4.56 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:24 PM PDT 24
Peak memory 164684 kb
Host smart-2b122ba2-2b5a-4b83-80e3-bc85d349c1fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108104275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.4108104275
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3194850054
Short name T127
Test name
Test status
Simulation time 1498590000 ps
CPU time 4.2 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 164788 kb
Host smart-bcd72784-62d7-44b0-a955-88427b97ec7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3194850054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3194850054
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3490230768
Short name T145
Test name
Test status
Simulation time 1532690000 ps
CPU time 3.92 seconds
Started Jun 04 12:45:10 PM PDT 24
Finished Jun 04 12:45:20 PM PDT 24
Peak memory 164752 kb
Host smart-ebf5b620-ee9f-4035-8352-96e503470b08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3490230768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3490230768
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3598067562
Short name T142
Test name
Test status
Simulation time 1575930000 ps
CPU time 4.07 seconds
Started Jun 04 12:45:14 PM PDT 24
Finished Jun 04 12:45:23 PM PDT 24
Peak memory 164844 kb
Host smart-1e763b3c-e552-4c70-a05a-da484e7de3c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3598067562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3598067562
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1398854381
Short name T125
Test name
Test status
Simulation time 1467530000 ps
CPU time 3.18 seconds
Started Jun 04 12:45:11 PM PDT 24
Finished Jun 04 12:45:19 PM PDT 24
Peak memory 164808 kb
Host smart-0d3b3eee-d398-4f85-aae8-76a8e42556cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398854381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1398854381
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3609427688
Short name T119
Test name
Test status
Simulation time 1464610000 ps
CPU time 4.58 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164856 kb
Host smart-59ef85bb-4811-499c-a3b9-59cff7736c0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3609427688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3609427688
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3422634094
Short name T113
Test name
Test status
Simulation time 1619390000 ps
CPU time 4.9 seconds
Started Jun 04 12:45:14 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164740 kb
Host smart-16595403-274f-483e-9be5-a537bd85df0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3422634094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3422634094
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1447521423
Short name T115
Test name
Test status
Simulation time 1546270000 ps
CPU time 4.08 seconds
Started Jun 04 12:45:09 PM PDT 24
Finished Jun 04 12:45:19 PM PDT 24
Peak memory 164740 kb
Host smart-6f1e9a50-a1fa-45d5-8987-f891f92fa5a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1447521423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1447521423
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.886084021
Short name T138
Test name
Test status
Simulation time 1520810000 ps
CPU time 4.74 seconds
Started Jun 04 12:45:08 PM PDT 24
Finished Jun 04 12:45:20 PM PDT 24
Peak memory 164772 kb
Host smart-d49b43d8-6b27-45cd-9c56-ca47549d1ed8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886084021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.886084021
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2740271611
Short name T150
Test name
Test status
Simulation time 1556290000 ps
CPU time 4.51 seconds
Started Jun 04 12:45:11 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 164848 kb
Host smart-41b9f51f-3a80-483f-8787-b30b7f1648ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2740271611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2740271611
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.933311282
Short name T144
Test name
Test status
Simulation time 1419590000 ps
CPU time 3.82 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:25 PM PDT 24
Peak memory 164808 kb
Host smart-500b630c-ebcd-4137-ae3c-3a104091d110
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933311282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.933311282
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3079786824
Short name T148
Test name
Test status
Simulation time 1528230000 ps
CPU time 6.07 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164796 kb
Host smart-157862e7-d1b0-4d11-b657-f5e2ec657a96
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3079786824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3079786824
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1018234546
Short name T128
Test name
Test status
Simulation time 1557590000 ps
CPU time 4.26 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 164836 kb
Host smart-44751e5b-cc0b-4087-905a-a8a10c6731b0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018234546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1018234546
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3049202781
Short name T158
Test name
Test status
Simulation time 1401950000 ps
CPU time 4.29 seconds
Started Jun 04 12:45:13 PM PDT 24
Finished Jun 04 12:45:23 PM PDT 24
Peak memory 164868 kb
Host smart-6b9a950a-aa39-48be-a9c4-4fe4162b8751
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3049202781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3049202781
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2516900517
Short name T122
Test name
Test status
Simulation time 1558470000 ps
CPU time 4.91 seconds
Started Jun 04 12:45:10 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 164804 kb
Host smart-efe9f24b-26c0-4641-9277-5ea20de18f0d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2516900517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2516900517
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4241248774
Short name T155
Test name
Test status
Simulation time 1532890000 ps
CPU time 3.85 seconds
Started Jun 04 12:45:14 PM PDT 24
Finished Jun 04 12:45:24 PM PDT 24
Peak memory 164836 kb
Host smart-f3e042ae-608e-45ed-9d30-c53ab94d726d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4241248774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4241248774
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1298780036
Short name T132
Test name
Test status
Simulation time 1409070000 ps
CPU time 4.56 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164856 kb
Host smart-39cc61f5-3459-43fc-a4c8-b533d7e837e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1298780036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1298780036
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2703889652
Short name T152
Test name
Test status
Simulation time 1314990000 ps
CPU time 4.14 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 164788 kb
Host smart-0cd4a08a-cf0c-4449-ae21-bebbcf95c307
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703889652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2703889652
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1012853671
Short name T112
Test name
Test status
Simulation time 1241850000 ps
CPU time 3.28 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 164808 kb
Host smart-b26b9514-febc-43cb-bf9b-6b81b1a93536
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1012853671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1012853671
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3742244791
Short name T129
Test name
Test status
Simulation time 1555690000 ps
CPU time 4.42 seconds
Started Jun 04 12:45:03 PM PDT 24
Finished Jun 04 12:45:14 PM PDT 24
Peak memory 164840 kb
Host smart-d0f9679e-5046-40f4-9a31-dc4933e2f6b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742244791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3742244791
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4285650646
Short name T126
Test name
Test status
Simulation time 1421930000 ps
CPU time 4.33 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164856 kb
Host smart-42bbc163-9682-4a6c-be06-735ecd111f8f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4285650646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.4285650646
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.4114558962
Short name T134
Test name
Test status
Simulation time 1598490000 ps
CPU time 4.74 seconds
Started Jun 04 12:45:11 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 164692 kb
Host smart-a4166cad-6a8c-4899-8769-82fe8faba433
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4114558962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.4114558962
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1832350085
Short name T157
Test name
Test status
Simulation time 1231930000 ps
CPU time 2.69 seconds
Started Jun 04 12:45:11 PM PDT 24
Finished Jun 04 12:45:18 PM PDT 24
Peak memory 164728 kb
Host smart-1b23ff39-2f85-4966-9133-cc887bab5798
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1832350085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1832350085
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1701559991
Short name T140
Test name
Test status
Simulation time 1418750000 ps
CPU time 4.85 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 164760 kb
Host smart-65e06df0-f841-4903-bb37-b0696dc5322d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1701559991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1701559991
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1722669595
Short name T121
Test name
Test status
Simulation time 1638230000 ps
CPU time 4.62 seconds
Started Jun 04 12:45:13 PM PDT 24
Finished Jun 04 12:45:24 PM PDT 24
Peak memory 164868 kb
Host smart-d03bdcd4-cc23-4f16-9fb0-137d1f509991
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722669595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1722669595
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2216786898
Short name T159
Test name
Test status
Simulation time 1544170000 ps
CPU time 4.64 seconds
Started Jun 04 12:45:14 PM PDT 24
Finished Jun 04 12:45:25 PM PDT 24
Peak memory 164788 kb
Host smart-2a588649-66bc-4dfa-b8e4-d6155924c9fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216786898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2216786898
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.133020279
Short name T133
Test name
Test status
Simulation time 1311470000 ps
CPU time 4.03 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:25 PM PDT 24
Peak memory 164848 kb
Host smart-12264bdb-9df6-4284-a3f0-382c919b9723
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=133020279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.133020279
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4286677703
Short name T117
Test name
Test status
Simulation time 1572710000 ps
CPU time 5.67 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:28 PM PDT 24
Peak memory 164760 kb
Host smart-9ee1e221-be8e-4786-a1e6-e11034d56b5c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4286677703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4286677703
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1045637626
Short name T153
Test name
Test status
Simulation time 1554910000 ps
CPU time 4.12 seconds
Started Jun 04 12:45:10 PM PDT 24
Finished Jun 04 12:45:20 PM PDT 24
Peak memory 164816 kb
Host smart-5e4c5a13-725c-4380-992a-ac9aea408697
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1045637626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1045637626
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4235378846
Short name T135
Test name
Test status
Simulation time 1562450000 ps
CPU time 3.79 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164816 kb
Host smart-23c583a2-37fc-4576-bfd3-7842b192913f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4235378846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.4235378846
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2062943338
Short name T136
Test name
Test status
Simulation time 1408010000 ps
CPU time 4.29 seconds
Started Jun 04 12:45:10 PM PDT 24
Finished Jun 04 12:45:20 PM PDT 24
Peak memory 164788 kb
Host smart-b5e02c48-6214-4555-9b62-af37574a12ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2062943338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2062943338
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1686554539
Short name T123
Test name
Test status
Simulation time 1501370000 ps
CPU time 3.75 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:21 PM PDT 24
Peak memory 164700 kb
Host smart-588eae21-a4b3-4dc3-8877-50b0a5af1caf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1686554539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1686554539
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.738043318
Short name T131
Test name
Test status
Simulation time 1549570000 ps
CPU time 3.53 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:25 PM PDT 24
Peak memory 164832 kb
Host smart-a7c4d141-1f5c-4adb-8d61-e502a3fb4993
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738043318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.738043318
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2520911627
Short name T118
Test name
Test status
Simulation time 1422330000 ps
CPU time 4.42 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 164788 kb
Host smart-34cb8b7b-7029-46bf-b9e1-f4c66a208c5a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2520911627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2520911627
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3400779468
Short name T154
Test name
Test status
Simulation time 1542350000 ps
CPU time 4.05 seconds
Started Jun 04 12:45:13 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 164828 kb
Host smart-ec0abeb3-878c-4eda-aeb9-335062c51831
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3400779468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3400779468
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2701997853
Short name T160
Test name
Test status
Simulation time 1625450000 ps
CPU time 3.78 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:21 PM PDT 24
Peak memory 164772 kb
Host smart-a940a7bc-301e-4dd3-864a-b284ac60b4a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2701997853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2701997853
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3711811800
Short name T120
Test name
Test status
Simulation time 1585170000 ps
CPU time 4.76 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 164788 kb
Host smart-7aead105-1de5-4079-a91e-6219610a3e00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3711811800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3711811800
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.207836954
Short name T147
Test name
Test status
Simulation time 1251090000 ps
CPU time 3.23 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:24 PM PDT 24
Peak memory 164748 kb
Host smart-7922bf96-834f-459e-ab16-7a3e46f26a10
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=207836954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.207836954
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.905935878
Short name T146
Test name
Test status
Simulation time 1516330000 ps
CPU time 5.09 seconds
Started Jun 04 12:45:09 PM PDT 24
Finished Jun 04 12:45:21 PM PDT 24
Peak memory 164768 kb
Host smart-f655e460-5233-49bb-9089-bbe8eacbbd0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905935878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.905935878
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1964149831
Short name T116
Test name
Test status
Simulation time 1514110000 ps
CPU time 3.75 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 164744 kb
Host smart-d04ef641-e761-4e4f-a7ea-1aada4a77b6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964149831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1964149831
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2900785850
Short name T149
Test name
Test status
Simulation time 1447710000 ps
CPU time 3.57 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:24 PM PDT 24
Peak memory 164692 kb
Host smart-c1619950-b57a-4b81-8e1c-aa1460e38ee5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2900785850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2900785850
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.254886336
Short name T111
Test name
Test status
Simulation time 1556090000 ps
CPU time 4.51 seconds
Started Jun 04 12:45:03 PM PDT 24
Finished Jun 04 12:45:13 PM PDT 24
Peak memory 164688 kb
Host smart-f93114bd-03ee-47ac-aefb-8e72a6ccf914
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254886336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.254886336
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3814391991
Short name T156
Test name
Test status
Simulation time 1572150000 ps
CPU time 5.03 seconds
Started Jun 04 12:45:06 PM PDT 24
Finished Jun 04 12:45:18 PM PDT 24
Peak memory 164716 kb
Host smart-18b636ef-c4ee-47c7-8891-e8c9c4acda4a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3814391991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3814391991
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3788887781
Short name T141
Test name
Test status
Simulation time 1425430000 ps
CPU time 3.77 seconds
Started Jun 04 12:45:03 PM PDT 24
Finished Jun 04 12:45:13 PM PDT 24
Peak memory 164752 kb
Host smart-b29f8e87-e17d-4c85-9f32-040d34a88cec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788887781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3788887781
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3407412161
Short name T151
Test name
Test status
Simulation time 1504950000 ps
CPU time 4.74 seconds
Started Jun 04 12:45:09 PM PDT 24
Finished Jun 04 12:45:20 PM PDT 24
Peak memory 164788 kb
Host smart-26429295-e6b8-4c76-ac32-5fefe86c9f95
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3407412161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3407412161
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2758020729
Short name T139
Test name
Test status
Simulation time 1417150000 ps
CPU time 3.12 seconds
Started Jun 04 12:45:03 PM PDT 24
Finished Jun 04 12:45:12 PM PDT 24
Peak memory 164796 kb
Host smart-214dc8b2-f6f9-46d2-8881-ca9b50bdcd77
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2758020729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2758020729
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1606119321
Short name T12
Test name
Test status
Simulation time 1426510000 ps
CPU time 4.15 seconds
Started Jun 04 12:17:50 PM PDT 24
Finished Jun 04 12:17:59 PM PDT 24
Peak memory 164924 kb
Host smart-4682bf52-7ef5-4d00-9466-72ac1bc48326
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1606119321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1606119321
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3498951871
Short name T65
Test name
Test status
Simulation time 1601790000 ps
CPU time 4.26 seconds
Started Jun 04 12:17:49 PM PDT 24
Finished Jun 04 12:17:59 PM PDT 24
Peak memory 164924 kb
Host smart-e650ac32-ed5c-44fc-9b6b-1a9fcf6e3c5f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3498951871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3498951871
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1480579715
Short name T69
Test name
Test status
Simulation time 1612150000 ps
CPU time 4.58 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164208 kb
Host smart-bdf30d92-7eab-44a6-a53a-5fc4a078ab18
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1480579715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1480579715
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2646215016
Short name T33
Test name
Test status
Simulation time 1568250000 ps
CPU time 5.53 seconds
Started Jun 04 12:17:40 PM PDT 24
Finished Jun 04 12:17:53 PM PDT 24
Peak memory 164532 kb
Host smart-4cc723c5-effb-464d-9cfd-00e735527bb6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2646215016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2646215016
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3868827347
Short name T47
Test name
Test status
Simulation time 1539410000 ps
CPU time 5.59 seconds
Started Jun 04 12:17:39 PM PDT 24
Finished Jun 04 12:17:52 PM PDT 24
Peak memory 164532 kb
Host smart-02559356-c95d-4dc7-a433-585c5bcd1982
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3868827347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3868827347
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3371769159
Short name T32
Test name
Test status
Simulation time 1505250000 ps
CPU time 3.7 seconds
Started Jun 04 12:18:46 PM PDT 24
Finished Jun 04 12:18:55 PM PDT 24
Peak memory 164844 kb
Host smart-ce073116-4e8f-43d0-94c1-f0c564d3e1db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371769159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3371769159
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1336963743
Short name T4
Test name
Test status
Simulation time 1562430000 ps
CPU time 4.53 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:55 PM PDT 24
Peak memory 163612 kb
Host smart-61247bbc-e9b2-4aa5-8b1f-34ebbdac80f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1336963743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1336963743
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2383280389
Short name T49
Test name
Test status
Simulation time 1390950000 ps
CPU time 4.55 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164704 kb
Host smart-f3b50783-f613-4729-8f9b-8f14cf54d27d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383280389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2383280389
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3276531913
Short name T38
Test name
Test status
Simulation time 1438750000 ps
CPU time 4.59 seconds
Started Jun 04 12:22:27 PM PDT 24
Finished Jun 04 12:22:39 PM PDT 24
Peak memory 162636 kb
Host smart-953aeb69-c6af-425d-b409-0eacf98c3bb7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3276531913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3276531913
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2888994166
Short name T39
Test name
Test status
Simulation time 1455570000 ps
CPU time 4.55 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164260 kb
Host smart-cc2d4d82-b786-42f5-bdc2-bac866715b53
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2888994166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2888994166
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.4232647410
Short name T13
Test name
Test status
Simulation time 1387010000 ps
CPU time 4.57 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164356 kb
Host smart-b40da486-87c4-4380-9484-1f41f2dc674b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4232647410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.4232647410
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1855573293
Short name T8
Test name
Test status
Simulation time 1592710000 ps
CPU time 4.81 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164180 kb
Host smart-683be141-0800-497d-a04c-7eae9c99583c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1855573293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1855573293
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.140220932
Short name T56
Test name
Test status
Simulation time 1492790000 ps
CPU time 4.85 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:56 PM PDT 24
Peak memory 162864 kb
Host smart-18afb11b-2964-48ce-8ec5-dea761d71d23
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=140220932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.140220932
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1482863179
Short name T70
Test name
Test status
Simulation time 1406530000 ps
CPU time 4.24 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:56 PM PDT 24
Peak memory 164224 kb
Host smart-a1a86217-5fe7-442e-878b-696ad8ea9e57
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1482863179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1482863179
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2451811309
Short name T48
Test name
Test status
Simulation time 1483750000 ps
CPU time 3.59 seconds
Started Jun 04 12:18:22 PM PDT 24
Finished Jun 04 12:18:31 PM PDT 24
Peak memory 164944 kb
Host smart-45253b04-c39f-4b94-9af0-10303e595b2b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2451811309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2451811309
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2900696746
Short name T46
Test name
Test status
Simulation time 1597650000 ps
CPU time 5.85 seconds
Started Jun 04 12:17:37 PM PDT 24
Finished Jun 04 12:17:51 PM PDT 24
Peak memory 164536 kb
Host smart-9b238ee1-3e8c-4614-b830-194e9d32d3e0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2900696746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2900696746
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1722545822
Short name T31
Test name
Test status
Simulation time 1468070000 ps
CPU time 4.47 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:56 PM PDT 24
Peak memory 164260 kb
Host smart-5d763d6e-b0bf-47ea-8092-7503fcce85a3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722545822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1722545822
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3705121399
Short name T59
Test name
Test status
Simulation time 1449730000 ps
CPU time 5.72 seconds
Started Jun 04 12:17:38 PM PDT 24
Finished Jun 04 12:17:51 PM PDT 24
Peak memory 164536 kb
Host smart-14fb611d-a1c4-45d1-a5a3-275266460565
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705121399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3705121399
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1901295444
Short name T45
Test name
Test status
Simulation time 1597770000 ps
CPU time 6.14 seconds
Started Jun 04 12:17:37 PM PDT 24
Finished Jun 04 12:17:52 PM PDT 24
Peak memory 164536 kb
Host smart-2d727bcb-b872-46a9-972f-8330cc58490a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1901295444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1901295444
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4260116966
Short name T57
Test name
Test status
Simulation time 1491770000 ps
CPU time 4.49 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:55 PM PDT 24
Peak memory 163584 kb
Host smart-c942ce90-2d36-4d74-a440-db04b2c34830
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4260116966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4260116966
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.406168794
Short name T44
Test name
Test status
Simulation time 1390370000 ps
CPU time 4.6 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164700 kb
Host smart-99782e3a-3d48-46c7-9f43-4e116fdc9c75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=406168794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.406168794
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2275210152
Short name T68
Test name
Test status
Simulation time 1588490000 ps
CPU time 4.88 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164260 kb
Host smart-ad900f4f-e013-44f6-97d6-b5f3c131451d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2275210152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2275210152
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3362066406
Short name T52
Test name
Test status
Simulation time 1549890000 ps
CPU time 5.6 seconds
Started Jun 04 12:17:39 PM PDT 24
Finished Jun 04 12:17:52 PM PDT 24
Peak memory 164508 kb
Host smart-d192b637-059f-4a2d-a537-6c5cdabcc745
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362066406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3362066406
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3728461403
Short name T64
Test name
Test status
Simulation time 1417410000 ps
CPU time 4.7 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:56 PM PDT 24
Peak memory 163248 kb
Host smart-06b77aa8-b06e-42d6-bfe7-fac03ad6319f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3728461403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3728461403
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3981052880
Short name T66
Test name
Test status
Simulation time 1611630000 ps
CPU time 4.46 seconds
Started Jun 04 12:17:50 PM PDT 24
Finished Jun 04 12:18:00 PM PDT 24
Peak memory 164944 kb
Host smart-7d1d698a-53ec-45d7-ae44-895b7a4b9d69
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981052880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3981052880
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3136273646
Short name T35
Test name
Test status
Simulation time 1364630000 ps
CPU time 4.46 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164700 kb
Host smart-16e98b7f-146d-4010-99ae-4158362f0885
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3136273646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3136273646
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3117875011
Short name T10
Test name
Test status
Simulation time 1405730000 ps
CPU time 4.17 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:55 PM PDT 24
Peak memory 164192 kb
Host smart-b2aa5f0f-e92e-4ef8-9096-5f1e1c6082af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3117875011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3117875011
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1694665358
Short name T11
Test name
Test status
Simulation time 1569410000 ps
CPU time 3.2 seconds
Started Jun 04 12:22:28 PM PDT 24
Finished Jun 04 12:22:36 PM PDT 24
Peak memory 164696 kb
Host smart-2f2de07f-1248-4482-9ae8-45dca2580311
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694665358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1694665358
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.540311293
Short name T61
Test name
Test status
Simulation time 1493250000 ps
CPU time 4.32 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:55 PM PDT 24
Peak memory 164316 kb
Host smart-bd9b2c3c-dd85-4bab-a4f1-42ea2a55c1ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=540311293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.540311293
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1836141078
Short name T51
Test name
Test status
Simulation time 1499550000 ps
CPU time 4.74 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:59 PM PDT 24
Peak memory 164316 kb
Host smart-8be7a4e7-dbfc-4cec-969b-03449f9064a0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1836141078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1836141078
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.77024799
Short name T41
Test name
Test status
Simulation time 1371410000 ps
CPU time 4.59 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164128 kb
Host smart-e9d36806-9fe0-43e5-bb4a-b6a901469f76
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=77024799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.77024799
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2246174594
Short name T54
Test name
Test status
Simulation time 1609830000 ps
CPU time 4.48 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164296 kb
Host smart-dfe9f133-5ba1-4cdf-a4f0-345c576529df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2246174594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2246174594
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2318011961
Short name T60
Test name
Test status
Simulation time 1364110000 ps
CPU time 4.31 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164248 kb
Host smart-7ca53652-fd96-4cab-9fc5-83cd22dd3dd0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2318011961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2318011961
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.491032423
Short name T53
Test name
Test status
Simulation time 1464670000 ps
CPU time 4.13 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164244 kb
Host smart-91574ebe-817e-4ec7-b1c3-70d6bbf8f818
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=491032423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.491032423
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1140881257
Short name T40
Test name
Test status
Simulation time 1450210000 ps
CPU time 4 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:55 PM PDT 24
Peak memory 164916 kb
Host smart-cd46dfb7-0c0b-4c15-b042-01325a8d8777
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1140881257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1140881257
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1119402940
Short name T42
Test name
Test status
Simulation time 1319450000 ps
CPU time 3.85 seconds
Started Jun 04 12:17:49 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164944 kb
Host smart-b5bd340a-6902-4657-9dba-89c25d2d58ed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1119402940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1119402940
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3924398557
Short name T1
Test name
Test status
Simulation time 1467450000 ps
CPU time 4.98 seconds
Started Jun 04 12:18:48 PM PDT 24
Finished Jun 04 12:19:01 PM PDT 24
Peak memory 162864 kb
Host smart-4b0b22c2-0717-452d-84ea-88ccad1e829d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3924398557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3924398557
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3554895381
Short name T67
Test name
Test status
Simulation time 1336330000 ps
CPU time 4.65 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:58 PM PDT 24
Peak memory 164636 kb
Host smart-56ab4e45-e3e3-4593-91b0-0f90d88f7015
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554895381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3554895381
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.629718908
Short name T36
Test name
Test status
Simulation time 1430390000 ps
CPU time 4.12 seconds
Started Jun 04 12:17:49 PM PDT 24
Finished Jun 04 12:17:59 PM PDT 24
Peak memory 164940 kb
Host smart-e2fd591e-40c5-4534-af7f-643b7e826e7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=629718908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.629718908
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3636491589
Short name T62
Test name
Test status
Simulation time 1611430000 ps
CPU time 5.64 seconds
Started Jun 04 12:17:39 PM PDT 24
Finished Jun 04 12:17:52 PM PDT 24
Peak memory 164504 kb
Host smart-8116933c-7415-48e9-8fdd-da63c2c22559
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3636491589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3636491589
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2398417597
Short name T58
Test name
Test status
Simulation time 1395070000 ps
CPU time 4.6 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:56 PM PDT 24
Peak memory 164168 kb
Host smart-6c5fc85f-9620-49b1-978d-f0ff2d99872f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2398417597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2398417597
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.4289691198
Short name T55
Test name
Test status
Simulation time 1450550000 ps
CPU time 5.52 seconds
Started Jun 04 12:17:37 PM PDT 24
Finished Jun 04 12:17:50 PM PDT 24
Peak memory 164536 kb
Host smart-5f9a3112-18a7-451c-a4e3-63ce631e74cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289691198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.4289691198
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3578140958
Short name T50
Test name
Test status
Simulation time 1531390000 ps
CPU time 4.95 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:57 PM PDT 24
Peak memory 164168 kb
Host smart-95e616c9-168d-4f62-abd7-27b3e819f520
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3578140958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3578140958
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.880066005
Short name T37
Test name
Test status
Simulation time 1327170000 ps
CPU time 3.77 seconds
Started Jun 04 12:17:46 PM PDT 24
Finished Jun 04 12:17:55 PM PDT 24
Peak memory 164248 kb
Host smart-99cfe852-95bf-4cc5-8ace-d18d9247cac5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=880066005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.880066005
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1870311738
Short name T3
Test name
Test status
Simulation time 1477130000 ps
CPU time 4.74 seconds
Started Jun 04 12:17:45 PM PDT 24
Finished Jun 04 12:17:56 PM PDT 24
Peak memory 163164 kb
Host smart-91cd84ea-1907-4426-a2ca-d119a0dbf9c3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1870311738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1870311738
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2993731596
Short name T34
Test name
Test status
Simulation time 1519770000 ps
CPU time 4.11 seconds
Started Jun 04 12:17:35 PM PDT 24
Finished Jun 04 12:17:44 PM PDT 24
Peak memory 164560 kb
Host smart-e4ad2cbd-5272-4c97-8aac-aad844bfc36e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2993731596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2993731596
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.865810138
Short name T63
Test name
Test status
Simulation time 1597850000 ps
CPU time 3.34 seconds
Started Jun 04 12:20:37 PM PDT 24
Finished Jun 04 12:20:45 PM PDT 24
Peak memory 164700 kb
Host smart-b9e1bab3-5cd5-44c1-b35c-1cf92b5d3edc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=865810138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.865810138
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2023612719
Short name T2
Test name
Test status
Simulation time 1577690000 ps
CPU time 4.38 seconds
Started Jun 04 12:17:35 PM PDT 24
Finished Jun 04 12:17:45 PM PDT 24
Peak memory 164560 kb
Host smart-e0f83691-e4b1-445d-be50-dc03328ab129
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2023612719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2023612719
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.200356553
Short name T43
Test name
Test status
Simulation time 1504550000 ps
CPU time 4.91 seconds
Started Jun 04 12:17:47 PM PDT 24
Finished Jun 04 12:17:59 PM PDT 24
Peak memory 164680 kb
Host smart-bb3122e8-b9b5-4d69-bf4e-fc9dc2c64606
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=200356553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.200356553
Directory /workspace/9.prim_lfsr_gal_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%