| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4161827789 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3792736645 | ||
| 98.31 | 3.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 15.00 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3021996391 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3306407729 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1403449089 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2269590885 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4017201439 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.556465234 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1416346412 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3007685684 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1230109539 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3540840940 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3792111795 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1121551788 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3352228624 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2313111352 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3666203204 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.255902615 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1900404132 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2983442851 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1507109750 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1801825113 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1486523630 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3357366681 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.898738077 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3435588401 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.219879875 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3782398889 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2651966955 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3397657102 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2649454050 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.347795409 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4212513946 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4087690058 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2922379186 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2456570489 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.57518825 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3357184056 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3920787192 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.61809235 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2957824158 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4052648023 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1088472745 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3966713785 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3652348198 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.983857585 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2952451412 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.564943128 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1871166498 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2005734494 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.864812733 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3292897014 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2798902335 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.955793696 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2940984168 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1781869694 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2968658954 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4111444262 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1281507709 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1112442654 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2730257979 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2279181101 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2170948644 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1597981593 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2992872519 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2121279199 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2740723095 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2616212276 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.657470953 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.79931396 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1776560860 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2358667462 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.447986790 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1138990102 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2988471235 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2497784531 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1577160365 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4266353750 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1627671857 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1123025463 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3750911806 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1419974790 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2304823311 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.759895410 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2794845844 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1523925511 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2576956534 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4000680042 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.510536055 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2881914959 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2135741928 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1751675054 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.322207019 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2739587033 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4075097731 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.103805658 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2150145094 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.733717901 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2045238244 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2027260714 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2699731985 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1114138391 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3052103422 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1447792232 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2679912772 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.285944900 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.589686140 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1613793225 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2973974069 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.322634018 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1207704332 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4102006607 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.940359968 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3365322734 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1632370868 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3421449296 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1130284898 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2971341980 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1445932385 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4087115819 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2570477733 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2294060396 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1158377283 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2805009487 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1144719017 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2295497897 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3480878085 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.615348871 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2907349842 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1061201271 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1307934255 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2924391947 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1161111807 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3854455863 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4219528978 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3839353742 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4070351367 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2343522555 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2484458383 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.33431017 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1243671801 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.967897169 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4192682665 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1949250163 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3950752641 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4226094263 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1941593294 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2395473396 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1382779102 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1164444059 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1378447106 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.394561393 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.846966557 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2299092560 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.153591421 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.516254179 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1051540695 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.864100965 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3157635386 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2829640121 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4205140610 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2531686665 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.653856211 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.148163000 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2306475357 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1668705638 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.711109392 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1835388467 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4071575690 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3165645600 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.10118605 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.675785349 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2503506397 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.961192816 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2632546349 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3671295387 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2144550484 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.350721514 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2924844793 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.845887390 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.336792614 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2905848322 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1906086081 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1561822485 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3829810342 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.958398373 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1250405771 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1401401232 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3180566206 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1244582745 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3238127214 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2783408748 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1595776497 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1617972114 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.234410882 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1151637259 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1761416071 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3050548823 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.278926797 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.297121582 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4071575690 | Jun 05 04:44:25 PM PDT 24 | Jun 05 04:44:36 PM PDT 24 | 1355830000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2531686665 | Jun 05 04:44:14 PM PDT 24 | Jun 05 04:44:22 PM PDT 24 | 1470190000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1561822485 | Jun 05 04:44:23 PM PDT 24 | Jun 05 04:44:35 PM PDT 24 | 1564710000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4161827789 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:24 PM PDT 24 | 1551830000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.958398373 | Jun 05 04:44:21 PM PDT 24 | Jun 05 04:44:33 PM PDT 24 | 1518310000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1401401232 | Jun 05 04:44:25 PM PDT 24 | Jun 05 04:44:37 PM PDT 24 | 1483330000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.711109392 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1402490000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2783408748 | Jun 05 04:44:28 PM PDT 24 | Jun 05 04:44:40 PM PDT 24 | 1220530000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.297121582 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:29 PM PDT 24 | 1627090000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1595776497 | Jun 05 04:44:28 PM PDT 24 | Jun 05 04:44:38 PM PDT 24 | 1275890000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2905848322 | Jun 05 04:44:21 PM PDT 24 | Jun 05 04:44:33 PM PDT 24 | 1436050000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1835388467 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:23 PM PDT 24 | 1523070000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2924844793 | Jun 05 04:44:20 PM PDT 24 | Jun 05 04:44:32 PM PDT 24 | 1528730000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2829640121 | Jun 05 04:44:13 PM PDT 24 | Jun 05 04:44:20 PM PDT 24 | 1454530000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.394561393 | Jun 05 04:44:17 PM PDT 24 | Jun 05 04:44:31 PM PDT 24 | 1433930000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.653856211 | Jun 05 04:44:17 PM PDT 24 | Jun 05 04:44:30 PM PDT 24 | 1505770000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3157635386 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:29 PM PDT 24 | 1428690000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3671295387 | Jun 05 04:44:20 PM PDT 24 | Jun 05 04:44:33 PM PDT 24 | 1603170000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1051540695 | Jun 05 04:44:14 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1604330000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.10118605 | Jun 05 04:44:18 PM PDT 24 | Jun 05 04:44:33 PM PDT 24 | 1560390000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2632546349 | Jun 05 04:44:18 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1559090000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4205140610 | Jun 05 04:44:08 PM PDT 24 | Jun 05 04:44:18 PM PDT 24 | 1403030000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.148163000 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:29 PM PDT 24 | 1498430000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.336792614 | Jun 05 04:44:24 PM PDT 24 | Jun 05 04:44:36 PM PDT 24 | 1617870000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1250405771 | Jun 05 04:44:20 PM PDT 24 | Jun 05 04:44:31 PM PDT 24 | 1141050000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.845887390 | Jun 05 04:44:20 PM PDT 24 | Jun 05 04:44:27 PM PDT 24 | 1014430000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1151637259 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1432290000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.234410882 | Jun 05 04:44:27 PM PDT 24 | Jun 05 04:44:42 PM PDT 24 | 1444950000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1244582745 | Jun 05 04:44:27 PM PDT 24 | Jun 05 04:44:35 PM PDT 24 | 1306410000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3165645600 | Jun 05 04:44:19 PM PDT 24 | Jun 05 04:44:32 PM PDT 24 | 1558170000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1761416071 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:29 PM PDT 24 | 1311210000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.846966557 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1486670000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.278926797 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:24 PM PDT 24 | 1466590000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3180566206 | Jun 05 04:44:30 PM PDT 24 | Jun 05 04:44:44 PM PDT 24 | 1547950000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3829810342 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1524670000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.153591421 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1443430000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3238127214 | Jun 05 04:44:27 PM PDT 24 | Jun 05 04:44:39 PM PDT 24 | 1508250000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.961192816 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:28 PM PDT 24 | 1398790000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2144550484 | Jun 05 04:44:26 PM PDT 24 | Jun 05 04:44:37 PM PDT 24 | 1397450000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3050548823 | Jun 05 04:44:14 PM PDT 24 | Jun 05 04:44:27 PM PDT 24 | 1463750000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2299092560 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:25 PM PDT 24 | 1463550000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.675785349 | Jun 05 04:44:19 PM PDT 24 | Jun 05 04:44:30 PM PDT 24 | 1131590000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.350721514 | Jun 05 04:44:22 PM PDT 24 | Jun 05 04:44:32 PM PDT 24 | 1396710000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2503506397 | Jun 05 04:44:20 PM PDT 24 | Jun 05 04:44:30 PM PDT 24 | 1463710000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2306475357 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:26 PM PDT 24 | 1299510000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.516254179 | Jun 05 04:44:17 PM PDT 24 | Jun 05 04:44:30 PM PDT 24 | 1473970000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.864100965 | Jun 05 04:44:16 PM PDT 24 | Jun 05 04:44:26 PM PDT 24 | 1321030000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1668705638 | Jun 05 04:44:15 PM PDT 24 | Jun 05 04:44:25 PM PDT 24 | 1305630000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1906086081 | Jun 05 04:44:19 PM PDT 24 | Jun 05 04:44:29 PM PDT 24 | 1424730000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1617972114 | Jun 05 04:44:28 PM PDT 24 | Jun 05 04:44:37 PM PDT 24 | 1566110000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2881914959 | Jun 05 05:07:36 PM PDT 24 | Jun 05 05:38:43 PM PDT 24 | 336365670000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1281507709 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:45:04 PM PDT 24 | 336540750000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3792736645 | Jun 05 05:07:25 PM PDT 24 | Jun 05 05:43:29 PM PDT 24 | 336458770000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2988471235 | Jun 05 05:07:16 PM PDT 24 | Jun 05 05:37:58 PM PDT 24 | 336951430000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.510536055 | Jun 05 05:07:38 PM PDT 24 | Jun 05 05:41:28 PM PDT 24 | 336973950000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2121279199 | Jun 05 05:07:21 PM PDT 24 | Jun 05 05:39:29 PM PDT 24 | 336679510000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2699731985 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:48:01 PM PDT 24 | 336627770000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4075097731 | Jun 05 05:07:37 PM PDT 24 | Jun 05 05:39:50 PM PDT 24 | 336909290000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2968658954 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:42:11 PM PDT 24 | 336966230000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1577160365 | Jun 05 05:07:30 PM PDT 24 | Jun 05 05:40:46 PM PDT 24 | 336938570000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4111444262 | Jun 05 05:07:21 PM PDT 24 | Jun 05 05:45:18 PM PDT 24 | 336966710000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2730257979 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:44:25 PM PDT 24 | 336355670000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2940984168 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:40:11 PM PDT 24 | 336392990000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.447986790 | Jun 05 05:07:25 PM PDT 24 | Jun 05 05:44:28 PM PDT 24 | 336530950000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2497784531 | Jun 05 05:07:32 PM PDT 24 | Jun 05 05:48:35 PM PDT 24 | 336834850000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2150145094 | Jun 05 05:07:14 PM PDT 24 | Jun 05 05:44:57 PM PDT 24 | 336946850000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2794845844 | Jun 05 05:07:31 PM PDT 24 | Jun 05 05:41:05 PM PDT 24 | 336778970000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1781869694 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:39:19 PM PDT 24 | 336976990000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1776560860 | Jun 05 05:07:26 PM PDT 24 | Jun 05 05:49:38 PM PDT 24 | 336561430000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2739587033 | Jun 05 05:07:37 PM PDT 24 | Jun 05 05:45:31 PM PDT 24 | 336581390000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.103805658 | Jun 05 05:07:36 PM PDT 24 | Jun 05 05:50:49 PM PDT 24 | 336861470000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2798902335 | Jun 05 05:07:16 PM PDT 24 | Jun 05 05:47:29 PM PDT 24 | 337164950000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2992872519 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:41:22 PM PDT 24 | 336792370000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4000680042 | Jun 05 05:07:32 PM PDT 24 | Jun 05 05:45:31 PM PDT 24 | 336688770000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2170948644 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:42:35 PM PDT 24 | 336535810000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2740723095 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:40:38 PM PDT 24 | 337063550000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2358667462 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:49:49 PM PDT 24 | 336328350000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.657470953 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:40:04 PM PDT 24 | 336399450000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1123025463 | Jun 05 05:07:31 PM PDT 24 | Jun 05 05:40:49 PM PDT 24 | 336512110000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.733717901 | Jun 05 05:07:19 PM PDT 24 | Jun 05 05:33:41 PM PDT 24 | 337046870000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2135741928 | Jun 05 05:07:39 PM PDT 24 | Jun 05 05:49:36 PM PDT 24 | 336404110000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2616212276 | Jun 05 05:07:25 PM PDT 24 | Jun 05 05:44:14 PM PDT 24 | 337023710000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2045238244 | Jun 05 05:07:16 PM PDT 24 | Jun 05 05:43:56 PM PDT 24 | 336597930000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.322207019 | Jun 05 05:07:35 PM PDT 24 | Jun 05 05:34:51 PM PDT 24 | 336336030000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.955793696 | Jun 05 05:07:14 PM PDT 24 | Jun 05 05:42:53 PM PDT 24 | 336347230000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1112442654 | Jun 05 05:07:22 PM PDT 24 | Jun 05 05:40:56 PM PDT 24 | 336344670000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2576956534 | Jun 05 05:07:30 PM PDT 24 | Jun 05 05:41:32 PM PDT 24 | 336573810000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4266353750 | Jun 05 05:07:34 PM PDT 24 | Jun 05 05:45:31 PM PDT 24 | 336859870000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1523925511 | Jun 05 05:07:17 PM PDT 24 | Jun 05 05:45:33 PM PDT 24 | 336424030000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1627671857 | Jun 05 05:07:30 PM PDT 24 | Jun 05 05:44:07 PM PDT 24 | 336945330000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.79931396 | Jun 05 05:07:24 PM PDT 24 | Jun 05 05:50:07 PM PDT 24 | 336984410000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1597981593 | Jun 05 05:07:19 PM PDT 24 | Jun 05 05:33:38 PM PDT 24 | 336624010000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1419974790 | Jun 05 05:07:30 PM PDT 24 | Jun 05 05:36:41 PM PDT 24 | 336869870000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2279181101 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:47:17 PM PDT 24 | 336845110000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.759895410 | Jun 05 05:07:30 PM PDT 24 | Jun 05 05:38:35 PM PDT 24 | 336456590000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3750911806 | Jun 05 05:07:31 PM PDT 24 | Jun 05 05:49:04 PM PDT 24 | 336563170000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1751675054 | Jun 05 05:07:36 PM PDT 24 | Jun 05 05:44:56 PM PDT 24 | 337082990000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2304823311 | Jun 05 05:07:30 PM PDT 24 | Jun 05 05:42:43 PM PDT 24 | 336466230000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1138990102 | Jun 05 05:07:32 PM PDT 24 | Jun 05 05:40:52 PM PDT 24 | 336307230000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2027260714 | Jun 05 05:07:23 PM PDT 24 | Jun 05 05:38:13 PM PDT 24 | 336654730000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3920787192 | Jun 05 05:08:04 PM PDT 24 | Jun 05 05:43:43 PM PDT 24 | 337042490000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.564943128 | Jun 05 05:07:36 PM PDT 24 | Jun 05 05:36:59 PM PDT 24 | 336686910000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1121551788 | Jun 05 05:07:44 PM PDT 24 | Jun 05 05:34:55 PM PDT 24 | 336646490000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3292897014 | Jun 05 05:07:47 PM PDT 24 | Jun 05 05:42:51 PM PDT 24 | 336692070000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1486523630 | Jun 05 05:07:53 PM PDT 24 | Jun 05 05:37:44 PM PDT 24 | 336676570000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3007685684 | Jun 05 05:07:46 PM PDT 24 | Jun 05 05:40:43 PM PDT 24 | 336304730000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3021996391 | Jun 05 05:07:47 PM PDT 24 | Jun 05 05:40:34 PM PDT 24 | 336833350000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1230109539 | Jun 05 05:07:46 PM PDT 24 | Jun 05 05:42:17 PM PDT 24 | 336367090000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.898738077 | Jun 05 05:07:53 PM PDT 24 | Jun 05 05:40:58 PM PDT 24 | 336488310000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.61809235 | Jun 05 05:08:01 PM PDT 24 | Jun 05 05:45:32 PM PDT 24 | 336331330000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2957824158 | Jun 05 05:08:07 PM PDT 24 | Jun 05 05:41:35 PM PDT 24 | 336841210000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3792111795 | Jun 05 05:07:46 PM PDT 24 | Jun 05 05:42:24 PM PDT 24 | 336518450000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4052648023 | Jun 05 05:08:15 PM PDT 24 | Jun 05 05:40:56 PM PDT 24 | 336570910000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2269590885 | Jun 05 05:07:47 PM PDT 24 | Jun 05 05:48:40 PM PDT 24 | 337048370000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1900404132 | Jun 05 05:07:52 PM PDT 24 | Jun 05 05:40:13 PM PDT 24 | 336565070000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1801825113 | Jun 05 05:07:55 PM PDT 24 | Jun 05 05:46:08 PM PDT 24 | 336660410000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4087690058 | Jun 05 05:08:00 PM PDT 24 | Jun 05 05:41:12 PM PDT 24 | 337007570000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3966713785 | Jun 05 05:08:08 PM PDT 24 | Jun 05 05:38:56 PM PDT 24 | 336582830000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.864812733 | Jun 05 05:07:46 PM PDT 24 | Jun 05 05:42:22 PM PDT 24 | 336632250000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1871166498 | Jun 05 05:07:47 PM PDT 24 | Jun 05 05:43:07 PM PDT 24 | 336679490000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2651966955 | Jun 05 05:08:01 PM PDT 24 | Jun 05 05:50:51 PM PDT 24 | 337005090000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3652348198 | Jun 05 05:08:15 PM PDT 24 | Jun 05 05:36:38 PM PDT 24 | 336632410000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2922379186 | Jun 05 05:08:00 PM PDT 24 | Jun 05 05:38:20 PM PDT 24 | 336660190000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3357184056 | Jun 05 05:07:59 PM PDT 24 | Jun 05 05:42:52 PM PDT 24 | 336571930000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.57518825 | Jun 05 05:07:38 PM PDT 24 | Jun 05 05:41:21 PM PDT 24 | 336511970000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2649454050 | Jun 05 05:08:03 PM PDT 24 | Jun 05 05:43:30 PM PDT 24 | 336401650000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4017201439 | Jun 05 05:07:48 PM PDT 24 | Jun 05 05:47:41 PM PDT 24 | 336486810000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3352228624 | Jun 05 05:07:37 PM PDT 24 | Jun 05 05:48:41 PM PDT 24 | 336728350000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2456570489 | Jun 05 05:08:03 PM PDT 24 | Jun 05 05:43:47 PM PDT 24 | 337060890000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3435588401 | Jun 05 05:07:40 PM PDT 24 | Jun 05 05:49:45 PM PDT 24 | 337127770000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2983442851 | Jun 05 05:07:52 PM PDT 24 | Jun 05 05:39:38 PM PDT 24 | 336344950000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3397657102 | Jun 05 05:08:01 PM PDT 24 | Jun 05 05:40:43 PM PDT 24 | 336919330000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.556465234 | Jun 05 05:07:46 PM PDT 24 | Jun 05 05:46:09 PM PDT 24 | 336432590000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.983857585 | Jun 05 05:08:10 PM PDT 24 | Jun 05 05:45:35 PM PDT 24 | 337046210000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.219879875 | Jun 05 05:07:55 PM PDT 24 | Jun 05 05:46:02 PM PDT 24 | 336456550000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1507109750 | Jun 05 05:07:53 PM PDT 24 | Jun 05 05:50:50 PM PDT 24 | 336728370000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1403449089 | Jun 05 05:07:40 PM PDT 24 | Jun 05 05:49:48 PM PDT 24 | 336719830000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1416346412 | Jun 05 05:07:49 PM PDT 24 | Jun 05 05:50:19 PM PDT 24 | 336363470000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3306407729 | Jun 05 05:07:38 PM PDT 24 | Jun 05 05:42:53 PM PDT 24 | 336511510000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3782398889 | Jun 05 05:07:52 PM PDT 24 | Jun 05 05:42:09 PM PDT 24 | 336513130000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4212513946 | Jun 05 05:08:01 PM PDT 24 | Jun 05 05:44:25 PM PDT 24 | 336570010000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2313111352 | Jun 05 05:07:45 PM PDT 24 | Jun 05 05:39:45 PM PDT 24 | 336389950000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2952451412 | Jun 05 05:08:08 PM PDT 24 | Jun 05 05:51:03 PM PDT 24 | 337019290000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2005734494 | Jun 05 05:07:47 PM PDT 24 | Jun 05 05:47:52 PM PDT 24 | 336959690000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3357366681 | Jun 05 05:07:56 PM PDT 24 | Jun 05 05:46:04 PM PDT 24 | 336867330000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3540840940 | Jun 05 05:07:47 PM PDT 24 | Jun 05 05:38:20 PM PDT 24 | 336445790000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.255902615 | Jun 05 05:07:52 PM PDT 24 | Jun 05 05:47:57 PM PDT 24 | 336535150000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.347795409 | Jun 05 05:08:00 PM PDT 24 | Jun 05 05:41:55 PM PDT 24 | 336836490000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1088472745 | Jun 05 05:08:09 PM PDT 24 | Jun 05 05:42:13 PM PDT 24 | 336996110000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3666203204 | Jun 05 05:07:53 PM PDT 24 | Jun 05 05:45:20 PM PDT 24 | 336545030000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2343522555 | Jun 05 05:13:06 PM PDT 24 | Jun 05 05:13:17 PM PDT 24 | 1507130000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1613793225 | Jun 05 05:12:52 PM PDT 24 | Jun 05 05:13:03 PM PDT 24 | 1366030000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1445932385 | Jun 05 05:13:01 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1488270000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1941593294 | Jun 05 05:12:52 PM PDT 24 | Jun 05 05:13:06 PM PDT 24 | 1556950000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1447792232 | Jun 05 05:12:53 PM PDT 24 | Jun 05 05:13:07 PM PDT 24 | 1471330000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1114138391 | Jun 05 05:12:45 PM PDT 24 | Jun 05 05:12:58 PM PDT 24 | 1540250000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.940359968 | Jun 05 05:13:01 PM PDT 24 | Jun 05 05:13:13 PM PDT 24 | 1324230000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2395473396 | Jun 05 05:12:53 PM PDT 24 | Jun 05 05:13:04 PM PDT 24 | 1469970000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2295497897 | Jun 05 05:13:02 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1498490000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1632370868 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:15 PM PDT 24 | 1583210000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1382779102 | Jun 05 05:12:53 PM PDT 24 | Jun 05 05:13:07 PM PDT 24 | 1593150000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2924391947 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1474610000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2907349842 | Jun 05 05:13:01 PM PDT 24 | Jun 05 05:13:11 PM PDT 24 | 1469430000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3052103422 | Jun 05 05:12:46 PM PDT 24 | Jun 05 05:12:56 PM PDT 24 | 1474150000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1164444059 | Jun 05 05:12:52 PM PDT 24 | Jun 05 05:13:00 PM PDT 24 | 1364990000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2971341980 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1450170000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.589686140 | Jun 05 05:12:54 PM PDT 24 | Jun 05 05:13:06 PM PDT 24 | 1525590000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2294060396 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:10 PM PDT 24 | 1565250000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.615348871 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:14 PM PDT 24 | 1481930000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.33431017 | Jun 05 05:13:06 PM PDT 24 | Jun 05 05:13:16 PM PDT 24 | 1246150000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1307934255 | Jun 05 05:13:01 PM PDT 24 | Jun 05 05:13:14 PM PDT 24 | 1499110000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3421449296 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:11 PM PDT 24 | 1441570000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.322634018 | Jun 05 05:12:54 PM PDT 24 | Jun 05 05:13:04 PM PDT 24 | 1447690000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1061201271 | Jun 05 05:12:59 PM PDT 24 | Jun 05 05:13:10 PM PDT 24 | 1455010000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1243671801 | Jun 05 05:13:08 PM PDT 24 | Jun 05 05:13:18 PM PDT 24 | 1151430000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4219528978 | Jun 05 05:13:09 PM PDT 24 | Jun 05 05:13:22 PM PDT 24 | 1335030000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4226094263 | Jun 05 05:13:06 PM PDT 24 | Jun 05 05:13:15 PM PDT 24 | 1199750000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1949250163 | Jun 05 05:13:09 PM PDT 24 | Jun 05 05:13:22 PM PDT 24 | 1388790000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2973974069 | Jun 05 05:12:52 PM PDT 24 | Jun 05 05:13:02 PM PDT 24 | 1231790000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.285944900 | Jun 05 05:12:53 PM PDT 24 | Jun 05 05:13:00 PM PDT 24 | 1123490000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4192682665 | Jun 05 05:13:08 PM PDT 24 | Jun 05 05:13:21 PM PDT 24 | 1593870000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4070351367 | Jun 05 05:13:09 PM PDT 24 | Jun 05 05:13:19 PM PDT 24 | 1543190000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4087115819 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1443610000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1130284898 | Jun 05 05:13:01 PM PDT 24 | Jun 05 05:13:13 PM PDT 24 | 1476850000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1161111807 | Jun 05 05:13:02 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1599470000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4102006607 | Jun 05 05:12:54 PM PDT 24 | Jun 05 05:13:04 PM PDT 24 | 1398690000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1378447106 | Jun 05 05:12:54 PM PDT 24 | Jun 05 05:13:07 PM PDT 24 | 1560210000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1207704332 | Jun 05 05:12:51 PM PDT 24 | Jun 05 05:12:58 PM PDT 24 | 1223550000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2484458383 | Jun 05 05:13:06 PM PDT 24 | Jun 05 05:13:16 PM PDT 24 | 1170910000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3839353742 | Jun 05 05:12:51 PM PDT 24 | Jun 05 05:13:05 PM PDT 24 | 1603670000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.967897169 | Jun 05 05:13:06 PM PDT 24 | Jun 05 05:13:17 PM PDT 24 | 1318050000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3950752641 | Jun 05 05:13:08 PM PDT 24 | Jun 05 05:13:18 PM PDT 24 | 1276450000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2679912772 | Jun 05 05:12:52 PM PDT 24 | Jun 05 05:13:06 PM PDT 24 | 1527370000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2570477733 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:10 PM PDT 24 | 1366770000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3480878085 | Jun 05 05:13:00 PM PDT 24 | Jun 05 05:13:12 PM PDT 24 | 1496830000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3854455863 | Jun 05 05:13:08 PM PDT 24 | Jun 05 05:13:20 PM PDT 24 | 1358630000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3365322734 | Jun 05 05:12:45 PM PDT 24 | Jun 05 05:12:58 PM PDT 24 | 1609210000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1144719017 | Jun 05 05:12:45 PM PDT 24 | Jun 05 05:12:58 PM PDT 24 | 1478710000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2805009487 | Jun 05 05:13:01 PM PDT 24 | Jun 05 05:13:14 PM PDT 24 | 1499070000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1158377283 | Jun 05 05:12:59 PM PDT 24 | Jun 05 05:13:10 PM PDT 24 | 1448770000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4161827789 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1551830000 ps |
| CPU time | 3.43 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:24 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-3ee704a7-2f89-4cbf-b882-289828c80741 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4161827789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.4161827789 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3792736645 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336458770000 ps |
| CPU time | 865.92 seconds |
| Started | Jun 05 05:07:25 PM PDT 24 |
| Finished | Jun 05 05:43:29 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-f7f5c1a2-c288-42cd-ad24-894bd9d9fbe3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3792736645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3792736645 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3021996391 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 336833350000 ps |
| CPU time | 786.82 seconds |
| Started | Jun 05 05:07:47 PM PDT 24 |
| Finished | Jun 05 05:40:34 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-5894dfce-9d43-4d41-90b7-6c02ad44e448 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3021996391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3021996391 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3306407729 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336511510000 ps |
| CPU time | 845.39 seconds |
| Started | Jun 05 05:07:38 PM PDT 24 |
| Finished | Jun 05 05:42:53 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-06ac1d9d-8716-4646-865d-930be2e7e964 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3306407729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3306407729 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1403449089 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336719830000 ps |
| CPU time | 993.27 seconds |
| Started | Jun 05 05:07:40 PM PDT 24 |
| Finished | Jun 05 05:49:48 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-8c0436d4-9419-4b8e-99cf-d08788c9a3b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1403449089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1403449089 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2269590885 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 337048370000 ps |
| CPU time | 988.3 seconds |
| Started | Jun 05 05:07:47 PM PDT 24 |
| Finished | Jun 05 05:48:40 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-55fc6f88-efd0-4d16-89bd-101ac95ed903 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2269590885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2269590885 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4017201439 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336486810000 ps |
| CPU time | 954.57 seconds |
| Started | Jun 05 05:07:48 PM PDT 24 |
| Finished | Jun 05 05:47:41 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-b7c604d3-92e1-47e0-a101-d04a0dacab4c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4017201439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4017201439 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.556465234 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336432590000 ps |
| CPU time | 913.79 seconds |
| Started | Jun 05 05:07:46 PM PDT 24 |
| Finished | Jun 05 05:46:09 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-c5340fcb-fb6d-4be4-866d-a1ae0f56249d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=556465234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.556465234 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1416346412 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336363470000 ps |
| CPU time | 1001.38 seconds |
| Started | Jun 05 05:07:49 PM PDT 24 |
| Finished | Jun 05 05:50:19 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-81d6db7e-fa38-4eeb-ba67-57b93a805836 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1416346412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1416346412 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3007685684 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336304730000 ps |
| CPU time | 824.39 seconds |
| Started | Jun 05 05:07:46 PM PDT 24 |
| Finished | Jun 05 05:40:43 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-1ce9df1c-9d0a-4657-b862-253cfcad4e61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3007685684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3007685684 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1230109539 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 336367090000 ps |
| CPU time | 832.02 seconds |
| Started | Jun 05 05:07:46 PM PDT 24 |
| Finished | Jun 05 05:42:17 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-fe2b13cd-4d54-4fc0-b95a-e46f7307c161 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1230109539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1230109539 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3540840940 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336445790000 ps |
| CPU time | 752.61 seconds |
| Started | Jun 05 05:07:47 PM PDT 24 |
| Finished | Jun 05 05:38:20 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-24bd061c-be2d-4a25-8144-e222d6c9930b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3540840940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3540840940 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3792111795 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336518450000 ps |
| CPU time | 858.29 seconds |
| Started | Jun 05 05:07:46 PM PDT 24 |
| Finished | Jun 05 05:42:24 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-7ccfac8e-a810-44cf-9679-ed8bec37b1c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3792111795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3792111795 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1121551788 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 336646490000 ps |
| CPU time | 647.39 seconds |
| Started | Jun 05 05:07:44 PM PDT 24 |
| Finished | Jun 05 05:34:55 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-8e3d38e2-9034-46e3-bc80-9fd205afcfce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1121551788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1121551788 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3352228624 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336728350000 ps |
| CPU time | 989.63 seconds |
| Started | Jun 05 05:07:37 PM PDT 24 |
| Finished | Jun 05 05:48:41 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-aa0cc860-f36e-44ef-bb68-a8109a0afa8e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3352228624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3352228624 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2313111352 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336389950000 ps |
| CPU time | 785.26 seconds |
| Started | Jun 05 05:07:45 PM PDT 24 |
| Finished | Jun 05 05:39:45 PM PDT 24 |
| Peak memory | 160892 kb |
| Host | smart-141cb4c3-96ee-4db8-a0ca-4ed81e980b14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2313111352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2313111352 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3666203204 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336545030000 ps |
| CPU time | 880.86 seconds |
| Started | Jun 05 05:07:53 PM PDT 24 |
| Finished | Jun 05 05:45:20 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-8fb696d4-1079-40fe-85aa-27ec5d45fb54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3666203204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3666203204 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.255902615 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336535150000 ps |
| CPU time | 959.61 seconds |
| Started | Jun 05 05:07:52 PM PDT 24 |
| Finished | Jun 05 05:47:57 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-fab17bcf-cf0f-4545-b1b5-4e01956ed35f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=255902615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.255902615 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1900404132 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336565070000 ps |
| CPU time | 796.51 seconds |
| Started | Jun 05 05:07:52 PM PDT 24 |
| Finished | Jun 05 05:40:13 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-b483de0c-ad5d-4cb8-89b6-8a8151397a05 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1900404132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1900404132 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2983442851 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336344950000 ps |
| CPU time | 773.51 seconds |
| Started | Jun 05 05:07:52 PM PDT 24 |
| Finished | Jun 05 05:39:38 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-c4e94ba4-196e-421e-9278-6229399b4a6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2983442851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2983442851 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1507109750 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336728370000 ps |
| CPU time | 1010.99 seconds |
| Started | Jun 05 05:07:53 PM PDT 24 |
| Finished | Jun 05 05:50:50 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-900fd054-a2e7-4df3-9d41-891f699ba2e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1507109750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1507109750 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1801825113 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 336660410000 ps |
| CPU time | 895.35 seconds |
| Started | Jun 05 05:07:55 PM PDT 24 |
| Finished | Jun 05 05:46:08 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-59a77b38-fbce-4ac6-8be5-a25fca52ff04 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1801825113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1801825113 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1486523630 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336676570000 ps |
| CPU time | 720.06 seconds |
| Started | Jun 05 05:07:53 PM PDT 24 |
| Finished | Jun 05 05:37:44 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-7fc83746-bdd6-4af9-8f84-b6d772f97e83 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1486523630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1486523630 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3357366681 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336867330000 ps |
| CPU time | 893.63 seconds |
| Started | Jun 05 05:07:56 PM PDT 24 |
| Finished | Jun 05 05:46:04 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-e02947e4-44e9-4852-a4da-6379dd7c5246 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3357366681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3357366681 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.898738077 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 336488310000 ps |
| CPU time | 826.47 seconds |
| Started | Jun 05 05:07:53 PM PDT 24 |
| Finished | Jun 05 05:40:58 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-f752eed1-68ea-4c8e-b3bb-0967161cef5e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=898738077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.898738077 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3435588401 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 337127770000 ps |
| CPU time | 990.74 seconds |
| Started | Jun 05 05:07:40 PM PDT 24 |
| Finished | Jun 05 05:49:45 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-1b71eb9b-083e-4f7d-9079-71c1a9d5abef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3435588401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3435588401 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.219879875 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336456550000 ps |
| CPU time | 889.02 seconds |
| Started | Jun 05 05:07:55 PM PDT 24 |
| Finished | Jun 05 05:46:02 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-5d20c1b8-24fe-4f50-99cc-b32fc009bf27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=219879875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.219879875 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3782398889 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336513130000 ps |
| CPU time | 832.85 seconds |
| Started | Jun 05 05:07:52 PM PDT 24 |
| Finished | Jun 05 05:42:09 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-d2c1c7f7-5b64-430f-b7ce-37d08a878d52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3782398889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3782398889 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2651966955 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 337005090000 ps |
| CPU time | 1005.99 seconds |
| Started | Jun 05 05:08:01 PM PDT 24 |
| Finished | Jun 05 05:50:51 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-923b83c3-a45e-4dbd-93db-8763fda59b75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2651966955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2651966955 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3397657102 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336919330000 ps |
| CPU time | 785.35 seconds |
| Started | Jun 05 05:08:01 PM PDT 24 |
| Finished | Jun 05 05:40:43 PM PDT 24 |
| Peak memory | 160864 kb |
| Host | smart-41dd4d4c-5f0c-4293-b051-81b1b48f1b88 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3397657102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3397657102 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2649454050 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336401650000 ps |
| CPU time | 845.48 seconds |
| Started | Jun 05 05:08:03 PM PDT 24 |
| Finished | Jun 05 05:43:30 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-43596a20-73fa-4d20-8bf6-189975f6add4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2649454050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2649454050 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.347795409 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336836490000 ps |
| CPU time | 816.42 seconds |
| Started | Jun 05 05:08:00 PM PDT 24 |
| Finished | Jun 05 05:41:55 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-e7e8b183-e9f4-4243-acc4-c8616f8bdfe1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=347795409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.347795409 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.4212513946 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336570010000 ps |
| CPU time | 895.42 seconds |
| Started | Jun 05 05:08:01 PM PDT 24 |
| Finished | Jun 05 05:44:25 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-9da4c7f3-f9f3-403e-9b66-cae8944cf39c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4212513946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.4212513946 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4087690058 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 337007570000 ps |
| CPU time | 809.39 seconds |
| Started | Jun 05 05:08:00 PM PDT 24 |
| Finished | Jun 05 05:41:12 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-4af6c556-fc24-42c7-ad08-112c40e8c171 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4087690058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.4087690058 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2922379186 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336660190000 ps |
| CPU time | 741.56 seconds |
| Started | Jun 05 05:08:00 PM PDT 24 |
| Finished | Jun 05 05:38:20 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-9d6c6bd6-155c-4e25-bedb-09486ebd5758 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2922379186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2922379186 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2456570489 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 337060890000 ps |
| CPU time | 857.52 seconds |
| Started | Jun 05 05:08:03 PM PDT 24 |
| Finished | Jun 05 05:43:47 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-94f1fd73-2f4b-4ec1-8dd1-5834022d6103 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2456570489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2456570489 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.57518825 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336511970000 ps |
| CPU time | 806.85 seconds |
| Started | Jun 05 05:07:38 PM PDT 24 |
| Finished | Jun 05 05:41:21 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-53f92751-a91c-4609-b695-a98d6b498ba0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=57518825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.57518825 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3357184056 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336571930000 ps |
| CPU time | 846.23 seconds |
| Started | Jun 05 05:07:59 PM PDT 24 |
| Finished | Jun 05 05:42:52 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-82e058b2-c55a-445a-a1a4-e0e9f99ae06f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3357184056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3357184056 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3920787192 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 337042490000 ps |
| CPU time | 850.35 seconds |
| Started | Jun 05 05:08:04 PM PDT 24 |
| Finished | Jun 05 05:43:43 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-2adc0e74-9809-44fc-bc45-ff64a74510b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3920787192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3920787192 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.61809235 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336331330000 ps |
| CPU time | 907.17 seconds |
| Started | Jun 05 05:08:01 PM PDT 24 |
| Finished | Jun 05 05:45:32 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-c1024c30-516e-4d79-bb34-6a7e3160371b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=61809235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.61809235 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2957824158 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336841210000 ps |
| CPU time | 796.13 seconds |
| Started | Jun 05 05:08:07 PM PDT 24 |
| Finished | Jun 05 05:41:35 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-a3cb1a13-ace4-48d8-a252-382289e85816 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2957824158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2957824158 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4052648023 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336570910000 ps |
| CPU time | 796.89 seconds |
| Started | Jun 05 05:08:15 PM PDT 24 |
| Finished | Jun 05 05:40:56 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-9052a680-3723-448d-83a4-2970cfb1cd87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4052648023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.4052648023 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1088472745 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336996110000 ps |
| CPU time | 834.41 seconds |
| Started | Jun 05 05:08:09 PM PDT 24 |
| Finished | Jun 05 05:42:13 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-017492f6-8a7e-45cf-b3be-d879c6a9f5c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1088472745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1088472745 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3966713785 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 336582830000 ps |
| CPU time | 756.51 seconds |
| Started | Jun 05 05:08:08 PM PDT 24 |
| Finished | Jun 05 05:38:56 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-442cd51b-8a8a-4f8c-ac57-955f88bff71b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3966713785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3966713785 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3652348198 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336632410000 ps |
| CPU time | 692.58 seconds |
| Started | Jun 05 05:08:15 PM PDT 24 |
| Finished | Jun 05 05:36:38 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-d6eae093-9e3c-4fe3-825a-a0cfaa9ee4bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3652348198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3652348198 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.983857585 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 337046210000 ps |
| CPU time | 905.66 seconds |
| Started | Jun 05 05:08:10 PM PDT 24 |
| Finished | Jun 05 05:45:35 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-c8fb0e96-4ec3-4d3f-9191-e5984cb995f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=983857585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.983857585 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2952451412 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 337019290000 ps |
| CPU time | 1010.66 seconds |
| Started | Jun 05 05:08:08 PM PDT 24 |
| Finished | Jun 05 05:51:03 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-0df3f42e-e183-410d-a922-1c8c669164f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2952451412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2952451412 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.564943128 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 336686910000 ps |
| CPU time | 716.32 seconds |
| Started | Jun 05 05:07:36 PM PDT 24 |
| Finished | Jun 05 05:36:59 PM PDT 24 |
| Peak memory | 160756 kb |
| Host | smart-2fca17d3-f56d-46d9-89a7-81e3efe5ae8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=564943128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.564943128 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1871166498 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336679490000 ps |
| CPU time | 870.08 seconds |
| Started | Jun 05 05:07:47 PM PDT 24 |
| Finished | Jun 05 05:43:07 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-8c2f74e1-8309-4cc8-8d8b-73966f6c6041 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1871166498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1871166498 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2005734494 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336959690000 ps |
| CPU time | 959.12 seconds |
| Started | Jun 05 05:07:47 PM PDT 24 |
| Finished | Jun 05 05:47:52 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-99e9dc6e-c382-420a-bf29-bc7a78dfc6c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2005734494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2005734494 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.864812733 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 336632250000 ps |
| CPU time | 838.58 seconds |
| Started | Jun 05 05:07:46 PM PDT 24 |
| Finished | Jun 05 05:42:22 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-e0f84acb-a0e0-4f1c-8baa-de9f2387de3b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=864812733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.864812733 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3292897014 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336692070000 ps |
| CPU time | 850.81 seconds |
| Started | Jun 05 05:07:47 PM PDT 24 |
| Finished | Jun 05 05:42:51 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-484f12a1-2fd8-441b-8b82-849ea6a35947 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3292897014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3292897014 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2798902335 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 337164950000 ps |
| CPU time | 953.99 seconds |
| Started | Jun 05 05:07:16 PM PDT 24 |
| Finished | Jun 05 05:47:29 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-951d1fbb-b77a-4d23-aa64-0f3e0ad5c644 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2798902335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2798902335 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.955793696 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336347230000 ps |
| CPU time | 878.2 seconds |
| Started | Jun 05 05:07:14 PM PDT 24 |
| Finished | Jun 05 05:42:53 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-5189257c-dfda-416b-b72f-8ceb653b07fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=955793696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.955793696 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2940984168 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336392990000 ps |
| CPU time | 787.9 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:40:11 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-98700b17-60b5-4b4f-ac62-f2a9164f0bc4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2940984168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2940984168 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1781869694 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336976990000 ps |
| CPU time | 776.63 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:39:19 PM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-39c1b7ac-3afa-4aaf-84d7-7461754b5ece |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1781869694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1781869694 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2968658954 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336966230000 ps |
| CPU time | 840.4 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:42:11 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-98f543b8-f141-4c73-a46f-e52d9883801f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2968658954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2968658954 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4111444262 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 336966710000 ps |
| CPU time | 894.17 seconds |
| Started | Jun 05 05:07:21 PM PDT 24 |
| Finished | Jun 05 05:45:18 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-0cdeac3d-fc5e-4f55-a0a9-46c8b24a2ff1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4111444262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4111444262 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1281507709 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336540750000 ps |
| CPU time | 893.37 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:45:04 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-942df18c-dac3-4bbd-b816-4e60b6709943 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1281507709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1281507709 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1112442654 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336344670000 ps |
| CPU time | 808.19 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:40:56 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-55dc4bc1-fc0d-4785-b27f-df67dbbe4bf7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1112442654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1112442654 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2730257979 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336355670000 ps |
| CPU time | 915.67 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:44:25 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-c037b95f-0571-4f49-a6ea-f1c9891cad5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2730257979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2730257979 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2279181101 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336845110000 ps |
| CPU time | 951.54 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:47:17 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-78227276-9d11-4a19-8204-a5b05bbe33ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2279181101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2279181101 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2170948644 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336535810000 ps |
| CPU time | 864.26 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:42:35 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-d1f359f7-4f2d-47eb-afa0-6ff106390f75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2170948644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2170948644 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1597981593 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336624010000 ps |
| CPU time | 628.4 seconds |
| Started | Jun 05 05:07:19 PM PDT 24 |
| Finished | Jun 05 05:33:38 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-8c9e7c7f-e04c-4824-ba06-860cafe15059 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1597981593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1597981593 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2992872519 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336792370000 ps |
| CPU time | 814.53 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:41:22 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-e8d9b971-8e73-47a1-9a2a-117c501cce53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2992872519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2992872519 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2121279199 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336679510000 ps |
| CPU time | 780.37 seconds |
| Started | Jun 05 05:07:21 PM PDT 24 |
| Finished | Jun 05 05:39:29 PM PDT 24 |
| Peak memory | 160896 kb |
| Host | smart-caafee51-805d-471b-982f-0c73ca57840c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2121279199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2121279199 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2740723095 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 337063550000 ps |
| CPU time | 826.75 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:40:38 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-d6412e8f-6084-4c68-ae64-7488b78b6696 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2740723095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2740723095 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2616212276 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 337023710000 ps |
| CPU time | 884.94 seconds |
| Started | Jun 05 05:07:25 PM PDT 24 |
| Finished | Jun 05 05:44:14 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-d5e33281-107a-4614-8a8e-9875ce18e957 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2616212276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2616212276 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.657470953 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336399450000 ps |
| CPU time | 786.72 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:40:04 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-4f9f6cc7-5b44-4ff5-a0e4-8bf216034b32 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=657470953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.657470953 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.79931396 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336984410000 ps |
| CPU time | 1004.99 seconds |
| Started | Jun 05 05:07:24 PM PDT 24 |
| Finished | Jun 05 05:50:07 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-805fcf46-6daf-4971-a498-bb650f90d933 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=79931396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.79931396 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1776560860 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 336561430000 ps |
| CPU time | 987.29 seconds |
| Started | Jun 05 05:07:26 PM PDT 24 |
| Finished | Jun 05 05:49:38 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-ea79a841-4957-4ddc-bcac-188a02592ffd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1776560860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1776560860 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2358667462 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336328350000 ps |
| CPU time | 997.18 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:49:49 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-beefc38f-99f2-499c-b243-19e9d7e22648 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2358667462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2358667462 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.447986790 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 336530950000 ps |
| CPU time | 890.81 seconds |
| Started | Jun 05 05:07:25 PM PDT 24 |
| Finished | Jun 05 05:44:28 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-f39699ef-edce-42ef-89e5-593d2916acd2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=447986790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.447986790 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1138990102 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336307230000 ps |
| CPU time | 800.81 seconds |
| Started | Jun 05 05:07:32 PM PDT 24 |
| Finished | Jun 05 05:40:52 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-83cbfa4f-bb25-49bc-beb2-7deb1edaa221 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1138990102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1138990102 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2988471235 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336951430000 ps |
| CPU time | 744.88 seconds |
| Started | Jun 05 05:07:16 PM PDT 24 |
| Finished | Jun 05 05:37:58 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-0f1ec022-6183-4afa-9396-5e95eda408b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2988471235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2988471235 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2497784531 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 336834850000 ps |
| CPU time | 987.51 seconds |
| Started | Jun 05 05:07:32 PM PDT 24 |
| Finished | Jun 05 05:48:35 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-3e0ec4e7-55f1-4d33-91ac-b0a4c0e1dea9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2497784531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2497784531 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1577160365 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336938570000 ps |
| CPU time | 797.89 seconds |
| Started | Jun 05 05:07:30 PM PDT 24 |
| Finished | Jun 05 05:40:46 PM PDT 24 |
| Peak memory | 160868 kb |
| Host | smart-5e0de44b-330b-4a2f-93e9-a039535191b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1577160365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1577160365 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4266353750 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336859870000 ps |
| CPU time | 899.04 seconds |
| Started | Jun 05 05:07:34 PM PDT 24 |
| Finished | Jun 05 05:45:31 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-da540248-bb01-4191-abce-d7ce5ee9c339 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4266353750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4266353750 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1627671857 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336945330000 ps |
| CPU time | 910.55 seconds |
| Started | Jun 05 05:07:30 PM PDT 24 |
| Finished | Jun 05 05:44:07 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-bfc93d1e-f87e-4581-8f59-165449adf728 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1627671857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1627671857 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1123025463 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336512110000 ps |
| CPU time | 812.29 seconds |
| Started | Jun 05 05:07:31 PM PDT 24 |
| Finished | Jun 05 05:40:49 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-7718c343-d3af-48bb-a329-62a036f74723 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1123025463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1123025463 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3750911806 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336563170000 ps |
| CPU time | 977.91 seconds |
| Started | Jun 05 05:07:31 PM PDT 24 |
| Finished | Jun 05 05:49:04 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-a24f5f83-8259-40b7-872c-f9aeede48c73 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3750911806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3750911806 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1419974790 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336869870000 ps |
| CPU time | 718.22 seconds |
| Started | Jun 05 05:07:30 PM PDT 24 |
| Finished | Jun 05 05:36:41 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-fbb4783e-8e59-4116-8b82-c948eb0bc892 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1419974790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1419974790 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2304823311 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336466230000 ps |
| CPU time | 860.2 seconds |
| Started | Jun 05 05:07:30 PM PDT 24 |
| Finished | Jun 05 05:42:43 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-448e047a-8904-4616-b783-e48fb793e726 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2304823311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2304823311 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.759895410 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336456590000 ps |
| CPU time | 764.17 seconds |
| Started | Jun 05 05:07:30 PM PDT 24 |
| Finished | Jun 05 05:38:35 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-7d4121ac-af73-423d-92f2-c0e734dd222e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=759895410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.759895410 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2794845844 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 336778970000 ps |
| CPU time | 809.19 seconds |
| Started | Jun 05 05:07:31 PM PDT 24 |
| Finished | Jun 05 05:41:05 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-7f841831-23cf-486b-a391-883c1edefe1f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2794845844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2794845844 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1523925511 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336424030000 ps |
| CPU time | 929.14 seconds |
| Started | Jun 05 05:07:17 PM PDT 24 |
| Finished | Jun 05 05:45:33 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-2d3c3eac-83c1-41b1-8b08-ffb0370ed805 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1523925511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1523925511 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2576956534 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336573810000 ps |
| CPU time | 848.16 seconds |
| Started | Jun 05 05:07:30 PM PDT 24 |
| Finished | Jun 05 05:41:32 PM PDT 24 |
| Peak memory | 160948 kb |
| Host | smart-3bf242c9-6f64-41b9-8734-a156575d35ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2576956534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2576956534 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4000680042 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336688770000 ps |
| CPU time | 901.02 seconds |
| Started | Jun 05 05:07:32 PM PDT 24 |
| Finished | Jun 05 05:45:31 PM PDT 24 |
| Peak memory | 160848 kb |
| Host | smart-dd4a811a-0ee1-4634-975f-6e31b2ae1dc7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4000680042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.4000680042 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.510536055 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336973950000 ps |
| CPU time | 806.73 seconds |
| Started | Jun 05 05:07:38 PM PDT 24 |
| Finished | Jun 05 05:41:28 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-822af342-52af-4211-8a08-5c106d39c369 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=510536055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.510536055 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2881914959 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336365670000 ps |
| CPU time | 754.06 seconds |
| Started | Jun 05 05:07:36 PM PDT 24 |
| Finished | Jun 05 05:38:43 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-99543dd5-ab52-4474-ac3a-34f97088ffcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2881914959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2881914959 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2135741928 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336404110000 ps |
| CPU time | 987.81 seconds |
| Started | Jun 05 05:07:39 PM PDT 24 |
| Finished | Jun 05 05:49:36 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-6a0d0feb-e25e-4a99-940b-8216ac549f2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2135741928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2135741928 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1751675054 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 337082990000 ps |
| CPU time | 909.71 seconds |
| Started | Jun 05 05:07:36 PM PDT 24 |
| Finished | Jun 05 05:44:56 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-0b832d6f-6bdb-475b-9398-90829b25d23f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1751675054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1751675054 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.322207019 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336336030000 ps |
| CPU time | 659.43 seconds |
| Started | Jun 05 05:07:35 PM PDT 24 |
| Finished | Jun 05 05:34:51 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-a629fcc6-d4ae-440b-9eb6-9ce3bdd86088 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=322207019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.322207019 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2739587033 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 336581390000 ps |
| CPU time | 886.92 seconds |
| Started | Jun 05 05:07:37 PM PDT 24 |
| Finished | Jun 05 05:45:31 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-a881a447-ad33-423a-bae9-3bedb790828f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2739587033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2739587033 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4075097731 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336909290000 ps |
| CPU time | 783.2 seconds |
| Started | Jun 05 05:07:37 PM PDT 24 |
| Finished | Jun 05 05:39:50 PM PDT 24 |
| Peak memory | 160836 kb |
| Host | smart-8b85615d-0857-4a73-99b4-2cb630b2ac35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4075097731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.4075097731 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.103805658 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336861470000 ps |
| CPU time | 1019.26 seconds |
| Started | Jun 05 05:07:36 PM PDT 24 |
| Finished | Jun 05 05:50:49 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-e15b540c-65b1-4d57-921b-5427c836a768 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=103805658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.103805658 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2150145094 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336946850000 ps |
| CPU time | 915.45 seconds |
| Started | Jun 05 05:07:14 PM PDT 24 |
| Finished | Jun 05 05:44:57 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-99a30e72-563b-4d57-94f2-e588ca44bae0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2150145094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2150145094 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.733717901 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 337046870000 ps |
| CPU time | 629.78 seconds |
| Started | Jun 05 05:07:19 PM PDT 24 |
| Finished | Jun 05 05:33:41 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-e73328bd-49a5-442f-86c5-9c11d405b46c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=733717901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.733717901 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2045238244 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336597930000 ps |
| CPU time | 897.31 seconds |
| Started | Jun 05 05:07:16 PM PDT 24 |
| Finished | Jun 05 05:43:56 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-1357ada8-582a-4999-b22e-7244979d2d28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2045238244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2045238244 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2027260714 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336654730000 ps |
| CPU time | 763.13 seconds |
| Started | Jun 05 05:07:23 PM PDT 24 |
| Finished | Jun 05 05:38:13 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-88c61a65-85a0-4ddc-a135-78ff42eb9b20 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2027260714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2027260714 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2699731985 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336627770000 ps |
| CPU time | 955.2 seconds |
| Started | Jun 05 05:07:22 PM PDT 24 |
| Finished | Jun 05 05:48:01 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-d6db8255-5f62-46d5-aa4a-928b64c88e97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2699731985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2699731985 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1114138391 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1540250000 ps |
| CPU time | 5.57 seconds |
| Started | Jun 05 05:12:45 PM PDT 24 |
| Finished | Jun 05 05:12:58 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-0a8132d1-20a8-4084-8262-e045a75ef424 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1114138391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1114138391 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3052103422 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1474150000 ps |
| CPU time | 4.02 seconds |
| Started | Jun 05 05:12:46 PM PDT 24 |
| Finished | Jun 05 05:12:56 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-40c3bfe7-4cb1-4703-ad65-2ba9c2c7a4b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3052103422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3052103422 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1447792232 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1471330000 ps |
| CPU time | 6.06 seconds |
| Started | Jun 05 05:12:53 PM PDT 24 |
| Finished | Jun 05 05:13:07 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-4aeae5fa-7c21-4a40-894e-19da7a719bff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1447792232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1447792232 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2679912772 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1527370000 ps |
| CPU time | 5.84 seconds |
| Started | Jun 05 05:12:52 PM PDT 24 |
| Finished | Jun 05 05:13:06 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-e595266f-95ce-4770-9450-2a73016d4b92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2679912772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2679912772 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.285944900 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1123490000 ps |
| CPU time | 3.01 seconds |
| Started | Jun 05 05:12:53 PM PDT 24 |
| Finished | Jun 05 05:13:00 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-ea10e62d-b3cd-46c0-aec0-75e29c9def16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=285944900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.285944900 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.589686140 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1525590000 ps |
| CPU time | 5.2 seconds |
| Started | Jun 05 05:12:54 PM PDT 24 |
| Finished | Jun 05 05:13:06 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-cbfe1a1e-e19e-47d4-b729-08e9528b7e6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=589686140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.589686140 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1613793225 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1366030000 ps |
| CPU time | 4.89 seconds |
| Started | Jun 05 05:12:52 PM PDT 24 |
| Finished | Jun 05 05:13:03 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-64578a14-36e8-47f9-8090-8c739b210b5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1613793225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1613793225 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2973974069 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1231790000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 05 05:12:52 PM PDT 24 |
| Finished | Jun 05 05:13:02 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-9ebb6ba7-8fb0-4c1b-852d-f6945239c1a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2973974069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2973974069 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.322634018 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1447690000 ps |
| CPU time | 4.2 seconds |
| Started | Jun 05 05:12:54 PM PDT 24 |
| Finished | Jun 05 05:13:04 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-9d6a3303-3cf5-40fa-a28b-0255d4e2c522 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=322634018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.322634018 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1207704332 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1223550000 ps |
| CPU time | 2.95 seconds |
| Started | Jun 05 05:12:51 PM PDT 24 |
| Finished | Jun 05 05:12:58 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-af042c5c-2538-4aff-8133-f4de3aaf928d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1207704332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1207704332 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4102006607 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1398690000 ps |
| CPU time | 4.72 seconds |
| Started | Jun 05 05:12:54 PM PDT 24 |
| Finished | Jun 05 05:13:04 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-b3691a39-0805-457c-bbcb-78b421e10b69 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4102006607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4102006607 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.940359968 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1324230000 ps |
| CPU time | 5.14 seconds |
| Started | Jun 05 05:13:01 PM PDT 24 |
| Finished | Jun 05 05:13:13 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-c233fef0-4ec9-4c14-a0c0-2a8808e27895 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=940359968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.940359968 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3365322734 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1609210000 ps |
| CPU time | 5.32 seconds |
| Started | Jun 05 05:12:45 PM PDT 24 |
| Finished | Jun 05 05:12:58 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-68bdce70-f215-452e-bc6c-d2fd66aaf5dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3365322734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3365322734 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1632370868 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1583210000 ps |
| CPU time | 6.47 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:15 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-ef2e371c-828e-4f20-84c6-c3d2a560d58d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1632370868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1632370868 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3421449296 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1441570000 ps |
| CPU time | 5.02 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:11 PM PDT 24 |
| Peak memory | 165064 kb |
| Host | smart-9ada5c4e-14a8-4d26-a5b7-d3fb01bb9352 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3421449296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3421449296 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1130284898 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1476850000 ps |
| CPU time | 5.62 seconds |
| Started | Jun 05 05:13:01 PM PDT 24 |
| Finished | Jun 05 05:13:13 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-fc59e3ce-14c7-4b46-a485-366402aa6a77 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1130284898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.1130284898 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2971341980 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1450170000 ps |
| CPU time | 4.94 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-0d90d8fc-6879-4533-b5d0-54665a08d12a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2971341980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2971341980 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1445932385 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1488270000 ps |
| CPU time | 4.58 seconds |
| Started | Jun 05 05:13:01 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-c90978b8-bcd7-4723-a045-979c1370d7be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1445932385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1445932385 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4087115819 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1443610000 ps |
| CPU time | 5.54 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-0c0d6de2-9b7c-4b74-80fe-6660bbc66e42 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4087115819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4087115819 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2570477733 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1366770000 ps |
| CPU time | 4.66 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:10 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-54c1316c-bfa8-40d6-9912-25472596ca72 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2570477733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2570477733 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2294060396 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1565250000 ps |
| CPU time | 4.53 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:10 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-49f8f359-9a78-4537-8a52-3c5c0a8edec7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2294060396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2294060396 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1158377283 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1448770000 ps |
| CPU time | 5.03 seconds |
| Started | Jun 05 05:12:59 PM PDT 24 |
| Finished | Jun 05 05:13:10 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-cc647163-80bf-418c-8af4-67d3fa28a681 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1158377283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1158377283 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2805009487 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1499070000 ps |
| CPU time | 5.52 seconds |
| Started | Jun 05 05:13:01 PM PDT 24 |
| Finished | Jun 05 05:13:14 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-298f01a2-5992-4332-935d-6e4ad46d51f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2805009487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2805009487 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1144719017 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1478710000 ps |
| CPU time | 5.73 seconds |
| Started | Jun 05 05:12:45 PM PDT 24 |
| Finished | Jun 05 05:12:58 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-a3a32da8-ec9d-415a-bbfc-44fa2f89416c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1144719017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1144719017 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2295497897 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1498490000 ps |
| CPU time | 4.65 seconds |
| Started | Jun 05 05:13:02 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-82f7d0ab-385c-4c13-9757-a0f2a94cced9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2295497897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2295497897 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3480878085 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1496830000 ps |
| CPU time | 5 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-5dd8abb9-1457-4d59-8227-593441e8eccd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3480878085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3480878085 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.615348871 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1481930000 ps |
| CPU time | 5.94 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:14 PM PDT 24 |
| Peak memory | 164880 kb |
| Host | smart-3d631a3b-0e08-42ef-95fb-5b764c698d2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=615348871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.615348871 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2907349842 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1469430000 ps |
| CPU time | 4.48 seconds |
| Started | Jun 05 05:13:01 PM PDT 24 |
| Finished | Jun 05 05:13:11 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-69ef43eb-0fb8-4642-939a-9936bb71ae5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2907349842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2907349842 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1061201271 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1455010000 ps |
| CPU time | 4.65 seconds |
| Started | Jun 05 05:12:59 PM PDT 24 |
| Finished | Jun 05 05:13:10 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-d7542b9e-3048-4e01-a742-337c390d4be2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1061201271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1061201271 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1307934255 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 1499110000 ps |
| CPU time | 5.49 seconds |
| Started | Jun 05 05:13:01 PM PDT 24 |
| Finished | Jun 05 05:13:14 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-9e44368c-7f89-4f41-9929-2983c0d2cd9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1307934255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1307934255 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2924391947 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1474610000 ps |
| CPU time | 5.2 seconds |
| Started | Jun 05 05:13:00 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-ee17fd7b-c2fd-468b-8b3c-dd5c3bb8690c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2924391947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2924391947 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1161111807 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1599470000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 05 05:13:02 PM PDT 24 |
| Finished | Jun 05 05:13:12 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-4414255a-2ed1-4390-ac50-2ab0855140af |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1161111807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1161111807 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3854455863 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1358630000 ps |
| CPU time | 4.83 seconds |
| Started | Jun 05 05:13:08 PM PDT 24 |
| Finished | Jun 05 05:13:20 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-52c45462-b6a7-4a66-aece-930be97ad665 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3854455863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3854455863 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.4219528978 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1335030000 ps |
| CPU time | 4.98 seconds |
| Started | Jun 05 05:13:09 PM PDT 24 |
| Finished | Jun 05 05:13:22 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-3675d526-7ab7-4c41-a678-5bb6f8996037 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4219528978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.4219528978 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3839353742 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1603670000 ps |
| CPU time | 6.03 seconds |
| Started | Jun 05 05:12:51 PM PDT 24 |
| Finished | Jun 05 05:13:05 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-a0288e2c-40da-4414-b41f-3d22e80a5230 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3839353742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3839353742 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4070351367 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1543190000 ps |
| CPU time | 4.47 seconds |
| Started | Jun 05 05:13:09 PM PDT 24 |
| Finished | Jun 05 05:13:19 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-f7f10ad5-41ac-4c91-b364-7825dfdee01c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4070351367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.4070351367 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2343522555 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1507130000 ps |
| CPU time | 4.55 seconds |
| Started | Jun 05 05:13:06 PM PDT 24 |
| Finished | Jun 05 05:13:17 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-21cfb2f3-8c82-48b3-bb66-48e790d24cc9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2343522555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2343522555 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2484458383 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1170910000 ps |
| CPU time | 4.29 seconds |
| Started | Jun 05 05:13:06 PM PDT 24 |
| Finished | Jun 05 05:13:16 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-6a94f52f-e20b-4311-b782-233b059db9e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2484458383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2484458383 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.33431017 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1246150000 ps |
| CPU time | 4.16 seconds |
| Started | Jun 05 05:13:06 PM PDT 24 |
| Finished | Jun 05 05:13:16 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-cb61164f-a30d-47c0-86fa-fb9eca236e94 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=33431017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.33431017 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1243671801 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1151430000 ps |
| CPU time | 4.12 seconds |
| Started | Jun 05 05:13:08 PM PDT 24 |
| Finished | Jun 05 05:13:18 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-f00685f3-b64d-4866-a7f0-9fdfa8c17aa1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1243671801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1243671801 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.967897169 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1318050000 ps |
| CPU time | 4.66 seconds |
| Started | Jun 05 05:13:06 PM PDT 24 |
| Finished | Jun 05 05:13:17 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-a195cca2-9aca-451c-b08d-8c464f2406e9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=967897169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.967897169 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4192682665 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1593870000 ps |
| CPU time | 5.87 seconds |
| Started | Jun 05 05:13:08 PM PDT 24 |
| Finished | Jun 05 05:13:21 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-ff92284e-5e76-4539-9d15-8acaaa5e7c28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4192682665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4192682665 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1949250163 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1388790000 ps |
| CPU time | 5.3 seconds |
| Started | Jun 05 05:13:09 PM PDT 24 |
| Finished | Jun 05 05:13:22 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-37b9e00d-11cd-4aa1-86f4-633e4f179daf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1949250163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1949250163 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3950752641 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1276450000 ps |
| CPU time | 4.12 seconds |
| Started | Jun 05 05:13:08 PM PDT 24 |
| Finished | Jun 05 05:13:18 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-d31c4857-ef73-412c-87fe-9452a6bbc68f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3950752641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3950752641 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.4226094263 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1199750000 ps |
| CPU time | 3.66 seconds |
| Started | Jun 05 05:13:06 PM PDT 24 |
| Finished | Jun 05 05:13:15 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-1f95264e-809d-40a8-8d74-96a9fd5def0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4226094263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.4226094263 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1941593294 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1556950000 ps |
| CPU time | 6.15 seconds |
| Started | Jun 05 05:12:52 PM PDT 24 |
| Finished | Jun 05 05:13:06 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-2fe26d6a-ef4d-455b-b020-1db2d9add157 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1941593294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1941593294 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2395473396 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1469970000 ps |
| CPU time | 4.96 seconds |
| Started | Jun 05 05:12:53 PM PDT 24 |
| Finished | Jun 05 05:13:04 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-65e92cba-5581-4a7d-b4ab-3c18a17327e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2395473396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2395473396 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1382779102 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1593150000 ps |
| CPU time | 5.99 seconds |
| Started | Jun 05 05:12:53 PM PDT 24 |
| Finished | Jun 05 05:13:07 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-fb238d5a-589e-4131-8145-1e8abf0eb92c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1382779102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1382779102 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1164444059 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1364990000 ps |
| CPU time | 3.41 seconds |
| Started | Jun 05 05:12:52 PM PDT 24 |
| Finished | Jun 05 05:13:00 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-c59d5524-c7ae-4425-9df1-6d9ec125a8bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1164444059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1164444059 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1378447106 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1560210000 ps |
| CPU time | 5.67 seconds |
| Started | Jun 05 05:12:54 PM PDT 24 |
| Finished | Jun 05 05:13:07 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-11737477-5e2a-4b30-8eb3-5c6ac4536253 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1378447106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1378447106 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.394561393 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1433930000 ps |
| CPU time | 6.34 seconds |
| Started | Jun 05 04:44:17 PM PDT 24 |
| Finished | Jun 05 04:44:31 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-c934a095-27ca-43b0-8e8e-9283ed61a144 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=394561393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.394561393 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.846966557 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1486670000 ps |
| CPU time | 5.15 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-cfa04bf9-d317-4340-83ff-8720678f742f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=846966557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.846966557 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2299092560 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1463550000 ps |
| CPU time | 3.76 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:25 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-b469d828-c56d-4525-9c6e-b9cfa4237378 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2299092560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2299092560 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.153591421 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1443430000 ps |
| CPU time | 5.93 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-1534a521-95cc-42af-9c9f-70996f26ae62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=153591421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.153591421 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.516254179 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1473970000 ps |
| CPU time | 5.49 seconds |
| Started | Jun 05 04:44:17 PM PDT 24 |
| Finished | Jun 05 04:44:30 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-8fcad1a5-1a37-4670-b0fc-edd5fc7c79a2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=516254179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.516254179 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1051540695 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1604330000 ps |
| CPU time | 6.42 seconds |
| Started | Jun 05 04:44:14 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-c664f117-8279-410c-89c2-04c1ddc34390 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1051540695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1051540695 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.864100965 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1321030000 ps |
| CPU time | 4.02 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:26 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-b5327ee2-edf6-4c2e-ad6a-72f83b1841a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=864100965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.864100965 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3157635386 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1428690000 ps |
| CPU time | 5.85 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:29 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-36594921-d3be-4835-9419-7a3c40e6ce3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3157635386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3157635386 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2829640121 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1454530000 ps |
| CPU time | 2.88 seconds |
| Started | Jun 05 04:44:13 PM PDT 24 |
| Finished | Jun 05 04:44:20 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-c88506ad-0cdf-46eb-9ccb-8960dcbd3437 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2829640121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2829640121 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4205140610 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1403030000 ps |
| CPU time | 4.33 seconds |
| Started | Jun 05 04:44:08 PM PDT 24 |
| Finished | Jun 05 04:44:18 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-87afa4d9-1dac-45e6-8af7-221ce6ef9298 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4205140610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4205140610 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2531686665 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1470190000 ps |
| CPU time | 3.34 seconds |
| Started | Jun 05 04:44:14 PM PDT 24 |
| Finished | Jun 05 04:44:22 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-f74e416a-01de-414d-8653-3d11fe7c9714 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2531686665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2531686665 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.653856211 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1505770000 ps |
| CPU time | 5.48 seconds |
| Started | Jun 05 04:44:17 PM PDT 24 |
| Finished | Jun 05 04:44:30 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-93b2e767-9ad7-4dfc-8fb2-a04f1bbe25c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=653856211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.653856211 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.148163000 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1498430000 ps |
| CPU time | 6.25 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:29 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-d7034600-d331-42bd-aab2-36e4f5400ab8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=148163000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.148163000 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2306475357 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1299510000 ps |
| CPU time | 3.94 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:26 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-14861b9a-941d-41c7-b99e-694dcf9b3441 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2306475357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2306475357 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1668705638 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1305630000 ps |
| CPU time | 4.53 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:25 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-85a58793-d092-4086-9c3d-e16142c6f624 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1668705638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1668705638 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.711109392 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1402490000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-632fcf9c-0d8f-4f9f-9a43-829442d6aad0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=711109392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.711109392 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1835388467 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1523070000 ps |
| CPU time | 3.52 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:23 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-cb73e223-a115-45af-aa3b-c9de4a5783d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1835388467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1835388467 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4071575690 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1355830000 ps |
| CPU time | 4.4 seconds |
| Started | Jun 05 04:44:25 PM PDT 24 |
| Finished | Jun 05 04:44:36 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-584ec182-61f0-49c6-8672-2e7f469982eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4071575690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4071575690 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3165645600 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1558170000 ps |
| CPU time | 5.81 seconds |
| Started | Jun 05 04:44:19 PM PDT 24 |
| Finished | Jun 05 04:44:32 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-561b19e4-842e-42ce-ad15-7d9a10213ed2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3165645600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3165645600 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.10118605 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1560390000 ps |
| CPU time | 7.11 seconds |
| Started | Jun 05 04:44:18 PM PDT 24 |
| Finished | Jun 05 04:44:33 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-39dbb575-be47-45a0-90dc-22147a1b9d5b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=10118605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.10118605 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.675785349 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1131590000 ps |
| CPU time | 4.4 seconds |
| Started | Jun 05 04:44:19 PM PDT 24 |
| Finished | Jun 05 04:44:30 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-4988db1a-cbf8-4ae8-a82d-c7c6b77dfba2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=675785349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.675785349 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2503506397 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1463710000 ps |
| CPU time | 4.02 seconds |
| Started | Jun 05 04:44:20 PM PDT 24 |
| Finished | Jun 05 04:44:30 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-2d15ef63-14bb-43bf-af10-0500ad68bcfb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2503506397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2503506397 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.961192816 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1398790000 ps |
| CPU time | 5.93 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-30478b3f-a0ba-4de0-b43d-4b16e578c4f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=961192816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.961192816 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2632546349 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1559090000 ps |
| CPU time | 4 seconds |
| Started | Jun 05 04:44:18 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-e02fdadb-df14-4812-a543-50d0d2b5a341 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2632546349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2632546349 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3671295387 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1603170000 ps |
| CPU time | 4.94 seconds |
| Started | Jun 05 04:44:20 PM PDT 24 |
| Finished | Jun 05 04:44:33 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-cdcac06c-dc9e-45fc-901f-0eebf2c8d531 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3671295387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3671295387 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2144550484 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1397450000 ps |
| CPU time | 4.57 seconds |
| Started | Jun 05 04:44:26 PM PDT 24 |
| Finished | Jun 05 04:44:37 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-9dcfd2df-e673-4d60-8019-b4a0f77afa7e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2144550484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2144550484 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.350721514 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1396710000 ps |
| CPU time | 4.33 seconds |
| Started | Jun 05 04:44:22 PM PDT 24 |
| Finished | Jun 05 04:44:32 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-9f094c9b-0bef-4d3b-9be3-88e096749c2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=350721514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.350721514 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2924844793 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1528730000 ps |
| CPU time | 4.79 seconds |
| Started | Jun 05 04:44:20 PM PDT 24 |
| Finished | Jun 05 04:44:32 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-42762d73-01a9-40ba-9716-fe55f8be6a48 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2924844793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2924844793 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.845887390 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1014430000 ps |
| CPU time | 3 seconds |
| Started | Jun 05 04:44:20 PM PDT 24 |
| Finished | Jun 05 04:44:27 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-80bd3f19-12f7-4dfd-95ec-6abb2efd01a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=845887390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.845887390 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.336792614 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1617870000 ps |
| CPU time | 5.04 seconds |
| Started | Jun 05 04:44:24 PM PDT 24 |
| Finished | Jun 05 04:44:36 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-d0ce9635-440b-48c6-b23f-1ad6285e5d6c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=336792614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.336792614 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2905848322 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1436050000 ps |
| CPU time | 4.62 seconds |
| Started | Jun 05 04:44:21 PM PDT 24 |
| Finished | Jun 05 04:44:33 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-2b203f82-817f-42ef-b3b4-c3e3b9397d14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2905848322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2905848322 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1906086081 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1424730000 ps |
| CPU time | 4.4 seconds |
| Started | Jun 05 04:44:19 PM PDT 24 |
| Finished | Jun 05 04:44:29 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-3449d82c-86a1-4b08-92ee-11520e36cce5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1906086081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1906086081 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1561822485 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1564710000 ps |
| CPU time | 4.79 seconds |
| Started | Jun 05 04:44:23 PM PDT 24 |
| Finished | Jun 05 04:44:35 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-57a23294-bb48-4870-b2fc-0284bb34202f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1561822485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1561822485 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3829810342 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1524670000 ps |
| CPU time | 5.3 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-7a747b7a-aec8-40ad-af18-5ea62cd7fd7d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3829810342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3829810342 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.958398373 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1518310000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 05 04:44:21 PM PDT 24 |
| Finished | Jun 05 04:44:33 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-e3ca61f8-dbed-45cd-be7f-67e8c3983269 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=958398373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.958398373 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1250405771 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1141050000 ps |
| CPU time | 4.77 seconds |
| Started | Jun 05 04:44:20 PM PDT 24 |
| Finished | Jun 05 04:44:31 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-bd3c3052-2324-4d5c-831a-e371f7a6fde7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1250405771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1250405771 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1401401232 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1483330000 ps |
| CPU time | 5.07 seconds |
| Started | Jun 05 04:44:25 PM PDT 24 |
| Finished | Jun 05 04:44:37 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-c146615d-8c97-4943-9438-3bac888e69c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1401401232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1401401232 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3180566206 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1547950000 ps |
| CPU time | 6.14 seconds |
| Started | Jun 05 04:44:30 PM PDT 24 |
| Finished | Jun 05 04:44:44 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-ef9f5cfa-a6bf-4174-b95d-b881fb2e47e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3180566206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3180566206 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.1244582745 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1306410000 ps |
| CPU time | 3.52 seconds |
| Started | Jun 05 04:44:27 PM PDT 24 |
| Finished | Jun 05 04:44:35 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-5b946b63-fdd8-4734-8f48-c1c6ffd2a680 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1244582745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.1244582745 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3238127214 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1508250000 ps |
| CPU time | 4.78 seconds |
| Started | Jun 05 04:44:27 PM PDT 24 |
| Finished | Jun 05 04:44:39 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-42fd6d9f-da4f-4e54-96fd-8f2096e0ebac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3238127214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3238127214 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2783408748 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1220530000 ps |
| CPU time | 5.53 seconds |
| Started | Jun 05 04:44:28 PM PDT 24 |
| Finished | Jun 05 04:44:40 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-8d9e4497-de96-4237-be70-199d42f43549 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2783408748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2783408748 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1595776497 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1275890000 ps |
| CPU time | 4.12 seconds |
| Started | Jun 05 04:44:28 PM PDT 24 |
| Finished | Jun 05 04:44:38 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-88f994cc-970a-4419-ba30-d0f1aa18e49b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1595776497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1595776497 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1617972114 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1566110000 ps |
| CPU time | 3.86 seconds |
| Started | Jun 05 04:44:28 PM PDT 24 |
| Finished | Jun 05 04:44:37 PM PDT 24 |
| Peak memory | 165064 kb |
| Host | smart-2eef7e40-bb23-4485-a62c-297f44957a72 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1617972114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1617972114 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.234410882 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1444950000 ps |
| CPU time | 6.23 seconds |
| Started | Jun 05 04:44:27 PM PDT 24 |
| Finished | Jun 05 04:44:42 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-d685561c-a2ba-4f98-a133-5bc7d4ffa8d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=234410882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.234410882 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1151637259 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1432290000 ps |
| CPU time | 5.33 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:28 PM PDT 24 |
| Peak memory | 164892 kb |
| Host | smart-bff9f427-59bc-4677-9a04-d88f52b35836 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1151637259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1151637259 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1761416071 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1311210000 ps |
| CPU time | 5.74 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:29 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-cd93a522-0505-4c37-b0fe-41272e05d280 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1761416071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1761416071 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3050548823 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1463750000 ps |
| CPU time | 6.26 seconds |
| Started | Jun 05 04:44:14 PM PDT 24 |
| Finished | Jun 05 04:44:27 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-4da91f0c-7459-430a-917f-4ffbc3142023 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3050548823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3050548823 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.278926797 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1466590000 ps |
| CPU time | 3.29 seconds |
| Started | Jun 05 04:44:16 PM PDT 24 |
| Finished | Jun 05 04:44:24 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-d451f1d6-4603-4d60-adcf-3ca81aa9dbc9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=278926797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.278926797 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.297121582 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1627090000 ps |
| CPU time | 5.51 seconds |
| Started | Jun 05 04:44:15 PM PDT 24 |
| Finished | Jun 05 04:44:29 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-bf927f14-ba83-4904-94d8-8f39ac5bb27d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=297121582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.297121582 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |