Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2884585555
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2321244651
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2603075859

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2874442251
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.716259512
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3555833440
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2136543503
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.370182965
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3379880470
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.16755527
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3773956463
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4047670592
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1899255164
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2179336931
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2215952196
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2595540660
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2397995038
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2633841125
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2391472495
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2710638233
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3131347157
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3533532343
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4259358723
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1940956844
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3130306556
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1421374239
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.237345215
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2478901302
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3612417054
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2656108407
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3526814463
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3085264856
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3707093616
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3138285895
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1650064024
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2026965456
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2344271223
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2060101225
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2006802559
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2292199918
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2530128622
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1880538073
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4265474060
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1980526764
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2279219226
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2377581909
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.610958785
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1603905482
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1520541430
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2255312451
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1468006769
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2169177322
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3178708346
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.117855608
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3959786295
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2670359417
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2523918117
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3968192229
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.814576969
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2905938623
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3680785054
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.690945094
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2786451846
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2259630043
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3262537621
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4099983279
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2389644557
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3704267266
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1850296327
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4008043964
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2094675575
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3529381860
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1202157372
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4159297702
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.531015901
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.32507302
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3385495676
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3824973912
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.171614075
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2813236829
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3216903956
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4194768805
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.777942410
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3093644648
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3634213881
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1767591392
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.533201480
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2853040465
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1036554589
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4218872714
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2670773918
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.336696965
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.502406579
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2774343133
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1984362311
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1574770091
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1870911683
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3232795090
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3652392046
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2785518692
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2300977135
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.186124325
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3007551688
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2846590930
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2507073562
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.161198535
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2537534550
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.170594732
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3133622107
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1818185015
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.188000688
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3256495346
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.992006018
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2813446330
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.783665835
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3333116371
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3720060340
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3896643548
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.986749707
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2343339823
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.760473938
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1504187039
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3464791014
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3495177681
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4074821487
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2117345850
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3506628877
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1545914116
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3481607
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2591787305
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1518258593
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.196750130
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3789004088
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1515612740
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3293904832
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4252315688
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2670072110
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1370878848
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4149914806
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4035229886
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2272175936
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1416607095
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.462576893
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3110472168
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1481162996
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1270370468
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.974081961
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2082704546
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3703872062
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.317678708
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2226232812
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.665417126
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3294489564
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3840309332
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.639003204
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.434036073
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1213996537
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1758671767
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3359203721
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.83047670
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2835428133
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2489245353
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2684183301
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4218162890
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.331017547
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3397950393
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1242012785
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3105011871
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1376721446
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4193585192
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4056341772
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2216773162
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2383332904
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4019182288
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.583406865
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3506287625
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.661320901
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1371928497
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2504734579
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2567376099
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4146997748
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.952161689
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2654455439
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2295125219
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3268831306
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2351180024
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.690505448
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2280301127
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3469865307
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2041817753
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.53060669
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1308154372
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2610605039
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3899923499
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.741080084
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2243090317
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3654788185
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.190345444
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2216825538
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1776480314



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1213996537 Jun 06 12:28:03 PM PDT 24 Jun 06 12:28:12 PM PDT 24 1543410000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2567376099 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:32 PM PDT 24 1573050000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3469865307 Jun 06 12:27:49 PM PDT 24 Jun 06 12:27:58 PM PDT 24 1393770000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2884585555 Jun 06 12:21:44 PM PDT 24 Jun 06 12:21:56 PM PDT 24 1434210000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2280301127 Jun 06 12:27:48 PM PDT 24 Jun 06 12:27:57 PM PDT 24 1219010000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1376721446 Jun 06 12:23:28 PM PDT 24 Jun 06 12:23:41 PM PDT 24 1479290000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4193585192 Jun 06 12:23:28 PM PDT 24 Jun 06 12:23:38 PM PDT 24 1226450000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2489245353 Jun 06 12:23:28 PM PDT 24 Jun 06 12:23:41 PM PDT 24 1423570000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2835428133 Jun 06 12:21:50 PM PDT 24 Jun 06 12:22:01 PM PDT 24 1410730000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.190345444 Jun 06 12:21:07 PM PDT 24 Jun 06 12:21:19 PM PDT 24 1263990000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2684183301 Jun 06 12:21:17 PM PDT 24 Jun 06 12:21:28 PM PDT 24 1506530000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2295125219 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:29 PM PDT 24 1198130000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2654455439 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:30 PM PDT 24 1512650000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.952161689 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:31 PM PDT 24 1424910000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4056341772 Jun 06 12:23:42 PM PDT 24 Jun 06 12:23:54 PM PDT 24 1464370000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.83047670 Jun 06 12:22:56 PM PDT 24 Jun 06 12:23:06 PM PDT 24 1204790000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2383332904 Jun 06 12:26:05 PM PDT 24 Jun 06 12:26:18 PM PDT 24 1558130000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3359203721 Jun 06 12:25:12 PM PDT 24 Jun 06 12:25:24 PM PDT 24 1569050000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3397950393 Jun 06 12:21:16 PM PDT 24 Jun 06 12:21:27 PM PDT 24 1569990000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.639003204 Jun 06 12:21:55 PM PDT 24 Jun 06 12:22:09 PM PDT 24 1560850000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.583406865 Jun 06 12:26:24 PM PDT 24 Jun 06 12:26:34 PM PDT 24 1633590000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1308154372 Jun 06 12:27:54 PM PDT 24 Jun 06 12:28:03 PM PDT 24 1538710000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3654788185 Jun 06 12:21:16 PM PDT 24 Jun 06 12:21:26 PM PDT 24 1393710000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1776480314 Jun 06 12:27:53 PM PDT 24 Jun 06 12:28:05 PM PDT 24 1394630000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3105011871 Jun 06 12:25:45 PM PDT 24 Jun 06 12:25:55 PM PDT 24 1513550000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2504734579 Jun 06 12:27:49 PM PDT 24 Jun 06 12:27:59 PM PDT 24 1408350000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3268831306 Jun 06 12:27:52 PM PDT 24 Jun 06 12:28:03 PM PDT 24 1490730000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2610605039 Jun 06 12:20:57 PM PDT 24 Jun 06 12:21:08 PM PDT 24 1605770000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3899923499 Jun 06 12:21:44 PM PDT 24 Jun 06 12:21:58 PM PDT 24 1518330000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3294489564 Jun 06 12:21:06 PM PDT 24 Jun 06 12:21:15 PM PDT 24 1441250000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.661320901 Jun 06 12:22:20 PM PDT 24 Jun 06 12:22:33 PM PDT 24 1451610000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2243090317 Jun 06 12:21:28 PM PDT 24 Jun 06 12:21:39 PM PDT 24 1453650000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.53060669 Jun 06 12:22:12 PM PDT 24 Jun 06 12:22:21 PM PDT 24 1288930000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.665417126 Jun 06 12:22:20 PM PDT 24 Jun 06 12:22:32 PM PDT 24 1520770000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1371928497 Jun 06 12:22:50 PM PDT 24 Jun 06 12:23:01 PM PDT 24 1352650000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2351180024 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:30 PM PDT 24 1421430000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2216773162 Jun 06 12:26:23 PM PDT 24 Jun 06 12:26:33 PM PDT 24 1288930000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4019182288 Jun 06 12:22:00 PM PDT 24 Jun 06 12:22:12 PM PDT 24 1442850000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3506287625 Jun 06 12:28:25 PM PDT 24 Jun 06 12:28:34 PM PDT 24 1373770000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2041817753 Jun 06 12:27:53 PM PDT 24 Jun 06 12:28:02 PM PDT 24 1602430000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2216825538 Jun 06 12:27:53 PM PDT 24 Jun 06 12:28:06 PM PDT 24 1559870000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4218162890 Jun 06 12:28:18 PM PDT 24 Jun 06 12:28:27 PM PDT 24 1419110000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3840309332 Jun 06 12:27:53 PM PDT 24 Jun 06 12:28:06 PM PDT 24 1524690000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.434036073 Jun 06 12:27:53 PM PDT 24 Jun 06 12:28:06 PM PDT 24 1528690000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1758671767 Jun 06 12:28:02 PM PDT 24 Jun 06 12:28:12 PM PDT 24 1394330000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.331017547 Jun 06 12:28:18 PM PDT 24 Jun 06 12:28:28 PM PDT 24 1427030000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4146997748 Jun 06 12:28:23 PM PDT 24 Jun 06 12:28:34 PM PDT 24 1411990000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.690505448 Jun 06 12:28:04 PM PDT 24 Jun 06 12:28:15 PM PDT 24 1554130000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1242012785 Jun 06 12:23:58 PM PDT 24 Jun 06 12:24:10 PM PDT 24 1344790000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.741080084 Jun 06 12:21:43 PM PDT 24 Jun 06 12:21:55 PM PDT 24 1376890000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4008043964 Jun 06 12:20:54 PM PDT 24 Jun 06 12:56:07 PM PDT 24 336929430000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3968192229 Jun 06 12:20:55 PM PDT 24 Jun 06 01:01:24 PM PDT 24 336979470000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.171614075 Jun 06 12:20:52 PM PDT 24 Jun 06 01:06:42 PM PDT 24 336654710000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4099983279 Jun 06 12:20:50 PM PDT 24 Jun 06 12:54:24 PM PDT 24 336358530000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3680785054 Jun 06 12:20:50 PM PDT 24 Jun 06 01:06:52 PM PDT 24 337008610000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3178708346 Jun 06 12:20:53 PM PDT 24 Jun 06 12:55:51 PM PDT 24 337161710000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2321244651 Jun 06 12:20:50 PM PDT 24 Jun 06 12:53:41 PM PDT 24 336761650000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1767591392 Jun 06 12:20:51 PM PDT 24 Jun 06 12:54:03 PM PDT 24 336511610000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4159297702 Jun 06 12:20:54 PM PDT 24 Jun 06 12:55:55 PM PDT 24 336681910000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.777942410 Jun 06 12:20:53 PM PDT 24 Jun 06 12:56:11 PM PDT 24 336728650000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.336696965 Jun 06 12:20:54 PM PDT 24 Jun 06 01:06:41 PM PDT 24 336746450000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2670773918 Jun 06 12:20:51 PM PDT 24 Jun 06 12:54:06 PM PDT 24 336422850000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3634213881 Jun 06 12:20:55 PM PDT 24 Jun 06 12:55:49 PM PDT 24 336816330000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1202157372 Jun 06 12:20:51 PM PDT 24 Jun 06 01:05:22 PM PDT 24 336821390000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3529381860 Jun 06 12:20:44 PM PDT 24 Jun 06 01:02:53 PM PDT 24 336512210000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2813236829 Jun 06 12:20:55 PM PDT 24 Jun 06 01:01:32 PM PDT 24 337066830000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4218872714 Jun 06 12:20:49 PM PDT 24 Jun 06 12:53:35 PM PDT 24 336949690000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2785518692 Jun 06 12:20:51 PM PDT 24 Jun 06 01:05:43 PM PDT 24 336820610000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3959786295 Jun 06 12:21:05 PM PDT 24 Jun 06 01:07:44 PM PDT 24 336786590000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2905938623 Jun 06 12:20:52 PM PDT 24 Jun 06 01:06:40 PM PDT 24 336941570000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2259630043 Jun 06 12:20:53 PM PDT 24 Jun 06 12:55:59 PM PDT 24 336986970000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.32507302 Jun 06 12:20:50 PM PDT 24 Jun 06 01:07:28 PM PDT 24 336810190000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.502406579 Jun 06 12:20:53 PM PDT 24 Jun 06 01:06:39 PM PDT 24 336584310000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.814576969 Jun 06 12:20:50 PM PDT 24 Jun 06 01:07:29 PM PDT 24 336696670000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2523918117 Jun 06 12:20:48 PM PDT 24 Jun 06 12:54:06 PM PDT 24 336840770000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1850296327 Jun 06 12:20:53 PM PDT 24 Jun 06 12:55:51 PM PDT 24 336409970000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3262537621 Jun 06 12:20:53 PM PDT 24 Jun 06 01:06:38 PM PDT 24 336401530000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2094675575 Jun 06 12:20:55 PM PDT 24 Jun 06 01:01:13 PM PDT 24 337000890000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2389644557 Jun 06 12:20:44 PM PDT 24 Jun 06 01:02:15 PM PDT 24 336880750000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2853040465 Jun 06 12:20:51 PM PDT 24 Jun 06 01:06:02 PM PDT 24 336408810000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.117855608 Jun 06 12:21:05 PM PDT 24 Jun 06 01:07:43 PM PDT 24 336802170000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3385495676 Jun 06 12:20:53 PM PDT 24 Jun 06 01:06:40 PM PDT 24 336993770000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4194768805 Jun 06 12:20:51 PM PDT 24 Jun 06 01:05:12 PM PDT 24 336757050000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3093644648 Jun 06 12:20:51 PM PDT 24 Jun 06 01:06:03 PM PDT 24 336939950000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1984362311 Jun 06 12:20:54 PM PDT 24 Jun 06 12:56:05 PM PDT 24 337030110000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3824973912 Jun 06 12:20:54 PM PDT 24 Jun 06 12:55:50 PM PDT 24 336395330000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.690945094 Jun 06 12:20:44 PM PDT 24 Jun 06 01:02:17 PM PDT 24 336960670000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2300977135 Jun 06 12:20:52 PM PDT 24 Jun 06 01:06:38 PM PDT 24 336923970000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3652392046 Jun 06 12:20:53 PM PDT 24 Jun 06 01:06:36 PM PDT 24 336583930000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1870911683 Jun 06 12:20:53 PM PDT 24 Jun 06 01:06:41 PM PDT 24 337004710000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2670359417 Jun 06 12:20:54 PM PDT 24 Jun 06 12:55:52 PM PDT 24 336967570000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2774343133 Jun 06 12:20:54 PM PDT 24 Jun 06 01:01:34 PM PDT 24 337052170000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1574770091 Jun 06 12:20:46 PM PDT 24 Jun 06 01:00:50 PM PDT 24 336738810000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3704267266 Jun 06 12:20:44 PM PDT 24 Jun 06 01:03:30 PM PDT 24 336617530000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2786451846 Jun 06 12:20:54 PM PDT 24 Jun 06 01:01:36 PM PDT 24 336901930000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1036554589 Jun 06 12:20:54 PM PDT 24 Jun 06 01:06:45 PM PDT 24 337050430000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3232795090 Jun 06 12:20:54 PM PDT 24 Jun 06 01:01:37 PM PDT 24 336958270000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.533201480 Jun 06 12:21:29 PM PDT 24 Jun 06 01:05:15 PM PDT 24 337106910000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.531015901 Jun 06 12:20:51 PM PDT 24 Jun 06 12:54:05 PM PDT 24 337133850000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3216903956 Jun 06 12:20:50 PM PDT 24 Jun 06 12:53:28 PM PDT 24 336829530000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2006802559 Jun 06 12:27:48 PM PDT 24 Jun 06 01:02:51 PM PDT 24 336637370000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3130306556 Jun 06 12:26:24 PM PDT 24 Jun 06 12:51:26 PM PDT 24 336843550000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1421374239 Jun 06 12:20:54 PM PDT 24 Jun 06 12:55:54 PM PDT 24 336884830000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2603075859 Jun 06 12:22:05 PM PDT 24 Jun 06 01:05:51 PM PDT 24 336937590000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3085264856 Jun 06 12:27:49 PM PDT 24 Jun 06 01:00:21 PM PDT 24 336679370000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4047670592 Jun 06 12:28:03 PM PDT 24 Jun 06 12:59:10 PM PDT 24 337066150000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2633841125 Jun 06 12:28:19 PM PDT 24 Jun 06 12:59:55 PM PDT 24 336557230000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1603905482 Jun 06 12:21:30 PM PDT 24 Jun 06 01:05:20 PM PDT 24 337026890000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2255312451 Jun 06 12:21:28 PM PDT 24 Jun 06 01:01:27 PM PDT 24 337106410000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3526814463 Jun 06 12:24:32 PM PDT 24 Jun 06 01:03:53 PM PDT 24 336560630000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2874442251 Jun 06 12:21:25 PM PDT 24 Jun 06 01:01:05 PM PDT 24 336796870000 ps
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T115 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2292199918 Jun 06 12:21:50 PM PDT 24 Jun 06 01:04:59 PM PDT 24 336857170000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2377581909 Jun 06 12:21:34 PM PDT 24 Jun 06 01:05:12 PM PDT 24 336716330000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2136543503 Jun 06 12:27:53 PM PDT 24 Jun 06 12:58:27 PM PDT 24 336927510000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2279219226 Jun 06 12:27:52 PM PDT 24 Jun 06 12:52:50 PM PDT 24 336515990000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2344271223 Jun 06 12:27:52 PM PDT 24 Jun 06 12:56:04 PM PDT 24 336334970000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.716259512 Jun 06 12:20:57 PM PDT 24 Jun 06 12:55:38 PM PDT 24 336618950000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1940956844 Jun 06 12:26:23 PM PDT 24 Jun 06 12:52:02 PM PDT 24 337084830000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3555833440 Jun 06 12:21:59 PM PDT 24 Jun 06 01:06:00 PM PDT 24 336966870000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.610958785 Jun 06 12:27:52 PM PDT 24 Jun 06 12:55:42 PM PDT 24 337118250000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2656108407 Jun 06 12:28:25 PM PDT 24 Jun 06 12:59:05 PM PDT 24 336868970000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2478901302 Jun 06 12:28:24 PM PDT 24 Jun 06 12:58:57 PM PDT 24 336502750000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3138285895 Jun 06 12:23:58 PM PDT 24 Jun 06 01:03:27 PM PDT 24 337029350000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4265474060 Jun 06 12:27:49 PM PDT 24 Jun 06 01:00:20 PM PDT 24 336340730000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3379880470 Jun 06 12:21:56 PM PDT 24 Jun 06 01:01:41 PM PDT 24 337062510000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1899255164 Jun 06 12:23:16 PM PDT 24 Jun 06 01:03:14 PM PDT 24 336729370000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1520541430 Jun 06 12:21:26 PM PDT 24 Jun 06 01:01:08 PM PDT 24 336611370000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3612417054 Jun 06 12:27:06 PM PDT 24 Jun 06 12:55:16 PM PDT 24 336600810000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1650064024 Jun 06 12:22:54 PM PDT 24 Jun 06 01:02:16 PM PDT 24 336493270000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1980526764 Jun 06 12:27:15 PM PDT 24 Jun 06 12:58:44 PM PDT 24 336426490000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2169177322 Jun 06 12:21:51 PM PDT 24 Jun 06 01:05:52 PM PDT 24 336483590000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2530128622 Jun 06 12:23:21 PM PDT 24 Jun 06 01:02:37 PM PDT 24 336732830000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2026965456 Jun 06 12:26:19 PM PDT 24 Jun 06 12:49:45 PM PDT 24 336493550000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2391472495 Jun 06 12:25:43 PM PDT 24 Jun 06 12:53:01 PM PDT 24 336712170000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3131347157 Jun 06 12:26:06 PM PDT 24 Jun 06 01:02:40 PM PDT 24 336406750000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.16755527 Jun 06 12:27:53 PM PDT 24 Jun 06 12:58:24 PM PDT 24 336994110000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2215952196 Jun 06 12:20:54 PM PDT 24 Jun 06 01:01:32 PM PDT 24 336999810000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2710638233 Jun 06 12:26:06 PM PDT 24 Jun 06 01:03:00 PM PDT 24 336865410000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2060101225 Jun 06 12:28:04 PM PDT 24 Jun 06 01:05:13 PM PDT 24 336469610000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1468006769 Jun 06 12:27:54 PM PDT 24 Jun 06 12:57:52 PM PDT 24 336860150000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3773956463 Jun 06 12:22:34 PM PDT 24 Jun 06 01:07:32 PM PDT 24 336503050000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2179336931 Jun 06 12:21:46 PM PDT 24 Jun 06 01:01:58 PM PDT 24 336912090000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4259358723 Jun 06 12:25:45 PM PDT 24 Jun 06 12:53:36 PM PDT 24 336859810000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3533532343 Jun 06 12:28:24 PM PDT 24 Jun 06 12:59:01 PM PDT 24 336992990000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1880538073 Jun 06 12:27:15 PM PDT 24 Jun 06 12:58:51 PM PDT 24 336803110000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2397995038 Jun 06 12:28:18 PM PDT 24 Jun 06 01:00:40 PM PDT 24 336833470000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3707093616 Jun 06 12:28:02 PM PDT 24 Jun 06 01:05:20 PM PDT 24 336610110000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1416607095 Jun 06 12:26:18 PM PDT 24 Jun 06 12:26:28 PM PDT 24 1517170000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1515612740 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:39 PM PDT 24 1547270000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2272175936 Jun 06 12:24:20 PM PDT 24 Jun 06 12:24:33 PM PDT 24 1493730000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.161198535 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:32 PM PDT 24 1479270000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2082704546 Jun 06 12:25:41 PM PDT 24 Jun 06 12:25:53 PM PDT 24 1468890000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1370878848 Jun 06 12:22:37 PM PDT 24 Jun 06 12:22:47 PM PDT 24 1341270000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.186124325 Jun 06 12:22:16 PM PDT 24 Jun 06 12:22:26 PM PDT 24 1094170000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3789004088 Jun 06 12:25:14 PM PDT 24 Jun 06 12:25:24 PM PDT 24 1246930000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3256495346 Jun 06 12:28:03 PM PDT 24 Jun 06 12:28:13 PM PDT 24 1404710000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.188000688 Jun 06 12:28:05 PM PDT 24 Jun 06 12:28:15 PM PDT 24 1545030000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4252315688 Jun 06 12:28:17 PM PDT 24 Jun 06 12:28:25 PM PDT 24 1222930000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2537534550 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:32 PM PDT 24 1507750000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3495177681 Jun 06 12:26:47 PM PDT 24 Jun 06 12:26:57 PM PDT 24 1464530000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2670072110 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:39 PM PDT 24 1448790000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2591787305 Jun 06 12:26:16 PM PDT 24 Jun 06 12:26:24 PM PDT 24 1163230000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3703872062 Jun 06 12:25:27 PM PDT 24 Jun 06 12:25:39 PM PDT 24 1453490000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.170594732 Jun 06 12:28:00 PM PDT 24 Jun 06 12:28:07 PM PDT 24 1221730000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3007551688 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:06 PM PDT 24 1366910000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1481162996 Jun 06 12:24:52 PM PDT 24 Jun 06 12:25:03 PM PDT 24 1303530000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4035229886 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:29 PM PDT 24 1126910000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3293904832 Jun 06 12:26:24 PM PDT 24 Jun 06 12:26:34 PM PDT 24 1498810000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2846590930 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:32 PM PDT 24 1412650000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.760473938 Jun 06 12:26:05 PM PDT 24 Jun 06 12:26:17 PM PDT 24 1560070000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3333116371 Jun 06 12:28:10 PM PDT 24 Jun 06 12:28:18 PM PDT 24 1508770000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2117345850 Jun 06 12:26:47 PM PDT 24 Jun 06 12:27:00 PM PDT 24 1482690000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.196750130 Jun 06 12:26:15 PM PDT 24 Jun 06 12:26:24 PM PDT 24 1356110000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.992006018 Jun 06 12:28:09 PM PDT 24 Jun 06 12:28:19 PM PDT 24 1550650000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2343339823 Jun 06 12:27:34 PM PDT 24 Jun 06 12:27:44 PM PDT 24 1550470000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3481607 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:38 PM PDT 24 1429310000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.462576893 Jun 06 12:27:45 PM PDT 24 Jun 06 12:27:53 PM PDT 24 1471970000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3506628877 Jun 06 12:28:02 PM PDT 24 Jun 06 12:28:12 PM PDT 24 1481450000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4149914806 Jun 06 12:26:18 PM PDT 24 Jun 06 12:26:29 PM PDT 24 1534730000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.974081961 Jun 06 12:28:28 PM PDT 24 Jun 06 12:28:36 PM PDT 24 1476110000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3896643548 Jun 06 12:27:51 PM PDT 24 Jun 06 12:27:59 PM PDT 24 1271970000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1818185015 Jun 06 12:27:56 PM PDT 24 Jun 06 12:28:05 PM PDT 24 1595470000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1545914116 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:36 PM PDT 24 1364010000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2813446330 Jun 06 12:22:21 PM PDT 24 Jun 06 12:22:35 PM PDT 24 1461330000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3133622107 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:32 PM PDT 24 1459450000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.317678708 Jun 06 12:28:17 PM PDT 24 Jun 06 12:28:26 PM PDT 24 1600390000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.783665835 Jun 06 12:28:08 PM PDT 24 Jun 06 12:28:17 PM PDT 24 1293070000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1518258593 Jun 06 12:23:41 PM PDT 24 Jun 06 12:23:53 PM PDT 24 1430810000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1504187039 Jun 06 12:27:34 PM PDT 24 Jun 06 12:27:44 PM PDT 24 1414010000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3720060340 Jun 06 12:24:34 PM PDT 24 Jun 06 12:24:47 PM PDT 24 1440350000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2507073562 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:33 PM PDT 24 1507730000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3464791014 Jun 06 12:27:34 PM PDT 24 Jun 06 12:27:44 PM PDT 24 1464250000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2226232812 Jun 06 12:25:53 PM PDT 24 Jun 06 12:26:08 PM PDT 24 1547030000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3110472168 Jun 06 12:26:35 PM PDT 24 Jun 06 12:26:43 PM PDT 24 1574670000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1270370468 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:34 PM PDT 24 1432250000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4074821487 Jun 06 12:27:55 PM PDT 24 Jun 06 12:28:03 PM PDT 24 1471670000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.986749707 Jun 06 12:28:08 PM PDT 24 Jun 06 12:28:18 PM PDT 24 1502670000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2884585555
Short name T7
Test name
Test status
Simulation time 1434210000 ps
CPU time 5.22 seconds
Started Jun 06 12:21:44 PM PDT 24
Finished Jun 06 12:21:56 PM PDT 24
Peak memory 164468 kb
Host smart-268ada8b-f687-4627-9a3c-eb3b732b5ba3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2884585555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2884585555
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2321244651
Short name T20
Test name
Test status
Simulation time 336761650000 ps
CPU time 792.77 seconds
Started Jun 06 12:20:50 PM PDT 24
Finished Jun 06 12:53:41 PM PDT 24
Peak memory 160216 kb
Host smart-d65e4885-f486-479c-a492-cce5a2ddeec9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2321244651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2321244651
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2603075859
Short name T24
Test name
Test status
Simulation time 336937590000 ps
CPU time 1031.75 seconds
Started Jun 06 12:22:05 PM PDT 24
Finished Jun 06 01:05:51 PM PDT 24
Peak memory 160468 kb
Host smart-72772268-aaa3-444b-88b8-320c12027c50
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2603075859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2603075859
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2874442251
Short name T111
Test name
Test status
Simulation time 336796870000 ps
CPU time 942.55 seconds
Started Jun 06 12:21:25 PM PDT 24
Finished Jun 06 01:01:05 PM PDT 24
Peak memory 160460 kb
Host smart-70535206-beed-4596-8b52-cfa2a897e722
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2874442251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2874442251
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.716259512
Short name T120
Test name
Test status
Simulation time 336618950000 ps
CPU time 868.68 seconds
Started Jun 06 12:20:57 PM PDT 24
Finished Jun 06 12:55:38 PM PDT 24
Peak memory 159712 kb
Host smart-5ed04c9e-00fd-4a2d-8823-76f38611d4e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=716259512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.716259512
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3555833440
Short name T122
Test name
Test status
Simulation time 336966870000 ps
CPU time 1059.22 seconds
Started Jun 06 12:21:59 PM PDT 24
Finished Jun 06 01:06:00 PM PDT 24
Peak memory 160468 kb
Host smart-459d6f1c-68eb-4f76-90b1-4afd049ef04c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3555833440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3555833440
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2136543503
Short name T117
Test name
Test status
Simulation time 336927510000 ps
CPU time 704.03 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:58:27 PM PDT 24
Peak memory 158648 kb
Host smart-28f8fe7c-9bc6-42c8-b56f-8054681ce5b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2136543503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2136543503
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.370182965
Short name T113
Test name
Test status
Simulation time 336557750000 ps
CPU time 981.86 seconds
Started Jun 06 12:21:57 PM PDT 24
Finished Jun 06 01:02:07 PM PDT 24
Peak memory 160460 kb
Host smart-136bd34e-a5a3-4e72-a187-5487893daa32
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=370182965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.370182965
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3379880470
Short name T128
Test name
Test status
Simulation time 337062510000 ps
CPU time 979.88 seconds
Started Jun 06 12:21:56 PM PDT 24
Finished Jun 06 01:01:41 PM PDT 24
Peak memory 160464 kb
Host smart-ce23c12c-b8d7-46cd-a2b2-3e4754eb5d06
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3379880470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3379880470
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.16755527
Short name T139
Test name
Test status
Simulation time 336994110000 ps
CPU time 704.87 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:58:24 PM PDT 24
Peak memory 158776 kb
Host smart-1fe414aa-2f58-4f71-a5e7-a42b524d5511
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=16755527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.16755527
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3773956463
Short name T144
Test name
Test status
Simulation time 336503050000 ps
CPU time 1052.21 seconds
Started Jun 06 12:22:34 PM PDT 24
Finished Jun 06 01:07:32 PM PDT 24
Peak memory 160892 kb
Host smart-e22ee097-d12b-4a86-b5da-293afd5e70a1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3773956463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3773956463
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4047670592
Short name T26
Test name
Test status
Simulation time 337066150000 ps
CPU time 761.48 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:59:10 PM PDT 24
Peak memory 160168 kb
Host smart-faf6b330-a4a0-47a5-9ec5-ec8003fad78d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4047670592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4047670592
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1899255164
Short name T129
Test name
Test status
Simulation time 336729370000 ps
CPU time 974.07 seconds
Started Jun 06 12:23:16 PM PDT 24
Finished Jun 06 01:03:14 PM PDT 24
Peak memory 160708 kb
Host smart-94c538a0-f4b2-4388-bf2c-db652597afec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1899255164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1899255164
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2179336931
Short name T145
Test name
Test status
Simulation time 336912090000 ps
CPU time 955.86 seconds
Started Jun 06 12:21:46 PM PDT 24
Finished Jun 06 01:01:58 PM PDT 24
Peak memory 160468 kb
Host smart-5e4e5fa1-fa1b-4d82-9498-a9813682243c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2179336931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2179336931
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2215952196
Short name T140
Test name
Test status
Simulation time 336999810000 ps
CPU time 925.8 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 01:01:32 PM PDT 24
Peak memory 158992 kb
Host smart-0de7cc6e-9672-4004-b03c-b9b10b70274d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2215952196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2215952196
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2595540660
Short name T114
Test name
Test status
Simulation time 336809690000 ps
CPU time 1004.56 seconds
Started Jun 06 12:26:59 PM PDT 24
Finished Jun 06 01:08:37 PM PDT 24
Peak memory 160904 kb
Host smart-2e94f81b-d96b-4ac9-9fd1-d242395c4a7c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2595540660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2595540660
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2397995038
Short name T149
Test name
Test status
Simulation time 336833470000 ps
CPU time 794.44 seconds
Started Jun 06 12:28:18 PM PDT 24
Finished Jun 06 01:00:40 PM PDT 24
Peak memory 160680 kb
Host smart-2e41367e-fbda-47f3-bdd8-7fccb0d69726
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2397995038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2397995038
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2633841125
Short name T27
Test name
Test status
Simulation time 336557230000 ps
CPU time 775.37 seconds
Started Jun 06 12:28:19 PM PDT 24
Finished Jun 06 12:59:55 PM PDT 24
Peak memory 160680 kb
Host smart-01142354-cc6f-4723-a488-cc7180413a9b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2633841125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2633841125
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2391472495
Short name T137
Test name
Test status
Simulation time 336712170000 ps
CPU time 659.12 seconds
Started Jun 06 12:25:43 PM PDT 24
Finished Jun 06 12:53:01 PM PDT 24
Peak memory 160548 kb
Host smart-1fbc6620-ba0b-44f5-8621-98a4fe36041c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2391472495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2391472495
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2710638233
Short name T141
Test name
Test status
Simulation time 336865410000 ps
CPU time 879.62 seconds
Started Jun 06 12:26:06 PM PDT 24
Finished Jun 06 01:03:00 PM PDT 24
Peak memory 159568 kb
Host smart-29704e65-0fd4-48ec-ba74-92704e66614a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2710638233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2710638233
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3131347157
Short name T138
Test name
Test status
Simulation time 336406750000 ps
CPU time 872.02 seconds
Started Jun 06 12:26:06 PM PDT 24
Finished Jun 06 01:02:40 PM PDT 24
Peak memory 160388 kb
Host smart-c5b24efe-cbde-4ea9-b496-217c99252fee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3131347157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3131347157
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3533532343
Short name T147
Test name
Test status
Simulation time 336992990000 ps
CPU time 729.1 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:59:01 PM PDT 24
Peak memory 160404 kb
Host smart-cf09dd21-2347-4ae0-8887-d1098ab64cfc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3533532343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3533532343
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4259358723
Short name T146
Test name
Test status
Simulation time 336859810000 ps
CPU time 668.25 seconds
Started Jun 06 12:25:45 PM PDT 24
Finished Jun 06 12:53:36 PM PDT 24
Peak memory 160548 kb
Host smart-87903c8f-a915-4842-9d09-8cdf0524a233
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4259358723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4259358723
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1940956844
Short name T121
Test name
Test status
Simulation time 337084830000 ps
CPU time 620.13 seconds
Started Jun 06 12:26:23 PM PDT 24
Finished Jun 06 12:52:02 PM PDT 24
Peak memory 159312 kb
Host smart-a12eb69c-0982-4944-9ba7-31a48839bb9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1940956844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1940956844
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3130306556
Short name T5
Test name
Test status
Simulation time 336843550000 ps
CPU time 602.9 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:51:26 PM PDT 24
Peak memory 160328 kb
Host smart-5fa814c3-7741-47e9-86f4-7da22b6771ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3130306556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3130306556
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1421374239
Short name T6
Test name
Test status
Simulation time 336884830000 ps
CPU time 864.78 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 12:55:54 PM PDT 24
Peak memory 159976 kb
Host smart-0f85004a-6ef3-49c4-89d1-473e4d9421a7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1421374239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1421374239
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.237345215
Short name T112
Test name
Test status
Simulation time 336673170000 ps
CPU time 878.86 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 01:03:07 PM PDT 24
Peak memory 158752 kb
Host smart-06c9f08c-9dc4-4f7d-824a-dbb31d93c2e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=237345215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.237345215
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2478901302
Short name T125
Test name
Test status
Simulation time 336502750000 ps
CPU time 734.95 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:58:57 PM PDT 24
Peak memory 159960 kb
Host smart-90da2bc0-1280-457b-b271-00cb7dc7cf81
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2478901302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2478901302
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3612417054
Short name T131
Test name
Test status
Simulation time 336600810000 ps
CPU time 696.71 seconds
Started Jun 06 12:27:06 PM PDT 24
Finished Jun 06 12:55:16 PM PDT 24
Peak memory 160600 kb
Host smart-3ef0c23b-87e6-45a1-9b22-4e777022866f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3612417054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3612417054
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2656108407
Short name T124
Test name
Test status
Simulation time 336868970000 ps
CPU time 729.54 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:59:05 PM PDT 24
Peak memory 160404 kb
Host smart-d236f943-9249-4f7a-bfc3-66e6205fd77d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2656108407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2656108407
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3526814463
Short name T30
Test name
Test status
Simulation time 336560630000 ps
CPU time 968.08 seconds
Started Jun 06 12:24:32 PM PDT 24
Finished Jun 06 01:03:53 PM PDT 24
Peak memory 160708 kb
Host smart-11b40e52-0514-43ef-8df8-48d7241ea619
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3526814463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3526814463
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3085264856
Short name T25
Test name
Test status
Simulation time 336679370000 ps
CPU time 751.28 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 01:00:21 PM PDT 24
Peak memory 160100 kb
Host smart-7676e32a-54eb-4bb4-8b5a-e906ee1ad655
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3085264856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3085264856
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3707093616
Short name T150
Test name
Test status
Simulation time 336610110000 ps
CPU time 928.53 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 160416 kb
Host smart-4a46ec29-7337-4a39-9bf7-6691f8ee903b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3707093616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3707093616
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3138285895
Short name T126
Test name
Test status
Simulation time 337029350000 ps
CPU time 940.89 seconds
Started Jun 06 12:23:58 PM PDT 24
Finished Jun 06 01:03:27 PM PDT 24
Peak memory 160736 kb
Host smart-877fece1-cf53-4f58-9e7c-472b280ac64d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3138285895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3138285895
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1650064024
Short name T132
Test name
Test status
Simulation time 336493270000 ps
CPU time 979.67 seconds
Started Jun 06 12:22:54 PM PDT 24
Finished Jun 06 01:02:16 PM PDT 24
Peak memory 160668 kb
Host smart-716179f1-d140-446c-867b-fce05607eea7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1650064024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1650064024
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2026965456
Short name T136
Test name
Test status
Simulation time 336493550000 ps
CPU time 564.68 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:49:45 PM PDT 24
Peak memory 160288 kb
Host smart-404d876e-efd9-44f7-b459-372504bfcc55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2026965456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2026965456
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2344271223
Short name T119
Test name
Test status
Simulation time 336334970000 ps
CPU time 670.89 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:56:04 PM PDT 24
Peak memory 159152 kb
Host smart-a846459a-b5b6-4066-aef3-f653eba0e211
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2344271223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2344271223
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2060101225
Short name T142
Test name
Test status
Simulation time 336469610000 ps
CPU time 925.73 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 01:05:13 PM PDT 24
Peak memory 160416 kb
Host smart-1b21cbab-97c0-43ba-b90a-708764df6794
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2060101225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2060101225
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2006802559
Short name T4
Test name
Test status
Simulation time 336637370000 ps
CPU time 852.54 seconds
Started Jun 06 12:27:48 PM PDT 24
Finished Jun 06 01:02:51 PM PDT 24
Peak memory 159372 kb
Host smart-d6be7f15-61af-4ca3-a204-aca7fa94e3ba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2006802559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2006802559
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2292199918
Short name T115
Test name
Test status
Simulation time 336857170000 ps
CPU time 1012.11 seconds
Started Jun 06 12:21:50 PM PDT 24
Finished Jun 06 01:04:59 PM PDT 24
Peak memory 160468 kb
Host smart-8725a029-2de3-4a02-9d48-fac20aa50b72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2292199918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2292199918
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2530128622
Short name T135
Test name
Test status
Simulation time 336732830000 ps
CPU time 964.11 seconds
Started Jun 06 12:23:21 PM PDT 24
Finished Jun 06 01:02:37 PM PDT 24
Peak memory 160708 kb
Host smart-c1549cb8-505f-4faa-b08a-c49d4c9cfea7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2530128622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2530128622
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1880538073
Short name T148
Test name
Test status
Simulation time 336803110000 ps
CPU time 769.12 seconds
Started Jun 06 12:27:15 PM PDT 24
Finished Jun 06 12:58:51 PM PDT 24
Peak memory 160712 kb
Host smart-026fcef6-39cf-41a8-91a3-2cee9a45ada3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1880538073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1880538073
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4265474060
Short name T127
Test name
Test status
Simulation time 336340730000 ps
CPU time 756.24 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 01:00:20 PM PDT 24
Peak memory 160100 kb
Host smart-3af648df-b2d2-481b-b855-74fe85034430
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4265474060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4265474060
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1980526764
Short name T133
Test name
Test status
Simulation time 336426490000 ps
CPU time 748.68 seconds
Started Jun 06 12:27:15 PM PDT 24
Finished Jun 06 12:58:44 PM PDT 24
Peak memory 160712 kb
Host smart-f95675b8-6fe7-4d12-b80c-2677fc0523ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1980526764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1980526764
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2279219226
Short name T118
Test name
Test status
Simulation time 336515990000 ps
CPU time 603.48 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:52:50 PM PDT 24
Peak memory 159888 kb
Host smart-c751cf8b-f9b6-40d8-9fa3-a05384f6404f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2279219226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2279219226
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2377581909
Short name T116
Test name
Test status
Simulation time 336716330000 ps
CPU time 1030.5 seconds
Started Jun 06 12:21:34 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 160468 kb
Host smart-f5eb4cbd-7028-40f6-8565-074b9b71d1bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2377581909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2377581909
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.610958785
Short name T123
Test name
Test status
Simulation time 337118250000 ps
CPU time 666.94 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:55:42 PM PDT 24
Peak memory 159112 kb
Host smart-f21a02fb-af1e-43c0-b66d-1946650eb8f7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=610958785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.610958785
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1603905482
Short name T28
Test name
Test status
Simulation time 337026890000 ps
CPU time 1018.93 seconds
Started Jun 06 12:21:30 PM PDT 24
Finished Jun 06 01:05:20 PM PDT 24
Peak memory 160460 kb
Host smart-3f78e86c-6a4e-4659-ab2f-6327b120f68e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1603905482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1603905482
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1520541430
Short name T130
Test name
Test status
Simulation time 336611370000 ps
CPU time 944.62 seconds
Started Jun 06 12:21:26 PM PDT 24
Finished Jun 06 01:01:08 PM PDT 24
Peak memory 160460 kb
Host smart-07511a35-0090-4f79-baa8-abddc34e47db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1520541430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1520541430
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2255312451
Short name T29
Test name
Test status
Simulation time 337106410000 ps
CPU time 984.08 seconds
Started Jun 06 12:21:28 PM PDT 24
Finished Jun 06 01:01:27 PM PDT 24
Peak memory 160456 kb
Host smart-17cc0473-bda9-439f-92a3-7095817f68c3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2255312451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2255312451
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1468006769
Short name T143
Test name
Test status
Simulation time 336860150000 ps
CPU time 687.02 seconds
Started Jun 06 12:27:54 PM PDT 24
Finished Jun 06 12:57:52 PM PDT 24
Peak memory 160132 kb
Host smart-d368b191-a829-42ca-8085-e061d5b8f333
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1468006769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1468006769
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2169177322
Short name T134
Test name
Test status
Simulation time 336483590000 ps
CPU time 1056.23 seconds
Started Jun 06 12:21:51 PM PDT 24
Finished Jun 06 01:05:52 PM PDT 24
Peak memory 160460 kb
Host smart-0b2983cc-8318-41d5-b28b-da764d92c0d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2169177322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2169177322
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3178708346
Short name T19
Test name
Test status
Simulation time 337161710000 ps
CPU time 864.86 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 12:55:51 PM PDT 24
Peak memory 160696 kb
Host smart-70b793fb-521c-4272-b175-c573741ac4c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3178708346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3178708346
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.117855608
Short name T91
Test name
Test status
Simulation time 336802170000 ps
CPU time 1116.18 seconds
Started Jun 06 12:21:05 PM PDT 24
Finished Jun 06 01:07:43 PM PDT 24
Peak memory 160208 kb
Host smart-1de6a9b0-5d72-4a83-8937-cdab979c4828
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=117855608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.117855608
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3959786295
Short name T79
Test name
Test status
Simulation time 336786590000 ps
CPU time 1114.53 seconds
Started Jun 06 12:21:05 PM PDT 24
Finished Jun 06 01:07:44 PM PDT 24
Peak memory 160216 kb
Host smart-0fb18532-4161-4445-bdff-219278501842
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3959786295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3959786295
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2670359417
Short name T101
Test name
Test status
Simulation time 336967570000 ps
CPU time 844.06 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 12:55:52 PM PDT 24
Peak memory 160712 kb
Host smart-c5265131-3e8a-49b8-a4f5-6cead75d2cae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2670359417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2670359417
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2523918117
Short name T85
Test name
Test status
Simulation time 336840770000 ps
CPU time 806.53 seconds
Started Jun 06 12:20:48 PM PDT 24
Finished Jun 06 12:54:06 PM PDT 24
Peak memory 159748 kb
Host smart-b6683144-8845-484b-aa3a-3f368ee8ef15
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2523918117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2523918117
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3968192229
Short name T15
Test name
Test status
Simulation time 336979470000 ps
CPU time 920.89 seconds
Started Jun 06 12:20:55 PM PDT 24
Finished Jun 06 01:01:24 PM PDT 24
Peak memory 160156 kb
Host smart-4fd0fbc9-f028-4987-b721-5d84e860e922
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3968192229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3968192229
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.814576969
Short name T84
Test name
Test status
Simulation time 336696670000 ps
CPU time 1118.23 seconds
Started Jun 06 12:20:50 PM PDT 24
Finished Jun 06 01:07:29 PM PDT 24
Peak memory 158264 kb
Host smart-5e97aecc-2d64-48c7-ac7d-07fd11c0ddbf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=814576969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.814576969
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2905938623
Short name T80
Test name
Test status
Simulation time 336941570000 ps
CPU time 1109 seconds
Started Jun 06 12:20:52 PM PDT 24
Finished Jun 06 01:06:40 PM PDT 24
Peak memory 160896 kb
Host smart-398270d4-f05f-4595-b867-cc6c6a0ef1af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2905938623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2905938623
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3680785054
Short name T18
Test name
Test status
Simulation time 337008610000 ps
CPU time 1097.58 seconds
Started Jun 06 12:20:50 PM PDT 24
Finished Jun 06 01:06:52 PM PDT 24
Peak memory 158712 kb
Host smart-f85fa3b8-d94b-4c12-9377-c169936f8406
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3680785054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3680785054
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.690945094
Short name T97
Test name
Test status
Simulation time 336960670000 ps
CPU time 976.76 seconds
Started Jun 06 12:20:44 PM PDT 24
Finished Jun 06 01:02:17 PM PDT 24
Peak memory 160900 kb
Host smart-7f588ed1-c34f-4e68-8c65-1af43df52127
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=690945094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.690945094
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2786451846
Short name T105
Test name
Test status
Simulation time 336901930000 ps
CPU time 931.39 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 01:01:36 PM PDT 24
Peak memory 158892 kb
Host smart-7916d398-31c4-4622-a66e-275e36991020
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2786451846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2786451846
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2259630043
Short name T81
Test name
Test status
Simulation time 336986970000 ps
CPU time 834.49 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 12:55:59 PM PDT 24
Peak memory 160688 kb
Host smart-b4a2a8c0-d8d2-46fb-9b1a-b722d632b6be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2259630043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2259630043
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3262537621
Short name T87
Test name
Test status
Simulation time 336401530000 ps
CPU time 1072.62 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 01:06:38 PM PDT 24
Peak memory 160896 kb
Host smart-3e7343d9-f7e3-401f-a323-3018d21abd19
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3262537621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3262537621
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4099983279
Short name T17
Test name
Test status
Simulation time 336358530000 ps
CPU time 817.09 seconds
Started Jun 06 12:20:50 PM PDT 24
Finished Jun 06 12:54:24 PM PDT 24
Peak memory 160224 kb
Host smart-224810f1-5614-4979-97db-0d6c753e7632
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4099983279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4099983279
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2389644557
Short name T89
Test name
Test status
Simulation time 336880750000 ps
CPU time 981.66 seconds
Started Jun 06 12:20:44 PM PDT 24
Finished Jun 06 01:02:15 PM PDT 24
Peak memory 160908 kb
Host smart-e60fa3d5-0eff-4e73-96c1-fe28a6f220d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2389644557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2389644557
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3704267266
Short name T104
Test name
Test status
Simulation time 336617530000 ps
CPU time 1023.6 seconds
Started Jun 06 12:20:44 PM PDT 24
Finished Jun 06 01:03:30 PM PDT 24
Peak memory 160908 kb
Host smart-c39712ec-173d-4d75-bb9b-6fc541d541a4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3704267266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3704267266
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1850296327
Short name T86
Test name
Test status
Simulation time 336409970000 ps
CPU time 847.12 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 12:55:51 PM PDT 24
Peak memory 160652 kb
Host smart-2889d8c0-c0c3-48c1-8d4d-966eeded0487
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1850296327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1850296327
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4008043964
Short name T14
Test name
Test status
Simulation time 336929430000 ps
CPU time 842.71 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 12:56:07 PM PDT 24
Peak memory 160712 kb
Host smart-fdd7c49f-fc02-4d42-a377-b9fa6448cc97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4008043964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4008043964
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2094675575
Short name T88
Test name
Test status
Simulation time 337000890000 ps
CPU time 893.42 seconds
Started Jun 06 12:20:55 PM PDT 24
Finished Jun 06 01:01:13 PM PDT 24
Peak memory 160156 kb
Host smart-db172538-da73-4e17-93cf-4b71d9a7fea8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2094675575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2094675575
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3529381860
Short name T75
Test name
Test status
Simulation time 336512210000 ps
CPU time 998.2 seconds
Started Jun 06 12:20:44 PM PDT 24
Finished Jun 06 01:02:53 PM PDT 24
Peak memory 160908 kb
Host smart-ad0261ea-036a-4eb8-85fa-5cef79a28c86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3529381860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3529381860
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1202157372
Short name T74
Test name
Test status
Simulation time 336821390000 ps
CPU time 1041 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 01:05:22 PM PDT 24
Peak memory 160124 kb
Host smart-95f9eaae-cb45-4a50-a17f-529829479a1c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1202157372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1202157372
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4159297702
Short name T22
Test name
Test status
Simulation time 336681910000 ps
CPU time 845.89 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 12:55:55 PM PDT 24
Peak memory 160044 kb
Host smart-0b32fc5a-c534-4607-8913-02a9c40cdc9e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4159297702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4159297702
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.531015901
Short name T109
Test name
Test status
Simulation time 337133850000 ps
CPU time 799.25 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 12:54:05 PM PDT 24
Peak memory 160216 kb
Host smart-2dce59a2-f387-450f-b274-db9a0d60b06c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=531015901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.531015901
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.32507302
Short name T82
Test name
Test status
Simulation time 336810190000 ps
CPU time 1120.9 seconds
Started Jun 06 12:20:50 PM PDT 24
Finished Jun 06 01:07:28 PM PDT 24
Peak memory 158156 kb
Host smart-1fd2b9b4-1fba-4b14-9eb2-f141983bb67d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=32507302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.32507302
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3385495676
Short name T92
Test name
Test status
Simulation time 336993770000 ps
CPU time 1109.1 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 01:06:40 PM PDT 24
Peak memory 160896 kb
Host smart-714d9e00-e005-4370-9fef-d801eb5844e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3385495676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3385495676
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3824973912
Short name T96
Test name
Test status
Simulation time 336395330000 ps
CPU time 844.13 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 12:55:50 PM PDT 24
Peak memory 160712 kb
Host smart-26ab20d4-8394-4d8e-956f-dc914a4f77bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3824973912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3824973912
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.171614075
Short name T16
Test name
Test status
Simulation time 336654710000 ps
CPU time 1076.78 seconds
Started Jun 06 12:20:52 PM PDT 24
Finished Jun 06 01:06:42 PM PDT 24
Peak memory 160892 kb
Host smart-b57c4397-9245-494f-83c7-c3d88daa898c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=171614075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.171614075
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2813236829
Short name T76
Test name
Test status
Simulation time 337066830000 ps
CPU time 915.68 seconds
Started Jun 06 12:20:55 PM PDT 24
Finished Jun 06 01:01:32 PM PDT 24
Peak memory 160200 kb
Host smart-0d4be726-24ad-4d83-87d6-a9735749de60
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2813236829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2813236829
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3216903956
Short name T110
Test name
Test status
Simulation time 336829530000 ps
CPU time 779.84 seconds
Started Jun 06 12:20:50 PM PDT 24
Finished Jun 06 12:53:28 PM PDT 24
Peak memory 160224 kb
Host smart-135bbf69-4ad5-4e50-89c7-de62b134cb38
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3216903956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3216903956
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.4194768805
Short name T93
Test name
Test status
Simulation time 336757050000 ps
CPU time 1002.26 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 01:05:12 PM PDT 24
Peak memory 160120 kb
Host smart-3315013b-fc58-4795-a7ac-ea23de31be7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4194768805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.4194768805
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.777942410
Short name T23
Test name
Test status
Simulation time 336728650000 ps
CPU time 847.77 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 12:56:11 PM PDT 24
Peak memory 160700 kb
Host smart-30e0d7a3-9ada-4c28-832c-2dcfaccc0146
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=777942410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.777942410
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3093644648
Short name T94
Test name
Test status
Simulation time 336939950000 ps
CPU time 1070.93 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 01:06:03 PM PDT 24
Peak memory 160128 kb
Host smart-d8147e77-a526-4710-8ebf-79fbea82d9db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3093644648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3093644648
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3634213881
Short name T73
Test name
Test status
Simulation time 336816330000 ps
CPU time 843.08 seconds
Started Jun 06 12:20:55 PM PDT 24
Finished Jun 06 12:55:49 PM PDT 24
Peak memory 160712 kb
Host smart-29184aa5-3f98-4a6e-8e82-5956ddc69409
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3634213881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3634213881
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1767591392
Short name T21
Test name
Test status
Simulation time 336511610000 ps
CPU time 798.51 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 12:54:03 PM PDT 24
Peak memory 160216 kb
Host smart-01e9dd52-0ef9-4d5e-8129-aa08b38109e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1767591392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1767591392
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.533201480
Short name T108
Test name
Test status
Simulation time 337106910000 ps
CPU time 1032.58 seconds
Started Jun 06 12:21:29 PM PDT 24
Finished Jun 06 01:05:15 PM PDT 24
Peak memory 160468 kb
Host smart-892b16eb-fada-4c41-a05b-64adffe1cfe0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=533201480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.533201480
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2853040465
Short name T90
Test name
Test status
Simulation time 336408810000 ps
CPU time 1062.26 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 01:06:02 PM PDT 24
Peak memory 160124 kb
Host smart-a628a8bd-5c1f-4474-a4d9-e0731f756dd9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2853040465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2853040465
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1036554589
Short name T106
Test name
Test status
Simulation time 337050430000 ps
CPU time 1071.26 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 01:06:45 PM PDT 24
Peak memory 160896 kb
Host smart-6b08513a-1165-492e-93a8-1fc5a88cbfeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1036554589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1036554589
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.4218872714
Short name T77
Test name
Test status
Simulation time 336949690000 ps
CPU time 787.85 seconds
Started Jun 06 12:20:49 PM PDT 24
Finished Jun 06 12:53:35 PM PDT 24
Peak memory 160220 kb
Host smart-e51050df-807b-4ec3-ad51-24f0058b69d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4218872714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.4218872714
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2670773918
Short name T72
Test name
Test status
Simulation time 336422850000 ps
CPU time 804.63 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 12:54:06 PM PDT 24
Peak memory 160224 kb
Host smart-a710dc0e-b955-4ab0-a8c8-269bd612561b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2670773918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2670773918
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.336696965
Short name T71
Test name
Test status
Simulation time 336746450000 ps
CPU time 1080.75 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 01:06:41 PM PDT 24
Peak memory 160892 kb
Host smart-4443b294-12a3-4ee4-9f43-98815191e57c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=336696965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.336696965
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.502406579
Short name T83
Test name
Test status
Simulation time 336584310000 ps
CPU time 1082.44 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 01:06:39 PM PDT 24
Peak memory 160892 kb
Host smart-f73c6296-a4de-4902-93ef-1fad9dd9486e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=502406579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.502406579
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2774343133
Short name T102
Test name
Test status
Simulation time 337052170000 ps
CPU time 912.44 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 01:01:34 PM PDT 24
Peak memory 158820 kb
Host smart-5a570370-3ed5-48bd-8156-b9ebfe5fa6af
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2774343133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2774343133
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1984362311
Short name T95
Test name
Test status
Simulation time 337030110000 ps
CPU time 852.97 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 12:56:05 PM PDT 24
Peak memory 160708 kb
Host smart-a59242b5-f22b-4de5-a3ec-ab2a3c2e9f54
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1984362311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1984362311
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1574770091
Short name T103
Test name
Test status
Simulation time 336738810000 ps
CPU time 954.12 seconds
Started Jun 06 12:20:46 PM PDT 24
Finished Jun 06 01:00:50 PM PDT 24
Peak memory 159740 kb
Host smart-c3f93ca6-b8f8-42fe-ac7c-39f0e1318a17
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1574770091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1574770091
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1870911683
Short name T100
Test name
Test status
Simulation time 337004710000 ps
CPU time 1085.93 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 01:06:41 PM PDT 24
Peak memory 160888 kb
Host smart-c9c0e715-7253-4fd2-867d-134f630b1cd4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1870911683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1870911683
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3232795090
Short name T107
Test name
Test status
Simulation time 336958270000 ps
CPU time 929.1 seconds
Started Jun 06 12:20:54 PM PDT 24
Finished Jun 06 01:01:37 PM PDT 24
Peak memory 159016 kb
Host smart-3cb0da3e-441a-46bb-81fb-5ff6478aebcc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3232795090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3232795090
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3652392046
Short name T99
Test name
Test status
Simulation time 336583930000 ps
CPU time 1111.78 seconds
Started Jun 06 12:20:53 PM PDT 24
Finished Jun 06 01:06:36 PM PDT 24
Peak memory 160888 kb
Host smart-061a5a41-2eb5-48b1-b5e8-ffb7721cfbba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652392046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3652392046
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2785518692
Short name T78
Test name
Test status
Simulation time 336820610000 ps
CPU time 1030.92 seconds
Started Jun 06 12:20:51 PM PDT 24
Finished Jun 06 01:05:43 PM PDT 24
Peak memory 160140 kb
Host smart-60c8f631-0ff9-4b83-bc48-7749f8c6ddf6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2785518692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2785518692
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2300977135
Short name T98
Test name
Test status
Simulation time 336923970000 ps
CPU time 1113.08 seconds
Started Jun 06 12:20:52 PM PDT 24
Finished Jun 06 01:06:38 PM PDT 24
Peak memory 160888 kb
Host smart-d3491b84-f39d-4570-a821-e0f30f9fefad
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2300977135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2300977135
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.186124325
Short name T157
Test name
Test status
Simulation time 1094170000 ps
CPU time 4.35 seconds
Started Jun 06 12:22:16 PM PDT 24
Finished Jun 06 12:22:26 PM PDT 24
Peak memory 164744 kb
Host smart-c27fc189-7ea8-4f2e-90e0-219a20937755
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=186124325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.186124325
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3007551688
Short name T168
Test name
Test status
Simulation time 1366910000 ps
CPU time 3.21 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:06 PM PDT 24
Peak memory 164616 kb
Host smart-1ffc1e3a-3b10-4682-b4ae-babf564cc626
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007551688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3007551688
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2846590930
Short name T172
Test name
Test status
Simulation time 1412650000 ps
CPU time 4.21 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 163580 kb
Host smart-dd3a2d5e-62b6-4b4c-a37f-44ec1c4aea65
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2846590930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2846590930
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2507073562
Short name T194
Test name
Test status
Simulation time 1507730000 ps
CPU time 4.27 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:33 PM PDT 24
Peak memory 164468 kb
Host smart-045b38f8-a330-477b-902a-3480939d75aa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2507073562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2507073562
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.161198535
Short name T154
Test name
Test status
Simulation time 1479270000 ps
CPU time 4.08 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 163644 kb
Host smart-5e25ff19-7da0-40fc-a656-bf08461f3942
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161198535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.161198535
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2537534550
Short name T162
Test name
Test status
Simulation time 1507750000 ps
CPU time 4.22 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 163132 kb
Host smart-32e20daa-5be1-412b-a05c-a74edb4812f7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2537534550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2537534550
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.170594732
Short name T167
Test name
Test status
Simulation time 1221730000 ps
CPU time 2.57 seconds
Started Jun 06 12:28:00 PM PDT 24
Finished Jun 06 12:28:07 PM PDT 24
Peak memory 164488 kb
Host smart-4626563c-0865-42fd-99f1-398610871ae2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170594732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.170594732
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3133622107
Short name T188
Test name
Test status
Simulation time 1459450000 ps
CPU time 5.22 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 164836 kb
Host smart-51ee25b9-92e9-4de1-a16c-c09ee07a51bb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133622107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3133622107
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1818185015
Short name T185
Test name
Test status
Simulation time 1595470000 ps
CPU time 3.6 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:28:05 PM PDT 24
Peak memory 163468 kb
Host smart-b810778c-0606-4709-b7ab-006b6bad3014
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1818185015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1818185015
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.188000688
Short name T160
Test name
Test status
Simulation time 1545030000 ps
CPU time 3.69 seconds
Started Jun 06 12:28:05 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 164544 kb
Host smart-760ce0a4-db60-4b8b-af45-b9cb10edcce4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=188000688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.188000688
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3256495346
Short name T159
Test name
Test status
Simulation time 1404710000 ps
CPU time 3.68 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 163832 kb
Host smart-59a8c294-f586-4296-9d2f-851a5255899a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3256495346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3256495346
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.992006018
Short name T177
Test name
Test status
Simulation time 1550650000 ps
CPU time 3.91 seconds
Started Jun 06 12:28:09 PM PDT 24
Finished Jun 06 12:28:19 PM PDT 24
Peak memory 164536 kb
Host smart-6754eb2c-f2cb-4436-b1d2-9ed75a9820fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=992006018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.992006018
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2813446330
Short name T187
Test name
Test status
Simulation time 1461330000 ps
CPU time 5.59 seconds
Started Jun 06 12:22:21 PM PDT 24
Finished Jun 06 12:22:35 PM PDT 24
Peak memory 164764 kb
Host smart-f4e9681c-7482-4bdf-8bf3-628b38e62c39
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813446330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2813446330
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.783665835
Short name T190
Test name
Test status
Simulation time 1293070000 ps
CPU time 3.64 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:17 PM PDT 24
Peak memory 163160 kb
Host smart-1a3cf372-510b-4cd3-9942-f28bba99729f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=783665835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.783665835
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3333116371
Short name T174
Test name
Test status
Simulation time 1508770000 ps
CPU time 3.18 seconds
Started Jun 06 12:28:10 PM PDT 24
Finished Jun 06 12:28:18 PM PDT 24
Peak memory 164796 kb
Host smart-82a1a5f8-2486-44c8-b5f9-ee7d7c1426ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3333116371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3333116371
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3720060340
Short name T193
Test name
Test status
Simulation time 1440350000 ps
CPU time 5.55 seconds
Started Jun 06 12:24:34 PM PDT 24
Finished Jun 06 12:24:47 PM PDT 24
Peak memory 164776 kb
Host smart-a628d86a-1198-447f-9818-fc782ee61d89
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3720060340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3720060340
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3896643548
Short name T184
Test name
Test status
Simulation time 1271970000 ps
CPU time 3.06 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 163192 kb
Host smart-42951a98-e922-43c4-bd5f-6caa0ad83e8e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3896643548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3896643548
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.986749707
Short name T200
Test name
Test status
Simulation time 1502670000 ps
CPU time 3.91 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:18 PM PDT 24
Peak memory 164436 kb
Host smart-7b666f98-841a-4bf4-9e06-59717b633600
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=986749707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.986749707
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2343339823
Short name T178
Test name
Test status
Simulation time 1550470000 ps
CPU time 3.97 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 164120 kb
Host smart-ab816b99-0ec7-49d2-b425-e09be6522149
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2343339823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2343339823
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.760473938
Short name T173
Test name
Test status
Simulation time 1560070000 ps
CPU time 5.55 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:26:17 PM PDT 24
Peak memory 164984 kb
Host smart-e8c313d1-b8d7-4de2-97ac-13cf9eb67d63
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=760473938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.760473938
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1504187039
Short name T192
Test name
Test status
Simulation time 1414010000 ps
CPU time 3.65 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 164672 kb
Host smart-9316721e-7df2-44c9-ad59-11fc03eda350
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504187039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1504187039
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3464791014
Short name T195
Test name
Test status
Simulation time 1464250000 ps
CPU time 3.88 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 164256 kb
Host smart-8c3980d3-c282-4c33-bd58-576f21f7d9b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3464791014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3464791014
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3495177681
Short name T163
Test name
Test status
Simulation time 1464530000 ps
CPU time 4.58 seconds
Started Jun 06 12:26:47 PM PDT 24
Finished Jun 06 12:26:57 PM PDT 24
Peak memory 164784 kb
Host smart-d069c197-849d-4339-842d-6790c1042027
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3495177681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3495177681
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4074821487
Short name T199
Test name
Test status
Simulation time 1471670000 ps
CPU time 3.27 seconds
Started Jun 06 12:27:55 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 164600 kb
Host smart-14b5a928-bfbb-4e96-ba65-56e35e492416
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4074821487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.4074821487
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2117345850
Short name T175
Test name
Test status
Simulation time 1482690000 ps
CPU time 5.63 seconds
Started Jun 06 12:26:47 PM PDT 24
Finished Jun 06 12:27:00 PM PDT 24
Peak memory 164988 kb
Host smart-84b7652d-3cbd-41dd-a140-11f7f7b802e8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2117345850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2117345850
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3506628877
Short name T181
Test name
Test status
Simulation time 1481450000 ps
CPU time 3.87 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:12 PM PDT 24
Peak memory 163040 kb
Host smart-c57f5735-ea72-4ab5-9fe8-6b54673a75ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3506628877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3506628877
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1545914116
Short name T186
Test name
Test status
Simulation time 1364010000 ps
CPU time 2.7 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:36 PM PDT 24
Peak memory 164740 kb
Host smart-b6e48aee-86a7-4a4f-8774-554daab11147
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1545914116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1545914116
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3481607
Short name T179
Test name
Test status
Simulation time 1429310000 ps
CPU time 3.72 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 163452 kb
Host smart-860c39c4-b08f-41e5-8291-7222c7bbce76
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3481607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3481607
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2591787305
Short name T165
Test name
Test status
Simulation time 1163230000 ps
CPU time 3.34 seconds
Started Jun 06 12:26:16 PM PDT 24
Finished Jun 06 12:26:24 PM PDT 24
Peak memory 164444 kb
Host smart-43aaf57d-2645-454c-9f3f-feed598c7b03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2591787305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2591787305
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1518258593
Short name T191
Test name
Test status
Simulation time 1430810000 ps
CPU time 4.69 seconds
Started Jun 06 12:23:41 PM PDT 24
Finished Jun 06 12:23:53 PM PDT 24
Peak memory 164988 kb
Host smart-4782abe5-f742-4b38-a171-55f4ba2250c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518258593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1518258593
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.196750130
Short name T176
Test name
Test status
Simulation time 1356110000 ps
CPU time 3.79 seconds
Started Jun 06 12:26:15 PM PDT 24
Finished Jun 06 12:26:24 PM PDT 24
Peak memory 162968 kb
Host smart-0bfaedc9-bb7d-4217-83d6-df0572d044e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196750130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.196750130
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3789004088
Short name T158
Test name
Test status
Simulation time 1246930000 ps
CPU time 4.53 seconds
Started Jun 06 12:25:14 PM PDT 24
Finished Jun 06 12:25:24 PM PDT 24
Peak memory 164780 kb
Host smart-eb845578-b96e-483e-8658-fde8ee9be4ba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3789004088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3789004088
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1515612740
Short name T152
Test name
Test status
Simulation time 1547270000 ps
CPU time 4.13 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:39 PM PDT 24
Peak memory 163268 kb
Host smart-41674f2a-da0a-4f61-9e5b-8eafc3480ad1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1515612740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1515612740
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3293904832
Short name T171
Test name
Test status
Simulation time 1498810000 ps
CPU time 3.57 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:34 PM PDT 24
Peak memory 162936 kb
Host smart-7bc8b47f-c7af-4c4c-8e7b-e2303988c268
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3293904832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3293904832
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.4252315688
Short name T161
Test name
Test status
Simulation time 1222930000 ps
CPU time 3.23 seconds
Started Jun 06 12:28:17 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 164900 kb
Host smart-21eaa363-4e55-4044-9573-98cd67072949
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252315688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.4252315688
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2670072110
Short name T164
Test name
Test status
Simulation time 1448790000 ps
CPU time 3.82 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:39 PM PDT 24
Peak memory 164408 kb
Host smart-ebcc7dbd-f9a5-4648-858d-768604a834ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670072110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2670072110
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1370878848
Short name T156
Test name
Test status
Simulation time 1341270000 ps
CPU time 4.31 seconds
Started Jun 06 12:22:37 PM PDT 24
Finished Jun 06 12:22:47 PM PDT 24
Peak memory 164724 kb
Host smart-7106193a-6ee7-4c2f-bf33-443010b72bf3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1370878848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1370878848
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4149914806
Short name T182
Test name
Test status
Simulation time 1534730000 ps
CPU time 3.78 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:26:29 PM PDT 24
Peak memory 162992 kb
Host smart-165fa840-afbc-4027-a830-5f218e4fad98
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4149914806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.4149914806
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4035229886
Short name T170
Test name
Test status
Simulation time 1126910000 ps
CPU time 2.74 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:29 PM PDT 24
Peak memory 164280 kb
Host smart-5f7c4d09-2425-444c-8b84-b28831c0f01d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4035229886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.4035229886
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2272175936
Short name T153
Test name
Test status
Simulation time 1493730000 ps
CPU time 5.34 seconds
Started Jun 06 12:24:20 PM PDT 24
Finished Jun 06 12:24:33 PM PDT 24
Peak memory 164768 kb
Host smart-6e46b909-3a75-4dcc-89b7-5e99815f9fcd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2272175936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2272175936
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1416607095
Short name T151
Test name
Test status
Simulation time 1517170000 ps
CPU time 3.28 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:26:28 PM PDT 24
Peak memory 162772 kb
Host smart-523753be-da55-4c69-aecf-1b257d178e3a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1416607095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1416607095
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.462576893
Short name T180
Test name
Test status
Simulation time 1471970000 ps
CPU time 3.18 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:27:53 PM PDT 24
Peak memory 163384 kb
Host smart-e2b60310-461f-4820-8c09-1b7f244ad2a5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=462576893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.462576893
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3110472168
Short name T197
Test name
Test status
Simulation time 1574670000 ps
CPU time 2.88 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:26:43 PM PDT 24
Peak memory 164736 kb
Host smart-0dcb0e3c-f836-429f-a5f1-bab75df49d05
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3110472168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3110472168
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1481162996
Short name T169
Test name
Test status
Simulation time 1303530000 ps
CPU time 4.77 seconds
Started Jun 06 12:24:52 PM PDT 24
Finished Jun 06 12:25:03 PM PDT 24
Peak memory 164780 kb
Host smart-61ebca10-c738-46c0-857e-7d95c4858051
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1481162996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1481162996
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1270370468
Short name T198
Test name
Test status
Simulation time 1432250000 ps
CPU time 3.27 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:34 PM PDT 24
Peak memory 164468 kb
Host smart-1124bb71-8207-418c-a81f-2b2eebcf210f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1270370468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1270370468
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.974081961
Short name T183
Test name
Test status
Simulation time 1476110000 ps
CPU time 2.86 seconds
Started Jun 06 12:28:28 PM PDT 24
Finished Jun 06 12:28:36 PM PDT 24
Peak memory 164716 kb
Host smart-8387ffb6-a761-4283-9656-9d4702055167
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974081961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.974081961
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2082704546
Short name T155
Test name
Test status
Simulation time 1468890000 ps
CPU time 5.56 seconds
Started Jun 06 12:25:41 PM PDT 24
Finished Jun 06 12:25:53 PM PDT 24
Peak memory 164836 kb
Host smart-b6954ca7-8d1e-4784-b2ab-1929c9cd000e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2082704546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2082704546
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3703872062
Short name T166
Test name
Test status
Simulation time 1453490000 ps
CPU time 5.24 seconds
Started Jun 06 12:25:27 PM PDT 24
Finished Jun 06 12:25:39 PM PDT 24
Peak memory 164780 kb
Host smart-7d9260da-44be-4382-bf6e-1da60f74e76e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3703872062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3703872062
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.317678708
Short name T189
Test name
Test status
Simulation time 1600390000 ps
CPU time 3.67 seconds
Started Jun 06 12:28:17 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 163440 kb
Host smart-1c0af66d-4810-4878-ac50-17b92d79982e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=317678708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.317678708
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2226232812
Short name T196
Test name
Test status
Simulation time 1547030000 ps
CPU time 6.06 seconds
Started Jun 06 12:25:53 PM PDT 24
Finished Jun 06 12:26:08 PM PDT 24
Peak memory 164772 kb
Host smart-110408f7-8e2a-4842-bc4f-78a5b5926c03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2226232812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2226232812
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.665417126
Short name T54
Test name
Test status
Simulation time 1520770000 ps
CPU time 5.34 seconds
Started Jun 06 12:22:20 PM PDT 24
Finished Jun 06 12:22:32 PM PDT 24
Peak memory 164552 kb
Host smart-37fd3493-947e-48d0-b952-5bf79a620efd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=665417126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.665417126
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3294489564
Short name T50
Test name
Test status
Simulation time 1441250000 ps
CPU time 3.55 seconds
Started Jun 06 12:21:06 PM PDT 24
Finished Jun 06 12:21:15 PM PDT 24
Peak memory 164304 kb
Host smart-3df6aace-328c-4a6b-9c74-45f70e15c06e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3294489564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3294489564
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3840309332
Short name T63
Test name
Test status
Simulation time 1524690000 ps
CPU time 4.93 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:06 PM PDT 24
Peak memory 162448 kb
Host smart-e795d827-297f-4198-a02c-c88edfa1576d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3840309332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3840309332
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.639003204
Short name T40
Test name
Test status
Simulation time 1560850000 ps
CPU time 6.09 seconds
Started Jun 06 12:21:55 PM PDT 24
Finished Jun 06 12:22:09 PM PDT 24
Peak memory 164460 kb
Host smart-1b10b77c-93f1-46d0-88dd-80e59e185955
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=639003204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.639003204
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.434036073
Short name T64
Test name
Test status
Simulation time 1528690000 ps
CPU time 4.88 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:06 PM PDT 24
Peak memory 162368 kb
Host smart-2e828d85-fa85-49f8-b860-2ed0130d1948
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=434036073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.434036073
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1213996537
Short name T1
Test name
Test status
Simulation time 1543410000 ps
CPU time 3.55 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:12 PM PDT 24
Peak memory 164188 kb
Host smart-6ec966bf-371d-4188-8b0c-b5925c6bd921
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1213996537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1213996537
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1758671767
Short name T65
Test name
Test status
Simulation time 1394330000 ps
CPU time 3.66 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:12 PM PDT 24
Peak memory 162984 kb
Host smart-d801aba4-2ef5-46c5-bc20-5bd2f6dec5db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1758671767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1758671767
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3359203721
Short name T38
Test name
Test status
Simulation time 1569050000 ps
CPU time 5.07 seconds
Started Jun 06 12:25:12 PM PDT 24
Finished Jun 06 12:25:24 PM PDT 24
Peak memory 164988 kb
Host smart-0b1f8955-76cc-4650-abf6-c2eb752bcb45
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3359203721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3359203721
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.83047670
Short name T36
Test name
Test status
Simulation time 1204790000 ps
CPU time 4.62 seconds
Started Jun 06 12:22:56 PM PDT 24
Finished Jun 06 12:23:06 PM PDT 24
Peak memory 164784 kb
Host smart-b8a5c1ac-6ec5-4870-908b-dc89e8c5509a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=83047670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.83047670
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2835428133
Short name T12
Test name
Test status
Simulation time 1410730000 ps
CPU time 4.45 seconds
Started Jun 06 12:21:50 PM PDT 24
Finished Jun 06 12:22:01 PM PDT 24
Peak memory 164468 kb
Host smart-85976964-dc9f-41d3-b328-e6a5f3a9fbf6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2835428133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2835428133
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2489245353
Short name T11
Test name
Test status
Simulation time 1423570000 ps
CPU time 5.59 seconds
Started Jun 06 12:23:28 PM PDT 24
Finished Jun 06 12:23:41 PM PDT 24
Peak memory 164768 kb
Host smart-273da90a-bcec-451a-831e-7dcd20120637
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2489245353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2489245353
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2684183301
Short name T31
Test name
Test status
Simulation time 1506530000 ps
CPU time 4.45 seconds
Started Jun 06 12:21:17 PM PDT 24
Finished Jun 06 12:21:28 PM PDT 24
Peak memory 164256 kb
Host smart-b2100a9c-2d20-45c8-b73a-c0fbd39f2467
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2684183301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2684183301
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4218162890
Short name T62
Test name
Test status
Simulation time 1419110000 ps
CPU time 3.68 seconds
Started Jun 06 12:28:18 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 164768 kb
Host smart-37f6e09d-2c09-4dfa-b040-30b7526c3a00
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4218162890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4218162890
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.331017547
Short name T66
Test name
Test status
Simulation time 1427030000 ps
CPU time 4.11 seconds
Started Jun 06 12:28:18 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 164760 kb
Host smart-54861f39-0f78-40b7-aecc-993a3b96b578
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=331017547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.331017547
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3397950393
Short name T39
Test name
Test status
Simulation time 1569990000 ps
CPU time 4.82 seconds
Started Jun 06 12:21:16 PM PDT 24
Finished Jun 06 12:21:27 PM PDT 24
Peak memory 164256 kb
Host smart-c1151c22-e0a0-463c-b88e-6b0a49a60a3b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3397950393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3397950393
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1242012785
Short name T69
Test name
Test status
Simulation time 1344790000 ps
CPU time 4.86 seconds
Started Jun 06 12:23:58 PM PDT 24
Finished Jun 06 12:24:10 PM PDT 24
Peak memory 164772 kb
Host smart-d5b7077f-465f-4aed-a89f-7a7e5c5c6a7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1242012785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1242012785
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3105011871
Short name T45
Test name
Test status
Simulation time 1513550000 ps
CPU time 3.8 seconds
Started Jun 06 12:25:45 PM PDT 24
Finished Jun 06 12:25:55 PM PDT 24
Peak memory 164576 kb
Host smart-a8785e19-c0e7-45c3-bbb4-a53ea5406992
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105011871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3105011871
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1376721446
Short name T9
Test name
Test status
Simulation time 1479290000 ps
CPU time 5.66 seconds
Started Jun 06 12:23:28 PM PDT 24
Finished Jun 06 12:23:41 PM PDT 24
Peak memory 164768 kb
Host smart-97cb06d1-dd27-4bfd-ab93-c762791a8bf5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1376721446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1376721446
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.4193585192
Short name T10
Test name
Test status
Simulation time 1226450000 ps
CPU time 4.09 seconds
Started Jun 06 12:23:28 PM PDT 24
Finished Jun 06 12:23:38 PM PDT 24
Peak memory 164768 kb
Host smart-107a47f9-7cf2-4235-9778-ed95ebe47c4c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193585192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.4193585192
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4056341772
Short name T35
Test name
Test status
Simulation time 1464370000 ps
CPU time 4.73 seconds
Started Jun 06 12:23:42 PM PDT 24
Finished Jun 06 12:23:54 PM PDT 24
Peak memory 164768 kb
Host smart-f06fd42d-a6d4-4f02-8ed2-f66d341561ff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056341772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4056341772
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2216773162
Short name T57
Test name
Test status
Simulation time 1288930000 ps
CPU time 3.54 seconds
Started Jun 06 12:26:23 PM PDT 24
Finished Jun 06 12:26:33 PM PDT 24
Peak memory 163296 kb
Host smart-6bffbd9b-8c49-4b97-aff7-57cf778a7774
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216773162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2216773162
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2383332904
Short name T37
Test name
Test status
Simulation time 1558130000 ps
CPU time 5.63 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:26:18 PM PDT 24
Peak memory 162312 kb
Host smart-7a09028a-2f4c-43a2-905e-1ec07f616d80
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383332904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2383332904
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4019182288
Short name T58
Test name
Test status
Simulation time 1442850000 ps
CPU time 5.27 seconds
Started Jun 06 12:22:00 PM PDT 24
Finished Jun 06 12:22:12 PM PDT 24
Peak memory 164552 kb
Host smart-94f7e636-9820-4cfb-aa18-c4532ec2c126
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4019182288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.4019182288
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.583406865
Short name T41
Test name
Test status
Simulation time 1633590000 ps
CPU time 3.9 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:34 PM PDT 24
Peak memory 163800 kb
Host smart-5342eeec-6bd7-4fc1-85d4-c9a269963ca5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=583406865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.583406865
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3506287625
Short name T59
Test name
Test status
Simulation time 1373770000 ps
CPU time 3.68 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 164480 kb
Host smart-59e7d0ad-5ac7-4e91-be7e-fa00e84e0110
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3506287625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3506287625
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.661320901
Short name T51
Test name
Test status
Simulation time 1451610000 ps
CPU time 5.59 seconds
Started Jun 06 12:22:20 PM PDT 24
Finished Jun 06 12:22:33 PM PDT 24
Peak memory 164756 kb
Host smart-e78531fb-8d67-4305-aa8f-1e16ce6806dc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=661320901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.661320901
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1371928497
Short name T55
Test name
Test status
Simulation time 1352650000 ps
CPU time 4.92 seconds
Started Jun 06 12:22:50 PM PDT 24
Finished Jun 06 12:23:01 PM PDT 24
Peak memory 164768 kb
Host smart-d0dd5374-cf76-4ca8-9f3d-db57df76ade7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1371928497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1371928497
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2504734579
Short name T46
Test name
Test status
Simulation time 1408350000 ps
CPU time 3.97 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 164140 kb
Host smart-89eef9b3-1d1a-4292-a452-da96d0aa97d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2504734579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2504734579
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2567376099
Short name T2
Test name
Test status
Simulation time 1573050000 ps
CPU time 4.19 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 164436 kb
Host smart-17d8bacf-f554-462d-a12d-88894e4b4135
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2567376099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2567376099
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.4146997748
Short name T67
Test name
Test status
Simulation time 1411990000 ps
CPU time 4.33 seconds
Started Jun 06 12:28:23 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 163536 kb
Host smart-e18ff358-b419-4cef-bd4c-715fe7d0c01a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4146997748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.4146997748
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.952161689
Short name T34
Test name
Test status
Simulation time 1424910000 ps
CPU time 4.08 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:31 PM PDT 24
Peak memory 164428 kb
Host smart-6cb1cfa9-398d-4eb0-b7b1-4e4b847d0e80
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=952161689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.952161689
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2654455439
Short name T33
Test name
Test status
Simulation time 1512650000 ps
CPU time 4.13 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:30 PM PDT 24
Peak memory 162460 kb
Host smart-1bbcc9b5-c834-4706-b2b6-7cc95a0184f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2654455439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2654455439
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2295125219
Short name T32
Test name
Test status
Simulation time 1198130000 ps
CPU time 3.48 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:29 PM PDT 24
Peak memory 164236 kb
Host smart-f1ff31fa-c1dc-4ec2-9aa4-d13fe456a2cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2295125219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2295125219
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3268831306
Short name T47
Test name
Test status
Simulation time 1490730000 ps
CPU time 3.96 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 162896 kb
Host smart-3d51dc7c-ef4e-4a05-b149-21ad379897cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3268831306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3268831306
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2351180024
Short name T56
Test name
Test status
Simulation time 1421430000 ps
CPU time 3.97 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:30 PM PDT 24
Peak memory 162376 kb
Host smart-eb902ed4-4371-462b-9d4e-49ac6f647900
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2351180024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2351180024
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.690505448
Short name T68
Test name
Test status
Simulation time 1554130000 ps
CPU time 4.35 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 164428 kb
Host smart-071aeb9f-56d5-4808-8cf8-c4900a7f7d6c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=690505448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.690505448
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2280301127
Short name T8
Test name
Test status
Simulation time 1219010000 ps
CPU time 3.65 seconds
Started Jun 06 12:27:48 PM PDT 24
Finished Jun 06 12:27:57 PM PDT 24
Peak memory 163944 kb
Host smart-5af97817-d347-4f45-a23d-9ed3ec03ab02
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2280301127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2280301127
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3469865307
Short name T3
Test name
Test status
Simulation time 1393770000 ps
CPU time 3.7 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 164124 kb
Host smart-3315029a-53b5-44ab-9d80-e68ff926284e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3469865307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3469865307
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2041817753
Short name T60
Test name
Test status
Simulation time 1602430000 ps
CPU time 3.37 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:02 PM PDT 24
Peak memory 164456 kb
Host smart-d5c73f2b-c436-4ffb-b610-e8e3bf3e6a97
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041817753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2041817753
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.53060669
Short name T53
Test name
Test status
Simulation time 1288930000 ps
CPU time 3.94 seconds
Started Jun 06 12:22:12 PM PDT 24
Finished Jun 06 12:22:21 PM PDT 24
Peak memory 164448 kb
Host smart-5d853407-73fe-4ea6-9c10-a9dd724c4a15
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=53060669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.53060669
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1308154372
Short name T42
Test name
Test status
Simulation time 1538710000 ps
CPU time 3.37 seconds
Started Jun 06 12:27:54 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 164500 kb
Host smart-ca2e46d3-3bd9-4369-a407-95208c6f5c6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308154372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1308154372
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2610605039
Short name T48
Test name
Test status
Simulation time 1605770000 ps
CPU time 4.79 seconds
Started Jun 06 12:20:57 PM PDT 24
Finished Jun 06 12:21:08 PM PDT 24
Peak memory 164916 kb
Host smart-b0e9c2ad-53f1-48f5-a7de-9d143b8dbaa5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610605039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2610605039
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3899923499
Short name T49
Test name
Test status
Simulation time 1518330000 ps
CPU time 5.66 seconds
Started Jun 06 12:21:44 PM PDT 24
Finished Jun 06 12:21:58 PM PDT 24
Peak memory 165056 kb
Host smart-01cf9a0c-b43d-43c8-8028-45c806ae18ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899923499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3899923499
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.741080084
Short name T70
Test name
Test status
Simulation time 1376890000 ps
CPU time 4.95 seconds
Started Jun 06 12:21:43 PM PDT 24
Finished Jun 06 12:21:55 PM PDT 24
Peak memory 164552 kb
Host smart-41bb39d8-53ac-4e6a-9a34-c265f7ba693e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=741080084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.741080084
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2243090317
Short name T52
Test name
Test status
Simulation time 1453650000 ps
CPU time 4.69 seconds
Started Jun 06 12:21:28 PM PDT 24
Finished Jun 06 12:21:39 PM PDT 24
Peak memory 164468 kb
Host smart-779c9ee5-2c0a-49e7-b0eb-9f208ecd7645
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2243090317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2243090317
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3654788185
Short name T43
Test name
Test status
Simulation time 1393710000 ps
CPU time 4.41 seconds
Started Jun 06 12:21:16 PM PDT 24
Finished Jun 06 12:21:26 PM PDT 24
Peak memory 164868 kb
Host smart-a4c57ac8-c2fd-4230-87e4-2aac7509a960
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654788185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3654788185
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.190345444
Short name T13
Test name
Test status
Simulation time 1263990000 ps
CPU time 5.15 seconds
Started Jun 06 12:21:07 PM PDT 24
Finished Jun 06 12:21:19 PM PDT 24
Peak memory 165008 kb
Host smart-bc51f75b-da2f-4fe1-af5f-b9525194269e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=190345444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.190345444
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2216825538
Short name T61
Test name
Test status
Simulation time 1559870000 ps
CPU time 4.98 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:06 PM PDT 24
Peak memory 162208 kb
Host smart-9713bfca-7ddb-4c26-9935-3cad7c5b56c8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216825538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2216825538
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1776480314
Short name T44
Test name
Test status
Simulation time 1394630000 ps
CPU time 4.67 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:05 PM PDT 24
Peak memory 162768 kb
Host smart-98992296-7e68-4c3a-8bfa-0c6864282650
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1776480314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1776480314
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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