Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4002333517
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1095877896
98.31 3.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 15.00 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2742280675

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2167386174
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.789603589
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.572256800
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2992035851
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2252997189
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2564146250
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2994334526
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2116754829
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1580265007
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3410781402
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2375565661
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.144604455
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1636362907
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2389835675
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1685199994
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3958346123
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.331927271
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1822976891
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3651205986
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3276413420
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1914966855
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3626744625
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1979458885
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3158780298
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2485886363
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.833337768
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2585653134
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4057362020
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2596555664
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.722256242
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1263647352
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3765490696
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2266101452
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1801019414
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1817754016
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3412859485
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.408182290
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2626076697
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3444915345
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.221536215
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.165750897
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3552022369
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1941730437
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3247525627
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3260095601
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1082817698
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2555730640
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.551054567
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3168492144
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4173809257
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1767867901
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3563160299
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3201689310
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4047241671
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3297700853
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3813783987
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3673119542
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4068951694
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3861365534
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.594666499
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.890818904
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3923704397
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.328395079
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.295570517
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.622064258
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3494912095
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.393066335
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3205442636
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.300970086
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3962518974
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1414320019
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.978724306
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.583225396
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1879228814
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.302976326
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.891274252
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2326193722
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1078512296
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3098361638
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2862946464
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2993168424
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3526852501
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1155834293
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.90837656
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4259686748
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1225113657
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.138073767
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3694185807
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1244451585
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.748440881
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2856326814
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.876603707
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1706774974
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1516555832
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2559702263
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1672178853
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.850255018
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3271886252
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2481166737
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4221436722
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3887590244
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3834482505
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1997462439
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4276040967
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2074380865
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2383844278
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.122053991
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1451577358
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.254261686
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2396598013
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4263281758
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3505365235
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3834692216
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3741690818
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.340833136
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1234032159
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1907190580
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1032644859
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.455235655
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1300238265
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.126114081
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2391229038
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.361494285
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2852527381
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4132210915
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3745085169
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.250565786
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1938065505
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2100987989
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1785759947
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.248268894
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1429885648
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2417016730
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3157177654
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3090709561
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3560020210
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1514384488
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2651201785
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3013288168
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.409489409
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1987641460
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2808199479
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3068106823
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.33143069
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2662010573
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.483521390
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2442071063
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4125848747
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1289048836
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.164603160
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2332967845
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.40105972
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2103301303
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3299716034
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2954690357
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.817209092
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.282958809
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3567481959
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.847970450
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2526173683
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3753304418
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.749262801
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2957269185
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.500210488
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4059186393
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3385023812
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3315565084
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4177904821
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3610156326
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3669483398
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.178987512
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1295110011
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.244870550
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.144921443
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.291112005
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1272834103
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.577855542
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2342051371
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3705179464
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2305704900
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1826503372
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1052846083
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1325518933
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2957762234
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2171193056
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3630617761
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4115963109
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2636866571
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2872984879
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3115094697
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.832168810
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1815077578
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.148388230
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1026897810
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3210457810
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3349671275
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.711728675



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.711728675 Jun 07 06:00:04 PM PDT 24 Jun 07 06:00:14 PM PDT 24 1356990000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.500210488 Jun 07 05:59:27 PM PDT 24 Jun 07 05:59:36 PM PDT 24 1356010000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3567481959 Jun 07 06:00:51 PM PDT 24 Jun 07 06:00:59 PM PDT 24 1417810000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3669483398 Jun 07 05:58:49 PM PDT 24 Jun 07 05:58:59 PM PDT 24 1508130000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3705179464 Jun 07 05:58:45 PM PDT 24 Jun 07 05:58:55 PM PDT 24 1506570000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4002333517 Jun 07 06:03:40 PM PDT 24 Jun 07 06:03:48 PM PDT 24 1058910000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1052846083 Jun 07 05:59:25 PM PDT 24 Jun 07 05:59:36 PM PDT 24 1489850000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2957269185 Jun 07 06:04:09 PM PDT 24 Jun 07 06:04:18 PM PDT 24 1463750000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1026897810 Jun 07 06:03:40 PM PDT 24 Jun 07 06:03:49 PM PDT 24 1293530000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4115963109 Jun 07 06:04:16 PM PDT 24 Jun 07 06:04:27 PM PDT 24 1477230000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2305704900 Jun 07 05:59:13 PM PDT 24 Jun 07 05:59:24 PM PDT 24 1493110000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2103301303 Jun 07 06:00:16 PM PDT 24 Jun 07 06:00:28 PM PDT 24 1450050000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.749262801 Jun 07 06:04:11 PM PDT 24 Jun 07 06:04:18 PM PDT 24 1397510000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3753304418 Jun 07 06:04:16 PM PDT 24 Jun 07 06:04:26 PM PDT 24 1586790000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4177904821 Jun 07 05:59:22 PM PDT 24 Jun 07 05:59:31 PM PDT 24 1414150000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4059186393 Jun 07 06:04:09 PM PDT 24 Jun 07 06:04:18 PM PDT 24 1438330000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3610156326 Jun 07 05:58:45 PM PDT 24 Jun 07 05:58:55 PM PDT 24 1559090000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3299716034 Jun 07 06:04:03 PM PDT 24 Jun 07 06:04:11 PM PDT 24 1233430000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2636866571 Jun 07 06:04:06 PM PDT 24 Jun 07 06:04:14 PM PDT 24 1295770000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2872984879 Jun 07 06:03:18 PM PDT 24 Jun 07 06:03:25 PM PDT 24 1560850000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.817209092 Jun 07 06:03:28 PM PDT 24 Jun 07 06:03:37 PM PDT 24 1442970000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1325518933 Jun 07 06:03:42 PM PDT 24 Jun 07 06:03:51 PM PDT 24 1523890000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.291112005 Jun 07 05:58:43 PM PDT 24 Jun 07 05:58:53 PM PDT 24 1432930000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3630617761 Jun 07 06:03:20 PM PDT 24 Jun 07 06:03:28 PM PDT 24 1470550000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.847970450 Jun 07 06:04:03 PM PDT 24 Jun 07 06:04:13 PM PDT 24 1523250000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2957762234 Jun 07 06:02:10 PM PDT 24 Jun 07 06:02:21 PM PDT 24 1492030000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1826503372 Jun 07 05:59:49 PM PDT 24 Jun 07 05:59:58 PM PDT 24 1134910000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3115094697 Jun 07 06:03:46 PM PDT 24 Jun 07 06:03:53 PM PDT 24 1478430000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.40105972 Jun 07 06:03:37 PM PDT 24 Jun 07 06:03:49 PM PDT 24 1368350000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2332967845 Jun 07 06:00:38 PM PDT 24 Jun 07 06:00:46 PM PDT 24 1462950000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.144921443 Jun 07 05:59:32 PM PDT 24 Jun 07 05:59:45 PM PDT 24 1571830000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1815077578 Jun 07 06:01:53 PM PDT 24 Jun 07 06:02:03 PM PDT 24 1279990000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3385023812 Jun 07 06:00:19 PM PDT 24 Jun 07 06:00:33 PM PDT 24 1567430000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.244870550 Jun 07 05:58:49 PM PDT 24 Jun 07 05:59:02 PM PDT 24 1536790000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2342051371 Jun 07 06:02:51 PM PDT 24 Jun 07 06:03:04 PM PDT 24 1421650000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2526173683 Jun 07 06:03:38 PM PDT 24 Jun 07 06:03:48 PM PDT 24 1323490000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.148388230 Jun 07 06:03:37 PM PDT 24 Jun 07 06:03:50 PM PDT 24 1513530000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.832168810 Jun 07 06:03:17 PM PDT 24 Jun 07 06:03:23 PM PDT 24 1073350000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2954690357 Jun 07 06:02:34 PM PDT 24 Jun 07 06:02:44 PM PDT 24 1363750000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.164603160 Jun 07 06:04:01 PM PDT 24 Jun 07 06:04:08 PM PDT 24 1540670000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.282958809 Jun 07 06:01:09 PM PDT 24 Jun 07 06:01:20 PM PDT 24 1428290000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1272834103 Jun 07 05:59:24 PM PDT 24 Jun 07 05:59:33 PM PDT 24 1363790000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3315565084 Jun 07 06:01:03 PM PDT 24 Jun 07 06:01:14 PM PDT 24 1506670000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1289048836 Jun 07 06:00:24 PM PDT 24 Jun 07 06:00:35 PM PDT 24 1252070000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3349671275 Jun 07 05:59:39 PM PDT 24 Jun 07 05:59:49 PM PDT 24 1506670000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.178987512 Jun 07 06:02:17 PM PDT 24 Jun 07 06:02:25 PM PDT 24 1295450000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1295110011 Jun 07 05:58:42 PM PDT 24 Jun 07 05:58:52 PM PDT 24 1477370000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.577855542 Jun 07 05:59:52 PM PDT 24 Jun 07 06:00:01 PM PDT 24 1315630000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3210457810 Jun 07 06:01:35 PM PDT 24 Jun 07 06:01:47 PM PDT 24 1435510000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2171193056 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:34 PM PDT 24 1610550000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.138073767 Jun 07 06:03:39 PM PDT 24 Jun 07 06:33:56 PM PDT 24 336374970000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1095877896 Jun 07 05:58:43 PM PDT 24 Jun 07 06:32:10 PM PDT 24 336696410000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3271886252 Jun 07 05:58:48 PM PDT 24 Jun 07 06:38:55 PM PDT 24 336985610000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2993168424 Jun 07 06:03:16 PM PDT 24 Jun 07 06:34:17 PM PDT 24 337004490000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4259686748 Jun 07 05:59:24 PM PDT 24 Jun 07 06:32:09 PM PDT 24 336414050000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.850255018 Jun 07 05:58:46 PM PDT 24 Jun 07 06:37:29 PM PDT 24 336544710000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4068951694 Jun 07 05:59:52 PM PDT 24 Jun 07 06:33:52 PM PDT 24 336443170000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2326193722 Jun 07 05:59:52 PM PDT 24 Jun 07 06:34:53 PM PDT 24 336972050000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3297700853 Jun 07 05:58:48 PM PDT 24 Jun 07 06:38:57 PM PDT 24 336699710000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.90837656 Jun 07 06:03:16 PM PDT 24 Jun 07 06:34:23 PM PDT 24 336343790000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.978724306 Jun 07 05:58:46 PM PDT 24 Jun 07 06:37:08 PM PDT 24 336614450000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2862946464 Jun 07 06:00:41 PM PDT 24 Jun 07 06:35:30 PM PDT 24 336334590000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.891274252 Jun 07 05:58:48 PM PDT 24 Jun 07 06:34:54 PM PDT 24 336967290000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1414320019 Jun 07 05:58:48 PM PDT 24 Jun 07 06:30:59 PM PDT 24 336587970000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3923704397 Jun 07 05:59:53 PM PDT 24 Jun 07 06:34:53 PM PDT 24 336407250000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1672178853 Jun 07 05:59:40 PM PDT 24 Jun 07 06:38:45 PM PDT 24 336487330000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.302976326 Jun 07 05:58:41 PM PDT 24 Jun 07 06:40:03 PM PDT 24 336697670000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3694185807 Jun 07 06:03:25 PM PDT 24 Jun 07 06:32:53 PM PDT 24 336677070000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.748440881 Jun 07 05:59:52 PM PDT 24 Jun 07 06:36:08 PM PDT 24 337131070000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1078512296 Jun 07 05:59:49 PM PDT 24 Jun 07 06:34:14 PM PDT 24 336885950000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1879228814 Jun 07 05:59:52 PM PDT 24 Jun 07 06:35:33 PM PDT 24 336595090000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.300970086 Jun 07 06:02:14 PM PDT 24 Jun 07 06:41:32 PM PDT 24 336691330000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3526852501 Jun 07 06:00:14 PM PDT 24 Jun 07 06:42:32 PM PDT 24 336915610000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2559702263 Jun 07 05:58:42 PM PDT 24 Jun 07 06:32:14 PM PDT 24 336482630000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2856326814 Jun 07 06:00:50 PM PDT 24 Jun 07 06:41:55 PM PDT 24 336345610000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.876603707 Jun 07 06:03:42 PM PDT 24 Jun 07 06:27:51 PM PDT 24 336793490000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.622064258 Jun 07 05:59:50 PM PDT 24 Jun 07 06:33:55 PM PDT 24 336523850000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3563160299 Jun 07 05:58:42 PM PDT 24 Jun 07 06:32:06 PM PDT 24 336319530000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1244451585 Jun 07 06:04:06 PM PDT 24 Jun 07 06:29:00 PM PDT 24 336783430000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.583225396 Jun 07 05:58:49 PM PDT 24 Jun 07 06:39:03 PM PDT 24 336922730000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4047241671 Jun 07 05:58:48 PM PDT 24 Jun 07 06:38:59 PM PDT 24 336459430000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1706774974 Jun 07 05:59:20 PM PDT 24 Jun 07 06:35:11 PM PDT 24 336565410000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3098361638 Jun 07 05:59:49 PM PDT 24 Jun 07 06:28:27 PM PDT 24 336407750000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1225113657 Jun 07 06:03:25 PM PDT 24 Jun 07 06:30:30 PM PDT 24 336461110000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3861365534 Jun 07 06:04:19 PM PDT 24 Jun 07 06:30:49 PM PDT 24 336537990000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3673119542 Jun 07 05:58:48 PM PDT 24 Jun 07 06:36:21 PM PDT 24 337119170000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3962518974 Jun 07 05:58:33 PM PDT 24 Jun 07 06:33:22 PM PDT 24 336877450000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3813783987 Jun 07 05:58:48 PM PDT 24 Jun 07 06:36:15 PM PDT 24 336574550000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.295570517 Jun 07 05:58:47 PM PDT 24 Jun 07 06:36:24 PM PDT 24 336622810000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.393066335 Jun 07 05:58:48 PM PDT 24 Jun 07 06:31:03 PM PDT 24 336404230000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1155834293 Jun 07 05:58:41 PM PDT 24 Jun 07 06:32:23 PM PDT 24 336950470000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3205442636 Jun 07 05:59:52 PM PDT 24 Jun 07 06:35:38 PM PDT 24 336528470000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3201689310 Jun 07 05:59:52 PM PDT 24 Jun 07 06:34:43 PM PDT 24 336361350000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.890818904 Jun 07 05:58:50 PM PDT 24 Jun 07 06:33:16 PM PDT 24 336849590000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4173809257 Jun 07 05:58:41 PM PDT 24 Jun 07 06:32:37 PM PDT 24 336322230000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1767867901 Jun 07 05:59:50 PM PDT 24 Jun 07 06:34:17 PM PDT 24 336466510000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1516555832 Jun 07 05:59:49 PM PDT 24 Jun 07 06:34:23 PM PDT 24 336525430000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.594666499 Jun 07 05:59:48 PM PDT 24 Jun 07 06:28:23 PM PDT 24 336419010000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.328395079 Jun 07 05:58:47 PM PDT 24 Jun 07 06:36:30 PM PDT 24 336483430000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3494912095 Jun 07 06:04:09 PM PDT 24 Jun 07 06:28:44 PM PDT 24 336732510000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2742280675 Jun 07 06:01:36 PM PDT 24 Jun 07 06:28:40 PM PDT 24 337034670000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3276413420 Jun 07 06:04:16 PM PDT 24 Jun 07 06:37:03 PM PDT 24 336440030000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3168492144 Jun 07 05:59:19 PM PDT 24 Jun 07 06:28:48 PM PDT 24 336408450000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3412859485 Jun 07 06:00:37 PM PDT 24 Jun 07 06:40:33 PM PDT 24 336902910000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.408182290 Jun 07 06:00:41 PM PDT 24 Jun 07 06:36:43 PM PDT 24 336557410000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1636362907 Jun 07 06:03:37 PM PDT 24 Jun 07 06:38:36 PM PDT 24 336523990000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3444915345 Jun 07 05:59:37 PM PDT 24 Jun 07 06:30:43 PM PDT 24 336487070000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2485886363 Jun 07 06:02:04 PM PDT 24 Jun 07 06:41:14 PM PDT 24 336492130000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2266101452 Jun 07 05:58:42 PM PDT 24 Jun 07 06:40:09 PM PDT 24 336424150000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.551054567 Jun 07 06:03:25 PM PDT 24 Jun 07 06:30:27 PM PDT 24 336351410000 ps
T111 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.572256800 Jun 07 06:03:39 PM PDT 24 Jun 07 06:34:06 PM PDT 24 336706370000 ps
T112 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.789603589 Jun 07 05:59:40 PM PDT 24 Jun 07 06:39:12 PM PDT 24 336444490000 ps
T113 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2626076697 Jun 07 06:04:15 PM PDT 24 Jun 07 06:28:51 PM PDT 24 336385530000 ps
T114 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2596555664 Jun 07 06:04:23 PM PDT 24 Jun 07 06:40:21 PM PDT 24 336528650000 ps
T115 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2167386174 Jun 07 05:59:33 PM PDT 24 Jun 07 06:37:38 PM PDT 24 336956450000 ps
T116 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1263647352 Jun 07 06:00:19 PM PDT 24 Jun 07 06:39:42 PM PDT 24 336586510000 ps
T117 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.165750897 Jun 07 05:59:36 PM PDT 24 Jun 07 06:39:37 PM PDT 24 336674910000 ps
T118 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1979458885 Jun 07 06:03:17 PM PDT 24 Jun 07 06:34:28 PM PDT 24 336535530000 ps
T119 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.833337768 Jun 07 05:59:36 PM PDT 24 Jun 07 06:39:39 PM PDT 24 337002670000 ps
T120 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2116754829 Jun 07 05:59:36 PM PDT 24 Jun 07 06:29:41 PM PDT 24 336999030000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2389835675 Jun 07 06:00:40 PM PDT 24 Jun 07 06:31:10 PM PDT 24 336968290000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3765490696 Jun 07 05:58:48 PM PDT 24 Jun 07 06:34:47 PM PDT 24 336622510000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1817754016 Jun 07 06:03:15 PM PDT 24 Jun 07 06:29:29 PM PDT 24 336680270000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3410781402 Jun 07 06:03:39 PM PDT 24 Jun 07 06:34:32 PM PDT 24 336860150000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1580265007 Jun 07 06:03:23 PM PDT 24 Jun 07 06:36:36 PM PDT 24 336410030000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3158780298 Jun 07 06:04:23 PM PDT 24 Jun 07 06:40:46 PM PDT 24 336680770000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2564146250 Jun 07 06:03:23 PM PDT 24 Jun 07 06:36:58 PM PDT 24 336854390000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1685199994 Jun 07 06:03:25 PM PDT 24 Jun 07 06:36:50 PM PDT 24 336472390000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.144604455 Jun 07 05:59:49 PM PDT 24 Jun 07 06:28:27 PM PDT 24 336696730000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.722256242 Jun 07 06:04:23 PM PDT 24 Jun 07 06:40:43 PM PDT 24 336653550000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1822976891 Jun 07 06:03:29 PM PDT 24 Jun 07 06:30:12 PM PDT 24 336885170000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1801019414 Jun 07 05:58:57 PM PDT 24 Jun 07 06:33:05 PM PDT 24 336682710000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2992035851 Jun 07 06:01:30 PM PDT 24 Jun 07 06:36:48 PM PDT 24 337041010000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2252997189 Jun 07 06:03:40 PM PDT 24 Jun 07 06:35:06 PM PDT 24 336991070000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2375565661 Jun 07 06:03:37 PM PDT 24 Jun 07 06:38:27 PM PDT 24 336891070000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2555730640 Jun 07 05:59:20 PM PDT 24 Jun 07 06:41:10 PM PDT 24 336899910000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.221536215 Jun 07 06:03:52 PM PDT 24 Jun 07 06:27:19 PM PDT 24 336580210000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3552022369 Jun 07 06:03:23 PM PDT 24 Jun 07 06:30:34 PM PDT 24 336948430000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3626744625 Jun 07 06:04:09 PM PDT 24 Jun 07 06:35:47 PM PDT 24 336828790000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2585653134 Jun 07 06:04:23 PM PDT 24 Jun 07 06:39:57 PM PDT 24 337086830000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1914966855 Jun 07 06:04:02 PM PDT 24 Jun 07 06:35:42 PM PDT 24 336395950000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.331927271 Jun 07 06:00:05 PM PDT 24 Jun 07 06:40:24 PM PDT 24 336836590000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3247525627 Jun 07 06:03:16 PM PDT 24 Jun 07 06:28:01 PM PDT 24 336376650000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4057362020 Jun 07 06:04:02 PM PDT 24 Jun 07 06:36:06 PM PDT 24 336492510000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1082817698 Jun 07 05:59:38 PM PDT 24 Jun 07 06:31:44 PM PDT 24 336656650000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3260095601 Jun 07 06:03:37 PM PDT 24 Jun 07 06:34:20 PM PDT 24 336865050000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1941730437 Jun 07 06:02:11 PM PDT 24 Jun 07 06:39:46 PM PDT 24 336541890000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2994334526 Jun 07 06:01:36 PM PDT 24 Jun 07 06:36:51 PM PDT 24 336450730000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3958346123 Jun 07 06:00:54 PM PDT 24 Jun 07 06:33:27 PM PDT 24 336363010000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3651205986 Jun 07 06:03:28 PM PDT 24 Jun 07 06:30:41 PM PDT 24 336548750000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1907190580 Jun 07 06:00:36 PM PDT 24 Jun 07 06:00:46 PM PDT 24 1222270000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1300238265 Jun 07 05:59:17 PM PDT 24 Jun 07 05:59:27 PM PDT 24 1513470000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4221436722 Jun 07 06:04:19 PM PDT 24 Jun 07 06:04:26 PM PDT 24 1469090000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1987641460 Jun 07 06:01:10 PM PDT 24 Jun 07 06:01:22 PM PDT 24 1580990000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4276040967 Jun 07 05:58:49 PM PDT 24 Jun 07 05:58:58 PM PDT 24 1424110000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3745085169 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:32 PM PDT 24 1461230000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3560020210 Jun 07 06:03:51 PM PDT 24 Jun 07 06:03:59 PM PDT 24 1584150000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3505365235 Jun 07 06:03:38 PM PDT 24 Jun 07 06:03:49 PM PDT 24 1477910000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2442071063 Jun 07 05:59:52 PM PDT 24 Jun 07 06:00:02 PM PDT 24 1459610000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1451577358 Jun 07 05:59:33 PM PDT 24 Jun 07 05:59:46 PM PDT 24 1534190000 ps
T161 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.254261686 Jun 07 05:59:06 PM PDT 24 Jun 07 05:59:17 PM PDT 24 1512870000 ps
T162 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3887590244 Jun 07 05:58:48 PM PDT 24 Jun 07 05:59:00 PM PDT 24 1424950000 ps
T163 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2852527381 Jun 07 06:02:44 PM PDT 24 Jun 07 06:02:55 PM PDT 24 1431110000 ps
T164 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.250565786 Jun 07 06:03:21 PM PDT 24 Jun 07 06:03:29 PM PDT 24 1395010000 ps
T165 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2383844278 Jun 07 05:59:49 PM PDT 24 Jun 07 05:59:59 PM PDT 24 1362730000 ps
T166 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3741690818 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:34 PM PDT 24 1484710000 ps
T167 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3013288168 Jun 07 06:03:55 PM PDT 24 Jun 07 06:04:04 PM PDT 24 1520890000 ps
T168 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2396598013 Jun 07 06:03:17 PM PDT 24 Jun 07 06:03:26 PM PDT 24 1318510000 ps
T169 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2417016730 Jun 07 05:58:49 PM PDT 24 Jun 07 05:59:00 PM PDT 24 1222890000 ps
T170 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2481166737 Jun 07 05:59:49 PM PDT 24 Jun 07 05:59:57 PM PDT 24 1351030000 ps
T171 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.409489409 Jun 07 06:04:06 PM PDT 24 Jun 07 06:04:14 PM PDT 24 1392350000 ps
T172 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.455235655 Jun 07 06:00:41 PM PDT 24 Jun 07 06:00:52 PM PDT 24 1552850000 ps
T173 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2662010573 Jun 07 05:58:49 PM PDT 24 Jun 07 05:58:59 PM PDT 24 1446310000 ps
T174 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1234032159 Jun 07 06:03:38 PM PDT 24 Jun 07 06:03:47 PM PDT 24 1161990000 ps
T175 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2651201785 Jun 07 06:01:20 PM PDT 24 Jun 07 06:01:31 PM PDT 24 1414010000 ps
T176 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1997462439 Jun 07 05:58:49 PM PDT 24 Jun 07 05:58:58 PM PDT 24 1219330000 ps
T177 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.483521390 Jun 07 05:58:48 PM PDT 24 Jun 07 05:59:01 PM PDT 24 1524450000 ps
T178 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.122053991 Jun 07 05:59:49 PM PDT 24 Jun 07 06:00:00 PM PDT 24 1510610000 ps
T179 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4263281758 Jun 07 05:58:42 PM PDT 24 Jun 07 05:58:52 PM PDT 24 1369010000 ps
T180 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1938065505 Jun 07 06:03:52 PM PDT 24 Jun 07 06:04:00 PM PDT 24 1543150000 ps
T181 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2808199479 Jun 07 06:03:55 PM PDT 24 Jun 07 06:04:03 PM PDT 24 1361070000 ps
T182 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.361494285 Jun 07 05:59:52 PM PDT 24 Jun 07 06:00:04 PM PDT 24 1502850000 ps
T183 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2074380865 Jun 07 05:59:48 PM PDT 24 Jun 07 05:59:58 PM PDT 24 1541470000 ps
T184 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4125848747 Jun 07 05:58:48 PM PDT 24 Jun 07 05:59:00 PM PDT 24 1490310000 ps
T185 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.340833136 Jun 07 06:00:07 PM PDT 24 Jun 07 06:00:16 PM PDT 24 1460370000 ps
T186 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1785759947 Jun 07 06:04:09 PM PDT 24 Jun 07 06:04:18 PM PDT 24 1532430000 ps
T187 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4132210915 Jun 07 06:00:25 PM PDT 24 Jun 07 06:00:38 PM PDT 24 1643490000 ps
T188 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3834482505 Jun 07 05:58:49 PM PDT 24 Jun 07 05:59:01 PM PDT 24 1409350000 ps
T189 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2100987989 Jun 07 06:03:36 PM PDT 24 Jun 07 06:03:47 PM PDT 24 1547250000 ps
T190 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2391229038 Jun 07 05:58:41 PM PDT 24 Jun 07 05:58:52 PM PDT 24 1481050000 ps
T191 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3157177654 Jun 07 06:03:51 PM PDT 24 Jun 07 06:03:58 PM PDT 24 1309330000 ps
T192 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.126114081 Jun 07 06:03:37 PM PDT 24 Jun 07 06:03:48 PM PDT 24 1424070000 ps
T193 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3090709561 Jun 07 06:04:06 PM PDT 24 Jun 07 06:04:13 PM PDT 24 1177250000 ps
T194 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1032644859 Jun 07 06:00:19 PM PDT 24 Jun 07 06:00:30 PM PDT 24 1490710000 ps
T195 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.33143069 Jun 07 05:59:11 PM PDT 24 Jun 07 05:59:22 PM PDT 24 1455590000 ps
T196 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3834692216 Jun 07 06:03:53 PM PDT 24 Jun 07 06:04:00 PM PDT 24 1486410000 ps
T197 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.248268894 Jun 07 05:59:13 PM PDT 24 Jun 07 05:59:22 PM PDT 24 1451710000 ps
T198 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1514384488 Jun 07 06:03:56 PM PDT 24 Jun 07 06:04:05 PM PDT 24 1486070000 ps
T199 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3068106823 Jun 07 06:03:55 PM PDT 24 Jun 07 06:04:03 PM PDT 24 1340770000 ps
T200 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1429885648 Jun 07 06:02:46 PM PDT 24 Jun 07 06:02:58 PM PDT 24 1512650000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.4002333517
Short name T9
Test name
Test status
Simulation time 1058910000 ps
CPU time 3.61 seconds
Started Jun 07 06:03:40 PM PDT 24
Finished Jun 07 06:03:48 PM PDT 24
Peak memory 164624 kb
Host smart-a70cd3bb-b02c-4cbd-af67-f5fbbe6592ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4002333517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.4002333517
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1095877896
Short name T15
Test name
Test status
Simulation time 336696410000 ps
CPU time 817.2 seconds
Started Jun 07 05:58:43 PM PDT 24
Finished Jun 07 06:32:10 PM PDT 24
Peak memory 159168 kb
Host smart-d11a42c5-b26c-428b-8a7a-08ea1d031665
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1095877896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1095877896
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2742280675
Short name T4
Test name
Test status
Simulation time 337034670000 ps
CPU time 657.78 seconds
Started Jun 07 06:01:36 PM PDT 24
Finished Jun 07 06:28:40 PM PDT 24
Peak memory 160644 kb
Host smart-333f0533-cd6a-4d08-8425-f38fea6d1343
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2742280675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2742280675
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2167386174
Short name T115
Test name
Test status
Simulation time 336956450000 ps
CPU time 913.31 seconds
Started Jun 07 05:59:33 PM PDT 24
Finished Jun 07 06:37:38 PM PDT 24
Peak memory 160632 kb
Host smart-4145ca0a-1b1c-4d23-8194-63ef50aa612a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2167386174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2167386174
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.789603589
Short name T112
Test name
Test status
Simulation time 336444490000 ps
CPU time 947.23 seconds
Started Jun 07 05:59:40 PM PDT 24
Finished Jun 07 06:39:12 PM PDT 24
Peak memory 160600 kb
Host smart-f01f2e3c-3887-4be7-84d9-21bbeb038349
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=789603589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.789603589
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.572256800
Short name T111
Test name
Test status
Simulation time 336706370000 ps
CPU time 728.38 seconds
Started Jun 07 06:03:39 PM PDT 24
Finished Jun 07 06:34:06 PM PDT 24
Peak memory 160284 kb
Host smart-27ab2889-b456-4f84-980f-269bcd5adf10
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=572256800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.572256800
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2992035851
Short name T133
Test name
Test status
Simulation time 337041010000 ps
CPU time 845.02 seconds
Started Jun 07 06:01:30 PM PDT 24
Finished Jun 07 06:36:48 PM PDT 24
Peak memory 160652 kb
Host smart-0d078438-e45e-4791-b34d-f5734872db86
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2992035851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2992035851
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2252997189
Short name T134
Test name
Test status
Simulation time 336991070000 ps
CPU time 754.09 seconds
Started Jun 07 06:03:40 PM PDT 24
Finished Jun 07 06:35:06 PM PDT 24
Peak memory 160556 kb
Host smart-02f40b77-b49c-462c-8127-36bddc41f112
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2252997189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2252997189
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2564146250
Short name T127
Test name
Test status
Simulation time 336854390000 ps
CPU time 803.8 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:36:58 PM PDT 24
Peak memory 159132 kb
Host smart-846b4132-15a1-46f0-b45f-f61913557b35
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2564146250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2564146250
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2994334526
Short name T148
Test name
Test status
Simulation time 336450730000 ps
CPU time 865.42 seconds
Started Jun 07 06:01:36 PM PDT 24
Finished Jun 07 06:36:51 PM PDT 24
Peak memory 160620 kb
Host smart-238734da-f4c3-4737-b7ab-0c177cecdcad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2994334526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2994334526
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2116754829
Short name T120
Test name
Test status
Simulation time 336999030000 ps
CPU time 736.26 seconds
Started Jun 07 05:59:36 PM PDT 24
Finished Jun 07 06:29:41 PM PDT 24
Peak memory 160640 kb
Host smart-d6223a96-7437-4f3f-88b2-aba9e095dd16
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2116754829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2116754829
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1580265007
Short name T125
Test name
Test status
Simulation time 336410030000 ps
CPU time 781.84 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:36:36 PM PDT 24
Peak memory 159128 kb
Host smart-df322f00-fe79-437d-a14d-5ef30356081c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1580265007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1580265007
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3410781402
Short name T124
Test name
Test status
Simulation time 336860150000 ps
CPU time 745.98 seconds
Started Jun 07 06:03:39 PM PDT 24
Finished Jun 07 06:34:32 PM PDT 24
Peak memory 160144 kb
Host smart-f9c17890-398d-4faf-b305-20aca9e8bdb1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3410781402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3410781402
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2375565661
Short name T135
Test name
Test status
Simulation time 336891070000 ps
CPU time 836.88 seconds
Started Jun 07 06:03:37 PM PDT 24
Finished Jun 07 06:38:27 PM PDT 24
Peak memory 160524 kb
Host smart-9c0f29b7-8cce-4983-89d1-bd13a1a56e08
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2375565661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2375565661
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.144604455
Short name T129
Test name
Test status
Simulation time 336696730000 ps
CPU time 691.09 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 06:28:27 PM PDT 24
Peak memory 160296 kb
Host smart-4d5096dd-c155-455b-91cd-30faa8792346
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=144604455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.144604455
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1636362907
Short name T26
Test name
Test status
Simulation time 336523990000 ps
CPU time 849.61 seconds
Started Jun 07 06:03:37 PM PDT 24
Finished Jun 07 06:38:36 PM PDT 24
Peak memory 160524 kb
Host smart-fae68fd3-0572-4c92-969c-509de076a06b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1636362907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1636362907
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2389835675
Short name T121
Test name
Test status
Simulation time 336968290000 ps
CPU time 753.96 seconds
Started Jun 07 06:00:40 PM PDT 24
Finished Jun 07 06:31:10 PM PDT 24
Peak memory 160644 kb
Host smart-7574c862-47d6-4c22-86c8-1120ca7b4c42
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2389835675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2389835675
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1685199994
Short name T128
Test name
Test status
Simulation time 336472390000 ps
CPU time 802.5 seconds
Started Jun 07 06:03:25 PM PDT 24
Finished Jun 07 06:36:50 PM PDT 24
Peak memory 160340 kb
Host smart-aae033a9-26a4-4961-9c1f-16c3bbea8696
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1685199994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1685199994
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3958346123
Short name T149
Test name
Test status
Simulation time 336363010000 ps
CPU time 790.21 seconds
Started Jun 07 06:00:54 PM PDT 24
Finished Jun 07 06:33:27 PM PDT 24
Peak memory 160620 kb
Host smart-65deea89-cbec-41d8-ba2e-84549d666ea7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3958346123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3958346123
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.331927271
Short name T142
Test name
Test status
Simulation time 336836590000 ps
CPU time 911.48 seconds
Started Jun 07 06:00:05 PM PDT 24
Finished Jun 07 06:40:24 PM PDT 24
Peak memory 160764 kb
Host smart-a26ea72e-2660-48bc-8c07-00d901987752
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=331927271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.331927271
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1822976891
Short name T131
Test name
Test status
Simulation time 336885170000 ps
CPU time 651.45 seconds
Started Jun 07 06:03:29 PM PDT 24
Finished Jun 07 06:30:12 PM PDT 24
Peak memory 160216 kb
Host smart-d770d8b8-16b5-481a-bce1-6bad3a100b95
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1822976891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1822976891
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3651205986
Short name T150
Test name
Test status
Simulation time 336548750000 ps
CPU time 669.28 seconds
Started Jun 07 06:03:28 PM PDT 24
Finished Jun 07 06:30:41 PM PDT 24
Peak memory 159748 kb
Host smart-148ee283-0520-4c6e-826c-9ac72973d309
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3651205986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3651205986
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3276413420
Short name T5
Test name
Test status
Simulation time 336440030000 ps
CPU time 786.81 seconds
Started Jun 07 06:04:16 PM PDT 24
Finished Jun 07 06:37:03 PM PDT 24
Peak memory 160624 kb
Host smart-5a90160b-6c6b-4acd-82ff-061940b591f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3276413420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3276413420
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1914966855
Short name T141
Test name
Test status
Simulation time 336395950000 ps
CPU time 774.29 seconds
Started Jun 07 06:04:02 PM PDT 24
Finished Jun 07 06:35:42 PM PDT 24
Peak memory 159912 kb
Host smart-1294a844-69ef-4e4c-9b85-1b178f933e0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1914966855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1914966855
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3626744625
Short name T139
Test name
Test status
Simulation time 336828790000 ps
CPU time 759 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:35:47 PM PDT 24
Peak memory 158932 kb
Host smart-d8d71345-2a41-489b-ab25-a24a9246efd0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3626744625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3626744625
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1979458885
Short name T118
Test name
Test status
Simulation time 336535530000 ps
CPU time 743.51 seconds
Started Jun 07 06:03:17 PM PDT 24
Finished Jun 07 06:34:28 PM PDT 24
Peak memory 160464 kb
Host smart-1dfb342c-80c2-4c87-b839-20caa71855ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1979458885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1979458885
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3158780298
Short name T126
Test name
Test status
Simulation time 336680770000 ps
CPU time 880.16 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:40:46 PM PDT 24
Peak memory 160528 kb
Host smart-bb544e64-b91a-4724-86d2-386c9d528259
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3158780298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3158780298
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2485886363
Short name T28
Test name
Test status
Simulation time 336492130000 ps
CPU time 933.2 seconds
Started Jun 07 06:02:04 PM PDT 24
Finished Jun 07 06:41:14 PM PDT 24
Peak memory 160644 kb
Host smart-ee3ccb7c-2e0c-4280-9467-a4ac8cb13e04
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2485886363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2485886363
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.833337768
Short name T119
Test name
Test status
Simulation time 337002670000 ps
CPU time 964.84 seconds
Started Jun 07 05:59:36 PM PDT 24
Finished Jun 07 06:39:39 PM PDT 24
Peak memory 160860 kb
Host smart-5f90ad81-f435-4bd6-b650-c59266f32e76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=833337768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.833337768
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2585653134
Short name T140
Test name
Test status
Simulation time 337086830000 ps
CPU time 852.74 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:39:57 PM PDT 24
Peak memory 160528 kb
Host smart-9166edc9-5632-48ea-a1da-5e8a57c1684c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2585653134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2585653134
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4057362020
Short name T144
Test name
Test status
Simulation time 336492510000 ps
CPU time 790.34 seconds
Started Jun 07 06:04:02 PM PDT 24
Finished Jun 07 06:36:06 PM PDT 24
Peak memory 159604 kb
Host smart-6e7e010f-9e87-447a-9406-6d4932337bcd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4057362020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4057362020
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2596555664
Short name T114
Test name
Test status
Simulation time 336528650000 ps
CPU time 866.38 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:40:21 PM PDT 24
Peak memory 160528 kb
Host smart-bdc885fa-580d-4fe3-ba16-d082c21c9caa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2596555664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2596555664
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.722256242
Short name T130
Test name
Test status
Simulation time 336653550000 ps
CPU time 886.3 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:40:43 PM PDT 24
Peak memory 160528 kb
Host smart-dd09c897-63e8-41af-90f8-f4b3b268f699
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=722256242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.722256242
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1263647352
Short name T116
Test name
Test status
Simulation time 336586510000 ps
CPU time 963.02 seconds
Started Jun 07 06:00:19 PM PDT 24
Finished Jun 07 06:39:42 PM PDT 24
Peak memory 160868 kb
Host smart-cc4588b3-5f13-46dd-a655-6601f84c57d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1263647352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1263647352
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3765490696
Short name T122
Test name
Test status
Simulation time 336622510000 ps
CPU time 884.11 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:34:47 PM PDT 24
Peak memory 160860 kb
Host smart-d03c47f7-b16f-4d1f-a69f-a7f9f8fd5aa6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3765490696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3765490696
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2266101452
Short name T29
Test name
Test status
Simulation time 336424150000 ps
CPU time 969.59 seconds
Started Jun 07 05:58:42 PM PDT 24
Finished Jun 07 06:40:09 PM PDT 24
Peak memory 160764 kb
Host smart-8cfa4f7b-8940-466b-a6af-e4fd13250476
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2266101452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2266101452
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1801019414
Short name T132
Test name
Test status
Simulation time 336682710000 ps
CPU time 828.83 seconds
Started Jun 07 05:58:57 PM PDT 24
Finished Jun 07 06:33:05 PM PDT 24
Peak memory 160596 kb
Host smart-b36580d6-00e9-4b50-9452-8c982763acb3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1801019414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1801019414
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1817754016
Short name T123
Test name
Test status
Simulation time 336680270000 ps
CPU time 640.72 seconds
Started Jun 07 06:03:15 PM PDT 24
Finished Jun 07 06:29:29 PM PDT 24
Peak memory 159764 kb
Host smart-7b183dd5-41fe-4fbd-94b5-468dffd123a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1817754016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1817754016
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3412859485
Short name T24
Test name
Test status
Simulation time 336902910000 ps
CPU time 952.45 seconds
Started Jun 07 06:00:37 PM PDT 24
Finished Jun 07 06:40:33 PM PDT 24
Peak memory 160632 kb
Host smart-2e049cf5-0c10-4ea3-a838-71417e23a7ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3412859485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3412859485
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.408182290
Short name T25
Test name
Test status
Simulation time 336557410000 ps
CPU time 881.9 seconds
Started Jun 07 06:00:41 PM PDT 24
Finished Jun 07 06:36:43 PM PDT 24
Peak memory 160632 kb
Host smart-5aa78bde-1c47-4b32-a70c-dea658556ef4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=408182290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.408182290
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2626076697
Short name T113
Test name
Test status
Simulation time 336385530000 ps
CPU time 602.58 seconds
Started Jun 07 06:04:15 PM PDT 24
Finished Jun 07 06:28:51 PM PDT 24
Peak memory 159764 kb
Host smart-e596dfe7-5113-4f19-a064-eb33eb28d87c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2626076697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2626076697
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3444915345
Short name T27
Test name
Test status
Simulation time 336487070000 ps
CPU time 746.13 seconds
Started Jun 07 05:59:37 PM PDT 24
Finished Jun 07 06:30:43 PM PDT 24
Peak memory 160644 kb
Host smart-f7d5299b-cd1b-4e3a-bb00-b6b85296c682
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3444915345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3444915345
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.221536215
Short name T137
Test name
Test status
Simulation time 336580210000 ps
CPU time 565.48 seconds
Started Jun 07 06:03:52 PM PDT 24
Finished Jun 07 06:27:19 PM PDT 24
Peak memory 160444 kb
Host smart-3e3b38e4-066c-4597-8d7b-11bb6a32504e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=221536215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.221536215
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.165750897
Short name T117
Test name
Test status
Simulation time 336674910000 ps
CPU time 966.87 seconds
Started Jun 07 05:59:36 PM PDT 24
Finished Jun 07 06:39:37 PM PDT 24
Peak memory 160860 kb
Host smart-2b3d3229-2889-4d68-badb-bc1a0c7c505c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=165750897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.165750897
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3552022369
Short name T138
Test name
Test status
Simulation time 336948430000 ps
CPU time 668.66 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:30:34 PM PDT 24
Peak memory 159760 kb
Host smart-86bbdbf5-2147-40e9-967e-3b306e63a7eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3552022369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3552022369
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1941730437
Short name T147
Test name
Test status
Simulation time 336541890000 ps
CPU time 904.53 seconds
Started Jun 07 06:02:11 PM PDT 24
Finished Jun 07 06:39:46 PM PDT 24
Peak memory 160644 kb
Host smart-a5006422-5124-4094-9e30-bd2c1ce01549
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1941730437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1941730437
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3247525627
Short name T143
Test name
Test status
Simulation time 336376650000 ps
CPU time 599.27 seconds
Started Jun 07 06:03:16 PM PDT 24
Finished Jun 07 06:28:01 PM PDT 24
Peak memory 160260 kb
Host smart-29c6ef34-9e93-4280-a9a3-7b8d6ade2614
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3247525627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3247525627
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3260095601
Short name T146
Test name
Test status
Simulation time 336865050000 ps
CPU time 746.69 seconds
Started Jun 07 06:03:37 PM PDT 24
Finished Jun 07 06:34:20 PM PDT 24
Peak memory 160632 kb
Host smart-9eec6cc5-478e-4f81-95cf-5625c1ee4b1d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3260095601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3260095601
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1082817698
Short name T145
Test name
Test status
Simulation time 336656650000 ps
CPU time 778.95 seconds
Started Jun 07 05:59:38 PM PDT 24
Finished Jun 07 06:31:44 PM PDT 24
Peak memory 160632 kb
Host smart-8533291f-9ec9-4759-aefc-2d19dcfe9ff7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1082817698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1082817698
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2555730640
Short name T136
Test name
Test status
Simulation time 336899910000 ps
CPU time 985.13 seconds
Started Jun 07 05:59:20 PM PDT 24
Finished Jun 07 06:41:10 PM PDT 24
Peak memory 160752 kb
Host smart-a956549a-576f-489e-b99a-3e67d08f735a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2555730640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2555730640
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.551054567
Short name T30
Test name
Test status
Simulation time 336351410000 ps
CPU time 650.1 seconds
Started Jun 07 06:03:25 PM PDT 24
Finished Jun 07 06:30:27 PM PDT 24
Peak memory 160468 kb
Host smart-3fac63d4-fcb2-4dbd-ae43-ba1a4e990d22
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=551054567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.551054567
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3168492144
Short name T6
Test name
Test status
Simulation time 336408450000 ps
CPU time 725.3 seconds
Started Jun 07 05:59:19 PM PDT 24
Finished Jun 07 06:28:48 PM PDT 24
Peak memory 160608 kb
Host smart-c67e90b4-908b-47a1-8814-bea2ba632310
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3168492144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3168492144
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4173809257
Short name T105
Test name
Test status
Simulation time 336322230000 ps
CPU time 816.03 seconds
Started Jun 07 05:58:41 PM PDT 24
Finished Jun 07 06:32:37 PM PDT 24
Peak memory 160664 kb
Host smart-ce97cae2-d91e-4ce7-a0be-3238b16f4e06
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4173809257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4173809257
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1767867901
Short name T106
Test name
Test status
Simulation time 336466510000 ps
CPU time 819.65 seconds
Started Jun 07 05:59:50 PM PDT 24
Finished Jun 07 06:34:17 PM PDT 24
Peak memory 160416 kb
Host smart-5eaa08d6-b8ce-4872-8514-131db1175975
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1767867901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1767867901
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3563160299
Short name T88
Test name
Test status
Simulation time 336319530000 ps
CPU time 796.23 seconds
Started Jun 07 05:58:42 PM PDT 24
Finished Jun 07 06:32:06 PM PDT 24
Peak memory 160748 kb
Host smart-590ab3d4-4fa5-4165-ad1b-d87c10b495ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3563160299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3563160299
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3201689310
Short name T103
Test name
Test status
Simulation time 336361350000 ps
CPU time 844.91 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:34:43 PM PDT 24
Peak memory 158144 kb
Host smart-1679787d-4289-4f19-a708-30de1fe6b57b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3201689310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3201689310
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4047241671
Short name T91
Test name
Test status
Simulation time 336459430000 ps
CPU time 969.02 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:38:59 PM PDT 24
Peak memory 160872 kb
Host smart-798bc79d-7f0d-4055-99cd-abe992c5bf66
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4047241671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4047241671
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3297700853
Short name T22
Test name
Test status
Simulation time 336699710000 ps
CPU time 965.17 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:38:57 PM PDT 24
Peak memory 160872 kb
Host smart-5019c215-8780-4489-b0dc-2994f94383ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3297700853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3297700853
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3813783987
Short name T98
Test name
Test status
Simulation time 336574550000 ps
CPU time 875.87 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:36:15 PM PDT 24
Peak memory 160428 kb
Host smart-a4c5a0cd-a7b1-4143-86a4-fde1dbe74bc5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3813783987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3813783987
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3673119542
Short name T96
Test name
Test status
Simulation time 337119170000 ps
CPU time 884.68 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:36:21 PM PDT 24
Peak memory 160436 kb
Host smart-c45fd139-d9c4-44ba-8051-0b53e6792e6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3673119542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3673119542
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4068951694
Short name T20
Test name
Test status
Simulation time 336443170000 ps
CPU time 798.19 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:33:52 PM PDT 24
Peak memory 160604 kb
Host smart-e75cd527-9b92-4a5a-92ed-3aefaa693a82
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4068951694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4068951694
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3861365534
Short name T95
Test name
Test status
Simulation time 336537990000 ps
CPU time 644.36 seconds
Started Jun 07 06:04:19 PM PDT 24
Finished Jun 07 06:30:49 PM PDT 24
Peak memory 160660 kb
Host smart-8d392a0f-ab11-4a33-a1c3-c22bcdf66b2a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3861365534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3861365534
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.594666499
Short name T108
Test name
Test status
Simulation time 336419010000 ps
CPU time 693.46 seconds
Started Jun 07 05:59:48 PM PDT 24
Finished Jun 07 06:28:23 PM PDT 24
Peak memory 159104 kb
Host smart-3ee470a6-f100-4323-ba98-58302975410c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=594666499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.594666499
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.890818904
Short name T104
Test name
Test status
Simulation time 336849590000 ps
CPU time 825.98 seconds
Started Jun 07 05:58:50 PM PDT 24
Finished Jun 07 06:33:16 PM PDT 24
Peak memory 160188 kb
Host smart-efddbcad-ad4e-418d-825b-0de3bdc38e7e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=890818904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.890818904
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3923704397
Short name T75
Test name
Test status
Simulation time 336407250000 ps
CPU time 843.53 seconds
Started Jun 07 05:59:53 PM PDT 24
Finished Jun 07 06:34:53 PM PDT 24
Peak memory 160432 kb
Host smart-5892ca92-a086-46fe-9607-5b8a5baf02ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3923704397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3923704397
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.328395079
Short name T109
Test name
Test status
Simulation time 336483430000 ps
CPU time 884.97 seconds
Started Jun 07 05:58:47 PM PDT 24
Finished Jun 07 06:36:30 PM PDT 24
Peak memory 160392 kb
Host smart-82048acd-212a-4be5-89a8-15d6be492dc9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=328395079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.328395079
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.295570517
Short name T99
Test name
Test status
Simulation time 336622810000 ps
CPU time 882.44 seconds
Started Jun 07 05:58:47 PM PDT 24
Finished Jun 07 06:36:24 PM PDT 24
Peak memory 160388 kb
Host smart-1c12ba22-c44e-4917-8b75-5e4610f01836
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=295570517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.295570517
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.622064258
Short name T87
Test name
Test status
Simulation time 336523850000 ps
CPU time 799.29 seconds
Started Jun 07 05:59:50 PM PDT 24
Finished Jun 07 06:33:55 PM PDT 24
Peak memory 160228 kb
Host smart-30ce5d2c-0f4a-4351-ab3e-f562e653bcda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622064258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.622064258
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3494912095
Short name T110
Test name
Test status
Simulation time 336732510000 ps
CPU time 590.75 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:28:44 PM PDT 24
Peak memory 160368 kb
Host smart-58f2a547-a444-4b29-b925-3de4b734f0d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3494912095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3494912095
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.393066335
Short name T100
Test name
Test status
Simulation time 336404230000 ps
CPU time 782.01 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:31:03 PM PDT 24
Peak memory 159972 kb
Host smart-46a69358-4050-4b09-9921-2061e46a708f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=393066335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.393066335
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3205442636
Short name T102
Test name
Test status
Simulation time 336528470000 ps
CPU time 860.38 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:35:38 PM PDT 24
Peak memory 158524 kb
Host smart-62232f6a-c737-4649-8906-2624d3332d15
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3205442636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3205442636
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.300970086
Short name T82
Test name
Test status
Simulation time 336691330000 ps
CPU time 945.51 seconds
Started Jun 07 06:02:14 PM PDT 24
Finished Jun 07 06:41:32 PM PDT 24
Peak memory 160644 kb
Host smart-1d2e5003-0f98-467b-94db-6bcab387bfe3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300970086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.300970086
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3962518974
Short name T97
Test name
Test status
Simulation time 336877450000 ps
CPU time 826.86 seconds
Started Jun 07 05:58:33 PM PDT 24
Finished Jun 07 06:33:22 PM PDT 24
Peak memory 159740 kb
Host smart-eeaabdee-f5e9-4a21-8d8f-16d66c961857
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3962518974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3962518974
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1414320019
Short name T74
Test name
Test status
Simulation time 336587970000 ps
CPU time 779.5 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:30:59 PM PDT 24
Peak memory 159572 kb
Host smart-a665dd4d-a0b2-4585-996d-88dffb159e09
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1414320019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1414320019
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.978724306
Short name T71
Test name
Test status
Simulation time 336614450000 ps
CPU time 918.83 seconds
Started Jun 07 05:58:46 PM PDT 24
Finished Jun 07 06:37:08 PM PDT 24
Peak memory 159236 kb
Host smart-f76f3627-876b-49ed-b5d2-76739cecfdcb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=978724306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.978724306
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.583225396
Short name T90
Test name
Test status
Simulation time 336922730000 ps
CPU time 967.43 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 06:39:03 PM PDT 24
Peak memory 160864 kb
Host smart-476abf9f-f084-4a56-abb2-1e38a85dd0ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=583225396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.583225396
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1879228814
Short name T81
Test name
Test status
Simulation time 336595090000 ps
CPU time 869.7 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:35:33 PM PDT 24
Peak memory 159672 kb
Host smart-104d2199-e4fe-4955-a0dc-eb312bff8290
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1879228814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1879228814
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.302976326
Short name T77
Test name
Test status
Simulation time 336697670000 ps
CPU time 964.18 seconds
Started Jun 07 05:58:41 PM PDT 24
Finished Jun 07 06:40:03 PM PDT 24
Peak memory 160640 kb
Host smart-7914fca4-75b5-451e-92f7-1cfd769f247c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=302976326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.302976326
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.891274252
Short name T73
Test name
Test status
Simulation time 336967290000 ps
CPU time 887.66 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:34:54 PM PDT 24
Peak memory 160856 kb
Host smart-85c12cea-1b93-4032-aee0-ae21487b80ca
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=891274252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.891274252
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2326193722
Short name T21
Test name
Test status
Simulation time 336972050000 ps
CPU time 846.83 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:34:53 PM PDT 24
Peak memory 158120 kb
Host smart-544c831c-fffe-48fc-87fd-eab5d312157d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2326193722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2326193722
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1078512296
Short name T80
Test name
Test status
Simulation time 336885950000 ps
CPU time 811.11 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 06:34:14 PM PDT 24
Peak memory 158652 kb
Host smart-50904602-33da-43f4-84f1-c996b9778a27
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1078512296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1078512296
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3098361638
Short name T93
Test name
Test status
Simulation time 336407750000 ps
CPU time 689.4 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 06:28:27 PM PDT 24
Peak memory 160428 kb
Host smart-1ccede44-67e1-4afb-9469-b321b6b9a672
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3098361638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3098361638
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2862946464
Short name T72
Test name
Test status
Simulation time 336334590000 ps
CPU time 836.06 seconds
Started Jun 07 06:00:41 PM PDT 24
Finished Jun 07 06:35:30 PM PDT 24
Peak memory 160640 kb
Host smart-e76f8293-f8ab-44cc-8b13-bfc1ccc65da8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2862946464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2862946464
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2993168424
Short name T17
Test name
Test status
Simulation time 337004490000 ps
CPU time 741.09 seconds
Started Jun 07 06:03:16 PM PDT 24
Finished Jun 07 06:34:17 PM PDT 24
Peak memory 159360 kb
Host smart-040b890a-1944-4331-9bdc-51e45b0d6e07
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2993168424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2993168424
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3526852501
Short name T83
Test name
Test status
Simulation time 336915610000 ps
CPU time 1005.01 seconds
Started Jun 07 06:00:14 PM PDT 24
Finished Jun 07 06:42:32 PM PDT 24
Peak memory 160768 kb
Host smart-2238baec-7c58-4047-a2e1-23cbf266d7a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3526852501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3526852501
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1155834293
Short name T101
Test name
Test status
Simulation time 336950470000 ps
CPU time 812.05 seconds
Started Jun 07 05:58:41 PM PDT 24
Finished Jun 07 06:32:23 PM PDT 24
Peak memory 160604 kb
Host smart-f3fa553c-49ae-45bc-b589-ac3f88595754
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1155834293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1155834293
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.90837656
Short name T23
Test name
Test status
Simulation time 336343790000 ps
CPU time 741.46 seconds
Started Jun 07 06:03:16 PM PDT 24
Finished Jun 07 06:34:23 PM PDT 24
Peak memory 160300 kb
Host smart-3bdca2c1-dfcc-4ec8-83fc-74ca8b1e5e97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=90837656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.90837656
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4259686748
Short name T18
Test name
Test status
Simulation time 336414050000 ps
CPU time 782.2 seconds
Started Jun 07 05:59:24 PM PDT 24
Finished Jun 07 06:32:09 PM PDT 24
Peak memory 160748 kb
Host smart-2c8bc4ff-2169-484e-b48d-c6c1c53e27b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4259686748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.4259686748
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1225113657
Short name T94
Test name
Test status
Simulation time 336461110000 ps
CPU time 651.5 seconds
Started Jun 07 06:03:25 PM PDT 24
Finished Jun 07 06:30:30 PM PDT 24
Peak memory 160524 kb
Host smart-5d9ce030-7288-4f5b-a9ce-eca16ed168f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1225113657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1225113657
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.138073767
Short name T14
Test name
Test status
Simulation time 336374970000 ps
CPU time 726.53 seconds
Started Jun 07 06:03:39 PM PDT 24
Finished Jun 07 06:33:56 PM PDT 24
Peak memory 160248 kb
Host smart-4521b7d0-f210-480c-8135-247644472b27
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=138073767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.138073767
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3694185807
Short name T78
Test name
Test status
Simulation time 336677070000 ps
CPU time 717.9 seconds
Started Jun 07 06:03:25 PM PDT 24
Finished Jun 07 06:32:53 PM PDT 24
Peak memory 160468 kb
Host smart-f8109093-16e9-4758-813c-7e2924488f68
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3694185807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3694185807
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1244451585
Short name T89
Test name
Test status
Simulation time 336783430000 ps
CPU time 606.5 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:29:00 PM PDT 24
Peak memory 159740 kb
Host smart-d6c5f70f-2760-4364-83ae-c5c122f11f48
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1244451585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1244451585
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.748440881
Short name T79
Test name
Test status
Simulation time 337131070000 ps
CPU time 886.01 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:36:08 PM PDT 24
Peak memory 160856 kb
Host smart-3806c224-66fa-4470-b4a9-92ece6caf778
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=748440881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.748440881
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2856326814
Short name T85
Test name
Test status
Simulation time 336345610000 ps
CPU time 945.64 seconds
Started Jun 07 06:00:50 PM PDT 24
Finished Jun 07 06:41:55 PM PDT 24
Peak memory 160768 kb
Host smart-198b5f7d-ec1e-4710-b99d-61be7e42ee6f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2856326814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2856326814
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.876603707
Short name T86
Test name
Test status
Simulation time 336793490000 ps
CPU time 587.56 seconds
Started Jun 07 06:03:42 PM PDT 24
Finished Jun 07 06:27:51 PM PDT 24
Peak memory 159760 kb
Host smart-866fa53e-7951-4a12-bdb2-9fd6b2493469
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=876603707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.876603707
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1706774974
Short name T92
Test name
Test status
Simulation time 336565410000 ps
CPU time 858.33 seconds
Started Jun 07 05:59:20 PM PDT 24
Finished Jun 07 06:35:11 PM PDT 24
Peak memory 160636 kb
Host smart-76f0ad9e-f308-4eda-8a65-bc0b8dc30737
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1706774974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1706774974
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1516555832
Short name T107
Test name
Test status
Simulation time 336525430000 ps
CPU time 813.25 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 06:34:23 PM PDT 24
Peak memory 159064 kb
Host smart-31a116b2-af10-4535-bda0-7a4d359d9a3c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1516555832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1516555832
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2559702263
Short name T84
Test name
Test status
Simulation time 336482630000 ps
CPU time 805.1 seconds
Started Jun 07 05:58:42 PM PDT 24
Finished Jun 07 06:32:14 PM PDT 24
Peak memory 160736 kb
Host smart-2c6306d7-e201-4b61-ae8d-e8ca4bb3887a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2559702263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2559702263
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1672178853
Short name T76
Test name
Test status
Simulation time 336487330000 ps
CPU time 917.43 seconds
Started Jun 07 05:59:40 PM PDT 24
Finished Jun 07 06:38:45 PM PDT 24
Peak memory 160600 kb
Host smart-676669a0-2c7f-483d-9bdb-b452533fde86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1672178853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1672178853
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.850255018
Short name T19
Test name
Test status
Simulation time 336544710000 ps
CPU time 940.75 seconds
Started Jun 07 05:58:46 PM PDT 24
Finished Jun 07 06:37:29 PM PDT 24
Peak memory 159168 kb
Host smart-6de36cd1-3141-49d5-974d-363feafe0a55
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=850255018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.850255018
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3271886252
Short name T16
Test name
Test status
Simulation time 336985610000 ps
CPU time 955.54 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 06:38:55 PM PDT 24
Peak memory 160860 kb
Host smart-2dcce25c-09a2-4819-aa47-dfeacfccc309
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3271886252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3271886252
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2481166737
Short name T170
Test name
Test status
Simulation time 1351030000 ps
CPU time 3.47 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 05:59:57 PM PDT 24
Peak memory 163528 kb
Host smart-4ad7d990-bb3a-4b8a-abec-593e172239a2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481166737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2481166737
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4221436722
Short name T153
Test name
Test status
Simulation time 1469090000 ps
CPU time 2.93 seconds
Started Jun 07 06:04:19 PM PDT 24
Finished Jun 07 06:04:26 PM PDT 24
Peak memory 164724 kb
Host smart-29e33f32-5e09-4cef-ab2e-ef35a8b31e11
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221436722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.4221436722
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3887590244
Short name T162
Test name
Test status
Simulation time 1424950000 ps
CPU time 5.52 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 05:59:00 PM PDT 24
Peak memory 164940 kb
Host smart-6849174d-e332-4671-9096-a66f7573c82e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3887590244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3887590244
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3834482505
Short name T188
Test name
Test status
Simulation time 1409350000 ps
CPU time 5.44 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:59:01 PM PDT 24
Peak memory 164940 kb
Host smart-60349eb3-3692-4b30-acf1-1b660a7e6d6f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3834482505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3834482505
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1997462439
Short name T176
Test name
Test status
Simulation time 1219330000 ps
CPU time 3.7 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:58:58 PM PDT 24
Peak memory 164508 kb
Host smart-8c3a9e4d-5b80-452b-a92e-32a7dea8a9fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997462439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1997462439
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4276040967
Short name T155
Test name
Test status
Simulation time 1424110000 ps
CPU time 3.79 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:58:58 PM PDT 24
Peak memory 164484 kb
Host smart-2dfd1441-8d7a-4dc2-af70-e0038fec648e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276040967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4276040967
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2074380865
Short name T183
Test name
Test status
Simulation time 1541470000 ps
CPU time 3.96 seconds
Started Jun 07 05:59:48 PM PDT 24
Finished Jun 07 05:59:58 PM PDT 24
Peak memory 162936 kb
Host smart-5ded0ef7-47ef-4a47-bcf4-5b9479d1402b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074380865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2074380865
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2383844278
Short name T165
Test name
Test status
Simulation time 1362730000 ps
CPU time 4.16 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 05:59:59 PM PDT 24
Peak memory 163660 kb
Host smart-79738641-ce91-4986-82f4-14398b87d169
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383844278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2383844278
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.122053991
Short name T178
Test name
Test status
Simulation time 1510610000 ps
CPU time 4.5 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 06:00:00 PM PDT 24
Peak memory 162652 kb
Host smart-3a7e8df4-d593-42bd-b4c4-878e6cff79dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122053991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.122053991
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1451577358
Short name T160
Test name
Test status
Simulation time 1534190000 ps
CPU time 5.58 seconds
Started Jun 07 05:59:33 PM PDT 24
Finished Jun 07 05:59:46 PM PDT 24
Peak memory 164836 kb
Host smart-0831e4e2-0553-421e-83ea-5f267b4887c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1451577358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1451577358
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.254261686
Short name T161
Test name
Test status
Simulation time 1512870000 ps
CPU time 5.06 seconds
Started Jun 07 05:59:06 PM PDT 24
Finished Jun 07 05:59:17 PM PDT 24
Peak memory 164672 kb
Host smart-5b03144d-78f6-4d0b-8315-1e957d957d28
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254261686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.254261686
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2396598013
Short name T168
Test name
Test status
Simulation time 1318510000 ps
CPU time 3.82 seconds
Started Jun 07 06:03:17 PM PDT 24
Finished Jun 07 06:03:26 PM PDT 24
Peak memory 164440 kb
Host smart-dd5680a2-c9e1-4b7e-b3ea-34d1d834f776
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396598013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2396598013
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4263281758
Short name T179
Test name
Test status
Simulation time 1369010000 ps
CPU time 4.15 seconds
Started Jun 07 05:58:42 PM PDT 24
Finished Jun 07 05:58:52 PM PDT 24
Peak memory 164832 kb
Host smart-02ca227e-3795-4512-a0d7-a28717f2c08b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4263281758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4263281758
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3505365235
Short name T158
Test name
Test status
Simulation time 1477910000 ps
CPU time 4.61 seconds
Started Jun 07 06:03:38 PM PDT 24
Finished Jun 07 06:03:49 PM PDT 24
Peak memory 162708 kb
Host smart-eb82bc96-1d0c-48df-84a7-17368108320b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3505365235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3505365235
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3834692216
Short name T196
Test name
Test status
Simulation time 1486410000 ps
CPU time 3.32 seconds
Started Jun 07 06:03:53 PM PDT 24
Finished Jun 07 06:04:00 PM PDT 24
Peak memory 163196 kb
Host smart-c450bae4-9960-44a2-a46b-357eacd9962d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3834692216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3834692216
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3741690818
Short name T166
Test name
Test status
Simulation time 1484710000 ps
CPU time 4.4 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:34 PM PDT 24
Peak memory 164304 kb
Host smart-af77bfe2-b2ad-4929-9ccf-53e71d272831
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3741690818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3741690818
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.340833136
Short name T185
Test name
Test status
Simulation time 1460370000 ps
CPU time 3.9 seconds
Started Jun 07 06:00:07 PM PDT 24
Finished Jun 07 06:00:16 PM PDT 24
Peak memory 164684 kb
Host smart-030326b6-1618-4c71-8bb9-a543c2351937
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=340833136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.340833136
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1234032159
Short name T174
Test name
Test status
Simulation time 1161990000 ps
CPU time 3.63 seconds
Started Jun 07 06:03:38 PM PDT 24
Finished Jun 07 06:03:47 PM PDT 24
Peak memory 163268 kb
Host smart-c5e218c5-ba8e-4b18-b955-8f92efe9a6fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1234032159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1234032159
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1907190580
Short name T151
Test name
Test status
Simulation time 1222270000 ps
CPU time 4.51 seconds
Started Jun 07 06:00:36 PM PDT 24
Finished Jun 07 06:00:46 PM PDT 24
Peak memory 164728 kb
Host smart-6272eb63-a718-4a8b-9795-189eebba55fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907190580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1907190580
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1032644859
Short name T194
Test name
Test status
Simulation time 1490710000 ps
CPU time 4.7 seconds
Started Jun 07 06:00:19 PM PDT 24
Finished Jun 07 06:00:30 PM PDT 24
Peak memory 164696 kb
Host smart-35a540e8-bf2f-41aa-b378-21f3ed67c482
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1032644859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1032644859
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.455235655
Short name T172
Test name
Test status
Simulation time 1552850000 ps
CPU time 4.59 seconds
Started Jun 07 06:00:41 PM PDT 24
Finished Jun 07 06:00:52 PM PDT 24
Peak memory 164688 kb
Host smart-77947a61-8afa-42de-91c9-af0da8111ba0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=455235655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.455235655
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1300238265
Short name T152
Test name
Test status
Simulation time 1513470000 ps
CPU time 4.76 seconds
Started Jun 07 05:59:17 PM PDT 24
Finished Jun 07 05:59:27 PM PDT 24
Peak memory 164680 kb
Host smart-40a91ee4-123a-4dd5-ab4a-2a5da180fbb1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1300238265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1300238265
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.126114081
Short name T192
Test name
Test status
Simulation time 1424070000 ps
CPU time 4.73 seconds
Started Jun 07 06:03:37 PM PDT 24
Finished Jun 07 06:03:48 PM PDT 24
Peak memory 164596 kb
Host smart-3e171993-28ec-4420-8b82-a73058ff911f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=126114081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.126114081
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2391229038
Short name T190
Test name
Test status
Simulation time 1481050000 ps
CPU time 4.32 seconds
Started Jun 07 05:58:41 PM PDT 24
Finished Jun 07 05:58:52 PM PDT 24
Peak memory 164756 kb
Host smart-bbf81fb6-705c-401c-b073-635c1ce6ff5e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2391229038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2391229038
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.361494285
Short name T182
Test name
Test status
Simulation time 1502850000 ps
CPU time 5.41 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:00:04 PM PDT 24
Peak memory 164936 kb
Host smart-0748322a-dcd0-407e-9a5e-444be5d9931a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=361494285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.361494285
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2852527381
Short name T163
Test name
Test status
Simulation time 1431110000 ps
CPU time 4.92 seconds
Started Jun 07 06:02:44 PM PDT 24
Finished Jun 07 06:02:55 PM PDT 24
Peak memory 164920 kb
Host smart-f5258691-2e45-473d-b444-2dcf1f44d794
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2852527381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2852527381
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4132210915
Short name T187
Test name
Test status
Simulation time 1643490000 ps
CPU time 5.34 seconds
Started Jun 07 06:00:25 PM PDT 24
Finished Jun 07 06:00:38 PM PDT 24
Peak memory 164920 kb
Host smart-87a9adc7-59b5-4204-870d-dfc3b0d93554
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4132210915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4132210915
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3745085169
Short name T156
Test name
Test status
Simulation time 1461230000 ps
CPU time 3.42 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:32 PM PDT 24
Peak memory 164292 kb
Host smart-15779522-28e8-4b29-9568-f4da4dc085c8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3745085169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3745085169
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.250565786
Short name T164
Test name
Test status
Simulation time 1395010000 ps
CPU time 3.26 seconds
Started Jun 07 06:03:21 PM PDT 24
Finished Jun 07 06:03:29 PM PDT 24
Peak memory 164328 kb
Host smart-c3444adc-d121-4377-9710-0b2e9d37fc00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=250565786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.250565786
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1938065505
Short name T180
Test name
Test status
Simulation time 1543150000 ps
CPU time 3.39 seconds
Started Jun 07 06:03:52 PM PDT 24
Finished Jun 07 06:04:00 PM PDT 24
Peak memory 164472 kb
Host smart-6493fb33-1f29-4d2d-b2d7-1d8d7e6cbce9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1938065505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1938065505
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2100987989
Short name T189
Test name
Test status
Simulation time 1547250000 ps
CPU time 4.8 seconds
Started Jun 07 06:03:36 PM PDT 24
Finished Jun 07 06:03:47 PM PDT 24
Peak memory 164672 kb
Host smart-311edbaa-0a61-4f57-af45-c792fd01e953
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2100987989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2100987989
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1785759947
Short name T186
Test name
Test status
Simulation time 1532430000 ps
CPU time 3.62 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:18 PM PDT 24
Peak memory 162392 kb
Host smart-06bdea78-5a8a-4f4b-b875-d725b9274f4c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1785759947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1785759947
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.248268894
Short name T197
Test name
Test status
Simulation time 1451710000 ps
CPU time 3.97 seconds
Started Jun 07 05:59:13 PM PDT 24
Finished Jun 07 05:59:22 PM PDT 24
Peak memory 163504 kb
Host smart-dace8644-95cd-46d3-83dd-fb6a0213ddd6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=248268894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.248268894
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1429885648
Short name T200
Test name
Test status
Simulation time 1512650000 ps
CPU time 5.33 seconds
Started Jun 07 06:02:46 PM PDT 24
Finished Jun 07 06:02:58 PM PDT 24
Peak memory 164940 kb
Host smart-295b2249-e13f-4c79-bfab-a83c6e3a4e38
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1429885648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1429885648
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2417016730
Short name T169
Test name
Test status
Simulation time 1222890000 ps
CPU time 4.77 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:59:00 PM PDT 24
Peak memory 164920 kb
Host smart-078faa9b-2e21-40e6-8bfc-c0bb597c50dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417016730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2417016730
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3157177654
Short name T191
Test name
Test status
Simulation time 1309330000 ps
CPU time 3.03 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:58 PM PDT 24
Peak memory 162272 kb
Host smart-a9d3182b-3268-48c3-adca-89a4ed90271b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3157177654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3157177654
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3090709561
Short name T193
Test name
Test status
Simulation time 1177250000 ps
CPU time 3.17 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:13 PM PDT 24
Peak memory 164588 kb
Host smart-49495c96-c301-49ed-b3d2-b17a0f79c8b7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3090709561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3090709561
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3560020210
Short name T157
Test name
Test status
Simulation time 1584150000 ps
CPU time 3.47 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:59 PM PDT 24
Peak memory 162172 kb
Host smart-3ff29f37-a99f-42e1-8707-d3aa0c5959dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3560020210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3560020210
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1514384488
Short name T198
Test name
Test status
Simulation time 1486070000 ps
CPU time 3.74 seconds
Started Jun 07 06:03:56 PM PDT 24
Finished Jun 07 06:04:05 PM PDT 24
Peak memory 164700 kb
Host smart-c164658e-5cfc-4b1c-a010-c2144b21a9b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514384488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1514384488
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2651201785
Short name T175
Test name
Test status
Simulation time 1414010000 ps
CPU time 4.71 seconds
Started Jun 07 06:01:20 PM PDT 24
Finished Jun 07 06:01:31 PM PDT 24
Peak memory 164876 kb
Host smart-4a3644e2-ce4f-4516-bd7a-2491fbef3785
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2651201785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2651201785
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3013288168
Short name T167
Test name
Test status
Simulation time 1520890000 ps
CPU time 4.11 seconds
Started Jun 07 06:03:55 PM PDT 24
Finished Jun 07 06:04:04 PM PDT 24
Peak memory 164356 kb
Host smart-ea4ba55e-5a5a-4678-84ae-daa27737806f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3013288168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3013288168
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.409489409
Short name T171
Test name
Test status
Simulation time 1392350000 ps
CPU time 3.59 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:14 PM PDT 24
Peak memory 164584 kb
Host smart-ce9482c8-48b8-4c21-8a8a-45fbab1adf48
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409489409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.409489409
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1987641460
Short name T154
Test name
Test status
Simulation time 1580990000 ps
CPU time 5.01 seconds
Started Jun 07 06:01:10 PM PDT 24
Finished Jun 07 06:01:22 PM PDT 24
Peak memory 164696 kb
Host smart-bb6a5209-90a3-4341-aff4-3fd78e920a14
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987641460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1987641460
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2808199479
Short name T181
Test name
Test status
Simulation time 1361070000 ps
CPU time 3.59 seconds
Started Jun 07 06:03:55 PM PDT 24
Finished Jun 07 06:04:03 PM PDT 24
Peak memory 163636 kb
Host smart-d962fb1f-3996-4d95-9648-60751fadc084
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2808199479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2808199479
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3068106823
Short name T199
Test name
Test status
Simulation time 1340770000 ps
CPU time 3.36 seconds
Started Jun 07 06:03:55 PM PDT 24
Finished Jun 07 06:04:03 PM PDT 24
Peak memory 164452 kb
Host smart-564a9632-b90c-4ede-a171-14eb0769431b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3068106823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3068106823
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.33143069
Short name T195
Test name
Test status
Simulation time 1455590000 ps
CPU time 5.02 seconds
Started Jun 07 05:59:11 PM PDT 24
Finished Jun 07 05:59:22 PM PDT 24
Peak memory 164692 kb
Host smart-3678ef48-3dc0-49f7-a5b6-a69681ea48f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33143069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.33143069
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2662010573
Short name T173
Test name
Test status
Simulation time 1446310000 ps
CPU time 3.92 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:58:59 PM PDT 24
Peak memory 164896 kb
Host smart-898671fe-2fc0-4535-a785-c106a74ce448
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2662010573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2662010573
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.483521390
Short name T177
Test name
Test status
Simulation time 1524450000 ps
CPU time 5.74 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 05:59:01 PM PDT 24
Peak memory 164884 kb
Host smart-f261f57b-cedf-4dc2-91f3-c47fcabf0a60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=483521390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.483521390
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2442071063
Short name T159
Test name
Test status
Simulation time 1459610000 ps
CPU time 4.45 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:00:02 PM PDT 24
Peak memory 161896 kb
Host smart-15ac70f6-1a60-4a6e-bfb5-f22ab65a82d3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2442071063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2442071063
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4125848747
Short name T184
Test name
Test status
Simulation time 1490310000 ps
CPU time 5.45 seconds
Started Jun 07 05:58:48 PM PDT 24
Finished Jun 07 05:59:00 PM PDT 24
Peak memory 164920 kb
Host smart-200f4240-d62a-4104-892c-b92c47e873a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4125848747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.4125848747
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1289048836
Short name T64
Test name
Test status
Simulation time 1252070000 ps
CPU time 5.14 seconds
Started Jun 07 06:00:24 PM PDT 24
Finished Jun 07 06:00:35 PM PDT 24
Peak memory 164896 kb
Host smart-503892ff-dd92-488f-834c-ea9aa0448d4b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289048836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1289048836
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.164603160
Short name T60
Test name
Test status
Simulation time 1540670000 ps
CPU time 3.1 seconds
Started Jun 07 06:04:01 PM PDT 24
Finished Jun 07 06:04:08 PM PDT 24
Peak memory 164548 kb
Host smart-328110f0-7558-4a06-8fa9-756b5fb7a9e7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=164603160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.164603160
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2332967845
Short name T50
Test name
Test status
Simulation time 1462950000 ps
CPU time 3.62 seconds
Started Jun 07 06:00:38 PM PDT 24
Finished Jun 07 06:00:46 PM PDT 24
Peak memory 164676 kb
Host smart-fdb1103b-9154-437c-b2f5-7e346e4c0b75
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332967845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2332967845
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.40105972
Short name T49
Test name
Test status
Simulation time 1368350000 ps
CPU time 5.28 seconds
Started Jun 07 06:03:37 PM PDT 24
Finished Jun 07 06:03:49 PM PDT 24
Peak memory 164656 kb
Host smart-4ef4d953-90da-4dae-96dc-5703044c3d17
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=40105972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.40105972
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2103301303
Short name T32
Test name
Test status
Simulation time 1450050000 ps
CPU time 5.38 seconds
Started Jun 07 06:00:16 PM PDT 24
Finished Jun 07 06:00:28 PM PDT 24
Peak memory 164920 kb
Host smart-e6d5fb8e-da69-440f-a27e-59145063da9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2103301303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2103301303
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3299716034
Short name T38
Test name
Test status
Simulation time 1233430000 ps
CPU time 3.9 seconds
Started Jun 07 06:04:03 PM PDT 24
Finished Jun 07 06:04:11 PM PDT 24
Peak memory 164428 kb
Host smart-1cd24e04-7dcc-4a5c-a8ed-ec3db7d7721a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299716034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3299716034
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2954690357
Short name T59
Test name
Test status
Simulation time 1363750000 ps
CPU time 4.73 seconds
Started Jun 07 06:02:34 PM PDT 24
Finished Jun 07 06:02:44 PM PDT 24
Peak memory 164920 kb
Host smart-41db36d3-36fe-4541-a4e3-e264b91b1bc2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2954690357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2954690357
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.817209092
Short name T41
Test name
Test status
Simulation time 1442970000 ps
CPU time 3.76 seconds
Started Jun 07 06:03:28 PM PDT 24
Finished Jun 07 06:03:37 PM PDT 24
Peak memory 164640 kb
Host smart-c230c1da-d3c9-4e54-b731-a3e45d87da5d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=817209092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.817209092
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.282958809
Short name T61
Test name
Test status
Simulation time 1428290000 ps
CPU time 4.65 seconds
Started Jun 07 06:01:09 PM PDT 24
Finished Jun 07 06:01:20 PM PDT 24
Peak memory 164940 kb
Host smart-27c24c3a-bf94-4628-8900-2b85ff771845
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=282958809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.282958809
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3567481959
Short name T3
Test name
Test status
Simulation time 1417810000 ps
CPU time 3.4 seconds
Started Jun 07 06:00:51 PM PDT 24
Finished Jun 07 06:00:59 PM PDT 24
Peak memory 164716 kb
Host smart-c7564bcf-476a-4f21-b5a0-ee2b62a94c41
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567481959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3567481959
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.847970450
Short name T45
Test name
Test status
Simulation time 1523250000 ps
CPU time 4.22 seconds
Started Jun 07 06:04:03 PM PDT 24
Finished Jun 07 06:04:13 PM PDT 24
Peak memory 164504 kb
Host smart-4cbfb2ec-3299-40c7-a93f-c54e5f21a508
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=847970450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.847970450
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2526173683
Short name T56
Test name
Test status
Simulation time 1323490000 ps
CPU time 4.37 seconds
Started Jun 07 06:03:38 PM PDT 24
Finished Jun 07 06:03:48 PM PDT 24
Peak memory 162704 kb
Host smart-ef622355-b84f-487e-8f9f-bbae40429237
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526173683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2526173683
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3753304418
Short name T34
Test name
Test status
Simulation time 1586790000 ps
CPU time 4.43 seconds
Started Jun 07 06:04:16 PM PDT 24
Finished Jun 07 06:04:26 PM PDT 24
Peak memory 164692 kb
Host smart-308edc13-0180-4a63-902c-ddcc6d76cd70
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3753304418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3753304418
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.749262801
Short name T33
Test name
Test status
Simulation time 1397510000 ps
CPU time 2.79 seconds
Started Jun 07 06:04:11 PM PDT 24
Finished Jun 07 06:04:18 PM PDT 24
Peak memory 164328 kb
Host smart-cac9f0d2-add4-4112-8b58-a569ced8de92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749262801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.749262801
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2957269185
Short name T11
Test name
Test status
Simulation time 1463750000 ps
CPU time 3.51 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:18 PM PDT 24
Peak memory 162592 kb
Host smart-da6a5982-9f4f-42d0-940c-3bc1892f678f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2957269185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2957269185
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.500210488
Short name T2
Test name
Test status
Simulation time 1356010000 ps
CPU time 4.13 seconds
Started Jun 07 05:59:27 PM PDT 24
Finished Jun 07 05:59:36 PM PDT 24
Peak memory 164672 kb
Host smart-527ca261-5caa-4eb8-b7dd-568a8193b0ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=500210488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.500210488
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.4059186393
Short name T36
Test name
Test status
Simulation time 1438330000 ps
CPU time 3.56 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:18 PM PDT 24
Peak memory 162488 kb
Host smart-aa2e4eef-390c-4ddb-96db-9fd46a8defd6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4059186393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.4059186393
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3385023812
Short name T53
Test name
Test status
Simulation time 1567430000 ps
CPU time 5.84 seconds
Started Jun 07 06:00:19 PM PDT 24
Finished Jun 07 06:00:33 PM PDT 24
Peak memory 164920 kb
Host smart-bdaa8ac7-39c4-4475-9a81-92b1523a13ca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3385023812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3385023812
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3315565084
Short name T63
Test name
Test status
Simulation time 1506670000 ps
CPU time 4.85 seconds
Started Jun 07 06:01:03 PM PDT 24
Finished Jun 07 06:01:14 PM PDT 24
Peak memory 164696 kb
Host smart-13e47e97-35bd-40ff-949b-985012dcdc8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315565084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3315565084
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.4177904821
Short name T35
Test name
Test status
Simulation time 1414150000 ps
CPU time 4.06 seconds
Started Jun 07 05:59:22 PM PDT 24
Finished Jun 07 05:59:31 PM PDT 24
Peak memory 164836 kb
Host smart-c8f58bfd-996e-476d-9307-c3958e5672ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4177904821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.4177904821
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3610156326
Short name T37
Test name
Test status
Simulation time 1559090000 ps
CPU time 4.34 seconds
Started Jun 07 05:58:45 PM PDT 24
Finished Jun 07 05:58:55 PM PDT 24
Peak memory 164680 kb
Host smart-c801af1e-cc4f-453b-98f2-0ff506d3c13f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3610156326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3610156326
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3669483398
Short name T7
Test name
Test status
Simulation time 1508130000 ps
CPU time 4.37 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:58:59 PM PDT 24
Peak memory 164920 kb
Host smart-3c2de652-d1b7-48f6-af65-063052f69de8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669483398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3669483398
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.178987512
Short name T66
Test name
Test status
Simulation time 1295450000 ps
CPU time 3.45 seconds
Started Jun 07 06:02:17 PM PDT 24
Finished Jun 07 06:02:25 PM PDT 24
Peak memory 164700 kb
Host smart-f2c558cc-f561-4cc4-a62d-f98654e3bc24
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=178987512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.178987512
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1295110011
Short name T67
Test name
Test status
Simulation time 1477370000 ps
CPU time 4.46 seconds
Started Jun 07 05:58:42 PM PDT 24
Finished Jun 07 05:58:52 PM PDT 24
Peak memory 164756 kb
Host smart-8d7ca160-905f-4cef-a93c-e98d548df8d0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1295110011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1295110011
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.244870550
Short name T54
Test name
Test status
Simulation time 1536790000 ps
CPU time 5.89 seconds
Started Jun 07 05:58:49 PM PDT 24
Finished Jun 07 05:59:02 PM PDT 24
Peak memory 164936 kb
Host smart-94a65d2d-91af-4afa-b5d2-81989415f6cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=244870550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.244870550
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.144921443
Short name T51
Test name
Test status
Simulation time 1571830000 ps
CPU time 5.53 seconds
Started Jun 07 05:59:32 PM PDT 24
Finished Jun 07 05:59:45 PM PDT 24
Peak memory 164824 kb
Host smart-4dec1e64-5618-41d4-a905-2f96d29099aa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=144921443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.144921443
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.291112005
Short name T43
Test name
Test status
Simulation time 1432930000 ps
CPU time 4.21 seconds
Started Jun 07 05:58:43 PM PDT 24
Finished Jun 07 05:58:53 PM PDT 24
Peak memory 163124 kb
Host smart-a9aa1f62-747a-4e20-926f-224502d18edb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=291112005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.291112005
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1272834103
Short name T62
Test name
Test status
Simulation time 1363790000 ps
CPU time 4.16 seconds
Started Jun 07 05:59:24 PM PDT 24
Finished Jun 07 05:59:33 PM PDT 24
Peak memory 164872 kb
Host smart-6d4586c9-b69d-44d1-8e89-3af338f741f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1272834103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1272834103
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.577855542
Short name T68
Test name
Test status
Simulation time 1315630000 ps
CPU time 4.09 seconds
Started Jun 07 05:59:52 PM PDT 24
Finished Jun 07 06:00:01 PM PDT 24
Peak memory 161876 kb
Host smart-d4ccae7e-9e4b-428b-b2df-7cb051302e52
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=577855542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.577855542
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2342051371
Short name T55
Test name
Test status
Simulation time 1421650000 ps
CPU time 5.26 seconds
Started Jun 07 06:02:51 PM PDT 24
Finished Jun 07 06:03:04 PM PDT 24
Peak memory 164836 kb
Host smart-703fa43e-ca0d-4731-9dba-ed2e3ef436ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342051371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2342051371
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3705179464
Short name T8
Test name
Test status
Simulation time 1506570000 ps
CPU time 4.32 seconds
Started Jun 07 05:58:45 PM PDT 24
Finished Jun 07 05:58:55 PM PDT 24
Peak memory 164516 kb
Host smart-0f23b7eb-e15a-47e6-9398-3020e9a72472
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705179464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3705179464
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2305704900
Short name T31
Test name
Test status
Simulation time 1493110000 ps
CPU time 4.73 seconds
Started Jun 07 05:59:13 PM PDT 24
Finished Jun 07 05:59:24 PM PDT 24
Peak memory 164700 kb
Host smart-7fb11b27-9cbd-47af-a9ad-de198206930e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2305704900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2305704900
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1826503372
Short name T47
Test name
Test status
Simulation time 1134910000 ps
CPU time 3.78 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 05:59:58 PM PDT 24
Peak memory 163100 kb
Host smart-c51bf163-08af-4bcb-905c-3eb9a0bb3fcf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1826503372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1826503372
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1052846083
Short name T10
Test name
Test status
Simulation time 1489850000 ps
CPU time 4.82 seconds
Started Jun 07 05:59:25 PM PDT 24
Finished Jun 07 05:59:36 PM PDT 24
Peak memory 164804 kb
Host smart-eda6bcd9-eb88-432d-a697-752274dcf557
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1052846083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1052846083
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1325518933
Short name T42
Test name
Test status
Simulation time 1523890000 ps
CPU time 3.73 seconds
Started Jun 07 06:03:42 PM PDT 24
Finished Jun 07 06:03:51 PM PDT 24
Peak memory 163836 kb
Host smart-ffdf8b5a-7006-42b1-9242-96531190bdbc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1325518933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1325518933
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2957762234
Short name T46
Test name
Test status
Simulation time 1492030000 ps
CPU time 4.68 seconds
Started Jun 07 06:02:10 PM PDT 24
Finished Jun 07 06:02:21 PM PDT 24
Peak memory 164728 kb
Host smart-1e8d9d37-1f07-45b1-b05c-101f9f29e41c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2957762234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2957762234
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2171193056
Short name T70
Test name
Test status
Simulation time 1610550000 ps
CPU time 4.1 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:34 PM PDT 24
Peak memory 163676 kb
Host smart-3bf29a97-ac19-48fb-adcf-d77414cf6872
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2171193056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2171193056
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3630617761
Short name T44
Test name
Test status
Simulation time 1470550000 ps
CPU time 3.04 seconds
Started Jun 07 06:03:20 PM PDT 24
Finished Jun 07 06:03:28 PM PDT 24
Peak memory 163676 kb
Host smart-62679fe1-866e-4c79-bde6-e9af2757bf28
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3630617761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3630617761
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4115963109
Short name T13
Test name
Test status
Simulation time 1477230000 ps
CPU time 2.81 seconds
Started Jun 07 06:04:16 PM PDT 24
Finished Jun 07 06:04:27 PM PDT 24
Peak memory 164092 kb
Host smart-7985764a-523f-47e9-927f-5fd3bad55a2a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4115963109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4115963109
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2636866571
Short name T39
Test name
Test status
Simulation time 1295770000 ps
CPU time 3.37 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:14 PM PDT 24
Peak memory 164692 kb
Host smart-ffeee940-74c7-4aaf-b881-c6ad72463ee7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636866571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2636866571
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2872984879
Short name T40
Test name
Test status
Simulation time 1560850000 ps
CPU time 3.2 seconds
Started Jun 07 06:03:18 PM PDT 24
Finished Jun 07 06:03:25 PM PDT 24
Peak memory 164332 kb
Host smart-e192566a-de75-4a6a-866a-6552e88144ea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2872984879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2872984879
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3115094697
Short name T48
Test name
Test status
Simulation time 1478430000 ps
CPU time 3.1 seconds
Started Jun 07 06:03:46 PM PDT 24
Finished Jun 07 06:03:53 PM PDT 24
Peak memory 164364 kb
Host smart-ba7564eb-83b0-4f53-998b-b6800f8b5a88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3115094697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3115094697
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.832168810
Short name T58
Test name
Test status
Simulation time 1073350000 ps
CPU time 2.64 seconds
Started Jun 07 06:03:17 PM PDT 24
Finished Jun 07 06:03:23 PM PDT 24
Peak memory 164864 kb
Host smart-db939e47-ac0f-4492-b578-2c18293cbef9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=832168810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.832168810
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1815077578
Short name T52
Test name
Test status
Simulation time 1279990000 ps
CPU time 4.41 seconds
Started Jun 07 06:01:53 PM PDT 24
Finished Jun 07 06:02:03 PM PDT 24
Peak memory 164696 kb
Host smart-5fbb7e1e-20fe-4f90-9790-359831a0345b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1815077578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1815077578
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.148388230
Short name T57
Test name
Test status
Simulation time 1513530000 ps
CPU time 5.71 seconds
Started Jun 07 06:03:37 PM PDT 24
Finished Jun 07 06:03:50 PM PDT 24
Peak memory 164596 kb
Host smart-e3b56198-68da-4e31-8a12-fd23523f9d67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=148388230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.148388230
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1026897810
Short name T12
Test name
Test status
Simulation time 1293530000 ps
CPU time 4.14 seconds
Started Jun 07 06:03:40 PM PDT 24
Finished Jun 07 06:03:49 PM PDT 24
Peak memory 164444 kb
Host smart-2da50989-a039-460d-8d5e-7f6967b6ca2c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1026897810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1026897810
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3210457810
Short name T69
Test name
Test status
Simulation time 1435510000 ps
CPU time 4.9 seconds
Started Jun 07 06:01:35 PM PDT 24
Finished Jun 07 06:01:47 PM PDT 24
Peak memory 164696 kb
Host smart-c178e701-4571-4228-8a8d-43285b5347ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3210457810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3210457810
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3349671275
Short name T65
Test name
Test status
Simulation time 1506670000 ps
CPU time 4.16 seconds
Started Jun 07 05:59:39 PM PDT 24
Finished Jun 07 05:59:49 PM PDT 24
Peak memory 164780 kb
Host smart-69a6c50d-dc2b-4123-a1cb-bf842fd1cffb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3349671275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3349671275
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.711728675
Short name T1
Test name
Test status
Simulation time 1356990000 ps
CPU time 4.44 seconds
Started Jun 07 06:00:04 PM PDT 24
Finished Jun 07 06:00:14 PM PDT 24
Peak memory 164708 kb
Host smart-2220fb52-aa4a-4fc2-9a59-009f074e5b3d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=711728675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.711728675
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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