| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.165953253 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2913997443 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3849181785 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.967193625 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2332270432 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.131748748 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.465245938 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2550739012 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1451921904 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1465861814 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3107460968 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.846087146 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3334629836 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.673446901 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.370683143 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3023859848 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1578030425 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2772345935 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2888179942 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.41065202 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.359679693 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.602892550 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3204648544 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1413901761 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2963878598 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2950590543 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1834864598 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3712736475 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1603235532 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.204939189 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1113793673 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2303251614 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2022346877 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2989278045 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.956403773 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1963045247 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2026722128 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3601432982 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2688992343 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3641257119 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1536843384 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2236941486 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3205194229 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3237663802 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1280390447 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.4209144646 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2424462081 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1920752062 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1265133285 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4237640883 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3573204696 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3532914266 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3436835536 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3850745613 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1878363121 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2533497559 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3015946614 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2273572925 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2026893649 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3220064729 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2323229894 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.604025829 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1310691432 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1329036840 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.114705614 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3132338781 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.431909883 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2621884326 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1271050121 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1454014009 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4241659922 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1829989080 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3005895298 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3451411010 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4151870842 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.794090810 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1893925730 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3865195820 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4187557483 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1609921865 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2831533452 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3037902395 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1090516098 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1963581141 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.681221590 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2025130859 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1783227380 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3342913292 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.784267697 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2034144767 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1577243972 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4225089746 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1714932464 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3662877025 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1823770942 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4110801282 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3349867256 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3468010500 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.992455808 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1745287562 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.314754706 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3324116773 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2291822803 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.335149285 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3565325232 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3442187285 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2421081639 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2148554937 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1892151021 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1375567842 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1364038178 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2601304483 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2289417415 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1996856621 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1993395191 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3695647368 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4083881618 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.263456810 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2094598428 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.152383046 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1892195643 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.721597148 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4120753408 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.271926435 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.881396350 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3237873730 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3768785835 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3554415940 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1604575131 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3185552918 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2426832591 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4244474367 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2614162659 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3401623666 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3586443063 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2535961538 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.125284123 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2953745231 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3088635572 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.41807566 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1343606425 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1244017445 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2940968965 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3358607949 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2710442581 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.86727387 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2269244982 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.107751503 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3265815810 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.231615150 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3665306385 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.575864927 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2465623653 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3439086124 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4265343246 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3364804134 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3476978537 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3178735215 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1323385548 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3727820007 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2493048039 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.784755550 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2678457097 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2229646316 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.6052031 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2317993866 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3622027569 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1150799775 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1985084351 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3764647430 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1560834068 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.618894963 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3501369680 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.939322852 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2285781178 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3473793881 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.260557180 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.143470479 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3394668550 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.688196845 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3154047957 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1136333331 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3748005411 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1867507201 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3681963152 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1066892165 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3417448253 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3202858758 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4116796424 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2289530855 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1692916496 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.771302428 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2604076401 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2327964237 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2480835281 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.734066863 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3571072849 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1350900411 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1159591954 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.679580 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2480835281 | Jun 09 12:21:14 PM PDT 24 | Jun 09 12:21:21 PM PDT 24 | 1350670000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.771302428 | Jun 09 12:20:05 PM PDT 24 | Jun 09 12:20:15 PM PDT 24 | 1431170000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3394668550 | Jun 09 12:20:05 PM PDT 24 | Jun 09 12:20:14 PM PDT 24 | 1398590000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3764647430 | Jun 09 12:21:19 PM PDT 24 | Jun 09 12:21:29 PM PDT 24 | 1468330000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2327964237 | Jun 09 12:22:14 PM PDT 24 | Jun 09 12:22:24 PM PDT 24 | 1538590000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1159591954 | Jun 09 12:16:55 PM PDT 24 | Jun 09 12:17:05 PM PDT 24 | 1496310000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1350900411 | Jun 09 12:21:42 PM PDT 24 | Jun 09 12:21:54 PM PDT 24 | 1220370000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3501369680 | Jun 09 12:21:26 PM PDT 24 | Jun 09 12:21:34 PM PDT 24 | 1444410000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.939322852 | Jun 09 12:20:10 PM PDT 24 | Jun 09 12:20:20 PM PDT 24 | 1642730000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.165953253 | Jun 09 12:21:10 PM PDT 24 | Jun 09 12:21:19 PM PDT 24 | 1272590000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3571072849 | Jun 09 12:21:42 PM PDT 24 | Jun 09 12:21:54 PM PDT 24 | 1261050000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2678457097 | Jun 09 12:17:22 PM PDT 24 | Jun 09 12:17:34 PM PDT 24 | 1402310000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.679580 | Jun 09 12:21:09 PM PDT 24 | Jun 09 12:21:18 PM PDT 24 | 1534610000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1985084351 | Jun 09 12:16:28 PM PDT 24 | Jun 09 12:16:37 PM PDT 24 | 1557370000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2229646316 | Jun 09 12:21:08 PM PDT 24 | Jun 09 12:21:20 PM PDT 24 | 1585030000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1692916496 | Jun 09 12:18:40 PM PDT 24 | Jun 09 12:18:49 PM PDT 24 | 1325470000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1136333331 | Jun 09 12:21:08 PM PDT 24 | Jun 09 12:21:20 PM PDT 24 | 1485730000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3473793881 | Jun 09 12:16:35 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1515430000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.143470479 | Jun 09 12:21:15 PM PDT 24 | Jun 09 12:21:26 PM PDT 24 | 1584510000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.784755550 | Jun 09 12:21:09 PM PDT 24 | Jun 09 12:21:20 PM PDT 24 | 1531570000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3202858758 | Jun 09 12:22:32 PM PDT 24 | Jun 09 12:22:43 PM PDT 24 | 1508930000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2285781178 | Jun 09 12:22:31 PM PDT 24 | Jun 09 12:22:42 PM PDT 24 | 1464630000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3476978537 | Jun 09 12:21:42 PM PDT 24 | Jun 09 12:21:55 PM PDT 24 | 1485130000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3154047957 | Jun 09 12:22:30 PM PDT 24 | Jun 09 12:22:41 PM PDT 24 | 1459110000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1066892165 | Jun 09 12:19:41 PM PDT 24 | Jun 09 12:19:52 PM PDT 24 | 1526830000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2604076401 | Jun 09 12:16:38 PM PDT 24 | Jun 09 12:16:47 PM PDT 24 | 1608890000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.575864927 | Jun 09 12:22:02 PM PDT 24 | Jun 09 12:22:08 PM PDT 24 | 1227230000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4265343246 | Jun 09 12:21:42 PM PDT 24 | Jun 09 12:21:55 PM PDT 24 | 1534270000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4116796424 | Jun 09 12:17:34 PM PDT 24 | Jun 09 12:17:42 PM PDT 24 | 1538430000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2317993866 | Jun 09 12:21:16 PM PDT 24 | Jun 09 12:21:24 PM PDT 24 | 1345010000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3417448253 | Jun 09 12:18:59 PM PDT 24 | Jun 09 12:19:10 PM PDT 24 | 1425950000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3178735215 | Jun 09 12:21:40 PM PDT 24 | Jun 09 12:21:50 PM PDT 24 | 1187090000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1323385548 | Jun 09 12:21:13 PM PDT 24 | Jun 09 12:21:24 PM PDT 24 | 1367910000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.6052031 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:21:23 PM PDT 24 | 1522770000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2493048039 | Jun 09 12:21:13 PM PDT 24 | Jun 09 12:21:25 PM PDT 24 | 1587990000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3622027569 | Jun 09 12:16:51 PM PDT 24 | Jun 09 12:17:03 PM PDT 24 | 1537070000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3748005411 | Jun 09 12:21:10 PM PDT 24 | Jun 09 12:21:22 PM PDT 24 | 1471790000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1867507201 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:21:20 PM PDT 24 | 1469390000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3681963152 | Jun 09 12:17:22 PM PDT 24 | Jun 09 12:17:34 PM PDT 24 | 1469490000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.734066863 | Jun 09 12:20:10 PM PDT 24 | Jun 09 12:20:20 PM PDT 24 | 1572310000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.688196845 | Jun 09 12:18:20 PM PDT 24 | Jun 09 12:18:28 PM PDT 24 | 1112050000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3364804134 | Jun 09 12:21:42 PM PDT 24 | Jun 09 12:21:55 PM PDT 24 | 1506490000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2465623653 | Jun 09 12:19:47 PM PDT 24 | Jun 09 12:19:59 PM PDT 24 | 1562310000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3727820007 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:21:22 PM PDT 24 | 1503570000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.618894963 | Jun 09 12:19:13 PM PDT 24 | Jun 09 12:19:24 PM PDT 24 | 1564210000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1560834068 | Jun 09 12:21:19 PM PDT 24 | Jun 09 12:21:29 PM PDT 24 | 1493750000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2289530855 | Jun 09 12:17:27 PM PDT 24 | Jun 09 12:17:36 PM PDT 24 | 1363950000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3439086124 | Jun 09 12:19:12 PM PDT 24 | Jun 09 12:19:23 PM PDT 24 | 1460410000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1150799775 | Jun 09 12:19:13 PM PDT 24 | Jun 09 12:19:25 PM PDT 24 | 1614530000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.260557180 | Jun 09 12:22:14 PM PDT 24 | Jun 09 12:22:22 PM PDT 24 | 1163690000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3088635572 | Jun 09 12:18:58 PM PDT 24 | Jun 09 12:19:10 PM PDT 24 | 1514050000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2710442581 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:21:40 PM PDT 24 | 1470070000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1364038178 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1585810000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.967193625 | Jun 09 12:17:46 PM PDT 24 | Jun 09 12:17:56 PM PDT 24 | 1493130000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.231615150 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1557550000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.263456810 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1589450000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1892151021 | Jun 09 12:18:03 PM PDT 24 | Jun 09 12:18:14 PM PDT 24 | 1342550000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1892195643 | Jun 09 12:22:12 PM PDT 24 | Jun 09 12:22:20 PM PDT 24 | 1576970000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3401623666 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:16:44 PM PDT 24 | 1605870000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1343606425 | Jun 09 12:22:06 PM PDT 24 | Jun 09 12:22:14 PM PDT 24 | 1217830000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.335149285 | Jun 09 12:16:29 PM PDT 24 | Jun 09 12:16:40 PM PDT 24 | 1337430000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3358607949 | Jun 09 12:16:58 PM PDT 24 | Jun 09 12:17:08 PM PDT 24 | 1597690000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2940968965 | Jun 09 12:22:21 PM PDT 24 | Jun 09 12:22:31 PM PDT 24 | 1429790000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.41807566 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:16:40 PM PDT 24 | 1439670000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2601304483 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:41 PM PDT 24 | 1332250000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2614162659 | Jun 09 12:21:46 PM PDT 24 | Jun 09 12:21:52 PM PDT 24 | 1461390000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.271926435 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:41 PM PDT 24 | 1536930000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3695647368 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:41 PM PDT 24 | 1431070000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3237873730 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:16:42 PM PDT 24 | 1362790000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1993395191 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:16:42 PM PDT 24 | 1427770000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3265815810 | Jun 09 12:16:26 PM PDT 24 | Jun 09 12:16:35 PM PDT 24 | 1428330000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1604575131 | Jun 09 12:22:01 PM PDT 24 | Jun 09 12:22:11 PM PDT 24 | 1584150000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4083881618 | Jun 09 12:17:46 PM PDT 24 | Jun 09 12:17:57 PM PDT 24 | 1511310000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2269244982 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:42 PM PDT 24 | 1481230000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2426832591 | Jun 09 12:16:52 PM PDT 24 | Jun 09 12:17:04 PM PDT 24 | 1489770000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2291822803 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:16:41 PM PDT 24 | 1254630000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4120753408 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1427090000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2094598428 | Jun 09 12:22:01 PM PDT 24 | Jun 09 12:22:08 PM PDT 24 | 1373010000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2148554937 | Jun 09 12:17:29 PM PDT 24 | Jun 09 12:17:36 PM PDT 24 | 1346210000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.881396350 | Jun 09 12:17:47 PM PDT 24 | Jun 09 12:17:57 PM PDT 24 | 1519470000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3586443063 | Jun 09 12:17:22 PM PDT 24 | Jun 09 12:17:34 PM PDT 24 | 1490370000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3768785835 | Jun 09 12:17:44 PM PDT 24 | Jun 09 12:17:53 PM PDT 24 | 1313990000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3185552918 | Jun 09 12:21:42 PM PDT 24 | Jun 09 12:21:49 PM PDT 24 | 1325330000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1375567842 | Jun 09 12:17:47 PM PDT 24 | Jun 09 12:17:58 PM PDT 24 | 1564230000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3565325232 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:40 PM PDT 24 | 1368270000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3665306385 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:40 PM PDT 24 | 1149330000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1244017445 | Jun 09 12:21:10 PM PDT 24 | Jun 09 12:21:22 PM PDT 24 | 1556770000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2421081639 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:16:42 PM PDT 24 | 1457650000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.107751503 | Jun 09 12:16:52 PM PDT 24 | Jun 09 12:17:02 PM PDT 24 | 1480710000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2289417415 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1419350000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.125284123 | Jun 09 12:16:27 PM PDT 24 | Jun 09 12:16:37 PM PDT 24 | 1460370000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3554415940 | Jun 09 12:16:18 PM PDT 24 | Jun 09 12:16:28 PM PDT 24 | 1593910000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4244474367 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:16:42 PM PDT 24 | 1511470000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1996856621 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:43 PM PDT 24 | 1489530000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.152383046 | Jun 09 12:16:29 PM PDT 24 | Jun 09 12:16:41 PM PDT 24 | 1470730000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2953745231 | Jun 09 12:16:43 PM PDT 24 | Jun 09 12:16:52 PM PDT 24 | 1391130000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.86727387 | Jun 09 12:22:28 PM PDT 24 | Jun 09 12:22:38 PM PDT 24 | 1483670000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3442187285 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:16:41 PM PDT 24 | 1463870000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2535961538 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:16:44 PM PDT 24 | 1559430000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.721597148 | Jun 09 12:16:53 PM PDT 24 | Jun 09 12:17:03 PM PDT 24 | 1331650000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2913997443 | Jun 09 12:17:26 PM PDT 24 | Jun 09 12:51:35 PM PDT 24 | 336364590000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.681221590 | Jun 09 12:17:48 PM PDT 24 | Jun 09 12:52:03 PM PDT 24 | 336779010000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1090516098 | Jun 09 12:21:51 PM PDT 24 | Jun 09 12:51:08 PM PDT 24 | 336432510000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1714932464 | Jun 09 12:22:06 PM PDT 24 | Jun 09 12:51:18 PM PDT 24 | 337002470000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1577243972 | Jun 09 12:22:30 PM PDT 24 | Jun 09 12:57:04 PM PDT 24 | 336422310000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3342913292 | Jun 09 12:16:53 PM PDT 24 | Jun 09 12:55:19 PM PDT 24 | 336712990000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1823770942 | Jun 09 12:19:31 PM PDT 24 | Jun 09 12:54:29 PM PDT 24 | 336465290000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4110801282 | Jun 09 12:22:07 PM PDT 24 | Jun 09 12:51:01 PM PDT 24 | 336437130000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.314754706 | Jun 09 12:21:13 PM PDT 24 | Jun 09 12:55:10 PM PDT 24 | 336963290000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4187557483 | Jun 09 12:17:47 PM PDT 24 | Jun 09 12:51:15 PM PDT 24 | 336955050000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2621884326 | Jun 09 12:16:29 PM PDT 24 | Jun 09 12:50:47 PM PDT 24 | 336713530000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3468010500 | Jun 09 12:16:28 PM PDT 24 | Jun 09 12:44:51 PM PDT 24 | 336744050000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4241659922 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:49:49 PM PDT 24 | 336290930000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2323229894 | Jun 09 12:21:18 PM PDT 24 | Jun 09 12:54:45 PM PDT 24 | 336631950000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2533497559 | Jun 09 12:21:18 PM PDT 24 | Jun 09 12:45:00 PM PDT 24 | 336956490000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3349867256 | Jun 09 12:22:14 PM PDT 24 | Jun 09 12:55:04 PM PDT 24 | 336419670000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3865195820 | Jun 09 12:22:02 PM PDT 24 | Jun 09 12:48:48 PM PDT 24 | 336489810000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2025130859 | Jun 09 12:17:07 PM PDT 24 | Jun 09 12:57:12 PM PDT 24 | 336341470000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3220064729 | Jun 09 12:22:29 PM PDT 24 | Jun 09 12:50:35 PM PDT 24 | 336491330000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2026893649 | Jun 09 12:21:18 PM PDT 24 | Jun 09 12:55:19 PM PDT 24 | 337112310000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1271050121 | Jun 09 12:19:44 PM PDT 24 | Jun 09 01:00:40 PM PDT 24 | 336792650000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.604025829 | Jun 09 12:16:27 PM PDT 24 | Jun 09 12:48:42 PM PDT 24 | 336475950000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4151870842 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:50:53 PM PDT 24 | 337035590000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3662877025 | Jun 09 12:21:10 PM PDT 24 | Jun 09 12:56:28 PM PDT 24 | 336519970000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1609921865 | Jun 09 12:16:29 PM PDT 24 | Jun 09 12:56:01 PM PDT 24 | 336928750000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1963581141 | Jun 09 12:21:51 PM PDT 24 | Jun 09 12:51:44 PM PDT 24 | 336565570000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3015946614 | Jun 09 12:17:27 PM PDT 24 | Jun 09 12:51:52 PM PDT 24 | 336708010000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1783227380 | Jun 09 12:17:25 PM PDT 24 | Jun 09 12:51:26 PM PDT 24 | 336783390000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3037902395 | Jun 09 12:18:15 PM PDT 24 | Jun 09 12:53:16 PM PDT 24 | 336611010000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.431909883 | Jun 09 12:21:13 PM PDT 24 | Jun 09 12:55:32 PM PDT 24 | 336946030000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2273572925 | Jun 09 12:20:10 PM PDT 24 | Jun 09 12:46:45 PM PDT 24 | 337067690000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1893925730 | Jun 09 12:16:52 PM PDT 24 | Jun 09 12:52:11 PM PDT 24 | 336862750000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.794090810 | Jun 09 12:21:10 PM PDT 24 | Jun 09 12:48:08 PM PDT 24 | 336896410000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3850745613 | Jun 09 12:21:09 PM PDT 24 | Jun 09 12:48:18 PM PDT 24 | 336468910000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.784267697 | Jun 09 12:21:08 PM PDT 24 | Jun 09 12:56:52 PM PDT 24 | 337008310000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1878363121 | Jun 09 12:21:40 PM PDT 24 | Jun 09 12:54:43 PM PDT 24 | 336967930000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.992455808 | Jun 09 12:21:40 PM PDT 24 | Jun 09 12:54:43 PM PDT 24 | 336515650000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3324116773 | Jun 09 12:21:09 PM PDT 24 | Jun 09 12:48:23 PM PDT 24 | 337011790000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3132338781 | Jun 09 12:17:30 PM PDT 24 | Jun 09 12:57:49 PM PDT 24 | 336360390000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4225089746 | Jun 09 12:21:08 PM PDT 24 | Jun 09 12:54:47 PM PDT 24 | 336625210000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1745287562 | Jun 09 12:17:27 PM PDT 24 | Jun 09 12:51:40 PM PDT 24 | 337125950000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2034144767 | Jun 09 12:18:19 PM PDT 24 | Jun 09 12:54:24 PM PDT 24 | 336842850000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2831533452 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:57:14 PM PDT 24 | 336761570000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1310691432 | Jun 09 12:21:18 PM PDT 24 | Jun 09 12:54:52 PM PDT 24 | 336763510000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.114705614 | Jun 09 12:21:13 PM PDT 24 | Jun 09 12:55:23 PM PDT 24 | 336493770000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1454014009 | Jun 09 12:19:53 PM PDT 24 | Jun 09 01:01:22 PM PDT 24 | 336645370000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1329036840 | Jun 09 12:21:18 PM PDT 24 | Jun 09 12:55:19 PM PDT 24 | 336725150000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3005895298 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:54:59 PM PDT 24 | 336728170000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3451411010 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:57:31 PM PDT 24 | 336886870000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1829989080 | Jun 09 12:19:52 PM PDT 24 | Jun 09 12:53:31 PM PDT 24 | 336725010000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3712736475 | Jun 09 12:22:21 PM PDT 24 | Jun 09 12:53:08 PM PDT 24 | 336703830000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.204939189 | Jun 09 12:21:27 PM PDT 24 | Jun 09 12:52:51 PM PDT 24 | 336479230000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2963878598 | Jun 09 12:21:09 PM PDT 24 | Jun 09 12:56:36 PM PDT 24 | 336855730000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3849181785 | Jun 09 12:22:01 PM PDT 24 | Jun 09 12:46:13 PM PDT 24 | 336957710000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1834864598 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:55:33 PM PDT 24 | 337057750000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.602892550 | Jun 09 12:22:22 PM PDT 24 | Jun 09 12:51:20 PM PDT 24 | 336462530000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2772345935 | Jun 09 12:22:21 PM PDT 24 | Jun 09 12:52:29 PM PDT 24 | 336611450000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3204648544 | Jun 09 12:21:33 PM PDT 24 | Jun 09 12:53:02 PM PDT 24 | 336396430000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.673446901 | Jun 09 12:21:38 PM PDT 24 | Jun 09 12:53:19 PM PDT 24 | 336352330000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3641257119 | Jun 09 12:21:15 PM PDT 24 | Jun 09 12:54:03 PM PDT 24 | 336762110000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3601432982 | Jun 09 12:21:13 PM PDT 24 | Jun 09 12:49:01 PM PDT 24 | 336425070000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.846087146 | Jun 09 12:17:47 PM PDT 24 | Jun 09 12:50:41 PM PDT 24 | 337022530000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3237663802 | Jun 09 12:22:37 PM PDT 24 | Jun 09 12:56:29 PM PDT 24 | 336915430000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2303251614 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:53:21 PM PDT 24 | 336820490000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.359679693 | Jun 09 12:17:08 PM PDT 24 | Jun 09 12:52:20 PM PDT 24 | 336414030000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1413901761 | Jun 09 12:22:21 PM PDT 24 | Jun 09 12:52:28 PM PDT 24 | 337200050000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2888179942 | Jun 09 12:22:14 PM PDT 24 | Jun 09 12:55:16 PM PDT 24 | 336457450000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2236941486 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:53:00 PM PDT 24 | 336779710000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1280390447 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:53:26 PM PDT 24 | 336563250000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1265133285 | Jun 09 12:16:34 PM PDT 24 | Jun 09 12:56:54 PM PDT 24 | 336498010000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1920752062 | Jun 09 12:16:38 PM PDT 24 | Jun 09 12:44:37 PM PDT 24 | 336926150000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1578030425 | Jun 09 12:22:31 PM PDT 24 | Jun 09 12:55:59 PM PDT 24 | 337037570000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.41065202 | Jun 09 12:18:40 PM PDT 24 | Jun 09 12:59:39 PM PDT 24 | 336510730000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2550739012 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:51:28 PM PDT 24 | 337141890000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3573204696 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:57:26 PM PDT 24 | 336802070000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3532914266 | Jun 09 12:17:47 PM PDT 24 | Jun 09 12:51:06 PM PDT 24 | 336902410000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2022346877 | Jun 09 12:21:15 PM PDT 24 | Jun 09 12:55:28 PM PDT 24 | 336809830000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1603235532 | Jun 09 12:17:30 PM PDT 24 | Jun 09 12:52:05 PM PDT 24 | 336470970000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3205194229 | Jun 09 12:22:35 PM PDT 24 | Jun 09 12:56:40 PM PDT 24 | 336885430000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1113793673 | Jun 09 12:18:41 PM PDT 24 | Jun 09 01:00:20 PM PDT 24 | 336404590000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2026722128 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:53:27 PM PDT 24 | 336453750000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.956403773 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:52:47 PM PDT 24 | 336395690000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.465245938 | Jun 09 12:22:03 PM PDT 24 | Jun 09 12:49:41 PM PDT 24 | 336736230000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3023859848 | Jun 09 12:16:30 PM PDT 24 | Jun 09 12:57:37 PM PDT 24 | 336411470000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1963045247 | Jun 09 12:21:32 PM PDT 24 | Jun 09 12:52:41 PM PDT 24 | 336904490000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1536843384 | Jun 09 12:21:16 PM PDT 24 | Jun 09 12:55:21 PM PDT 24 | 336554650000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3107460968 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:50:52 PM PDT 24 | 336749270000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3334629836 | Jun 09 12:16:31 PM PDT 24 | Jun 09 12:51:19 PM PDT 24 | 336384050000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3436835536 | Jun 09 12:16:32 PM PDT 24 | Jun 09 12:50:55 PM PDT 24 | 336451950000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2424462081 | Jun 09 12:16:50 PM PDT 24 | Jun 09 12:59:10 PM PDT 24 | 336334370000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1451921904 | Jun 09 12:18:46 PM PDT 24 | Jun 09 12:52:31 PM PDT 24 | 336659890000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2688992343 | Jun 09 12:21:15 PM PDT 24 | Jun 09 12:55:06 PM PDT 24 | 336501810000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.131748748 | Jun 09 12:17:31 PM PDT 24 | Jun 09 12:52:13 PM PDT 24 | 336910750000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2950590543 | Jun 09 12:22:30 PM PDT 24 | Jun 09 12:57:28 PM PDT 24 | 336396750000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1465861814 | Jun 09 12:17:47 PM PDT 24 | Jun 09 12:51:01 PM PDT 24 | 336988350000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2332270432 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:56:02 PM PDT 24 | 336840750000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.370683143 | Jun 09 12:16:27 PM PDT 24 | Jun 09 12:49:12 PM PDT 24 | 336493470000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.4209144646 | Jun 09 12:16:50 PM PDT 24 | Jun 09 12:59:13 PM PDT 24 | 336859950000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4237640883 | Jun 09 12:21:12 PM PDT 24 | Jun 09 12:55:48 PM PDT 24 | 336655210000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2989278045 | Jun 09 12:21:15 PM PDT 24 | Jun 09 12:55:15 PM PDT 24 | 337073630000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.165953253 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1272590000 ps |
| CPU time | 3.9 seconds |
| Started | Jun 09 12:21:10 PM PDT 24 |
| Finished | Jun 09 12:21:19 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-395ed758-1fe8-42eb-8fb0-2211d1547a40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=165953253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.165953253 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2913997443 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336364590000 ps |
| CPU time | 819.68 seconds |
| Started | Jun 09 12:17:26 PM PDT 24 |
| Finished | Jun 09 12:51:35 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-85fd53b8-2c1e-45dc-8edd-9e21a5be27b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2913997443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2913997443 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3849181785 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336957710000 ps |
| CPU time | 586.49 seconds |
| Started | Jun 09 12:22:01 PM PDT 24 |
| Finished | Jun 09 12:46:13 PM PDT 24 |
| Peak memory | 160584 kb |
| Host | smart-cb18b854-cbc3-4db2-b0e4-7c00ee77b5dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3849181785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3849181785 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.967193625 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1493130000 ps |
| CPU time | 4.5 seconds |
| Started | Jun 09 12:17:46 PM PDT 24 |
| Finished | Jun 09 12:17:56 PM PDT 24 |
| Peak memory | 164428 kb |
| Host | smart-cf89351d-d866-45e7-b8c5-ba4990f5fcd9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=967193625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.967193625 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2332270432 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336840750000 ps |
| CPU time | 837.76 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:56:02 PM PDT 24 |
| Peak memory | 159224 kb |
| Host | smart-8b21004d-d01a-49f0-bd56-fab7d2c6ce6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2332270432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2332270432 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.131748748 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336910750000 ps |
| CPU time | 838.22 seconds |
| Started | Jun 09 12:17:31 PM PDT 24 |
| Finished | Jun 09 12:52:13 PM PDT 24 |
| Peak memory | 160868 kb |
| Host | smart-3325a4c8-b33b-44ad-b5ad-ce17a79afbf5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=131748748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.131748748 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.465245938 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336736230000 ps |
| CPU time | 672.89 seconds |
| Started | Jun 09 12:22:03 PM PDT 24 |
| Finished | Jun 09 12:49:41 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-6b3f174a-22d8-49b6-9318-dd8a626b14cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=465245938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.465245938 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2550739012 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 337141890000 ps |
| CPU time | 845.76 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:51:28 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-566c814f-a63f-40da-b9c0-0d4c3e360875 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2550739012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2550739012 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1451921904 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336659890000 ps |
| CPU time | 835.59 seconds |
| Started | Jun 09 12:18:46 PM PDT 24 |
| Finished | Jun 09 12:52:31 PM PDT 24 |
| Peak memory | 160468 kb |
| Host | smart-5a50e0a1-31a5-4a1f-8de9-ea87252ce2f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1451921904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1451921904 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1465861814 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336988350000 ps |
| CPU time | 791.43 seconds |
| Started | Jun 09 12:17:47 PM PDT 24 |
| Finished | Jun 09 12:51:01 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-6f34f9f0-2ac7-4633-9fee-ed3085dab257 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1465861814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1465861814 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3107460968 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336749270000 ps |
| CPU time | 817.58 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:50:52 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-1f6994df-0018-426e-8acd-1e1105065ef7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3107460968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3107460968 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.846087146 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 337022530000 ps |
| CPU time | 799.59 seconds |
| Started | Jun 09 12:17:47 PM PDT 24 |
| Finished | Jun 09 12:50:41 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-cd6f4746-e467-4888-be0f-171f6e34e317 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=846087146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.846087146 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3334629836 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336384050000 ps |
| CPU time | 847.25 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:51:19 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-a6cb8006-8067-43fb-83c5-c81e625c33d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3334629836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3334629836 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.673446901 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336352330000 ps |
| CPU time | 775.09 seconds |
| Started | Jun 09 12:21:38 PM PDT 24 |
| Finished | Jun 09 12:53:19 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-1905756b-d39e-4f13-be75-257bbe5404ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=673446901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.673446901 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.370683143 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336493470000 ps |
| CPU time | 787.96 seconds |
| Started | Jun 09 12:16:27 PM PDT 24 |
| Finished | Jun 09 12:49:12 PM PDT 24 |
| Peak memory | 160116 kb |
| Host | smart-6beca4cf-504c-4888-bf69-a5fe44dd81eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=370683143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.370683143 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3023859848 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336411470000 ps |
| CPU time | 982.67 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:57:37 PM PDT 24 |
| Peak memory | 160864 kb |
| Host | smart-d040e5d2-1660-453f-96bc-b71744a06fa6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3023859848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3023859848 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1578030425 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 337037570000 ps |
| CPU time | 815.2 seconds |
| Started | Jun 09 12:22:31 PM PDT 24 |
| Finished | Jun 09 12:55:59 PM PDT 24 |
| Peak memory | 160408 kb |
| Host | smart-627fb994-6170-40d9-b6b3-489248e0de8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1578030425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1578030425 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2772345935 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336611450000 ps |
| CPU time | 735.29 seconds |
| Started | Jun 09 12:22:21 PM PDT 24 |
| Finished | Jun 09 12:52:29 PM PDT 24 |
| Peak memory | 160168 kb |
| Host | smart-6711df1a-ae11-4c71-a89a-be4b1834d8da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2772345935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2772345935 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2888179942 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336457450000 ps |
| CPU time | 800.26 seconds |
| Started | Jun 09 12:22:14 PM PDT 24 |
| Finished | Jun 09 12:55:16 PM PDT 24 |
| Peak memory | 159068 kb |
| Host | smart-af53e6f3-6aa6-4264-a7d3-73241807b95f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2888179942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2888179942 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.41065202 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336510730000 ps |
| CPU time | 979.21 seconds |
| Started | Jun 09 12:18:40 PM PDT 24 |
| Finished | Jun 09 12:59:39 PM PDT 24 |
| Peak memory | 160444 kb |
| Host | smart-05526ceb-444d-48e6-9200-05a4f86aaa64 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=41065202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.41065202 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.359679693 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336414030000 ps |
| CPU time | 873.18 seconds |
| Started | Jun 09 12:17:08 PM PDT 24 |
| Finished | Jun 09 12:52:20 PM PDT 24 |
| Peak memory | 160464 kb |
| Host | smart-a6b2b7f7-5745-473f-9b7b-a8400561fe59 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=359679693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.359679693 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.602892550 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336462530000 ps |
| CPU time | 708.12 seconds |
| Started | Jun 09 12:22:22 PM PDT 24 |
| Finished | Jun 09 12:51:20 PM PDT 24 |
| Peak memory | 160456 kb |
| Host | smart-559b8b44-d561-4bbc-9515-e5b72cfda0a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=602892550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.602892550 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3204648544 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336396430000 ps |
| CPU time | 752.31 seconds |
| Started | Jun 09 12:21:33 PM PDT 24 |
| Finished | Jun 09 12:53:02 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-4d729467-4470-41a9-8c9d-d7e9009f0b64 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3204648544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3204648544 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1413901761 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 337200050000 ps |
| CPU time | 735.12 seconds |
| Started | Jun 09 12:22:21 PM PDT 24 |
| Finished | Jun 09 12:52:28 PM PDT 24 |
| Peak memory | 160180 kb |
| Host | smart-045c29b3-ecef-4f8a-85ec-a1c841bca930 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1413901761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1413901761 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2963878598 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336855730000 ps |
| CPU time | 854.21 seconds |
| Started | Jun 09 12:21:09 PM PDT 24 |
| Finished | Jun 09 12:56:36 PM PDT 24 |
| Peak memory | 160144 kb |
| Host | smart-464fc57f-c845-46b7-ae98-ea072a0617a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2963878598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2963878598 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2950590543 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336396750000 ps |
| CPU time | 871.94 seconds |
| Started | Jun 09 12:22:30 PM PDT 24 |
| Finished | Jun 09 12:57:28 PM PDT 24 |
| Peak memory | 160408 kb |
| Host | smart-9be491ce-b7df-4b8e-8693-6c2ca8883057 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2950590543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2950590543 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1834864598 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 337057750000 ps |
| CPU time | 821.12 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:55:33 PM PDT 24 |
| Peak memory | 159200 kb |
| Host | smart-5500f808-4855-49e6-9068-e8b4426da8ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1834864598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1834864598 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3712736475 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336703830000 ps |
| CPU time | 758.6 seconds |
| Started | Jun 09 12:22:21 PM PDT 24 |
| Finished | Jun 09 12:53:08 PM PDT 24 |
| Peak memory | 159764 kb |
| Host | smart-5d8f1c04-bc30-4e62-9db2-9fa9d0c30c29 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3712736475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3712736475 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1603235532 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336470970000 ps |
| CPU time | 829.03 seconds |
| Started | Jun 09 12:17:30 PM PDT 24 |
| Finished | Jun 09 12:52:05 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-0af46089-ed02-48c6-bb66-95f143be40e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1603235532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1603235532 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.204939189 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336479230000 ps |
| CPU time | 762.85 seconds |
| Started | Jun 09 12:21:27 PM PDT 24 |
| Finished | Jun 09 12:52:51 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-fc33070a-96be-459b-a033-dd926e3ddecb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=204939189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.204939189 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1113793673 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336404590000 ps |
| CPU time | 991.5 seconds |
| Started | Jun 09 12:18:41 PM PDT 24 |
| Finished | Jun 09 01:00:20 PM PDT 24 |
| Peak memory | 160468 kb |
| Host | smart-c79ab006-6c69-4e99-8c65-bca0e195f728 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1113793673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1113793673 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2303251614 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336820490000 ps |
| CPU time | 763.03 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:53:21 PM PDT 24 |
| Peak memory | 160292 kb |
| Host | smart-cdf4a247-1aec-45bf-b712-c64009be2c99 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2303251614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2303251614 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2022346877 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336809830000 ps |
| CPU time | 819.03 seconds |
| Started | Jun 09 12:21:15 PM PDT 24 |
| Finished | Jun 09 12:55:28 PM PDT 24 |
| Peak memory | 160140 kb |
| Host | smart-30ec299e-5cfa-4d24-8733-45b3a0befbc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2022346877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2022346877 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2989278045 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 337073630000 ps |
| CPU time | 818.64 seconds |
| Started | Jun 09 12:21:15 PM PDT 24 |
| Finished | Jun 09 12:55:15 PM PDT 24 |
| Peak memory | 159072 kb |
| Host | smart-197230e1-cad3-43e2-bb1f-b165ea239720 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2989278045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2989278045 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.956403773 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336395690000 ps |
| CPU time | 747.89 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:52:47 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-c592279a-666d-4149-9e66-62ef98f836df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=956403773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.956403773 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1963045247 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336904490000 ps |
| CPU time | 746.71 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:52:41 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-cbc10c39-ba42-4a4d-b56d-8881ff815096 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1963045247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1963045247 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2026722128 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336453750000 ps |
| CPU time | 768.41 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:53:27 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-a9d53dc5-8c70-43e4-b9a4-9349b4327ea2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2026722128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2026722128 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3601432982 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336425070000 ps |
| CPU time | 674.96 seconds |
| Started | Jun 09 12:21:13 PM PDT 24 |
| Finished | Jun 09 12:49:01 PM PDT 24 |
| Peak memory | 160144 kb |
| Host | smart-83439bf2-d7bb-4f19-9a82-1d79a6531892 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3601432982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3601432982 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2688992343 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336501810000 ps |
| CPU time | 807.72 seconds |
| Started | Jun 09 12:21:15 PM PDT 24 |
| Finished | Jun 09 12:55:06 PM PDT 24 |
| Peak memory | 159276 kb |
| Host | smart-a7348771-32a6-425c-8777-4d8d6a1739f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2688992343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2688992343 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3641257119 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336762110000 ps |
| CPU time | 775.76 seconds |
| Started | Jun 09 12:21:15 PM PDT 24 |
| Finished | Jun 09 12:54:03 PM PDT 24 |
| Peak memory | 160296 kb |
| Host | smart-e35c3d34-89cb-4ac0-9674-ae4700494eb0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3641257119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3641257119 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1536843384 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336554650000 ps |
| CPU time | 812.52 seconds |
| Started | Jun 09 12:21:16 PM PDT 24 |
| Finished | Jun 09 12:55:21 PM PDT 24 |
| Peak memory | 160348 kb |
| Host | smart-b57ecd67-32e7-40c0-aca6-d5efc070e452 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1536843384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1536843384 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2236941486 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336779710000 ps |
| CPU time | 755.47 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:53:00 PM PDT 24 |
| Peak memory | 160424 kb |
| Host | smart-9e5429eb-2f4f-4137-bf47-8fdb22d46f30 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2236941486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2236941486 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3205194229 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336885430000 ps |
| CPU time | 850.17 seconds |
| Started | Jun 09 12:22:35 PM PDT 24 |
| Finished | Jun 09 12:56:40 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-0b6bc1a0-9457-45b5-8e72-4441f1783deb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3205194229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3205194229 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3237663802 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336915430000 ps |
| CPU time | 842.03 seconds |
| Started | Jun 09 12:22:37 PM PDT 24 |
| Finished | Jun 09 12:56:29 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-75ed2343-f3a1-41e3-af4e-234ac5531a27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3237663802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3237663802 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1280390447 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336563250000 ps |
| CPU time | 765.29 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:53:26 PM PDT 24 |
| Peak memory | 160324 kb |
| Host | smart-8f092b30-75ec-4ea7-9fe1-5256258fac26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1280390447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1280390447 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.4209144646 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336859950000 ps |
| CPU time | 1050.29 seconds |
| Started | Jun 09 12:16:50 PM PDT 24 |
| Finished | Jun 09 12:59:13 PM PDT 24 |
| Peak memory | 160212 kb |
| Host | smart-f3515856-2151-4406-97b8-624b092f5d97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4209144646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.4209144646 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2424462081 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336334370000 ps |
| CPU time | 1048.99 seconds |
| Started | Jun 09 12:16:50 PM PDT 24 |
| Finished | Jun 09 12:59:10 PM PDT 24 |
| Peak memory | 160212 kb |
| Host | smart-dd00513c-ec53-4ee7-85be-5f8e8d78a114 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2424462081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2424462081 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1920752062 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336926150000 ps |
| CPU time | 684.08 seconds |
| Started | Jun 09 12:16:38 PM PDT 24 |
| Finished | Jun 09 12:44:37 PM PDT 24 |
| Peak memory | 160468 kb |
| Host | smart-ffea3966-2138-4414-9887-b874587be243 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1920752062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1920752062 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1265133285 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336498010000 ps |
| CPU time | 998.76 seconds |
| Started | Jun 09 12:16:34 PM PDT 24 |
| Finished | Jun 09 12:56:54 PM PDT 24 |
| Peak memory | 159728 kb |
| Host | smart-c21f71bb-a491-4f09-92d0-88152812104e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1265133285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1265133285 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4237640883 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336655210000 ps |
| CPU time | 824.21 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:55:48 PM PDT 24 |
| Peak memory | 158792 kb |
| Host | smart-ba7b76dd-7230-42c2-a94a-dd6864c8c144 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4237640883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4237640883 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3573204696 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336802070000 ps |
| CPU time | 971.19 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:57:26 PM PDT 24 |
| Peak memory | 160864 kb |
| Host | smart-0a73d2b3-cb0a-4421-9c41-8bc6c90b0613 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3573204696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3573204696 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3532914266 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336902410000 ps |
| CPU time | 805.6 seconds |
| Started | Jun 09 12:17:47 PM PDT 24 |
| Finished | Jun 09 12:51:06 PM PDT 24 |
| Peak memory | 160444 kb |
| Host | smart-94cbf91b-270a-4cc5-ab9d-7596d576f214 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3532914266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3532914266 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3436835536 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336451950000 ps |
| CPU time | 827.46 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:50:55 PM PDT 24 |
| Peak memory | 160872 kb |
| Host | smart-c329b6ac-88ed-435b-990c-6362fea0210a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3436835536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3436835536 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3850745613 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336468910000 ps |
| CPU time | 655 seconds |
| Started | Jun 09 12:21:09 PM PDT 24 |
| Finished | Jun 09 12:48:18 PM PDT 24 |
| Peak memory | 160480 kb |
| Host | smart-c57e3dca-d926-45dc-976e-71c4f16a916c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3850745613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3850745613 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1878363121 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336967930000 ps |
| CPU time | 799.35 seconds |
| Started | Jun 09 12:21:40 PM PDT 24 |
| Finished | Jun 09 12:54:43 PM PDT 24 |
| Peak memory | 159276 kb |
| Host | smart-99095337-b47d-4cfb-9a6c-28ab7f7d60b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1878363121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1878363121 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2533497559 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336956490000 ps |
| CPU time | 565.07 seconds |
| Started | Jun 09 12:21:18 PM PDT 24 |
| Finished | Jun 09 12:45:00 PM PDT 24 |
| Peak memory | 160264 kb |
| Host | smart-af18c5d1-28e2-469a-9610-261bb086f9ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2533497559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2533497559 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3015946614 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336708010000 ps |
| CPU time | 825.37 seconds |
| Started | Jun 09 12:17:27 PM PDT 24 |
| Finished | Jun 09 12:51:52 PM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-316a7237-51b4-4e09-8160-28107bf09e3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3015946614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3015946614 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2273572925 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 337067690000 ps |
| CPU time | 642.65 seconds |
| Started | Jun 09 12:20:10 PM PDT 24 |
| Finished | Jun 09 12:46:45 PM PDT 24 |
| Peak memory | 159484 kb |
| Host | smart-2dedbc9b-a4e8-404c-8b73-7c173ab36d30 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2273572925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2273572925 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2026893649 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 337112310000 ps |
| CPU time | 809.31 seconds |
| Started | Jun 09 12:21:18 PM PDT 24 |
| Finished | Jun 09 12:55:19 PM PDT 24 |
| Peak memory | 158112 kb |
| Host | smart-51ca01f2-faa2-418c-84bd-77acd7dd8b2d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2026893649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2026893649 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3220064729 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336491330000 ps |
| CPU time | 677.73 seconds |
| Started | Jun 09 12:22:29 PM PDT 24 |
| Finished | Jun 09 12:50:35 PM PDT 24 |
| Peak memory | 160436 kb |
| Host | smart-40c298c4-bb1e-4e25-8755-b62cd7ce6e2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3220064729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3220064729 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2323229894 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336631950000 ps |
| CPU time | 795.82 seconds |
| Started | Jun 09 12:21:18 PM PDT 24 |
| Finished | Jun 09 12:54:45 PM PDT 24 |
| Peak memory | 158232 kb |
| Host | smart-4833bc6a-25fb-4212-83f3-10f1ad464580 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2323229894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2323229894 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.604025829 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336475950000 ps |
| CPU time | 780.47 seconds |
| Started | Jun 09 12:16:27 PM PDT 24 |
| Finished | Jun 09 12:48:42 PM PDT 24 |
| Peak memory | 159740 kb |
| Host | smart-ca974912-97cc-435d-a4de-b0e16ec543de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=604025829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.604025829 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1310691432 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336763510000 ps |
| CPU time | 798.06 seconds |
| Started | Jun 09 12:21:18 PM PDT 24 |
| Finished | Jun 09 12:54:52 PM PDT 24 |
| Peak memory | 158324 kb |
| Host | smart-8366c669-5e62-4bfa-b9d7-d9268ef292eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1310691432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1310691432 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1329036840 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336725150000 ps |
| CPU time | 805.36 seconds |
| Started | Jun 09 12:21:18 PM PDT 24 |
| Finished | Jun 09 12:55:19 PM PDT 24 |
| Peak memory | 158336 kb |
| Host | smart-8a78724c-0dbb-41fc-b973-f84becb64aa3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1329036840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1329036840 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.114705614 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336493770000 ps |
| CPU time | 817.61 seconds |
| Started | Jun 09 12:21:13 PM PDT 24 |
| Finished | Jun 09 12:55:23 PM PDT 24 |
| Peak memory | 160132 kb |
| Host | smart-aa9fccba-a5bc-495f-a2b8-b054473943f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=114705614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.114705614 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3132338781 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336360390000 ps |
| CPU time | 966.14 seconds |
| Started | Jun 09 12:17:30 PM PDT 24 |
| Finished | Jun 09 12:57:49 PM PDT 24 |
| Peak memory | 160868 kb |
| Host | smart-13b81d60-c0e5-4c6b-b6e4-6894165e9501 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3132338781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3132338781 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.431909883 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336946030000 ps |
| CPU time | 813.26 seconds |
| Started | Jun 09 12:21:13 PM PDT 24 |
| Finished | Jun 09 12:55:32 PM PDT 24 |
| Peak memory | 160200 kb |
| Host | smart-2b2698ca-5936-46c0-a5e6-6e34b41dc9df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=431909883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.431909883 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2621884326 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336713530000 ps |
| CPU time | 837.8 seconds |
| Started | Jun 09 12:16:29 PM PDT 24 |
| Finished | Jun 09 12:50:47 PM PDT 24 |
| Peak memory | 160212 kb |
| Host | smart-2d7fda5d-7759-437e-8df3-edeca12af3ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2621884326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2621884326 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1271050121 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336792650000 ps |
| CPU time | 1016.09 seconds |
| Started | Jun 09 12:19:44 PM PDT 24 |
| Finished | Jun 09 01:00:40 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-a870788b-0708-4feb-b039-13ad390fe5fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1271050121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1271050121 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1454014009 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336645370000 ps |
| CPU time | 1028.51 seconds |
| Started | Jun 09 12:19:53 PM PDT 24 |
| Finished | Jun 09 01:01:22 PM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-7c5e5bda-5ebb-4533-838f-76bdd718ed88 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1454014009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1454014009 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4241659922 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336290930000 ps |
| CPU time | 700.8 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:49:49 PM PDT 24 |
| Peak memory | 159680 kb |
| Host | smart-3bd26eec-0454-4865-af25-842152bee6b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4241659922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.4241659922 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1829989080 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336725010000 ps |
| CPU time | 829.89 seconds |
| Started | Jun 09 12:19:52 PM PDT 24 |
| Finished | Jun 09 12:53:31 PM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-fa47d6ba-216c-448d-a2d9-eb6f04466b59 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1829989080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1829989080 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3005895298 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336728170000 ps |
| CPU time | 802.66 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:54:59 PM PDT 24 |
| Peak memory | 160000 kb |
| Host | smart-6333b180-6a86-44de-b278-bdcd8df1a275 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3005895298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3005895298 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3451411010 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336886870000 ps |
| CPU time | 977.49 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:57:31 PM PDT 24 |
| Peak memory | 160880 kb |
| Host | smart-2f446c9d-0dac-47a5-9e06-9ddde9153a7e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3451411010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3451411010 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4151870842 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 337035590000 ps |
| CPU time | 826.93 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:50:53 PM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-82d531ea-c65a-4c69-bfbe-6afdcae1e2f0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4151870842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4151870842 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.794090810 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336896410000 ps |
| CPU time | 650.76 seconds |
| Started | Jun 09 12:21:10 PM PDT 24 |
| Finished | Jun 09 12:48:08 PM PDT 24 |
| Peak memory | 160484 kb |
| Host | smart-8234d82c-38b3-4800-b481-b96b06f2e8cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=794090810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.794090810 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1893925730 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336862750000 ps |
| CPU time | 879.32 seconds |
| Started | Jun 09 12:16:52 PM PDT 24 |
| Finished | Jun 09 12:52:11 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-b0f37b44-b326-438b-8822-1338a9e0340c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1893925730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1893925730 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3865195820 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336489810000 ps |
| CPU time | 659.11 seconds |
| Started | Jun 09 12:22:02 PM PDT 24 |
| Finished | Jun 09 12:48:48 PM PDT 24 |
| Peak memory | 160480 kb |
| Host | smart-e3a73b56-719b-4541-9bf2-fbea00dd0c5e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3865195820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3865195820 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4187557483 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336955050000 ps |
| CPU time | 803.9 seconds |
| Started | Jun 09 12:17:47 PM PDT 24 |
| Finished | Jun 09 12:51:15 PM PDT 24 |
| Peak memory | 160428 kb |
| Host | smart-f8fae826-9f48-4ceb-baa2-60b2e057c82f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4187557483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4187557483 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1609921865 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336928750000 ps |
| CPU time | 926.47 seconds |
| Started | Jun 09 12:16:29 PM PDT 24 |
| Finished | Jun 09 12:56:01 PM PDT 24 |
| Peak memory | 160880 kb |
| Host | smart-93dfc333-ea19-409e-900c-bc2b2448986d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1609921865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1609921865 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2831533452 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336761570000 ps |
| CPU time | 966.89 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:57:14 PM PDT 24 |
| Peak memory | 160880 kb |
| Host | smart-f05afd3b-2ae1-43ed-a59c-69f172f5227c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2831533452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2831533452 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.3037902395 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336611010000 ps |
| CPU time | 859.95 seconds |
| Started | Jun 09 12:18:15 PM PDT 24 |
| Finished | Jun 09 12:53:16 PM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-a868d02b-925f-4e9f-9edd-e07b11e7b6b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3037902395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.3037902395 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1090516098 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336432510000 ps |
| CPU time | 725.42 seconds |
| Started | Jun 09 12:21:51 PM PDT 24 |
| Finished | Jun 09 12:51:08 PM PDT 24 |
| Peak memory | 160588 kb |
| Host | smart-b09bb9e6-a730-42ce-96ca-a1d314cf1a37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1090516098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1090516098 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1963581141 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336565570000 ps |
| CPU time | 740.04 seconds |
| Started | Jun 09 12:21:51 PM PDT 24 |
| Finished | Jun 09 12:51:44 PM PDT 24 |
| Peak memory | 160552 kb |
| Host | smart-b229fe02-000c-42b4-a2b9-f193b37351bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1963581141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1963581141 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.681221590 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336779010000 ps |
| CPU time | 832.52 seconds |
| Started | Jun 09 12:17:48 PM PDT 24 |
| Finished | Jun 09 12:52:03 PM PDT 24 |
| Peak memory | 160428 kb |
| Host | smart-226aa188-326e-4614-800d-b212c23f93b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=681221590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.681221590 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2025130859 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336341470000 ps |
| CPU time | 963.5 seconds |
| Started | Jun 09 12:17:07 PM PDT 24 |
| Finished | Jun 09 12:57:12 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-be4d887d-c712-44d7-8729-5ad4b3709585 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2025130859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2025130859 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1783227380 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336783390000 ps |
| CPU time | 815.5 seconds |
| Started | Jun 09 12:17:25 PM PDT 24 |
| Finished | Jun 09 12:51:26 PM PDT 24 |
| Peak memory | 160876 kb |
| Host | smart-99f6cc3e-6c13-4d61-84b2-cf7dea0453ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1783227380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1783227380 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3342913292 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336712990000 ps |
| CPU time | 942.75 seconds |
| Started | Jun 09 12:16:53 PM PDT 24 |
| Finished | Jun 09 12:55:19 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-8a131509-8dd3-47b6-9ee8-b5beceef7e5b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3342913292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3342913292 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.784267697 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 337008310000 ps |
| CPU time | 859.35 seconds |
| Started | Jun 09 12:21:08 PM PDT 24 |
| Finished | Jun 09 12:56:52 PM PDT 24 |
| Peak memory | 159260 kb |
| Host | smart-aec8a5ed-062a-4d91-b432-e5b83ae3e5de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=784267697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.784267697 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2034144767 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336842850000 ps |
| CPU time | 835.72 seconds |
| Started | Jun 09 12:18:19 PM PDT 24 |
| Finished | Jun 09 12:54:24 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-381f78fc-03ac-4c39-9487-5c9d7cc2c6c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2034144767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2034144767 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1577243972 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336422310000 ps |
| CPU time | 859 seconds |
| Started | Jun 09 12:22:30 PM PDT 24 |
| Finished | Jun 09 12:57:04 PM PDT 24 |
| Peak memory | 160412 kb |
| Host | smart-65133fc7-fb37-41e5-819f-a05ecf875018 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1577243972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1577243972 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4225089746 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336625210000 ps |
| CPU time | 797.43 seconds |
| Started | Jun 09 12:21:08 PM PDT 24 |
| Finished | Jun 09 12:54:47 PM PDT 24 |
| Peak memory | 159512 kb |
| Host | smart-f81096fe-81ec-4aeb-9c7e-d0ce57e54ca9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4225089746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4225089746 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1714932464 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 337002470000 ps |
| CPU time | 713.18 seconds |
| Started | Jun 09 12:22:06 PM PDT 24 |
| Finished | Jun 09 12:51:18 PM PDT 24 |
| Peak memory | 159668 kb |
| Host | smart-6e12fc2f-1f7e-434f-a1ab-0938f694f400 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1714932464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1714932464 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3662877025 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336519970000 ps |
| CPU time | 851.89 seconds |
| Started | Jun 09 12:21:10 PM PDT 24 |
| Finished | Jun 09 12:56:28 PM PDT 24 |
| Peak memory | 160236 kb |
| Host | smart-017402f5-cbea-4929-a433-70e8c72325c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3662877025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3662877025 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1823770942 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336465290000 ps |
| CPU time | 861 seconds |
| Started | Jun 09 12:19:31 PM PDT 24 |
| Finished | Jun 09 12:54:29 PM PDT 24 |
| Peak memory | 160508 kb |
| Host | smart-355557dd-d6eb-417c-b6f7-176f3f8074fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1823770942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1823770942 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.4110801282 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336437130000 ps |
| CPU time | 695.42 seconds |
| Started | Jun 09 12:22:07 PM PDT 24 |
| Finished | Jun 09 12:51:01 PM PDT 24 |
| Peak memory | 160172 kb |
| Host | smart-525db08f-04c9-40d6-9665-da313b1338d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4110801282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.4110801282 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3349867256 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336419670000 ps |
| CPU time | 791.07 seconds |
| Started | Jun 09 12:22:14 PM PDT 24 |
| Finished | Jun 09 12:55:04 PM PDT 24 |
| Peak memory | 159056 kb |
| Host | smart-1795c9eb-b386-4820-a8f0-3e60a59278ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3349867256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3349867256 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3468010500 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336744050000 ps |
| CPU time | 689.4 seconds |
| Started | Jun 09 12:16:28 PM PDT 24 |
| Finished | Jun 09 12:44:51 PM PDT 24 |
| Peak memory | 160208 kb |
| Host | smart-620f53df-efd0-4513-a913-477b47c0a3a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3468010500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3468010500 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.992455808 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336515650000 ps |
| CPU time | 799.16 seconds |
| Started | Jun 09 12:21:40 PM PDT 24 |
| Finished | Jun 09 12:54:43 PM PDT 24 |
| Peak memory | 159072 kb |
| Host | smart-d161b650-1960-452e-b8e0-a8eb192a2833 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=992455808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.992455808 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1745287562 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 337125950000 ps |
| CPU time | 822.19 seconds |
| Started | Jun 09 12:17:27 PM PDT 24 |
| Finished | Jun 09 12:51:40 PM PDT 24 |
| Peak memory | 160876 kb |
| Host | smart-cf1296ab-2a66-490a-8376-6494bdeabbe8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1745287562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1745287562 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.314754706 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336963290000 ps |
| CPU time | 796.62 seconds |
| Started | Jun 09 12:21:13 PM PDT 24 |
| Finished | Jun 09 12:55:10 PM PDT 24 |
| Peak memory | 160124 kb |
| Host | smart-761051f5-459c-4009-acd4-e7777d95c934 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=314754706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.314754706 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3324116773 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 337011790000 ps |
| CPU time | 658.52 seconds |
| Started | Jun 09 12:21:09 PM PDT 24 |
| Finished | Jun 09 12:48:23 PM PDT 24 |
| Peak memory | 160468 kb |
| Host | smart-4f8943f9-1265-4f30-877e-4d06b92b610e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3324116773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3324116773 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2291822803 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1254630000 ps |
| CPU time | 4.28 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:16:41 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-6c0b0dd4-1051-446b-abc0-d2ffaff36bf1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2291822803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2291822803 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.335149285 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1337430000 ps |
| CPU time | 4.78 seconds |
| Started | Jun 09 12:16:29 PM PDT 24 |
| Finished | Jun 09 12:16:40 PM PDT 24 |
| Peak memory | 165036 kb |
| Host | smart-5f8def5f-af26-46d9-b32c-0eb35e49b5d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=335149285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.335149285 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3565325232 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1368270000 ps |
| CPU time | 4.17 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:40 PM PDT 24 |
| Peak memory | 165004 kb |
| Host | smart-2a88ca85-93bd-4dbf-8a72-d9ddb427ae77 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3565325232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3565325232 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3442187285 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1463870000 ps |
| CPU time | 4.6 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:41 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-c1a62ae1-2eb6-401d-bfeb-e430a39d2dd6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3442187285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3442187285 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2421081639 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1457650000 ps |
| CPU time | 5.1 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:16:42 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-409d8622-b58f-4bb7-b8ba-e370d98be215 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2421081639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2421081639 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2148554937 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1346210000 ps |
| CPU time | 2.9 seconds |
| Started | Jun 09 12:17:29 PM PDT 24 |
| Finished | Jun 09 12:17:36 PM PDT 24 |
| Peak memory | 164284 kb |
| Host | smart-53f1526b-b5e4-40e6-a1a1-714f08ed4f55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2148554937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2148554937 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1892151021 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1342550000 ps |
| CPU time | 4.53 seconds |
| Started | Jun 09 12:18:03 PM PDT 24 |
| Finished | Jun 09 12:18:14 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-9551d887-bcd9-4413-ad2b-0696c0d3dbcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1892151021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1892151021 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1375567842 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1564230000 ps |
| CPU time | 4.78 seconds |
| Started | Jun 09 12:17:47 PM PDT 24 |
| Finished | Jun 09 12:17:58 PM PDT 24 |
| Peak memory | 164432 kb |
| Host | smart-00aeb4d9-5fbb-415c-afb4-ee692fccc031 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1375567842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1375567842 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1364038178 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1585810000 ps |
| CPU time | 5.16 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-3ff1e6cd-d315-465e-a7c2-7e1e660b3416 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1364038178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1364038178 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2601304483 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1332250000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:41 PM PDT 24 |
| Peak memory | 165004 kb |
| Host | smart-c63f7344-1529-4da1-acc3-a6d9defb00a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2601304483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2601304483 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2289417415 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1419350000 ps |
| CPU time | 4.91 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-6c24b54a-531d-459c-9437-8a852aee5e35 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2289417415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2289417415 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1996856621 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1489530000 ps |
| CPU time | 4.88 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-b5e125a9-c2b6-416d-a61e-a6c81ee35332 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1996856621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1996856621 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1993395191 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1427770000 ps |
| CPU time | 5.15 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:16:42 PM PDT 24 |
| Peak memory | 165048 kb |
| Host | smart-442b4ded-10e5-4de2-9d09-57ae62ff8f88 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1993395191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1993395191 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3695647368 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1431070000 ps |
| CPU time | 4.52 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:41 PM PDT 24 |
| Peak memory | 165004 kb |
| Host | smart-f01ab78c-9dee-44c2-bc84-0f2f2803744b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3695647368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3695647368 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4083881618 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1511310000 ps |
| CPU time | 4.6 seconds |
| Started | Jun 09 12:17:46 PM PDT 24 |
| Finished | Jun 09 12:17:57 PM PDT 24 |
| Peak memory | 164432 kb |
| Host | smart-4c305b10-16c5-4134-8167-ec3744f6e0b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4083881618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4083881618 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.263456810 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1589450000 ps |
| CPU time | 4.94 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-bf3d4765-0075-4249-bceb-7e750caeef37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=263456810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.263456810 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2094598428 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1373010000 ps |
| CPU time | 3.31 seconds |
| Started | Jun 09 12:22:01 PM PDT 24 |
| Finished | Jun 09 12:22:08 PM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-edfc9ee2-b4f1-4c48-8aa9-fe5bb6d5acac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2094598428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2094598428 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.152383046 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1470730000 ps |
| CPU time | 5.3 seconds |
| Started | Jun 09 12:16:29 PM PDT 24 |
| Finished | Jun 09 12:16:41 PM PDT 24 |
| Peak memory | 165040 kb |
| Host | smart-d336017a-bf7d-4d28-a0b4-b053e4ba90ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=152383046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.152383046 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1892195643 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1576970000 ps |
| CPU time | 3.28 seconds |
| Started | Jun 09 12:22:12 PM PDT 24 |
| Finished | Jun 09 12:22:20 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-a0843b96-1ea1-4c0d-9bfc-515847fe63be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1892195643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1892195643 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.721597148 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1331650000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 09 12:16:53 PM PDT 24 |
| Finished | Jun 09 12:17:03 PM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-0f46e70d-6d0d-48ea-bc33-f285f70dbaf5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=721597148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.721597148 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4120753408 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1427090000 ps |
| CPU time | 4.87 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-2a7d1f87-c1e0-4ba2-91e1-b10212e481ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4120753408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.4120753408 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.271926435 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1536930000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:41 PM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-da2f35ad-1de2-4d10-8ce8-519b78ddec64 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=271926435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.271926435 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.881396350 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1519470000 ps |
| CPU time | 4.3 seconds |
| Started | Jun 09 12:17:47 PM PDT 24 |
| Finished | Jun 09 12:17:57 PM PDT 24 |
| Peak memory | 164428 kb |
| Host | smart-0b8ce405-66ee-43b7-a930-8ee28acaf985 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=881396350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.881396350 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3237873730 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1362790000 ps |
| CPU time | 4.38 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:16:42 PM PDT 24 |
| Peak memory | 165004 kb |
| Host | smart-44eac90a-55e0-4393-a9ea-8ac09a80b08f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3237873730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3237873730 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3768785835 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1313990000 ps |
| CPU time | 3.81 seconds |
| Started | Jun 09 12:17:44 PM PDT 24 |
| Finished | Jun 09 12:17:53 PM PDT 24 |
| Peak memory | 164432 kb |
| Host | smart-f4ab050a-e4dc-44d1-923b-ff9d7f1d1d39 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3768785835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3768785835 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3554415940 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1593910000 ps |
| CPU time | 4.27 seconds |
| Started | Jun 09 12:16:18 PM PDT 24 |
| Finished | Jun 09 12:16:28 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-fe9fa1a5-9553-4684-bdbc-ce297d4ca67d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3554415940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3554415940 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1604575131 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1584150000 ps |
| CPU time | 4.32 seconds |
| Started | Jun 09 12:22:01 PM PDT 24 |
| Finished | Jun 09 12:22:11 PM PDT 24 |
| Peak memory | 164668 kb |
| Host | smart-90befb3e-a5a5-489a-91bc-a37018d88b25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1604575131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1604575131 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3185552918 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1325330000 ps |
| CPU time | 2.75 seconds |
| Started | Jun 09 12:21:42 PM PDT 24 |
| Finished | Jun 09 12:21:49 PM PDT 24 |
| Peak memory | 164284 kb |
| Host | smart-0a42f7ed-e13d-4b92-9c5e-363a20ca62c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3185552918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3185552918 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2426832591 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1489770000 ps |
| CPU time | 5.4 seconds |
| Started | Jun 09 12:16:52 PM PDT 24 |
| Finished | Jun 09 12:17:04 PM PDT 24 |
| Peak memory | 164464 kb |
| Host | smart-3a3f67cf-d9a2-418e-8113-180c484dbc2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2426832591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2426832591 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4244474367 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1511470000 ps |
| CPU time | 5.39 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:16:42 PM PDT 24 |
| Peak memory | 165048 kb |
| Host | smart-896ed513-dea9-4151-89a5-1cc5b3983853 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4244474367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.4244474367 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2614162659 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1461390000 ps |
| CPU time | 2.86 seconds |
| Started | Jun 09 12:21:46 PM PDT 24 |
| Finished | Jun 09 12:21:52 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-cc468c13-30a6-4b38-8bc8-99803c7638bc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2614162659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2614162659 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3401623666 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1605870000 ps |
| CPU time | 5.12 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:16:44 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-131b9feb-499f-4c67-b868-7494b076b6c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3401623666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3401623666 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3586443063 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1490370000 ps |
| CPU time | 5.46 seconds |
| Started | Jun 09 12:17:22 PM PDT 24 |
| Finished | Jun 09 12:17:34 PM PDT 24 |
| Peak memory | 165048 kb |
| Host | smart-0f8ff462-da0a-4c08-863a-09b0f0635c7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3586443063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3586443063 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2535961538 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1559430000 ps |
| CPU time | 5.06 seconds |
| Started | Jun 09 12:16:32 PM PDT 24 |
| Finished | Jun 09 12:16:44 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-63fe7f79-717b-4bdc-8e15-570742685930 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2535961538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2535961538 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.125284123 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1460370000 ps |
| CPU time | 4.47 seconds |
| Started | Jun 09 12:16:27 PM PDT 24 |
| Finished | Jun 09 12:16:37 PM PDT 24 |
| Peak memory | 165676 kb |
| Host | smart-6760c0f3-9e14-489d-92c0-08d239744c89 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=125284123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.125284123 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2953745231 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1391130000 ps |
| CPU time | 3.92 seconds |
| Started | Jun 09 12:16:43 PM PDT 24 |
| Finished | Jun 09 12:16:52 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-22fdd117-ad28-4a0b-b54a-bbd513586371 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2953745231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2953745231 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3088635572 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1514050000 ps |
| CPU time | 4.99 seconds |
| Started | Jun 09 12:18:58 PM PDT 24 |
| Finished | Jun 09 12:19:10 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-0cae47ff-e1c5-4e53-a56a-2b31ba35e16a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3088635572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3088635572 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.41807566 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1439670000 ps |
| CPU time | 3.94 seconds |
| Started | Jun 09 12:16:30 PM PDT 24 |
| Finished | Jun 09 12:16:40 PM PDT 24 |
| Peak memory | 164240 kb |
| Host | smart-7e76415e-40ef-4cf0-8132-a19167fede24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=41807566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.41807566 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1343606425 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1217830000 ps |
| CPU time | 3.07 seconds |
| Started | Jun 09 12:22:06 PM PDT 24 |
| Finished | Jun 09 12:22:14 PM PDT 24 |
| Peak memory | 164032 kb |
| Host | smart-71c4ba72-3014-4800-9d7d-dedb733bc295 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1343606425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1343606425 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1244017445 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1556770000 ps |
| CPU time | 5.12 seconds |
| Started | Jun 09 12:21:10 PM PDT 24 |
| Finished | Jun 09 12:21:22 PM PDT 24 |
| Peak memory | 164228 kb |
| Host | smart-8efa8f29-47be-4a28-92a5-bb7c8e708bb4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1244017445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1244017445 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2940968965 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1429790000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 09 12:22:21 PM PDT 24 |
| Finished | Jun 09 12:22:31 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-3d2d23db-2944-416a-85cc-595e31dc7a77 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2940968965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2940968965 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3358607949 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1597690000 ps |
| CPU time | 4.4 seconds |
| Started | Jun 09 12:16:58 PM PDT 24 |
| Finished | Jun 09 12:17:08 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-626fad44-93fb-467a-a7a9-8c6584eda628 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3358607949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3358607949 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2710442581 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1470070000 ps |
| CPU time | 3.71 seconds |
| Started | Jun 09 12:21:32 PM PDT 24 |
| Finished | Jun 09 12:21:40 PM PDT 24 |
| Peak memory | 164432 kb |
| Host | smart-4572d0ba-1864-46f8-85f6-4c80847d8b11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2710442581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2710442581 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.86727387 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1483670000 ps |
| CPU time | 4.21 seconds |
| Started | Jun 09 12:22:28 PM PDT 24 |
| Finished | Jun 09 12:22:38 PM PDT 24 |
| Peak memory | 164464 kb |
| Host | smart-5fdd7f75-b177-4408-a2a8-2b6dc2fde791 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=86727387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.86727387 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2269244982 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1481230000 ps |
| CPU time | 4.86 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:42 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-9acb8008-cc5c-49da-b0d1-5027db1dc948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2269244982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2269244982 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.107751503 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1480710000 ps |
| CPU time | 4.38 seconds |
| Started | Jun 09 12:16:52 PM PDT 24 |
| Finished | Jun 09 12:17:02 PM PDT 24 |
| Peak memory | 164288 kb |
| Host | smart-e83981be-b263-477e-848d-73e70ffc39c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=107751503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.107751503 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3265815810 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1428330000 ps |
| CPU time | 3.9 seconds |
| Started | Jun 09 12:16:26 PM PDT 24 |
| Finished | Jun 09 12:16:35 PM PDT 24 |
| Peak memory | 164300 kb |
| Host | smart-f1e84a5c-1a87-4800-a8bd-1ab6f77395c3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3265815810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3265815810 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.231615150 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1557550000 ps |
| CPU time | 5.14 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-79d49046-6475-4383-9628-2df092ed7c2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=231615150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.231615150 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3665306385 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1149330000 ps |
| CPU time | 3.75 seconds |
| Started | Jun 09 12:16:31 PM PDT 24 |
| Finished | Jun 09 12:16:40 PM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-83627a04-95dd-48d6-9a96-2a742447b744 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3665306385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3665306385 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.575864927 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1227230000 ps |
| CPU time | 3 seconds |
| Started | Jun 09 12:22:02 PM PDT 24 |
| Finished | Jun 09 12:22:08 PM PDT 24 |
| Peak memory | 164464 kb |
| Host | smart-95b8ddaf-2c3c-45eb-948d-c021da7af701 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=575864927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.575864927 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2465623653 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1562310000 ps |
| CPU time | 5.48 seconds |
| Started | Jun 09 12:19:47 PM PDT 24 |
| Finished | Jun 09 12:19:59 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-7e5dbe30-b26a-4483-8b5f-3d5b1a84185e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2465623653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2465623653 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3439086124 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1460410000 ps |
| CPU time | 4.99 seconds |
| Started | Jun 09 12:19:12 PM PDT 24 |
| Finished | Jun 09 12:19:23 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-85eda9a1-aa77-40d4-8695-2ecb39ea8b85 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3439086124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3439086124 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.4265343246 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1534270000 ps |
| CPU time | 5.46 seconds |
| Started | Jun 09 12:21:42 PM PDT 24 |
| Finished | Jun 09 12:21:55 PM PDT 24 |
| Peak memory | 163396 kb |
| Host | smart-9915fc48-382e-4973-8b95-757e9fa748cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4265343246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.4265343246 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3364804134 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1506490000 ps |
| CPU time | 5.69 seconds |
| Started | Jun 09 12:21:42 PM PDT 24 |
| Finished | Jun 09 12:21:55 PM PDT 24 |
| Peak memory | 164144 kb |
| Host | smart-1959733f-84bf-4fa7-ba17-23c7afb6776e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3364804134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3364804134 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3476978537 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1485130000 ps |
| CPU time | 5.37 seconds |
| Started | Jun 09 12:21:42 PM PDT 24 |
| Finished | Jun 09 12:21:55 PM PDT 24 |
| Peak memory | 163676 kb |
| Host | smart-3ef6cb4c-c734-4c07-8772-ca15b3df1ae4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3476978537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3476978537 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3178735215 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1187090000 ps |
| CPU time | 4.27 seconds |
| Started | Jun 09 12:21:40 PM PDT 24 |
| Finished | Jun 09 12:21:50 PM PDT 24 |
| Peak memory | 163940 kb |
| Host | smart-b07ac027-e951-47ca-a2a6-3d6370212170 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3178735215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3178735215 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1323385548 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1367910000 ps |
| CPU time | 4.51 seconds |
| Started | Jun 09 12:21:13 PM PDT 24 |
| Finished | Jun 09 12:21:24 PM PDT 24 |
| Peak memory | 164288 kb |
| Host | smart-ac2a5311-54a0-4668-bbc4-4ae5e813e954 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1323385548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1323385548 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3727820007 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1503570000 ps |
| CPU time | 4.29 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:21:22 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-7e824c8f-c99e-4d48-bb8f-97a07a5a203c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3727820007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3727820007 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2493048039 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1587990000 ps |
| CPU time | 4.75 seconds |
| Started | Jun 09 12:21:13 PM PDT 24 |
| Finished | Jun 09 12:21:25 PM PDT 24 |
| Peak memory | 164236 kb |
| Host | smart-4e0d9735-5483-4b5d-ae35-cf8589ca0d3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2493048039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2493048039 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.784755550 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1531570000 ps |
| CPU time | 5.1 seconds |
| Started | Jun 09 12:21:09 PM PDT 24 |
| Finished | Jun 09 12:21:20 PM PDT 24 |
| Peak memory | 164520 kb |
| Host | smart-918859bb-5ae0-4523-a49d-963cf042569b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=784755550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.784755550 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2678457097 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1402310000 ps |
| CPU time | 4.89 seconds |
| Started | Jun 09 12:17:22 PM PDT 24 |
| Finished | Jun 09 12:17:34 PM PDT 24 |
| Peak memory | 164980 kb |
| Host | smart-4f802be8-51d0-4fe4-b600-86a27d6a0df0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2678457097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2678457097 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2229646316 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1585030000 ps |
| CPU time | 4.88 seconds |
| Started | Jun 09 12:21:08 PM PDT 24 |
| Finished | Jun 09 12:21:20 PM PDT 24 |
| Peak memory | 164528 kb |
| Host | smart-770928f9-4176-436c-8871-d8ff66bcadc4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2229646316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2229646316 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.6052031 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1522770000 ps |
| CPU time | 4.71 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:21:23 PM PDT 24 |
| Peak memory | 164140 kb |
| Host | smart-36c9cdc7-78f9-49c6-8d95-223a976f9c6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=6052031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.6052031 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2317993866 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1345010000 ps |
| CPU time | 3.15 seconds |
| Started | Jun 09 12:21:16 PM PDT 24 |
| Finished | Jun 09 12:21:24 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-a22587af-a3f9-46d9-a6bc-2a8a7ce2a82d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2317993866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2317993866 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3622027569 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1537070000 ps |
| CPU time | 5.13 seconds |
| Started | Jun 09 12:16:51 PM PDT 24 |
| Finished | Jun 09 12:17:03 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-a2d2b8b6-e1be-4e9a-b703-990760ac6344 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3622027569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3622027569 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1150799775 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1614530000 ps |
| CPU time | 5.09 seconds |
| Started | Jun 09 12:19:13 PM PDT 24 |
| Finished | Jun 09 12:19:25 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-5658ad63-20b1-402d-94b9-ae48d5696060 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1150799775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1150799775 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1985084351 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1557370000 ps |
| CPU time | 4.15 seconds |
| Started | Jun 09 12:16:28 PM PDT 24 |
| Finished | Jun 09 12:16:37 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-22e206c3-edfd-4e13-85d1-514031e5dbcc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1985084351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1985084351 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3764647430 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1468330000 ps |
| CPU time | 3.94 seconds |
| Started | Jun 09 12:21:19 PM PDT 24 |
| Finished | Jun 09 12:21:29 PM PDT 24 |
| Peak memory | 164592 kb |
| Host | smart-2fb32641-ce4b-4acc-91fa-dac8334e4c46 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3764647430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3764647430 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1560834068 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1493750000 ps |
| CPU time | 4.06 seconds |
| Started | Jun 09 12:21:19 PM PDT 24 |
| Finished | Jun 09 12:21:29 PM PDT 24 |
| Peak memory | 163976 kb |
| Host | smart-ba52d73e-ab1b-4f47-8242-7e19ed2206db |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1560834068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1560834068 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.618894963 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1564210000 ps |
| CPU time | 5.05 seconds |
| Started | Jun 09 12:19:13 PM PDT 24 |
| Finished | Jun 09 12:19:24 PM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-3b2cfdfa-8a71-43cf-b40b-006e0f7b0181 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=618894963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.618894963 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3501369680 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1444410000 ps |
| CPU time | 3.03 seconds |
| Started | Jun 09 12:21:26 PM PDT 24 |
| Finished | Jun 09 12:21:34 PM PDT 24 |
| Peak memory | 163652 kb |
| Host | smart-ed7b065f-0c2b-4a30-8777-888321e63e3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3501369680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3501369680 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.939322852 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1642730000 ps |
| CPU time | 4.21 seconds |
| Started | Jun 09 12:20:10 PM PDT 24 |
| Finished | Jun 09 12:20:20 PM PDT 24 |
| Peak memory | 163816 kb |
| Host | smart-4715336a-2351-4ca0-ab3e-6f39dce2d59b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=939322852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.939322852 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2285781178 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1464630000 ps |
| CPU time | 4.97 seconds |
| Started | Jun 09 12:22:31 PM PDT 24 |
| Finished | Jun 09 12:22:42 PM PDT 24 |
| Peak memory | 164408 kb |
| Host | smart-6a9b5dcf-a8ee-4301-a14f-c73c319f6f4d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2285781178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2285781178 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3473793881 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1515430000 ps |
| CPU time | 3.41 seconds |
| Started | Jun 09 12:16:35 PM PDT 24 |
| Finished | Jun 09 12:16:43 PM PDT 24 |
| Peak memory | 164304 kb |
| Host | smart-03ba66d0-7d90-4d4b-b240-f64f6f2f7b92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3473793881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3473793881 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.260557180 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1163690000 ps |
| CPU time | 3.3 seconds |
| Started | Jun 09 12:22:14 PM PDT 24 |
| Finished | Jun 09 12:22:22 PM PDT 24 |
| Peak memory | 163668 kb |
| Host | smart-f1a1d69d-cae4-405c-bc0a-e8d793af863e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=260557180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.260557180 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.143470479 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1584510000 ps |
| CPU time | 4.53 seconds |
| Started | Jun 09 12:21:15 PM PDT 24 |
| Finished | Jun 09 12:21:26 PM PDT 24 |
| Peak memory | 164408 kb |
| Host | smart-56a17ebc-729b-4815-b670-3dc2eacd7f8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=143470479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.143470479 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3394668550 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1398590000 ps |
| CPU time | 4.33 seconds |
| Started | Jun 09 12:20:05 PM PDT 24 |
| Finished | Jun 09 12:20:14 PM PDT 24 |
| Peak memory | 164704 kb |
| Host | smart-44ce9866-e36e-4a57-907f-de0d0efb4cf2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3394668550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3394668550 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.688196845 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1112050000 ps |
| CPU time | 3.56 seconds |
| Started | Jun 09 12:18:20 PM PDT 24 |
| Finished | Jun 09 12:18:28 PM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-67681339-ed44-4c64-a4b4-d427176e020b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=688196845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.688196845 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3154047957 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1459110000 ps |
| CPU time | 4.72 seconds |
| Started | Jun 09 12:22:30 PM PDT 24 |
| Finished | Jun 09 12:22:41 PM PDT 24 |
| Peak memory | 164408 kb |
| Host | smart-96ede867-a044-450b-9ef6-f75bab86f42d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3154047957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3154047957 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1136333331 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1485730000 ps |
| CPU time | 4.8 seconds |
| Started | Jun 09 12:21:08 PM PDT 24 |
| Finished | Jun 09 12:21:20 PM PDT 24 |
| Peak memory | 163764 kb |
| Host | smart-5ee4b5bc-e79e-43b7-950c-7dbe11ddaf47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1136333331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1136333331 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3748005411 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1471790000 ps |
| CPU time | 4.93 seconds |
| Started | Jun 09 12:21:10 PM PDT 24 |
| Finished | Jun 09 12:21:22 PM PDT 24 |
| Peak memory | 164228 kb |
| Host | smart-38caee9d-2c26-4af2-b517-ef69068943b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3748005411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3748005411 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1867507201 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1469390000 ps |
| CPU time | 3.21 seconds |
| Started | Jun 09 12:21:12 PM PDT 24 |
| Finished | Jun 09 12:21:20 PM PDT 24 |
| Peak memory | 163468 kb |
| Host | smart-14ba20f6-9038-4acd-876c-d1b288c80f0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1867507201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1867507201 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3681963152 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1469490000 ps |
| CPU time | 5.44 seconds |
| Started | Jun 09 12:17:22 PM PDT 24 |
| Finished | Jun 09 12:17:34 PM PDT 24 |
| Peak memory | 164980 kb |
| Host | smart-728d117e-6f8c-4045-b80b-f8b393849d95 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3681963152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3681963152 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1066892165 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1526830000 ps |
| CPU time | 4.9 seconds |
| Started | Jun 09 12:19:41 PM PDT 24 |
| Finished | Jun 09 12:19:52 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-dbe79056-675f-44f0-b8ac-6df0f7a989f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1066892165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1066892165 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3417448253 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1425950000 ps |
| CPU time | 4.77 seconds |
| Started | Jun 09 12:18:59 PM PDT 24 |
| Finished | Jun 09 12:19:10 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-3a82aeb6-129f-42b7-8ac4-7643f23d4273 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3417448253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3417448253 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3202858758 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1508930000 ps |
| CPU time | 4.85 seconds |
| Started | Jun 09 12:22:32 PM PDT 24 |
| Finished | Jun 09 12:22:43 PM PDT 24 |
| Peak memory | 164408 kb |
| Host | smart-fa196d22-e2ed-4a3a-b152-ee7733d8ce27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3202858758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3202858758 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.4116796424 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1538430000 ps |
| CPU time | 3.6 seconds |
| Started | Jun 09 12:17:34 PM PDT 24 |
| Finished | Jun 09 12:17:42 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-36c2dd26-9907-4b14-b151-096a1fbac66e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4116796424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.4116796424 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2289530855 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1363950000 ps |
| CPU time | 4.19 seconds |
| Started | Jun 09 12:17:27 PM PDT 24 |
| Finished | Jun 09 12:17:36 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-bfb4f1ac-d9d0-40a0-a12b-7e1773ad4883 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2289530855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2289530855 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1692916496 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1325470000 ps |
| CPU time | 3.9 seconds |
| Started | Jun 09 12:18:40 PM PDT 24 |
| Finished | Jun 09 12:18:49 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-a1a1d79c-907f-42d4-851d-0ef9ee0c662d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1692916496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1692916496 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.771302428 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1431170000 ps |
| CPU time | 4.31 seconds |
| Started | Jun 09 12:20:05 PM PDT 24 |
| Finished | Jun 09 12:20:15 PM PDT 24 |
| Peak memory | 164696 kb |
| Host | smart-9862cbf6-ece1-4928-ab91-88046d04ee11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=771302428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.771302428 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2604076401 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1608890000 ps |
| CPU time | 4.27 seconds |
| Started | Jun 09 12:16:38 PM PDT 24 |
| Finished | Jun 09 12:16:47 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-23446c1c-409d-42b0-908d-fb67a6b7dfa2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2604076401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2604076401 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2327964237 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1538590000 ps |
| CPU time | 4.23 seconds |
| Started | Jun 09 12:22:14 PM PDT 24 |
| Finished | Jun 09 12:22:24 PM PDT 24 |
| Peak memory | 162936 kb |
| Host | smart-d24c5ea0-0105-4c20-8063-1fa407479bae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2327964237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2327964237 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2480835281 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1350670000 ps |
| CPU time | 2.79 seconds |
| Started | Jun 09 12:21:14 PM PDT 24 |
| Finished | Jun 09 12:21:21 PM PDT 24 |
| Peak memory | 164284 kb |
| Host | smart-511bb6e6-1bc9-4370-aae3-a90423b0cc7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2480835281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2480835281 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.734066863 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1572310000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 09 12:20:10 PM PDT 24 |
| Finished | Jun 09 12:20:20 PM PDT 24 |
| Peak memory | 163560 kb |
| Host | smart-f97f2937-0547-4be3-8da3-84be5125c5ee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=734066863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.734066863 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3571072849 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1261050000 ps |
| CPU time | 4.94 seconds |
| Started | Jun 09 12:21:42 PM PDT 24 |
| Finished | Jun 09 12:21:54 PM PDT 24 |
| Peak memory | 163284 kb |
| Host | smart-cfa9aee0-9e87-48a7-8226-465a8ce4b6d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3571072849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3571072849 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1350900411 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1220370000 ps |
| CPU time | 4.77 seconds |
| Started | Jun 09 12:21:42 PM PDT 24 |
| Finished | Jun 09 12:21:54 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-a8528eb8-a5e7-4a90-a918-fdfd7076257c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1350900411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1350900411 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1159591954 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1496310000 ps |
| CPU time | 3.95 seconds |
| Started | Jun 09 12:16:55 PM PDT 24 |
| Finished | Jun 09 12:17:05 PM PDT 24 |
| Peak memory | 164468 kb |
| Host | smart-23eedbb9-0805-4966-a636-1fe3673fa480 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1159591954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1159591954 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.679580 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1534610000 ps |
| CPU time | 4.12 seconds |
| Started | Jun 09 12:21:09 PM PDT 24 |
| Finished | Jun 09 12:21:18 PM PDT 24 |
| Peak memory | 164544 kb |
| Host | smart-92797ae6-3532-49ea-bea9-4f2657795095 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=679580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.679580 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |