Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3341022863
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3546901263
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4065650599

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2814836395
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2841145531
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2946641022
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1479765137
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3367751316
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3287258392
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4077478971
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2851031467
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2190316770
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1847977837
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3894007976
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2394468819
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2701836570
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.172796099
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3223947228
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.817850606
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4068372530
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.651814490
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3245128642
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2287611085
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1094447815
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2009916685
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2653005937
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2329945638
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2835104601
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1571417791
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3934095416
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1775208308
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2070956892
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3428463660
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4032974562
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3439803200
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1132955735
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2915823498
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4274918307
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.309589204
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3194442920
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3716255957
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3361535086
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2892068353
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2949467617
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1951341746
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1529894778
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1941558124
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1579514031
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4045624970
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.869007995
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2855846781
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2122632213
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.820037511
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3978119150
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2479134972
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.765714895
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2138058584
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.869097431
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.399089816
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2408313280
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2568533086
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1027362136
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1007905195
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.29114842
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2416787635
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.581647496
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.702400178
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.602974443
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3384379465
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2021692448
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4056759768
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.90966714
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1428553854
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3763553907
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3996901509
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.860926321
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.761889514
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3483399708
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1006479191
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.505542880
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1494432961
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3477532455
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3917503738
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2185432865
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1589796426
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1063722179
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1928600736
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1247738400
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2713322852
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.832894298
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4270511502
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3840898090
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.37547691
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2754326101
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.395279088
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2180385870
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.290792473
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3806482643
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2185736901
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3328251643
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2613297699
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1200613630
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1518784967
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.120719283
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.313421132
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1371343274
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2548688997
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3060294405
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.252573730
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2555962781
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3490187198
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.197873095
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3284755705
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.656319318
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1440444801
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3699289882
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3822120740
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2157257424
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3124136135
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.462075339
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.124458163
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.592774273
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1157699534
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1684788654
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2821504201
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3660305447
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2012688632
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.539682367
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2417153837
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1801644480
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.834440650
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.816147336
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.507413493
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2547026695
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1956996036
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2896020458
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.584749968
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3631453526
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3585996198
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4171612295
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1341446629
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2766944873
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2971730967
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1776842386
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1369213354
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1073969361
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2517531612
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.552828166
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2343097540
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2904351389
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.988144747
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1803908423
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1493688427
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2753047499
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2911270344
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2937990404
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3202206487
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1637790219
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3116863494
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1414147659
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1463830856
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1508814298
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3838010864
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1122367509
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4248164175
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2379039607
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1657682237
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3361704505
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1534780523
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2239305295
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2202892832
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.461873758
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.406470668
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2129726048
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3870559833
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.309288013
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1929167961
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2250027494
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.454476665
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.777826176
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.562569420
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4193398644
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.145330702
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1362678935
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.289393874
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1526969301
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2814987287
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4112306512
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2606753793
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.200690518
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3125774041
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.58555450
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3589987099
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3475791447
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3322255536
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3551389083
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3085863064
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4045998192
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3929533788
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3206285939



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2250027494 Jun 10 04:55:10 PM PDT 24 Jun 10 04:55:20 PM PDT 24 1585290000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3116863494 Jun 10 04:55:12 PM PDT 24 Jun 10 04:55:21 PM PDT 24 1535490000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.562569420 Jun 10 04:55:35 PM PDT 24 Jun 10 04:55:41 PM PDT 24 1148270000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2129726048 Jun 10 04:55:19 PM PDT 24 Jun 10 04:55:25 PM PDT 24 1418530000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3475791447 Jun 10 04:55:17 PM PDT 24 Jun 10 04:55:25 PM PDT 24 1534610000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.145330702 Jun 10 04:55:10 PM PDT 24 Jun 10 04:55:19 PM PDT 24 1404490000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2239305295 Jun 10 04:55:15 PM PDT 24 Jun 10 04:55:25 PM PDT 24 1576430000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3125774041 Jun 10 04:55:01 PM PDT 24 Jun 10 04:55:10 PM PDT 24 1486510000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3341022863 Jun 10 04:55:06 PM PDT 24 Jun 10 04:55:13 PM PDT 24 1400990000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1414147659 Jun 10 04:55:01 PM PDT 24 Jun 10 04:55:09 PM PDT 24 1490450000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1929167961 Jun 10 04:55:14 PM PDT 24 Jun 10 04:55:23 PM PDT 24 1586910000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3361704505 Jun 10 04:55:41 PM PDT 24 Jun 10 04:55:48 PM PDT 24 1505310000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3551389083 Jun 10 04:55:04 PM PDT 24 Jun 10 04:55:16 PM PDT 24 1615930000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1362678935 Jun 10 04:55:16 PM PDT 24 Jun 10 04:55:30 PM PDT 24 1435370000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1493688427 Jun 10 04:55:20 PM PDT 24 Jun 10 04:55:28 PM PDT 24 1340590000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.406470668 Jun 10 04:55:41 PM PDT 24 Jun 10 04:55:48 PM PDT 24 1490870000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4193398644 Jun 10 04:55:10 PM PDT 24 Jun 10 04:55:19 PM PDT 24 1418430000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3838010864 Jun 10 04:55:38 PM PDT 24 Jun 10 04:55:49 PM PDT 24 1311210000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3202206487 Jun 10 04:55:47 PM PDT 24 Jun 10 04:55:54 PM PDT 24 1531630000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.289393874 Jun 10 04:55:10 PM PDT 24 Jun 10 04:55:18 PM PDT 24 1424370000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2937990404 Jun 10 04:55:07 PM PDT 24 Jun 10 04:55:15 PM PDT 24 1451250000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2814987287 Jun 10 04:55:10 PM PDT 24 Jun 10 04:55:24 PM PDT 24 1501550000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.58555450 Jun 10 04:55:23 PM PDT 24 Jun 10 04:55:30 PM PDT 24 1390690000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.200690518 Jun 10 04:55:27 PM PDT 24 Jun 10 04:55:35 PM PDT 24 1373570000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2911270344 Jun 10 04:55:01 PM PDT 24 Jun 10 04:55:11 PM PDT 24 1468290000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3870559833 Jun 10 04:55:37 PM PDT 24 Jun 10 04:55:44 PM PDT 24 1415630000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2379039607 Jun 10 04:55:11 PM PDT 24 Jun 10 04:55:20 PM PDT 24 1377270000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.777826176 Jun 10 04:55:16 PM PDT 24 Jun 10 04:55:24 PM PDT 24 1429090000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2202892832 Jun 10 04:55:05 PM PDT 24 Jun 10 04:55:16 PM PDT 24 1533550000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4112306512 Jun 10 04:55:28 PM PDT 24 Jun 10 04:55:38 PM PDT 24 1591810000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3322255536 Jun 10 04:55:20 PM PDT 24 Jun 10 04:55:28 PM PDT 24 1376310000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1637790219 Jun 10 04:55:00 PM PDT 24 Jun 10 04:55:09 PM PDT 24 1537750000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.454476665 Jun 10 04:55:43 PM PDT 24 Jun 10 04:55:51 PM PDT 24 1528250000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3085863064 Jun 10 04:55:05 PM PDT 24 Jun 10 04:55:14 PM PDT 24 1444750000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2753047499 Jun 10 04:55:11 PM PDT 24 Jun 10 04:55:18 PM PDT 24 1230970000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3589987099 Jun 10 04:55:24 PM PDT 24 Jun 10 04:55:32 PM PDT 24 1240010000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1463830856 Jun 10 04:55:22 PM PDT 24 Jun 10 04:55:28 PM PDT 24 1218030000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1657682237 Jun 10 04:55:08 PM PDT 24 Jun 10 04:55:15 PM PDT 24 1352310000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2606753793 Jun 10 04:55:26 PM PDT 24 Jun 10 04:55:34 PM PDT 24 1510630000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1122367509 Jun 10 04:55:30 PM PDT 24 Jun 10 04:55:39 PM PDT 24 1525990000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.461873758 Jun 10 04:55:08 PM PDT 24 Jun 10 04:55:16 PM PDT 24 1433230000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3206285939 Jun 10 04:55:24 PM PDT 24 Jun 10 04:55:32 PM PDT 24 1432430000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3929533788 Jun 10 04:55:02 PM PDT 24 Jun 10 04:55:09 PM PDT 24 1395590000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1803908423 Jun 10 04:55:26 PM PDT 24 Jun 10 04:55:33 PM PDT 24 1198950000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1508814298 Jun 10 04:55:31 PM PDT 24 Jun 10 04:55:38 PM PDT 24 1536370000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.309288013 Jun 10 04:55:26 PM PDT 24 Jun 10 04:55:33 PM PDT 24 1466650000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1534780523 Jun 10 04:55:18 PM PDT 24 Jun 10 04:55:26 PM PDT 24 1389690000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1526969301 Jun 10 04:55:22 PM PDT 24 Jun 10 04:55:29 PM PDT 24 1448210000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4045998192 Jun 10 04:55:07 PM PDT 24 Jun 10 04:55:14 PM PDT 24 1338010000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4248164175 Jun 10 04:55:36 PM PDT 24 Jun 10 04:55:43 PM PDT 24 1457030000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3223947228 Jun 10 04:55:53 PM PDT 24 Jun 10 05:31:17 PM PDT 24 336372490000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2070956892 Jun 10 04:55:35 PM PDT 24 Jun 10 05:27:20 PM PDT 24 336899710000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1529894778 Jun 10 04:55:30 PM PDT 24 Jun 10 05:23:09 PM PDT 24 336890310000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3894007976 Jun 10 04:55:31 PM PDT 24 Jun 10 05:35:56 PM PDT 24 337070190000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1094447815 Jun 10 04:56:01 PM PDT 24 Jun 10 05:21:37 PM PDT 24 336729550000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4274918307 Jun 10 04:56:17 PM PDT 24 Jun 10 05:34:10 PM PDT 24 336667870000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2009916685 Jun 10 04:55:48 PM PDT 24 Jun 10 05:26:18 PM PDT 24 336342710000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2701836570 Jun 10 04:55:31 PM PDT 24 Jun 10 05:34:57 PM PDT 24 336693410000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1951341746 Jun 10 04:55:59 PM PDT 24 Jun 10 05:22:03 PM PDT 24 336403590000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3546901263 Jun 10 04:55:32 PM PDT 24 Jun 10 05:33:16 PM PDT 24 336699490000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2329945638 Jun 10 04:56:01 PM PDT 24 Jun 10 05:28:58 PM PDT 24 337031690000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2653005937 Jun 10 04:55:31 PM PDT 24 Jun 10 05:34:39 PM PDT 24 336761930000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3361535086 Jun 10 04:56:15 PM PDT 24 Jun 10 05:31:14 PM PDT 24 336644330000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2122632213 Jun 10 04:55:31 PM PDT 24 Jun 10 05:35:52 PM PDT 24 336743510000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.309589204 Jun 10 04:56:00 PM PDT 24 Jun 10 05:23:10 PM PDT 24 336628790000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3367751316 Jun 10 04:55:32 PM PDT 24 Jun 10 05:35:00 PM PDT 24 336877050000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1132955735 Jun 10 04:55:29 PM PDT 24 Jun 10 05:24:15 PM PDT 24 336757270000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3245128642 Jun 10 04:55:35 PM PDT 24 Jun 10 05:26:45 PM PDT 24 336326190000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4032974562 Jun 10 04:56:15 PM PDT 24 Jun 10 05:29:24 PM PDT 24 337015410000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2851031467 Jun 10 04:55:49 PM PDT 24 Jun 10 05:24:44 PM PDT 24 337009050000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3287258392 Jun 10 04:55:52 PM PDT 24 Jun 10 05:34:47 PM PDT 24 336647830000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2190316770 Jun 10 04:55:30 PM PDT 24 Jun 10 05:33:38 PM PDT 24 336624750000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1479765137 Jun 10 04:55:28 PM PDT 24 Jun 10 05:25:56 PM PDT 24 337020670000 ps
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T85 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2892068353 Jun 10 04:56:00 PM PDT 24 Jun 10 05:30:17 PM PDT 24 336408410000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2394468819 Jun 10 04:55:54 PM PDT 24 Jun 10 05:31:32 PM PDT 24 336990650000 ps
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T88 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4045624970 Jun 10 04:55:43 PM PDT 24 Jun 10 05:31:08 PM PDT 24 336516910000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1571417791 Jun 10 04:56:00 PM PDT 24 Jun 10 05:34:12 PM PDT 24 336668510000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2841145531 Jun 10 04:55:31 PM PDT 24 Jun 10 05:34:41 PM PDT 24 336765090000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2855846781 Jun 10 04:55:29 PM PDT 24 Jun 10 05:33:11 PM PDT 24 336484830000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.172796099 Jun 10 04:55:56 PM PDT 24 Jun 10 05:29:45 PM PDT 24 336736530000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.651814490 Jun 10 04:55:30 PM PDT 24 Jun 10 05:34:25 PM PDT 24 336369070000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1579514031 Jun 10 04:55:47 PM PDT 24 Jun 10 05:31:20 PM PDT 24 336854230000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1847977837 Jun 10 04:55:45 PM PDT 24 Jun 10 05:31:47 PM PDT 24 336445770000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.817850606 Jun 10 04:55:32 PM PDT 24 Jun 10 05:30:37 PM PDT 24 337031910000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2946641022 Jun 10 04:55:56 PM PDT 24 Jun 10 05:29:00 PM PDT 24 336364410000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1941558124 Jun 10 04:55:36 PM PDT 24 Jun 10 05:33:29 PM PDT 24 336712650000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3716255957 Jun 10 04:55:47 PM PDT 24 Jun 10 05:29:46 PM PDT 24 336540870000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3428463660 Jun 10 04:56:05 PM PDT 24 Jun 10 05:28:32 PM PDT 24 336833790000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1775208308 Jun 10 04:55:36 PM PDT 24 Jun 10 05:24:19 PM PDT 24 336399090000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4077478971 Jun 10 04:55:32 PM PDT 24 Jun 10 05:34:28 PM PDT 24 336633750000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3439803200 Jun 10 04:55:39 PM PDT 24 Jun 10 05:27:14 PM PDT 24 337101770000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2915823498 Jun 10 04:55:49 PM PDT 24 Jun 10 05:31:43 PM PDT 24 336665570000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3194442920 Jun 10 04:55:52 PM PDT 24 Jun 10 05:29:04 PM PDT 24 336623350000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4068372530 Jun 10 04:55:59 PM PDT 24 Jun 10 05:30:05 PM PDT 24 336372710000 ps
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T108 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2835104601 Jun 10 04:55:59 PM PDT 24 Jun 10 05:26:45 PM PDT 24 336647790000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2949467617 Jun 10 04:55:31 PM PDT 24 Jun 10 05:29:30 PM PDT 24 337011490000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2287611085 Jun 10 04:55:54 PM PDT 24 Jun 10 05:31:44 PM PDT 24 336388310000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2896020458 Jun 10 04:56:38 PM PDT 24 Jun 10 04:56:46 PM PDT 24 1560430000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3822120740 Jun 10 04:56:52 PM PDT 24 Jun 10 04:57:02 PM PDT 24 1518930000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1073969361 Jun 10 04:57:09 PM PDT 24 Jun 10 04:57:21 PM PDT 24 1507670000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1200613630 Jun 10 04:56:49 PM PDT 24 Jun 10 04:56:57 PM PDT 24 1553810000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1776842386 Jun 10 04:56:57 PM PDT 24 Jun 10 04:57:08 PM PDT 24 1513870000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.592774273 Jun 10 04:56:49 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1481910000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2548688997 Jun 10 04:56:35 PM PDT 24 Jun 10 04:56:44 PM PDT 24 1284890000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2766944873 Jun 10 04:57:00 PM PDT 24 Jun 10 04:57:14 PM PDT 24 1524410000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.834440650 Jun 10 04:56:55 PM PDT 24 Jun 10 04:57:05 PM PDT 24 1417250000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1801644480 Jun 10 04:56:53 PM PDT 24 Jun 10 04:57:03 PM PDT 24 1460830000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.124458163 Jun 10 04:56:48 PM PDT 24 Jun 10 04:56:55 PM PDT 24 1327930000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.816147336 Jun 10 04:57:00 PM PDT 24 Jun 10 04:57:10 PM PDT 24 1493110000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.552828166 Jun 10 04:56:45 PM PDT 24 Jun 10 04:56:56 PM PDT 24 1383070000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.584749968 Jun 10 04:56:57 PM PDT 24 Jun 10 04:57:07 PM PDT 24 1529510000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.507413493 Jun 10 04:56:51 PM PDT 24 Jun 10 04:57:01 PM PDT 24 1652470000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.656319318 Jun 10 04:56:43 PM PDT 24 Jun 10 04:56:51 PM PDT 24 1479850000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1371343274 Jun 10 04:56:54 PM PDT 24 Jun 10 04:57:04 PM PDT 24 1632790000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1157699534 Jun 10 04:57:00 PM PDT 24 Jun 10 04:57:10 PM PDT 24 1312230000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3490187198 Jun 10 04:56:43 PM PDT 24 Jun 10 04:56:54 PM PDT 24 1567550000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1341446629 Jun 10 04:56:56 PM PDT 24 Jun 10 04:57:06 PM PDT 24 1505690000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3060294405 Jun 10 04:56:50 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1525670000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4171612295 Jun 10 04:56:56 PM PDT 24 Jun 10 04:57:04 PM PDT 24 1413950000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.313421132 Jun 10 04:56:42 PM PDT 24 Jun 10 04:56:52 PM PDT 24 1542690000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2821504201 Jun 10 04:56:37 PM PDT 24 Jun 10 04:56:45 PM PDT 24 1449130000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2343097540 Jun 10 04:57:06 PM PDT 24 Jun 10 04:57:13 PM PDT 24 1169330000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.197873095 Jun 10 04:56:48 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1564770000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2157257424 Jun 10 04:56:51 PM PDT 24 Jun 10 04:57:00 PM PDT 24 1514950000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.120719283 Jun 10 04:56:50 PM PDT 24 Jun 10 04:56:58 PM PDT 24 1513130000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3631453526 Jun 10 04:56:54 PM PDT 24 Jun 10 04:57:04 PM PDT 24 1484510000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3284755705 Jun 10 04:56:43 PM PDT 24 Jun 10 04:56:53 PM PDT 24 1505550000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2904351389 Jun 10 04:56:35 PM PDT 24 Jun 10 04:56:45 PM PDT 24 1430510000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3660305447 Jun 10 04:57:05 PM PDT 24 Jun 10 04:57:12 PM PDT 24 1288950000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.988144747 Jun 10 04:56:54 PM PDT 24 Jun 10 04:57:00 PM PDT 24 1173010000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1956996036 Jun 10 04:56:57 PM PDT 24 Jun 10 04:57:07 PM PDT 24 1527630000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1440444801 Jun 10 04:56:48 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1511930000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2555962781 Jun 10 04:56:46 PM PDT 24 Jun 10 04:56:55 PM PDT 24 1187910000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2417153837 Jun 10 04:57:07 PM PDT 24 Jun 10 04:57:14 PM PDT 24 1506250000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2971730967 Jun 10 04:56:48 PM PDT 24 Jun 10 04:57:00 PM PDT 24 1503810000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3585996198 Jun 10 04:56:40 PM PDT 24 Jun 10 04:56:48 PM PDT 24 1344170000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2012688632 Jun 10 04:56:53 PM PDT 24 Jun 10 04:57:04 PM PDT 24 1557590000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.539682367 Jun 10 04:56:57 PM PDT 24 Jun 10 04:57:09 PM PDT 24 1564690000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1518784967 Jun 10 04:56:27 PM PDT 24 Jun 10 04:56:36 PM PDT 24 1317910000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2547026695 Jun 10 04:56:49 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1388510000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2517531612 Jun 10 04:56:49 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1495430000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.462075339 Jun 10 04:56:51 PM PDT 24 Jun 10 04:57:01 PM PDT 24 1517770000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3699289882 Jun 10 04:56:45 PM PDT 24 Jun 10 04:56:59 PM PDT 24 1536270000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.252573730 Jun 10 04:56:54 PM PDT 24 Jun 10 04:57:03 PM PDT 24 1286410000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3124136135 Jun 10 04:57:04 PM PDT 24 Jun 10 04:57:14 PM PDT 24 1514610000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1369213354 Jun 10 04:57:06 PM PDT 24 Jun 10 04:57:14 PM PDT 24 1365030000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1684788654 Jun 10 04:57:02 PM PDT 24 Jun 10 04:57:11 PM PDT 24 1443650000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3996901509 Jun 10 04:57:15 PM PDT 24 Jun 10 05:31:19 PM PDT 24 336597730000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.90966714 Jun 10 04:57:17 PM PDT 24 Jun 10 05:31:39 PM PDT 24 337089970000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.832894298 Jun 10 04:57:18 PM PDT 24 Jun 10 05:28:20 PM PDT 24 336987270000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4270511502 Jun 10 04:57:22 PM PDT 24 Jun 10 05:31:15 PM PDT 24 336552310000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3483399708 Jun 10 04:57:25 PM PDT 24 Jun 10 05:31:14 PM PDT 24 336669810000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1428553854 Jun 10 04:57:14 PM PDT 24 Jun 10 05:30:36 PM PDT 24 336917790000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2479134972 Jun 10 04:57:09 PM PDT 24 Jun 10 05:27:18 PM PDT 24 336787910000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.765714895 Jun 10 04:57:09 PM PDT 24 Jun 10 05:31:33 PM PDT 24 337102910000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4065650599 Jun 10 04:57:19 PM PDT 24 Jun 10 05:35:59 PM PDT 24 336347570000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2613297699 Jun 10 04:57:17 PM PDT 24 Jun 10 05:29:24 PM PDT 24 336627690000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2185432865 Jun 10 04:57:20 PM PDT 24 Jun 10 05:29:17 PM PDT 24 336546610000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.290792473 Jun 10 04:57:16 PM PDT 24 Jun 10 05:28:08 PM PDT 24 337031290000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2568533086 Jun 10 04:57:26 PM PDT 24 Jun 10 05:32:39 PM PDT 24 336996830000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1007905195 Jun 10 04:57:34 PM PDT 24 Jun 10 05:27:12 PM PDT 24 336622130000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2754326101 Jun 10 04:57:19 PM PDT 24 Jun 10 05:26:16 PM PDT 24 336743050000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3477532455 Jun 10 04:57:23 PM PDT 24 Jun 10 05:28:40 PM PDT 24 336509030000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.399089816 Jun 10 04:57:09 PM PDT 24 Jun 10 05:35:34 PM PDT 24 336320470000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.869097431 Jun 10 04:57:11 PM PDT 24 Jun 10 05:25:43 PM PDT 24 336349390000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2408313280 Jun 10 04:57:16 PM PDT 24 Jun 10 05:32:52 PM PDT 24 336400570000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.602974443 Jun 10 04:57:21 PM PDT 24 Jun 10 05:29:33 PM PDT 24 337147490000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.702400178 Jun 10 04:57:26 PM PDT 24 Jun 10 05:29:55 PM PDT 24 336817790000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.761889514 Jun 10 04:57:15 PM PDT 24 Jun 10 05:30:38 PM PDT 24 336374930000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.860926321 Jun 10 04:57:33 PM PDT 24 Jun 10 05:28:09 PM PDT 24 336931870000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4056759768 Jun 10 04:57:30 PM PDT 24 Jun 10 05:28:01 PM PDT 24 336847370000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1928600736 Jun 10 04:57:36 PM PDT 24 Jun 10 05:36:13 PM PDT 24 336308110000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.37547691 Jun 10 04:57:35 PM PDT 24 Jun 10 05:27:36 PM PDT 24 337062790000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1027362136 Jun 10 04:57:22 PM PDT 24 Jun 10 05:31:56 PM PDT 24 337104630000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.29114842 Jun 10 04:57:16 PM PDT 24 Jun 10 05:29:53 PM PDT 24 336839990000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.395279088 Jun 10 04:57:39 PM PDT 24 Jun 10 05:28:44 PM PDT 24 336622610000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2416787635 Jun 10 04:57:45 PM PDT 24 Jun 10 05:31:52 PM PDT 24 336959390000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1063722179 Jun 10 04:57:29 PM PDT 24 Jun 10 05:25:31 PM PDT 24 336489750000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3917503738 Jun 10 04:57:16 PM PDT 24 Jun 10 05:33:49 PM PDT 24 336766150000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1247738400 Jun 10 04:57:27 PM PDT 24 Jun 10 05:29:30 PM PDT 24 336801950000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3328251643 Jun 10 04:57:32 PM PDT 24 Jun 10 05:32:39 PM PDT 24 336426210000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2713322852 Jun 10 04:57:39 PM PDT 24 Jun 10 05:28:29 PM PDT 24 336882450000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.581647496 Jun 10 04:57:20 PM PDT 24 Jun 10 05:27:19 PM PDT 24 336417950000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2185736901 Jun 10 04:57:14 PM PDT 24 Jun 10 05:28:26 PM PDT 24 336713190000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3763553907 Jun 10 04:57:17 PM PDT 24 Jun 10 05:27:35 PM PDT 24 336929670000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.820037511 Jun 10 04:57:24 PM PDT 24 Jun 10 05:27:59 PM PDT 24 336909050000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3806482643 Jun 10 04:57:15 PM PDT 24 Jun 10 05:35:56 PM PDT 24 336985030000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3384379465 Jun 10 04:57:26 PM PDT 24 Jun 10 05:32:17 PM PDT 24 336519730000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.505542880 Jun 10 04:57:18 PM PDT 24 Jun 10 05:30:39 PM PDT 24 336587490000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3978119150 Jun 10 04:57:36 PM PDT 24 Jun 10 05:29:49 PM PDT 24 336650250000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3840898090 Jun 10 04:57:20 PM PDT 24 Jun 10 05:34:17 PM PDT 24 336931490000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1494432961 Jun 10 04:57:17 PM PDT 24 Jun 10 05:29:11 PM PDT 24 336466770000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2138058584 Jun 10 04:57:26 PM PDT 24 Jun 10 05:29:33 PM PDT 24 336526250000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1006479191 Jun 10 04:57:25 PM PDT 24 Jun 10 05:26:01 PM PDT 24 336732290000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2180385870 Jun 10 04:57:18 PM PDT 24 Jun 10 05:30:53 PM PDT 24 336994850000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2021692448 Jun 10 04:57:17 PM PDT 24 Jun 10 05:32:41 PM PDT 24 336757310000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1589796426 Jun 10 04:57:33 PM PDT 24 Jun 10 05:32:11 PM PDT 24 336498910000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3341022863
Short name T12
Test name
Test status
Simulation time 1400990000 ps
CPU time 3.15 seconds
Started Jun 10 04:55:06 PM PDT 24
Finished Jun 10 04:55:13 PM PDT 24
Peak memory 164780 kb
Host smart-1daac153-2c66-48d8-9f38-93dd912a60f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3341022863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3341022863
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3546901263
Short name T20
Test name
Test status
Simulation time 336699490000 ps
CPU time 911.49 seconds
Started Jun 10 04:55:32 PM PDT 24
Finished Jun 10 05:33:16 PM PDT 24
Peak memory 160708 kb
Host smart-f1899696-84be-4b9e-bda9-86405a6ade26
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3546901263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3546901263
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.4065650599
Short name T29
Test name
Test status
Simulation time 336347570000 ps
CPU time 928 seconds
Started Jun 10 04:57:19 PM PDT 24
Finished Jun 10 05:35:59 PM PDT 24
Peak memory 160660 kb
Host smart-b3b1cdb8-a177-4fc2-86c7-a241d9470401
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4065650599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.4065650599
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2814836395
Short name T87
Test name
Test status
Simulation time 336994610000 ps
CPU time 762.86 seconds
Started Jun 10 04:55:56 PM PDT 24
Finished Jun 10 05:26:53 PM PDT 24
Peak memory 160720 kb
Host smart-12712519-c5d1-4a31-9ba0-eecbce4cb183
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2814836395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2814836395
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2841145531
Short name T90
Test name
Test status
Simulation time 336765090000 ps
CPU time 957.4 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 05:34:41 PM PDT 24
Peak memory 159916 kb
Host smart-342dc579-2bde-4dc5-b7a9-7a01bda1e162
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2841145531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2841145531
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2946641022
Short name T97
Test name
Test status
Simulation time 336364410000 ps
CPU time 814.61 seconds
Started Jun 10 04:55:56 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 160700 kb
Host smart-93d71e1d-6f37-4b73-a74e-ad74d5c6b786
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2946641022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2946641022
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1479765137
Short name T83
Test name
Test status
Simulation time 337020670000 ps
CPU time 753.18 seconds
Started Jun 10 04:55:28 PM PDT 24
Finished Jun 10 05:25:56 PM PDT 24
Peak memory 160676 kb
Host smart-45aa62c4-4267-4454-8b00-4624e24a939d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1479765137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1479765137
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3367751316
Short name T76
Test name
Test status
Simulation time 336877050000 ps
CPU time 969.17 seconds
Started Jun 10 04:55:32 PM PDT 24
Finished Jun 10 05:35:00 PM PDT 24
Peak memory 160708 kb
Host smart-e8ce6210-0275-48c5-b720-ab19eaea6756
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3367751316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3367751316
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3287258392
Short name T81
Test name
Test status
Simulation time 336647830000 ps
CPU time 936.43 seconds
Started Jun 10 04:55:52 PM PDT 24
Finished Jun 10 05:34:47 PM PDT 24
Peak memory 160708 kb
Host smart-22950528-f338-4e01-bc11-509db0354f49
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3287258392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3287258392
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4077478971
Short name T102
Test name
Test status
Simulation time 336633750000 ps
CPU time 947.39 seconds
Started Jun 10 04:55:32 PM PDT 24
Finished Jun 10 05:34:28 PM PDT 24
Peak memory 160708 kb
Host smart-72a33daf-6b1c-403f-a933-81d436f153ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4077478971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.4077478971
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2851031467
Short name T80
Test name
Test status
Simulation time 337009050000 ps
CPU time 712.08 seconds
Started Jun 10 04:55:49 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 160644 kb
Host smart-4cf43b70-72f4-4b6a-905b-bc740d46f389
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2851031467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2851031467
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2190316770
Short name T82
Test name
Test status
Simulation time 336624750000 ps
CPU time 906.22 seconds
Started Jun 10 04:55:30 PM PDT 24
Finished Jun 10 05:33:38 PM PDT 24
Peak memory 160280 kb
Host smart-d0f393f1-61e5-40c8-be69-51c15e545d9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2190316770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2190316770
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1847977837
Short name T95
Test name
Test status
Simulation time 336445770000 ps
CPU time 862.28 seconds
Started Jun 10 04:55:45 PM PDT 24
Finished Jun 10 05:31:47 PM PDT 24
Peak memory 160756 kb
Host smart-e17dc9da-3c4b-47d5-bece-7f817334a009
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1847977837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1847977837
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3894007976
Short name T14
Test name
Test status
Simulation time 337070190000 ps
CPU time 1006.57 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 160268 kb
Host smart-46bd243e-ae9a-41b3-b369-b2dbf3043a63
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3894007976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3894007976
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2394468819
Short name T86
Test name
Test status
Simulation time 336990650000 ps
CPU time 861.26 seconds
Started Jun 10 04:55:54 PM PDT 24
Finished Jun 10 05:31:32 PM PDT 24
Peak memory 160664 kb
Host smart-13ebbd17-8f1d-4595-bb57-c26e0c4d5f23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2394468819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2394468819
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2701836570
Short name T18
Test name
Test status
Simulation time 336693410000 ps
CPU time 963.4 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 05:34:57 PM PDT 24
Peak memory 160032 kb
Host smart-7e5bfe45-a8a2-43c1-a773-d99c6a6a73d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2701836570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2701836570
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.172796099
Short name T92
Test name
Test status
Simulation time 336736530000 ps
CPU time 824.45 seconds
Started Jun 10 04:55:56 PM PDT 24
Finished Jun 10 05:29:45 PM PDT 24
Peak memory 160664 kb
Host smart-32084e9b-8b3c-4bf8-9ec9-848356511fd9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=172796099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.172796099
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3223947228
Short name T5
Test name
Test status
Simulation time 336372490000 ps
CPU time 860.78 seconds
Started Jun 10 04:55:53 PM PDT 24
Finished Jun 10 05:31:17 PM PDT 24
Peak memory 160672 kb
Host smart-c7890ddb-6677-4468-9463-35284cf875f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3223947228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3223947228
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.817850606
Short name T96
Test name
Test status
Simulation time 337031910000 ps
CPU time 870.25 seconds
Started Jun 10 04:55:32 PM PDT 24
Finished Jun 10 05:30:37 PM PDT 24
Peak memory 160668 kb
Host smart-d9a307e9-337c-44b3-9bda-90034cf7821a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=817850606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.817850606
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.4068372530
Short name T106
Test name
Test status
Simulation time 336372710000 ps
CPU time 838.56 seconds
Started Jun 10 04:55:59 PM PDT 24
Finished Jun 10 05:30:05 PM PDT 24
Peak memory 160704 kb
Host smart-3448ada6-7d1f-4e78-b851-e30d68f3cbd3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4068372530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.4068372530
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.651814490
Short name T93
Test name
Test status
Simulation time 336369070000 ps
CPU time 941.9 seconds
Started Jun 10 04:55:30 PM PDT 24
Finished Jun 10 05:34:25 PM PDT 24
Peak memory 160316 kb
Host smart-9b3c4b54-32f6-442c-9a72-cfd9a2422649
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=651814490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.651814490
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3245128642
Short name T78
Test name
Test status
Simulation time 336326190000 ps
CPU time 766.26 seconds
Started Jun 10 04:55:35 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 160744 kb
Host smart-bd909b09-a14a-4fbf-aab8-bf4038be377f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3245128642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3245128642
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2287611085
Short name T110
Test name
Test status
Simulation time 336388310000 ps
CPU time 858.25 seconds
Started Jun 10 04:55:54 PM PDT 24
Finished Jun 10 05:31:44 PM PDT 24
Peak memory 160756 kb
Host smart-36d29ca3-d428-4a13-97d3-57fe83a32467
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2287611085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2287611085
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1094447815
Short name T15
Test name
Test status
Simulation time 336729550000 ps
CPU time 617.51 seconds
Started Jun 10 04:56:01 PM PDT 24
Finished Jun 10 05:21:37 PM PDT 24
Peak memory 160532 kb
Host smart-0a7847e2-ce4a-435d-9ba6-f96e3fcd832b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1094447815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1094447815
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2009916685
Short name T17
Test name
Test status
Simulation time 336342710000 ps
CPU time 745.6 seconds
Started Jun 10 04:55:48 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 160732 kb
Host smart-5ab20a5f-e00b-44b7-8bcf-c237be3c21f4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2009916685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2009916685
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2653005937
Short name T72
Test name
Test status
Simulation time 336761930000 ps
CPU time 953.82 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 05:34:39 PM PDT 24
Peak memory 159744 kb
Host smart-23c21ab4-9567-4db9-8518-09c3ea4545a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2653005937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2653005937
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2329945638
Short name T71
Test name
Test status
Simulation time 337031690000 ps
CPU time 802.79 seconds
Started Jun 10 04:56:01 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 160688 kb
Host smart-f04e131d-80dd-48ca-b934-1dcfc97474f4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2329945638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2329945638
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2835104601
Short name T108
Test name
Test status
Simulation time 336647790000 ps
CPU time 763.54 seconds
Started Jun 10 04:55:59 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 160596 kb
Host smart-6c9d848e-4778-4341-a338-b0dc31151a4b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2835104601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2835104601
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1571417791
Short name T89
Test name
Test status
Simulation time 336668510000 ps
CPU time 939.25 seconds
Started Jun 10 04:56:00 PM PDT 24
Finished Jun 10 05:34:12 PM PDT 24
Peak memory 160708 kb
Host smart-ff8d25ce-c85a-4bd9-9f69-70f1d68123fb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1571417791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1571417791
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3934095416
Short name T107
Test name
Test status
Simulation time 336315170000 ps
CPU time 921.23 seconds
Started Jun 10 04:55:53 PM PDT 24
Finished Jun 10 05:34:03 PM PDT 24
Peak memory 160664 kb
Host smart-dda9a368-1425-4815-a887-35dedca482f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3934095416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3934095416
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1775208308
Short name T101
Test name
Test status
Simulation time 336399090000 ps
CPU time 704.42 seconds
Started Jun 10 04:55:36 PM PDT 24
Finished Jun 10 05:24:19 PM PDT 24
Peak memory 160732 kb
Host smart-8c3665b8-f75b-4b46-a826-d263087dcd90
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1775208308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1775208308
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2070956892
Short name T6
Test name
Test status
Simulation time 336899710000 ps
CPU time 782.73 seconds
Started Jun 10 04:55:35 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 160764 kb
Host smart-162e61e8-cd7b-4ec7-bafa-14e7c7426369
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2070956892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2070956892
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3428463660
Short name T100
Test name
Test status
Simulation time 336833790000 ps
CPU time 794.84 seconds
Started Jun 10 04:56:05 PM PDT 24
Finished Jun 10 05:28:32 PM PDT 24
Peak memory 160700 kb
Host smart-d9db391b-a7c2-492b-89f1-3530b8153845
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3428463660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3428463660
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.4032974562
Short name T79
Test name
Test status
Simulation time 337015410000 ps
CPU time 809.14 seconds
Started Jun 10 04:56:15 PM PDT 24
Finished Jun 10 05:29:24 PM PDT 24
Peak memory 160700 kb
Host smart-edd2c309-5680-4ec1-832d-94f098204d73
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4032974562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.4032974562
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3439803200
Short name T103
Test name
Test status
Simulation time 337101770000 ps
CPU time 775.69 seconds
Started Jun 10 04:55:39 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 160660 kb
Host smart-af0af01f-1742-4d53-b414-22e57fc26c18
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3439803200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3439803200
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1132955735
Short name T77
Test name
Test status
Simulation time 336757270000 ps
CPU time 704.69 seconds
Started Jun 10 04:55:29 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 160692 kb
Host smart-798a09e3-ccf2-4150-9b83-36b76e45f854
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1132955735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1132955735
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2915823498
Short name T104
Test name
Test status
Simulation time 336665570000 ps
CPU time 861.82 seconds
Started Jun 10 04:55:49 PM PDT 24
Finished Jun 10 05:31:43 PM PDT 24
Peak memory 160748 kb
Host smart-dca173f6-13ae-42b8-8aee-575aad6b9c9c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2915823498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2915823498
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4274918307
Short name T16
Test name
Test status
Simulation time 336667870000 ps
CPU time 907.6 seconds
Started Jun 10 04:56:17 PM PDT 24
Finished Jun 10 05:34:10 PM PDT 24
Peak memory 160664 kb
Host smart-9575d4e0-0c33-45b4-b560-e7f1522db9f2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4274918307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4274918307
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.309589204
Short name T75
Test name
Test status
Simulation time 336628790000 ps
CPU time 651.54 seconds
Started Jun 10 04:56:00 PM PDT 24
Finished Jun 10 05:23:10 PM PDT 24
Peak memory 160632 kb
Host smart-bd7ec70d-0cf1-475e-93a0-b48071323d6a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=309589204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.309589204
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3194442920
Short name T105
Test name
Test status
Simulation time 336623350000 ps
CPU time 816.7 seconds
Started Jun 10 04:55:52 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 160704 kb
Host smart-48d982a4-f109-4e0c-b9cb-eefa68f45431
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3194442920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3194442920
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3716255957
Short name T99
Test name
Test status
Simulation time 336540870000 ps
CPU time 834.18 seconds
Started Jun 10 04:55:47 PM PDT 24
Finished Jun 10 05:29:46 PM PDT 24
Peak memory 160672 kb
Host smart-54990980-3ddd-4b92-89c3-2014f6931d31
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3716255957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3716255957
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3361535086
Short name T73
Test name
Test status
Simulation time 336644330000 ps
CPU time 839.53 seconds
Started Jun 10 04:56:15 PM PDT 24
Finished Jun 10 05:31:14 PM PDT 24
Peak memory 160672 kb
Host smart-bb2a473e-a98c-42c6-a906-6895c345a2ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3361535086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3361535086
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2892068353
Short name T85
Test name
Test status
Simulation time 336408410000 ps
CPU time 836.21 seconds
Started Jun 10 04:56:00 PM PDT 24
Finished Jun 10 05:30:17 PM PDT 24
Peak memory 160704 kb
Host smart-c0c121f5-d5d6-4dad-b50b-e68c8a94803f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2892068353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2892068353
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2949467617
Short name T109
Test name
Test status
Simulation time 337011490000 ps
CPU time 838.5 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 05:29:30 PM PDT 24
Peak memory 160672 kb
Host smart-bd5524ee-b101-426c-8561-028fc261506c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2949467617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2949467617
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1951341746
Short name T19
Test name
Test status
Simulation time 336403590000 ps
CPU time 621.3 seconds
Started Jun 10 04:55:59 PM PDT 24
Finished Jun 10 05:22:03 PM PDT 24
Peak memory 160644 kb
Host smart-6f021c63-8993-4143-b3d8-35ee03e1466a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1951341746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1951341746
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1529894778
Short name T7
Test name
Test status
Simulation time 336890310000 ps
CPU time 673.71 seconds
Started Jun 10 04:55:30 PM PDT 24
Finished Jun 10 05:23:09 PM PDT 24
Peak memory 160728 kb
Host smart-5d4c8085-9309-44a8-9aa6-c98945869dbd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1529894778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1529894778
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1941558124
Short name T98
Test name
Test status
Simulation time 336712650000 ps
CPU time 916.41 seconds
Started Jun 10 04:55:36 PM PDT 24
Finished Jun 10 05:33:29 PM PDT 24
Peak memory 160708 kb
Host smart-d76cbe7a-1895-4310-94e5-2a7b7280bf4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1941558124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1941558124
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1579514031
Short name T94
Test name
Test status
Simulation time 336854230000 ps
CPU time 875.96 seconds
Started Jun 10 04:55:47 PM PDT 24
Finished Jun 10 05:31:20 PM PDT 24
Peak memory 160664 kb
Host smart-29ae0d47-94b8-4fb4-ba6b-c08376c33e80
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1579514031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1579514031
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.4045624970
Short name T88
Test name
Test status
Simulation time 336516910000 ps
CPU time 869.38 seconds
Started Jun 10 04:55:43 PM PDT 24
Finished Jun 10 05:31:08 PM PDT 24
Peak memory 160696 kb
Host smart-00a46108-4d6c-41b3-871c-d1d90519493e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4045624970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.4045624970
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.869007995
Short name T84
Test name
Test status
Simulation time 336453490000 ps
CPU time 861.29 seconds
Started Jun 10 04:55:58 PM PDT 24
Finished Jun 10 05:31:05 PM PDT 24
Peak memory 160700 kb
Host smart-1e7c6a43-4efc-4188-a83f-ee98c9bea93a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869007995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.869007995
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2855846781
Short name T91
Test name
Test status
Simulation time 336484830000 ps
CPU time 911.92 seconds
Started Jun 10 04:55:29 PM PDT 24
Finished Jun 10 05:33:11 PM PDT 24
Peak memory 160700 kb
Host smart-8f39e0cb-8836-4cae-91e2-a6b7f53e1535
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2855846781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2855846781
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2122632213
Short name T74
Test name
Test status
Simulation time 336743510000 ps
CPU time 1000.79 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 159876 kb
Host smart-393e6637-3cc4-4552-85da-0d20feacd7af
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2122632213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2122632213
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.820037511
Short name T189
Test name
Test status
Simulation time 336909050000 ps
CPU time 747.66 seconds
Started Jun 10 04:57:24 PM PDT 24
Finished Jun 10 05:27:59 PM PDT 24
Peak memory 160680 kb
Host smart-f8ef0669-23fa-4cab-b649-58f4aeaebf0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=820037511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.820037511
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3978119150
Short name T193
Test name
Test status
Simulation time 336650250000 ps
CPU time 781.55 seconds
Started Jun 10 04:57:36 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 160708 kb
Host smart-4206e86a-7ee4-4d7a-9322-b961e35f2cb2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3978119150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3978119150
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2479134972
Short name T27
Test name
Test status
Simulation time 336787910000 ps
CPU time 748.37 seconds
Started Jun 10 04:57:09 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 160716 kb
Host smart-ddcde91a-1481-4ef9-bf91-42ed755bbe67
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2479134972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2479134972
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.765714895
Short name T28
Test name
Test status
Simulation time 337102910000 ps
CPU time 845.65 seconds
Started Jun 10 04:57:09 PM PDT 24
Finished Jun 10 05:31:33 PM PDT 24
Peak memory 160832 kb
Host smart-f48893ab-5001-4672-9a91-25d0c9659cc6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=765714895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.765714895
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2138058584
Short name T196
Test name
Test status
Simulation time 336526250000 ps
CPU time 780.86 seconds
Started Jun 10 04:57:26 PM PDT 24
Finished Jun 10 05:29:33 PM PDT 24
Peak memory 160804 kb
Host smart-6033d52f-b1a5-4d1f-bd88-51b58f542aac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2138058584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2138058584
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.869097431
Short name T168
Test name
Test status
Simulation time 336349390000 ps
CPU time 703.7 seconds
Started Jun 10 04:57:11 PM PDT 24
Finished Jun 10 05:25:43 PM PDT 24
Peak memory 160652 kb
Host smart-9e34eba2-246f-40ff-b853-269c964cbbc6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869097431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.869097431
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.399089816
Short name T167
Test name
Test status
Simulation time 336320470000 ps
CPU time 927.95 seconds
Started Jun 10 04:57:09 PM PDT 24
Finished Jun 10 05:35:34 PM PDT 24
Peak memory 160708 kb
Host smart-9fec458f-fb0b-4e53-b5ac-d226b3f78b34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=399089816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.399089816
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2408313280
Short name T169
Test name
Test status
Simulation time 336400570000 ps
CPU time 879.02 seconds
Started Jun 10 04:57:16 PM PDT 24
Finished Jun 10 05:32:52 PM PDT 24
Peak memory 160712 kb
Host smart-5c2dcd4e-7b8c-42bf-b396-3f9f82467d61
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2408313280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2408313280
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2568533086
Short name T163
Test name
Test status
Simulation time 336996830000 ps
CPU time 842.86 seconds
Started Jun 10 04:57:26 PM PDT 24
Finished Jun 10 05:32:39 PM PDT 24
Peak memory 160760 kb
Host smart-55addab6-5d27-48cb-839a-9a0a5d2d2fd8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2568533086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2568533086
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1027362136
Short name T177
Test name
Test status
Simulation time 337104630000 ps
CPU time 862.25 seconds
Started Jun 10 04:57:22 PM PDT 24
Finished Jun 10 05:31:56 PM PDT 24
Peak memory 160712 kb
Host smart-c14c46b0-2678-4d02-83f8-b7c3127361da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1027362136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1027362136
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1007905195
Short name T164
Test name
Test status
Simulation time 336622130000 ps
CPU time 733.36 seconds
Started Jun 10 04:57:34 PM PDT 24
Finished Jun 10 05:27:12 PM PDT 24
Peak memory 160732 kb
Host smart-f15a87cb-e60c-496f-87f8-24a3ffdd6439
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1007905195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1007905195
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.29114842
Short name T178
Test name
Test status
Simulation time 336839990000 ps
CPU time 798.41 seconds
Started Jun 10 04:57:16 PM PDT 24
Finished Jun 10 05:29:53 PM PDT 24
Peak memory 160676 kb
Host smart-26cb911d-65fd-41b1-bd0a-1e1b03e65d0d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=29114842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.29114842
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2416787635
Short name T180
Test name
Test status
Simulation time 336959390000 ps
CPU time 828.33 seconds
Started Jun 10 04:57:45 PM PDT 24
Finished Jun 10 05:31:52 PM PDT 24
Peak memory 160672 kb
Host smart-b9e75c89-60eb-4036-aab4-a29c22cd04aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2416787635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2416787635
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.581647496
Short name T186
Test name
Test status
Simulation time 336417950000 ps
CPU time 736.27 seconds
Started Jun 10 04:57:20 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 160720 kb
Host smart-d1299c6e-9222-4254-bd56-45698dc4fd25
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=581647496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.581647496
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.702400178
Short name T171
Test name
Test status
Simulation time 336817790000 ps
CPU time 786.27 seconds
Started Jun 10 04:57:26 PM PDT 24
Finished Jun 10 05:29:55 PM PDT 24
Peak memory 160704 kb
Host smart-72816bb3-3857-4ce8-8184-87966b780384
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=702400178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.702400178
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.602974443
Short name T170
Test name
Test status
Simulation time 337147490000 ps
CPU time 790.81 seconds
Started Jun 10 04:57:21 PM PDT 24
Finished Jun 10 05:29:33 PM PDT 24
Peak memory 160700 kb
Host smart-6d98b61d-075f-4352-9b71-7db473542a5b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=602974443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.602974443
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3384379465
Short name T191
Test name
Test status
Simulation time 336519730000 ps
CPU time 839.13 seconds
Started Jun 10 04:57:26 PM PDT 24
Finished Jun 10 05:32:17 PM PDT 24
Peak memory 160676 kb
Host smart-c6b572ba-f526-4760-ae94-c753de3402b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3384379465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3384379465
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2021692448
Short name T199
Test name
Test status
Simulation time 336757310000 ps
CPU time 868.03 seconds
Started Jun 10 04:57:17 PM PDT 24
Finished Jun 10 05:32:41 PM PDT 24
Peak memory 160712 kb
Host smart-ae553a74-340f-46dd-8ac1-f0f5a2bf5901
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2021692448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2021692448
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4056759768
Short name T174
Test name
Test status
Simulation time 336847370000 ps
CPU time 751.12 seconds
Started Jun 10 04:57:30 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 160648 kb
Host smart-b660882d-d917-4ee5-a6b1-f7b8b9978f7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4056759768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4056759768
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.90966714
Short name T22
Test name
Test status
Simulation time 337089970000 ps
CPU time 841.48 seconds
Started Jun 10 04:57:17 PM PDT 24
Finished Jun 10 05:31:39 PM PDT 24
Peak memory 160812 kb
Host smart-b6d2bf83-9fd8-4588-83ed-72b68d8eecee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=90966714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.90966714
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1428553854
Short name T26
Test name
Test status
Simulation time 336917790000 ps
CPU time 821.5 seconds
Started Jun 10 04:57:14 PM PDT 24
Finished Jun 10 05:30:36 PM PDT 24
Peak memory 160668 kb
Host smart-57782111-86cb-4bcc-a6dd-6fd988fd68b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1428553854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1428553854
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3763553907
Short name T188
Test name
Test status
Simulation time 336929670000 ps
CPU time 753.21 seconds
Started Jun 10 04:57:17 PM PDT 24
Finished Jun 10 05:27:35 PM PDT 24
Peak memory 160700 kb
Host smart-e097582b-5c0d-455d-88e4-188782033ae1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3763553907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3763553907
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3996901509
Short name T21
Test name
Test status
Simulation time 336597730000 ps
CPU time 846.2 seconds
Started Jun 10 04:57:15 PM PDT 24
Finished Jun 10 05:31:19 PM PDT 24
Peak memory 160832 kb
Host smart-94e02149-e85f-4314-83ab-673d3a9a4fbf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3996901509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3996901509
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.860926321
Short name T173
Test name
Test status
Simulation time 336931870000 ps
CPU time 750.32 seconds
Started Jun 10 04:57:33 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 160700 kb
Host smart-c8931b11-d9d3-4eda-970b-845b2d2c7c06
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=860926321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.860926321
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.761889514
Short name T172
Test name
Test status
Simulation time 336374930000 ps
CPU time 819.45 seconds
Started Jun 10 04:57:15 PM PDT 24
Finished Jun 10 05:30:38 PM PDT 24
Peak memory 160664 kb
Host smart-dfca2199-bb62-49c1-ae36-5d60cad7a5b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=761889514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.761889514
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3483399708
Short name T25
Test name
Test status
Simulation time 336669810000 ps
CPU time 830.92 seconds
Started Jun 10 04:57:25 PM PDT 24
Finished Jun 10 05:31:14 PM PDT 24
Peak memory 160692 kb
Host smart-1306f728-720b-42cf-a646-03e732bb87e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3483399708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3483399708
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1006479191
Short name T197
Test name
Test status
Simulation time 336732290000 ps
CPU time 688.05 seconds
Started Jun 10 04:57:25 PM PDT 24
Finished Jun 10 05:26:01 PM PDT 24
Peak memory 160732 kb
Host smart-bc7e09c6-8b39-418c-bb63-b67174358ac1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1006479191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1006479191
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.505542880
Short name T192
Test name
Test status
Simulation time 336587490000 ps
CPU time 818.72 seconds
Started Jun 10 04:57:18 PM PDT 24
Finished Jun 10 05:30:39 PM PDT 24
Peak memory 160672 kb
Host smart-6cc16c33-0043-4893-a972-20ba5e77eede
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505542880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.505542880
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1494432961
Short name T195
Test name
Test status
Simulation time 336466770000 ps
CPU time 781.79 seconds
Started Jun 10 04:57:17 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 160664 kb
Host smart-d68f0be9-055a-441c-89cb-3e9581ab8219
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1494432961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1494432961
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3477532455
Short name T166
Test name
Test status
Simulation time 336509030000 ps
CPU time 767.95 seconds
Started Jun 10 04:57:23 PM PDT 24
Finished Jun 10 05:28:40 PM PDT 24
Peak memory 160732 kb
Host smart-917e4c89-b19a-453a-bbd2-fafda628ccea
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3477532455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3477532455
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3917503738
Short name T182
Test name
Test status
Simulation time 336766150000 ps
CPU time 885.56 seconds
Started Jun 10 04:57:16 PM PDT 24
Finished Jun 10 05:33:49 PM PDT 24
Peak memory 160712 kb
Host smart-f22d3df1-39c6-410e-a522-dda9b2317fda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3917503738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3917503738
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2185432865
Short name T161
Test name
Test status
Simulation time 336546610000 ps
CPU time 783.02 seconds
Started Jun 10 04:57:20 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 160664 kb
Host smart-7ea9dbca-7770-4228-9af7-af1eb43f10d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2185432865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2185432865
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1589796426
Short name T200
Test name
Test status
Simulation time 336498910000 ps
CPU time 853.47 seconds
Started Jun 10 04:57:33 PM PDT 24
Finished Jun 10 05:32:11 PM PDT 24
Peak memory 160712 kb
Host smart-eb8c7401-6795-459f-b8ce-13ac4a49eb52
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1589796426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1589796426
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1063722179
Short name T181
Test name
Test status
Simulation time 336489750000 ps
CPU time 668.17 seconds
Started Jun 10 04:57:29 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 160672 kb
Host smart-25680833-3578-4ade-b071-c9eee622f4e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1063722179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1063722179
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1928600736
Short name T175
Test name
Test status
Simulation time 336308110000 ps
CPU time 926.52 seconds
Started Jun 10 04:57:36 PM PDT 24
Finished Jun 10 05:36:13 PM PDT 24
Peak memory 160668 kb
Host smart-90ad9b8b-d726-446f-a910-c3c57f8fab8c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1928600736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1928600736
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1247738400
Short name T183
Test name
Test status
Simulation time 336801950000 ps
CPU time 784.68 seconds
Started Jun 10 04:57:27 PM PDT 24
Finished Jun 10 05:29:30 PM PDT 24
Peak memory 160724 kb
Host smart-10c2fd56-c575-45f2-9553-35479fa8f4d6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1247738400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1247738400
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2713322852
Short name T185
Test name
Test status
Simulation time 336882450000 ps
CPU time 754.36 seconds
Started Jun 10 04:57:39 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 160712 kb
Host smart-4436548e-a514-49b2-afb0-862a331ea235
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2713322852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2713322852
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.832894298
Short name T23
Test name
Test status
Simulation time 336987270000 ps
CPU time 770.14 seconds
Started Jun 10 04:57:18 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 160640 kb
Host smart-434e0d5b-2e08-4ae9-9a26-a86965ab2281
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=832894298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.832894298
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4270511502
Short name T24
Test name
Test status
Simulation time 336552310000 ps
CPU time 837.81 seconds
Started Jun 10 04:57:22 PM PDT 24
Finished Jun 10 05:31:15 PM PDT 24
Peak memory 160712 kb
Host smart-d1e768e9-b72b-448a-9335-c4d97d92dff1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270511502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4270511502
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3840898090
Short name T194
Test name
Test status
Simulation time 336931490000 ps
CPU time 891.01 seconds
Started Jun 10 04:57:20 PM PDT 24
Finished Jun 10 05:34:17 PM PDT 24
Peak memory 160712 kb
Host smart-0eadf067-1e25-42ec-af5a-f90966a5f6b3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3840898090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3840898090
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.37547691
Short name T176
Test name
Test status
Simulation time 337062790000 ps
CPU time 734.98 seconds
Started Jun 10 04:57:35 PM PDT 24
Finished Jun 10 05:27:36 PM PDT 24
Peak memory 160648 kb
Host smart-c1c662f4-73a2-4a03-8001-946df3ff1428
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=37547691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.37547691
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2754326101
Short name T165
Test name
Test status
Simulation time 336743050000 ps
CPU time 713.79 seconds
Started Jun 10 04:57:19 PM PDT 24
Finished Jun 10 05:26:16 PM PDT 24
Peak memory 160680 kb
Host smart-2cde469e-cf68-468d-a9fb-4d10079dc257
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754326101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2754326101
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.395279088
Short name T179
Test name
Test status
Simulation time 336622610000 ps
CPU time 752.39 seconds
Started Jun 10 04:57:39 PM PDT 24
Finished Jun 10 05:28:44 PM PDT 24
Peak memory 160700 kb
Host smart-7fdb7e07-705f-4026-bcd7-1b45200430d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395279088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.395279088
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2180385870
Short name T198
Test name
Test status
Simulation time 336994850000 ps
CPU time 839.65 seconds
Started Jun 10 04:57:18 PM PDT 24
Finished Jun 10 05:30:53 PM PDT 24
Peak memory 160716 kb
Host smart-3b309be9-00c6-40c0-8c72-76a4fd1d07e9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2180385870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2180385870
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.290792473
Short name T162
Test name
Test status
Simulation time 337031290000 ps
CPU time 755.1 seconds
Started Jun 10 04:57:16 PM PDT 24
Finished Jun 10 05:28:08 PM PDT 24
Peak memory 160676 kb
Host smart-810edf7b-31f8-480f-b895-d1e7a5d7b06e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=290792473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.290792473
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3806482643
Short name T190
Test name
Test status
Simulation time 336985030000 ps
CPU time 927.43 seconds
Started Jun 10 04:57:15 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 160660 kb
Host smart-b80e5cc5-2a9a-4d9b-bf3c-882cbec42165
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3806482643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3806482643
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2185736901
Short name T187
Test name
Test status
Simulation time 336713190000 ps
CPU time 769.48 seconds
Started Jun 10 04:57:14 PM PDT 24
Finished Jun 10 05:28:26 PM PDT 24
Peak memory 160724 kb
Host smart-58eccee6-7747-4f94-bd86-72ad6bc2ffe5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2185736901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2185736901
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3328251643
Short name T184
Test name
Test status
Simulation time 336426210000 ps
CPU time 851.95 seconds
Started Jun 10 04:57:32 PM PDT 24
Finished Jun 10 05:32:39 PM PDT 24
Peak memory 160752 kb
Host smart-36db2914-5f06-40ef-8d33-f0806fc6de7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328251643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3328251643
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2613297699
Short name T30
Test name
Test status
Simulation time 336627690000 ps
CPU time 781.44 seconds
Started Jun 10 04:57:17 PM PDT 24
Finished Jun 10 05:29:24 PM PDT 24
Peak memory 160704 kb
Host smart-8a51ee64-f7ac-4243-8797-940b0881ce8f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2613297699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2613297699
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1200613630
Short name T114
Test name
Test status
Simulation time 1553810000 ps
CPU time 3.92 seconds
Started Jun 10 04:56:49 PM PDT 24
Finished Jun 10 04:56:57 PM PDT 24
Peak memory 164812 kb
Host smart-3d141685-3249-4957-9073-bb1457ca3fe5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1200613630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1200613630
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1518784967
Short name T152
Test name
Test status
Simulation time 1317910000 ps
CPU time 3.92 seconds
Started Jun 10 04:56:27 PM PDT 24
Finished Jun 10 04:56:36 PM PDT 24
Peak memory 164908 kb
Host smart-9da24263-d788-45d6-8915-b0cf697bc9b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518784967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1518784967
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.120719283
Short name T138
Test name
Test status
Simulation time 1513130000 ps
CPU time 3.23 seconds
Started Jun 10 04:56:50 PM PDT 24
Finished Jun 10 04:56:58 PM PDT 24
Peak memory 164700 kb
Host smart-8403a182-e66c-41bc-a58e-ad4885b68270
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120719283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.120719283
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.313421132
Short name T133
Test name
Test status
Simulation time 1542690000 ps
CPU time 4.84 seconds
Started Jun 10 04:56:42 PM PDT 24
Finished Jun 10 04:56:52 PM PDT 24
Peak memory 164700 kb
Host smart-66df391b-799b-4dd8-a287-09372183b986
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=313421132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.313421132
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1371343274
Short name T127
Test name
Test status
Simulation time 1632790000 ps
CPU time 4.22 seconds
Started Jun 10 04:56:54 PM PDT 24
Finished Jun 10 04:57:04 PM PDT 24
Peak memory 164816 kb
Host smart-cb0e00e2-5753-4c1c-9069-8ebe7695b695
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1371343274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1371343274
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2548688997
Short name T117
Test name
Test status
Simulation time 1284890000 ps
CPU time 4.31 seconds
Started Jun 10 04:56:35 PM PDT 24
Finished Jun 10 04:56:44 PM PDT 24
Peak memory 164776 kb
Host smart-cb031cad-9639-4cd0-ac48-113473a0892f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2548688997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2548688997
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3060294405
Short name T131
Test name
Test status
Simulation time 1525670000 ps
CPU time 4.02 seconds
Started Jun 10 04:56:50 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164728 kb
Host smart-14413362-194a-4ba7-a196-3ae420dfb2a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060294405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3060294405
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.252573730
Short name T157
Test name
Test status
Simulation time 1286410000 ps
CPU time 3.85 seconds
Started Jun 10 04:56:54 PM PDT 24
Finished Jun 10 04:57:03 PM PDT 24
Peak memory 164736 kb
Host smart-2280afad-71a1-4c6d-a154-968a4baacfef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=252573730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.252573730
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2555962781
Short name T146
Test name
Test status
Simulation time 1187910000 ps
CPU time 4.27 seconds
Started Jun 10 04:56:46 PM PDT 24
Finished Jun 10 04:56:55 PM PDT 24
Peak memory 164764 kb
Host smart-b4cbaffb-7179-4f6e-918f-f19980811153
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2555962781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2555962781
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3490187198
Short name T129
Test name
Test status
Simulation time 1567550000 ps
CPU time 4.98 seconds
Started Jun 10 04:56:43 PM PDT 24
Finished Jun 10 04:56:54 PM PDT 24
Peak memory 164780 kb
Host smart-c6b9ff89-ce93-4437-8820-87c57a8761c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3490187198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3490187198
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.197873095
Short name T136
Test name
Test status
Simulation time 1564770000 ps
CPU time 4.61 seconds
Started Jun 10 04:56:48 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164776 kb
Host smart-613572fc-a81e-4089-bbda-64d35d5222a1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=197873095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.197873095
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3284755705
Short name T140
Test name
Test status
Simulation time 1505550000 ps
CPU time 4.67 seconds
Started Jun 10 04:56:43 PM PDT 24
Finished Jun 10 04:56:53 PM PDT 24
Peak memory 164824 kb
Host smart-472b470b-7ad6-42c4-ace4-2b63a636f36b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3284755705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3284755705
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.656319318
Short name T126
Test name
Test status
Simulation time 1479850000 ps
CPU time 3.7 seconds
Started Jun 10 04:56:43 PM PDT 24
Finished Jun 10 04:56:51 PM PDT 24
Peak memory 164764 kb
Host smart-15b31821-8c96-4874-889f-a00319bde8f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=656319318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.656319318
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1440444801
Short name T145
Test name
Test status
Simulation time 1511930000 ps
CPU time 4.67 seconds
Started Jun 10 04:56:48 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164780 kb
Host smart-1a7f01a7-538a-450c-8f65-e6d8f32aad60
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440444801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1440444801
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3699289882
Short name T156
Test name
Test status
Simulation time 1536270000 ps
CPU time 3.91 seconds
Started Jun 10 04:56:45 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164784 kb
Host smart-5d436947-2f43-4cd9-a1fb-56e940331474
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699289882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3699289882
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3822120740
Short name T112
Test name
Test status
Simulation time 1518930000 ps
CPU time 4.45 seconds
Started Jun 10 04:56:52 PM PDT 24
Finished Jun 10 04:57:02 PM PDT 24
Peak memory 164784 kb
Host smart-9d1ca551-547b-4d1a-955d-3167fed15a8e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3822120740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3822120740
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2157257424
Short name T137
Test name
Test status
Simulation time 1514950000 ps
CPU time 3.71 seconds
Started Jun 10 04:56:51 PM PDT 24
Finished Jun 10 04:57:00 PM PDT 24
Peak memory 164780 kb
Host smart-7d6ff4ce-c35a-40ae-a9e0-639b6c63508d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2157257424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2157257424
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3124136135
Short name T158
Test name
Test status
Simulation time 1514610000 ps
CPU time 4.76 seconds
Started Jun 10 04:57:04 PM PDT 24
Finished Jun 10 04:57:14 PM PDT 24
Peak memory 164512 kb
Host smart-d962f41d-4f58-4f87-ba08-a4e0b8b3c571
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3124136135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3124136135
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.462075339
Short name T155
Test name
Test status
Simulation time 1517770000 ps
CPU time 4.05 seconds
Started Jun 10 04:56:51 PM PDT 24
Finished Jun 10 04:57:01 PM PDT 24
Peak memory 164812 kb
Host smart-b7377fcb-c2ea-409c-8416-74ef24c34349
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=462075339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.462075339
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.124458163
Short name T121
Test name
Test status
Simulation time 1327930000 ps
CPU time 2.95 seconds
Started Jun 10 04:56:48 PM PDT 24
Finished Jun 10 04:56:55 PM PDT 24
Peak memory 164780 kb
Host smart-8f3adab8-f4ce-4269-9c75-cfa3d8ed18d5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124458163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.124458163
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.592774273
Short name T116
Test name
Test status
Simulation time 1481910000 ps
CPU time 4.53 seconds
Started Jun 10 04:56:49 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164812 kb
Host smart-b6857d31-e8e9-43d2-9056-2c62d6894ab7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=592774273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.592774273
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1157699534
Short name T128
Test name
Test status
Simulation time 1312230000 ps
CPU time 4.35 seconds
Started Jun 10 04:57:00 PM PDT 24
Finished Jun 10 04:57:10 PM PDT 24
Peak memory 164776 kb
Host smart-4debb709-7f62-4362-8a5f-3f93d3b98b4e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1157699534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1157699534
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1684788654
Short name T160
Test name
Test status
Simulation time 1443650000 ps
CPU time 4.03 seconds
Started Jun 10 04:57:02 PM PDT 24
Finished Jun 10 04:57:11 PM PDT 24
Peak memory 164776 kb
Host smart-ef4ef9b7-d775-44bd-8902-6904c538ac84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1684788654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1684788654
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2821504201
Short name T134
Test name
Test status
Simulation time 1449130000 ps
CPU time 3.27 seconds
Started Jun 10 04:56:37 PM PDT 24
Finished Jun 10 04:56:45 PM PDT 24
Peak memory 164784 kb
Host smart-b128b933-439f-43b2-a422-473bc269ad02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2821504201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2821504201
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3660305447
Short name T142
Test name
Test status
Simulation time 1288950000 ps
CPU time 3.26 seconds
Started Jun 10 04:57:05 PM PDT 24
Finished Jun 10 04:57:12 PM PDT 24
Peak memory 164808 kb
Host smart-b49398e9-34a1-4cf3-a630-d780bff90cdf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3660305447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3660305447
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2012688632
Short name T150
Test name
Test status
Simulation time 1557590000 ps
CPU time 4.76 seconds
Started Jun 10 04:56:53 PM PDT 24
Finished Jun 10 04:57:04 PM PDT 24
Peak memory 164764 kb
Host smart-87501bc8-6c4f-4dfc-b1a4-05f746c493ae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2012688632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2012688632
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.539682367
Short name T151
Test name
Test status
Simulation time 1564690000 ps
CPU time 5.7 seconds
Started Jun 10 04:56:57 PM PDT 24
Finished Jun 10 04:57:09 PM PDT 24
Peak memory 164736 kb
Host smart-4edaec32-2bc5-44c7-ac52-63d532142e46
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539682367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.539682367
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2417153837
Short name T147
Test name
Test status
Simulation time 1506250000 ps
CPU time 3.39 seconds
Started Jun 10 04:57:07 PM PDT 24
Finished Jun 10 04:57:14 PM PDT 24
Peak memory 164780 kb
Host smart-6712a38a-6455-47a1-a2e3-0f588ea81034
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417153837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2417153837
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1801644480
Short name T120
Test name
Test status
Simulation time 1460830000 ps
CPU time 4.52 seconds
Started Jun 10 04:56:53 PM PDT 24
Finished Jun 10 04:57:03 PM PDT 24
Peak memory 164764 kb
Host smart-6b783568-6352-45cc-9724-40f148c7ca57
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1801644480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1801644480
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.834440650
Short name T119
Test name
Test status
Simulation time 1417250000 ps
CPU time 4.63 seconds
Started Jun 10 04:56:55 PM PDT 24
Finished Jun 10 04:57:05 PM PDT 24
Peak memory 164504 kb
Host smart-b9fa7750-10f0-4759-bc8d-420404776c73
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=834440650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.834440650
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.816147336
Short name T122
Test name
Test status
Simulation time 1493110000 ps
CPU time 4.57 seconds
Started Jun 10 04:57:00 PM PDT 24
Finished Jun 10 04:57:10 PM PDT 24
Peak memory 164688 kb
Host smart-fbecf30a-4baa-44ce-8b8e-1cb6af95483d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=816147336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.816147336
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.507413493
Short name T125
Test name
Test status
Simulation time 1652470000 ps
CPU time 4.18 seconds
Started Jun 10 04:56:51 PM PDT 24
Finished Jun 10 04:57:01 PM PDT 24
Peak memory 164720 kb
Host smart-362d756b-33b5-45cd-b483-0569f0e04d33
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=507413493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.507413493
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2547026695
Short name T153
Test name
Test status
Simulation time 1388510000 ps
CPU time 4.2 seconds
Started Jun 10 04:56:49 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164764 kb
Host smart-9aa68cc4-4765-4a98-8d62-bd870703e3c8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2547026695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2547026695
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1956996036
Short name T144
Test name
Test status
Simulation time 1527630000 ps
CPU time 4.44 seconds
Started Jun 10 04:56:57 PM PDT 24
Finished Jun 10 04:57:07 PM PDT 24
Peak memory 164764 kb
Host smart-0c5d6491-64ab-4e99-a67f-00d4f2b0b228
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1956996036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1956996036
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2896020458
Short name T111
Test name
Test status
Simulation time 1560430000 ps
CPU time 3.28 seconds
Started Jun 10 04:56:38 PM PDT 24
Finished Jun 10 04:56:46 PM PDT 24
Peak memory 164816 kb
Host smart-f161b608-7689-4415-811c-71ec766cc149
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2896020458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2896020458
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.584749968
Short name T124
Test name
Test status
Simulation time 1529510000 ps
CPU time 4.51 seconds
Started Jun 10 04:56:57 PM PDT 24
Finished Jun 10 04:57:07 PM PDT 24
Peak memory 164756 kb
Host smart-37b74f8e-64bc-4e02-95ec-f15d4bdc7993
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=584749968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.584749968
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3631453526
Short name T139
Test name
Test status
Simulation time 1484510000 ps
CPU time 4.28 seconds
Started Jun 10 04:56:54 PM PDT 24
Finished Jun 10 04:57:04 PM PDT 24
Peak memory 164764 kb
Host smart-03e4d4c5-1d1e-46a2-8844-cd885bb89f5e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631453526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3631453526
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3585996198
Short name T149
Test name
Test status
Simulation time 1344170000 ps
CPU time 3.72 seconds
Started Jun 10 04:56:40 PM PDT 24
Finished Jun 10 04:56:48 PM PDT 24
Peak memory 164760 kb
Host smart-97a1424a-6593-492a-b442-d1daac53d7ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585996198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3585996198
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4171612295
Short name T132
Test name
Test status
Simulation time 1413950000 ps
CPU time 3.19 seconds
Started Jun 10 04:56:56 PM PDT 24
Finished Jun 10 04:57:04 PM PDT 24
Peak memory 164804 kb
Host smart-76f6101f-a11b-432f-aca5-3d3c8661c649
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4171612295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.4171612295
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1341446629
Short name T130
Test name
Test status
Simulation time 1505690000 ps
CPU time 4.38 seconds
Started Jun 10 04:56:56 PM PDT 24
Finished Jun 10 04:57:06 PM PDT 24
Peak memory 164728 kb
Host smart-106ce10d-e1d7-440a-9677-9ff59e2b5c00
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341446629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1341446629
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2766944873
Short name T118
Test name
Test status
Simulation time 1524410000 ps
CPU time 5.88 seconds
Started Jun 10 04:57:00 PM PDT 24
Finished Jun 10 04:57:14 PM PDT 24
Peak memory 164744 kb
Host smart-1a00593c-ff70-4019-b5f8-a6e50b77fc02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2766944873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2766944873
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2971730967
Short name T148
Test name
Test status
Simulation time 1503810000 ps
CPU time 5.32 seconds
Started Jun 10 04:56:48 PM PDT 24
Finished Jun 10 04:57:00 PM PDT 24
Peak memory 164780 kb
Host smart-51a783f3-4a5c-4d89-b5d8-0c4ad1408688
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2971730967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2971730967
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1776842386
Short name T115
Test name
Test status
Simulation time 1513870000 ps
CPU time 4.66 seconds
Started Jun 10 04:56:57 PM PDT 24
Finished Jun 10 04:57:08 PM PDT 24
Peak memory 164780 kb
Host smart-b5d1512f-b470-4b25-807c-2e3e9f048c2e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1776842386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1776842386
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1369213354
Short name T159
Test name
Test status
Simulation time 1365030000 ps
CPU time 3.35 seconds
Started Jun 10 04:57:06 PM PDT 24
Finished Jun 10 04:57:14 PM PDT 24
Peak memory 164708 kb
Host smart-bb3a3ba6-1b44-4b51-9279-2616422cc6c9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1369213354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.1369213354
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1073969361
Short name T113
Test name
Test status
Simulation time 1507670000 ps
CPU time 4.78 seconds
Started Jun 10 04:57:09 PM PDT 24
Finished Jun 10 04:57:21 PM PDT 24
Peak memory 164744 kb
Host smart-f03084a5-9d92-44b9-8b95-f83453d62dc5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1073969361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1073969361
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2517531612
Short name T154
Test name
Test status
Simulation time 1495430000 ps
CPU time 4.28 seconds
Started Jun 10 04:56:49 PM PDT 24
Finished Jun 10 04:56:59 PM PDT 24
Peak memory 164784 kb
Host smart-2673da9f-a462-4332-b55e-a8cd97deb6ff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517531612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2517531612
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.552828166
Short name T123
Test name
Test status
Simulation time 1383070000 ps
CPU time 4.73 seconds
Started Jun 10 04:56:45 PM PDT 24
Finished Jun 10 04:56:56 PM PDT 24
Peak memory 164764 kb
Host smart-b911c4b8-5bcf-44c6-9bdc-d043a5aa4f80
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=552828166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.552828166
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2343097540
Short name T135
Test name
Test status
Simulation time 1169330000 ps
CPU time 2.84 seconds
Started Jun 10 04:57:06 PM PDT 24
Finished Jun 10 04:57:13 PM PDT 24
Peak memory 164724 kb
Host smart-49bca88c-38e6-40d6-ac4f-5d563f91c02c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2343097540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2343097540
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.2904351389
Short name T141
Test name
Test status
Simulation time 1430510000 ps
CPU time 4.39 seconds
Started Jun 10 04:56:35 PM PDT 24
Finished Jun 10 04:56:45 PM PDT 24
Peak memory 164788 kb
Host smart-b342acfa-9eba-445e-b348-6ca09b1f1054
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2904351389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.2904351389
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.988144747
Short name T143
Test name
Test status
Simulation time 1173010000 ps
CPU time 2.73 seconds
Started Jun 10 04:56:54 PM PDT 24
Finished Jun 10 04:57:00 PM PDT 24
Peak memory 164760 kb
Host smart-6a6f07f2-b2b6-456b-a676-035c801f29bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=988144747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.988144747
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1803908423
Short name T64
Test name
Test status
Simulation time 1198950000 ps
CPU time 3.06 seconds
Started Jun 10 04:55:26 PM PDT 24
Finished Jun 10 04:55:33 PM PDT 24
Peak memory 164812 kb
Host smart-bd2c21bf-97c8-4083-8eea-58680f9ba145
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1803908423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1803908423
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1493688427
Short name T35
Test name
Test status
Simulation time 1340590000 ps
CPU time 3.74 seconds
Started Jun 10 04:55:20 PM PDT 24
Finished Jun 10 04:55:28 PM PDT 24
Peak memory 164840 kb
Host smart-5526a390-36cd-4319-b09c-8d829a5970ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493688427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1493688427
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2753047499
Short name T55
Test name
Test status
Simulation time 1230970000 ps
CPU time 3.28 seconds
Started Jun 10 04:55:11 PM PDT 24
Finished Jun 10 04:55:18 PM PDT 24
Peak memory 164712 kb
Host smart-2777c382-c312-4ab3-9307-540f2011c6c6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2753047499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2753047499
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2911270344
Short name T45
Test name
Test status
Simulation time 1468290000 ps
CPU time 4.28 seconds
Started Jun 10 04:55:01 PM PDT 24
Finished Jun 10 04:55:11 PM PDT 24
Peak memory 164760 kb
Host smart-a915b530-b11f-4543-9c9d-5778a7bae678
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911270344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2911270344
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2937990404
Short name T41
Test name
Test status
Simulation time 1451250000 ps
CPU time 3.34 seconds
Started Jun 10 04:55:07 PM PDT 24
Finished Jun 10 04:55:15 PM PDT 24
Peak memory 164724 kb
Host smart-8b8fb483-163d-4618-a495-c658d5504d24
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2937990404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2937990404
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3202206487
Short name T39
Test name
Test status
Simulation time 1531630000 ps
CPU time 3.18 seconds
Started Jun 10 04:55:47 PM PDT 24
Finished Jun 10 04:55:54 PM PDT 24
Peak memory 164776 kb
Host smart-4afb650f-a9d5-4bd8-87fc-4eccfb81858a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3202206487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3202206487
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1637790219
Short name T52
Test name
Test status
Simulation time 1537750000 ps
CPU time 4.01 seconds
Started Jun 10 04:55:00 PM PDT 24
Finished Jun 10 04:55:09 PM PDT 24
Peak memory 164760 kb
Host smart-d00636c6-b1fd-4e07-80f2-b3b764592c91
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1637790219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1637790219
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3116863494
Short name T2
Test name
Test status
Simulation time 1535490000 ps
CPU time 4.22 seconds
Started Jun 10 04:55:12 PM PDT 24
Finished Jun 10 04:55:21 PM PDT 24
Peak memory 164748 kb
Host smart-45f30fcf-21c2-4147-a0ce-c1a411701392
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3116863494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3116863494
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1414147659
Short name T13
Test name
Test status
Simulation time 1490450000 ps
CPU time 3.64 seconds
Started Jun 10 04:55:01 PM PDT 24
Finished Jun 10 04:55:09 PM PDT 24
Peak memory 164780 kb
Host smart-1a6421e3-57c6-4957-bd56-e9d65d2c906d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414147659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1414147659
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1463830856
Short name T57
Test name
Test status
Simulation time 1218030000 ps
CPU time 2.71 seconds
Started Jun 10 04:55:22 PM PDT 24
Finished Jun 10 04:55:28 PM PDT 24
Peak memory 164676 kb
Host smart-90d924be-a337-4a05-8dc6-7700e9b5926f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463830856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1463830856
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1508814298
Short name T65
Test name
Test status
Simulation time 1536370000 ps
CPU time 3.05 seconds
Started Jun 10 04:55:31 PM PDT 24
Finished Jun 10 04:55:38 PM PDT 24
Peak memory 164728 kb
Host smart-ee08e3bc-c446-4531-9d38-1ade2fec7359
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1508814298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1508814298
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3838010864
Short name T38
Test name
Test status
Simulation time 1311210000 ps
CPU time 2.75 seconds
Started Jun 10 04:55:38 PM PDT 24
Finished Jun 10 04:55:49 PM PDT 24
Peak memory 164768 kb
Host smart-3c43564c-13a0-43ac-967a-a4cb8225bfbf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3838010864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3838010864
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1122367509
Short name T60
Test name
Test status
Simulation time 1525990000 ps
CPU time 4.26 seconds
Started Jun 10 04:55:30 PM PDT 24
Finished Jun 10 04:55:39 PM PDT 24
Peak memory 164780 kb
Host smart-4b82f800-54ba-45b2-8c96-53484683f145
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1122367509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1122367509
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4248164175
Short name T70
Test name
Test status
Simulation time 1457030000 ps
CPU time 3.34 seconds
Started Jun 10 04:55:36 PM PDT 24
Finished Jun 10 04:55:43 PM PDT 24
Peak memory 164772 kb
Host smart-096e5337-0a0b-4bad-ba77-13349847581f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248164175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.4248164175
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2379039607
Short name T47
Test name
Test status
Simulation time 1377270000 ps
CPU time 4.07 seconds
Started Jun 10 04:55:11 PM PDT 24
Finished Jun 10 04:55:20 PM PDT 24
Peak memory 164812 kb
Host smart-cdb237be-dfce-4fa3-ad6f-e04a8d6647a1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2379039607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2379039607
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1657682237
Short name T58
Test name
Test status
Simulation time 1352310000 ps
CPU time 2.89 seconds
Started Jun 10 04:55:08 PM PDT 24
Finished Jun 10 04:55:15 PM PDT 24
Peak memory 164764 kb
Host smart-9ff9b0ee-a036-4dd7-bae4-871202d0a291
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1657682237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1657682237
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3361704505
Short name T32
Test name
Test status
Simulation time 1505310000 ps
CPU time 3 seconds
Started Jun 10 04:55:41 PM PDT 24
Finished Jun 10 04:55:48 PM PDT 24
Peak memory 164728 kb
Host smart-55bb3062-30d7-4556-810d-7889e188535b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3361704505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3361704505
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1534780523
Short name T67
Test name
Test status
Simulation time 1389690000 ps
CPU time 3.64 seconds
Started Jun 10 04:55:18 PM PDT 24
Finished Jun 10 04:55:26 PM PDT 24
Peak memory 164760 kb
Host smart-c94dcc0e-07f7-4135-973f-d8f600640126
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1534780523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1534780523
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2239305295
Short name T10
Test name
Test status
Simulation time 1576430000 ps
CPU time 4.14 seconds
Started Jun 10 04:55:15 PM PDT 24
Finished Jun 10 04:55:25 PM PDT 24
Peak memory 164748 kb
Host smart-ef2cc5e5-8f1f-4bc9-bd86-3f2049c6ed1e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2239305295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2239305295
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2202892832
Short name T49
Test name
Test status
Simulation time 1533550000 ps
CPU time 5.44 seconds
Started Jun 10 04:55:05 PM PDT 24
Finished Jun 10 04:55:16 PM PDT 24
Peak memory 164748 kb
Host smart-ebdae34e-baf9-459a-9a6c-174ad92adff8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2202892832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2202892832
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.461873758
Short name T61
Test name
Test status
Simulation time 1433230000 ps
CPU time 3.55 seconds
Started Jun 10 04:55:08 PM PDT 24
Finished Jun 10 04:55:16 PM PDT 24
Peak memory 164780 kb
Host smart-21539c94-59e2-4554-bdd7-93b78cfc3d42
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461873758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.461873758
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.406470668
Short name T36
Test name
Test status
Simulation time 1490870000 ps
CPU time 3.1 seconds
Started Jun 10 04:55:41 PM PDT 24
Finished Jun 10 04:55:48 PM PDT 24
Peak memory 164768 kb
Host smart-759c4e84-e096-43ec-b3cf-db367c5ba556
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=406470668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.406470668
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2129726048
Short name T4
Test name
Test status
Simulation time 1418530000 ps
CPU time 2.81 seconds
Started Jun 10 04:55:19 PM PDT 24
Finished Jun 10 04:55:25 PM PDT 24
Peak memory 164736 kb
Host smart-b53b1518-fc7b-44db-a187-64567fdbf364
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2129726048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2129726048
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3870559833
Short name T46
Test name
Test status
Simulation time 1415630000 ps
CPU time 3.03 seconds
Started Jun 10 04:55:37 PM PDT 24
Finished Jun 10 04:55:44 PM PDT 24
Peak memory 164784 kb
Host smart-c8ac4e4a-c364-4c8a-84ce-b707ef8dcce2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3870559833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3870559833
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.309288013
Short name T66
Test name
Test status
Simulation time 1466650000 ps
CPU time 2.96 seconds
Started Jun 10 04:55:26 PM PDT 24
Finished Jun 10 04:55:33 PM PDT 24
Peak memory 164776 kb
Host smart-39dd1b98-af74-4839-907d-f08e3adf60f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=309288013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.309288013
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1929167961
Short name T31
Test name
Test status
Simulation time 1586910000 ps
CPU time 3.88 seconds
Started Jun 10 04:55:14 PM PDT 24
Finished Jun 10 04:55:23 PM PDT 24
Peak memory 164780 kb
Host smart-4f7b99c8-a04b-4c2e-bf5e-9763edf03b60
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1929167961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1929167961
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2250027494
Short name T1
Test name
Test status
Simulation time 1585290000 ps
CPU time 4.24 seconds
Started Jun 10 04:55:10 PM PDT 24
Finished Jun 10 04:55:20 PM PDT 24
Peak memory 164744 kb
Host smart-115a099b-0fa2-4887-8037-01ba474c95bc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2250027494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2250027494
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.454476665
Short name T53
Test name
Test status
Simulation time 1528250000 ps
CPU time 3.53 seconds
Started Jun 10 04:55:43 PM PDT 24
Finished Jun 10 04:55:51 PM PDT 24
Peak memory 164672 kb
Host smart-08fd0095-2af7-442b-9169-1338de09b996
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454476665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.454476665
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.777826176
Short name T48
Test name
Test status
Simulation time 1429090000 ps
CPU time 3.17 seconds
Started Jun 10 04:55:16 PM PDT 24
Finished Jun 10 04:55:24 PM PDT 24
Peak memory 164504 kb
Host smart-273b2039-9912-408c-92f7-5b9f2bf7ab32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777826176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.777826176
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.562569420
Short name T3
Test name
Test status
Simulation time 1148270000 ps
CPU time 2.7 seconds
Started Jun 10 04:55:35 PM PDT 24
Finished Jun 10 04:55:41 PM PDT 24
Peak memory 164736 kb
Host smart-47da8793-0ff8-4aff-bfe7-9430d0ff83a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=562569420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.562569420
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.4193398644
Short name T37
Test name
Test status
Simulation time 1418430000 ps
CPU time 3.99 seconds
Started Jun 10 04:55:10 PM PDT 24
Finished Jun 10 04:55:19 PM PDT 24
Peak memory 164816 kb
Host smart-dd15fbcc-dc39-4a95-8b67-1e998d75f338
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193398644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.4193398644
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.145330702
Short name T9
Test name
Test status
Simulation time 1404490000 ps
CPU time 3.9 seconds
Started Jun 10 04:55:10 PM PDT 24
Finished Jun 10 04:55:19 PM PDT 24
Peak memory 164900 kb
Host smart-1ea5588e-00d3-4985-bbe0-17656a9ef61d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=145330702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.145330702
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1362678935
Short name T34
Test name
Test status
Simulation time 1435370000 ps
CPU time 3.65 seconds
Started Jun 10 04:55:16 PM PDT 24
Finished Jun 10 04:55:30 PM PDT 24
Peak memory 164772 kb
Host smart-19599f86-f800-4486-b321-12499d51e8b0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1362678935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1362678935
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.289393874
Short name T40
Test name
Test status
Simulation time 1424370000 ps
CPU time 3.42 seconds
Started Jun 10 04:55:10 PM PDT 24
Finished Jun 10 04:55:18 PM PDT 24
Peak memory 164468 kb
Host smart-69539471-c518-4ed5-981e-5a0099a5ba9f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=289393874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.289393874
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1526969301
Short name T68
Test name
Test status
Simulation time 1448210000 ps
CPU time 3.11 seconds
Started Jun 10 04:55:22 PM PDT 24
Finished Jun 10 04:55:29 PM PDT 24
Peak memory 164712 kb
Host smart-f5b2b727-aa11-4fe7-b95c-219a73d38629
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1526969301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1526969301
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2814987287
Short name T42
Test name
Test status
Simulation time 1501550000 ps
CPU time 3.89 seconds
Started Jun 10 04:55:10 PM PDT 24
Finished Jun 10 04:55:24 PM PDT 24
Peak memory 164720 kb
Host smart-cda9e63d-2bc4-464d-b67c-1ff4e3cc4d5b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814987287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2814987287
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.4112306512
Short name T50
Test name
Test status
Simulation time 1591810000 ps
CPU time 4.49 seconds
Started Jun 10 04:55:28 PM PDT 24
Finished Jun 10 04:55:38 PM PDT 24
Peak memory 164780 kb
Host smart-1910c022-03e8-496f-b5df-260b320d7150
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4112306512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.4112306512
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2606753793
Short name T59
Test name
Test status
Simulation time 1510630000 ps
CPU time 3.82 seconds
Started Jun 10 04:55:26 PM PDT 24
Finished Jun 10 04:55:34 PM PDT 24
Peak memory 164728 kb
Host smart-b942daba-b976-4512-af17-6ea9e8a788bd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2606753793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2606753793
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.200690518
Short name T44
Test name
Test status
Simulation time 1373570000 ps
CPU time 3.5 seconds
Started Jun 10 04:55:27 PM PDT 24
Finished Jun 10 04:55:35 PM PDT 24
Peak memory 164728 kb
Host smart-6a85aebe-de07-4493-9bda-64fe9e0c7a3e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=200690518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.200690518
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3125774041
Short name T11
Test name
Test status
Simulation time 1486510000 ps
CPU time 4.37 seconds
Started Jun 10 04:55:01 PM PDT 24
Finished Jun 10 04:55:10 PM PDT 24
Peak memory 164788 kb
Host smart-b77e3516-ba6b-46a1-a941-e9d07a88db54
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3125774041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3125774041
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.58555450
Short name T43
Test name
Test status
Simulation time 1390690000 ps
CPU time 3.1 seconds
Started Jun 10 04:55:23 PM PDT 24
Finished Jun 10 04:55:30 PM PDT 24
Peak memory 164768 kb
Host smart-355cbc28-ad3a-45f7-ae16-2702c202c15e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58555450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.58555450
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3589987099
Short name T56
Test name
Test status
Simulation time 1240010000 ps
CPU time 3.78 seconds
Started Jun 10 04:55:24 PM PDT 24
Finished Jun 10 04:55:32 PM PDT 24
Peak memory 164772 kb
Host smart-ab768c39-6c57-47c4-963c-487fe6218f47
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589987099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3589987099
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3475791447
Short name T8
Test name
Test status
Simulation time 1534610000 ps
CPU time 3.34 seconds
Started Jun 10 04:55:17 PM PDT 24
Finished Jun 10 04:55:25 PM PDT 24
Peak memory 164728 kb
Host smart-cca1974c-300a-4f44-bd94-00eaca7b7611
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3475791447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3475791447
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3322255536
Short name T51
Test name
Test status
Simulation time 1376310000 ps
CPU time 3.76 seconds
Started Jun 10 04:55:20 PM PDT 24
Finished Jun 10 04:55:28 PM PDT 24
Peak memory 164760 kb
Host smart-775eaea9-7154-44ba-a3ab-1591669062d7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3322255536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3322255536
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3551389083
Short name T33
Test name
Test status
Simulation time 1615930000 ps
CPU time 5.16 seconds
Started Jun 10 04:55:04 PM PDT 24
Finished Jun 10 04:55:16 PM PDT 24
Peak memory 164748 kb
Host smart-51996ba5-5d89-4f50-9dd6-bddf81a85d6a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3551389083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3551389083
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3085863064
Short name T54
Test name
Test status
Simulation time 1444750000 ps
CPU time 3.85 seconds
Started Jun 10 04:55:05 PM PDT 24
Finished Jun 10 04:55:14 PM PDT 24
Peak memory 164824 kb
Host smart-91a83730-c2cb-40f1-9654-37dee11b2f5e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3085863064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3085863064
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4045998192
Short name T69
Test name
Test status
Simulation time 1338010000 ps
CPU time 3.25 seconds
Started Jun 10 04:55:07 PM PDT 24
Finished Jun 10 04:55:14 PM PDT 24
Peak memory 164760 kb
Host smart-f48ef3f3-6f1e-484e-907d-db48c85d44c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045998192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.4045998192
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3929533788
Short name T63
Test name
Test status
Simulation time 1395590000 ps
CPU time 2.94 seconds
Started Jun 10 04:55:02 PM PDT 24
Finished Jun 10 04:55:09 PM PDT 24
Peak memory 164788 kb
Host smart-bf73e8fc-82fe-40e0-b378-291e30f3345e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3929533788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3929533788
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3206285939
Short name T62
Test name
Test status
Simulation time 1432430000 ps
CPU time 3.71 seconds
Started Jun 10 04:55:24 PM PDT 24
Finished Jun 10 04:55:32 PM PDT 24
Peak memory 164696 kb
Host smart-67ba62b6-3566-48b4-b7e3-af3f4758c083
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3206285939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3206285939
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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