Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3583405218
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1388709727
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.73797355

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3680972599
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.763175659
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4066806933
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1577185959
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.921189485
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2889282220
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.774489116
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2343375801
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4111134231
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1291295266
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1691666310
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1109907717
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.472889088
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1232789425
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.880758755
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1244623716
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.171882496
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1028324315
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.223756999
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2086753227
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3302486718
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.418196686
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2624020600
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2847337107
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3028045271
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4249709860
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2573935896
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.239239099
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1502949757
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1862046385
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3802783767
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2963096732
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1995196823
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.409241565
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1225084578
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3947572034
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2344006839
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2817821834
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3201755140
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2343811400
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.854030831
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2730730081
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1119016616
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.973389279
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.38375060
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3481200324
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1291894637
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2171480675
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1228549757
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3897860352
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2742128577
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.328158757
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1391195500
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4035238509
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2862638793
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2225208254
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1304965279
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3353268323
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3317903118
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2753101576
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3243734081
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1585217079
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.229034537
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1847161118
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1193999648
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2691710091
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.469411956
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3372342166
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1684487999
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4258784776
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.793120492
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1096910711
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3117641252
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2572744114
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4192598295
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4208325140
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.5538970
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1945748712
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1168695140
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.8129137
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3374922871
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3676319700
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.663525099
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.905652123
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2721300381
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.785981933
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.317880678
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1670037768
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3043357903
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2985163519
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.49624402
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1129997004
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2234172019
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.724338988
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2007251225
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4149284094
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4291163006
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3655543439
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3565958932
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.129085394
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3193267266
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4068986785
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4225090239
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.512380963
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2623378353
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1750844578
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1703337513
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1691696760
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2438322883
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.718879279
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1586358378
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3760136549
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2338766721
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4256013167
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2217068720
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.127390246
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4021152203
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2481529935
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2419869583
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2899420400
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.867610033
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3013997553
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1373643564
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3511899924
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.324961439
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3745643298
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4218802886
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3919532838
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.104882641
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2874776966
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3442742648
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2648204
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1109416247
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2211175533
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.726209798
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3047666646
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1747214406
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.645360773
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.33704015
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.190968482
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.976332351
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2922447734
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.323745361
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2716395516
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1530727513
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2788726082
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1077896670
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.695608259
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3157528933
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3737291568
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2081521915
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3311970240
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1505335539
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1004723481
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1398315720
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2692965580
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.47362512
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3699853362
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3228885509
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.413608577
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1803488700
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3197519569
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4283341609
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2973536275
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2143059747
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3207773743
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1020843378
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.239927135
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1282610458
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.280260283
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.704783842
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.779808965
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.529663493
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3414364012
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2349452086
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2411268389
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4219419909
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1844510777
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2772932285
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.813319723
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2984146603
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3475322304
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1857192203
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4187392099
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.396984690
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3855341485
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2312425853
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1213918494
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1421986580
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2331916805
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1645083553
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3318663470
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1624485573
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1604001339
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3144533825
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.824587503
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3206580312



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3737291568 Jun 11 01:49:19 PM PDT 24 Jun 11 01:49:32 PM PDT 24 1322310000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.239927135 Jun 11 01:49:41 PM PDT 24 Jun 11 01:49:50 PM PDT 24 1536550000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2331916805 Jun 11 01:49:42 PM PDT 24 Jun 11 01:49:54 PM PDT 24 1614250000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.824587503 Jun 11 01:49:25 PM PDT 24 Jun 11 01:49:37 PM PDT 24 1479970000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1604001339 Jun 11 01:49:30 PM PDT 24 Jun 11 01:49:40 PM PDT 24 1607670000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2772932285 Jun 11 01:49:40 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1465450000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3157528933 Jun 11 01:49:27 PM PDT 24 Jun 11 01:49:36 PM PDT 24 1350270000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3583405218 Jun 11 01:49:46 PM PDT 24 Jun 11 01:49:56 PM PDT 24 1513070000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2349452086 Jun 11 01:49:43 PM PDT 24 Jun 11 01:49:51 PM PDT 24 1435630000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4219419909 Jun 11 01:49:44 PM PDT 24 Jun 11 01:49:55 PM PDT 24 1511450000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.396984690 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:45 PM PDT 24 1449170000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.280260283 Jun 11 01:49:32 PM PDT 24 Jun 11 01:49:43 PM PDT 24 1490750000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2984146603 Jun 11 01:49:35 PM PDT 24 Jun 11 01:49:44 PM PDT 24 1439590000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3311970240 Jun 11 01:49:20 PM PDT 24 Jun 11 01:49:34 PM PDT 24 1345090000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3206580312 Jun 11 01:49:33 PM PDT 24 Jun 11 01:49:45 PM PDT 24 1323070000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2312425853 Jun 11 01:49:43 PM PDT 24 Jun 11 01:49:53 PM PDT 24 1537630000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1213918494 Jun 11 01:49:38 PM PDT 24 Jun 11 01:49:50 PM PDT 24 1552890000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.47362512 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:47 PM PDT 24 1515310000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.413608577 Jun 11 01:49:45 PM PDT 24 Jun 11 01:49:54 PM PDT 24 1588530000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1645083553 Jun 11 01:49:46 PM PDT 24 Jun 11 01:49:55 PM PDT 24 1313310000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1020843378 Jun 11 01:49:42 PM PDT 24 Jun 11 01:49:55 PM PDT 24 1562790000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1624485573 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:46 PM PDT 24 1156490000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.779808965 Jun 11 01:49:47 PM PDT 24 Jun 11 01:49:56 PM PDT 24 1303230000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3197519569 Jun 11 01:49:38 PM PDT 24 Jun 11 01:49:46 PM PDT 24 1179610000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1857192203 Jun 11 01:49:43 PM PDT 24 Jun 11 01:49:53 PM PDT 24 1550650000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.813319723 Jun 11 01:49:38 PM PDT 24 Jun 11 01:49:45 PM PDT 24 1129030000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3207773743 Jun 11 01:49:46 PM PDT 24 Jun 11 01:49:56 PM PDT 24 1573830000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4283341609 Jun 11 01:49:42 PM PDT 24 Jun 11 01:49:52 PM PDT 24 1235930000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2411268389 Jun 11 01:49:38 PM PDT 24 Jun 11 01:49:50 PM PDT 24 1605390000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3414364012 Jun 11 01:49:35 PM PDT 24 Jun 11 01:49:46 PM PDT 24 1560010000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1505335539 Jun 11 01:49:34 PM PDT 24 Jun 11 01:49:44 PM PDT 24 1538170000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3318663470 Jun 11 01:49:30 PM PDT 24 Jun 11 01:49:39 PM PDT 24 1300090000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2143059747 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1570530000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3144533825 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:47 PM PDT 24 1435610000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3855341485 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:43 PM PDT 24 1099370000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4187392099 Jun 11 01:49:40 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1565430000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3699853362 Jun 11 01:49:36 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1524410000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.529663493 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:47 PM PDT 24 1359650000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1282610458 Jun 11 01:49:40 PM PDT 24 Jun 11 01:49:50 PM PDT 24 1582950000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1004723481 Jun 11 01:49:35 PM PDT 24 Jun 11 01:49:46 PM PDT 24 1450710000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2692965580 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1635790000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2081521915 Jun 11 01:49:29 PM PDT 24 Jun 11 01:49:39 PM PDT 24 1339570000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1421986580 Jun 11 01:49:42 PM PDT 24 Jun 11 01:49:52 PM PDT 24 1305970000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3228885509 Jun 11 01:49:41 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1249050000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.704783842 Jun 11 01:49:20 PM PDT 24 Jun 11 01:49:30 PM PDT 24 1555490000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1398315720 Jun 11 01:49:35 PM PDT 24 Jun 11 01:49:47 PM PDT 24 1523430000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2973536275 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:49 PM PDT 24 1531290000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3475322304 Jun 11 01:49:30 PM PDT 24 Jun 11 01:49:40 PM PDT 24 1470450000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1803488700 Jun 11 01:49:41 PM PDT 24 Jun 11 01:49:52 PM PDT 24 1414750000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1844510777 Jun 11 01:49:37 PM PDT 24 Jun 11 01:49:48 PM PDT 24 1536830000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1577185959 Jun 11 01:08:03 PM PDT 24 Jun 11 01:38:29 PM PDT 24 336668950000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1502949757 Jun 11 01:08:16 PM PDT 24 Jun 11 01:43:37 PM PDT 24 336536070000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.880758755 Jun 11 01:08:17 PM PDT 24 Jun 11 01:42:16 PM PDT 24 336831690000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1225084578 Jun 11 01:08:15 PM PDT 24 Jun 11 01:40:58 PM PDT 24 336625750000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1388709727 Jun 11 01:08:04 PM PDT 24 Jun 11 01:38:18 PM PDT 24 336589890000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.239239099 Jun 11 01:08:18 PM PDT 24 Jun 11 01:40:43 PM PDT 24 337010830000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.38375060 Jun 11 01:08:04 PM PDT 24 Jun 11 01:39:40 PM PDT 24 336818710000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.973389279 Jun 11 01:08:30 PM PDT 24 Jun 11 01:43:46 PM PDT 24 336702150000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.472889088 Jun 11 01:08:16 PM PDT 24 Jun 11 01:36:11 PM PDT 24 336388070000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.171882496 Jun 11 01:08:17 PM PDT 24 Jun 11 01:41:49 PM PDT 24 336960090000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4066806933 Jun 11 01:08:04 PM PDT 24 Jun 11 01:42:20 PM PDT 24 336761930000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2171480675 Jun 11 01:08:06 PM PDT 24 Jun 11 01:42:04 PM PDT 24 336343150000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2847337107 Jun 11 01:08:16 PM PDT 24 Jun 11 01:41:55 PM PDT 24 336873850000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3947572034 Jun 11 01:08:18 PM PDT 24 Jun 11 01:38:45 PM PDT 24 336998590000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2343811400 Jun 11 01:08:16 PM PDT 24 Jun 11 01:38:52 PM PDT 24 336579070000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1119016616 Jun 11 01:08:28 PM PDT 24 Jun 11 01:39:57 PM PDT 24 336962110000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2573935896 Jun 11 01:08:14 PM PDT 24 Jun 11 01:38:45 PM PDT 24 336533490000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2343375801 Jun 11 01:08:05 PM PDT 24 Jun 11 01:41:31 PM PDT 24 336587610000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3028045271 Jun 11 01:08:17 PM PDT 24 Jun 11 01:42:39 PM PDT 24 336992310000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.223756999 Jun 11 01:08:14 PM PDT 24 Jun 11 01:42:47 PM PDT 24 336769950000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2889282220 Jun 11 01:08:04 PM PDT 24 Jun 11 01:37:20 PM PDT 24 336921010000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1244623716 Jun 11 01:08:18 PM PDT 24 Jun 11 01:41:28 PM PDT 24 336413750000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2344006839 Jun 11 01:08:17 PM PDT 24 Jun 11 01:41:41 PM PDT 24 336434970000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2624020600 Jun 11 01:08:05 PM PDT 24 Jun 11 01:36:50 PM PDT 24 336361150000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4111134231 Jun 11 01:08:14 PM PDT 24 Jun 11 01:34:05 PM PDT 24 336973230000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2730730081 Jun 11 01:08:29 PM PDT 24 Jun 11 01:42:31 PM PDT 24 337061170000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1291295266 Jun 11 01:08:15 PM PDT 24 Jun 11 01:40:03 PM PDT 24 336826390000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2086753227 Jun 11 01:08:18 PM PDT 24 Jun 11 01:40:39 PM PDT 24 336443870000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.418196686 Jun 11 01:08:16 PM PDT 24 Jun 11 01:41:41 PM PDT 24 336989890000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1232789425 Jun 11 01:08:14 PM PDT 24 Jun 11 01:40:04 PM PDT 24 336675110000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1291894637 Jun 11 01:08:06 PM PDT 24 Jun 11 01:40:26 PM PDT 24 336638770000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.763175659 Jun 11 01:08:04 PM PDT 24 Jun 11 01:42:24 PM PDT 24 336408950000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3802783767 Jun 11 01:08:14 PM PDT 24 Jun 11 01:38:50 PM PDT 24 336588910000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2817821834 Jun 11 01:08:18 PM PDT 24 Jun 11 01:41:33 PM PDT 24 337003370000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3481200324 Jun 11 01:08:04 PM PDT 24 Jun 11 01:40:32 PM PDT 24 336562130000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1028324315 Jun 11 01:08:17 PM PDT 24 Jun 11 01:41:39 PM PDT 24 337136510000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3201755140 Jun 11 01:08:15 PM PDT 24 Jun 11 01:39:58 PM PDT 24 336874790000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.854030831 Jun 11 01:08:15 PM PDT 24 Jun 11 01:41:12 PM PDT 24 336465670000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.921189485 Jun 11 01:08:04 PM PDT 24 Jun 11 01:43:28 PM PDT 24 336446430000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1109907717 Jun 11 01:08:05 PM PDT 24 Jun 11 01:39:10 PM PDT 24 336556930000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4249709860 Jun 11 01:08:16 PM PDT 24 Jun 11 01:38:41 PM PDT 24 336369750000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1995196823 Jun 11 01:08:18 PM PDT 24 Jun 11 01:40:31 PM PDT 24 336826870000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1691666310 Jun 11 01:08:16 PM PDT 24 Jun 11 01:43:00 PM PDT 24 336664350000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1228549757 Jun 11 01:08:03 PM PDT 24 Jun 11 01:40:21 PM PDT 24 337070990000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3302486718 Jun 11 01:08:16 PM PDT 24 Jun 11 01:42:40 PM PDT 24 336481410000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3680972599 Jun 11 01:08:02 PM PDT 24 Jun 11 01:36:51 PM PDT 24 336597970000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1862046385 Jun 11 01:08:16 PM PDT 24 Jun 11 01:36:01 PM PDT 24 336436650000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.409241565 Jun 11 01:08:05 PM PDT 24 Jun 11 01:43:10 PM PDT 24 337095990000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.774489116 Jun 11 01:08:05 PM PDT 24 Jun 11 01:40:04 PM PDT 24 336426190000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2963096732 Jun 11 01:08:15 PM PDT 24 Jun 11 01:38:52 PM PDT 24 337002610000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.104882641 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:28 PM PDT 24 1581730000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2623378353 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:25 PM PDT 24 1524230000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1530727513 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1368390000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.512380963 Jun 11 02:46:15 PM PDT 24 Jun 11 02:46:27 PM PDT 24 1556970000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3442742648 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:31 PM PDT 24 992810000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1747214406 Jun 11 02:46:15 PM PDT 24 Jun 11 02:46:27 PM PDT 24 1382650000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1703337513 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:34 PM PDT 24 1527190000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4021152203 Jun 11 02:46:12 PM PDT 24 Jun 11 02:46:24 PM PDT 24 1462050000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.323745361 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:25 PM PDT 24 1359510000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.718879279 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1431630000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3013997553 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1425170000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1077896670 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:25 PM PDT 24 1565090000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2922447734 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:32 PM PDT 24 1506290000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2788726082 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:25 PM PDT 24 1366730000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.129085394 Jun 11 02:46:15 PM PDT 24 Jun 11 02:46:26 PM PDT 24 1520510000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2874776966 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1451590000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2716395516 Jun 11 02:46:15 PM PDT 24 Jun 11 02:46:26 PM PDT 24 1448170000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.324961439 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1361970000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2419869583 Jun 11 02:46:12 PM PDT 24 Jun 11 02:46:22 PM PDT 24 1458170000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2338766721 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:22 PM PDT 24 1206830000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.695608259 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:31 PM PDT 24 1280070000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4225090239 Jun 11 02:46:12 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1216990000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2648204 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:34 PM PDT 24 1611810000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3193267266 Jun 11 02:46:20 PM PDT 24 Jun 11 02:46:31 PM PDT 24 1539790000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2899420400 Jun 11 02:46:20 PM PDT 24 Jun 11 02:46:30 PM PDT 24 1422250000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3565958932 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:33 PM PDT 24 1518810000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3919532838 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:26 PM PDT 24 1403270000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.190968482 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:24 PM PDT 24 1491790000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.867610033 Jun 11 02:46:16 PM PDT 24 Jun 11 02:46:27 PM PDT 24 1558210000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3760136549 Jun 11 02:46:11 PM PDT 24 Jun 11 02:46:21 PM PDT 24 1448330000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1109416247 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1305470000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2217068720 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:33 PM PDT 24 1467250000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.33704015 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1477970000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3511899924 Jun 11 02:46:11 PM PDT 24 Jun 11 02:46:22 PM PDT 24 1431590000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.127390246 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:25 PM PDT 24 1477650000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1373643564 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:26 PM PDT 24 1505730000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4218802886 Jun 11 02:46:17 PM PDT 24 Jun 11 02:46:26 PM PDT 24 1479210000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.976332351 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:22 PM PDT 24 1433610000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4256013167 Jun 11 02:46:13 PM PDT 24 Jun 11 02:46:24 PM PDT 24 1520330000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2438322883 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:31 PM PDT 24 1063670000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3047666646 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:34 PM PDT 24 1579130000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.645360773 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1061630000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4068986785 Jun 11 02:46:11 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1490950000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1586358378 Jun 11 02:46:11 PM PDT 24 Jun 11 02:46:23 PM PDT 24 1538070000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.726209798 Jun 11 02:46:21 PM PDT 24 Jun 11 02:46:32 PM PDT 24 1526810000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1750844578 Jun 11 02:46:11 PM PDT 24 Jun 11 02:46:20 PM PDT 24 1258570000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2211175533 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:25 PM PDT 24 1511330000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2481529935 Jun 11 02:46:14 PM PDT 24 Jun 11 02:46:24 PM PDT 24 1213510000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3745643298 Jun 11 02:46:16 PM PDT 24 Jun 11 02:46:29 PM PDT 24 1600730000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1691696760 Jun 11 02:46:16 PM PDT 24 Jun 11 02:46:29 PM PDT 24 1583790000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.73797355 Jun 11 01:55:13 PM PDT 24 Jun 11 02:21:55 PM PDT 24 336661390000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2691710091 Jun 11 01:55:14 PM PDT 24 Jun 11 02:27:24 PM PDT 24 336929770000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2985163519 Jun 11 01:55:14 PM PDT 24 Jun 11 02:24:13 PM PDT 24 336790010000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1304965279 Jun 11 01:55:11 PM PDT 24 Jun 11 02:23:49 PM PDT 24 337018170000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4208325140 Jun 11 01:55:14 PM PDT 24 Jun 11 02:28:33 PM PDT 24 336579630000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.317880678 Jun 11 01:55:14 PM PDT 24 Jun 11 02:25:33 PM PDT 24 336635210000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1684487999 Jun 11 01:55:13 PM PDT 24 Jun 11 02:26:11 PM PDT 24 336410410000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1945748712 Jun 11 01:55:11 PM PDT 24 Jun 11 02:25:36 PM PDT 24 337071130000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.793120492 Jun 11 01:55:14 PM PDT 24 Jun 11 02:25:47 PM PDT 24 337002650000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1168695140 Jun 11 01:55:15 PM PDT 24 Jun 11 02:26:54 PM PDT 24 337101570000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.663525099 Jun 11 01:55:12 PM PDT 24 Jun 11 02:25:23 PM PDT 24 336478090000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1391195500 Jun 11 01:55:12 PM PDT 24 Jun 11 02:23:45 PM PDT 24 336931370000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.905652123 Jun 11 01:55:17 PM PDT 24 Jun 11 02:28:24 PM PDT 24 337091390000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2753101576 Jun 11 01:55:12 PM PDT 24 Jun 11 02:25:02 PM PDT 24 336555570000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1096910711 Jun 11 01:55:11 PM PDT 24 Jun 11 02:21:28 PM PDT 24 336994690000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1129997004 Jun 11 01:55:12 PM PDT 24 Jun 11 02:24:51 PM PDT 24 336377870000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1847161118 Jun 11 01:55:15 PM PDT 24 Jun 11 02:24:09 PM PDT 24 336400830000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4258784776 Jun 11 01:55:14 PM PDT 24 Jun 11 02:24:48 PM PDT 24 336482190000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3374922871 Jun 11 01:55:14 PM PDT 24 Jun 11 02:27:07 PM PDT 24 336416490000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.469411956 Jun 11 01:55:11 PM PDT 24 Jun 11 02:23:53 PM PDT 24 336885710000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3243734081 Jun 11 01:55:12 PM PDT 24 Jun 11 02:25:57 PM PDT 24 336930930000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4035238509 Jun 11 01:55:16 PM PDT 24 Jun 11 02:27:08 PM PDT 24 336692790000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3317903118 Jun 11 01:55:13 PM PDT 24 Jun 11 02:25:58 PM PDT 24 336401150000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3117641252 Jun 11 01:55:16 PM PDT 24 Jun 11 02:23:31 PM PDT 24 336474590000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2234172019 Jun 11 01:55:26 PM PDT 24 Jun 11 02:26:29 PM PDT 24 336848250000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.5538970 Jun 11 01:55:13 PM PDT 24 Jun 11 02:23:35 PM PDT 24 336471110000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4291163006 Jun 11 01:55:15 PM PDT 24 Jun 11 02:27:12 PM PDT 24 336608190000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.8129137 Jun 11 01:55:12 PM PDT 24 Jun 11 02:25:00 PM PDT 24 336712410000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.49624402 Jun 11 01:55:13 PM PDT 24 Jun 11 02:21:51 PM PDT 24 336579090000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1193999648 Jun 11 01:55:16 PM PDT 24 Jun 11 02:28:16 PM PDT 24 336343210000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3353268323 Jun 11 01:55:14 PM PDT 24 Jun 11 02:23:31 PM PDT 24 336899810000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3676319700 Jun 11 01:55:13 PM PDT 24 Jun 11 02:24:17 PM PDT 24 336972970000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2742128577 Jun 11 01:55:11 PM PDT 24 Jun 11 02:25:37 PM PDT 24 336330950000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2225208254 Jun 11 01:55:15 PM PDT 24 Jun 11 02:24:21 PM PDT 24 336907350000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.785981933 Jun 11 01:55:13 PM PDT 24 Jun 11 02:28:35 PM PDT 24 336764390000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2572744114 Jun 11 01:55:14 PM PDT 24 Jun 11 02:28:42 PM PDT 24 336737190000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2862638793 Jun 11 01:55:12 PM PDT 24 Jun 11 02:24:45 PM PDT 24 336806810000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.229034537 Jun 11 01:55:12 PM PDT 24 Jun 11 02:24:24 PM PDT 24 336937150000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4149284094 Jun 11 01:55:14 PM PDT 24 Jun 11 02:25:12 PM PDT 24 336575910000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2721300381 Jun 11 01:55:11 PM PDT 24 Jun 11 02:25:21 PM PDT 24 336890250000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.328158757 Jun 11 01:55:10 PM PDT 24 Jun 11 02:25:11 PM PDT 24 336775990000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4192598295 Jun 11 01:55:14 PM PDT 24 Jun 11 02:24:37 PM PDT 24 336841970000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.724338988 Jun 11 01:55:15 PM PDT 24 Jun 11 02:24:33 PM PDT 24 337016630000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3897860352 Jun 11 01:55:16 PM PDT 24 Jun 11 02:27:17 PM PDT 24 337101870000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3655543439 Jun 11 01:55:15 PM PDT 24 Jun 11 02:28:20 PM PDT 24 337099910000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1670037768 Jun 11 01:55:12 PM PDT 24 Jun 11 02:24:57 PM PDT 24 336702230000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3043357903 Jun 11 01:55:14 PM PDT 24 Jun 11 02:27:08 PM PDT 24 336650350000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3372342166 Jun 11 01:55:13 PM PDT 24 Jun 11 02:24:15 PM PDT 24 336442230000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2007251225 Jun 11 01:55:13 PM PDT 24 Jun 11 02:23:52 PM PDT 24 336887610000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1585217079 Jun 11 01:55:11 PM PDT 24 Jun 11 02:25:43 PM PDT 24 336581470000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3583405218
Short name T11
Test name
Test status
Simulation time 1513070000 ps
CPU time 4.47 seconds
Started Jun 11 01:49:46 PM PDT 24
Finished Jun 11 01:49:56 PM PDT 24
Peak memory 164872 kb
Host smart-1a9a55c0-cf9c-4fca-9cdf-21cd3973f4e5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3583405218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3583405218
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1388709727
Short name T15
Test name
Test status
Simulation time 336589890000 ps
CPU time 740.17 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:38:18 PM PDT 24
Peak memory 160808 kb
Host smart-19fecf5d-3b2a-4bd0-9e28-e866ad9b14b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1388709727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1388709727
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.73797355
Short name T21
Test name
Test status
Simulation time 336661390000 ps
CPU time 655.73 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:21:55 PM PDT 24
Peak memory 160700 kb
Host smart-d2a44e18-818f-49f7-bb72-55d0e6f30912
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=73797355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.73797355
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3680972599
Short name T106
Test name
Test status
Simulation time 336597970000 ps
CPU time 705.4 seconds
Started Jun 11 01:08:02 PM PDT 24
Finished Jun 11 01:36:51 PM PDT 24
Peak memory 160808 kb
Host smart-f1869d09-a657-4532-959d-bfbd6694408d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3680972599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3680972599
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.763175659
Short name T92
Test name
Test status
Simulation time 336408950000 ps
CPU time 849.81 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:42:24 PM PDT 24
Peak memory 160776 kb
Host smart-d0b98d29-8c1c-44bf-9ff7-15246152af4f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=763175659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.763175659
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4066806933
Short name T71
Test name
Test status
Simulation time 336761930000 ps
CPU time 865.89 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:42:20 PM PDT 24
Peak memory 160716 kb
Host smart-f12273e5-3bb2-4983-af34-4fd37a7b756c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4066806933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.4066806933
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1577185959
Short name T5
Test name
Test status
Simulation time 336668950000 ps
CPU time 749.93 seconds
Started Jun 11 01:08:03 PM PDT 24
Finished Jun 11 01:38:29 PM PDT 24
Peak memory 160816 kb
Host smart-cecdeaef-f7cd-4e83-a667-ff8cf5de7087
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1577185959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1577185959
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.921189485
Short name T99
Test name
Test status
Simulation time 336446430000 ps
CPU time 846.12 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:43:28 PM PDT 24
Peak memory 160800 kb
Host smart-f5de78d5-01ef-4a36-bac4-108ec786a166
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=921189485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.921189485
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2889282220
Short name T81
Test name
Test status
Simulation time 336921010000 ps
CPU time 721.62 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:37:20 PM PDT 24
Peak memory 160780 kb
Host smart-e8c48927-3735-4d2f-8767-ee1047d015c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2889282220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2889282220
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.774489116
Short name T109
Test name
Test status
Simulation time 336426190000 ps
CPU time 796.96 seconds
Started Jun 11 01:08:05 PM PDT 24
Finished Jun 11 01:40:04 PM PDT 24
Peak memory 160800 kb
Host smart-a3aad38b-0a49-4306-8e6c-b5150c173d23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=774489116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.774489116
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2343375801
Short name T78
Test name
Test status
Simulation time 336587610000 ps
CPU time 830.67 seconds
Started Jun 11 01:08:05 PM PDT 24
Finished Jun 11 01:41:31 PM PDT 24
Peak memory 160796 kb
Host smart-081cd053-8435-44e9-b316-1aa7c897d4c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2343375801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2343375801
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.4111134231
Short name T85
Test name
Test status
Simulation time 336973230000 ps
CPU time 624.51 seconds
Started Jun 11 01:08:14 PM PDT 24
Finished Jun 11 01:34:05 PM PDT 24
Peak memory 160828 kb
Host smart-bfa018f6-390b-4534-b14c-fe659d41c7c3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4111134231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.4111134231
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1291295266
Short name T87
Test name
Test status
Simulation time 336826390000 ps
CPU time 791.6 seconds
Started Jun 11 01:08:15 PM PDT 24
Finished Jun 11 01:40:03 PM PDT 24
Peak memory 160812 kb
Host smart-a79c582a-0a5c-4dc5-bd6b-68852bb3a90e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1291295266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1291295266
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1691666310
Short name T103
Test name
Test status
Simulation time 336664350000 ps
CPU time 855.63 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:43:00 PM PDT 24
Peak memory 160720 kb
Host smart-71301597-7e6f-4be5-8b94-a06e2bd42b55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1691666310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1691666310
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1109907717
Short name T100
Test name
Test status
Simulation time 336556930000 ps
CPU time 757.01 seconds
Started Jun 11 01:08:05 PM PDT 24
Finished Jun 11 01:39:10 PM PDT 24
Peak memory 160804 kb
Host smart-35fea9e0-f002-4490-b63f-1834791ca0bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1109907717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1109907717
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.472889088
Short name T19
Test name
Test status
Simulation time 336388070000 ps
CPU time 680.37 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:36:11 PM PDT 24
Peak memory 160816 kb
Host smart-10944624-b3a4-4aa1-a762-c3964a0805b6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=472889088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.472889088
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1232789425
Short name T90
Test name
Test status
Simulation time 336675110000 ps
CPU time 777.45 seconds
Started Jun 11 01:08:14 PM PDT 24
Finished Jun 11 01:40:04 PM PDT 24
Peak memory 160832 kb
Host smart-49236938-332e-4ec8-8774-4f25f1efe134
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1232789425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1232789425
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.880758755
Short name T7
Test name
Test status
Simulation time 336831690000 ps
CPU time 816.54 seconds
Started Jun 11 01:08:17 PM PDT 24
Finished Jun 11 01:42:16 PM PDT 24
Peak memory 160792 kb
Host smart-986b87b2-5b6c-4c64-9bc9-c7b60a7ae364
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=880758755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.880758755
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1244623716
Short name T82
Test name
Test status
Simulation time 336413750000 ps
CPU time 811.44 seconds
Started Jun 11 01:08:18 PM PDT 24
Finished Jun 11 01:41:28 PM PDT 24
Peak memory 160824 kb
Host smart-97fce9a9-8b74-40c1-8cdc-7585ca707aa1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1244623716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1244623716
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.171882496
Short name T20
Test name
Test status
Simulation time 336960090000 ps
CPU time 810.87 seconds
Started Jun 11 01:08:17 PM PDT 24
Finished Jun 11 01:41:49 PM PDT 24
Peak memory 160824 kb
Host smart-fea6ccd1-6c01-4c29-bd99-b00f0d07e909
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=171882496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.171882496
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1028324315
Short name T96
Test name
Test status
Simulation time 337136510000 ps
CPU time 803.73 seconds
Started Jun 11 01:08:17 PM PDT 24
Finished Jun 11 01:41:39 PM PDT 24
Peak memory 160828 kb
Host smart-0c2c2c75-3054-4908-8fc8-c1518239daa9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1028324315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1028324315
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.223756999
Short name T80
Test name
Test status
Simulation time 336769950000 ps
CPU time 842.69 seconds
Started Jun 11 01:08:14 PM PDT 24
Finished Jun 11 01:42:47 PM PDT 24
Peak memory 160800 kb
Host smart-a3b3670e-f6eb-4fbf-882c-50a9a3088e21
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=223756999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.223756999
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2086753227
Short name T88
Test name
Test status
Simulation time 336443870000 ps
CPU time 787.52 seconds
Started Jun 11 01:08:18 PM PDT 24
Finished Jun 11 01:40:39 PM PDT 24
Peak memory 160792 kb
Host smart-2381df1e-0fbf-4d3d-acd8-60715ef4effc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2086753227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2086753227
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3302486718
Short name T105
Test name
Test status
Simulation time 336481410000 ps
CPU time 844.04 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:42:40 PM PDT 24
Peak memory 160720 kb
Host smart-e2c3da6f-00e1-4a5a-b829-2c15e458d644
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3302486718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3302486718
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.418196686
Short name T89
Test name
Test status
Simulation time 336989890000 ps
CPU time 806.56 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:41:41 PM PDT 24
Peak memory 160820 kb
Host smart-025e9979-03f1-4851-a4ed-976d1eaa443e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=418196686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.418196686
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2624020600
Short name T84
Test name
Test status
Simulation time 336361150000 ps
CPU time 705.33 seconds
Started Jun 11 01:08:05 PM PDT 24
Finished Jun 11 01:36:50 PM PDT 24
Peak memory 160824 kb
Host smart-e12c3d87-be1b-42ad-853d-5e54ae7881cf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2624020600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2624020600
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2847337107
Short name T73
Test name
Test status
Simulation time 336873850000 ps
CPU time 812.94 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:41:55 PM PDT 24
Peak memory 160688 kb
Host smart-cd8dc4f2-bcec-4ce7-afd3-73676ddf5c7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2847337107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2847337107
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3028045271
Short name T79
Test name
Test status
Simulation time 336992310000 ps
CPU time 839.21 seconds
Started Jun 11 01:08:17 PM PDT 24
Finished Jun 11 01:42:39 PM PDT 24
Peak memory 160796 kb
Host smart-f598d0f3-03de-43ce-936c-dba7192d8727
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3028045271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3028045271
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4249709860
Short name T101
Test name
Test status
Simulation time 336369750000 ps
CPU time 750.21 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:38:41 PM PDT 24
Peak memory 160816 kb
Host smart-176bfdda-e98f-4afe-aea2-4baf4442ef47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4249709860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4249709860
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2573935896
Short name T77
Test name
Test status
Simulation time 336533490000 ps
CPU time 744.32 seconds
Started Jun 11 01:08:14 PM PDT 24
Finished Jun 11 01:38:45 PM PDT 24
Peak memory 160812 kb
Host smart-e6d54c67-9f3f-44f1-8f17-d9467101327a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2573935896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2573935896
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.239239099
Short name T16
Test name
Test status
Simulation time 337010830000 ps
CPU time 783.22 seconds
Started Jun 11 01:08:18 PM PDT 24
Finished Jun 11 01:40:43 PM PDT 24
Peak memory 160788 kb
Host smart-127184ac-6e57-4a9d-a026-4cfb172137e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=239239099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.239239099
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1502949757
Short name T6
Test name
Test status
Simulation time 336536070000 ps
CPU time 842.89 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:43:37 PM PDT 24
Peak memory 160804 kb
Host smart-be5d6ebd-9e29-45d6-83a0-4a32f8fb201f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1502949757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1502949757
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1862046385
Short name T107
Test name
Test status
Simulation time 336436650000 ps
CPU time 672.48 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:36:01 PM PDT 24
Peak memory 160820 kb
Host smart-01eb1c46-6ca9-4892-a575-c05adbd0fd11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1862046385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1862046385
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3802783767
Short name T93
Test name
Test status
Simulation time 336588910000 ps
CPU time 752.18 seconds
Started Jun 11 01:08:14 PM PDT 24
Finished Jun 11 01:38:50 PM PDT 24
Peak memory 160684 kb
Host smart-9656f31b-6008-49ec-9ebc-da6d14dc3af7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3802783767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3802783767
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2963096732
Short name T110
Test name
Test status
Simulation time 337002610000 ps
CPU time 739.26 seconds
Started Jun 11 01:08:15 PM PDT 24
Finished Jun 11 01:38:52 PM PDT 24
Peak memory 160812 kb
Host smart-51456a55-327f-408a-adcd-1b97c58e6ca7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963096732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2963096732
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1995196823
Short name T102
Test name
Test status
Simulation time 336826870000 ps
CPU time 785.26 seconds
Started Jun 11 01:08:18 PM PDT 24
Finished Jun 11 01:40:31 PM PDT 24
Peak memory 160792 kb
Host smart-45528c2e-b3a6-46ec-b27e-4347ab246d24
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1995196823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1995196823
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.409241565
Short name T108
Test name
Test status
Simulation time 337095990000 ps
CPU time 848.2 seconds
Started Jun 11 01:08:05 PM PDT 24
Finished Jun 11 01:43:10 PM PDT 24
Peak memory 160780 kb
Host smart-e37dbad8-f62c-4020-a7c1-a75f811c9521
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=409241565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.409241565
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1225084578
Short name T14
Test name
Test status
Simulation time 336625750000 ps
CPU time 794.73 seconds
Started Jun 11 01:08:15 PM PDT 24
Finished Jun 11 01:40:58 PM PDT 24
Peak memory 160792 kb
Host smart-71d90aa5-38ed-4760-85ae-837c0ee53a69
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1225084578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1225084578
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3947572034
Short name T74
Test name
Test status
Simulation time 336998590000 ps
CPU time 727.44 seconds
Started Jun 11 01:08:18 PM PDT 24
Finished Jun 11 01:38:45 PM PDT 24
Peak memory 160800 kb
Host smart-2d517584-9f02-4990-a152-39abe530b6f9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3947572034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.3947572034
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2344006839
Short name T83
Test name
Test status
Simulation time 336434970000 ps
CPU time 802.96 seconds
Started Jun 11 01:08:17 PM PDT 24
Finished Jun 11 01:41:41 PM PDT 24
Peak memory 160688 kb
Host smart-9b56229c-a33c-4f8b-b270-468d5455eb94
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2344006839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2344006839
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2817821834
Short name T94
Test name
Test status
Simulation time 337003370000 ps
CPU time 811.25 seconds
Started Jun 11 01:08:18 PM PDT 24
Finished Jun 11 01:41:33 PM PDT 24
Peak memory 160824 kb
Host smart-816f324c-8565-4b10-9db9-a0ed6ca98b28
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2817821834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2817821834
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3201755140
Short name T97
Test name
Test status
Simulation time 336874790000 ps
CPU time 786.28 seconds
Started Jun 11 01:08:15 PM PDT 24
Finished Jun 11 01:39:58 PM PDT 24
Peak memory 160788 kb
Host smart-6707eb68-1f12-4fee-81d8-f14034d30b33
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3201755140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3201755140
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2343811400
Short name T75
Test name
Test status
Simulation time 336579070000 ps
CPU time 732.79 seconds
Started Jun 11 01:08:16 PM PDT 24
Finished Jun 11 01:38:52 PM PDT 24
Peak memory 160800 kb
Host smart-84e98d09-3cd1-4d03-97fe-d8948c74e954
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2343811400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2343811400
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.854030831
Short name T98
Test name
Test status
Simulation time 336465670000 ps
CPU time 799.8 seconds
Started Jun 11 01:08:15 PM PDT 24
Finished Jun 11 01:41:12 PM PDT 24
Peak memory 160788 kb
Host smart-97f80e35-7f3b-4324-b6c0-aac1eb9a5c4e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=854030831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.854030831
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2730730081
Short name T86
Test name
Test status
Simulation time 337061170000 ps
CPU time 819.99 seconds
Started Jun 11 01:08:29 PM PDT 24
Finished Jun 11 01:42:31 PM PDT 24
Peak memory 160808 kb
Host smart-136a40c2-11d6-4336-80b1-956a77166dcb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2730730081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2730730081
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1119016616
Short name T76
Test name
Test status
Simulation time 336962110000 ps
CPU time 764.59 seconds
Started Jun 11 01:08:28 PM PDT 24
Finished Jun 11 01:39:57 PM PDT 24
Peak memory 160832 kb
Host smart-e8c3859f-5869-4229-8c09-d8ce270a8c47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1119016616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1119016616
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.973389279
Short name T18
Test name
Test status
Simulation time 336702150000 ps
CPU time 840.44 seconds
Started Jun 11 01:08:30 PM PDT 24
Finished Jun 11 01:43:46 PM PDT 24
Peak memory 160800 kb
Host smart-6b1a270d-35d3-402e-b468-ebebd385e5ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=973389279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.973389279
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.38375060
Short name T17
Test name
Test status
Simulation time 336818710000 ps
CPU time 792.1 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:39:40 PM PDT 24
Peak memory 160744 kb
Host smart-7ba9f88f-f5d8-41b3-a2b1-c24a0f53c43e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=38375060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.38375060
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3481200324
Short name T95
Test name
Test status
Simulation time 336562130000 ps
CPU time 799.14 seconds
Started Jun 11 01:08:04 PM PDT 24
Finished Jun 11 01:40:32 PM PDT 24
Peak memory 160784 kb
Host smart-ea9e5863-db0d-4c6d-8f76-f24d547a4801
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3481200324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3481200324
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1291894637
Short name T91
Test name
Test status
Simulation time 336638770000 ps
CPU time 799.89 seconds
Started Jun 11 01:08:06 PM PDT 24
Finished Jun 11 01:40:26 PM PDT 24
Peak memory 160764 kb
Host smart-ace0bd44-f89d-4f61-8005-ccd0f0683c5e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1291894637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1291894637
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2171480675
Short name T72
Test name
Test status
Simulation time 336343150000 ps
CPU time 843.15 seconds
Started Jun 11 01:08:06 PM PDT 24
Finished Jun 11 01:42:04 PM PDT 24
Peak memory 160736 kb
Host smart-64e3a315-24d9-4ac7-967a-36205ea8241e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2171480675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2171480675
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1228549757
Short name T104
Test name
Test status
Simulation time 337070990000 ps
CPU time 793.94 seconds
Started Jun 11 01:08:03 PM PDT 24
Finished Jun 11 01:40:21 PM PDT 24
Peak memory 160780 kb
Host smart-9ad50b40-9722-4a2d-8ce1-db570b441b9a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1228549757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1228549757
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3897860352
Short name T194
Test name
Test status
Simulation time 337101870000 ps
CPU time 780.49 seconds
Started Jun 11 01:55:16 PM PDT 24
Finished Jun 11 02:27:17 PM PDT 24
Peak memory 160824 kb
Host smart-09406ec0-c599-46c8-ace4-7250f6010215
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3897860352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3897860352
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2742128577
Short name T183
Test name
Test status
Simulation time 336330950000 ps
CPU time 747.78 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:25:37 PM PDT 24
Peak memory 160768 kb
Host smart-218a4fea-59fd-4964-a261-f353264d9f13
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2742128577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2742128577
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.328158757
Short name T191
Test name
Test status
Simulation time 336775990000 ps
CPU time 738.33 seconds
Started Jun 11 01:55:10 PM PDT 24
Finished Jun 11 02:25:11 PM PDT 24
Peak memory 160800 kb
Host smart-8fc8eca3-8e32-42bd-8d72-0f8e2f859b70
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=328158757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.328158757
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1391195500
Short name T162
Test name
Test status
Simulation time 336931370000 ps
CPU time 701.74 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:23:45 PM PDT 24
Peak memory 160800 kb
Host smart-41cc23eb-3153-48cb-8524-729886ed4ea2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1391195500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1391195500
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4035238509
Short name T172
Test name
Test status
Simulation time 336692790000 ps
CPU time 774.08 seconds
Started Jun 11 01:55:16 PM PDT 24
Finished Jun 11 02:27:08 PM PDT 24
Peak memory 160832 kb
Host smart-8292ed20-d3a2-42ee-b687-edda2a156ffc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4035238509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4035238509
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2862638793
Short name T187
Test name
Test status
Simulation time 336806810000 ps
CPU time 726.57 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:24:45 PM PDT 24
Peak memory 160724 kb
Host smart-f3973fe7-bb5d-4414-8013-dc7ea99f8603
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2862638793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2862638793
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2225208254
Short name T184
Test name
Test status
Simulation time 336907350000 ps
CPU time 715.8 seconds
Started Jun 11 01:55:15 PM PDT 24
Finished Jun 11 02:24:21 PM PDT 24
Peak memory 160776 kb
Host smart-c90c8e5c-e3b8-407d-81c8-1cb715fff9c4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2225208254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2225208254
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1304965279
Short name T24
Test name
Test status
Simulation time 337018170000 ps
CPU time 694.59 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:23:49 PM PDT 24
Peak memory 160816 kb
Host smart-41e38b31-a6ab-48e2-85e9-9e3f792e2849
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1304965279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1304965279
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3353268323
Short name T181
Test name
Test status
Simulation time 336899810000 ps
CPU time 689.14 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:23:31 PM PDT 24
Peak memory 160836 kb
Host smart-f6a4d9e7-6e0d-4b5d-8e71-28b29b25193a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3353268323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3353268323
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3317903118
Short name T173
Test name
Test status
Simulation time 336401150000 ps
CPU time 757.19 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:25:58 PM PDT 24
Peak memory 160808 kb
Host smart-9ae898d0-b5d1-425e-8b4a-55a4ee267663
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3317903118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3317903118
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2753101576
Short name T164
Test name
Test status
Simulation time 336555570000 ps
CPU time 734.8 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:25:02 PM PDT 24
Peak memory 160740 kb
Host smart-8fa68150-7b55-4e73-8248-1a37d75771d8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2753101576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2753101576
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3243734081
Short name T171
Test name
Test status
Simulation time 336930930000 ps
CPU time 760.1 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:25:57 PM PDT 24
Peak memory 160872 kb
Host smart-a8f941c1-22e9-4488-a8da-f8333046bb00
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3243734081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3243734081
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1585217079
Short name T200
Test name
Test status
Simulation time 336581470000 ps
CPU time 741.99 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:25:43 PM PDT 24
Peak memory 160808 kb
Host smart-509f6ab6-622b-4011-9c8b-6d8c328409de
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1585217079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1585217079
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.229034537
Short name T188
Test name
Test status
Simulation time 336937150000 ps
CPU time 709.64 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:24:24 PM PDT 24
Peak memory 160788 kb
Host smart-db66b61b-5674-402e-b4ba-532983bfd3a5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=229034537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.229034537
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1847161118
Short name T167
Test name
Test status
Simulation time 336400830000 ps
CPU time 705.66 seconds
Started Jun 11 01:55:15 PM PDT 24
Finished Jun 11 02:24:09 PM PDT 24
Peak memory 160772 kb
Host smart-050c0692-daad-4c6c-992e-14a7c5f0a99e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1847161118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1847161118
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1193999648
Short name T180
Test name
Test status
Simulation time 336343210000 ps
CPU time 804.27 seconds
Started Jun 11 01:55:16 PM PDT 24
Finished Jun 11 02:28:16 PM PDT 24
Peak memory 160832 kb
Host smart-2826629c-9428-45a7-b363-d8f8eaae1839
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1193999648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1193999648
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2691710091
Short name T22
Test name
Test status
Simulation time 336929770000 ps
CPU time 788.55 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:27:24 PM PDT 24
Peak memory 160796 kb
Host smart-877fcbfa-8e8d-4cff-8a6a-6dd3ef01e178
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2691710091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2691710091
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.469411956
Short name T170
Test name
Test status
Simulation time 336885710000 ps
CPU time 697.66 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:23:53 PM PDT 24
Peak memory 160720 kb
Host smart-91cc7ce0-ff27-44af-9d00-219c531816c2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=469411956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.469411956
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3372342166
Short name T198
Test name
Test status
Simulation time 336442230000 ps
CPU time 715.14 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:24:15 PM PDT 24
Peak memory 160820 kb
Host smart-209f04d5-049d-47bd-8d5e-602d93bdf3ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3372342166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3372342166
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1684487999
Short name T27
Test name
Test status
Simulation time 336410410000 ps
CPU time 765.84 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:26:11 PM PDT 24
Peak memory 160804 kb
Host smart-f132a154-da4b-42ea-a513-dd3f7bc5ac6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1684487999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1684487999
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4258784776
Short name T168
Test name
Test status
Simulation time 336482190000 ps
CPU time 719.97 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:24:48 PM PDT 24
Peak memory 160820 kb
Host smart-da72d258-a82b-4abf-8779-fec23b47f3cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4258784776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.4258784776
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.793120492
Short name T29
Test name
Test status
Simulation time 337002650000 ps
CPU time 753.08 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:25:47 PM PDT 24
Peak memory 160724 kb
Host smart-bc750111-3cec-4208-ac57-79269a6b3947
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=793120492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.793120492
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1096910711
Short name T165
Test name
Test status
Simulation time 336994690000 ps
CPU time 643.41 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:21:28 PM PDT 24
Peak memory 160812 kb
Host smart-1b5bffec-c4e5-4130-a26c-d517b12919cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1096910711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1096910711
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3117641252
Short name T174
Test name
Test status
Simulation time 336474590000 ps
CPU time 684.11 seconds
Started Jun 11 01:55:16 PM PDT 24
Finished Jun 11 02:23:31 PM PDT 24
Peak memory 160816 kb
Host smart-26057b26-7446-4220-9c0c-59a037d8de0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3117641252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3117641252
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2572744114
Short name T186
Test name
Test status
Simulation time 336737190000 ps
CPU time 826.43 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:28:42 PM PDT 24
Peak memory 160812 kb
Host smart-020caeaf-b0e0-4ce4-a845-9223b4655b06
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2572744114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2572744114
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4192598295
Short name T192
Test name
Test status
Simulation time 336841970000 ps
CPU time 715.66 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:24:37 PM PDT 24
Peak memory 160820 kb
Host smart-b6d3d2b8-c9ac-4519-8d41-09ba5570bf2b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4192598295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4192598295
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.4208325140
Short name T25
Test name
Test status
Simulation time 336579630000 ps
CPU time 819.32 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:28:33 PM PDT 24
Peak memory 160812 kb
Host smart-78ea6989-6250-460a-83da-105747015b06
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4208325140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.4208325140
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.5538970
Short name T176
Test name
Test status
Simulation time 336471110000 ps
CPU time 687.02 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:23:35 PM PDT 24
Peak memory 160776 kb
Host smart-f11e9d89-f09b-4321-81fd-ab4c63f36409
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=5538970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.5538970
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1945748712
Short name T28
Test name
Test status
Simulation time 337071130000 ps
CPU time 743.78 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:25:36 PM PDT 24
Peak memory 160812 kb
Host smart-1f6dd6d3-b7c7-446c-9fae-f13afa8afe6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1945748712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1945748712
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1168695140
Short name T30
Test name
Test status
Simulation time 337101570000 ps
CPU time 772.18 seconds
Started Jun 11 01:55:15 PM PDT 24
Finished Jun 11 02:26:54 PM PDT 24
Peak memory 160796 kb
Host smart-fbf33dd7-5c08-4ab8-a980-0aabf89893c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1168695140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1168695140
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.8129137
Short name T178
Test name
Test status
Simulation time 336712410000 ps
CPU time 729.38 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:25:00 PM PDT 24
Peak memory 160784 kb
Host smart-842d8260-a8fe-4576-85c7-27bceab4a9d6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=8129137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.8129137
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3374922871
Short name T169
Test name
Test status
Simulation time 336416490000 ps
CPU time 786.56 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:27:07 PM PDT 24
Peak memory 160808 kb
Host smart-41c12050-56f0-442b-817f-f89209b06eab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3374922871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3374922871
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3676319700
Short name T182
Test name
Test status
Simulation time 336972970000 ps
CPU time 715.19 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:24:17 PM PDT 24
Peak memory 160800 kb
Host smart-fd317b6a-3b0b-42c7-a37d-369c74efc042
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3676319700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3676319700
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.663525099
Short name T161
Test name
Test status
Simulation time 336478090000 ps
CPU time 744.28 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:25:23 PM PDT 24
Peak memory 160768 kb
Host smart-ba7fb9b0-ae5b-4d55-9acb-307b2fc016f7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=663525099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.663525099
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.905652123
Short name T163
Test name
Test status
Simulation time 337091390000 ps
CPU time 806.28 seconds
Started Jun 11 01:55:17 PM PDT 24
Finished Jun 11 02:28:24 PM PDT 24
Peak memory 160828 kb
Host smart-8e7694ac-375b-4ccb-a0e5-5b04ed7ee43d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=905652123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.905652123
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2721300381
Short name T190
Test name
Test status
Simulation time 336890250000 ps
CPU time 742.1 seconds
Started Jun 11 01:55:11 PM PDT 24
Finished Jun 11 02:25:21 PM PDT 24
Peak memory 160812 kb
Host smart-9e4e8aeb-75ba-456c-a5e4-ed05e9d16007
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2721300381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2721300381
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.785981933
Short name T185
Test name
Test status
Simulation time 336764390000 ps
CPU time 824.51 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:28:35 PM PDT 24
Peak memory 160796 kb
Host smart-58ed53d3-0d56-467d-8f06-74202bce7108
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=785981933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.785981933
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.317880678
Short name T26
Test name
Test status
Simulation time 336635210000 ps
CPU time 738.79 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:25:33 PM PDT 24
Peak memory 160796 kb
Host smart-41d6dea0-d8f7-4c90-9c2c-75938fe14156
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=317880678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.317880678
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1670037768
Short name T196
Test name
Test status
Simulation time 336702230000 ps
CPU time 726.12 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:24:57 PM PDT 24
Peak memory 160792 kb
Host smart-243fd1f6-955c-4e6a-8a20-85db67d857d5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1670037768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1670037768
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3043357903
Short name T197
Test name
Test status
Simulation time 336650350000 ps
CPU time 778.89 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:27:08 PM PDT 24
Peak memory 160812 kb
Host smart-62601065-8306-473f-9bb6-8c287cf06914
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3043357903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3043357903
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2985163519
Short name T23
Test name
Test status
Simulation time 336790010000 ps
CPU time 708.46 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:24:13 PM PDT 24
Peak memory 160772 kb
Host smart-37638c01-9142-4173-b5e9-02310b4f1c81
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2985163519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2985163519
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.49624402
Short name T179
Test name
Test status
Simulation time 336579090000 ps
CPU time 640.37 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:21:51 PM PDT 24
Peak memory 160716 kb
Host smart-ec15e61e-473a-42eb-8df4-b5ce2ece3616
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=49624402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.49624402
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1129997004
Short name T166
Test name
Test status
Simulation time 336377870000 ps
CPU time 719.12 seconds
Started Jun 11 01:55:12 PM PDT 24
Finished Jun 11 02:24:51 PM PDT 24
Peak memory 160756 kb
Host smart-11fe3996-4b46-4203-925c-c5c6de392430
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1129997004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1129997004
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2234172019
Short name T175
Test name
Test status
Simulation time 336848250000 ps
CPU time 763.37 seconds
Started Jun 11 01:55:26 PM PDT 24
Finished Jun 11 02:26:29 PM PDT 24
Peak memory 160804 kb
Host smart-e3bdfd91-2045-423d-9e91-d4f8800f9457
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2234172019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2234172019
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.724338988
Short name T193
Test name
Test status
Simulation time 337016630000 ps
CPU time 713.4 seconds
Started Jun 11 01:55:15 PM PDT 24
Finished Jun 11 02:24:33 PM PDT 24
Peak memory 160716 kb
Host smart-87a25690-c99e-433d-afde-c33fd2680bbe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=724338988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.724338988
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2007251225
Short name T199
Test name
Test status
Simulation time 336887610000 ps
CPU time 698.51 seconds
Started Jun 11 01:55:13 PM PDT 24
Finished Jun 11 02:23:52 PM PDT 24
Peak memory 160824 kb
Host smart-c78669b1-a83f-4490-b866-7b28bd883392
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2007251225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2007251225
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4149284094
Short name T189
Test name
Test status
Simulation time 336575910000 ps
CPU time 737.62 seconds
Started Jun 11 01:55:14 PM PDT 24
Finished Jun 11 02:25:12 PM PDT 24
Peak memory 160812 kb
Host smart-85715f92-9c90-4f36-8503-e8a7ce6ff1aa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4149284094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.4149284094
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.4291163006
Short name T177
Test name
Test status
Simulation time 336608190000 ps
CPU time 779.92 seconds
Started Jun 11 01:55:15 PM PDT 24
Finished Jun 11 02:27:12 PM PDT 24
Peak memory 160804 kb
Host smart-1ddfa1bd-c2d9-4cac-9750-e9933d1fae78
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4291163006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.4291163006
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3655543439
Short name T195
Test name
Test status
Simulation time 337099910000 ps
CPU time 803.25 seconds
Started Jun 11 01:55:15 PM PDT 24
Finished Jun 11 02:28:20 PM PDT 24
Peak memory 160824 kb
Host smart-47922fc5-8ecb-4b99-9905-bc5d670a7a00
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3655543439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3655543439
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3565958932
Short name T136
Test name
Test status
Simulation time 1518810000 ps
CPU time 4.51 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:33 PM PDT 24
Peak memory 164908 kb
Host smart-543ecec2-0dcc-48af-adfe-e95f386d6591
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3565958932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3565958932
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.129085394
Short name T125
Test name
Test status
Simulation time 1520510000 ps
CPU time 4.77 seconds
Started Jun 11 02:46:15 PM PDT 24
Finished Jun 11 02:46:26 PM PDT 24
Peak memory 164884 kb
Host smart-eff514d8-7dd6-4546-b968-8f0a8a171307
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=129085394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.129085394
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.3193267266
Short name T134
Test name
Test status
Simulation time 1539790000 ps
CPU time 4.73 seconds
Started Jun 11 02:46:20 PM PDT 24
Finished Jun 11 02:46:31 PM PDT 24
Peak memory 164792 kb
Host smart-eef01b19-102b-4739-8e27-ebf52f2fc217
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3193267266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.3193267266
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.4068986785
Short name T153
Test name
Test status
Simulation time 1490950000 ps
CPU time 4.49 seconds
Started Jun 11 02:46:11 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164868 kb
Host smart-f3013378-63e3-4b69-9e8d-14f85d23e0b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4068986785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.4068986785
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.4225090239
Short name T132
Test name
Test status
Simulation time 1216990000 ps
CPU time 4.37 seconds
Started Jun 11 02:46:12 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164896 kb
Host smart-dcbfa0f3-dd9d-4df0-aee4-af17f3a100e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4225090239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.4225090239
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.512380963
Short name T114
Test name
Test status
Simulation time 1556970000 ps
CPU time 4.51 seconds
Started Jun 11 02:46:15 PM PDT 24
Finished Jun 11 02:46:27 PM PDT 24
Peak memory 164844 kb
Host smart-d2943b35-f9c1-4b08-aba6-f2542a73f0b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512380963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.512380963
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2623378353
Short name T112
Test name
Test status
Simulation time 1524230000 ps
CPU time 4.84 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:25 PM PDT 24
Peak memory 164780 kb
Host smart-2d7685f7-c986-4f98-bcf6-82d284513a75
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2623378353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2623378353
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1750844578
Short name T156
Test name
Test status
Simulation time 1258570000 ps
CPU time 3.79 seconds
Started Jun 11 02:46:11 PM PDT 24
Finished Jun 11 02:46:20 PM PDT 24
Peak memory 164856 kb
Host smart-0d72ef84-8d8c-4e0e-b247-1400da488cdf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1750844578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1750844578
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1703337513
Short name T117
Test name
Test status
Simulation time 1527190000 ps
CPU time 4.55 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:34 PM PDT 24
Peak memory 164908 kb
Host smart-7a110e7d-526d-48ff-b268-8a3237f101eb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1703337513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1703337513
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1691696760
Short name T160
Test name
Test status
Simulation time 1583790000 ps
CPU time 4.98 seconds
Started Jun 11 02:46:16 PM PDT 24
Finished Jun 11 02:46:29 PM PDT 24
Peak memory 164860 kb
Host smart-9b210dbf-2625-4c2c-97d6-d0869458b5e5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691696760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1691696760
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2438322883
Short name T150
Test name
Test status
Simulation time 1063670000 ps
CPU time 3.39 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:31 PM PDT 24
Peak memory 164908 kb
Host smart-7342ac81-d862-4d26-a67f-967c693b83c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2438322883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2438322883
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.718879279
Short name T120
Test name
Test status
Simulation time 1431630000 ps
CPU time 4.14 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164868 kb
Host smart-419fd0d3-3408-43a3-9fa9-2c9eed10e35d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718879279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.718879279
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1586358378
Short name T154
Test name
Test status
Simulation time 1538070000 ps
CPU time 5.27 seconds
Started Jun 11 02:46:11 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164896 kb
Host smart-dc56a640-24c1-4ab5-8c70-30a4164f2220
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586358378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1586358378
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3760136549
Short name T140
Test name
Test status
Simulation time 1448330000 ps
CPU time 3.8 seconds
Started Jun 11 02:46:11 PM PDT 24
Finished Jun 11 02:46:21 PM PDT 24
Peak memory 164852 kb
Host smart-c2b540a2-91f9-47ab-98e4-65f973e107df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3760136549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3760136549
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2338766721
Short name T130
Test name
Test status
Simulation time 1206830000 ps
CPU time 3.02 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:22 PM PDT 24
Peak memory 164888 kb
Host smart-944535cf-0e6d-4fd5-8e5d-a93bb022a230
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2338766721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2338766721
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4256013167
Short name T149
Test name
Test status
Simulation time 1520330000 ps
CPU time 4.45 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:24 PM PDT 24
Peak memory 164888 kb
Host smart-0d191567-6918-4cfb-8dcc-da1ef9bade73
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256013167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4256013167
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2217068720
Short name T142
Test name
Test status
Simulation time 1467250000 ps
CPU time 4.19 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:33 PM PDT 24
Peak memory 164908 kb
Host smart-ef9f1009-7862-42c5-8096-f89c146bea94
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2217068720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2217068720
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.127390246
Short name T145
Test name
Test status
Simulation time 1477650000 ps
CPU time 4.08 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:25 PM PDT 24
Peak memory 164880 kb
Host smart-95e5f4a4-ba18-48ba-9caf-b34c931dfe3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=127390246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.127390246
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4021152203
Short name T118
Test name
Test status
Simulation time 1462050000 ps
CPU time 4.93 seconds
Started Jun 11 02:46:12 PM PDT 24
Finished Jun 11 02:46:24 PM PDT 24
Peak memory 164856 kb
Host smart-4f57c026-7ce5-4e06-a504-098f59b7cd9c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4021152203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4021152203
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2481529935
Short name T158
Test name
Test status
Simulation time 1213510000 ps
CPU time 3.92 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:24 PM PDT 24
Peak memory 164832 kb
Host smart-3c99cf0f-1e3a-4aa4-984a-a0a0643df2ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481529935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2481529935
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2419869583
Short name T129
Test name
Test status
Simulation time 1458170000 ps
CPU time 4.4 seconds
Started Jun 11 02:46:12 PM PDT 24
Finished Jun 11 02:46:22 PM PDT 24
Peak memory 164908 kb
Host smart-928cbb8d-dbce-4c05-b95c-c90455a261d6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2419869583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2419869583
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2899420400
Short name T135
Test name
Test status
Simulation time 1422250000 ps
CPU time 4.11 seconds
Started Jun 11 02:46:20 PM PDT 24
Finished Jun 11 02:46:30 PM PDT 24
Peak memory 164792 kb
Host smart-fda3d0f8-ab42-4f16-9c4c-7750f8fd8b57
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2899420400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2899420400
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.867610033
Short name T139
Test name
Test status
Simulation time 1558210000 ps
CPU time 4.43 seconds
Started Jun 11 02:46:16 PM PDT 24
Finished Jun 11 02:46:27 PM PDT 24
Peak memory 164852 kb
Host smart-50f6e14b-3fd3-4927-82bd-f1413e8d81fa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=867610033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.867610033
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3013997553
Short name T121
Test name
Test status
Simulation time 1425170000 ps
CPU time 4.06 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164884 kb
Host smart-be2dbe4a-6a9d-43f5-b28d-fcf01244b08c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3013997553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3013997553
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1373643564
Short name T146
Test name
Test status
Simulation time 1505730000 ps
CPU time 4.64 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:26 PM PDT 24
Peak memory 164912 kb
Host smart-15c11d24-ae4e-40f7-b314-2db0599d6776
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1373643564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1373643564
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3511899924
Short name T144
Test name
Test status
Simulation time 1431590000 ps
CPU time 4.58 seconds
Started Jun 11 02:46:11 PM PDT 24
Finished Jun 11 02:46:22 PM PDT 24
Peak memory 164872 kb
Host smart-431f0ab6-9166-4ec9-9976-f5ede9d596c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3511899924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3511899924
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.324961439
Short name T128
Test name
Test status
Simulation time 1361970000 ps
CPU time 3.33 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164880 kb
Host smart-94b5bbb3-df84-4061-9575-c21e0300f820
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=324961439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.324961439
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3745643298
Short name T159
Test name
Test status
Simulation time 1600730000 ps
CPU time 5.13 seconds
Started Jun 11 02:46:16 PM PDT 24
Finished Jun 11 02:46:29 PM PDT 24
Peak memory 164900 kb
Host smart-7819f89c-ea12-411d-9e25-555655e56df8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3745643298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3745643298
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4218802886
Short name T147
Test name
Test status
Simulation time 1479210000 ps
CPU time 3.54 seconds
Started Jun 11 02:46:17 PM PDT 24
Finished Jun 11 02:46:26 PM PDT 24
Peak memory 164900 kb
Host smart-7df15954-5671-4996-b5c7-dc535dc9b4de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4218802886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4218802886
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3919532838
Short name T137
Test name
Test status
Simulation time 1403270000 ps
CPU time 4.47 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:26 PM PDT 24
Peak memory 164832 kb
Host smart-ac1c8c2f-45d9-4645-8511-a81203ad985a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3919532838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3919532838
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.104882641
Short name T111
Test name
Test status
Simulation time 1581730000 ps
CPU time 6.26 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:28 PM PDT 24
Peak memory 164848 kb
Host smart-85125a10-b34f-4c1a-91c9-4516077cff68
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104882641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.104882641
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.2874776966
Short name T126
Test name
Test status
Simulation time 1451590000 ps
CPU time 4.27 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164876 kb
Host smart-351af4e2-e20c-42eb-bc2b-87d60fe32e48
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2874776966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.2874776966
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3442742648
Short name T115
Test name
Test status
Simulation time 992810000 ps
CPU time 3.38 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:31 PM PDT 24
Peak memory 164784 kb
Host smart-677b1a84-1f04-444c-8ead-55d6c5ba896a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3442742648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3442742648
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2648204
Short name T133
Test name
Test status
Simulation time 1611810000 ps
CPU time 4.69 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:34 PM PDT 24
Peak memory 164760 kb
Host smart-09edb917-d06b-4b69-b81d-a0e08f35b27e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2648204
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1109416247
Short name T141
Test name
Test status
Simulation time 1305470000 ps
CPU time 3.58 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164888 kb
Host smart-f826060e-1401-4eb8-a21d-b1003d1abde1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109416247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1109416247
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2211175533
Short name T157
Test name
Test status
Simulation time 1511330000 ps
CPU time 4.4 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:25 PM PDT 24
Peak memory 164916 kb
Host smart-9505d3d6-db6d-4abb-aa91-4f826c72e94f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2211175533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2211175533
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.726209798
Short name T155
Test name
Test status
Simulation time 1526810000 ps
CPU time 4.5 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:32 PM PDT 24
Peak memory 164784 kb
Host smart-867015a7-7170-400e-bb54-6193c37922ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726209798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.726209798
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3047666646
Short name T151
Test name
Test status
Simulation time 1579130000 ps
CPU time 4.88 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:34 PM PDT 24
Peak memory 164792 kb
Host smart-63beb3c2-e52f-4939-8e28-174880892936
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3047666646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3047666646
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1747214406
Short name T116
Test name
Test status
Simulation time 1382650000 ps
CPU time 4.33 seconds
Started Jun 11 02:46:15 PM PDT 24
Finished Jun 11 02:46:27 PM PDT 24
Peak memory 164916 kb
Host smart-cadc0b9d-e8e8-471d-8b0b-4bc54352fb41
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747214406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1747214406
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.645360773
Short name T152
Test name
Test status
Simulation time 1061630000 ps
CPU time 3.25 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164908 kb
Host smart-56052989-5f3c-40b6-8682-c390264d098d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=645360773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.645360773
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.33704015
Short name T143
Test name
Test status
Simulation time 1477970000 ps
CPU time 3.36 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164856 kb
Host smart-0c31d065-fe74-4b22-b086-d88abfc03970
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33704015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.33704015
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.190968482
Short name T138
Test name
Test status
Simulation time 1491790000 ps
CPU time 3.94 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:24 PM PDT 24
Peak memory 164880 kb
Host smart-35cc8a12-ef75-4c9e-864a-9111e9d2d14d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=190968482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.190968482
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.976332351
Short name T148
Test name
Test status
Simulation time 1433610000 ps
CPU time 3.68 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:22 PM PDT 24
Peak memory 164880 kb
Host smart-f4e1f0e5-a271-49c0-9c06-a35b4cba2811
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=976332351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.976332351
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2922447734
Short name T123
Test name
Test status
Simulation time 1506290000 ps
CPU time 4.4 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:32 PM PDT 24
Peak memory 164792 kb
Host smart-99b478ac-c8c2-403f-a9c5-8f8eb69726fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922447734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2922447734
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.323745361
Short name T119
Test name
Test status
Simulation time 1359510000 ps
CPU time 4.33 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:25 PM PDT 24
Peak memory 164864 kb
Host smart-335caa4d-3e1a-4f1d-9e68-9a51ff1aa45b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=323745361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.323745361
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2716395516
Short name T127
Test name
Test status
Simulation time 1448170000 ps
CPU time 3.8 seconds
Started Jun 11 02:46:15 PM PDT 24
Finished Jun 11 02:46:26 PM PDT 24
Peak memory 164880 kb
Host smart-4928b389-2566-4a18-a66b-283cabba421c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2716395516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2716395516
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1530727513
Short name T113
Test name
Test status
Simulation time 1368390000 ps
CPU time 3.7 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:23 PM PDT 24
Peak memory 164860 kb
Host smart-3321bfa0-d9ba-4cb1-af61-0f5a3c6c14ff
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530727513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1530727513
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2788726082
Short name T124
Test name
Test status
Simulation time 1366730000 ps
CPU time 4.79 seconds
Started Jun 11 02:46:13 PM PDT 24
Finished Jun 11 02:46:25 PM PDT 24
Peak memory 164892 kb
Host smart-65478c04-f63d-4d8f-b68c-486bc5f4eb28
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788726082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2788726082
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1077896670
Short name T122
Test name
Test status
Simulation time 1565090000 ps
CPU time 4.33 seconds
Started Jun 11 02:46:14 PM PDT 24
Finished Jun 11 02:46:25 PM PDT 24
Peak memory 165004 kb
Host smart-d6f1f3c4-47c0-4ebc-8f31-5ceddac2f1e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1077896670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1077896670
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.695608259
Short name T131
Test name
Test status
Simulation time 1280070000 ps
CPU time 3.85 seconds
Started Jun 11 02:46:21 PM PDT 24
Finished Jun 11 02:46:31 PM PDT 24
Peak memory 164776 kb
Host smart-1fbb4296-d7d2-4a77-a357-617e90a07499
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=695608259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.695608259
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3157528933
Short name T10
Test name
Test status
Simulation time 1350270000 ps
CPU time 3.07 seconds
Started Jun 11 01:49:27 PM PDT 24
Finished Jun 11 01:49:36 PM PDT 24
Peak memory 164852 kb
Host smart-e6abb73e-8f61-401c-af35-25bbb99bd37d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3157528933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3157528933
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3737291568
Short name T1
Test name
Test status
Simulation time 1322310000 ps
CPU time 5.59 seconds
Started Jun 11 01:49:19 PM PDT 24
Finished Jun 11 01:49:32 PM PDT 24
Peak memory 164852 kb
Host smart-df562855-1b92-415b-85fa-b29e5221425c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3737291568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3737291568
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2081521915
Short name T62
Test name
Test status
Simulation time 1339570000 ps
CPU time 3.53 seconds
Started Jun 11 01:49:29 PM PDT 24
Finished Jun 11 01:49:39 PM PDT 24
Peak memory 164892 kb
Host smart-e48d667e-9895-4ddb-853e-4ac0fa587288
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2081521915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2081521915
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3311970240
Short name T34
Test name
Test status
Simulation time 1345090000 ps
CPU time 5.93 seconds
Started Jun 11 01:49:20 PM PDT 24
Finished Jun 11 01:49:34 PM PDT 24
Peak memory 164888 kb
Host smart-f3738ac0-81c6-44fc-9412-f75a27c5159f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3311970240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3311970240
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1505335539
Short name T51
Test name
Test status
Simulation time 1538170000 ps
CPU time 3.98 seconds
Started Jun 11 01:49:34 PM PDT 24
Finished Jun 11 01:49:44 PM PDT 24
Peak memory 164868 kb
Host smart-8e9fe3ac-87d8-40a2-8c04-0a66ae81ae74
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505335539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1505335539
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1004723481
Short name T60
Test name
Test status
Simulation time 1450710000 ps
CPU time 4.1 seconds
Started Jun 11 01:49:35 PM PDT 24
Finished Jun 11 01:49:46 PM PDT 24
Peak memory 164892 kb
Host smart-1fe094a5-c2e7-493e-881b-bdcf7a25b847
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1004723481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1004723481
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1398315720
Short name T66
Test name
Test status
Simulation time 1523430000 ps
CPU time 4.85 seconds
Started Jun 11 01:49:35 PM PDT 24
Finished Jun 11 01:49:47 PM PDT 24
Peak memory 164912 kb
Host smart-0cba40f8-3548-4f92-bb3a-1cb327c15e1a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1398315720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1398315720
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2692965580
Short name T61
Test name
Test status
Simulation time 1635790000 ps
CPU time 4.7 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164864 kb
Host smart-32417b33-b459-4064-be13-061c4b880511
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692965580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2692965580
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.47362512
Short name T38
Test name
Test status
Simulation time 1515310000 ps
CPU time 4.68 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:47 PM PDT 24
Peak memory 164820 kb
Host smart-59b1a9b7-11b5-4f16-8216-d350045224b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47362512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.47362512
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3699853362
Short name T57
Test name
Test status
Simulation time 1524410000 ps
CPU time 5.09 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164876 kb
Host smart-3921d5e8-309f-41f8-90c7-28da3152140d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699853362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3699853362
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3228885509
Short name T64
Test name
Test status
Simulation time 1249050000 ps
CPU time 2.78 seconds
Started Jun 11 01:49:41 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164840 kb
Host smart-a9c24158-d659-4c51-99ba-861621cf2efd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3228885509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3228885509
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.413608577
Short name T39
Test name
Test status
Simulation time 1588530000 ps
CPU time 3.77 seconds
Started Jun 11 01:49:45 PM PDT 24
Finished Jun 11 01:49:54 PM PDT 24
Peak memory 164876 kb
Host smart-9c98649d-2729-4f29-b140-f984c591f84e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=413608577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.413608577
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1803488700
Short name T69
Test name
Test status
Simulation time 1414750000 ps
CPU time 4.21 seconds
Started Jun 11 01:49:41 PM PDT 24
Finished Jun 11 01:49:52 PM PDT 24
Peak memory 164864 kb
Host smart-dddebf78-041e-4c39-a9e0-8fea18f958d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1803488700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1803488700
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3197519569
Short name T44
Test name
Test status
Simulation time 1179610000 ps
CPU time 3.12 seconds
Started Jun 11 01:49:38 PM PDT 24
Finished Jun 11 01:49:46 PM PDT 24
Peak memory 164888 kb
Host smart-a79c1890-6fc9-47c9-8e27-840ea04f2e97
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197519569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3197519569
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4283341609
Short name T48
Test name
Test status
Simulation time 1235930000 ps
CPU time 3.76 seconds
Started Jun 11 01:49:42 PM PDT 24
Finished Jun 11 01:49:52 PM PDT 24
Peak memory 164880 kb
Host smart-ef85e8d1-f4e9-4de0-81fa-263cab5b4ee8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283341609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.4283341609
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2973536275
Short name T67
Test name
Test status
Simulation time 1531290000 ps
CPU time 5.02 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164888 kb
Host smart-ac8b126a-83d6-4913-8cc5-c33278a1ff35
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2973536275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2973536275
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2143059747
Short name T53
Test name
Test status
Simulation time 1570530000 ps
CPU time 5.48 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164876 kb
Host smart-daf312ee-b98b-49db-a1e8-69615c2e2a29
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2143059747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2143059747
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3207773743
Short name T47
Test name
Test status
Simulation time 1573830000 ps
CPU time 3.99 seconds
Started Jun 11 01:49:46 PM PDT 24
Finished Jun 11 01:49:56 PM PDT 24
Peak memory 164868 kb
Host smart-c72af1ae-c156-4b6b-b98f-79d33b44184e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3207773743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3207773743
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1020843378
Short name T41
Test name
Test status
Simulation time 1562790000 ps
CPU time 5.6 seconds
Started Jun 11 01:49:42 PM PDT 24
Finished Jun 11 01:49:55 PM PDT 24
Peak memory 164824 kb
Host smart-ce0646be-50b4-4a1b-9b53-aa15656caf02
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1020843378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1020843378
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.239927135
Short name T2
Test name
Test status
Simulation time 1536550000 ps
CPU time 3.73 seconds
Started Jun 11 01:49:41 PM PDT 24
Finished Jun 11 01:49:50 PM PDT 24
Peak memory 164880 kb
Host smart-947190b4-44b9-4599-b85f-9a29786258a4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=239927135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.239927135
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1282610458
Short name T59
Test name
Test status
Simulation time 1582950000 ps
CPU time 4.33 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:50 PM PDT 24
Peak memory 164896 kb
Host smart-8fc8c88b-4e67-4801-b514-6e940a2abce8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1282610458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1282610458
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.280260283
Short name T32
Test name
Test status
Simulation time 1490750000 ps
CPU time 4.43 seconds
Started Jun 11 01:49:32 PM PDT 24
Finished Jun 11 01:49:43 PM PDT 24
Peak memory 164844 kb
Host smart-950943d7-78b9-4ba8-8cf1-9e2a1412e938
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=280260283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.280260283
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.704783842
Short name T65
Test name
Test status
Simulation time 1555490000 ps
CPU time 3.94 seconds
Started Jun 11 01:49:20 PM PDT 24
Finished Jun 11 01:49:30 PM PDT 24
Peak memory 164848 kb
Host smart-2627f19e-919d-4c3b-bf17-df91077c5321
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=704783842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.704783842
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.779808965
Short name T43
Test name
Test status
Simulation time 1303230000 ps
CPU time 3.61 seconds
Started Jun 11 01:49:47 PM PDT 24
Finished Jun 11 01:49:56 PM PDT 24
Peak memory 164880 kb
Host smart-487c3ecb-ec63-489b-b3dc-10ae535ff73d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=779808965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.779808965
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.529663493
Short name T58
Test name
Test status
Simulation time 1359650000 ps
CPU time 4.05 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:47 PM PDT 24
Peak memory 164772 kb
Host smart-ae725c18-d3dd-4e77-9797-89701534dcb5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=529663493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.529663493
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3414364012
Short name T50
Test name
Test status
Simulation time 1560010000 ps
CPU time 4.67 seconds
Started Jun 11 01:49:35 PM PDT 24
Finished Jun 11 01:49:46 PM PDT 24
Peak memory 164900 kb
Host smart-637241fd-5cba-4380-98f3-7d16f5a5d2bc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3414364012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3414364012
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2349452086
Short name T12
Test name
Test status
Simulation time 1435630000 ps
CPU time 3.17 seconds
Started Jun 11 01:49:43 PM PDT 24
Finished Jun 11 01:49:51 PM PDT 24
Peak memory 164856 kb
Host smart-27e08541-ac89-4876-b72d-9b440fb66ed5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349452086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2349452086
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2411268389
Short name T49
Test name
Test status
Simulation time 1605390000 ps
CPU time 4.56 seconds
Started Jun 11 01:49:38 PM PDT 24
Finished Jun 11 01:49:50 PM PDT 24
Peak memory 164896 kb
Host smart-9668acdc-d226-409f-8a94-9a6a4101d409
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2411268389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2411268389
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.4219419909
Short name T13
Test name
Test status
Simulation time 1511450000 ps
CPU time 5.04 seconds
Started Jun 11 01:49:44 PM PDT 24
Finished Jun 11 01:49:55 PM PDT 24
Peak memory 164888 kb
Host smart-8084d982-85c0-42d0-a58b-dae815a86653
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4219419909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.4219419909
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1844510777
Short name T70
Test name
Test status
Simulation time 1536830000 ps
CPU time 4.5 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:48 PM PDT 24
Peak memory 164904 kb
Host smart-5fdd9389-a489-4f5c-91f6-09502d5e8121
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1844510777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1844510777
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2772932285
Short name T9
Test name
Test status
Simulation time 1465450000 ps
CPU time 3.44 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164908 kb
Host smart-c8090f4c-e825-41e2-af22-2d2946c4b4d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2772932285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2772932285
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.813319723
Short name T46
Test name
Test status
Simulation time 1129030000 ps
CPU time 2.64 seconds
Started Jun 11 01:49:38 PM PDT 24
Finished Jun 11 01:49:45 PM PDT 24
Peak memory 164880 kb
Host smart-50ff2b9a-8fba-43d0-88d6-05899031186f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=813319723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.813319723
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2984146603
Short name T33
Test name
Test status
Simulation time 1439590000 ps
CPU time 3.33 seconds
Started Jun 11 01:49:35 PM PDT 24
Finished Jun 11 01:49:44 PM PDT 24
Peak memory 164888 kb
Host smart-8b5b63d7-f9ce-4a70-aa75-7dd43d605567
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984146603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2984146603
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3475322304
Short name T68
Test name
Test status
Simulation time 1470450000 ps
CPU time 4.14 seconds
Started Jun 11 01:49:30 PM PDT 24
Finished Jun 11 01:49:40 PM PDT 24
Peak memory 164892 kb
Host smart-70b8a225-1f44-435b-91a2-7657e059f188
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3475322304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3475322304
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.1857192203
Short name T45
Test name
Test status
Simulation time 1550650000 ps
CPU time 4.15 seconds
Started Jun 11 01:49:43 PM PDT 24
Finished Jun 11 01:49:53 PM PDT 24
Peak memory 164904 kb
Host smart-aad485fa-7ba6-4cf9-8acc-c2729627504b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857192203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.1857192203
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4187392099
Short name T56
Test name
Test status
Simulation time 1565430000 ps
CPU time 3.61 seconds
Started Jun 11 01:49:40 PM PDT 24
Finished Jun 11 01:49:49 PM PDT 24
Peak memory 164852 kb
Host smart-57592fe8-57fa-47ba-a21e-61b9017410ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4187392099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4187392099
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.396984690
Short name T31
Test name
Test status
Simulation time 1449170000 ps
CPU time 3.02 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:45 PM PDT 24
Peak memory 164848 kb
Host smart-dbf1280a-6109-425d-b001-15165b60e9d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396984690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.396984690
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3855341485
Short name T55
Test name
Test status
Simulation time 1099370000 ps
CPU time 2.95 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:43 PM PDT 24
Peak memory 164868 kb
Host smart-cce574b0-ed24-4737-8401-bbed5f1a22a5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3855341485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3855341485
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2312425853
Short name T36
Test name
Test status
Simulation time 1537630000 ps
CPU time 4.27 seconds
Started Jun 11 01:49:43 PM PDT 24
Finished Jun 11 01:49:53 PM PDT 24
Peak memory 164888 kb
Host smart-d48a581c-e6e7-4743-84ea-e4d633e2aaff
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2312425853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2312425853
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1213918494
Short name T37
Test name
Test status
Simulation time 1552890000 ps
CPU time 4.79 seconds
Started Jun 11 01:49:38 PM PDT 24
Finished Jun 11 01:49:50 PM PDT 24
Peak memory 164852 kb
Host smart-ae9d5cb0-ee3e-49bc-a236-266b9b895b3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1213918494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1213918494
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1421986580
Short name T63
Test name
Test status
Simulation time 1305970000 ps
CPU time 3.91 seconds
Started Jun 11 01:49:42 PM PDT 24
Finished Jun 11 01:49:52 PM PDT 24
Peak memory 164880 kb
Host smart-304cda64-4ae8-469d-88f2-f06dddb609ea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1421986580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1421986580
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2331916805
Short name T3
Test name
Test status
Simulation time 1614250000 ps
CPU time 5.21 seconds
Started Jun 11 01:49:42 PM PDT 24
Finished Jun 11 01:49:54 PM PDT 24
Peak memory 164856 kb
Host smart-e253f3fd-58b0-4549-9597-7dbefdefbb61
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331916805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2331916805
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1645083553
Short name T40
Test name
Test status
Simulation time 1313310000 ps
CPU time 3.41 seconds
Started Jun 11 01:49:46 PM PDT 24
Finished Jun 11 01:49:55 PM PDT 24
Peak memory 164856 kb
Host smart-024ff97d-7196-42e9-a12a-eadc52bd7110
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1645083553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1645083553
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3318663470
Short name T52
Test name
Test status
Simulation time 1300090000 ps
CPU time 3.41 seconds
Started Jun 11 01:49:30 PM PDT 24
Finished Jun 11 01:49:39 PM PDT 24
Peak memory 164856 kb
Host smart-0ba2df9b-2ce5-409e-a3b2-9091216c410b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3318663470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3318663470
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1624485573
Short name T42
Test name
Test status
Simulation time 1156490000 ps
CPU time 4.03 seconds
Started Jun 11 01:49:36 PM PDT 24
Finished Jun 11 01:49:46 PM PDT 24
Peak memory 164852 kb
Host smart-6aef9806-30ad-4fa4-9bf2-06b7b8ecd968
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1624485573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1624485573
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1604001339
Short name T8
Test name
Test status
Simulation time 1607670000 ps
CPU time 3.99 seconds
Started Jun 11 01:49:30 PM PDT 24
Finished Jun 11 01:49:40 PM PDT 24
Peak memory 164844 kb
Host smart-2b1c339b-201e-41c7-9570-8476ef8b682f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1604001339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1604001339
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3144533825
Short name T54
Test name
Test status
Simulation time 1435610000 ps
CPU time 3.77 seconds
Started Jun 11 01:49:37 PM PDT 24
Finished Jun 11 01:49:47 PM PDT 24
Peak memory 164892 kb
Host smart-f962c803-5c31-4763-9b37-3d393a82baef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3144533825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3144533825
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.824587503
Short name T4
Test name
Test status
Simulation time 1479970000 ps
CPU time 4.33 seconds
Started Jun 11 01:49:25 PM PDT 24
Finished Jun 11 01:49:37 PM PDT 24
Peak memory 164892 kb
Host smart-09463d5f-5a64-465a-8d98-1f713a22a87d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824587503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.824587503
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3206580312
Short name T35
Test name
Test status
Simulation time 1323070000 ps
CPU time 5.08 seconds
Started Jun 11 01:49:33 PM PDT 24
Finished Jun 11 01:49:45 PM PDT 24
Peak memory 164856 kb
Host smart-8a22ff3d-02bc-432a-b57a-31a900bc3869
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3206580312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3206580312
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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