Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3320316638
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3859286015
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1318091553
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3498785146

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.670891374
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2171328308
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1143060925
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3939697234
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3153236303
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2633884500
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2744098395
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.960571947
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1170186103
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1934540115
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2859605972
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1542498626
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3204139616
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3600461863
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1559192292
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1381012899
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1079443808
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4144483468
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3668433655
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.583071204
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1070994422
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.467922784
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.142921431
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3305181351
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.340889167
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1718062030
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.461539847
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1605438743
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3470504145
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.703856732
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3770585185
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2779463709
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3776715858
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1167044943
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2556677565
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4182992133
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2241003768
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3273829311
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.864360713
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4005275146
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1658961894
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2083114455
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2078998108
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.972749276
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3957067325
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3360841352
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2177054186
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1204988475
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2657888260
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1048383718
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.268864018
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1898454232
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2188233092
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.121700999
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3145328049
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2717736899
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.905515489
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.218603486
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2707695220
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1916785805
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1295993097
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2963223360
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3436057549
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.441905740
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1039903218
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2392445478
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2110249225
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2249702442
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3505262213
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1618751437
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3408571276
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3179135263
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3967972118
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3138710901
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.195873055
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1625906650
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1204692859
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.496124046
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.160986422
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.804526679
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.208476613
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1706144644
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1416453307
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.771642939
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.79608450
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.701098420
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.274649929
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.829079924
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1222440206
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.659240934
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4204363562
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3529776016
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.891393200
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2928583836
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2212275955
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.20611938
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1824718238
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2032322518
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1049322600
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.505467176
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2072219587
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1450438888
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4005293226
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2574386939
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4073155598
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.939373903
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2672720137
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3939009157
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2530532366
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.41329506
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4080685514
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1143344846
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4206704707
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1947222373
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3555953823
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.248334479
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3174842058
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4207128025
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.681726554
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1677646613
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.276152349
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2579128513
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.25219459
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1980035143
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1851935520
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2597520568
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.56304184
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3093227724
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1871389432
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2257920361
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.851799170
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2658024688
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1225435930
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2825571828
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4176187544
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2783942061
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1199145562
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.343381442
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.846001869
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3776440334
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2136214962
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1777355815
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3041034517
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1061522491
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3219321032
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1206019436
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2813393118
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4246993248
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3418379256
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3599363841
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.879881070
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1243448346
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3134576489
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3064276691
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1419322655
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1127117523
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2815966242
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2544516778
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3548725430
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1598750371
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1518536218
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2995605564
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3928435720
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.413991763
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2087943331
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2441303387
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3351303748
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.14026706
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3669953059
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.863236778
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.987253242
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.241753951
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2529253654
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1489807018
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2590143420
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1159489644
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2057061529
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1359468902
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3671164195
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.471539485
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1764935468
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.48704539
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4119951721
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3676185307
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.486222044
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4179988302
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.71923668
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1359081930
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.499882394
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2920765147
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2754271447
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.453362537
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3066092537
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1844100687
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3392576215
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2316573743



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.486222044 Jun 21 05:58:30 PM PDT 24 Jun 21 05:58:40 PM PDT 24 1526910000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3320316638 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:25 PM PDT 24 1497490000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3548725430 Jun 21 05:58:15 PM PDT 24 Jun 21 05:58:26 PM PDT 24 1446570000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.471539485 Jun 21 05:58:29 PM PDT 24 Jun 21 05:58:40 PM PDT 24 1306290000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.413991763 Jun 21 05:58:23 PM PDT 24 Jun 21 05:58:40 PM PDT 24 1599630000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2920765147 Jun 21 05:58:37 PM PDT 24 Jun 21 05:58:45 PM PDT 24 1469250000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1489807018 Jun 21 05:58:24 PM PDT 24 Jun 21 05:58:35 PM PDT 24 1445070000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1359468902 Jun 21 05:58:30 PM PDT 24 Jun 21 05:58:41 PM PDT 24 1379190000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3351303748 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:32 PM PDT 24 1514770000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2544516778 Jun 21 05:58:24 PM PDT 24 Jun 21 05:58:36 PM PDT 24 1448330000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2316573743 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:24 PM PDT 24 1483750000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3669953059 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:35 PM PDT 24 1471010000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1127117523 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:31 PM PDT 24 1458230000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3134576489 Jun 21 05:58:17 PM PDT 24 Jun 21 05:58:28 PM PDT 24 1500430000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3599363841 Jun 21 05:58:15 PM PDT 24 Jun 21 05:58:27 PM PDT 24 1358510000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1844100687 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:25 PM PDT 24 1469270000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.241753951 Jun 21 05:58:21 PM PDT 24 Jun 21 05:58:33 PM PDT 24 1324550000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2057061529 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:36 PM PDT 24 1543490000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1419322655 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:35 PM PDT 24 1518450000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3676185307 Jun 21 05:58:32 PM PDT 24 Jun 21 05:58:45 PM PDT 24 1531670000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1764935468 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:24 PM PDT 24 1377430000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1359081930 Jun 21 05:58:29 PM PDT 24 Jun 21 05:58:43 PM PDT 24 1492290000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4119951721 Jun 21 05:58:30 PM PDT 24 Jun 21 05:58:41 PM PDT 24 1532990000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3418379256 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:25 PM PDT 24 1514730000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2815966242 Jun 21 05:58:24 PM PDT 24 Jun 21 05:58:35 PM PDT 24 1239710000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.48704539 Jun 21 05:58:32 PM PDT 24 Jun 21 05:58:43 PM PDT 24 1521270000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1598750371 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:33 PM PDT 24 1472830000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2754271447 Jun 21 05:58:38 PM PDT 24 Jun 21 05:58:49 PM PDT 24 1535630000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3066092537 Jun 21 05:58:13 PM PDT 24 Jun 21 05:58:26 PM PDT 24 1481790000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3064276691 Jun 21 05:58:17 PM PDT 24 Jun 21 05:58:28 PM PDT 24 1454390000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.987253242 Jun 21 05:58:21 PM PDT 24 Jun 21 05:58:30 PM PDT 24 1598010000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2995605564 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:35 PM PDT 24 1384430000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4246993248 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:26 PM PDT 24 1399950000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3928435720 Jun 21 05:58:21 PM PDT 24 Jun 21 05:58:33 PM PDT 24 1461110000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.453362537 Jun 21 05:58:15 PM PDT 24 Jun 21 05:58:27 PM PDT 24 1397670000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1159489644 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:35 PM PDT 24 1504110000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3392576215 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:27 PM PDT 24 1531730000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4179988302 Jun 21 05:58:37 PM PDT 24 Jun 21 05:58:45 PM PDT 24 1326190000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.863236778 Jun 21 05:58:14 PM PDT 24 Jun 21 05:58:24 PM PDT 24 1476710000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.14026706 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:31 PM PDT 24 1553110000 ps
T71 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2590143420 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:38 PM PDT 24 1563330000 ps
T72 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1243448346 Jun 21 05:58:17 PM PDT 24 Jun 21 05:58:27 PM PDT 24 1590050000 ps
T73 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2087943331 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:33 PM PDT 24 1461390000 ps
T74 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1518536218 Jun 21 05:58:23 PM PDT 24 Jun 21 05:58:33 PM PDT 24 1387170000 ps
T75 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.499882394 Jun 21 05:58:32 PM PDT 24 Jun 21 05:58:43 PM PDT 24 1552050000 ps
T76 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2529253654 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:34 PM PDT 24 1395530000 ps
T77 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.879881070 Jun 21 05:58:17 PM PDT 24 Jun 21 05:58:27 PM PDT 24 1567650000 ps
T78 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.71923668 Jun 21 05:58:30 PM PDT 24 Jun 21 05:58:42 PM PDT 24 1379390000 ps
T79 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2441303387 Jun 21 05:58:22 PM PDT 24 Jun 21 05:58:31 PM PDT 24 1482950000 ps
T80 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3671164195 Jun 21 05:58:29 PM PDT 24 Jun 21 05:58:37 PM PDT 24 1428690000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2597520568 Jun 21 05:38:25 PM PDT 24 Jun 21 05:38:38 PM PDT 24 1465530000 ps
T5 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2672720137 Jun 21 05:38:02 PM PDT 24 Jun 21 05:38:11 PM PDT 24 1521750000 ps
T6 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.681726554 Jun 21 05:38:25 PM PDT 24 Jun 21 05:38:38 PM PDT 24 1433170000 ps
T24 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.25219459 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:40 PM PDT 24 1477910000 ps
T25 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4073155598 Jun 21 05:38:04 PM PDT 24 Jun 21 05:38:13 PM PDT 24 1506530000 ps
T26 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1206019436 Jun 21 05:37:52 PM PDT 24 Jun 21 05:38:00 PM PDT 24 1495670000 ps
T27 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.41329506 Jun 21 05:37:42 PM PDT 24 Jun 21 05:37:58 PM PDT 24 1564030000 ps
T28 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1450438888 Jun 21 05:37:52 PM PDT 24 Jun 21 05:38:06 PM PDT 24 1458550000 ps
T29 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3498785146 Jun 21 05:37:43 PM PDT 24 Jun 21 05:37:54 PM PDT 24 1588310000 ps
T30 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3174842058 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:34 PM PDT 24 1386550000 ps
T81 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4080685514 Jun 21 05:38:02 PM PDT 24 Jun 21 05:38:11 PM PDT 24 1458610000 ps
T82 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1225435930 Jun 21 05:38:36 PM PDT 24 Jun 21 05:38:45 PM PDT 24 1614470000 ps
T83 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1143344846 Jun 21 05:38:03 PM PDT 24 Jun 21 05:38:11 PM PDT 24 1349610000 ps
T84 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3041034517 Jun 21 05:37:51 PM PDT 24 Jun 21 05:38:01 PM PDT 24 1420930000 ps
T85 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3219321032 Jun 21 05:37:54 PM PDT 24 Jun 21 05:38:05 PM PDT 24 1384370000 ps
T86 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.343381442 Jun 21 05:38:34 PM PDT 24 Jun 21 05:38:42 PM PDT 24 1208910000 ps
T87 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.56304184 Jun 21 05:38:25 PM PDT 24 Jun 21 05:38:37 PM PDT 24 1348930000 ps
T88 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2579128513 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:39 PM PDT 24 1517490000 ps
T89 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1061522491 Jun 21 05:37:53 PM PDT 24 Jun 21 05:38:01 PM PDT 24 1503330000 ps
T90 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1049322600 Jun 21 05:37:44 PM PDT 24 Jun 21 05:37:53 PM PDT 24 1390750000 ps
T91 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2072219587 Jun 21 05:37:52 PM PDT 24 Jun 21 05:38:05 PM PDT 24 1508230000 ps
T92 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.505467176 Jun 21 05:37:52 PM PDT 24 Jun 21 05:38:01 PM PDT 24 1363230000 ps
T93 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4206704707 Jun 21 05:38:17 PM PDT 24 Jun 21 05:38:30 PM PDT 24 1536170000 ps
T94 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2825571828 Jun 21 05:38:33 PM PDT 24 Jun 21 05:38:40 PM PDT 24 1093150000 ps
T95 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1199145562 Jun 21 05:38:39 PM PDT 24 Jun 21 05:38:49 PM PDT 24 1449250000 ps
T96 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3776440334 Jun 21 05:38:39 PM PDT 24 Jun 21 05:38:47 PM PDT 24 1267950000 ps
T97 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2530532366 Jun 21 05:38:00 PM PDT 24 Jun 21 05:38:13 PM PDT 24 1420490000 ps
T98 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4207128025 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:39 PM PDT 24 1542770000 ps
T99 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1871389432 Jun 21 05:38:25 PM PDT 24 Jun 21 05:38:36 PM PDT 24 1595870000 ps
T100 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2574386939 Jun 21 05:38:03 PM PDT 24 Jun 21 05:38:12 PM PDT 24 1483850000 ps
T101 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2257920361 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:42 PM PDT 24 1487370000 ps
T102 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1947222373 Jun 21 05:38:17 PM PDT 24 Jun 21 05:38:26 PM PDT 24 1514810000 ps
T103 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.276152349 Jun 21 05:37:54 PM PDT 24 Jun 21 05:38:06 PM PDT 24 1483330000 ps
T104 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4176187544 Jun 21 05:38:33 PM PDT 24 Jun 21 05:38:49 PM PDT 24 1505590000 ps
T105 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2783942061 Jun 21 05:38:34 PM PDT 24 Jun 21 05:38:46 PM PDT 24 1398710000 ps
T106 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1777355815 Jun 21 05:38:41 PM PDT 24 Jun 21 05:38:58 PM PDT 24 1559610000 ps
T107 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.248334479 Jun 21 05:38:18 PM PDT 24 Jun 21 05:38:32 PM PDT 24 1507470000 ps
T108 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.851799170 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:38 PM PDT 24 1453950000 ps
T109 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2136214962 Jun 21 05:38:41 PM PDT 24 Jun 21 05:38:50 PM PDT 24 1497570000 ps
T110 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3939009157 Jun 21 05:38:02 PM PDT 24 Jun 21 05:38:12 PM PDT 24 1364190000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.846001869 Jun 21 05:38:36 PM PDT 24 Jun 21 05:38:45 PM PDT 24 1548810000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1851935520 Jun 21 05:38:27 PM PDT 24 Jun 21 05:38:38 PM PDT 24 1468390000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3555953823 Jun 21 05:38:17 PM PDT 24 Jun 21 05:38:27 PM PDT 24 1512450000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3093227724 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:41 PM PDT 24 1462370000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1677646613 Jun 21 05:38:26 PM PDT 24 Jun 21 05:38:34 PM PDT 24 1421090000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2658024688 Jun 21 05:37:52 PM PDT 24 Jun 21 05:38:03 PM PDT 24 1531630000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.939373903 Jun 21 05:38:01 PM PDT 24 Jun 21 05:38:15 PM PDT 24 1526830000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2813393118 Jun 21 05:37:54 PM PDT 24 Jun 21 05:38:10 PM PDT 24 1508110000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1980035143 Jun 21 05:38:27 PM PDT 24 Jun 21 05:38:40 PM PDT 24 1528410000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4005293226 Jun 21 05:38:02 PM PDT 24 Jun 21 05:38:17 PM PDT 24 1660570000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1295993097 Jun 21 05:44:28 PM PDT 24 Jun 21 06:24:26 PM PDT 24 336891030000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2032322518 Jun 21 05:44:35 PM PDT 24 Jun 21 06:18:43 PM PDT 24 336981430000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1898454232 Jun 21 05:44:35 PM PDT 24 Jun 21 06:18:19 PM PDT 24 336838270000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4204363562 Jun 21 05:44:42 PM PDT 24 Jun 21 06:14:53 PM PDT 24 336979030000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2392445478 Jun 21 05:44:33 PM PDT 24 Jun 21 06:18:34 PM PDT 24 336341070000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1916785805 Jun 21 05:44:34 PM PDT 24 Jun 21 06:18:52 PM PDT 24 336781350000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3859286015 Jun 21 05:44:25 PM PDT 24 Jun 21 06:17:40 PM PDT 24 336786210000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.905515489 Jun 21 05:44:33 PM PDT 24 Jun 21 06:17:20 PM PDT 24 336998190000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.829079924 Jun 21 05:44:40 PM PDT 24 Jun 21 06:21:47 PM PDT 24 337022290000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.195873055 Jun 21 05:44:42 PM PDT 24 Jun 21 06:30:00 PM PDT 24 336415330000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.891393200 Jun 21 05:44:42 PM PDT 24 Jun 21 06:19:25 PM PDT 24 336850070000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2928583836 Jun 21 05:44:35 PM PDT 24 Jun 21 06:18:59 PM PDT 24 336967370000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3436057549 Jun 21 05:44:37 PM PDT 24 Jun 21 06:24:07 PM PDT 24 336527110000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.274649929 Jun 21 05:44:41 PM PDT 24 Jun 21 06:18:45 PM PDT 24 336906130000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.121700999 Jun 21 05:44:34 PM PDT 24 Jun 21 06:17:39 PM PDT 24 336929370000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3505262213 Jun 21 05:44:35 PM PDT 24 Jun 21 06:23:24 PM PDT 24 336765850000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1618751437 Jun 21 05:44:40 PM PDT 24 Jun 21 06:11:10 PM PDT 24 336649410000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1039903218 Jun 21 05:44:32 PM PDT 24 Jun 21 06:21:59 PM PDT 24 336414830000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1824718238 Jun 21 05:44:33 PM PDT 24 Jun 21 06:19:26 PM PDT 24 336387190000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2212275955 Jun 21 05:44:35 PM PDT 24 Jun 21 06:16:35 PM PDT 24 336426150000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.496124046 Jun 21 05:44:41 PM PDT 24 Jun 21 06:22:01 PM PDT 24 336680990000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2707695220 Jun 21 05:44:33 PM PDT 24 Jun 21 06:15:30 PM PDT 24 337053070000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1204692859 Jun 21 05:44:42 PM PDT 24 Jun 21 06:18:56 PM PDT 24 336573350000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.208476613 Jun 21 05:44:41 PM PDT 24 Jun 21 06:22:45 PM PDT 24 336960970000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1416453307 Jun 21 05:44:33 PM PDT 24 Jun 21 06:19:50 PM PDT 24 336372030000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2249702442 Jun 21 05:44:34 PM PDT 24 Jun 21 06:17:43 PM PDT 24 336434890000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.160986422 Jun 21 05:44:41 PM PDT 24 Jun 21 06:19:10 PM PDT 24 336829770000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2717736899 Jun 21 05:44:34 PM PDT 24 Jun 21 06:20:44 PM PDT 24 336322150000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3408571276 Jun 21 05:44:42 PM PDT 24 Jun 21 06:22:18 PM PDT 24 337046030000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1048383718 Jun 21 05:44:25 PM PDT 24 Jun 21 06:23:12 PM PDT 24 336375930000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2963223360 Jun 21 05:44:36 PM PDT 24 Jun 21 06:18:25 PM PDT 24 336421030000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3967972118 Jun 21 05:44:43 PM PDT 24 Jun 21 06:13:45 PM PDT 24 336764590000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3529776016 Jun 21 05:44:43 PM PDT 24 Jun 21 06:17:18 PM PDT 24 336880870000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.441905740 Jun 21 05:44:33 PM PDT 24 Jun 21 06:15:20 PM PDT 24 336323310000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1706144644 Jun 21 05:44:41 PM PDT 24 Jun 21 06:19:00 PM PDT 24 336747670000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1222440206 Jun 21 05:44:42 PM PDT 24 Jun 21 06:13:42 PM PDT 24 336779170000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1625906650 Jun 21 05:44:40 PM PDT 24 Jun 21 06:16:32 PM PDT 24 336362530000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.268864018 Jun 21 05:44:33 PM PDT 24 Jun 21 06:20:17 PM PDT 24 336838610000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.20611938 Jun 21 05:44:32 PM PDT 24 Jun 21 06:15:26 PM PDT 24 336452550000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2188233092 Jun 21 05:44:33 PM PDT 24 Jun 21 06:17:25 PM PDT 24 336626610000 ps
T151 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.771642939 Jun 21 05:44:42 PM PDT 24 Jun 21 06:22:16 PM PDT 24 336921310000 ps
T152 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.218603486 Jun 21 05:44:33 PM PDT 24 Jun 21 06:18:44 PM PDT 24 336514370000 ps
T153 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.804526679 Jun 21 05:44:43 PM PDT 24 Jun 21 06:13:49 PM PDT 24 336882530000 ps
T154 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.79608450 Jun 21 05:44:39 PM PDT 24 Jun 21 06:12:56 PM PDT 24 336982550000 ps
T155 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3179135263 Jun 21 05:44:26 PM PDT 24 Jun 21 06:25:45 PM PDT 24 336783470000 ps
T156 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.659240934 Jun 21 05:44:40 PM PDT 24 Jun 21 06:26:46 PM PDT 24 336615210000 ps
T157 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2110249225 Jun 21 05:44:34 PM PDT 24 Jun 21 06:17:04 PM PDT 24 336477730000 ps
T158 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3138710901 Jun 21 05:44:40 PM PDT 24 Jun 21 06:21:35 PM PDT 24 337005830000 ps
T159 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.701098420 Jun 21 05:44:41 PM PDT 24 Jun 21 06:22:39 PM PDT 24 337068470000 ps
T160 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3145328049 Jun 21 05:44:33 PM PDT 24 Jun 21 06:19:14 PM PDT 24 336885950000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2744098395 Jun 21 05:49:32 PM PDT 24 Jun 21 06:20:50 PM PDT 24 336449370000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2241003768 Jun 21 05:50:15 PM PDT 24 Jun 21 06:27:40 PM PDT 24 336470590000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1318091553 Jun 21 05:49:32 PM PDT 24 Jun 21 06:24:47 PM PDT 24 336796430000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1170186103 Jun 21 05:49:33 PM PDT 24 Jun 21 06:29:46 PM PDT 24 337100630000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4144483468 Jun 21 05:49:47 PM PDT 24 Jun 21 06:28:42 PM PDT 24 336496590000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1381012899 Jun 21 05:49:47 PM PDT 24 Jun 21 06:19:21 PM PDT 24 336999830000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1542498626 Jun 21 05:49:10 PM PDT 24 Jun 21 06:18:46 PM PDT 24 337036930000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1204988475 Jun 21 05:49:25 PM PDT 24 Jun 21 06:29:24 PM PDT 24 336726350000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1079443808 Jun 21 05:49:47 PM PDT 24 Jun 21 06:22:58 PM PDT 24 337010650000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1070994422 Jun 21 05:49:47 PM PDT 24 Jun 21 06:28:35 PM PDT 24 336843690000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.972749276 Jun 21 05:50:29 PM PDT 24 Jun 21 06:27:22 PM PDT 24 336879370000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.864360713 Jun 21 05:50:20 PM PDT 24 Jun 21 06:27:11 PM PDT 24 336785830000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2078998108 Jun 21 05:50:31 PM PDT 24 Jun 21 06:30:02 PM PDT 24 336510210000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2859605972 Jun 21 05:49:40 PM PDT 24 Jun 21 06:22:52 PM PDT 24 336451890000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2171328308 Jun 21 05:49:10 PM PDT 24 Jun 21 06:28:58 PM PDT 24 336638750000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.670891374 Jun 21 05:49:10 PM PDT 24 Jun 21 06:22:45 PM PDT 24 336851510000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.583071204 Jun 21 05:49:49 PM PDT 24 Jun 21 06:19:30 PM PDT 24 336668970000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.703856732 Jun 21 05:50:00 PM PDT 24 Jun 21 06:29:50 PM PDT 24 336880710000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1559192292 Jun 21 05:49:46 PM PDT 24 Jun 21 06:26:50 PM PDT 24 336768650000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3305181351 Jun 21 05:49:53 PM PDT 24 Jun 21 06:23:52 PM PDT 24 337029570000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3204139616 Jun 21 05:49:45 PM PDT 24 Jun 21 06:27:00 PM PDT 24 336623490000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3273829311 Jun 21 05:50:17 PM PDT 24 Jun 21 06:25:42 PM PDT 24 336500230000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1934540115 Jun 21 05:49:33 PM PDT 24 Jun 21 06:14:46 PM PDT 24 337079730000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2633884500 Jun 21 05:49:35 PM PDT 24 Jun 21 06:34:48 PM PDT 24 336749590000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2556677565 Jun 21 05:50:14 PM PDT 24 Jun 21 06:23:53 PM PDT 24 336983590000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3939697234 Jun 21 05:49:23 PM PDT 24 Jun 21 06:21:33 PM PDT 24 337019750000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2657888260 Jun 21 05:49:24 PM PDT 24 Jun 21 06:17:17 PM PDT 24 337042190000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1605438743 Jun 21 05:50:02 PM PDT 24 Jun 21 06:21:14 PM PDT 24 336335770000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2083114455 Jun 21 05:50:22 PM PDT 24 Jun 21 06:23:57 PM PDT 24 336909870000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1167044943 Jun 21 05:49:19 PM PDT 24 Jun 21 06:29:43 PM PDT 24 336481990000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3470504145 Jun 21 05:50:01 PM PDT 24 Jun 21 06:21:11 PM PDT 24 336743230000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3770585185 Jun 21 05:50:10 PM PDT 24 Jun 21 06:32:02 PM PDT 24 336924090000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.142921431 Jun 21 05:49:10 PM PDT 24 Jun 21 06:16:32 PM PDT 24 336702670000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3153236303 Jun 21 05:49:32 PM PDT 24 Jun 21 06:26:00 PM PDT 24 336954270000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4182992133 Jun 21 05:50:14 PM PDT 24 Jun 21 06:26:45 PM PDT 24 336833590000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.467922784 Jun 21 05:49:54 PM PDT 24 Jun 21 06:21:06 PM PDT 24 336526050000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1658961894 Jun 21 05:50:24 PM PDT 24 Jun 21 06:29:04 PM PDT 24 336978870000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3776715858 Jun 21 05:50:15 PM PDT 24 Jun 21 06:23:51 PM PDT 24 336847890000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.461539847 Jun 21 05:50:01 PM PDT 24 Jun 21 06:25:19 PM PDT 24 336807830000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3957067325 Jun 21 05:49:20 PM PDT 24 Jun 21 06:25:02 PM PDT 24 336449410000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2779463709 Jun 21 05:50:09 PM PDT 24 Jun 21 06:32:16 PM PDT 24 336886770000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3600461863 Jun 21 05:49:50 PM PDT 24 Jun 21 06:34:25 PM PDT 24 336593290000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1718062030 Jun 21 05:50:00 PM PDT 24 Jun 21 06:26:08 PM PDT 24 336656930000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.340889167 Jun 21 05:50:00 PM PDT 24 Jun 21 06:31:45 PM PDT 24 336556930000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4005275146 Jun 21 05:50:24 PM PDT 24 Jun 21 06:29:19 PM PDT 24 337101190000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1143060925 Jun 21 05:49:25 PM PDT 24 Jun 21 06:28:14 PM PDT 24 337147870000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3668433655 Jun 21 05:49:46 PM PDT 24 Jun 21 06:22:12 PM PDT 24 336800510000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2177054186 Jun 21 05:49:16 PM PDT 24 Jun 21 06:25:58 PM PDT 24 337043990000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3360841352 Jun 21 05:49:19 PM PDT 24 Jun 21 06:29:51 PM PDT 24 336665750000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.960571947 Jun 21 05:49:32 PM PDT 24 Jun 21 06:25:35 PM PDT 24 337087490000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3320316638
Short name T2
Test name
Test status
Simulation time 1497490000 ps
CPU time 4.91 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:25 PM PDT 24
Peak memory 164948 kb
Host smart-0baf389a-cc63-4c6d-bbd1-a13357e89be5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3320316638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3320316638
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3859286015
Short name T20
Test name
Test status
Simulation time 336786210000 ps
CPU time 812.66 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 06:17:40 PM PDT 24
Peak memory 160812 kb
Host smart-87dc3a54-8e20-423d-a1fb-571f07207aa9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3859286015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3859286015
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1318091553
Short name T33
Test name
Test status
Simulation time 336796430000 ps
CPU time 874.83 seconds
Started Jun 21 05:49:32 PM PDT 24
Finished Jun 21 06:24:47 PM PDT 24
Peak memory 160808 kb
Host smart-69e1a389-9b1f-4052-8db3-31c04b9cf0c6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1318091553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1318091553
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3498785146
Short name T29
Test name
Test status
Simulation time 1588310000 ps
CPU time 4.1 seconds
Started Jun 21 05:37:43 PM PDT 24
Finished Jun 21 05:37:54 PM PDT 24
Peak memory 164924 kb
Host smart-0e64d475-e9bc-441a-a6c4-392e3d45584b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3498785146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3498785146
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.670891374
Short name T166
Test name
Test status
Simulation time 336851510000 ps
CPU time 826.91 seconds
Started Jun 21 05:49:10 PM PDT 24
Finished Jun 21 06:22:45 PM PDT 24
Peak memory 160792 kb
Host smart-c945d379-d2af-4a99-a96e-edbf1d166934
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=670891374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.670891374
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2171328308
Short name T165
Test name
Test status
Simulation time 336638750000 ps
CPU time 942.12 seconds
Started Jun 21 05:49:10 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 160792 kb
Host smart-68d77983-ebe4-4f59-9ce0-534faf91427b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2171328308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2171328308
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1143060925
Short name T196
Test name
Test status
Simulation time 337147870000 ps
CPU time 952.55 seconds
Started Jun 21 05:49:25 PM PDT 24
Finished Jun 21 06:28:14 PM PDT 24
Peak memory 160808 kb
Host smart-5e504b53-23d5-46b5-ada9-0484d00f37e0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1143060925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1143060925
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3939697234
Short name T176
Test name
Test status
Simulation time 337019750000 ps
CPU time 804.65 seconds
Started Jun 21 05:49:23 PM PDT 24
Finished Jun 21 06:21:33 PM PDT 24
Peak memory 160916 kb
Host smart-f3e031a8-1195-461f-bb6d-28aa9c56bd8e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3939697234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3939697234
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3153236303
Short name T184
Test name
Test status
Simulation time 336954270000 ps
CPU time 876.39 seconds
Started Jun 21 05:49:32 PM PDT 24
Finished Jun 21 06:26:00 PM PDT 24
Peak memory 160860 kb
Host smart-b79baeea-8698-400a-ba7f-6995155fc62f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3153236303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3153236303
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2633884500
Short name T174
Test name
Test status
Simulation time 336749590000 ps
CPU time 1059.99 seconds
Started Jun 21 05:49:35 PM PDT 24
Finished Jun 21 06:34:48 PM PDT 24
Peak memory 160812 kb
Host smart-bad9f653-7620-4056-9cb6-a883df12e01c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2633884500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2633884500
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2744098395
Short name T31
Test name
Test status
Simulation time 336449370000 ps
CPU time 774.25 seconds
Started Jun 21 05:49:32 PM PDT 24
Finished Jun 21 06:20:50 PM PDT 24
Peak memory 160748 kb
Host smart-0ead9a23-544d-4e9a-bc78-ce213149aeb3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2744098395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2744098395
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.960571947
Short name T200
Test name
Test status
Simulation time 337087490000 ps
CPU time 879.12 seconds
Started Jun 21 05:49:32 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 160816 kb
Host smart-9c997395-31a8-4b5d-979f-119d4a527044
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=960571947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.960571947
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1170186103
Short name T34
Test name
Test status
Simulation time 337100630000 ps
CPU time 990.68 seconds
Started Jun 21 05:49:33 PM PDT 24
Finished Jun 21 06:29:46 PM PDT 24
Peak memory 160808 kb
Host smart-35890470-f033-41cd-a989-b3d4276687e8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1170186103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1170186103
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1934540115
Short name T173
Test name
Test status
Simulation time 337079730000 ps
CPU time 587.98 seconds
Started Jun 21 05:49:33 PM PDT 24
Finished Jun 21 06:14:46 PM PDT 24
Peak memory 160832 kb
Host smart-05367434-5507-4793-a074-bd8500bb97a2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1934540115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1934540115
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2859605972
Short name T164
Test name
Test status
Simulation time 336451890000 ps
CPU time 819.77 seconds
Started Jun 21 05:49:40 PM PDT 24
Finished Jun 21 06:22:52 PM PDT 24
Peak memory 160820 kb
Host smart-607a9e5b-5eb3-4533-85c6-1a149edb9d00
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2859605972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2859605972
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1542498626
Short name T37
Test name
Test status
Simulation time 337036930000 ps
CPU time 719.79 seconds
Started Jun 21 05:49:10 PM PDT 24
Finished Jun 21 06:18:46 PM PDT 24
Peak memory 160804 kb
Host smart-cfc04580-34cc-49b2-a702-10717841439c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1542498626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1542498626
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3204139616
Short name T171
Test name
Test status
Simulation time 336623490000 ps
CPU time 898.88 seconds
Started Jun 21 05:49:45 PM PDT 24
Finished Jun 21 06:27:00 PM PDT 24
Peak memory 160812 kb
Host smart-8b553b10-ec72-499a-9057-7ccbe03a910c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3204139616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3204139616
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3600461863
Short name T192
Test name
Test status
Simulation time 336593290000 ps
CPU time 1039.89 seconds
Started Jun 21 05:49:50 PM PDT 24
Finished Jun 21 06:34:25 PM PDT 24
Peak memory 160812 kb
Host smart-f5b87e0e-343f-4171-9443-55fcf3d5c378
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3600461863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3600461863
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1559192292
Short name T169
Test name
Test status
Simulation time 336768650000 ps
CPU time 911.14 seconds
Started Jun 21 05:49:46 PM PDT 24
Finished Jun 21 06:26:50 PM PDT 24
Peak memory 160808 kb
Host smart-28cf721e-b2b4-44c6-bd91-83d7bd708b72
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1559192292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1559192292
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1381012899
Short name T36
Test name
Test status
Simulation time 336999830000 ps
CPU time 717.47 seconds
Started Jun 21 05:49:47 PM PDT 24
Finished Jun 21 06:19:21 PM PDT 24
Peak memory 160812 kb
Host smart-0a069179-fba7-4c14-97c4-47a6d5996f9f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1381012899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1381012899
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1079443808
Short name T39
Test name
Test status
Simulation time 337010650000 ps
CPU time 816.14 seconds
Started Jun 21 05:49:47 PM PDT 24
Finished Jun 21 06:22:58 PM PDT 24
Peak memory 160824 kb
Host smart-756e7912-d097-49c2-b608-880557ad4213
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1079443808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1079443808
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4144483468
Short name T35
Test name
Test status
Simulation time 336496590000 ps
CPU time 952.94 seconds
Started Jun 21 05:49:47 PM PDT 24
Finished Jun 21 06:28:42 PM PDT 24
Peak memory 160808 kb
Host smart-433f43e2-3098-4e1e-a020-21a8b1aae537
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4144483468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4144483468
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3668433655
Short name T197
Test name
Test status
Simulation time 336800510000 ps
CPU time 778.73 seconds
Started Jun 21 05:49:46 PM PDT 24
Finished Jun 21 06:22:12 PM PDT 24
Peak memory 160824 kb
Host smart-1a358744-4ef2-410e-a833-41611d19a375
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668433655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3668433655
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.583071204
Short name T167
Test name
Test status
Simulation time 336668970000 ps
CPU time 728.08 seconds
Started Jun 21 05:49:49 PM PDT 24
Finished Jun 21 06:19:30 PM PDT 24
Peak memory 160912 kb
Host smart-731c4bbb-090b-4806-b96a-d886ff29d624
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=583071204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.583071204
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1070994422
Short name T40
Test name
Test status
Simulation time 336843690000 ps
CPU time 952.41 seconds
Started Jun 21 05:49:47 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 160808 kb
Host smart-9939da2a-281f-435c-9184-233c2567e91c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1070994422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.1070994422
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.467922784
Short name T186
Test name
Test status
Simulation time 336526050000 ps
CPU time 752.14 seconds
Started Jun 21 05:49:54 PM PDT 24
Finished Jun 21 06:21:06 PM PDT 24
Peak memory 160800 kb
Host smart-212cac5f-7b04-4741-9b01-d8fb14917f81
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=467922784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.467922784
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.142921431
Short name T183
Test name
Test status
Simulation time 336702670000 ps
CPU time 645.81 seconds
Started Jun 21 05:49:10 PM PDT 24
Finished Jun 21 06:16:32 PM PDT 24
Peak memory 160804 kb
Host smart-c650187c-45fe-46b7-a2f5-c09db8b3e391
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=142921431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.142921431
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3305181351
Short name T170
Test name
Test status
Simulation time 337029570000 ps
CPU time 836.88 seconds
Started Jun 21 05:49:53 PM PDT 24
Finished Jun 21 06:23:52 PM PDT 24
Peak memory 160832 kb
Host smart-450100e1-eac5-4276-b0d5-e1d5385d074d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3305181351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3305181351
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.340889167
Short name T194
Test name
Test status
Simulation time 336556930000 ps
CPU time 988.21 seconds
Started Jun 21 05:50:00 PM PDT 24
Finished Jun 21 06:31:45 PM PDT 24
Peak memory 160812 kb
Host smart-e8f9ab6b-395a-4103-b11e-c312b703d6cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=340889167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.340889167
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1718062030
Short name T193
Test name
Test status
Simulation time 336656930000 ps
CPU time 870.66 seconds
Started Jun 21 05:50:00 PM PDT 24
Finished Jun 21 06:26:08 PM PDT 24
Peak memory 160856 kb
Host smart-d7065bbe-0eef-4cbe-b573-d50c12089845
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1718062030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1718062030
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.461539847
Short name T189
Test name
Test status
Simulation time 336807830000 ps
CPU time 867.13 seconds
Started Jun 21 05:50:01 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 160800 kb
Host smart-209a6aeb-559f-44a4-b766-7c5b28deb870
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=461539847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.461539847
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1605438743
Short name T178
Test name
Test status
Simulation time 336335770000 ps
CPU time 770.26 seconds
Started Jun 21 05:50:02 PM PDT 24
Finished Jun 21 06:21:14 PM PDT 24
Peak memory 160776 kb
Host smart-92131195-552f-452c-812f-20e8cbb9ad26
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1605438743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1605438743
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3470504145
Short name T181
Test name
Test status
Simulation time 336743230000 ps
CPU time 768.1 seconds
Started Jun 21 05:50:01 PM PDT 24
Finished Jun 21 06:21:11 PM PDT 24
Peak memory 160748 kb
Host smart-734d2527-9ee9-4644-a5dc-3e1751fa39e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3470504145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3470504145
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.703856732
Short name T168
Test name
Test status
Simulation time 336880710000 ps
CPU time 945.8 seconds
Started Jun 21 05:50:00 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 160792 kb
Host smart-c758af00-6898-454d-9204-17da3ef9d89a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=703856732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.703856732
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3770585185
Short name T182
Test name
Test status
Simulation time 336924090000 ps
CPU time 990.81 seconds
Started Jun 21 05:50:10 PM PDT 24
Finished Jun 21 06:32:02 PM PDT 24
Peak memory 160820 kb
Host smart-18c1608c-254d-4dc2-a378-fdbd3d1f1768
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3770585185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3770585185
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2779463709
Short name T191
Test name
Test status
Simulation time 336886770000 ps
CPU time 1001.01 seconds
Started Jun 21 05:50:09 PM PDT 24
Finished Jun 21 06:32:16 PM PDT 24
Peak memory 160820 kb
Host smart-fcfdc652-de6a-4648-b38c-65f97f038145
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2779463709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2779463709
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3776715858
Short name T188
Test name
Test status
Simulation time 336847890000 ps
CPU time 821.13 seconds
Started Jun 21 05:50:15 PM PDT 24
Finished Jun 21 06:23:51 PM PDT 24
Peak memory 160812 kb
Host smart-5e4234e4-bd8c-4411-af8b-bcea0b27fc59
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3776715858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3776715858
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1167044943
Short name T180
Test name
Test status
Simulation time 336481990000 ps
CPU time 950.77 seconds
Started Jun 21 05:49:19 PM PDT 24
Finished Jun 21 06:29:43 PM PDT 24
Peak memory 160792 kb
Host smart-e6e17d75-1888-498d-b5eb-a6499dfb0348
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1167044943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1167044943
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2556677565
Short name T175
Test name
Test status
Simulation time 336983590000 ps
CPU time 813.9 seconds
Started Jun 21 05:50:14 PM PDT 24
Finished Jun 21 06:23:53 PM PDT 24
Peak memory 160840 kb
Host smart-46e55ec4-7281-40ae-acad-c709d58fadde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2556677565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2556677565
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4182992133
Short name T185
Test name
Test status
Simulation time 336833590000 ps
CPU time 899.46 seconds
Started Jun 21 05:50:14 PM PDT 24
Finished Jun 21 06:26:45 PM PDT 24
Peak memory 160744 kb
Host smart-8b8f1e61-9a9a-4111-a397-5bf396516a98
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4182992133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4182992133
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2241003768
Short name T32
Test name
Test status
Simulation time 336470590000 ps
CPU time 916.46 seconds
Started Jun 21 05:50:15 PM PDT 24
Finished Jun 21 06:27:40 PM PDT 24
Peak memory 160812 kb
Host smart-16dcd91e-03be-4a65-83b3-a5cfa3aa8cfe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2241003768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2241003768
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3273829311
Short name T172
Test name
Test status
Simulation time 336500230000 ps
CPU time 862.2 seconds
Started Jun 21 05:50:17 PM PDT 24
Finished Jun 21 06:25:42 PM PDT 24
Peak memory 160812 kb
Host smart-32898c42-0381-4ff2-af3a-0e08496de8d3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3273829311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3273829311
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.864360713
Short name T162
Test name
Test status
Simulation time 336785830000 ps
CPU time 886.81 seconds
Started Jun 21 05:50:20 PM PDT 24
Finished Jun 21 06:27:11 PM PDT 24
Peak memory 160804 kb
Host smart-31d2141b-9483-435d-8798-5dfcbd3a429f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=864360713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.864360713
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4005275146
Short name T195
Test name
Test status
Simulation time 337101190000 ps
CPU time 942.67 seconds
Started Jun 21 05:50:24 PM PDT 24
Finished Jun 21 06:29:19 PM PDT 24
Peak memory 160816 kb
Host smart-c0de2004-1852-44a4-8f22-f95885b8c9bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4005275146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4005275146
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1658961894
Short name T187
Test name
Test status
Simulation time 336978870000 ps
CPU time 938.86 seconds
Started Jun 21 05:50:24 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 160816 kb
Host smart-a31ee672-d2c0-420d-813a-b14bc1cb0978
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1658961894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1658961894
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2083114455
Short name T179
Test name
Test status
Simulation time 336909870000 ps
CPU time 819.75 seconds
Started Jun 21 05:50:22 PM PDT 24
Finished Jun 21 06:23:57 PM PDT 24
Peak memory 160824 kb
Host smart-20ed3e36-cfc9-4e8e-b43b-2fd83cac7e09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2083114455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2083114455
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2078998108
Short name T163
Test name
Test status
Simulation time 336510210000 ps
CPU time 962.22 seconds
Started Jun 21 05:50:31 PM PDT 24
Finished Jun 21 06:30:02 PM PDT 24
Peak memory 160828 kb
Host smart-d9640a23-de0f-44f0-9c18-8e618dc5dffb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2078998108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2078998108
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.972749276
Short name T161
Test name
Test status
Simulation time 336879370000 ps
CPU time 906.57 seconds
Started Jun 21 05:50:29 PM PDT 24
Finished Jun 21 06:27:22 PM PDT 24
Peak memory 160804 kb
Host smart-e7effd24-c043-42aa-87c5-c00e4353b12d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=972749276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.972749276
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3957067325
Short name T190
Test name
Test status
Simulation time 336449410000 ps
CPU time 866.7 seconds
Started Jun 21 05:49:20 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 160804 kb
Host smart-e878ed97-bf4a-4b07-adc7-ec90fb17b46e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3957067325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3957067325
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3360841352
Short name T199
Test name
Test status
Simulation time 336665750000 ps
CPU time 951.53 seconds
Started Jun 21 05:49:19 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 160792 kb
Host smart-2c0f8a81-f046-48ed-8d37-99ee1f4c818b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3360841352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3360841352
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2177054186
Short name T198
Test name
Test status
Simulation time 337043990000 ps
CPU time 894.04 seconds
Started Jun 21 05:49:16 PM PDT 24
Finished Jun 21 06:25:58 PM PDT 24
Peak memory 160736 kb
Host smart-bba4e108-db8e-4302-8c3e-ba4362b3f507
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2177054186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2177054186
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1204988475
Short name T38
Test name
Test status
Simulation time 336726350000 ps
CPU time 983.98 seconds
Started Jun 21 05:49:25 PM PDT 24
Finished Jun 21 06:29:24 PM PDT 24
Peak memory 160800 kb
Host smart-a6825ba2-cb50-4b37-9f24-8b5ccdd29efd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1204988475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1204988475
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2657888260
Short name T177
Test name
Test status
Simulation time 337042190000 ps
CPU time 685.82 seconds
Started Jun 21 05:49:24 PM PDT 24
Finished Jun 21 06:17:17 PM PDT 24
Peak memory 160708 kb
Host smart-b32fdbf1-0538-4aea-ba13-7f952aa5a549
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2657888260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2657888260
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1048383718
Short name T140
Test name
Test status
Simulation time 336375930000 ps
CPU time 966.55 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 06:23:12 PM PDT 24
Peak memory 160812 kb
Host smart-93e7ad5f-5860-4f18-b8fc-7f443d448279
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1048383718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1048383718
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.268864018
Short name T148
Test name
Test status
Simulation time 336838610000 ps
CPU time 860.2 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:20:17 PM PDT 24
Peak memory 160852 kb
Host smart-6ba0a3ce-d017-41f2-9e7a-a512b319d2c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=268864018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.268864018
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1898454232
Short name T16
Test name
Test status
Simulation time 336838270000 ps
CPU time 831.07 seconds
Started Jun 21 05:44:35 PM PDT 24
Finished Jun 21 06:18:19 PM PDT 24
Peak memory 160812 kb
Host smart-da8c1e9d-19ee-4a81-a055-584cf8693ee7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1898454232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1898454232
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2188233092
Short name T150
Test name
Test status
Simulation time 336626610000 ps
CPU time 815.1 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:17:25 PM PDT 24
Peak memory 160812 kb
Host smart-61eaa804-dec2-4880-ad59-452d6ca93133
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2188233092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2188233092
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.121700999
Short name T125
Test name
Test status
Simulation time 336929370000 ps
CPU time 808.09 seconds
Started Jun 21 05:44:34 PM PDT 24
Finished Jun 21 06:17:39 PM PDT 24
Peak memory 160784 kb
Host smart-3b10b05e-fbe2-4321-8d95-e5749bbc862b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=121700999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.121700999
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3145328049
Short name T160
Test name
Test status
Simulation time 336885950000 ps
CPU time 864.84 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:19:14 PM PDT 24
Peak memory 160812 kb
Host smart-0dd21606-bdab-4015-86db-5947e8544920
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3145328049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3145328049
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2717736899
Short name T138
Test name
Test status
Simulation time 336322150000 ps
CPU time 875.17 seconds
Started Jun 21 05:44:34 PM PDT 24
Finished Jun 21 06:20:44 PM PDT 24
Peak memory 160808 kb
Host smart-521ad77b-af2d-40f6-9645-37f6611ac5a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2717736899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2717736899
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.905515489
Short name T21
Test name
Test status
Simulation time 336998190000 ps
CPU time 816.27 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:17:20 PM PDT 24
Peak memory 160800 kb
Host smart-4b80ae82-2d2c-4642-a9bd-e0f79757e426
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=905515489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.905515489
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.218603486
Short name T152
Test name
Test status
Simulation time 336514370000 ps
CPU time 847.43 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:18:44 PM PDT 24
Peak memory 160816 kb
Host smart-ff4ba9b5-c906-4c37-95cf-864e087ed46f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=218603486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.218603486
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2707695220
Short name T132
Test name
Test status
Simulation time 337053070000 ps
CPU time 749.96 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:15:30 PM PDT 24
Peak memory 160824 kb
Host smart-642c7e53-cb60-4acb-b781-92ed77fa9e97
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2707695220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2707695220
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1916785805
Short name T19
Test name
Test status
Simulation time 336781350000 ps
CPU time 849.07 seconds
Started Jun 21 05:44:34 PM PDT 24
Finished Jun 21 06:18:52 PM PDT 24
Peak memory 160812 kb
Host smart-bc254877-dbb1-409d-8e97-79f2b94010ce
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1916785805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1916785805
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1295993097
Short name T14
Test name
Test status
Simulation time 336891030000 ps
CPU time 968.12 seconds
Started Jun 21 05:44:28 PM PDT 24
Finished Jun 21 06:24:26 PM PDT 24
Peak memory 160816 kb
Host smart-8df8f3b1-ded2-4f39-b4d4-714160609cd2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1295993097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1295993097
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2963223360
Short name T141
Test name
Test status
Simulation time 336421030000 ps
CPU time 820.49 seconds
Started Jun 21 05:44:36 PM PDT 24
Finished Jun 21 06:18:25 PM PDT 24
Peak memory 160832 kb
Host smart-cf13945a-8869-4ebd-b38e-06896f8c8f98
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963223360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2963223360
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3436057549
Short name T123
Test name
Test status
Simulation time 336527110000 ps
CPU time 952.5 seconds
Started Jun 21 05:44:37 PM PDT 24
Finished Jun 21 06:24:07 PM PDT 24
Peak memory 160824 kb
Host smart-8c2fe214-89bb-4f66-97af-847742029243
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3436057549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3436057549
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.441905740
Short name T144
Test name
Test status
Simulation time 336323310000 ps
CPU time 743.6 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:15:20 PM PDT 24
Peak memory 160816 kb
Host smart-ca9811de-c47b-4701-8afd-e95efc1cc297
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=441905740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.441905740
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1039903218
Short name T128
Test name
Test status
Simulation time 336414830000 ps
CPU time 913.52 seconds
Started Jun 21 05:44:32 PM PDT 24
Finished Jun 21 06:21:59 PM PDT 24
Peak memory 160812 kb
Host smart-41266e9f-ce3c-4833-a018-79fd36eb6952
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1039903218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1039903218
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2392445478
Short name T18
Test name
Test status
Simulation time 336341070000 ps
CPU time 830.87 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:18:34 PM PDT 24
Peak memory 160824 kb
Host smart-7b91ff46-4f74-4aad-8033-901679a76ea8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2392445478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2392445478
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2110249225
Short name T157
Test name
Test status
Simulation time 336477730000 ps
CPU time 802.37 seconds
Started Jun 21 05:44:34 PM PDT 24
Finished Jun 21 06:17:04 PM PDT 24
Peak memory 160792 kb
Host smart-bb8adcc5-5e8b-4858-9938-190c75b6536b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2110249225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2110249225
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2249702442
Short name T136
Test name
Test status
Simulation time 336434890000 ps
CPU time 817.54 seconds
Started Jun 21 05:44:34 PM PDT 24
Finished Jun 21 06:17:43 PM PDT 24
Peak memory 160824 kb
Host smart-e9f2202e-c0d0-467e-8334-10cebfe726c1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2249702442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2249702442
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3505262213
Short name T126
Test name
Test status
Simulation time 336765850000 ps
CPU time 963.22 seconds
Started Jun 21 05:44:35 PM PDT 24
Finished Jun 21 06:23:24 PM PDT 24
Peak memory 160812 kb
Host smart-bdf29309-3d71-449c-b1e4-d56f22ce7690
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3505262213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3505262213
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1618751437
Short name T127
Test name
Test status
Simulation time 336649410000 ps
CPU time 638.47 seconds
Started Jun 21 05:44:40 PM PDT 24
Finished Jun 21 06:11:10 PM PDT 24
Peak memory 160836 kb
Host smart-dc5e1615-3f71-401d-ba63-e92b6cd38dbd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1618751437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1618751437
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3408571276
Short name T139
Test name
Test status
Simulation time 337046030000 ps
CPU time 913.83 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:22:18 PM PDT 24
Peak memory 160744 kb
Host smart-79790ecf-10d7-47fe-a04a-270ed91b6c24
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408571276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3408571276
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3179135263
Short name T155
Test name
Test status
Simulation time 336783470000 ps
CPU time 984.68 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 160788 kb
Host smart-148d95b0-b9df-497f-8f75-254e7f4ee284
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3179135263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3179135263
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3967972118
Short name T142
Test name
Test status
Simulation time 336764590000 ps
CPU time 688.42 seconds
Started Jun 21 05:44:43 PM PDT 24
Finished Jun 21 06:13:45 PM PDT 24
Peak memory 160824 kb
Host smart-010ec362-ce8b-448e-97b0-5f83b5668c7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3967972118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3967972118
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3138710901
Short name T158
Test name
Test status
Simulation time 337005830000 ps
CPU time 905.69 seconds
Started Jun 21 05:44:40 PM PDT 24
Finished Jun 21 06:21:35 PM PDT 24
Peak memory 160812 kb
Host smart-b8da9524-db03-4abd-9a8b-978ac188f637
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3138710901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3138710901
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.195873055
Short name T23
Test name
Test status
Simulation time 336415330000 ps
CPU time 1050.14 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:30:00 PM PDT 24
Peak memory 160804 kb
Host smart-feca0327-fa5d-4b30-85ad-1d3af7e72f3c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=195873055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.195873055
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1625906650
Short name T147
Test name
Test status
Simulation time 336362530000 ps
CPU time 788.18 seconds
Started Jun 21 05:44:40 PM PDT 24
Finished Jun 21 06:16:32 PM PDT 24
Peak memory 160812 kb
Host smart-658d883c-8c9c-4209-96ba-911d355d12e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1625906650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1625906650
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1204692859
Short name T133
Test name
Test status
Simulation time 336573350000 ps
CPU time 847.6 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:18:56 PM PDT 24
Peak memory 160816 kb
Host smart-f31b6295-a5df-437c-a301-eee6c371683e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1204692859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1204692859
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.496124046
Short name T131
Test name
Test status
Simulation time 336680990000 ps
CPU time 925.23 seconds
Started Jun 21 05:44:41 PM PDT 24
Finished Jun 21 06:22:01 PM PDT 24
Peak memory 160804 kb
Host smart-8287fec3-639a-4416-bf77-bc609ba15fa2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=496124046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.496124046
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.160986422
Short name T137
Test name
Test status
Simulation time 336829770000 ps
CPU time 829.09 seconds
Started Jun 21 05:44:41 PM PDT 24
Finished Jun 21 06:19:10 PM PDT 24
Peak memory 160800 kb
Host smart-e809a298-ec55-4306-a160-88be179dc747
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=160986422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.160986422
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.804526679
Short name T153
Test name
Test status
Simulation time 336882530000 ps
CPU time 691.64 seconds
Started Jun 21 05:44:43 PM PDT 24
Finished Jun 21 06:13:49 PM PDT 24
Peak memory 160816 kb
Host smart-404db633-76ab-45d5-bfa6-17a5258e74a1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=804526679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.804526679
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.208476613
Short name T134
Test name
Test status
Simulation time 336960970000 ps
CPU time 939.91 seconds
Started Jun 21 05:44:41 PM PDT 24
Finished Jun 21 06:22:45 PM PDT 24
Peak memory 160804 kb
Host smart-c34f6843-e9ee-4f1c-88b7-2995bc063504
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=208476613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.208476613
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1706144644
Short name T145
Test name
Test status
Simulation time 336747670000 ps
CPU time 830.89 seconds
Started Jun 21 05:44:41 PM PDT 24
Finished Jun 21 06:19:00 PM PDT 24
Peak memory 160840 kb
Host smart-45a59ad7-32a1-4872-bf78-a7757b409281
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1706144644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1706144644
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1416453307
Short name T135
Test name
Test status
Simulation time 336372030000 ps
CPU time 854.8 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:19:50 PM PDT 24
Peak memory 160816 kb
Host smart-1b29d678-70b9-4e1b-87fa-e11bbee05cef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1416453307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1416453307
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.771642939
Short name T151
Test name
Test status
Simulation time 336921310000 ps
CPU time 891.98 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:22:16 PM PDT 24
Peak memory 160808 kb
Host smart-33ece22e-d215-4daa-9686-f4da55f8c125
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=771642939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.771642939
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.79608450
Short name T154
Test name
Test status
Simulation time 336982550000 ps
CPU time 691.14 seconds
Started Jun 21 05:44:39 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 160796 kb
Host smart-7cf89494-d401-4b67-8072-fc326c00c2a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=79608450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.79608450
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.701098420
Short name T159
Test name
Test status
Simulation time 337068470000 ps
CPU time 899.3 seconds
Started Jun 21 05:44:41 PM PDT 24
Finished Jun 21 06:22:39 PM PDT 24
Peak memory 160804 kb
Host smart-467e93f2-dc1c-4073-8992-d13cb85fe252
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=701098420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.701098420
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.274649929
Short name T124
Test name
Test status
Simulation time 336906130000 ps
CPU time 836.73 seconds
Started Jun 21 05:44:41 PM PDT 24
Finished Jun 21 06:18:45 PM PDT 24
Peak memory 160800 kb
Host smart-35cafef9-b65e-4e35-a772-09ed67af0d7c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=274649929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.274649929
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.829079924
Short name T22
Test name
Test status
Simulation time 337022290000 ps
CPU time 927.14 seconds
Started Jun 21 05:44:40 PM PDT 24
Finished Jun 21 06:21:47 PM PDT 24
Peak memory 160804 kb
Host smart-485ca709-bd9e-4ead-a4c5-5b0d73a609e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=829079924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.829079924
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1222440206
Short name T146
Test name
Test status
Simulation time 336779170000 ps
CPU time 689.21 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:13:42 PM PDT 24
Peak memory 160824 kb
Host smart-2e0e59ba-5068-4e2c-9972-b6bd5320ecc5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1222440206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1222440206
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.659240934
Short name T156
Test name
Test status
Simulation time 336615210000 ps
CPU time 991.95 seconds
Started Jun 21 05:44:40 PM PDT 24
Finished Jun 21 06:26:46 PM PDT 24
Peak memory 160812 kb
Host smart-1071b6b9-fa29-4ff3-bd12-3dc070bb4f6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=659240934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.659240934
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4204363562
Short name T17
Test name
Test status
Simulation time 336979030000 ps
CPU time 729.17 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:14:53 PM PDT 24
Peak memory 160780 kb
Host smart-78adc6f8-c438-48f9-873c-b4757b3cffb5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4204363562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4204363562
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3529776016
Short name T143
Test name
Test status
Simulation time 336880870000 ps
CPU time 803.23 seconds
Started Jun 21 05:44:43 PM PDT 24
Finished Jun 21 06:17:18 PM PDT 24
Peak memory 160792 kb
Host smart-7f4ac469-f1e5-474a-b85c-0a88626b0122
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3529776016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3529776016
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.891393200
Short name T121
Test name
Test status
Simulation time 336850070000 ps
CPU time 836.04 seconds
Started Jun 21 05:44:42 PM PDT 24
Finished Jun 21 06:19:25 PM PDT 24
Peak memory 160832 kb
Host smart-f171ae43-6c37-4140-8f2e-01cf4c4a1da9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=891393200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.891393200
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2928583836
Short name T122
Test name
Test status
Simulation time 336967370000 ps
CPU time 840.83 seconds
Started Jun 21 05:44:35 PM PDT 24
Finished Jun 21 06:18:59 PM PDT 24
Peak memory 160824 kb
Host smart-39548d8d-f1ed-484e-9ffe-4396d9e8bb29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928583836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2928583836
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2212275955
Short name T130
Test name
Test status
Simulation time 336426150000 ps
CPU time 776.19 seconds
Started Jun 21 05:44:35 PM PDT 24
Finished Jun 21 06:16:35 PM PDT 24
Peak memory 160800 kb
Host smart-ae7699f3-ae69-4fa0-b2c6-62bb27f2bed5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2212275955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2212275955
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.20611938
Short name T149
Test name
Test status
Simulation time 336452550000 ps
CPU time 758.39 seconds
Started Jun 21 05:44:32 PM PDT 24
Finished Jun 21 06:15:26 PM PDT 24
Peak memory 160784 kb
Host smart-b6db4138-db02-4562-9731-8520ecc6e528
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=20611938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.20611938
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1824718238
Short name T129
Test name
Test status
Simulation time 336387190000 ps
CPU time 850.42 seconds
Started Jun 21 05:44:33 PM PDT 24
Finished Jun 21 06:19:26 PM PDT 24
Peak memory 160816 kb
Host smart-adc61fe2-0515-4fba-b78e-13d1bf5ea6b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1824718238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1824718238
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2032322518
Short name T15
Test name
Test status
Simulation time 336981430000 ps
CPU time 829.19 seconds
Started Jun 21 05:44:35 PM PDT 24
Finished Jun 21 06:18:43 PM PDT 24
Peak memory 160824 kb
Host smart-cf5c31a1-b88a-4cfc-af4c-49a65699858f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2032322518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2032322518
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1049322600
Short name T90
Test name
Test status
Simulation time 1390750000 ps
CPU time 3.42 seconds
Started Jun 21 05:37:44 PM PDT 24
Finished Jun 21 05:37:53 PM PDT 24
Peak memory 164924 kb
Host smart-71d2af65-81cb-473d-98cf-906f01163ce5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1049322600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1049322600
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.505467176
Short name T92
Test name
Test status
Simulation time 1363230000 ps
CPU time 3.03 seconds
Started Jun 21 05:37:52 PM PDT 24
Finished Jun 21 05:38:01 PM PDT 24
Peak memory 164904 kb
Host smart-4b4d1a32-e644-46c4-aacd-2fcfaed1cc87
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=505467176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.505467176
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2072219587
Short name T91
Test name
Test status
Simulation time 1508230000 ps
CPU time 5.41 seconds
Started Jun 21 05:37:52 PM PDT 24
Finished Jun 21 05:38:05 PM PDT 24
Peak memory 164932 kb
Host smart-b785d52e-a704-44b5-b4f2-f70b9ad25289
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2072219587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2072219587
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1450438888
Short name T28
Test name
Test status
Simulation time 1458550000 ps
CPU time 5.53 seconds
Started Jun 21 05:37:52 PM PDT 24
Finished Jun 21 05:38:06 PM PDT 24
Peak memory 164932 kb
Host smart-579197b1-c5a5-4f50-b725-264540a69d62
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1450438888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1450438888
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4005293226
Short name T120
Test name
Test status
Simulation time 1660570000 ps
CPU time 6.55 seconds
Started Jun 21 05:38:02 PM PDT 24
Finished Jun 21 05:38:17 PM PDT 24
Peak memory 164932 kb
Host smart-0b8f55f3-b5f7-41ef-ba45-c5b557775798
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4005293226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4005293226
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2574386939
Short name T100
Test name
Test status
Simulation time 1483850000 ps
CPU time 3.58 seconds
Started Jun 21 05:38:03 PM PDT 24
Finished Jun 21 05:38:12 PM PDT 24
Peak memory 164720 kb
Host smart-3d163a24-cd6f-46b9-8580-0215f4d6f485
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2574386939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2574386939
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4073155598
Short name T25
Test name
Test status
Simulation time 1506530000 ps
CPU time 3.82 seconds
Started Jun 21 05:38:04 PM PDT 24
Finished Jun 21 05:38:13 PM PDT 24
Peak memory 164944 kb
Host smart-58e7cbc8-8333-4003-8a8c-eaa8451c99aa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4073155598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4073155598
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.939373903
Short name T117
Test name
Test status
Simulation time 1526830000 ps
CPU time 6 seconds
Started Jun 21 05:38:01 PM PDT 24
Finished Jun 21 05:38:15 PM PDT 24
Peak memory 164908 kb
Host smart-1f2d658b-6dcf-459c-b0e3-27249483a3fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=939373903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.939373903
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2672720137
Short name T5
Test name
Test status
Simulation time 1521750000 ps
CPU time 3.71 seconds
Started Jun 21 05:38:02 PM PDT 24
Finished Jun 21 05:38:11 PM PDT 24
Peak memory 164932 kb
Host smart-db6b5b19-a004-429f-8142-08f00eb26023
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2672720137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2672720137
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3939009157
Short name T110
Test name
Test status
Simulation time 1364190000 ps
CPU time 4.28 seconds
Started Jun 21 05:38:02 PM PDT 24
Finished Jun 21 05:38:12 PM PDT 24
Peak memory 164932 kb
Host smart-54aded4b-1015-4028-86ea-f1fef6d0d6c3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3939009157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3939009157
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2530532366
Short name T97
Test name
Test status
Simulation time 1420490000 ps
CPU time 5.98 seconds
Started Jun 21 05:38:00 PM PDT 24
Finished Jun 21 05:38:13 PM PDT 24
Peak memory 164920 kb
Host smart-5c71c528-e061-415c-9ac2-f46f9b373514
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2530532366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2530532366
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.41329506
Short name T27
Test name
Test status
Simulation time 1564030000 ps
CPU time 6.26 seconds
Started Jun 21 05:37:42 PM PDT 24
Finished Jun 21 05:37:58 PM PDT 24
Peak memory 164856 kb
Host smart-33a918b9-0cd6-4ffa-8b64-75df80854b6b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=41329506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.41329506
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.4080685514
Short name T81
Test name
Test status
Simulation time 1458610000 ps
CPU time 3.55 seconds
Started Jun 21 05:38:02 PM PDT 24
Finished Jun 21 05:38:11 PM PDT 24
Peak memory 164872 kb
Host smart-0174ccc1-abaa-465d-8502-9ecb83a1992d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4080685514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.4080685514
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1143344846
Short name T83
Test name
Test status
Simulation time 1349610000 ps
CPU time 3.54 seconds
Started Jun 21 05:38:03 PM PDT 24
Finished Jun 21 05:38:11 PM PDT 24
Peak memory 164932 kb
Host smart-9174acc6-81c5-4664-b5c4-effcb66c4da7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1143344846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1143344846
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4206704707
Short name T93
Test name
Test status
Simulation time 1536170000 ps
CPU time 5.5 seconds
Started Jun 21 05:38:17 PM PDT 24
Finished Jun 21 05:38:30 PM PDT 24
Peak memory 164932 kb
Host smart-70229e3d-7bc6-4b77-b009-2562bbabe92a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4206704707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4206704707
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1947222373
Short name T102
Test name
Test status
Simulation time 1514810000 ps
CPU time 3.48 seconds
Started Jun 21 05:38:17 PM PDT 24
Finished Jun 21 05:38:26 PM PDT 24
Peak memory 164904 kb
Host smart-42269ab8-2c52-4494-8787-34a6512baa74
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947222373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1947222373
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3555953823
Short name T113
Test name
Test status
Simulation time 1512450000 ps
CPU time 4.74 seconds
Started Jun 21 05:38:17 PM PDT 24
Finished Jun 21 05:38:27 PM PDT 24
Peak memory 165004 kb
Host smart-306b6c50-d69c-4e75-a78d-93bbb16ca30c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555953823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3555953823
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.248334479
Short name T107
Test name
Test status
Simulation time 1507470000 ps
CPU time 6.31 seconds
Started Jun 21 05:38:18 PM PDT 24
Finished Jun 21 05:38:32 PM PDT 24
Peak memory 164928 kb
Host smart-cc0e62cf-f58e-452d-a65a-b49357496ac6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=248334479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.248334479
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3174842058
Short name T30
Test name
Test status
Simulation time 1386550000 ps
CPU time 3.44 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:34 PM PDT 24
Peak memory 164932 kb
Host smart-ebb76e81-b34c-4553-88ec-e179a9c1641c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3174842058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3174842058
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4207128025
Short name T98
Test name
Test status
Simulation time 1542770000 ps
CPU time 5.65 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:39 PM PDT 24
Peak memory 164932 kb
Host smart-8796f29a-7f7b-44e4-a0b7-67cfc237833a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4207128025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.4207128025
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.681726554
Short name T6
Test name
Test status
Simulation time 1433170000 ps
CPU time 6.18 seconds
Started Jun 21 05:38:25 PM PDT 24
Finished Jun 21 05:38:38 PM PDT 24
Peak memory 164904 kb
Host smart-7d0ecb2b-1780-4a47-869d-43c3ca6ca2b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=681726554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.681726554
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1677646613
Short name T115
Test name
Test status
Simulation time 1421090000 ps
CPU time 3.33 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:34 PM PDT 24
Peak memory 165004 kb
Host smart-dc9ce514-5095-4204-97a3-eae0b0578074
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1677646613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1677646613
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.276152349
Short name T103
Test name
Test status
Simulation time 1483330000 ps
CPU time 4.59 seconds
Started Jun 21 05:37:54 PM PDT 24
Finished Jun 21 05:38:06 PM PDT 24
Peak memory 164856 kb
Host smart-e1c78a20-e771-4938-b89a-39c17894cd5a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=276152349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.276152349
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2579128513
Short name T88
Test name
Test status
Simulation time 1517490000 ps
CPU time 5.85 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:39 PM PDT 24
Peak memory 164880 kb
Host smart-42bca589-fde9-4aec-96df-a9969f5eb6cf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2579128513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2579128513
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.25219459
Short name T24
Test name
Test status
Simulation time 1477910000 ps
CPU time 6.06 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:40 PM PDT 24
Peak memory 164856 kb
Host smart-f72e602b-3c87-420e-b9e7-5e3932bc8447
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25219459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.25219459
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1980035143
Short name T119
Test name
Test status
Simulation time 1528410000 ps
CPU time 5.68 seconds
Started Jun 21 05:38:27 PM PDT 24
Finished Jun 21 05:38:40 PM PDT 24
Peak memory 164860 kb
Host smart-bca549be-887f-4d6a-8510-6254d24195c4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980035143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1980035143
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1851935520
Short name T112
Test name
Test status
Simulation time 1468390000 ps
CPU time 4.54 seconds
Started Jun 21 05:38:27 PM PDT 24
Finished Jun 21 05:38:38 PM PDT 24
Peak memory 164932 kb
Host smart-858917cd-1ac6-4261-b015-e30c262f2dfc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1851935520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1851935520
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2597520568
Short name T4
Test name
Test status
Simulation time 1465530000 ps
CPU time 5.65 seconds
Started Jun 21 05:38:25 PM PDT 24
Finished Jun 21 05:38:38 PM PDT 24
Peak memory 164912 kb
Host smart-a68eae3d-4c43-4296-8dee-7eb828978801
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2597520568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2597520568
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.56304184
Short name T87
Test name
Test status
Simulation time 1348930000 ps
CPU time 5.19 seconds
Started Jun 21 05:38:25 PM PDT 24
Finished Jun 21 05:38:37 PM PDT 24
Peak memory 164856 kb
Host smart-7581d08c-d634-46ea-8e29-954143f2c5c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56304184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.56304184
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3093227724
Short name T114
Test name
Test status
Simulation time 1462370000 ps
CPU time 6.68 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:41 PM PDT 24
Peak memory 164932 kb
Host smart-74a8f429-16a5-44cf-b7b3-cb38658d5efb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093227724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3093227724
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1871389432
Short name T99
Test name
Test status
Simulation time 1595870000 ps
CPU time 5.08 seconds
Started Jun 21 05:38:25 PM PDT 24
Finished Jun 21 05:38:36 PM PDT 24
Peak memory 164920 kb
Host smart-94b37144-7a7e-4990-b648-a34498ec4be4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1871389432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1871389432
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2257920361
Short name T101
Test name
Test status
Simulation time 1487370000 ps
CPU time 6.63 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:42 PM PDT 24
Peak memory 164896 kb
Host smart-01611317-09ee-475c-80f8-11f9b3426a67
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2257920361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2257920361
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.851799170
Short name T108
Test name
Test status
Simulation time 1453950000 ps
CPU time 5.34 seconds
Started Jun 21 05:38:26 PM PDT 24
Finished Jun 21 05:38:38 PM PDT 24
Peak memory 164908 kb
Host smart-b2c3fba7-3e93-4d43-96c3-c0942d287732
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851799170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.851799170
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2658024688
Short name T116
Test name
Test status
Simulation time 1531630000 ps
CPU time 4.39 seconds
Started Jun 21 05:37:52 PM PDT 24
Finished Jun 21 05:38:03 PM PDT 24
Peak memory 164908 kb
Host smart-c6198946-f259-484c-b37a-7d2c69efaa92
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2658024688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2658024688
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1225435930
Short name T82
Test name
Test status
Simulation time 1614470000 ps
CPU time 3.8 seconds
Started Jun 21 05:38:36 PM PDT 24
Finished Jun 21 05:38:45 PM PDT 24
Peak memory 164912 kb
Host smart-db1063f7-9dc5-42e0-8b3b-85c6a586f08e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1225435930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1225435930
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2825571828
Short name T94
Test name
Test status
Simulation time 1093150000 ps
CPU time 2.66 seconds
Started Jun 21 05:38:33 PM PDT 24
Finished Jun 21 05:38:40 PM PDT 24
Peak memory 164916 kb
Host smart-460ba9ab-edac-4cd0-9f02-e0cc4c55e898
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2825571828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2825571828
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4176187544
Short name T104
Test name
Test status
Simulation time 1505590000 ps
CPU time 6.59 seconds
Started Jun 21 05:38:33 PM PDT 24
Finished Jun 21 05:38:49 PM PDT 24
Peak memory 164932 kb
Host smart-03f73324-678e-45d1-b7d3-ebf0b60c84cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176187544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.4176187544
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2783942061
Short name T105
Test name
Test status
Simulation time 1398710000 ps
CPU time 5.26 seconds
Started Jun 21 05:38:34 PM PDT 24
Finished Jun 21 05:38:46 PM PDT 24
Peak memory 164932 kb
Host smart-2b986296-85b4-4492-8aaa-529b7a772ce0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2783942061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2783942061
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1199145562
Short name T95
Test name
Test status
Simulation time 1449250000 ps
CPU time 4.34 seconds
Started Jun 21 05:38:39 PM PDT 24
Finished Jun 21 05:38:49 PM PDT 24
Peak memory 164720 kb
Host smart-958793f1-72dd-474e-b5be-9479504ed35c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1199145562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1199145562
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.343381442
Short name T86
Test name
Test status
Simulation time 1208910000 ps
CPU time 3.52 seconds
Started Jun 21 05:38:34 PM PDT 24
Finished Jun 21 05:38:42 PM PDT 24
Peak memory 164916 kb
Host smart-9c9bab05-2ff1-4743-b18c-5033eb256f6f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=343381442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.343381442
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.846001869
Short name T111
Test name
Test status
Simulation time 1548810000 ps
CPU time 3.85 seconds
Started Jun 21 05:38:36 PM PDT 24
Finished Jun 21 05:38:45 PM PDT 24
Peak memory 164940 kb
Host smart-19a7bc24-5198-4b1b-ae5f-347a16b177cb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=846001869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.846001869
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3776440334
Short name T96
Test name
Test status
Simulation time 1267950000 ps
CPU time 3.61 seconds
Started Jun 21 05:38:39 PM PDT 24
Finished Jun 21 05:38:47 PM PDT 24
Peak memory 164720 kb
Host smart-e9630755-1882-43fb-b4ba-b48c21ac27d9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3776440334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3776440334
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2136214962
Short name T109
Test name
Test status
Simulation time 1497570000 ps
CPU time 3.56 seconds
Started Jun 21 05:38:41 PM PDT 24
Finished Jun 21 05:38:50 PM PDT 24
Peak memory 164908 kb
Host smart-b8d80f85-3d8f-4f21-bcd3-dfd29a6ff217
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2136214962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2136214962
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1777355815
Short name T106
Test name
Test status
Simulation time 1559610000 ps
CPU time 7.46 seconds
Started Jun 21 05:38:41 PM PDT 24
Finished Jun 21 05:38:58 PM PDT 24
Peak memory 164932 kb
Host smart-15268fed-2142-4608-a71d-87a954b75b7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777355815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1777355815
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3041034517
Short name T84
Test name
Test status
Simulation time 1420930000 ps
CPU time 3.88 seconds
Started Jun 21 05:37:51 PM PDT 24
Finished Jun 21 05:38:01 PM PDT 24
Peak memory 164920 kb
Host smart-2d013ddc-415b-4bc5-8692-bab531104e77
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041034517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3041034517
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1061522491
Short name T89
Test name
Test status
Simulation time 1503330000 ps
CPU time 3.3 seconds
Started Jun 21 05:37:53 PM PDT 24
Finished Jun 21 05:38:01 PM PDT 24
Peak memory 164908 kb
Host smart-3e302996-27e4-4fff-9e03-28eeef2805e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1061522491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1061522491
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3219321032
Short name T85
Test name
Test status
Simulation time 1384370000 ps
CPU time 4.56 seconds
Started Jun 21 05:37:54 PM PDT 24
Finished Jun 21 05:38:05 PM PDT 24
Peak memory 164932 kb
Host smart-ec549906-4a29-4a9e-9897-98fbcd1089dc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3219321032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3219321032
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1206019436
Short name T26
Test name
Test status
Simulation time 1495670000 ps
CPU time 3.43 seconds
Started Jun 21 05:37:52 PM PDT 24
Finished Jun 21 05:38:00 PM PDT 24
Peak memory 164932 kb
Host smart-04f731c5-085c-4b93-b3ae-4648d25dc7bd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1206019436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1206019436
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2813393118
Short name T118
Test name
Test status
Simulation time 1508110000 ps
CPU time 6.89 seconds
Started Jun 21 05:37:54 PM PDT 24
Finished Jun 21 05:38:10 PM PDT 24
Peak memory 164864 kb
Host smart-c2531d58-a838-4e66-b1b3-127f31844cf8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2813393118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2813393118
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.4246993248
Short name T63
Test name
Test status
Simulation time 1399950000 ps
CPU time 5.06 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:26 PM PDT 24
Peak memory 164948 kb
Host smart-bf796c03-6cf2-4ab4-bdb7-6028edfd8d65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4246993248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.4246993248
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3418379256
Short name T54
Test name
Test status
Simulation time 1514730000 ps
CPU time 4.23 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:25 PM PDT 24
Peak memory 164956 kb
Host smart-9026740b-d08b-477c-b586-7db039fcdf5b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3418379256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3418379256
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3599363841
Short name T45
Test name
Test status
Simulation time 1358510000 ps
CPU time 4.81 seconds
Started Jun 21 05:58:15 PM PDT 24
Finished Jun 21 05:58:27 PM PDT 24
Peak memory 164948 kb
Host smart-bde8d847-b360-4772-b541-4c3b16b2bc6b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3599363841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.3599363841
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.879881070
Short name T77
Test name
Test status
Simulation time 1567650000 ps
CPU time 4.23 seconds
Started Jun 21 05:58:17 PM PDT 24
Finished Jun 21 05:58:27 PM PDT 24
Peak memory 164964 kb
Host smart-169f508b-ebba-4dca-94ff-73b934cef20c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=879881070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.879881070
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1243448346
Short name T72
Test name
Test status
Simulation time 1590050000 ps
CPU time 4.33 seconds
Started Jun 21 05:58:17 PM PDT 24
Finished Jun 21 05:58:27 PM PDT 24
Peak memory 164968 kb
Host smart-cbc1c375-0826-46bd-a81e-7deaa928afed
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1243448346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1243448346
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3134576489
Short name T44
Test name
Test status
Simulation time 1500430000 ps
CPU time 4.32 seconds
Started Jun 21 05:58:17 PM PDT 24
Finished Jun 21 05:58:28 PM PDT 24
Peak memory 164948 kb
Host smart-f486b86a-5301-46a1-ae4b-c42fb8be9dd7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3134576489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3134576489
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3064276691
Short name T60
Test name
Test status
Simulation time 1454390000 ps
CPU time 4.34 seconds
Started Jun 21 05:58:17 PM PDT 24
Finished Jun 21 05:58:28 PM PDT 24
Peak memory 164948 kb
Host smart-acd5714b-4658-4849-ab41-bf37433cc134
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064276691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3064276691
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1419322655
Short name T49
Test name
Test status
Simulation time 1518450000 ps
CPU time 5 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:35 PM PDT 24
Peak memory 164968 kb
Host smart-a10a0de4-332c-4da6-8326-cf7906f31f31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1419322655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1419322655
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1127117523
Short name T43
Test name
Test status
Simulation time 1458230000 ps
CPU time 3.98 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:31 PM PDT 24
Peak memory 164980 kb
Host smart-3feec00e-a1c9-4a03-bb9a-b437452e4465
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1127117523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1127117523
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2815966242
Short name T55
Test name
Test status
Simulation time 1239710000 ps
CPU time 4.58 seconds
Started Jun 21 05:58:24 PM PDT 24
Finished Jun 21 05:58:35 PM PDT 24
Peak memory 164956 kb
Host smart-2866b4d8-4f06-48f2-8fe8-a6908569c261
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2815966242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2815966242
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2544516778
Short name T13
Test name
Test status
Simulation time 1448330000 ps
CPU time 4.74 seconds
Started Jun 21 05:58:24 PM PDT 24
Finished Jun 21 05:58:36 PM PDT 24
Peak memory 164972 kb
Host smart-bc400f4a-e4ba-4bc1-9a2c-29212d6136e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2544516778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2544516778
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3548725430
Short name T3
Test name
Test status
Simulation time 1446570000 ps
CPU time 4.67 seconds
Started Jun 21 05:58:15 PM PDT 24
Finished Jun 21 05:58:26 PM PDT 24
Peak memory 164904 kb
Host smart-d2c42c62-c1b9-4232-a215-18ea71456ad2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3548725430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3548725430
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1598750371
Short name T57
Test name
Test status
Simulation time 1472830000 ps
CPU time 4.74 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:33 PM PDT 24
Peak memory 164948 kb
Host smart-cd3e2143-a9f0-4022-bc12-7ed55664e481
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1598750371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1598750371
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1518536218
Short name T74
Test name
Test status
Simulation time 1387170000 ps
CPU time 3.97 seconds
Started Jun 21 05:58:23 PM PDT 24
Finished Jun 21 05:58:33 PM PDT 24
Peak memory 164980 kb
Host smart-464e6553-d0be-4c3b-8d32-0a19d3a60f31
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518536218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1518536218
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2995605564
Short name T62
Test name
Test status
Simulation time 1384430000 ps
CPU time 4.85 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:35 PM PDT 24
Peak memory 164948 kb
Host smart-816a3186-8e05-4e98-a7e6-cf5757f5a309
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2995605564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2995605564
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3928435720
Short name T64
Test name
Test status
Simulation time 1461110000 ps
CPU time 4.59 seconds
Started Jun 21 05:58:21 PM PDT 24
Finished Jun 21 05:58:33 PM PDT 24
Peak memory 164932 kb
Host smart-3cc2330a-93e7-4c5f-9625-c0119ada76b9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3928435720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3928435720
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.413991763
Short name T8
Test name
Test status
Simulation time 1599630000 ps
CPU time 7.24 seconds
Started Jun 21 05:58:23 PM PDT 24
Finished Jun 21 05:58:40 PM PDT 24
Peak memory 164964 kb
Host smart-5c39f6a2-f9f6-437a-9b3a-5fcafbd979f0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=413991763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.413991763
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2087943331
Short name T73
Test name
Test status
Simulation time 1461390000 ps
CPU time 4.42 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:33 PM PDT 24
Peak memory 164968 kb
Host smart-3f3d6032-b6d7-43b7-8631-4835ab605fc0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087943331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2087943331
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2441303387
Short name T79
Test name
Test status
Simulation time 1482950000 ps
CPU time 3.68 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:31 PM PDT 24
Peak memory 164968 kb
Host smart-13c1b2e4-0ee0-4645-8ecb-005fa1aca3c3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2441303387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2441303387
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3351303748
Short name T12
Test name
Test status
Simulation time 1514770000 ps
CPU time 4 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:32 PM PDT 24
Peak memory 164968 kb
Host smart-45c8a58c-5f41-44b4-b7f5-fae7cd777d45
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3351303748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3351303748
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.14026706
Short name T70
Test name
Test status
Simulation time 1553110000 ps
CPU time 3.67 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:31 PM PDT 24
Peak memory 165000 kb
Host smart-796eb8cb-e78f-4a9d-8063-dc00568b6355
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=14026706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.14026706
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3669953059
Short name T42
Test name
Test status
Simulation time 1471010000 ps
CPU time 4.84 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:35 PM PDT 24
Peak memory 164968 kb
Host smart-d13e274d-a5fa-4134-bbfd-3ca383dcef71
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669953059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3669953059
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.863236778
Short name T69
Test name
Test status
Simulation time 1476710000 ps
CPU time 4.45 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:24 PM PDT 24
Peak memory 164836 kb
Host smart-0d27a7f3-ae8d-4583-9bc5-d563e54834f1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=863236778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.863236778
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.987253242
Short name T61
Test name
Test status
Simulation time 1598010000 ps
CPU time 3.94 seconds
Started Jun 21 05:58:21 PM PDT 24
Finished Jun 21 05:58:30 PM PDT 24
Peak memory 164968 kb
Host smart-6ec63624-f301-4ea8-9b2a-5fa9354a493b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=987253242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.987253242
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.241753951
Short name T47
Test name
Test status
Simulation time 1324550000 ps
CPU time 5.01 seconds
Started Jun 21 05:58:21 PM PDT 24
Finished Jun 21 05:58:33 PM PDT 24
Peak memory 164968 kb
Host smart-ffcd0401-6b89-42fc-9f9e-89003713d043
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=241753951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.241753951
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2529253654
Short name T76
Test name
Test status
Simulation time 1395530000 ps
CPU time 4.87 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:34 PM PDT 24
Peak memory 164972 kb
Host smart-aef3dec3-ee88-4640-a314-90f154d440fd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2529253654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2529253654
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1489807018
Short name T10
Test name
Test status
Simulation time 1445070000 ps
CPU time 4.51 seconds
Started Jun 21 05:58:24 PM PDT 24
Finished Jun 21 05:58:35 PM PDT 24
Peak memory 164968 kb
Host smart-666c427b-5e75-44fa-943e-d9a8617688c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1489807018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1489807018
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2590143420
Short name T71
Test name
Test status
Simulation time 1563330000 ps
CPU time 7.35 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:38 PM PDT 24
Peak memory 164972 kb
Host smart-ddadf52b-faec-4769-bb81-f73cacc90fa5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590143420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2590143420
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1159489644
Short name T66
Test name
Test status
Simulation time 1504110000 ps
CPU time 4.95 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:35 PM PDT 24
Peak memory 164972 kb
Host smart-1e7c0f67-ff8d-40b4-983d-77c0eaba6156
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159489644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1159489644
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2057061529
Short name T48
Test name
Test status
Simulation time 1543490000 ps
CPU time 5.41 seconds
Started Jun 21 05:58:22 PM PDT 24
Finished Jun 21 05:58:36 PM PDT 24
Peak memory 164944 kb
Host smart-2150d97d-05c5-49e5-8f96-2a3a8ed16996
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2057061529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2057061529
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1359468902
Short name T11
Test name
Test status
Simulation time 1379190000 ps
CPU time 4.41 seconds
Started Jun 21 05:58:30 PM PDT 24
Finished Jun 21 05:58:41 PM PDT 24
Peak memory 164932 kb
Host smart-152a50d7-3f9f-4dad-b034-f23a6a2cc229
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359468902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1359468902
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3671164195
Short name T80
Test name
Test status
Simulation time 1428690000 ps
CPU time 2.77 seconds
Started Jun 21 05:58:29 PM PDT 24
Finished Jun 21 05:58:37 PM PDT 24
Peak memory 164876 kb
Host smart-ce066443-5fe7-4ade-810a-b6240ee08aa6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3671164195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3671164195
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.471539485
Short name T7
Test name
Test status
Simulation time 1306290000 ps
CPU time 4.24 seconds
Started Jun 21 05:58:29 PM PDT 24
Finished Jun 21 05:58:40 PM PDT 24
Peak memory 164968 kb
Host smart-118eddee-3964-45a0-8136-6e7ed110212d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=471539485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.471539485
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1764935468
Short name T51
Test name
Test status
Simulation time 1377430000 ps
CPU time 4.11 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:24 PM PDT 24
Peak memory 164964 kb
Host smart-a1a7c196-35a3-4898-9eda-5f9c04014f20
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1764935468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1764935468
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.48704539
Short name T56
Test name
Test status
Simulation time 1521270000 ps
CPU time 4.44 seconds
Started Jun 21 05:58:32 PM PDT 24
Finished Jun 21 05:58:43 PM PDT 24
Peak memory 164872 kb
Host smart-c752034c-62cc-40f7-a3aa-0fa075ed687d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48704539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.48704539
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4119951721
Short name T53
Test name
Test status
Simulation time 1532990000 ps
CPU time 4.27 seconds
Started Jun 21 05:58:30 PM PDT 24
Finished Jun 21 05:58:41 PM PDT 24
Peak memory 164968 kb
Host smart-7496e406-1793-4cda-b528-7f4bc4f649d4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119951721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4119951721
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3676185307
Short name T50
Test name
Test status
Simulation time 1531670000 ps
CPU time 5.68 seconds
Started Jun 21 05:58:32 PM PDT 24
Finished Jun 21 05:58:45 PM PDT 24
Peak memory 164948 kb
Host smart-970662b2-117c-45e7-a741-6c507fa3aa33
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3676185307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3676185307
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.486222044
Short name T1
Test name
Test status
Simulation time 1526910000 ps
CPU time 4.48 seconds
Started Jun 21 05:58:30 PM PDT 24
Finished Jun 21 05:58:40 PM PDT 24
Peak memory 164964 kb
Host smart-903ecad5-a98a-4c89-a419-12204e570875
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=486222044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.486222044
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4179988302
Short name T68
Test name
Test status
Simulation time 1326190000 ps
CPU time 3.44 seconds
Started Jun 21 05:58:37 PM PDT 24
Finished Jun 21 05:58:45 PM PDT 24
Peak memory 164968 kb
Host smart-b2edc918-349a-4d8c-8bb7-31506b631526
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4179988302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4179988302
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.71923668
Short name T78
Test name
Test status
Simulation time 1379390000 ps
CPU time 4.87 seconds
Started Jun 21 05:58:30 PM PDT 24
Finished Jun 21 05:58:42 PM PDT 24
Peak memory 164892 kb
Host smart-c0e8ddd2-a212-43ec-9298-8afdb433cd09
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=71923668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.71923668
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1359081930
Short name T52
Test name
Test status
Simulation time 1492290000 ps
CPU time 5.47 seconds
Started Jun 21 05:58:29 PM PDT 24
Finished Jun 21 05:58:43 PM PDT 24
Peak memory 164936 kb
Host smart-7143fa00-0870-4c8b-b7d9-a0bba54c9087
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1359081930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1359081930
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.499882394
Short name T75
Test name
Test status
Simulation time 1552050000 ps
CPU time 4.78 seconds
Started Jun 21 05:58:32 PM PDT 24
Finished Jun 21 05:58:43 PM PDT 24
Peak memory 164968 kb
Host smart-2494ecda-5eba-40e9-ab2e-b441c9af21e8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=499882394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.499882394
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2920765147
Short name T9
Test name
Test status
Simulation time 1469250000 ps
CPU time 3.77 seconds
Started Jun 21 05:58:37 PM PDT 24
Finished Jun 21 05:58:45 PM PDT 24
Peak memory 164968 kb
Host smart-00f5bc68-6173-4428-a732-fd5a19066a07
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2920765147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2920765147
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2754271447
Short name T58
Test name
Test status
Simulation time 1535630000 ps
CPU time 5.04 seconds
Started Jun 21 05:58:38 PM PDT 24
Finished Jun 21 05:58:49 PM PDT 24
Peak memory 164912 kb
Host smart-a9ccdc29-97c4-4677-872a-d2722a1410eb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2754271447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2754271447
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.453362537
Short name T65
Test name
Test status
Simulation time 1397670000 ps
CPU time 4.96 seconds
Started Jun 21 05:58:15 PM PDT 24
Finished Jun 21 05:58:27 PM PDT 24
Peak memory 164872 kb
Host smart-bfe75f6d-4e88-4497-9645-cc65605d3f1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453362537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.453362537
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3066092537
Short name T59
Test name
Test status
Simulation time 1481790000 ps
CPU time 5.63 seconds
Started Jun 21 05:58:13 PM PDT 24
Finished Jun 21 05:58:26 PM PDT 24
Peak memory 165032 kb
Host smart-d1282252-9a98-4918-8a40-c78fa903aad4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066092537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3066092537
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1844100687
Short name T46
Test name
Test status
Simulation time 1469270000 ps
CPU time 4.6 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:25 PM PDT 24
Peak memory 164972 kb
Host smart-26205dbf-c36e-4a87-af0d-2ce4c0149f8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1844100687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1844100687
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3392576215
Short name T67
Test name
Test status
Simulation time 1531730000 ps
CPU time 5.63 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:27 PM PDT 24
Peak memory 164944 kb
Host smart-07687668-f63d-4106-8be5-a1225a3d1acf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3392576215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3392576215
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2316573743
Short name T41
Test name
Test status
Simulation time 1483750000 ps
CPU time 4.22 seconds
Started Jun 21 05:58:14 PM PDT 24
Finished Jun 21 05:58:24 PM PDT 24
Peak memory 164964 kb
Host smart-4baa31fd-477a-401d-a523-ca776a439902
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2316573743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2316573743
Directory /workspace/9.prim_lfsr_gal_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%