| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4223799453 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.821009774 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.460697808 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2962106392 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2454995187 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3109308953 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3720394462 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3274676416 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3386521428 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1731454690 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2614663362 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3521028751 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1197847642 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3030469282 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1695356677 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3527391574 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2902229739 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1777427718 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2799896236 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1615591455 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2282096259 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.248961347 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3278687894 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3912898620 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.932446916 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1122971258 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1283811547 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.429651364 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2504633592 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2675784261 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3220886713 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1071607134 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3193804481 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3835390875 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.914150935 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4196644626 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3306919745 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3978763609 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1155442341 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1706106939 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3727809406 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.510553444 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2597544226 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1526402220 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4168197400 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1200069408 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3382758435 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.309206280 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.984053183 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2770539326 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.694227514 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2414583973 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3912426706 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1861930611 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2541672283 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1984488125 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4133233778 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3104992448 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2403733552 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2741138822 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.398756808 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2590757730 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3063988871 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1218359303 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4021154119 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2345515642 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1870814464 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2837879223 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.486579481 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2334801320 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3687001357 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1191475179 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3952608788 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.585792545 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.20872977 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3857355129 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2892652655 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2694010496 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4165164040 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3153311738 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4078229264 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1231997914 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3390528590 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4282946357 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3063298812 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1951785540 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3847400617 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3457603627 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2311354602 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3454366421 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3322539022 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1105216944 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2910448135 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.733789121 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2090600628 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1339052813 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1747140856 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1286856381 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.530050626 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2562064134 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2146110681 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3559439307 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1318789291 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2595646603 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3950456668 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2528935250 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.34998049 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4160685304 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1931322437 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2859095863 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1074768161 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1906856070 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1148122389 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.709682545 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3002367123 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1028993679 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.573194917 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2706704538 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3458989641 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2129544043 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4102328616 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1085115184 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.942696739 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.831612684 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3109346112 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2415368978 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.90258437 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1958324535 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.346655592 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.696604763 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2552788711 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3694630451 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.678653927 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2481909910 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1222424911 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3832945108 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1859248601 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1357254970 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3265124459 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2402799970 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1430595790 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1934936524 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4020150299 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2432995860 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3982214794 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1944830637 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1463954541 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3541219609 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1240147682 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1590379487 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.224756577 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3072201042 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2483436206 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2516225468 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.924834929 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2607412786 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.91415998 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3498256586 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2698849106 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1364867098 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1222920309 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.896572192 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2766467018 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1923942624 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2825273628 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4057254282 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2744921280 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3435257824 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.986402544 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.796609631 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.320749756 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4116028917 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.625624327 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1776352078 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.441059584 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2339680443 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.655547379 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3859856719 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3301092234 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.797385868 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2638850954 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1710549671 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1488338013 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2225082668 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3020453413 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3714923697 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1728719740 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2951077484 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.586962862 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2269720812 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2206800356 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2141072911 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1238271562 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1268483867 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3317885515 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2138586482 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3892377041 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2167248119 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1239350987 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1363746763 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2141072911 | Jun 22 04:40:06 PM PDT 24 | Jun 22 04:40:14 PM PDT 24 | 1317430000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2206800356 | Jun 22 04:39:52 PM PDT 24 | Jun 22 04:40:00 PM PDT 24 | 1221870000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.586962862 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:40:12 PM PDT 24 | 1468190000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4223799453 | Jun 22 04:40:01 PM PDT 24 | Jun 22 04:40:16 PM PDT 24 | 1552470000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2638850954 | Jun 22 04:39:51 PM PDT 24 | Jun 22 04:40:00 PM PDT 24 | 1151670000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.896572192 | Jun 22 04:40:11 PM PDT 24 | Jun 22 04:40:26 PM PDT 24 | 1445370000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1238271562 | Jun 22 04:39:58 PM PDT 24 | Jun 22 04:40:08 PM PDT 24 | 1294470000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.320749756 | Jun 22 04:39:48 PM PDT 24 | Jun 22 04:39:58 PM PDT 24 | 1505710000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2269720812 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:40:15 PM PDT 24 | 1443430000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.796609631 | Jun 22 04:39:53 PM PDT 24 | Jun 22 04:40:02 PM PDT 24 | 1398070000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1363746763 | Jun 22 04:40:04 PM PDT 24 | Jun 22 04:40:15 PM PDT 24 | 1519930000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2516225468 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:40:11 PM PDT 24 | 1535030000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1364867098 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:40:17 PM PDT 24 | 1540770000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1239350987 | Jun 22 04:39:47 PM PDT 24 | Jun 22 04:39:57 PM PDT 24 | 1433430000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2698849106 | Jun 22 04:39:54 PM PDT 24 | Jun 22 04:40:05 PM PDT 24 | 1256630000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2744921280 | Jun 22 04:39:54 PM PDT 24 | Jun 22 04:40:05 PM PDT 24 | 1604230000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2766467018 | Jun 22 04:39:40 PM PDT 24 | Jun 22 04:39:53 PM PDT 24 | 1485450000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.91415998 | Jun 22 04:39:53 PM PDT 24 | Jun 22 04:40:06 PM PDT 24 | 1554750000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3435257824 | Jun 22 04:39:55 PM PDT 24 | Jun 22 04:40:07 PM PDT 24 | 1509250000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1710549671 | Jun 22 04:39:51 PM PDT 24 | Jun 22 04:40:02 PM PDT 24 | 1520190000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.625624327 | Jun 22 04:40:07 PM PDT 24 | Jun 22 04:40:17 PM PDT 24 | 1323470000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3301092234 | Jun 22 04:39:56 PM PDT 24 | Jun 22 04:40:07 PM PDT 24 | 1421530000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1728719740 | Jun 22 04:40:03 PM PDT 24 | Jun 22 04:40:13 PM PDT 24 | 1441210000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3859856719 | Jun 22 04:39:46 PM PDT 24 | Jun 22 04:39:55 PM PDT 24 | 1570570000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4057254282 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:40:09 PM PDT 24 | 1444330000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3892377041 | Jun 22 04:39:33 PM PDT 24 | Jun 22 04:39:44 PM PDT 24 | 1472570000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3714923697 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:40:13 PM PDT 24 | 1592750000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.924834929 | Jun 22 04:39:50 PM PDT 24 | Jun 22 04:39:59 PM PDT 24 | 1526970000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2339680443 | Jun 22 04:40:07 PM PDT 24 | Jun 22 04:40:14 PM PDT 24 | 1385110000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3072201042 | Jun 22 04:40:02 PM PDT 24 | Jun 22 04:40:14 PM PDT 24 | 1540710000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2825273628 | Jun 22 04:39:51 PM PDT 24 | Jun 22 04:40:01 PM PDT 24 | 1450370000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3020453413 | Jun 22 04:39:52 PM PDT 24 | Jun 22 04:40:09 PM PDT 24 | 1567870000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2138586482 | Jun 22 04:39:52 PM PDT 24 | Jun 22 04:40:04 PM PDT 24 | 1554550000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1268483867 | Jun 22 04:40:05 PM PDT 24 | Jun 22 04:40:16 PM PDT 24 | 1460690000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2225082668 | Jun 22 04:39:51 PM PDT 24 | Jun 22 04:39:59 PM PDT 24 | 1435770000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3498256586 | Jun 22 04:40:07 PM PDT 24 | Jun 22 04:40:18 PM PDT 24 | 1431730000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2951077484 | Jun 22 04:39:45 PM PDT 24 | Jun 22 04:39:53 PM PDT 24 | 1534090000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4116028917 | Jun 22 04:39:50 PM PDT 24 | Jun 22 04:39:59 PM PDT 24 | 1469770000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1776352078 | Jun 22 04:40:00 PM PDT 24 | Jun 22 04:40:11 PM PDT 24 | 1384810000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2167248119 | Jun 22 04:39:58 PM PDT 24 | Jun 22 04:40:11 PM PDT 24 | 1390050000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3317885515 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:40:12 PM PDT 24 | 1590930000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1488338013 | Jun 22 04:39:57 PM PDT 24 | Jun 22 04:40:11 PM PDT 24 | 1552650000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.441059584 | Jun 22 04:39:54 PM PDT 24 | Jun 22 04:40:05 PM PDT 24 | 1363110000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1222920309 | Jun 22 04:39:58 PM PDT 24 | Jun 22 04:40:06 PM PDT 24 | 1426310000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.655547379 | Jun 22 04:39:47 PM PDT 24 | Jun 22 04:39:58 PM PDT 24 | 1557350000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.797385868 | Jun 22 04:39:56 PM PDT 24 | Jun 22 04:40:07 PM PDT 24 | 1132550000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.986402544 | Jun 22 04:39:59 PM PDT 24 | Jun 22 04:40:09 PM PDT 24 | 1372310000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2483436206 | Jun 22 04:39:57 PM PDT 24 | Jun 22 04:40:07 PM PDT 24 | 1419230000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1923942624 | Jun 22 04:40:07 PM PDT 24 | Jun 22 04:40:16 PM PDT 24 | 1424030000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2607412786 | Jun 22 04:39:58 PM PDT 24 | Jun 22 04:40:12 PM PDT 24 | 1472850000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2595646603 | Jun 22 04:39:12 PM PDT 24 | Jun 22 04:39:22 PM PDT 24 | 1465630000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3950456668 | Jun 22 04:39:17 PM PDT 24 | Jun 22 04:39:28 PM PDT 24 | 1522230000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3832945108 | Jun 22 04:39:20 PM PDT 24 | Jun 22 04:39:30 PM PDT 24 | 1539250000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.696604763 | Jun 22 04:39:27 PM PDT 24 | Jun 22 04:39:37 PM PDT 24 | 1556570000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2962106392 | Jun 22 04:39:23 PM PDT 24 | Jun 22 04:39:33 PM PDT 24 | 1292030000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3982214794 | Jun 22 04:39:28 PM PDT 24 | Jun 22 04:39:37 PM PDT 24 | 1552130000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.346655592 | Jun 22 04:39:22 PM PDT 24 | Jun 22 04:39:31 PM PDT 24 | 1580890000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1240147682 | Jun 22 04:39:16 PM PDT 24 | Jun 22 04:39:29 PM PDT 24 | 1421990000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1859248601 | Jun 22 04:39:20 PM PDT 24 | Jun 22 04:39:32 PM PDT 24 | 1583590000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1148122389 | Jun 22 04:39:19 PM PDT 24 | Jun 22 04:39:29 PM PDT 24 | 1383090000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1463954541 | Jun 22 04:39:26 PM PDT 24 | Jun 22 04:39:38 PM PDT 24 | 1480130000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1906856070 | Jun 22 04:39:27 PM PDT 24 | Jun 22 04:39:39 PM PDT 24 | 1490870000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3541219609 | Jun 22 04:39:17 PM PDT 24 | Jun 22 04:39:29 PM PDT 24 | 1557170000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2528935250 | Jun 22 04:39:18 PM PDT 24 | Jun 22 04:39:27 PM PDT 24 | 1466370000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1318789291 | Jun 22 04:39:07 PM PDT 24 | Jun 22 04:39:17 PM PDT 24 | 1428910000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.709682545 | Jun 22 04:39:15 PM PDT 24 | Jun 22 04:39:26 PM PDT 24 | 1492830000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2129544043 | Jun 22 04:39:18 PM PDT 24 | Jun 22 04:39:28 PM PDT 24 | 1478350000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.224756577 | Jun 22 04:39:11 PM PDT 24 | Jun 22 04:39:24 PM PDT 24 | 1626390000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1934936524 | Jun 22 04:39:28 PM PDT 24 | Jun 22 04:39:36 PM PDT 24 | 1433690000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2432995860 | Jun 22 04:39:19 PM PDT 24 | Jun 22 04:39:28 PM PDT 24 | 1503950000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2415368978 | Jun 22 04:39:20 PM PDT 24 | Jun 22 04:39:31 PM PDT 24 | 1525610000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4160685304 | Jun 22 04:39:30 PM PDT 24 | Jun 22 04:39:39 PM PDT 24 | 1584270000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1931322437 | Jun 22 04:39:19 PM PDT 24 | Jun 22 04:39:30 PM PDT 24 | 1500750000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2706704538 | Jun 22 04:39:18 PM PDT 24 | Jun 22 04:39:29 PM PDT 24 | 1348690000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4102328616 | Jun 22 04:39:17 PM PDT 24 | Jun 22 04:39:26 PM PDT 24 | 1378730000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1222424911 | Jun 22 04:39:27 PM PDT 24 | Jun 22 04:39:39 PM PDT 24 | 1476070000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1085115184 | Jun 22 04:39:24 PM PDT 24 | Jun 22 04:39:33 PM PDT 24 | 1181330000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1028993679 | Jun 22 04:39:27 PM PDT 24 | Jun 22 04:39:37 PM PDT 24 | 1515290000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1590379487 | Jun 22 04:39:11 PM PDT 24 | Jun 22 04:39:23 PM PDT 24 | 1355510000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3109346112 | Jun 22 04:39:19 PM PDT 24 | Jun 22 04:39:26 PM PDT 24 | 1291990000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.573194917 | Jun 22 04:39:17 PM PDT 24 | Jun 22 04:39:26 PM PDT 24 | 1155530000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2481909910 | Jun 22 04:39:16 PM PDT 24 | Jun 22 04:39:26 PM PDT 24 | 1488050000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.90258437 | Jun 22 04:39:32 PM PDT 24 | Jun 22 04:39:45 PM PDT 24 | 1341650000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2552788711 | Jun 22 04:39:25 PM PDT 24 | Jun 22 04:39:34 PM PDT 24 | 1621950000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4020150299 | Jun 22 04:39:27 PM PDT 24 | Jun 22 04:39:39 PM PDT 24 | 1489710000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3002367123 | Jun 22 04:39:16 PM PDT 24 | Jun 22 04:39:27 PM PDT 24 | 1555530000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2402799970 | Jun 22 04:39:24 PM PDT 24 | Jun 22 04:39:31 PM PDT 24 | 1375010000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3694630451 | Jun 22 04:39:11 PM PDT 24 | Jun 22 04:39:22 PM PDT 24 | 1487390000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2859095863 | Jun 22 04:39:32 PM PDT 24 | Jun 22 04:39:46 PM PDT 24 | 1602030000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1944830637 | Jun 22 04:39:24 PM PDT 24 | Jun 22 04:39:34 PM PDT 24 | 1563090000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1074768161 | Jun 22 04:39:14 PM PDT 24 | Jun 22 04:39:26 PM PDT 24 | 1452930000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1430595790 | Jun 22 04:39:26 PM PDT 24 | Jun 22 04:39:35 PM PDT 24 | 1506150000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.942696739 | Jun 22 04:39:47 PM PDT 24 | Jun 22 04:39:55 PM PDT 24 | 1483270000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3458989641 | Jun 22 04:39:17 PM PDT 24 | Jun 22 04:39:29 PM PDT 24 | 1551570000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1357254970 | Jun 22 04:39:22 PM PDT 24 | Jun 22 04:39:30 PM PDT 24 | 1494950000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1958324535 | Jun 22 04:39:18 PM PDT 24 | Jun 22 04:39:29 PM PDT 24 | 1520090000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.34998049 | Jun 22 04:39:23 PM PDT 24 | Jun 22 04:39:31 PM PDT 24 | 1349690000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.678653927 | Jun 22 04:39:16 PM PDT 24 | Jun 22 04:39:27 PM PDT 24 | 1448030000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3265124459 | Jun 22 04:39:26 PM PDT 24 | Jun 22 04:39:35 PM PDT 24 | 1558290000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.831612684 | Jun 22 04:39:26 PM PDT 24 | Jun 22 04:39:35 PM PDT 24 | 1485430000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3104992448 | Jun 22 04:39:42 PM PDT 24 | Jun 22 05:18:31 PM PDT 24 | 336973930000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3952608788 | Jun 22 04:39:34 PM PDT 24 | Jun 22 05:14:49 PM PDT 24 | 336854810000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.733789121 | Jun 22 04:39:50 PM PDT 24 | Jun 22 05:07:41 PM PDT 24 | 336975890000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1951785540 | Jun 22 04:39:38 PM PDT 24 | Jun 22 05:16:32 PM PDT 24 | 336671790000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2090600628 | Jun 22 04:39:52 PM PDT 24 | Jun 22 05:11:22 PM PDT 24 | 336837730000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2910448135 | Jun 22 04:39:59 PM PDT 24 | Jun 22 05:21:29 PM PDT 24 | 336354770000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2403733552 | Jun 22 04:39:51 PM PDT 24 | Jun 22 05:17:49 PM PDT 24 | 336497510000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.821009774 | Jun 22 04:39:39 PM PDT 24 | Jun 22 05:08:41 PM PDT 24 | 336725290000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3454366421 | Jun 22 04:39:52 PM PDT 24 | Jun 22 05:19:12 PM PDT 24 | 336652670000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3559439307 | Jun 22 04:39:42 PM PDT 24 | Jun 22 05:12:11 PM PDT 24 | 336466050000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1218359303 | Jun 22 04:39:46 PM PDT 24 | Jun 22 05:09:58 PM PDT 24 | 336618210000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3457603627 | Jun 22 04:39:35 PM PDT 24 | Jun 22 05:14:47 PM PDT 24 | 336664790000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3847400617 | Jun 22 04:39:48 PM PDT 24 | Jun 22 05:18:23 PM PDT 24 | 336731530000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4078229264 | Jun 22 04:39:45 PM PDT 24 | Jun 22 05:12:42 PM PDT 24 | 337040890000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4021154119 | Jun 22 04:39:39 PM PDT 24 | Jun 22 05:11:49 PM PDT 24 | 336467030000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3063298812 | Jun 22 04:39:46 PM PDT 24 | Jun 22 05:13:20 PM PDT 24 | 336898790000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4282946357 | Jun 22 04:39:37 PM PDT 24 | Jun 22 05:14:05 PM PDT 24 | 336733110000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1339052813 | Jun 22 04:39:55 PM PDT 24 | Jun 22 05:10:35 PM PDT 24 | 336759710000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3857355129 | Jun 22 04:39:34 PM PDT 24 | Jun 22 05:16:08 PM PDT 24 | 336709870000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1984488125 | Jun 22 04:39:48 PM PDT 24 | Jun 22 05:16:18 PM PDT 24 | 336549030000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4165164040 | Jun 22 04:39:34 PM PDT 24 | Jun 22 05:10:05 PM PDT 24 | 336704090000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2741138822 | Jun 22 04:39:50 PM PDT 24 | Jun 22 05:15:00 PM PDT 24 | 336774410000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2311354602 | Jun 22 04:39:48 PM PDT 24 | Jun 22 05:18:21 PM PDT 24 | 336864570000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1286856381 | Jun 22 04:39:34 PM PDT 24 | Jun 22 05:12:43 PM PDT 24 | 336591690000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.530050626 | Jun 22 04:39:34 PM PDT 24 | Jun 22 05:11:39 PM PDT 24 | 337018610000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.585792545 | Jun 22 04:39:38 PM PDT 24 | Jun 22 05:11:23 PM PDT 24 | 336478610000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3063988871 | Jun 22 04:40:02 PM PDT 24 | Jun 22 05:22:25 PM PDT 24 | 336903670000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4133233778 | Jun 22 04:39:33 PM PDT 24 | Jun 22 05:15:09 PM PDT 24 | 336426810000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1105216944 | Jun 22 04:39:50 PM PDT 24 | Jun 22 05:11:35 PM PDT 24 | 336492890000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3687001357 | Jun 22 04:40:01 PM PDT 24 | Jun 22 05:22:44 PM PDT 24 | 336633410000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2345515642 | Jun 22 04:39:47 PM PDT 24 | Jun 22 05:14:47 PM PDT 24 | 336462890000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1861930611 | Jun 22 04:39:42 PM PDT 24 | Jun 22 05:16:26 PM PDT 24 | 336488310000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2334801320 | Jun 22 04:39:46 PM PDT 24 | Jun 22 05:11:28 PM PDT 24 | 336345870000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2837879223 | Jun 22 04:39:51 PM PDT 24 | Jun 22 05:10:46 PM PDT 24 | 336960210000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2590757730 | Jun 22 04:40:04 PM PDT 24 | Jun 22 05:13:47 PM PDT 24 | 336405530000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2694010496 | Jun 22 04:39:41 PM PDT 24 | Jun 22 05:12:04 PM PDT 24 | 337064690000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.20872977 | Jun 22 04:39:52 PM PDT 24 | Jun 22 05:21:34 PM PDT 24 | 336708450000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.486579481 | Jun 22 04:39:36 PM PDT 24 | Jun 22 05:17:34 PM PDT 24 | 336406870000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1231997914 | Jun 22 04:39:35 PM PDT 24 | Jun 22 05:12:50 PM PDT 24 | 336951250000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1870814464 | Jun 22 04:39:52 PM PDT 24 | Jun 22 05:12:13 PM PDT 24 | 336621970000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1191475179 | Jun 22 04:39:51 PM PDT 24 | Jun 22 05:10:29 PM PDT 24 | 336530630000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3153311738 | Jun 22 04:39:56 PM PDT 24 | Jun 22 05:12:27 PM PDT 24 | 337001570000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3390528590 | Jun 22 04:39:49 PM PDT 24 | Jun 22 05:16:49 PM PDT 24 | 336629670000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2892652655 | Jun 22 04:39:48 PM PDT 24 | Jun 22 05:12:06 PM PDT 24 | 336846750000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2146110681 | Jun 22 04:39:43 PM PDT 24 | Jun 22 05:09:32 PM PDT 24 | 336534410000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2562064134 | Jun 22 04:39:35 PM PDT 24 | Jun 22 05:08:24 PM PDT 24 | 336911590000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3322539022 | Jun 22 04:39:40 PM PDT 24 | Jun 22 05:11:51 PM PDT 24 | 337102790000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2541672283 | Jun 22 04:39:52 PM PDT 24 | Jun 22 05:10:41 PM PDT 24 | 336995790000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.398756808 | Jun 22 04:39:35 PM PDT 24 | Jun 22 05:08:21 PM PDT 24 | 336812730000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1747140856 | Jun 22 04:39:52 PM PDT 24 | Jun 22 05:22:30 PM PDT 24 | 336554370000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.510553444 | Jun 22 04:36:58 PM PDT 24 | Jun 22 05:03:08 PM PDT 24 | 336674010000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.460697808 | Jun 22 04:36:53 PM PDT 24 | Jun 22 05:14:51 PM PDT 24 | 336721790000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.932446916 | Jun 22 04:38:21 PM PDT 24 | Jun 22 05:00:51 PM PDT 24 | 337139650000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3382758435 | Jun 22 04:37:14 PM PDT 24 | Jun 22 05:04:29 PM PDT 24 | 336892590000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3912898620 | Jun 22 04:37:16 PM PDT 24 | Jun 22 05:11:45 PM PDT 24 | 336634510000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.914150935 | Jun 22 04:36:50 PM PDT 24 | Jun 22 05:14:17 PM PDT 24 | 336435270000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3306919745 | Jun 22 04:37:01 PM PDT 24 | Jun 22 05:15:00 PM PDT 24 | 337114410000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1071607134 | Jun 22 04:36:50 PM PDT 24 | Jun 22 05:09:14 PM PDT 24 | 336992410000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1695356677 | Jun 22 04:36:48 PM PDT 24 | Jun 22 05:06:03 PM PDT 24 | 336385350000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1615591455 | Jun 22 04:37:05 PM PDT 24 | Jun 22 05:14:49 PM PDT 24 | 336882450000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3521028751 | Jun 22 04:36:52 PM PDT 24 | Jun 22 05:05:55 PM PDT 24 | 336673290000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2614663362 | Jun 22 04:36:50 PM PDT 24 | Jun 22 05:13:10 PM PDT 24 | 336529990000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3220886713 | Jun 22 04:37:07 PM PDT 24 | Jun 22 05:15:11 PM PDT 24 | 336680130000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2282096259 | Jun 22 04:36:57 PM PDT 24 | Jun 22 05:04:29 PM PDT 24 | 336360210000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3912426706 | Jun 22 04:36:56 PM PDT 24 | Jun 22 05:18:48 PM PDT 24 | 336299930000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3109308953 | Jun 22 04:36:58 PM PDT 24 | Jun 22 05:08:58 PM PDT 24 | 336916770000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3978763609 | Jun 22 04:36:51 PM PDT 24 | Jun 22 05:08:31 PM PDT 24 | 336546850000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3278687894 | Jun 22 04:36:54 PM PDT 24 | Jun 22 05:16:48 PM PDT 24 | 337022230000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3193804481 | Jun 22 04:37:16 PM PDT 24 | Jun 22 05:09:40 PM PDT 24 | 336795430000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1526402220 | Jun 22 04:36:56 PM PDT 24 | Jun 22 05:12:51 PM PDT 24 | 336857410000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2414583973 | Jun 22 04:36:52 PM PDT 24 | Jun 22 05:14:32 PM PDT 24 | 337118950000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1777427718 | Jun 22 04:36:53 PM PDT 24 | Jun 22 05:06:02 PM PDT 24 | 336734610000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.984053183 | Jun 22 04:36:57 PM PDT 24 | Jun 22 05:14:56 PM PDT 24 | 336941170000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2799896236 | Jun 22 04:37:04 PM PDT 24 | Jun 22 05:11:39 PM PDT 24 | 336421210000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2504633592 | Jun 22 04:36:56 PM PDT 24 | Jun 22 05:09:09 PM PDT 24 | 336663950000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2597544226 | Jun 22 04:37:14 PM PDT 24 | Jun 22 05:07:34 PM PDT 24 | 337036650000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2902229739 | Jun 22 04:37:08 PM PDT 24 | Jun 22 05:17:55 PM PDT 24 | 336822210000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3835390875 | Jun 22 04:37:26 PM PDT 24 | Jun 22 05:11:37 PM PDT 24 | 336378810000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.694227514 | Jun 22 04:37:01 PM PDT 24 | Jun 22 05:15:56 PM PDT 24 | 336933970000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2770539326 | Jun 22 04:37:02 PM PDT 24 | Jun 22 05:05:49 PM PDT 24 | 336465830000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3720394462 | Jun 22 04:36:53 PM PDT 24 | Jun 22 05:06:06 PM PDT 24 | 336318550000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1197847642 | Jun 22 04:37:16 PM PDT 24 | Jun 22 05:16:01 PM PDT 24 | 336862630000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.309206280 | Jun 22 04:37:08 PM PDT 24 | Jun 22 05:15:07 PM PDT 24 | 336735650000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3030469282 | Jun 22 04:36:49 PM PDT 24 | Jun 22 05:09:35 PM PDT 24 | 336853930000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.248961347 | Jun 22 04:36:53 PM PDT 24 | Jun 22 05:02:01 PM PDT 24 | 336932770000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1155442341 | Jun 22 04:37:12 PM PDT 24 | Jun 22 05:14:46 PM PDT 24 | 336421910000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3527391574 | Jun 22 04:36:48 PM PDT 24 | Jun 22 05:03:34 PM PDT 24 | 336713190000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1731454690 | Jun 22 04:37:12 PM PDT 24 | Jun 22 05:16:44 PM PDT 24 | 336509150000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1200069408 | Jun 22 04:36:53 PM PDT 24 | Jun 22 05:09:48 PM PDT 24 | 336783690000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3274676416 | Jun 22 04:37:07 PM PDT 24 | Jun 22 05:17:49 PM PDT 24 | 336816550000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3727809406 | Jun 22 04:36:50 PM PDT 24 | Jun 22 05:12:51 PM PDT 24 | 337083590000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2675784261 | Jun 22 04:36:49 PM PDT 24 | Jun 22 05:16:45 PM PDT 24 | 336432450000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4168197400 | Jun 22 04:37:20 PM PDT 24 | Jun 22 05:05:14 PM PDT 24 | 336494810000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1706106939 | Jun 22 04:37:06 PM PDT 24 | Jun 22 05:07:32 PM PDT 24 | 336830590000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3386521428 | Jun 22 04:36:50 PM PDT 24 | Jun 22 05:13:41 PM PDT 24 | 336871910000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1122971258 | Jun 22 04:36:49 PM PDT 24 | Jun 22 05:08:58 PM PDT 24 | 336408130000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.429651364 | Jun 22 04:37:03 PM PDT 24 | Jun 22 05:15:00 PM PDT 24 | 336790190000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4196644626 | Jun 22 04:37:07 PM PDT 24 | Jun 22 05:17:54 PM PDT 24 | 336400950000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1283811547 | Jun 22 04:36:52 PM PDT 24 | Jun 22 05:06:47 PM PDT 24 | 336558110000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2454995187 | Jun 22 04:36:51 PM PDT 24 | Jun 22 05:12:56 PM PDT 24 | 336976010000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.4223799453 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1552470000 ps |
| CPU time | 5.75 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 04:40:16 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-0bc23e00-3ce3-4308-b3e2-8d6147a60908 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4223799453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.4223799453 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.821009774 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336725290000 ps |
| CPU time | 701.81 seconds |
| Started | Jun 22 04:39:39 PM PDT 24 |
| Finished | Jun 22 05:08:41 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-8cc3145d-ca9e-4c24-85f8-592ec49d98e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=821009774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.821009774 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.460697808 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336721790000 ps |
| CPU time | 922.68 seconds |
| Started | Jun 22 04:36:53 PM PDT 24 |
| Finished | Jun 22 05:14:51 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-d310b2c2-c763-4db6-9695-b4f462b25ac5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=460697808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.460697808 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2962106392 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1292030000 ps |
| CPU time | 4 seconds |
| Started | Jun 22 04:39:23 PM PDT 24 |
| Finished | Jun 22 04:39:33 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-c93af59e-2bb2-4146-b8fa-f6ee329237ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2962106392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2962106392 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2454995187 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336976010000 ps |
| CPU time | 875.66 seconds |
| Started | Jun 22 04:36:51 PM PDT 24 |
| Finished | Jun 22 05:12:56 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-7f1b8dab-50d9-4549-864a-a204afb9616b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2454995187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2454995187 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3109308953 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336916770000 ps |
| CPU time | 791.26 seconds |
| Started | Jun 22 04:36:58 PM PDT 24 |
| Finished | Jun 22 05:08:58 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-cd38f6d3-f350-4f55-8a1a-abdda23510eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3109308953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3109308953 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3720394462 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336318550000 ps |
| CPU time | 714.96 seconds |
| Started | Jun 22 04:36:53 PM PDT 24 |
| Finished | Jun 22 05:06:06 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-859c37f8-c3ac-48c6-be62-23bba9ffdcda |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3720394462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3720394462 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3274676416 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336816550000 ps |
| CPU time | 979.3 seconds |
| Started | Jun 22 04:37:07 PM PDT 24 |
| Finished | Jun 22 05:17:49 PM PDT 24 |
| Peak memory | 160448 kb |
| Host | smart-f660c508-f5f7-4dbb-b7c1-617f67f430c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3274676416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3274676416 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3386521428 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336871910000 ps |
| CPU time | 898.15 seconds |
| Started | Jun 22 04:36:50 PM PDT 24 |
| Finished | Jun 22 05:13:41 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-ff88aca0-2128-4366-9df8-7a8c1d40a41d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3386521428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3386521428 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1731454690 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336509150000 ps |
| CPU time | 971.56 seconds |
| Started | Jun 22 04:37:12 PM PDT 24 |
| Finished | Jun 22 05:16:44 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-0cbb20bf-202f-4284-80a4-08ba578a3463 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1731454690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1731454690 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2614663362 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336529990000 ps |
| CPU time | 864.05 seconds |
| Started | Jun 22 04:36:50 PM PDT 24 |
| Finished | Jun 22 05:13:10 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-93aa5f96-a655-4d09-9f10-13ec0aabce28 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2614663362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2614663362 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3521028751 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336673290000 ps |
| CPU time | 704.89 seconds |
| Started | Jun 22 04:36:52 PM PDT 24 |
| Finished | Jun 22 05:05:55 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-a0ee320c-51e6-4354-bfbe-078cb7e14b9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3521028751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3521028751 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1197847642 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336862630000 ps |
| CPU time | 940.7 seconds |
| Started | Jun 22 04:37:16 PM PDT 24 |
| Finished | Jun 22 05:16:01 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-ad95a881-2745-43f5-b5af-cd78aec33165 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1197847642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1197847642 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3030469282 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336853930000 ps |
| CPU time | 784.35 seconds |
| Started | Jun 22 04:36:49 PM PDT 24 |
| Finished | Jun 22 05:09:35 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-b2a47d73-481c-4f62-beb9-9181b9befe74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3030469282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3030469282 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1695356677 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336385350000 ps |
| CPU time | 717.64 seconds |
| Started | Jun 22 04:36:48 PM PDT 24 |
| Finished | Jun 22 05:06:03 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-df692e1a-c9ff-4276-a0a7-fbe86e2ca154 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1695356677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1695356677 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3527391574 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336713190000 ps |
| CPU time | 645.15 seconds |
| Started | Jun 22 04:36:48 PM PDT 24 |
| Finished | Jun 22 05:03:34 PM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-29217155-8ae7-44cf-9351-a61b4f230f67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3527391574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3527391574 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2902229739 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336822210000 ps |
| CPU time | 980.22 seconds |
| Started | Jun 22 04:37:08 PM PDT 24 |
| Finished | Jun 22 05:17:55 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-7b53bbb2-587b-4a19-8813-0d76346fb6de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2902229739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2902229739 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1777427718 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336734610000 ps |
| CPU time | 714.88 seconds |
| Started | Jun 22 04:36:53 PM PDT 24 |
| Finished | Jun 22 05:06:02 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-7cdbe0e9-0f0d-412e-a040-3468205a59cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1777427718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1777427718 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2799896236 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336421210000 ps |
| CPU time | 854.03 seconds |
| Started | Jun 22 04:37:04 PM PDT 24 |
| Finished | Jun 22 05:11:39 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-23cb8a07-76ae-4c8d-9d85-8889c91b5613 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2799896236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2799896236 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1615591455 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336882450000 ps |
| CPU time | 921.99 seconds |
| Started | Jun 22 04:37:05 PM PDT 24 |
| Finished | Jun 22 05:14:49 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-64a5fc6e-4841-4187-8cbb-def4a8a3ffd8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1615591455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1615591455 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2282096259 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336360210000 ps |
| CPU time | 675.28 seconds |
| Started | Jun 22 04:36:57 PM PDT 24 |
| Finished | Jun 22 05:04:29 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-0c4925b1-ae1f-467d-a1db-f44b11b9a6cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2282096259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2282096259 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.248961347 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336932770000 ps |
| CPU time | 607.57 seconds |
| Started | Jun 22 04:36:53 PM PDT 24 |
| Finished | Jun 22 05:02:01 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-06de87b5-3382-4051-9359-0f03538cd0e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=248961347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.248961347 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3278687894 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 337022230000 ps |
| CPU time | 982.83 seconds |
| Started | Jun 22 04:36:54 PM PDT 24 |
| Finished | Jun 22 05:16:48 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-5d64d7dc-bbeb-4bae-bf74-b37f3a5326c9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3278687894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3278687894 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3912898620 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336634510000 ps |
| CPU time | 848.4 seconds |
| Started | Jun 22 04:37:16 PM PDT 24 |
| Finished | Jun 22 05:11:45 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-02f986fe-2d3f-4df5-b5bb-6b8fbb2ff64a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3912898620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3912898620 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.932446916 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 337139650000 ps |
| CPU time | 513.54 seconds |
| Started | Jun 22 04:38:21 PM PDT 24 |
| Finished | Jun 22 05:00:51 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-7fc3580c-5cc7-40d1-bbba-14a494c93f22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=932446916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.932446916 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1122971258 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336408130000 ps |
| CPU time | 768.82 seconds |
| Started | Jun 22 04:36:49 PM PDT 24 |
| Finished | Jun 22 05:08:58 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-9c597ab7-73c0-4a16-94e2-c338d6fb79be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1122971258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1122971258 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1283811547 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336558110000 ps |
| CPU time | 717.08 seconds |
| Started | Jun 22 04:36:52 PM PDT 24 |
| Finished | Jun 22 05:06:47 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-f47548b1-a625-4827-98f4-7db8e8810f06 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1283811547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1283811547 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.429651364 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336790190000 ps |
| CPU time | 914.18 seconds |
| Started | Jun 22 04:37:03 PM PDT 24 |
| Finished | Jun 22 05:15:00 PM PDT 24 |
| Peak memory | 160856 kb |
| Host | smart-8f55410b-4d70-468a-801c-68f460afc817 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=429651364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.429651364 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2504633592 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336663950000 ps |
| CPU time | 788.55 seconds |
| Started | Jun 22 04:36:56 PM PDT 24 |
| Finished | Jun 22 05:09:09 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-58b48769-bf8f-40c3-9d7e-318cc96d625c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2504633592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2504633592 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2675784261 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336432450000 ps |
| CPU time | 961.61 seconds |
| Started | Jun 22 04:36:49 PM PDT 24 |
| Finished | Jun 22 05:16:45 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-93a8f733-8b74-4a08-ae9b-4cd1443ca42b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2675784261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2675784261 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3220886713 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336680130000 ps |
| CPU time | 917.29 seconds |
| Started | Jun 22 04:37:07 PM PDT 24 |
| Finished | Jun 22 05:15:11 PM PDT 24 |
| Peak memory | 160860 kb |
| Host | smart-220c3cfe-bc82-4a43-b558-5a9685f0689c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3220886713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3220886713 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1071607134 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336992410000 ps |
| CPU time | 790.63 seconds |
| Started | Jun 22 04:36:50 PM PDT 24 |
| Finished | Jun 22 05:09:14 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-2292d33c-b6df-44ad-b0c7-202d65c3ae1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1071607134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1071607134 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3193804481 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336795430000 ps |
| CPU time | 796.27 seconds |
| Started | Jun 22 04:37:16 PM PDT 24 |
| Finished | Jun 22 05:09:40 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-6714e232-6876-4109-b6ee-b54b17fcae51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3193804481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3193804481 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3835390875 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336378810000 ps |
| CPU time | 844.46 seconds |
| Started | Jun 22 04:37:26 PM PDT 24 |
| Finished | Jun 22 05:11:37 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-b9e14198-549d-47f7-9674-766dd288736b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3835390875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3835390875 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.914150935 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336435270000 ps |
| CPU time | 901.13 seconds |
| Started | Jun 22 04:36:50 PM PDT 24 |
| Finished | Jun 22 05:14:17 PM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-c802b5ff-aeab-42ad-99b7-7ee81cd5721b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=914150935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.914150935 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4196644626 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336400950000 ps |
| CPU time | 979.73 seconds |
| Started | Jun 22 04:37:07 PM PDT 24 |
| Finished | Jun 22 05:17:54 PM PDT 24 |
| Peak memory | 160456 kb |
| Host | smart-5e7971e4-6496-4ac9-ba51-dd57cc89d89e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4196644626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4196644626 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3306919745 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 337114410000 ps |
| CPU time | 911.23 seconds |
| Started | Jun 22 04:37:01 PM PDT 24 |
| Finished | Jun 22 05:15:00 PM PDT 24 |
| Peak memory | 160860 kb |
| Host | smart-55cc979b-ffc2-4cf6-9ff6-13a751a19b3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3306919745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3306919745 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3978763609 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336546850000 ps |
| CPU time | 766.08 seconds |
| Started | Jun 22 04:36:51 PM PDT 24 |
| Finished | Jun 22 05:08:31 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-4f5ff78a-4b2b-44e8-aca4-61636bd493a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3978763609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3978763609 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1155442341 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336421910000 ps |
| CPU time | 904.23 seconds |
| Started | Jun 22 04:37:12 PM PDT 24 |
| Finished | Jun 22 05:14:46 PM PDT 24 |
| Peak memory | 160860 kb |
| Host | smart-721fb9ed-cb92-43ce-804e-de406af508be |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1155442341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1155442341 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1706106939 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336830590000 ps |
| CPU time | 748.76 seconds |
| Started | Jun 22 04:37:06 PM PDT 24 |
| Finished | Jun 22 05:07:32 PM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-c8710628-cb02-401d-9e3b-8019c9c43601 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1706106939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1706106939 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3727809406 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 337083590000 ps |
| CPU time | 878.27 seconds |
| Started | Jun 22 04:36:50 PM PDT 24 |
| Finished | Jun 22 05:12:51 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-d1fcc5eb-d867-4615-9f6b-8a81dab168b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3727809406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3727809406 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.510553444 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336674010000 ps |
| CPU time | 622 seconds |
| Started | Jun 22 04:36:58 PM PDT 24 |
| Finished | Jun 22 05:03:08 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-b743795e-f066-45a0-9081-378e5ca31c7f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=510553444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.510553444 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2597544226 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337036650000 ps |
| CPU time | 743.2 seconds |
| Started | Jun 22 04:37:14 PM PDT 24 |
| Finished | Jun 22 05:07:34 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-2d00984d-03d6-45c2-b8b0-545d2b3f1d00 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2597544226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2597544226 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1526402220 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336857410000 ps |
| CPU time | 873.08 seconds |
| Started | Jun 22 04:36:56 PM PDT 24 |
| Finished | Jun 22 05:12:51 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-bc27bc9e-33b1-4449-932f-4e3092949c92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1526402220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1526402220 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4168197400 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336494810000 ps |
| CPU time | 670.38 seconds |
| Started | Jun 22 04:37:20 PM PDT 24 |
| Finished | Jun 22 05:05:14 PM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-2ae3277c-3949-435c-beb7-6b6fa3b0544c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4168197400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.4168197400 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1200069408 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336783690000 ps |
| CPU time | 805.61 seconds |
| Started | Jun 22 04:36:53 PM PDT 24 |
| Finished | Jun 22 05:09:48 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-d7c9e8cc-6ac2-47b7-bd7d-9133ac280d97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1200069408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1200069408 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3382758435 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336892590000 ps |
| CPU time | 666.88 seconds |
| Started | Jun 22 04:37:14 PM PDT 24 |
| Finished | Jun 22 05:04:29 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-cfede8ec-e44f-484e-9666-585abb0ef06e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3382758435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3382758435 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.309206280 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336735650000 ps |
| CPU time | 920.68 seconds |
| Started | Jun 22 04:37:08 PM PDT 24 |
| Finished | Jun 22 05:15:07 PM PDT 24 |
| Peak memory | 160856 kb |
| Host | smart-7f5d261e-280d-41d1-b45c-2c356a877698 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=309206280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.309206280 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.984053183 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336941170000 ps |
| CPU time | 917.76 seconds |
| Started | Jun 22 04:36:57 PM PDT 24 |
| Finished | Jun 22 05:14:56 PM PDT 24 |
| Peak memory | 160856 kb |
| Host | smart-d98f6e35-39da-4899-ac87-3553aa1c58c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=984053183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.984053183 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2770539326 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336465830000 ps |
| CPU time | 683.29 seconds |
| Started | Jun 22 04:37:02 PM PDT 24 |
| Finished | Jun 22 05:05:49 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-3833e6c7-2bad-44fb-b955-af3be1d6a0d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2770539326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2770539326 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.694227514 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336933970000 ps |
| CPU time | 944.97 seconds |
| Started | Jun 22 04:37:01 PM PDT 24 |
| Finished | Jun 22 05:15:56 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-f44ae2c7-86d1-4adc-a8e6-581572257811 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=694227514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.694227514 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2414583973 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 337118950000 ps |
| CPU time | 911.55 seconds |
| Started | Jun 22 04:36:52 PM PDT 24 |
| Finished | Jun 22 05:14:32 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-d8d51528-5b60-4090-bcc4-7fe00be07016 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2414583973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2414583973 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3912426706 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336299930000 ps |
| CPU time | 988.46 seconds |
| Started | Jun 22 04:36:56 PM PDT 24 |
| Finished | Jun 22 05:18:48 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-047d8e9f-95a7-4ef4-baef-5688541ff1ba |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3912426706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3912426706 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1861930611 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336488310000 ps |
| CPU time | 908.31 seconds |
| Started | Jun 22 04:39:42 PM PDT 24 |
| Finished | Jun 22 05:16:26 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-7d782886-2e49-461b-bb04-9062de4194ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1861930611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1861930611 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2541672283 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336995790000 ps |
| CPU time | 760.3 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 05:10:41 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-ba784f78-4c97-42b1-91a5-3de8213fac6d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2541672283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2541672283 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1984488125 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336549030000 ps |
| CPU time | 909.33 seconds |
| Started | Jun 22 04:39:48 PM PDT 24 |
| Finished | Jun 22 05:16:18 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-fcfc4ba1-58e6-472f-afa5-6d905c723925 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1984488125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1984488125 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.4133233778 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336426810000 ps |
| CPU time | 866.16 seconds |
| Started | Jun 22 04:39:33 PM PDT 24 |
| Finished | Jun 22 05:15:09 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-f23e2fc8-4709-4f62-be5a-fca5011569f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4133233778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.4133233778 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3104992448 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336973930000 ps |
| CPU time | 946.46 seconds |
| Started | Jun 22 04:39:42 PM PDT 24 |
| Finished | Jun 22 05:18:31 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-845103bc-778d-41df-83fb-9fbe26755f3c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3104992448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3104992448 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2403733552 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336497510000 ps |
| CPU time | 910.95 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 05:17:49 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-0236a472-8fa2-487d-809b-98adcbc96d40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2403733552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2403733552 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2741138822 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336774410000 ps |
| CPU time | 866.42 seconds |
| Started | Jun 22 04:39:50 PM PDT 24 |
| Finished | Jun 22 05:15:00 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-ee2f14c0-c3db-4e2d-8156-978743323742 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2741138822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2741138822 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.398756808 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336812730000 ps |
| CPU time | 684.04 seconds |
| Started | Jun 22 04:39:35 PM PDT 24 |
| Finished | Jun 22 05:08:21 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-1bcbf5d4-1d5e-4966-82f2-a28b90c77a36 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=398756808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.398756808 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2590757730 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336405530000 ps |
| CPU time | 821.24 seconds |
| Started | Jun 22 04:40:04 PM PDT 24 |
| Finished | Jun 22 05:13:47 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-7d43cba6-8a91-4ee7-81b2-d25f2986d7e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2590757730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2590757730 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3063988871 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336903670000 ps |
| CPU time | 996.41 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 05:22:25 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-abc58577-f65c-452c-9c5e-b341a7b7b124 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3063988871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3063988871 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1218359303 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336618210000 ps |
| CPU time | 749.34 seconds |
| Started | Jun 22 04:39:46 PM PDT 24 |
| Finished | Jun 22 05:09:58 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-00e35a48-7d09-471b-ade1-69a35d6f497b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1218359303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1218359303 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4021154119 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336467030000 ps |
| CPU time | 781.51 seconds |
| Started | Jun 22 04:39:39 PM PDT 24 |
| Finished | Jun 22 05:11:49 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-7b30c13f-ae6a-47a6-b30e-e42934c61a53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4021154119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.4021154119 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2345515642 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336462890000 ps |
| CPU time | 869.95 seconds |
| Started | Jun 22 04:39:47 PM PDT 24 |
| Finished | Jun 22 05:14:47 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-175c19c3-2976-4b35-a5a6-ecf2f03c7f78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2345515642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2345515642 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1870814464 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336621970000 ps |
| CPU time | 779.36 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 05:12:13 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-3c82835f-607b-4797-85bd-462d3824dde6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1870814464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1870814464 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2837879223 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336960210000 ps |
| CPU time | 753.4 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 05:10:46 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-a6e06181-6b36-4a0e-84bc-64abbd696131 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2837879223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2837879223 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.486579481 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336406870000 ps |
| CPU time | 906.94 seconds |
| Started | Jun 22 04:39:36 PM PDT 24 |
| Finished | Jun 22 05:17:34 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-98ebdbeb-6cb8-49b8-97a7-a100d228d9d2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=486579481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.486579481 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2334801320 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336345870000 ps |
| CPU time | 782.39 seconds |
| Started | Jun 22 04:39:46 PM PDT 24 |
| Finished | Jun 22 05:11:28 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-875b4ac3-1589-4fa1-b660-2b59e413ee3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2334801320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2334801320 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3687001357 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336633410000 ps |
| CPU time | 1014.53 seconds |
| Started | Jun 22 04:40:01 PM PDT 24 |
| Finished | Jun 22 05:22:44 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-54265fc9-9bca-4ca2-80d8-6883283f6da6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3687001357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3687001357 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1191475179 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336530630000 ps |
| CPU time | 752.52 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 05:10:29 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-9ad30abe-68a3-46bc-8810-433ff4c93948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1191475179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1191475179 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3952608788 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336854810000 ps |
| CPU time | 854.47 seconds |
| Started | Jun 22 04:39:34 PM PDT 24 |
| Finished | Jun 22 05:14:49 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-22c9f490-c9b4-4a8a-9c62-e9fb079daddf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3952608788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3952608788 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.585792545 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336478610000 ps |
| CPU time | 780.26 seconds |
| Started | Jun 22 04:39:38 PM PDT 24 |
| Finished | Jun 22 05:11:23 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-976eebfa-b012-41b6-ad54-b9c51f3f7fcd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=585792545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.585792545 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.20872977 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336708450000 ps |
| CPU time | 979.4 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 05:21:34 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-812e174c-c709-4d67-949f-e184f4f43320 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=20872977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.20872977 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3857355129 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336709870000 ps |
| CPU time | 890.73 seconds |
| Started | Jun 22 04:39:34 PM PDT 24 |
| Finished | Jun 22 05:16:08 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-4221f9ba-aabe-434a-a20e-7f507005c2f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3857355129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3857355129 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2892652655 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336846750000 ps |
| CPU time | 792.98 seconds |
| Started | Jun 22 04:39:48 PM PDT 24 |
| Finished | Jun 22 05:12:06 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-93eae42e-47b5-442a-bc4e-8e7a08a3c268 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2892652655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2892652655 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2694010496 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 337064690000 ps |
| CPU time | 780.08 seconds |
| Started | Jun 22 04:39:41 PM PDT 24 |
| Finished | Jun 22 05:12:04 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-acdcb0ca-c870-4977-87b0-f76c4fed6b47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2694010496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2694010496 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4165164040 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336704090000 ps |
| CPU time | 755.96 seconds |
| Started | Jun 22 04:39:34 PM PDT 24 |
| Finished | Jun 22 05:10:05 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-09e57f8d-647f-4ac5-8c72-b8300d3a7e74 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4165164040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4165164040 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3153311738 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 337001570000 ps |
| CPU time | 777.28 seconds |
| Started | Jun 22 04:39:56 PM PDT 24 |
| Finished | Jun 22 05:12:27 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-db0018f9-6f75-4aa9-ad5a-8421adf59960 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3153311738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3153311738 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4078229264 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 337040890000 ps |
| CPU time | 809.95 seconds |
| Started | Jun 22 04:39:45 PM PDT 24 |
| Finished | Jun 22 05:12:42 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-7f4136c9-61b7-419b-b477-ae270556e042 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4078229264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.4078229264 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1231997914 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336951250000 ps |
| CPU time | 821.54 seconds |
| Started | Jun 22 04:39:35 PM PDT 24 |
| Finished | Jun 22 05:12:50 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-daeaf7ef-e82d-4e9c-b49a-bdc4654a33e7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1231997914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1231997914 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3390528590 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336629670000 ps |
| CPU time | 907.34 seconds |
| Started | Jun 22 04:39:49 PM PDT 24 |
| Finished | Jun 22 05:16:49 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-381be575-110e-4b96-be9a-dd85e0a49f12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3390528590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3390528590 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4282946357 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336733110000 ps |
| CPU time | 847.84 seconds |
| Started | Jun 22 04:39:37 PM PDT 24 |
| Finished | Jun 22 05:14:05 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-f8a2ec74-da81-411d-bcf2-80e884407302 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4282946357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4282946357 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3063298812 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336898790000 ps |
| CPU time | 825.82 seconds |
| Started | Jun 22 04:39:46 PM PDT 24 |
| Finished | Jun 22 05:13:20 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-3dc31f72-0100-4520-8b7b-ff11bcdbe2ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3063298812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3063298812 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1951785540 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336671790000 ps |
| CPU time | 895.96 seconds |
| Started | Jun 22 04:39:38 PM PDT 24 |
| Finished | Jun 22 05:16:32 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-96f60acb-0902-472c-8639-fb219f1a9faa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1951785540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1951785540 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3847400617 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336731530000 ps |
| CPU time | 928.73 seconds |
| Started | Jun 22 04:39:48 PM PDT 24 |
| Finished | Jun 22 05:18:23 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-96ebeb5f-a602-49ae-8825-4f734d0b0a82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3847400617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.3847400617 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3457603627 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336664790000 ps |
| CPU time | 857.97 seconds |
| Started | Jun 22 04:39:35 PM PDT 24 |
| Finished | Jun 22 05:14:47 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-48cb7721-8ccc-4d8b-8834-97e1285929c5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3457603627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3457603627 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2311354602 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336864570000 ps |
| CPU time | 935.58 seconds |
| Started | Jun 22 04:39:48 PM PDT 24 |
| Finished | Jun 22 05:18:21 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-f7136c12-1f6a-45ec-9996-cf197f025b70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2311354602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2311354602 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3454366421 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336652670000 ps |
| CPU time | 957.97 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 05:19:12 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-c7d9ceac-855d-4807-98a7-3261b65f24de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3454366421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3454366421 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3322539022 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 337102790000 ps |
| CPU time | 776.51 seconds |
| Started | Jun 22 04:39:40 PM PDT 24 |
| Finished | Jun 22 05:11:51 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-1f267fbc-6219-4389-9fa1-501ccfc2eddb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3322539022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3322539022 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1105216944 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336492890000 ps |
| CPU time | 769.96 seconds |
| Started | Jun 22 04:39:50 PM PDT 24 |
| Finished | Jun 22 05:11:35 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-224537de-674e-4d72-a704-e902d0bbd3cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1105216944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1105216944 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2910448135 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336354770000 ps |
| CPU time | 971.28 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 05:21:29 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-c07f2097-59b0-479c-851e-57184aca7c0f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2910448135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2910448135 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.733789121 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336975890000 ps |
| CPU time | 687.27 seconds |
| Started | Jun 22 04:39:50 PM PDT 24 |
| Finished | Jun 22 05:07:41 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-e1913ed2-84f7-4d3e-87c3-54b9113f2457 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=733789121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.733789121 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2090600628 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336837730000 ps |
| CPU time | 749.71 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 05:11:22 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-373665bc-20f2-43e7-8068-7ba46d46f422 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2090600628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2090600628 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1339052813 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336759710000 ps |
| CPU time | 758.73 seconds |
| Started | Jun 22 04:39:55 PM PDT 24 |
| Finished | Jun 22 05:10:35 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-a4f8034f-d294-4f28-a282-54073b3f023b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1339052813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1339052813 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1747140856 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336554370000 ps |
| CPU time | 1005.46 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 05:22:30 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-3c692f29-a249-45e6-aa84-3c9c49035f5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1747140856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1747140856 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1286856381 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336591690000 ps |
| CPU time | 816.21 seconds |
| Started | Jun 22 04:39:34 PM PDT 24 |
| Finished | Jun 22 05:12:43 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-a96d0f9f-8b61-4950-ba98-58caa0a08f9c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1286856381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1286856381 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.530050626 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 337018610000 ps |
| CPU time | 776.13 seconds |
| Started | Jun 22 04:39:34 PM PDT 24 |
| Finished | Jun 22 05:11:39 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-bd3b1796-2476-46e3-9fce-7a980141fb04 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=530050626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.530050626 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2562064134 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336911590000 ps |
| CPU time | 705.47 seconds |
| Started | Jun 22 04:39:35 PM PDT 24 |
| Finished | Jun 22 05:08:24 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-08f9c602-7275-4cf6-900e-3e59ee56bae9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2562064134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2562064134 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2146110681 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336534410000 ps |
| CPU time | 732.43 seconds |
| Started | Jun 22 04:39:43 PM PDT 24 |
| Finished | Jun 22 05:09:32 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-782c3103-0372-455e-8927-4b6225ca16f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2146110681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2146110681 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3559439307 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336466050000 ps |
| CPU time | 780.84 seconds |
| Started | Jun 22 04:39:42 PM PDT 24 |
| Finished | Jun 22 05:12:11 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-ea5c64bc-4e14-4bf8-b5d0-415eae6d5079 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3559439307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3559439307 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1318789291 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1428910000 ps |
| CPU time | 3.83 seconds |
| Started | Jun 22 04:39:07 PM PDT 24 |
| Finished | Jun 22 04:39:17 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-91c6f791-008e-4c1b-89cc-c5c25404a0e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1318789291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1318789291 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2595646603 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1465630000 ps |
| CPU time | 3.21 seconds |
| Started | Jun 22 04:39:12 PM PDT 24 |
| Finished | Jun 22 04:39:22 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-6b8b1722-377a-4610-8af0-aa1309519af1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2595646603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2595646603 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3950456668 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1522230000 ps |
| CPU time | 4.22 seconds |
| Started | Jun 22 04:39:17 PM PDT 24 |
| Finished | Jun 22 04:39:28 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-09c6b8a3-0012-4757-8b87-92543596c23f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3950456668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3950456668 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2528935250 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1466370000 ps |
| CPU time | 3.75 seconds |
| Started | Jun 22 04:39:18 PM PDT 24 |
| Finished | Jun 22 04:39:27 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-83790938-bfa6-4940-bd9e-e91a7e6de09a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2528935250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2528935250 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.34998049 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1349690000 ps |
| CPU time | 3.13 seconds |
| Started | Jun 22 04:39:23 PM PDT 24 |
| Finished | Jun 22 04:39:31 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-8ebeeebf-8bb6-4d6b-a5d7-f94b687ed72e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=34998049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.34998049 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4160685304 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1584270000 ps |
| CPU time | 3.41 seconds |
| Started | Jun 22 04:39:30 PM PDT 24 |
| Finished | Jun 22 04:39:39 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-d1f52586-228c-4460-99ca-a472687829b2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4160685304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.4160685304 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1931322437 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1500750000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 22 04:39:19 PM PDT 24 |
| Finished | Jun 22 04:39:30 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-f7fbe016-893b-49be-8755-551cff89c722 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1931322437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1931322437 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.2859095863 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1602030000 ps |
| CPU time | 5.31 seconds |
| Started | Jun 22 04:39:32 PM PDT 24 |
| Finished | Jun 22 04:39:46 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-66c6dd66-87dd-45b3-b9f8-f7e8e8d9a2ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2859095863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.2859095863 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1074768161 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1452930000 ps |
| CPU time | 4.72 seconds |
| Started | Jun 22 04:39:14 PM PDT 24 |
| Finished | Jun 22 04:39:26 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-429ca55b-37a9-4b07-8ab9-1455ef7e5881 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1074768161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1074768161 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1906856070 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1490870000 ps |
| CPU time | 5.4 seconds |
| Started | Jun 22 04:39:27 PM PDT 24 |
| Finished | Jun 22 04:39:39 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-69f2602b-f0a2-4cea-b7ec-32e8c315cb7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1906856070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1906856070 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1148122389 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1383090000 ps |
| CPU time | 3.93 seconds |
| Started | Jun 22 04:39:19 PM PDT 24 |
| Finished | Jun 22 04:39:29 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-ae1fba3a-9fd2-4050-84c1-63d264ba8a33 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1148122389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1148122389 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.709682545 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1492830000 ps |
| CPU time | 4.72 seconds |
| Started | Jun 22 04:39:15 PM PDT 24 |
| Finished | Jun 22 04:39:26 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-42433ba8-50f5-470f-890d-f0d8ce6ac486 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=709682545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.709682545 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3002367123 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1555530000 ps |
| CPU time | 4.49 seconds |
| Started | Jun 22 04:39:16 PM PDT 24 |
| Finished | Jun 22 04:39:27 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-c5f66eb1-4a36-40c3-8a86-8363a4f55e6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3002367123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3002367123 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1028993679 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1515290000 ps |
| CPU time | 3.73 seconds |
| Started | Jun 22 04:39:27 PM PDT 24 |
| Finished | Jun 22 04:39:37 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-064fe437-4ee6-4d5e-9081-8fdb051db22c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1028993679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1028993679 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.573194917 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1155530000 ps |
| CPU time | 3.9 seconds |
| Started | Jun 22 04:39:17 PM PDT 24 |
| Finished | Jun 22 04:39:26 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-b2616653-8fbb-48be-a4b6-fe893718f52a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=573194917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.573194917 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2706704538 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1348690000 ps |
| CPU time | 4.36 seconds |
| Started | Jun 22 04:39:18 PM PDT 24 |
| Finished | Jun 22 04:39:29 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-2f8ccdcc-5c86-4a0f-a0cc-b4683eb2632c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2706704538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2706704538 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3458989641 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1551570000 ps |
| CPU time | 5.08 seconds |
| Started | Jun 22 04:39:17 PM PDT 24 |
| Finished | Jun 22 04:39:29 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-94d3d8a5-8efd-4549-8c56-a0603fce3e14 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3458989641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3458989641 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2129544043 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1478350000 ps |
| CPU time | 4.26 seconds |
| Started | Jun 22 04:39:18 PM PDT 24 |
| Finished | Jun 22 04:39:28 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-aac63cdd-81e4-4ba8-8116-6657e656196e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2129544043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2129544043 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4102328616 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1378730000 ps |
| CPU time | 3.33 seconds |
| Started | Jun 22 04:39:17 PM PDT 24 |
| Finished | Jun 22 04:39:26 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-42e3cf30-c8fa-4ed2-9136-051c137b63f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4102328616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4102328616 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1085115184 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1181330000 ps |
| CPU time | 3.88 seconds |
| Started | Jun 22 04:39:24 PM PDT 24 |
| Finished | Jun 22 04:39:33 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-d139b61b-aa8d-4e85-b55c-a0a2daa9f7b4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1085115184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1085115184 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.942696739 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1483270000 ps |
| CPU time | 3.39 seconds |
| Started | Jun 22 04:39:47 PM PDT 24 |
| Finished | Jun 22 04:39:55 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-3be5ef19-a048-47dd-aa82-b11f7dc0ba15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=942696739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.942696739 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.831612684 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1485430000 ps |
| CPU time | 3.03 seconds |
| Started | Jun 22 04:39:26 PM PDT 24 |
| Finished | Jun 22 04:39:35 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-ce2a4f73-f602-4f91-8e6d-3db9e3f387cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=831612684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.831612684 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3109346112 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1291990000 ps |
| CPU time | 2.81 seconds |
| Started | Jun 22 04:39:19 PM PDT 24 |
| Finished | Jun 22 04:39:26 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-12c5270c-58a5-427d-8fa6-d2b2c0256ece |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3109346112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3109346112 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2415368978 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1525610000 ps |
| CPU time | 4.18 seconds |
| Started | Jun 22 04:39:20 PM PDT 24 |
| Finished | Jun 22 04:39:31 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-8d8fbdfa-dca1-4e26-aea8-bdd640f36275 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2415368978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2415368978 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.90258437 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1341650000 ps |
| CPU time | 4.53 seconds |
| Started | Jun 22 04:39:32 PM PDT 24 |
| Finished | Jun 22 04:39:45 PM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-b23022ae-828b-4de1-b0b2-4151c295186c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=90258437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.90258437 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1958324535 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1520090000 ps |
| CPU time | 4.5 seconds |
| Started | Jun 22 04:39:18 PM PDT 24 |
| Finished | Jun 22 04:39:29 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-a05a7570-7227-4e8f-ad95-6df80d5ca272 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1958324535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1958324535 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.346655592 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1580890000 ps |
| CPU time | 3.65 seconds |
| Started | Jun 22 04:39:22 PM PDT 24 |
| Finished | Jun 22 04:39:31 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-fafb05ca-4f57-4688-a209-11d2f5b70817 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=346655592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.346655592 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.696604763 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1556570000 ps |
| CPU time | 3.82 seconds |
| Started | Jun 22 04:39:27 PM PDT 24 |
| Finished | Jun 22 04:39:37 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-7efca54f-f8c0-4e29-8528-d772ee1c5f2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=696604763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.696604763 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2552788711 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1621950000 ps |
| CPU time | 3.82 seconds |
| Started | Jun 22 04:39:25 PM PDT 24 |
| Finished | Jun 22 04:39:34 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-b3e8eed6-0db4-4be9-8cfe-280a2d91d686 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2552788711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2552788711 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3694630451 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1487390000 ps |
| CPU time | 4 seconds |
| Started | Jun 22 04:39:11 PM PDT 24 |
| Finished | Jun 22 04:39:22 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-cc6c8e50-be09-453c-be63-14b637388128 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3694630451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3694630451 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.678653927 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1448030000 ps |
| CPU time | 4.63 seconds |
| Started | Jun 22 04:39:16 PM PDT 24 |
| Finished | Jun 22 04:39:27 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-626131ae-51fb-486e-8a9c-5b6a6a5d4b67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=678653927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.678653927 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2481909910 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1488050000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 22 04:39:16 PM PDT 24 |
| Finished | Jun 22 04:39:26 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-911a24ac-c33d-4aca-81d1-72bb534f0b55 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2481909910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2481909910 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1222424911 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1476070000 ps |
| CPU time | 4.75 seconds |
| Started | Jun 22 04:39:27 PM PDT 24 |
| Finished | Jun 22 04:39:39 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-2cbf8b20-dd29-4e97-b8ce-b8163b54dac3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1222424911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1222424911 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3832945108 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1539250000 ps |
| CPU time | 3.98 seconds |
| Started | Jun 22 04:39:20 PM PDT 24 |
| Finished | Jun 22 04:39:30 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-13eea759-a5f7-42e4-a8ab-976c94b7bab5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3832945108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3832945108 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1859248601 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1583590000 ps |
| CPU time | 4.71 seconds |
| Started | Jun 22 04:39:20 PM PDT 24 |
| Finished | Jun 22 04:39:32 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-9d78f73a-88a4-4661-90f7-29205a3f32a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1859248601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1859248601 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1357254970 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1494950000 ps |
| CPU time | 3.14 seconds |
| Started | Jun 22 04:39:22 PM PDT 24 |
| Finished | Jun 22 04:39:30 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-3a11f4b8-1013-4645-96ef-0a3815975521 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1357254970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1357254970 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3265124459 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1558290000 ps |
| CPU time | 3.26 seconds |
| Started | Jun 22 04:39:26 PM PDT 24 |
| Finished | Jun 22 04:39:35 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-6cbf99ba-8fb2-47db-b045-a2a9d68b7129 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3265124459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3265124459 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2402799970 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1375010000 ps |
| CPU time | 3.23 seconds |
| Started | Jun 22 04:39:24 PM PDT 24 |
| Finished | Jun 22 04:39:31 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-2718299e-2b1f-4685-aec6-5796417f72f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2402799970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2402799970 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1430595790 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1506150000 ps |
| CPU time | 3.62 seconds |
| Started | Jun 22 04:39:26 PM PDT 24 |
| Finished | Jun 22 04:39:35 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-f97e69f2-abdf-47a1-b204-71e5357877a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1430595790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1430595790 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1934936524 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1433690000 ps |
| CPU time | 3.25 seconds |
| Started | Jun 22 04:39:28 PM PDT 24 |
| Finished | Jun 22 04:39:36 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-246e8098-9ff7-4bc5-8da3-b5cfd69888b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1934936524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1934936524 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4020150299 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1489710000 ps |
| CPU time | 4.98 seconds |
| Started | Jun 22 04:39:27 PM PDT 24 |
| Finished | Jun 22 04:39:39 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-224a4cb3-f4a7-47ea-875e-79bd56de76e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4020150299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4020150299 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2432995860 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1503950000 ps |
| CPU time | 3.6 seconds |
| Started | Jun 22 04:39:19 PM PDT 24 |
| Finished | Jun 22 04:39:28 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-eeb9b780-0e38-4642-b0c9-4e280252fd15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2432995860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2432995860 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3982214794 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1552130000 ps |
| CPU time | 3.4 seconds |
| Started | Jun 22 04:39:28 PM PDT 24 |
| Finished | Jun 22 04:39:37 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-3e6675a1-f212-495f-9cf4-9c2dcc67146a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3982214794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3982214794 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1944830637 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1563090000 ps |
| CPU time | 4.31 seconds |
| Started | Jun 22 04:39:24 PM PDT 24 |
| Finished | Jun 22 04:39:34 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-a76b8dfb-ef76-46c1-94c7-02fdf865ee24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1944830637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1944830637 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1463954541 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1480130000 ps |
| CPU time | 4.61 seconds |
| Started | Jun 22 04:39:26 PM PDT 24 |
| Finished | Jun 22 04:39:38 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-da33465b-b65e-4b43-8a51-1ed6a071a29b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1463954541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1463954541 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3541219609 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1557170000 ps |
| CPU time | 4.97 seconds |
| Started | Jun 22 04:39:17 PM PDT 24 |
| Finished | Jun 22 04:39:29 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-6deb9440-fb81-40ab-8d98-cee7411f873d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3541219609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3541219609 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1240147682 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1421990000 ps |
| CPU time | 5.42 seconds |
| Started | Jun 22 04:39:16 PM PDT 24 |
| Finished | Jun 22 04:39:29 PM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-22f359ab-75c6-4669-8ee9-58749339ffc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1240147682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1240147682 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1590379487 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1355510000 ps |
| CPU time | 4.23 seconds |
| Started | Jun 22 04:39:11 PM PDT 24 |
| Finished | Jun 22 04:39:23 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-f2a64945-16a2-461f-bfb4-efaffff67b18 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1590379487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1590379487 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.224756577 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1626390000 ps |
| CPU time | 4.65 seconds |
| Started | Jun 22 04:39:11 PM PDT 24 |
| Finished | Jun 22 04:39:24 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-db2142f7-5d4b-4356-91a8-3d04f4f5673e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=224756577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.224756577 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3072201042 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1540710000 ps |
| CPU time | 4.67 seconds |
| Started | Jun 22 04:40:02 PM PDT 24 |
| Finished | Jun 22 04:40:14 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-3ed70ec3-0ab3-4e21-a88d-a8d49c362734 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3072201042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3072201042 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2483436206 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1419230000 ps |
| CPU time | 4.04 seconds |
| Started | Jun 22 04:39:57 PM PDT 24 |
| Finished | Jun 22 04:40:07 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-23f6552c-3e17-4412-b3ad-18f524fcb2b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2483436206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2483436206 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2516225468 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1535030000 ps |
| CPU time | 4.65 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:40:11 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-c5fcf92e-dca8-409a-a1c7-0813f32e0b25 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2516225468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2516225468 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.924834929 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1526970000 ps |
| CPU time | 4.18 seconds |
| Started | Jun 22 04:39:50 PM PDT 24 |
| Finished | Jun 22 04:39:59 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-7bbc1170-5bb0-4ebf-a3f0-7e7c178e2f97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=924834929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.924834929 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2607412786 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1472850000 ps |
| CPU time | 4.83 seconds |
| Started | Jun 22 04:39:58 PM PDT 24 |
| Finished | Jun 22 04:40:12 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-138a81a6-1638-4763-88d8-e8aa1442f086 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2607412786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2607412786 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.91415998 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1554750000 ps |
| CPU time | 5.25 seconds |
| Started | Jun 22 04:39:53 PM PDT 24 |
| Finished | Jun 22 04:40:06 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-6c04748d-5a98-4131-9b27-200075c356b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=91415998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.91415998 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3498256586 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1431730000 ps |
| CPU time | 4.48 seconds |
| Started | Jun 22 04:40:07 PM PDT 24 |
| Finished | Jun 22 04:40:18 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-7296b49c-f111-4b57-ba4f-dc11b11b4e51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3498256586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3498256586 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2698849106 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1256630000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 22 04:39:54 PM PDT 24 |
| Finished | Jun 22 04:40:05 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-d32891f6-c2bc-467b-96eb-cb24a504b761 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2698849106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2698849106 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1364867098 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1540770000 ps |
| CPU time | 5.65 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:40:17 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-66a994f1-6b6a-41d0-9409-120c1d316647 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1364867098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1364867098 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1222920309 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1426310000 ps |
| CPU time | 2.95 seconds |
| Started | Jun 22 04:39:58 PM PDT 24 |
| Finished | Jun 22 04:40:06 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-3ce666c2-a2dc-4ed0-bb39-d419a63857ad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1222920309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1222920309 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.896572192 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1445370000 ps |
| CPU time | 6.44 seconds |
| Started | Jun 22 04:40:11 PM PDT 24 |
| Finished | Jun 22 04:40:26 PM PDT 24 |
| Peak memory | 165044 kb |
| Host | smart-9694dd75-713c-4963-9f8c-d5e43667d30b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=896572192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.896572192 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2766467018 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1485450000 ps |
| CPU time | 5.01 seconds |
| Started | Jun 22 04:39:40 PM PDT 24 |
| Finished | Jun 22 04:39:53 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-38f28afd-0bda-4c9c-9d76-9b8c756ed862 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2766467018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2766467018 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1923942624 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1424030000 ps |
| CPU time | 3.44 seconds |
| Started | Jun 22 04:40:07 PM PDT 24 |
| Finished | Jun 22 04:40:16 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-8d0d2254-39c3-4f0d-8a39-ff02ec39a94a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1923942624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1923942624 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2825273628 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1450370000 ps |
| CPU time | 3.71 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 04:40:01 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-3e74ee45-bf5a-44de-b176-dca6c8e8a51f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2825273628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2825273628 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.4057254282 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1444330000 ps |
| CPU time | 3.52 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:40:09 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-b8cbdf33-c931-4b14-b138-0ccb5c7d1674 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4057254282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.4057254282 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2744921280 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1604230000 ps |
| CPU time | 4.23 seconds |
| Started | Jun 22 04:39:54 PM PDT 24 |
| Finished | Jun 22 04:40:05 PM PDT 24 |
| Peak memory | 164856 kb |
| Host | smart-503da3cc-6244-4f66-8444-9fd9c5245c2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2744921280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2744921280 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3435257824 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1509250000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 22 04:39:55 PM PDT 24 |
| Finished | Jun 22 04:40:07 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-c426ff3a-52c4-4340-b17b-a59dd48d8d7f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3435257824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3435257824 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.986402544 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1372310000 ps |
| CPU time | 3.53 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:40:09 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-725656d1-2abb-4f9d-bd87-5c58fe9078a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=986402544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.986402544 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.796609631 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1398070000 ps |
| CPU time | 3.56 seconds |
| Started | Jun 22 04:39:53 PM PDT 24 |
| Finished | Jun 22 04:40:02 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-490cc647-ab76-4f82-8dc6-ff39572c9268 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=796609631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.796609631 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.320749756 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1505710000 ps |
| CPU time | 4.12 seconds |
| Started | Jun 22 04:39:48 PM PDT 24 |
| Finished | Jun 22 04:39:58 PM PDT 24 |
| Peak memory | 164760 kb |
| Host | smart-ef621176-abcc-4971-aafe-b988e22f0941 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=320749756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.320749756 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4116028917 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1469770000 ps |
| CPU time | 3.64 seconds |
| Started | Jun 22 04:39:50 PM PDT 24 |
| Finished | Jun 22 04:39:59 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-fe3118b5-7724-476b-b7fe-d7eb3378c2ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4116028917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4116028917 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.625624327 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1323470000 ps |
| CPU time | 4.36 seconds |
| Started | Jun 22 04:40:07 PM PDT 24 |
| Finished | Jun 22 04:40:17 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-c996bf0d-e693-45e8-92de-ab461894eee2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=625624327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.625624327 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1776352078 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1384810000 ps |
| CPU time | 4.11 seconds |
| Started | Jun 22 04:40:00 PM PDT 24 |
| Finished | Jun 22 04:40:11 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-9b302654-1f4c-4666-83a5-866184df7b54 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1776352078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1776352078 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.441059584 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1363110000 ps |
| CPU time | 4.59 seconds |
| Started | Jun 22 04:39:54 PM PDT 24 |
| Finished | Jun 22 04:40:05 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-6b4b6a9c-dddd-4ea3-a3c1-c47f35b9ae71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=441059584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.441059584 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2339680443 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1385110000 ps |
| CPU time | 2.89 seconds |
| Started | Jun 22 04:40:07 PM PDT 24 |
| Finished | Jun 22 04:40:14 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-d9f9f176-84d4-4231-8f6e-8b3745efb09f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2339680443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2339680443 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.655547379 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1557350000 ps |
| CPU time | 4.45 seconds |
| Started | Jun 22 04:39:47 PM PDT 24 |
| Finished | Jun 22 04:39:58 PM PDT 24 |
| Peak memory | 164780 kb |
| Host | smart-8fdd1279-c79a-4b6f-bd5c-1f00ef1ed0d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=655547379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.655547379 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3859856719 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1570570000 ps |
| CPU time | 3.88 seconds |
| Started | Jun 22 04:39:46 PM PDT 24 |
| Finished | Jun 22 04:39:55 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-cba6fc3f-e167-4bfb-8d74-6daca8d48eab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3859856719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3859856719 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3301092234 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1421530000 ps |
| CPU time | 4.51 seconds |
| Started | Jun 22 04:39:56 PM PDT 24 |
| Finished | Jun 22 04:40:07 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-2db89aa9-bf62-4f21-8444-4dc7805225b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3301092234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3301092234 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.797385868 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1132550000 ps |
| CPU time | 4.38 seconds |
| Started | Jun 22 04:39:56 PM PDT 24 |
| Finished | Jun 22 04:40:07 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-9d2a3b52-9a76-4770-80b4-d99af64cb39f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=797385868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.797385868 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2638850954 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1151670000 ps |
| CPU time | 3.66 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 04:40:00 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-17f4554b-e2ec-4da1-a9f0-ebcd6f3f7ada |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2638850954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2638850954 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1710549671 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1520190000 ps |
| CPU time | 4.85 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 04:40:02 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-42c51905-4c65-44d3-9f49-518cce93c85f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1710549671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1710549671 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1488338013 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1552650000 ps |
| CPU time | 5.45 seconds |
| Started | Jun 22 04:39:57 PM PDT 24 |
| Finished | Jun 22 04:40:11 PM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-62474b41-e805-4294-be10-c177944d0410 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1488338013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1488338013 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2225082668 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1435770000 ps |
| CPU time | 3.2 seconds |
| Started | Jun 22 04:39:51 PM PDT 24 |
| Finished | Jun 22 04:39:59 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-5b1a80ca-a803-4bc8-b1f3-c79d3ebfa0a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2225082668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2225082668 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3020453413 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1567870000 ps |
| CPU time | 4.63 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 04:40:09 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-624938d6-26aa-4ccf-9a3e-354efe5ab7d8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3020453413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3020453413 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3714923697 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1592750000 ps |
| CPU time | 5.42 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:40:13 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-47ca2fc5-b126-456b-9c06-8d463e7df11c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3714923697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3714923697 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1728719740 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1441210000 ps |
| CPU time | 3.55 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:40:13 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-e438abf5-6d00-4941-871b-7ae5e032daca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1728719740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1728719740 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2951077484 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1534090000 ps |
| CPU time | 3.37 seconds |
| Started | Jun 22 04:39:45 PM PDT 24 |
| Finished | Jun 22 04:39:53 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-52b2f469-0180-47f6-9a02-ba141b4bc1da |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2951077484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2951077484 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.586962862 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1468190000 ps |
| CPU time | 4.86 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:40:12 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-4a9d93f6-d421-4a8c-a283-3bd476c49106 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=586962862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.586962862 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2269720812 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1443430000 ps |
| CPU time | 4.4 seconds |
| Started | Jun 22 04:40:03 PM PDT 24 |
| Finished | Jun 22 04:40:15 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-4ce2cd3b-433b-473f-a412-6a5029333bc1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2269720812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2269720812 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2206800356 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1221870000 ps |
| CPU time | 3.41 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 04:40:00 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-3f40ac71-be6f-4a81-8fba-48b229dc7548 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2206800356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2206800356 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2141072911 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1317430000 ps |
| CPU time | 3.25 seconds |
| Started | Jun 22 04:40:06 PM PDT 24 |
| Finished | Jun 22 04:40:14 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-e8599012-3aa1-49ed-8961-4fa204e84a30 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2141072911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2141072911 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1238271562 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1294470000 ps |
| CPU time | 3.85 seconds |
| Started | Jun 22 04:39:58 PM PDT 24 |
| Finished | Jun 22 04:40:08 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-61ff7b4f-c584-40fb-bd1a-ea1107274cfb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1238271562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1238271562 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1268483867 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1460690000 ps |
| CPU time | 4.5 seconds |
| Started | Jun 22 04:40:05 PM PDT 24 |
| Finished | Jun 22 04:40:16 PM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-37ebe50d-eb02-4b0e-a3bf-2deab3c5fcee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1268483867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1268483867 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3317885515 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1590930000 ps |
| CPU time | 4.75 seconds |
| Started | Jun 22 04:39:59 PM PDT 24 |
| Finished | Jun 22 04:40:12 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-86508a24-8191-4ee5-844e-4a1ef07fc00f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3317885515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3317885515 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2138586482 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1554550000 ps |
| CPU time | 4.91 seconds |
| Started | Jun 22 04:39:52 PM PDT 24 |
| Finished | Jun 22 04:40:04 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-e56781a0-ffef-4bd6-b3cc-29f255d740f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2138586482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2138586482 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3892377041 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1472570000 ps |
| CPU time | 3.32 seconds |
| Started | Jun 22 04:39:33 PM PDT 24 |
| Finished | Jun 22 04:39:44 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-0cfe7e8b-4624-4c13-bcfc-954543e456e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3892377041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3892377041 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.2167248119 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1390050000 ps |
| CPU time | 4.76 seconds |
| Started | Jun 22 04:39:58 PM PDT 24 |
| Finished | Jun 22 04:40:11 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-3b02bce5-4548-4315-85cd-02afbcc3ac8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2167248119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.2167248119 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1239350987 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1433430000 ps |
| CPU time | 4.47 seconds |
| Started | Jun 22 04:39:47 PM PDT 24 |
| Finished | Jun 22 04:39:57 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-8a31f6f6-0881-4385-95aa-730ca5000e75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1239350987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1239350987 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1363746763 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1519930000 ps |
| CPU time | 4.45 seconds |
| Started | Jun 22 04:40:04 PM PDT 24 |
| Finished | Jun 22 04:40:15 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-02bcaee6-894d-4cd8-a71c-4fc367512d8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1363746763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1363746763 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |