Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4097548939
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1623205034
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3391218220
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2711355318

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3351441475
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4148979202
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.938942618
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4056652938
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3809085761
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2518095270
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2970803400
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1727203057
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1179400196
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2765245602
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1344061844
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1274539305
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2531740339
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.447644286
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1102399157
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1365370811
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.114553623
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3049240046
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1855122230
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2431706963
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.579839133
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.975256711
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.995911819
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2485507452
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1982060140
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4015428834
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3505743937
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3706865326
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3682464131
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3703649182
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.551581345
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4070391463
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.689777102
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.20524511
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1371699667
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2517171766
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.866291289
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2437191260
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2069532951
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1721481180
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2764220470
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3828241362
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2298909179
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4157371296
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1892902482
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2665640499
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.592421113
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1222941600
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1722472562
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.581849138
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.498096052
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.576901446
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2589365274
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1181169202
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3002105358
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1412586195
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3682511872
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2932073415
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1219329689
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2819567787
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2704696813
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1930990283
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2858868289
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4267074503
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.86506068
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1234816268
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3605675304
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3281508202
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3792534466
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2823382883
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1052668335
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1489153361
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1922702744
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1586897508
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4142172994
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3782565865
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4020227270
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4046401288
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.409179037
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1256447767
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3951589213
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3637220448
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1553498444
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3553597736
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1446803108
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.456022695
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.396605736
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3066006761
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1086102136
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3289190341
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.530971998
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3291935850
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.351109739
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2713507516
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4038655875
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3070590251
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1863134106
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3766565172
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1336267520
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1493825803
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3398989162
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1093623660
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.273172212
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3313672535
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.218268986
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1432870057
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2474643545
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1504409250
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4131924775
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3227181916
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2850883183
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2953115601
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.497811425
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2351045768
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3563677859
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4248096942
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2573493466
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.637622463
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2006163816
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1087660828
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2797902239
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.632674550
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3315802000
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.831049835
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.834246525
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.512263987
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2783388815
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.844455302
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1828802561
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2735916991
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2116125409
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3352933782
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3724877688
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3582380286
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1481475426
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4223704958
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2742742330
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4196977428
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2065229681
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.67165141
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4043067663
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2373691755
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1240247687
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2981671843
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3531191599
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3162094070
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4092122662
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.47662237
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.231223346
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.288221597
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1771684378
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2229475597
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1390499468
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1014150579
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1591146026
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3408658878
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2674984360
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.239007932
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2307440493
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2309079014
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.407648674
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.933002651
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3644730705
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2880199571
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.658525705
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.951972089
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2671547531
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4133368637
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1407770958
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3791505384
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3309732901
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.649447450
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.66092260
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4288727647
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.180849904
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.824728329
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1394146099
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3891764335
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1726125894
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.837379040
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.899257956
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.903772994
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1842644227
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2409803534
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3557868625
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2109343340
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3288590244
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1690190282
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.133440729
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3803026813
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3881083876
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2509155176
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4014357662
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.315069671
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2934672422
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1470854011



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3803026813 Jun 23 05:52:27 PM PDT 24 Jun 23 05:52:36 PM PDT 24 1368790000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.407648674 Jun 23 05:52:25 PM PDT 24 Jun 23 05:52:36 PM PDT 24 1389570000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2674984360 Jun 23 05:52:21 PM PDT 24 Jun 23 05:52:32 PM PDT 24 1500990000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3791505384 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:43 PM PDT 24 1475670000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.933002651 Jun 23 05:52:21 PM PDT 24 Jun 23 05:52:36 PM PDT 24 1557250000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.899257956 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:36 PM PDT 24 941270000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.649447450 Jun 23 05:52:30 PM PDT 24 Jun 23 05:52:42 PM PDT 24 1604710000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3288590244 Jun 23 05:52:34 PM PDT 24 Jun 23 05:52:46 PM PDT 24 1554650000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4097548939 Jun 23 05:52:26 PM PDT 24 Jun 23 05:52:38 PM PDT 24 1461030000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3891764335 Jun 23 05:52:31 PM PDT 24 Jun 23 05:52:41 PM PDT 24 1291370000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4288727647 Jun 23 05:52:38 PM PDT 24 Jun 23 05:52:47 PM PDT 24 1249650000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1591146026 Jun 23 05:52:25 PM PDT 24 Jun 23 05:52:35 PM PDT 24 1266430000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2307440493 Jun 23 05:52:23 PM PDT 24 Jun 23 05:52:32 PM PDT 24 1320250000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.239007932 Jun 23 05:52:25 PM PDT 24 Jun 23 05:52:37 PM PDT 24 1506350000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3408658878 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:40 PM PDT 24 1471610000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1726125894 Jun 23 05:52:35 PM PDT 24 Jun 23 05:52:42 PM PDT 24 1048250000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1842644227 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1447870000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1394146099 Jun 23 05:52:26 PM PDT 24 Jun 23 05:52:38 PM PDT 24 1615110000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.66092260 Jun 23 05:52:30 PM PDT 24 Jun 23 05:52:41 PM PDT 24 1442110000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2671547531 Jun 23 05:52:34 PM PDT 24 Jun 23 05:52:44 PM PDT 24 1331050000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2109343340 Jun 23 05:52:26 PM PDT 24 Jun 23 05:52:38 PM PDT 24 1422170000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4014357662 Jun 23 05:52:24 PM PDT 24 Jun 23 05:52:34 PM PDT 24 1263150000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.231223346 Jun 23 05:52:19 PM PDT 24 Jun 23 05:52:31 PM PDT 24 1445290000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2880199571 Jun 23 05:52:29 PM PDT 24 Jun 23 05:52:38 PM PDT 24 1489730000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1407770958 Jun 23 05:52:35 PM PDT 24 Jun 23 05:52:45 PM PDT 24 1317770000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.951972089 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:36 PM PDT 24 1194590000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3644730705 Jun 23 05:52:29 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1573390000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1771684378 Jun 23 05:52:21 PM PDT 24 Jun 23 05:52:32 PM PDT 24 1481510000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.824728329 Jun 23 05:52:23 PM PDT 24 Jun 23 05:52:34 PM PDT 24 1511190000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.315069671 Jun 23 05:52:21 PM PDT 24 Jun 23 05:52:30 PM PDT 24 1545530000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2934672422 Jun 23 05:52:26 PM PDT 24 Jun 23 05:52:36 PM PDT 24 1276970000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.903772994 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:40 PM PDT 24 1259790000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2409803534 Jun 23 05:52:30 PM PDT 24 Jun 23 05:52:40 PM PDT 24 1470730000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3557868625 Jun 23 05:52:34 PM PDT 24 Jun 23 05:52:45 PM PDT 24 1489710000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1470854011 Jun 23 05:52:26 PM PDT 24 Jun 23 05:52:38 PM PDT 24 1509870000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2309079014 Jun 23 05:52:28 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1058390000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1014150579 Jun 23 05:52:23 PM PDT 24 Jun 23 05:52:35 PM PDT 24 1663970000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2229475597 Jun 23 05:52:27 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1541390000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.658525705 Jun 23 05:52:27 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1370050000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.288221597 Jun 23 05:52:24 PM PDT 24 Jun 23 05:52:36 PM PDT 24 1567470000 ps
T71 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.837379040 Jun 23 05:52:27 PM PDT 24 Jun 23 05:52:37 PM PDT 24 1397530000 ps
T72 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.180849904 Jun 23 05:52:34 PM PDT 24 Jun 23 05:52:43 PM PDT 24 1352930000 ps
T73 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1390499468 Jun 23 05:52:31 PM PDT 24 Jun 23 05:52:38 PM PDT 24 1315950000 ps
T74 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.133440729 Jun 23 05:52:29 PM PDT 24 Jun 23 05:52:40 PM PDT 24 1401250000 ps
T75 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3309732901 Jun 23 05:52:26 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1471930000 ps
T76 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2509155176 Jun 23 05:52:21 PM PDT 24 Jun 23 05:52:31 PM PDT 24 1341110000 ps
T77 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3881083876 Jun 23 05:52:30 PM PDT 24 Jun 23 05:52:41 PM PDT 24 1344770000 ps
T78 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.47662237 Jun 23 05:52:21 PM PDT 24 Jun 23 05:52:33 PM PDT 24 1454590000 ps
T79 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4133368637 Jun 23 05:52:30 PM PDT 24 Jun 23 05:52:40 PM PDT 24 1507530000 ps
T80 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1690190282 Jun 23 05:52:27 PM PDT 24 Jun 23 05:52:39 PM PDT 24 1299770000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2711355318 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:41 PM PDT 24 1561170000 ps
T5 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3724877688 Jun 23 05:49:41 PM PDT 24 Jun 23 05:49:50 PM PDT 24 1352110000 ps
T6 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1481475426 Jun 23 05:49:40 PM PDT 24 Jun 23 05:49:48 PM PDT 24 1155290000 ps
T24 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4092122662 Jun 23 05:49:40 PM PDT 24 Jun 23 05:49:50 PM PDT 24 1458310000 ps
T25 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4248096942 Jun 23 05:49:35 PM PDT 24 Jun 23 05:49:44 PM PDT 24 1491970000 ps
T26 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.512263987 Jun 23 05:49:38 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1417410000 ps
T27 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.637622463 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:48 PM PDT 24 1573510000 ps
T28 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1504409250 Jun 23 05:49:35 PM PDT 24 Jun 23 05:49:45 PM PDT 24 1303870000 ps
T29 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2474643545 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:41 PM PDT 24 1467730000 ps
T30 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3563677859 Jun 23 05:49:37 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1505410000 ps
T81 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2573493466 Jun 23 05:49:40 PM PDT 24 Jun 23 05:49:50 PM PDT 24 1549150000 ps
T82 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1828802561 Jun 23 05:49:37 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1594850000 ps
T83 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3582380286 Jun 23 05:49:41 PM PDT 24 Jun 23 05:49:52 PM PDT 24 1352870000 ps
T84 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.497811425 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1335530000 ps
T85 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1087660828 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1505310000 ps
T86 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3313672535 Jun 23 05:49:38 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1345670000 ps
T87 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3315802000 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:48 PM PDT 24 1528290000 ps
T88 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2797902239 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1542270000 ps
T89 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2735916991 Jun 23 05:49:40 PM PDT 24 Jun 23 05:49:50 PM PDT 24 1535690000 ps
T90 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3531191599 Jun 23 05:49:37 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1333530000 ps
T91 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3162094070 Jun 23 05:49:35 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1590550000 ps
T92 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2065229681 Jun 23 05:49:39 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1311870000 ps
T93 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2742742330 Jun 23 05:49:39 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1463990000 ps
T94 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4223704958 Jun 23 05:49:39 PM PDT 24 Jun 23 05:49:49 PM PDT 24 1515410000 ps
T95 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1240247687 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:41 PM PDT 24 1478390000 ps
T96 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4196977428 Jun 23 05:49:42 PM PDT 24 Jun 23 05:49:52 PM PDT 24 1480050000 ps
T97 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.67165141 Jun 23 05:49:41 PM PDT 24 Jun 23 05:49:50 PM PDT 24 1459250000 ps
T98 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3352933782 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1471770000 ps
T99 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1093623660 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1476270000 ps
T100 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.632674550 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1386030000 ps
T101 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.273172212 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:48 PM PDT 24 1494610000 ps
T102 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2953115601 Jun 23 05:49:34 PM PDT 24 Jun 23 05:49:44 PM PDT 24 1512910000 ps
T103 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.218268986 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:41 PM PDT 24 1503150000 ps
T104 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2981671843 Jun 23 05:49:35 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1554230000 ps
T105 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1493825803 Jun 23 05:49:33 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1198850000 ps
T106 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2373691755 Jun 23 05:49:41 PM PDT 24 Jun 23 05:49:50 PM PDT 24 1481430000 ps
T107 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.831049835 Jun 23 05:49:34 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1199650000 ps
T108 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3398989162 Jun 23 05:49:38 PM PDT 24 Jun 23 05:49:49 PM PDT 24 1575510000 ps
T109 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2116125409 Jun 23 05:49:39 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1585890000 ps
T110 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2006163816 Jun 23 05:49:31 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1494110000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2351045768 Jun 23 05:49:34 PM PDT 24 Jun 23 05:49:44 PM PDT 24 1580850000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1336267520 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1474870000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2850883183 Jun 23 05:49:35 PM PDT 24 Jun 23 05:49:42 PM PDT 24 1496790000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2783388815 Jun 23 05:49:32 PM PDT 24 Jun 23 05:49:40 PM PDT 24 1464250000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.844455302 Jun 23 05:49:36 PM PDT 24 Jun 23 05:49:47 PM PDT 24 1442970000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1432870057 Jun 23 05:49:34 PM PDT 24 Jun 23 05:49:46 PM PDT 24 1493170000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4131924775 Jun 23 05:49:34 PM PDT 24 Jun 23 05:49:44 PM PDT 24 1442430000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3227181916 Jun 23 05:49:30 PM PDT 24 Jun 23 05:49:38 PM PDT 24 1102430000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.834246525 Jun 23 05:49:33 PM PDT 24 Jun 23 05:49:44 PM PDT 24 1538150000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4043067663 Jun 23 05:49:40 PM PDT 24 Jun 23 05:49:48 PM PDT 24 1454450000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1412586195 Jun 23 05:52:14 PM PDT 24 Jun 23 06:28:10 PM PDT 24 336656050000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1623205034 Jun 23 05:52:09 PM PDT 24 Jun 23 06:31:46 PM PDT 24 336707750000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4142172994 Jun 23 05:52:08 PM PDT 24 Jun 23 06:26:13 PM PDT 24 337104110000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4038655875 Jun 23 05:52:08 PM PDT 24 Jun 23 06:28:44 PM PDT 24 336807030000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1446803108 Jun 23 05:52:11 PM PDT 24 Jun 23 06:20:24 PM PDT 24 336961470000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.86506068 Jun 23 05:52:03 PM PDT 24 Jun 23 06:22:29 PM PDT 24 337031690000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2858868289 Jun 23 05:52:10 PM PDT 24 Jun 23 06:23:10 PM PDT 24 337032350000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1086102136 Jun 23 05:52:18 PM PDT 24 Jun 23 06:30:51 PM PDT 24 336821370000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.351109739 Jun 23 05:52:10 PM PDT 24 Jun 23 06:22:30 PM PDT 24 336714710000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1863134106 Jun 23 05:52:12 PM PDT 24 Jun 23 06:21:19 PM PDT 24 336830410000 ps
T121 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1922702744 Jun 23 05:52:12 PM PDT 24 Jun 23 06:26:16 PM PDT 24 336632310000 ps
T122 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.456022695 Jun 23 05:52:16 PM PDT 24 Jun 23 06:25:01 PM PDT 24 336497630000 ps
T123 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2704696813 Jun 23 05:52:05 PM PDT 24 Jun 23 06:23:42 PM PDT 24 336801070000 ps
T124 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1586897508 Jun 23 05:52:11 PM PDT 24 Jun 23 06:28:30 PM PDT 24 337009010000 ps
T125 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3002105358 Jun 23 05:52:08 PM PDT 24 Jun 23 06:29:26 PM PDT 24 336814830000 ps
T126 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3070590251 Jun 23 05:52:05 PM PDT 24 Jun 23 06:26:29 PM PDT 24 336519470000 ps
T127 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2823382883 Jun 23 05:52:05 PM PDT 24 Jun 23 06:25:35 PM PDT 24 336389310000 ps
T128 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2932073415 Jun 23 05:52:13 PM PDT 24 Jun 23 06:31:23 PM PDT 24 336691310000 ps
T129 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2589365274 Jun 23 05:52:07 PM PDT 24 Jun 23 06:19:28 PM PDT 24 336696490000 ps
T130 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1256447767 Jun 23 05:52:09 PM PDT 24 Jun 23 06:25:26 PM PDT 24 336963370000 ps
T131 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1181169202 Jun 23 05:52:05 PM PDT 24 Jun 23 06:24:03 PM PDT 24 337080310000 ps
T132 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3951589213 Jun 23 05:52:09 PM PDT 24 Jun 23 06:21:38 PM PDT 24 336773050000 ps
T133 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4046401288 Jun 23 05:52:15 PM PDT 24 Jun 23 06:25:38 PM PDT 24 336632730000 ps
T134 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1930990283 Jun 23 05:52:11 PM PDT 24 Jun 23 06:22:31 PM PDT 24 336687750000 ps
T135 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4020227270 Jun 23 05:52:15 PM PDT 24 Jun 23 06:28:39 PM PDT 24 336795430000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2713507516 Jun 23 05:52:04 PM PDT 24 Jun 23 06:29:42 PM PDT 24 336510590000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3637220448 Jun 23 05:52:10 PM PDT 24 Jun 23 06:27:13 PM PDT 24 336944330000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3281508202 Jun 23 05:52:07 PM PDT 24 Jun 23 06:25:51 PM PDT 24 336415310000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1052668335 Jun 23 05:52:07 PM PDT 24 Jun 23 06:28:28 PM PDT 24 336972370000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1553498444 Jun 23 05:52:05 PM PDT 24 Jun 23 06:22:08 PM PDT 24 336397130000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.396605736 Jun 23 05:52:10 PM PDT 24 Jun 23 06:26:41 PM PDT 24 337095210000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.498096052 Jun 23 05:52:13 PM PDT 24 Jun 23 06:23:25 PM PDT 24 336373810000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1489153361 Jun 23 05:52:05 PM PDT 24 Jun 23 06:27:19 PM PDT 24 336686350000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3605675304 Jun 23 05:52:06 PM PDT 24 Jun 23 06:28:35 PM PDT 24 336646450000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4267074503 Jun 23 05:52:06 PM PDT 24 Jun 23 06:22:59 PM PDT 24 336940810000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.409179037 Jun 23 05:52:12 PM PDT 24 Jun 23 06:23:22 PM PDT 24 336552570000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.581849138 Jun 23 05:52:07 PM PDT 24 Jun 23 06:26:28 PM PDT 24 336397610000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3682511872 Jun 23 05:52:06 PM PDT 24 Jun 23 06:21:47 PM PDT 24 336922830000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2819567787 Jun 23 05:52:09 PM PDT 24 Jun 23 06:27:29 PM PDT 24 336573490000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3553597736 Jun 23 05:52:13 PM PDT 24 Jun 23 06:31:50 PM PDT 24 336844850000 ps
T151 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.576901446 Jun 23 05:52:13 PM PDT 24 Jun 23 06:27:54 PM PDT 24 336381190000 ps
T152 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.530971998 Jun 23 05:52:10 PM PDT 24 Jun 23 06:23:23 PM PDT 24 336524770000 ps
T153 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1234816268 Jun 23 05:52:08 PM PDT 24 Jun 23 06:28:45 PM PDT 24 336389290000 ps
T154 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3766565172 Jun 23 05:52:05 PM PDT 24 Jun 23 06:24:11 PM PDT 24 336442070000 ps
T155 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1219329689 Jun 23 05:52:08 PM PDT 24 Jun 23 06:32:19 PM PDT 24 336955750000 ps
T156 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3291935850 Jun 23 05:52:12 PM PDT 24 Jun 23 06:25:30 PM PDT 24 336825670000 ps
T157 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3289190341 Jun 23 05:52:11 PM PDT 24 Jun 23 06:19:54 PM PDT 24 336675570000 ps
T158 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3066006761 Jun 23 05:52:09 PM PDT 24 Jun 23 06:22:09 PM PDT 24 336647210000 ps
T159 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3792534466 Jun 23 05:52:11 PM PDT 24 Jun 23 06:25:40 PM PDT 24 336920210000 ps
T160 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3782565865 Jun 23 05:52:14 PM PDT 24 Jun 23 06:25:41 PM PDT 24 336531930000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2517171766 Jun 23 05:52:26 PM PDT 24 Jun 23 06:28:26 PM PDT 24 336935430000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2518095270 Jun 23 05:52:16 PM PDT 24 Jun 23 06:23:21 PM PDT 24 336410870000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2764220470 Jun 23 05:52:21 PM PDT 24 Jun 23 06:30:34 PM PDT 24 336615870000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3391218220 Jun 23 05:52:09 PM PDT 24 Jun 23 06:26:55 PM PDT 24 337059710000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1365370811 Jun 23 05:52:19 PM PDT 24 Jun 23 06:31:59 PM PDT 24 336430870000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1179400196 Jun 23 05:52:16 PM PDT 24 Jun 23 06:24:25 PM PDT 24 336437850000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1727203057 Jun 23 05:52:17 PM PDT 24 Jun 23 06:25:42 PM PDT 24 336793390000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1892902482 Jun 23 05:52:13 PM PDT 24 Jun 23 06:30:24 PM PDT 24 336566290000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.689777102 Jun 23 05:52:20 PM PDT 24 Jun 23 06:31:37 PM PDT 24 336806090000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.20524511 Jun 23 05:52:13 PM PDT 24 Jun 23 06:24:05 PM PDT 24 336855190000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1722472562 Jun 23 05:52:14 PM PDT 24 Jun 23 06:30:36 PM PDT 24 336670070000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.551581345 Jun 23 05:52:16 PM PDT 24 Jun 23 06:27:34 PM PDT 24 336491530000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3505743937 Jun 23 05:52:21 PM PDT 24 Jun 23 06:32:01 PM PDT 24 336654170000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2765245602 Jun 23 05:52:16 PM PDT 24 Jun 23 06:24:31 PM PDT 24 336503770000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3049240046 Jun 23 05:52:15 PM PDT 24 Jun 23 06:22:30 PM PDT 24 336833470000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1102399157 Jun 23 05:52:17 PM PDT 24 Jun 23 06:30:35 PM PDT 24 336851770000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3703649182 Jun 23 05:52:17 PM PDT 24 Jun 23 06:27:40 PM PDT 24 337004950000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.592421113 Jun 23 05:52:18 PM PDT 24 Jun 23 06:29:04 PM PDT 24 336601590000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3706865326 Jun 23 05:52:18 PM PDT 24 Jun 23 06:32:30 PM PDT 24 336874790000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4148979202 Jun 23 05:52:11 PM PDT 24 Jun 23 06:22:27 PM PDT 24 336766770000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1274539305 Jun 23 05:52:15 PM PDT 24 Jun 23 06:22:49 PM PDT 24 336362150000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3682464131 Jun 23 05:52:17 PM PDT 24 Jun 23 06:30:34 PM PDT 24 336914810000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1855122230 Jun 23 05:52:17 PM PDT 24 Jun 23 06:29:10 PM PDT 24 336467050000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3809085761 Jun 23 05:52:22 PM PDT 24 Jun 23 06:25:45 PM PDT 24 337090550000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2069532951 Jun 23 05:52:27 PM PDT 24 Jun 23 06:27:12 PM PDT 24 336349670000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.975256711 Jun 23 05:52:15 PM PDT 24 Jun 23 06:23:01 PM PDT 24 336961870000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3351441475 Jun 23 05:52:14 PM PDT 24 Jun 23 06:30:28 PM PDT 24 336858830000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4056652938 Jun 23 05:52:17 PM PDT 24 Jun 23 06:25:42 PM PDT 24 336421890000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2437191260 Jun 23 05:52:24 PM PDT 24 Jun 23 06:25:47 PM PDT 24 336451030000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.866291289 Jun 23 05:52:28 PM PDT 24 Jun 23 06:27:18 PM PDT 24 337102410000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.447644286 Jun 23 05:52:16 PM PDT 24 Jun 23 06:28:46 PM PDT 24 336432510000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.114553623 Jun 23 05:52:18 PM PDT 24 Jun 23 06:29:14 PM PDT 24 336674630000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1344061844 Jun 23 05:52:20 PM PDT 24 Jun 23 06:25:56 PM PDT 24 336541870000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2298909179 Jun 23 05:52:23 PM PDT 24 Jun 23 06:25:53 PM PDT 24 336499110000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4015428834 Jun 23 05:52:17 PM PDT 24 Jun 23 06:24:42 PM PDT 24 336478450000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4157371296 Jun 23 05:52:23 PM PDT 24 Jun 23 06:32:16 PM PDT 24 336641090000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1721481180 Jun 23 05:52:22 PM PDT 24 Jun 23 06:30:26 PM PDT 24 336598310000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3828241362 Jun 23 05:52:20 PM PDT 24 Jun 23 06:26:48 PM PDT 24 336586630000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2431706963 Jun 23 05:52:24 PM PDT 24 Jun 23 06:30:17 PM PDT 24 336596590000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.579839133 Jun 23 05:52:19 PM PDT 24 Jun 23 06:26:45 PM PDT 24 336822230000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2970803400 Jun 23 05:52:20 PM PDT 24 Jun 23 06:27:07 PM PDT 24 337083470000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1222941600 Jun 23 05:52:11 PM PDT 24 Jun 23 06:21:10 PM PDT 24 336762230000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2531740339 Jun 23 05:52:14 PM PDT 24 Jun 23 06:25:40 PM PDT 24 337026170000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.995911819 Jun 23 05:52:11 PM PDT 24 Jun 23 06:25:33 PM PDT 24 336536910000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1371699667 Jun 23 05:52:25 PM PDT 24 Jun 23 06:25:24 PM PDT 24 336418070000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.938942618 Jun 23 05:52:10 PM PDT 24 Jun 23 06:28:19 PM PDT 24 336546010000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2665640499 Jun 23 05:52:11 PM PDT 24 Jun 23 06:28:29 PM PDT 24 336991590000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1982060140 Jun 23 05:52:19 PM PDT 24 Jun 23 06:30:25 PM PDT 24 336919610000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4070391463 Jun 23 05:52:17 PM PDT 24 Jun 23 06:30:47 PM PDT 24 337017650000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2485507452 Jun 23 05:52:19 PM PDT 24 Jun 23 06:24:52 PM PDT 24 336738450000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4097548939
Short name T12
Test name
Test status
Simulation time 1461030000 ps
CPU time 5.37 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 05:52:38 PM PDT 24
Peak memory 164976 kb
Host smart-2404dd77-83e1-43ff-a107-c2b5398bd7c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4097548939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4097548939
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1623205034
Short name T15
Test name
Test status
Simulation time 336707750000 ps
CPU time 940.23 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 06:31:46 PM PDT 24
Peak memory 160884 kb
Host smart-4c12632a-014a-4ea2-b175-21d575bc13ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1623205034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1623205034
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3391218220
Short name T34
Test name
Test status
Simulation time 337059710000 ps
CPU time 843.88 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 06:26:55 PM PDT 24
Peak memory 160780 kb
Host smart-2f9762b3-370b-4086-8450-8e018bdf5a33
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3391218220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3391218220
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2711355318
Short name T4
Test name
Test status
Simulation time 1561170000 ps
CPU time 5.02 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:41 PM PDT 24
Peak memory 164940 kb
Host smart-18b81985-4ab0-4340-8b6e-e9a2152ed2ad
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2711355318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2711355318
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3351441475
Short name T177
Test name
Test status
Simulation time 336858830000 ps
CPU time 907.11 seconds
Started Jun 23 05:52:14 PM PDT 24
Finished Jun 23 06:30:28 PM PDT 24
Peak memory 160832 kb
Host smart-50564887-eb82-4162-af94-2220f961994e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3351441475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3351441475
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.4148979202
Short name T170
Test name
Test status
Simulation time 336766770000 ps
CPU time 740.88 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:22:27 PM PDT 24
Peak memory 160816 kb
Host smart-ed2c3586-e68c-49e8-a825-ea171b95b970
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4148979202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.4148979202
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.938942618
Short name T196
Test name
Test status
Simulation time 336546010000 ps
CPU time 889.39 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 06:28:19 PM PDT 24
Peak memory 160800 kb
Host smart-eb16df18-a259-4c4d-88a8-70a49c5f738e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=938942618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.938942618
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4056652938
Short name T178
Test name
Test status
Simulation time 336421890000 ps
CPU time 805.79 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:25:42 PM PDT 24
Peak memory 160824 kb
Host smart-4e56b581-bb02-4c3a-8997-db3a43c0f2e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4056652938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4056652938
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3809085761
Short name T174
Test name
Test status
Simulation time 337090550000 ps
CPU time 816.23 seconds
Started Jun 23 05:52:22 PM PDT 24
Finished Jun 23 06:25:45 PM PDT 24
Peak memory 160828 kb
Host smart-94d816c0-6483-4449-bc76-fffd6318a932
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3809085761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3809085761
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2518095270
Short name T32
Test name
Test status
Simulation time 336410870000 ps
CPU time 758.95 seconds
Started Jun 23 05:52:16 PM PDT 24
Finished Jun 23 06:23:21 PM PDT 24
Peak memory 160824 kb
Host smart-989d94bb-6309-4cbc-a00e-f3440ad14c30
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2518095270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2518095270
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2970803400
Short name T191
Test name
Test status
Simulation time 337083470000 ps
CPU time 848.91 seconds
Started Jun 23 05:52:20 PM PDT 24
Finished Jun 23 06:27:07 PM PDT 24
Peak memory 160820 kb
Host smart-8bb67e11-3ee2-41b0-9116-e943ce813505
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2970803400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2970803400
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1727203057
Short name T37
Test name
Test status
Simulation time 336793390000 ps
CPU time 822.05 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:25:42 PM PDT 24
Peak memory 160824 kb
Host smart-7282d7f6-7185-4f0c-9381-eeeb3e88ba93
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1727203057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1727203057
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1179400196
Short name T36
Test name
Test status
Simulation time 336437850000 ps
CPU time 801.84 seconds
Started Jun 23 05:52:16 PM PDT 24
Finished Jun 23 06:24:25 PM PDT 24
Peak memory 160820 kb
Host smart-d7ba6b23-0cf7-47d9-837f-89e1ac28fd7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1179400196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1179400196
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2765245602
Short name T164
Test name
Test status
Simulation time 336503770000 ps
CPU time 782.34 seconds
Started Jun 23 05:52:16 PM PDT 24
Finished Jun 23 06:24:31 PM PDT 24
Peak memory 160832 kb
Host smart-b1c2e71f-64be-4073-b813-7baa3a8b3d7c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2765245602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2765245602
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1344061844
Short name T183
Test name
Test status
Simulation time 336541870000 ps
CPU time 811.06 seconds
Started Jun 23 05:52:20 PM PDT 24
Finished Jun 23 06:25:56 PM PDT 24
Peak memory 160828 kb
Host smart-ddc49334-846b-4340-bde4-67a4d6491924
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1344061844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1344061844
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1274539305
Short name T171
Test name
Test status
Simulation time 336362150000 ps
CPU time 748.46 seconds
Started Jun 23 05:52:15 PM PDT 24
Finished Jun 23 06:22:49 PM PDT 24
Peak memory 160736 kb
Host smart-651449f7-6cd4-4046-80bb-0a6fea8b2869
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1274539305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1274539305
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2531740339
Short name T193
Test name
Test status
Simulation time 337026170000 ps
CPU time 818.56 seconds
Started Jun 23 05:52:14 PM PDT 24
Finished Jun 23 06:25:40 PM PDT 24
Peak memory 160836 kb
Host smart-cbcec368-d132-4504-a587-9fc1e21934e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2531740339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2531740339
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.447644286
Short name T181
Test name
Test status
Simulation time 336432510000 ps
CPU time 870.98 seconds
Started Jun 23 05:52:16 PM PDT 24
Finished Jun 23 06:28:46 PM PDT 24
Peak memory 160816 kb
Host smart-30fd84b5-4162-4d23-aed9-e11314d50981
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=447644286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.447644286
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1102399157
Short name T166
Test name
Test status
Simulation time 336851770000 ps
CPU time 917.17 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:30:35 PM PDT 24
Peak memory 160808 kb
Host smart-3e0da591-3ae5-49a7-9104-ec9032f447ba
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1102399157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1102399157
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1365370811
Short name T35
Test name
Test status
Simulation time 336430870000 ps
CPU time 926.06 seconds
Started Jun 23 05:52:19 PM PDT 24
Finished Jun 23 06:31:59 PM PDT 24
Peak memory 160892 kb
Host smart-2f14315c-dbf7-4510-9c42-4a6128776158
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1365370811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1365370811
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.114553623
Short name T182
Test name
Test status
Simulation time 336674630000 ps
CPU time 884.16 seconds
Started Jun 23 05:52:18 PM PDT 24
Finished Jun 23 06:29:14 PM PDT 24
Peak memory 160820 kb
Host smart-946bbeaf-4ddc-421f-af82-9bd691c67b7f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=114553623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.114553623
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3049240046
Short name T165
Test name
Test status
Simulation time 336833470000 ps
CPU time 745.19 seconds
Started Jun 23 05:52:15 PM PDT 24
Finished Jun 23 06:22:30 PM PDT 24
Peak memory 160828 kb
Host smart-e08a00fb-0610-45cd-a1e1-8dd04f13f9f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3049240046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3049240046
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1855122230
Short name T173
Test name
Test status
Simulation time 336467050000 ps
CPU time 882.75 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:29:10 PM PDT 24
Peak memory 160828 kb
Host smart-996b23ce-5347-42f6-8f9a-685c3b2758ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1855122230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1855122230
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2431706963
Short name T189
Test name
Test status
Simulation time 336596590000 ps
CPU time 893.15 seconds
Started Jun 23 05:52:24 PM PDT 24
Finished Jun 23 06:30:17 PM PDT 24
Peak memory 160840 kb
Host smart-b7773ac7-2413-452f-87df-4d1e7d43a377
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2431706963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2431706963
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.579839133
Short name T190
Test name
Test status
Simulation time 336822230000 ps
CPU time 840.75 seconds
Started Jun 23 05:52:19 PM PDT 24
Finished Jun 23 06:26:45 PM PDT 24
Peak memory 160812 kb
Host smart-334069c1-873b-4c55-8d52-59bc40d9c511
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=579839133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.579839133
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.975256711
Short name T176
Test name
Test status
Simulation time 336961870000 ps
CPU time 752.83 seconds
Started Jun 23 05:52:15 PM PDT 24
Finished Jun 23 06:23:01 PM PDT 24
Peak memory 160748 kb
Host smart-ff315583-5a79-402e-b017-f8d646d5918c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=975256711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.975256711
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.995911819
Short name T194
Test name
Test status
Simulation time 336536910000 ps
CPU time 821.44 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:25:33 PM PDT 24
Peak memory 160808 kb
Host smart-318dd8f3-1498-4370-8fb5-dff5d21f3916
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=995911819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.995911819
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2485507452
Short name T200
Test name
Test status
Simulation time 336738450000 ps
CPU time 798.28 seconds
Started Jun 23 05:52:19 PM PDT 24
Finished Jun 23 06:24:52 PM PDT 24
Peak memory 160824 kb
Host smart-c89b3d93-0110-42b2-94dd-3a1ba48d0722
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2485507452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2485507452
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1982060140
Short name T198
Test name
Test status
Simulation time 336919610000 ps
CPU time 904.97 seconds
Started Jun 23 05:52:19 PM PDT 24
Finished Jun 23 06:30:25 PM PDT 24
Peak memory 160808 kb
Host smart-1577e747-867b-4cbd-8363-8b5d1e115254
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1982060140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1982060140
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.4015428834
Short name T185
Test name
Test status
Simulation time 336478450000 ps
CPU time 776.89 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:24:42 PM PDT 24
Peak memory 160832 kb
Host smart-8457e794-0c1e-44da-96e7-25ba19b03dd3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4015428834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.4015428834
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3505743937
Short name T163
Test name
Test status
Simulation time 336654170000 ps
CPU time 932.91 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 06:32:01 PM PDT 24
Peak memory 160892 kb
Host smart-edca07fa-2d21-42b4-b8a9-a618f6884738
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3505743937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3505743937
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3706865326
Short name T169
Test name
Test status
Simulation time 336874790000 ps
CPU time 970.63 seconds
Started Jun 23 05:52:18 PM PDT 24
Finished Jun 23 06:32:30 PM PDT 24
Peak memory 160824 kb
Host smart-c3e59aa5-5e06-4c32-97ff-52a32731abab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706865326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3706865326
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3682464131
Short name T172
Test name
Test status
Simulation time 336914810000 ps
CPU time 914.52 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:30:34 PM PDT 24
Peak memory 160840 kb
Host smart-8745a805-7078-4864-8581-f862deda5827
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3682464131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3682464131
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3703649182
Short name T167
Test name
Test status
Simulation time 337004950000 ps
CPU time 867.51 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:27:40 PM PDT 24
Peak memory 160816 kb
Host smart-60ee6181-eb91-41a6-b313-a1fdfb6d34e0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3703649182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3703649182
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.551581345
Short name T162
Test name
Test status
Simulation time 336491530000 ps
CPU time 883.74 seconds
Started Jun 23 05:52:16 PM PDT 24
Finished Jun 23 06:27:34 PM PDT 24
Peak memory 160816 kb
Host smart-314fc5ff-44ed-4b2b-bf8d-88511bb7a595
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=551581345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.551581345
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.4070391463
Short name T199
Test name
Test status
Simulation time 337017650000 ps
CPU time 911.99 seconds
Started Jun 23 05:52:17 PM PDT 24
Finished Jun 23 06:30:47 PM PDT 24
Peak memory 160840 kb
Host smart-61df62dc-cfdb-4e23-94a7-d15cf6d3d05b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4070391463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.4070391463
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.689777102
Short name T39
Test name
Test status
Simulation time 336806090000 ps
CPU time 951.66 seconds
Started Jun 23 05:52:20 PM PDT 24
Finished Jun 23 06:31:37 PM PDT 24
Peak memory 160884 kb
Host smart-92d6c471-6b0f-4020-87eb-cf979b05c9ad
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=689777102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.689777102
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.20524511
Short name T40
Test name
Test status
Simulation time 336855190000 ps
CPU time 775.19 seconds
Started Jun 23 05:52:13 PM PDT 24
Finished Jun 23 06:24:05 PM PDT 24
Peak memory 160812 kb
Host smart-56b87df3-12f8-4bdc-9a51-ec8eb2c656ea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=20524511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.20524511
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1371699667
Short name T195
Test name
Test status
Simulation time 336418070000 ps
CPU time 813.44 seconds
Started Jun 23 05:52:25 PM PDT 24
Finished Jun 23 06:25:24 PM PDT 24
Peak memory 160840 kb
Host smart-3438d0de-9822-4b34-9bb3-d6d03b39d8f8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1371699667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1371699667
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2517171766
Short name T31
Test name
Test status
Simulation time 336935430000 ps
CPU time 883.97 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 06:28:26 PM PDT 24
Peak memory 160828 kb
Host smart-46629363-bb11-478a-8c83-7bd3fff3ca25
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2517171766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2517171766
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.866291289
Short name T180
Test name
Test status
Simulation time 337102410000 ps
CPU time 857.38 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 06:27:18 PM PDT 24
Peak memory 160820 kb
Host smart-a3a39842-d458-4262-8873-aab00a06bf96
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=866291289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.866291289
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2437191260
Short name T179
Test name
Test status
Simulation time 336451030000 ps
CPU time 812.88 seconds
Started Jun 23 05:52:24 PM PDT 24
Finished Jun 23 06:25:47 PM PDT 24
Peak memory 160824 kb
Host smart-a783e2a5-f82c-4bb7-b40c-0e3b4f5938d7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2437191260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2437191260
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2069532951
Short name T175
Test name
Test status
Simulation time 336349670000 ps
CPU time 845.66 seconds
Started Jun 23 05:52:27 PM PDT 24
Finished Jun 23 06:27:12 PM PDT 24
Peak memory 160828 kb
Host smart-fe543ed9-5744-4431-8e50-232c146e79f0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2069532951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2069532951
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1721481180
Short name T187
Test name
Test status
Simulation time 336598310000 ps
CPU time 908.85 seconds
Started Jun 23 05:52:22 PM PDT 24
Finished Jun 23 06:30:26 PM PDT 24
Peak memory 160808 kb
Host smart-d538f754-c1b2-41cf-890f-0fef18c323d1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1721481180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1721481180
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2764220470
Short name T33
Test name
Test status
Simulation time 336615870000 ps
CPU time 908.88 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 06:30:34 PM PDT 24
Peak memory 160828 kb
Host smart-1157842c-052c-4a57-8223-913798d67ecd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2764220470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2764220470
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3828241362
Short name T188
Test name
Test status
Simulation time 336586630000 ps
CPU time 858.99 seconds
Started Jun 23 05:52:20 PM PDT 24
Finished Jun 23 06:26:48 PM PDT 24
Peak memory 160824 kb
Host smart-6e0dfa89-86dc-49d1-81ab-2c8360ec1d23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3828241362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3828241362
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2298909179
Short name T184
Test name
Test status
Simulation time 336499110000 ps
CPU time 816.65 seconds
Started Jun 23 05:52:23 PM PDT 24
Finished Jun 23 06:25:53 PM PDT 24
Peak memory 160828 kb
Host smart-39e748c5-20ff-43f1-b496-81cd12e1d0b5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2298909179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2298909179
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4157371296
Short name T186
Test name
Test status
Simulation time 336641090000 ps
CPU time 969.35 seconds
Started Jun 23 05:52:23 PM PDT 24
Finished Jun 23 06:32:16 PM PDT 24
Peak memory 160824 kb
Host smart-acdffdc0-25c5-486d-8e4a-ce6431dccc7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4157371296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4157371296
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1892902482
Short name T38
Test name
Test status
Simulation time 336566290000 ps
CPU time 910.46 seconds
Started Jun 23 05:52:13 PM PDT 24
Finished Jun 23 06:30:24 PM PDT 24
Peak memory 160820 kb
Host smart-cfddfe36-cdbb-40d8-999a-c9c420bbb8a3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1892902482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1892902482
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2665640499
Short name T197
Test name
Test status
Simulation time 336991590000 ps
CPU time 868.18 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:28:29 PM PDT 24
Peak memory 160816 kb
Host smart-52920715-6d4c-4a2e-9157-b49111cdc443
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2665640499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2665640499
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.592421113
Short name T168
Test name
Test status
Simulation time 336601590000 ps
CPU time 877.67 seconds
Started Jun 23 05:52:18 PM PDT 24
Finished Jun 23 06:29:04 PM PDT 24
Peak memory 160808 kb
Host smart-e6bd8403-01dd-4e1f-918a-cdcb1de1cd01
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=592421113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.592421113
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1222941600
Short name T192
Test name
Test status
Simulation time 336762230000 ps
CPU time 702.06 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:21:10 PM PDT 24
Peak memory 160820 kb
Host smart-25409137-4779-4f4c-a1f4-09c29f14c51a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1222941600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1222941600
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1722472562
Short name T161
Test name
Test status
Simulation time 336670070000 ps
CPU time 911.19 seconds
Started Jun 23 05:52:14 PM PDT 24
Finished Jun 23 06:30:36 PM PDT 24
Peak memory 160832 kb
Host smart-1ad77c3f-f922-4c27-9f65-30bc5d23de39
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1722472562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1722472562
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.581849138
Short name T147
Test name
Test status
Simulation time 336397610000 ps
CPU time 824.21 seconds
Started Jun 23 05:52:07 PM PDT 24
Finished Jun 23 06:26:28 PM PDT 24
Peak memory 160812 kb
Host smart-ad5c9841-6584-4b1a-b914-48ed9360e924
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=581849138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.581849138
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.498096052
Short name T142
Test name
Test status
Simulation time 336373810000 ps
CPU time 759.89 seconds
Started Jun 23 05:52:13 PM PDT 24
Finished Jun 23 06:23:25 PM PDT 24
Peak memory 160824 kb
Host smart-fea12768-d022-4309-94cc-dc5f6b82d8c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=498096052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.498096052
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.576901446
Short name T151
Test name
Test status
Simulation time 336381190000 ps
CPU time 874.99 seconds
Started Jun 23 05:52:13 PM PDT 24
Finished Jun 23 06:27:54 PM PDT 24
Peak memory 160824 kb
Host smart-73425c6c-5627-4061-8a09-07cc1f3c5b13
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=576901446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.576901446
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2589365274
Short name T129
Test name
Test status
Simulation time 336696490000 ps
CPU time 675.13 seconds
Started Jun 23 05:52:07 PM PDT 24
Finished Jun 23 06:19:28 PM PDT 24
Peak memory 160764 kb
Host smart-c74038a6-99a5-4658-9200-b5c4bf85b49e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2589365274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2589365274
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1181169202
Short name T131
Test name
Test status
Simulation time 337080310000 ps
CPU time 781.53 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:24:03 PM PDT 24
Peak memory 160804 kb
Host smart-13e7d1c6-ec90-4b69-850f-2fc5114135f2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1181169202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1181169202
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3002105358
Short name T125
Test name
Test status
Simulation time 336814830000 ps
CPU time 879.53 seconds
Started Jun 23 05:52:08 PM PDT 24
Finished Jun 23 06:29:26 PM PDT 24
Peak memory 160844 kb
Host smart-09146cb6-cb8b-45ef-bcd2-ff93fca5feda
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3002105358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3002105358
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1412586195
Short name T14
Test name
Test status
Simulation time 336656050000 ps
CPU time 883.8 seconds
Started Jun 23 05:52:14 PM PDT 24
Finished Jun 23 06:28:10 PM PDT 24
Peak memory 160832 kb
Host smart-0fc7523a-e3d0-410d-a865-aa14706847ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1412586195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1412586195
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3682511872
Short name T148
Test name
Test status
Simulation time 336922830000 ps
CPU time 722.28 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 06:21:47 PM PDT 24
Peak memory 160824 kb
Host smart-f14dbb1d-1429-4718-b11a-9d9c1cd40375
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3682511872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3682511872
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2932073415
Short name T128
Test name
Test status
Simulation time 336691310000 ps
CPU time 926.16 seconds
Started Jun 23 05:52:13 PM PDT 24
Finished Jun 23 06:31:23 PM PDT 24
Peak memory 160844 kb
Host smart-42459a6d-2739-4d79-b263-cfe46a3c261f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2932073415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2932073415
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1219329689
Short name T155
Test name
Test status
Simulation time 336955750000 ps
CPU time 976.42 seconds
Started Jun 23 05:52:08 PM PDT 24
Finished Jun 23 06:32:19 PM PDT 24
Peak memory 160828 kb
Host smart-c0d33951-39bb-4f8a-ada9-39c17b0db37f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219329689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1219329689
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2819567787
Short name T149
Test name
Test status
Simulation time 336573490000 ps
CPU time 871.64 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 06:27:29 PM PDT 24
Peak memory 160868 kb
Host smart-131b42a1-ebf0-44a2-ba41-a68dab62eace
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2819567787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2819567787
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2704696813
Short name T123
Test name
Test status
Simulation time 336801070000 ps
CPU time 781.81 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:23:42 PM PDT 24
Peak memory 160828 kb
Host smart-2398ea9d-81a8-4e9d-9902-4060de55e797
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2704696813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2704696813
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1930990283
Short name T134
Test name
Test status
Simulation time 336687750000 ps
CPU time 731.91 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:22:31 PM PDT 24
Peak memory 160836 kb
Host smart-6950c66c-8c2e-4454-8a8a-7cdb529b2f92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1930990283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1930990283
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2858868289
Short name T20
Test name
Test status
Simulation time 337032350000 ps
CPU time 757.28 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 06:23:10 PM PDT 24
Peak memory 160836 kb
Host smart-c5746747-6e8c-4e5f-b957-471cb4bb5373
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2858868289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2858868289
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4267074503
Short name T145
Test name
Test status
Simulation time 336940810000 ps
CPU time 757.91 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 06:22:59 PM PDT 24
Peak memory 160760 kb
Host smart-b191ca74-f05c-49c1-acfc-7547cf5446b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4267074503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4267074503
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.86506068
Short name T19
Test name
Test status
Simulation time 337031690000 ps
CPU time 742 seconds
Started Jun 23 05:52:03 PM PDT 24
Finished Jun 23 06:22:29 PM PDT 24
Peak memory 160816 kb
Host smart-3445e169-9f1d-4894-b189-45043342810d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=86506068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.86506068
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.1234816268
Short name T153
Test name
Test status
Simulation time 336389290000 ps
CPU time 881.54 seconds
Started Jun 23 05:52:08 PM PDT 24
Finished Jun 23 06:28:45 PM PDT 24
Peak memory 160832 kb
Host smart-becc455b-0d89-4275-a381-27bc1726f49d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1234816268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.1234816268
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3605675304
Short name T144
Test name
Test status
Simulation time 336646450000 ps
CPU time 900.51 seconds
Started Jun 23 05:52:06 PM PDT 24
Finished Jun 23 06:28:35 PM PDT 24
Peak memory 160812 kb
Host smart-bb1e3844-125f-4fb0-a4d7-de12fc29059e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3605675304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3605675304
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3281508202
Short name T138
Test name
Test status
Simulation time 336415310000 ps
CPU time 827.54 seconds
Started Jun 23 05:52:07 PM PDT 24
Finished Jun 23 06:25:51 PM PDT 24
Peak memory 160800 kb
Host smart-b649dd26-35b8-4796-b44e-bbed4c329594
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3281508202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3281508202
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3792534466
Short name T159
Test name
Test status
Simulation time 336920210000 ps
CPU time 808.74 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:25:40 PM PDT 24
Peak memory 160828 kb
Host smart-c37168b8-288e-4286-bca9-0f4499cd158d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3792534466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3792534466
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2823382883
Short name T127
Test name
Test status
Simulation time 336389310000 ps
CPU time 817.7 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:25:35 PM PDT 24
Peak memory 160828 kb
Host smart-a62582b2-0bd2-4f8e-9880-cef171e3fca5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2823382883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2823382883
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.1052668335
Short name T139
Test name
Test status
Simulation time 336972370000 ps
CPU time 869.57 seconds
Started Jun 23 05:52:07 PM PDT 24
Finished Jun 23 06:28:28 PM PDT 24
Peak memory 160812 kb
Host smart-f61deffb-acba-45a2-9634-91f6491601c0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1052668335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.1052668335
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1489153361
Short name T143
Test name
Test status
Simulation time 336686350000 ps
CPU time 846.21 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:27:19 PM PDT 24
Peak memory 160776 kb
Host smart-d69d39d2-bb58-4445-8af1-9bba0a00b569
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1489153361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1489153361
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1922702744
Short name T121
Test name
Test status
Simulation time 336632310000 ps
CPU time 840.12 seconds
Started Jun 23 05:52:12 PM PDT 24
Finished Jun 23 06:26:16 PM PDT 24
Peak memory 160824 kb
Host smart-01c51df0-6cfd-41d9-9ac4-e454b42edcb3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1922702744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1922702744
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1586897508
Short name T124
Test name
Test status
Simulation time 337009010000 ps
CPU time 878.37 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:28:30 PM PDT 24
Peak memory 160832 kb
Host smart-fc63ad38-4d40-4ba2-bbfc-005c5eb92aff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1586897508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1586897508
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.4142172994
Short name T16
Test name
Test status
Simulation time 337104110000 ps
CPU time 840.98 seconds
Started Jun 23 05:52:08 PM PDT 24
Finished Jun 23 06:26:13 PM PDT 24
Peak memory 160828 kb
Host smart-1b2f3bce-30d8-4bb3-86a0-2b18ab63d196
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4142172994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.4142172994
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3782565865
Short name T160
Test name
Test status
Simulation time 336531930000 ps
CPU time 816.71 seconds
Started Jun 23 05:52:14 PM PDT 24
Finished Jun 23 06:25:41 PM PDT 24
Peak memory 160844 kb
Host smart-db4ed984-6a6e-4d6f-b32a-f28604b2e0d6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3782565865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3782565865
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.4020227270
Short name T135
Test name
Test status
Simulation time 336795430000 ps
CPU time 882.39 seconds
Started Jun 23 05:52:15 PM PDT 24
Finished Jun 23 06:28:39 PM PDT 24
Peak memory 160864 kb
Host smart-7dcdf676-6e62-46c3-8096-0ab04cf434ee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4020227270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.4020227270
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4046401288
Short name T133
Test name
Test status
Simulation time 336632730000 ps
CPU time 812.6 seconds
Started Jun 23 05:52:15 PM PDT 24
Finished Jun 23 06:25:38 PM PDT 24
Peak memory 160840 kb
Host smart-ccf210a8-da02-44ca-828c-21ee34522931
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4046401288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.4046401288
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.409179037
Short name T146
Test name
Test status
Simulation time 336552570000 ps
CPU time 762.02 seconds
Started Jun 23 05:52:12 PM PDT 24
Finished Jun 23 06:23:22 PM PDT 24
Peak memory 160820 kb
Host smart-a68926c8-ce76-4f97-a58b-76df34c85d47
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=409179037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.409179037
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1256447767
Short name T130
Test name
Test status
Simulation time 336963370000 ps
CPU time 819.76 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 06:25:26 PM PDT 24
Peak memory 160832 kb
Host smart-5eb1cfbb-a32d-4273-93ea-faab9ee51bef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1256447767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1256447767
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3951589213
Short name T132
Test name
Test status
Simulation time 336773050000 ps
CPU time 727.56 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 06:21:38 PM PDT 24
Peak memory 160756 kb
Host smart-6dfb3059-0ade-4bd5-b636-01aead666c09
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3951589213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3951589213
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.3637220448
Short name T137
Test name
Test status
Simulation time 336944330000 ps
CPU time 867.19 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 06:27:13 PM PDT 24
Peak memory 160820 kb
Host smart-ff3b6bc6-f8c9-4214-af7f-98c9e201ad96
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3637220448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.3637220448
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1553498444
Short name T140
Test name
Test status
Simulation time 336397130000 ps
CPU time 731.39 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:22:08 PM PDT 24
Peak memory 160824 kb
Host smart-70fdf627-3a97-41b2-8ca7-5c64290151ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1553498444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1553498444
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3553597736
Short name T150
Test name
Test status
Simulation time 336844850000 ps
CPU time 961.92 seconds
Started Jun 23 05:52:13 PM PDT 24
Finished Jun 23 06:31:50 PM PDT 24
Peak memory 160896 kb
Host smart-6d4e927b-9a69-4567-95b2-f410f521c103
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3553597736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3553597736
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1446803108
Short name T18
Test name
Test status
Simulation time 336961470000 ps
CPU time 686.32 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:20:24 PM PDT 24
Peak memory 160824 kb
Host smart-08071e50-b337-47a5-ac9e-4d0376133536
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1446803108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1446803108
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.456022695
Short name T122
Test name
Test status
Simulation time 336497630000 ps
CPU time 791.53 seconds
Started Jun 23 05:52:16 PM PDT 24
Finished Jun 23 06:25:01 PM PDT 24
Peak memory 160820 kb
Host smart-f8496473-b7ff-4c6e-826a-af955689d517
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=456022695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.456022695
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.396605736
Short name T141
Test name
Test status
Simulation time 337095210000 ps
CPU time 838.22 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 06:26:41 PM PDT 24
Peak memory 160792 kb
Host smart-1e280e7c-3349-432c-b7ca-28f750c1402a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=396605736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.396605736
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3066006761
Short name T158
Test name
Test status
Simulation time 336647210000 ps
CPU time 726.29 seconds
Started Jun 23 05:52:09 PM PDT 24
Finished Jun 23 06:22:09 PM PDT 24
Peak memory 160804 kb
Host smart-f4d02a2a-6782-4ae8-a505-713d657142f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3066006761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3066006761
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1086102136
Short name T21
Test name
Test status
Simulation time 336821370000 ps
CPU time 910.13 seconds
Started Jun 23 05:52:18 PM PDT 24
Finished Jun 23 06:30:51 PM PDT 24
Peak memory 160844 kb
Host smart-f6772090-d90b-4bce-b36d-8753eae14390
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1086102136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1086102136
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3289190341
Short name T157
Test name
Test status
Simulation time 336675570000 ps
CPU time 675.12 seconds
Started Jun 23 05:52:11 PM PDT 24
Finished Jun 23 06:19:54 PM PDT 24
Peak memory 160852 kb
Host smart-d09aaf9d-da6e-4991-83f6-6b90b091fecd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3289190341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3289190341
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.530971998
Short name T152
Test name
Test status
Simulation time 336524770000 ps
CPU time 778.79 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 06:23:23 PM PDT 24
Peak memory 160824 kb
Host smart-599ae5f6-666b-4bf6-bcab-44ef8cdd6950
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=530971998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.530971998
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.3291935850
Short name T156
Test name
Test status
Simulation time 336825670000 ps
CPU time 815.17 seconds
Started Jun 23 05:52:12 PM PDT 24
Finished Jun 23 06:25:30 PM PDT 24
Peak memory 160828 kb
Host smart-ded1fbc5-c54d-4ba7-9494-ddbbe5c6845c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3291935850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.3291935850
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.351109739
Short name T22
Test name
Test status
Simulation time 336714710000 ps
CPU time 729.98 seconds
Started Jun 23 05:52:10 PM PDT 24
Finished Jun 23 06:22:30 PM PDT 24
Peak memory 160816 kb
Host smart-5b3d7315-7f3f-41cf-bb23-1299380e56a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=351109739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.351109739
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2713507516
Short name T136
Test name
Test status
Simulation time 336510590000 ps
CPU time 904.65 seconds
Started Jun 23 05:52:04 PM PDT 24
Finished Jun 23 06:29:42 PM PDT 24
Peak memory 160824 kb
Host smart-5cd29084-5dc1-4230-8cae-4c94a95df6ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2713507516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2713507516
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4038655875
Short name T17
Test name
Test status
Simulation time 336807030000 ps
CPU time 888.96 seconds
Started Jun 23 05:52:08 PM PDT 24
Finished Jun 23 06:28:44 PM PDT 24
Peak memory 160824 kb
Host smart-c1b21dd7-4712-43a5-8b93-aa3415cc9ac7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4038655875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.4038655875
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3070590251
Short name T126
Test name
Test status
Simulation time 336519470000 ps
CPU time 848 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:26:29 PM PDT 24
Peak memory 160816 kb
Host smart-51a62d94-f4a3-4a70-b370-d2da5535e594
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3070590251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3070590251
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1863134106
Short name T23
Test name
Test status
Simulation time 336830410000 ps
CPU time 709.61 seconds
Started Jun 23 05:52:12 PM PDT 24
Finished Jun 23 06:21:19 PM PDT 24
Peak memory 160824 kb
Host smart-d8ad3f77-343e-4214-86de-160add49bf6f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1863134106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1863134106
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3766565172
Short name T154
Test name
Test status
Simulation time 336442070000 ps
CPU time 786.68 seconds
Started Jun 23 05:52:05 PM PDT 24
Finished Jun 23 06:24:11 PM PDT 24
Peak memory 160824 kb
Host smart-2f423125-f310-4574-8189-c22ff9bd6496
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3766565172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3766565172
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1336267520
Short name T112
Test name
Test status
Simulation time 1474870000 ps
CPU time 4.72 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164920 kb
Host smart-652f2315-af34-4377-a44b-ff6670d97266
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1336267520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1336267520
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1493825803
Short name T105
Test name
Test status
Simulation time 1198850000 ps
CPU time 4.04 seconds
Started Jun 23 05:49:33 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164924 kb
Host smart-d9315e56-82f4-4df2-94a9-68cc4d045526
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493825803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1493825803
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3398989162
Short name T108
Test name
Test status
Simulation time 1575510000 ps
CPU time 4.7 seconds
Started Jun 23 05:49:38 PM PDT 24
Finished Jun 23 05:49:49 PM PDT 24
Peak memory 164972 kb
Host smart-4134a5a4-84da-4039-a178-d3272f723680
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3398989162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3398989162
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1093623660
Short name T99
Test name
Test status
Simulation time 1476270000 ps
CPU time 3.93 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164984 kb
Host smart-466d13dc-b7d0-4b43-a245-acd83b194503
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093623660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1093623660
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.273172212
Short name T101
Test name
Test status
Simulation time 1494610000 ps
CPU time 5.17 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 164944 kb
Host smart-3f1b2574-064c-4a0b-b4c2-3b14a665d7a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=273172212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.273172212
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3313672535
Short name T86
Test name
Test status
Simulation time 1345670000 ps
CPU time 3.59 seconds
Started Jun 23 05:49:38 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164984 kb
Host smart-880e5bad-4f54-4715-82d9-6b8c670c0946
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3313672535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3313672535
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.218268986
Short name T103
Test name
Test status
Simulation time 1503150000 ps
CPU time 4.46 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:41 PM PDT 24
Peak memory 164968 kb
Host smart-c9f55e05-97d2-4ca9-b14a-f0ffc1e8dd32
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218268986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.218268986
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1432870057
Short name T116
Test name
Test status
Simulation time 1493170000 ps
CPU time 5.57 seconds
Started Jun 23 05:49:34 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164976 kb
Host smart-a7ff6891-99f2-4302-a67d-064607b4e52f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432870057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1432870057
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2474643545
Short name T29
Test name
Test status
Simulation time 1467730000 ps
CPU time 3.96 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:41 PM PDT 24
Peak memory 164972 kb
Host smart-6a828fee-801a-4792-bce9-d8312150b5ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2474643545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2474643545
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1504409250
Short name T28
Test name
Test status
Simulation time 1303870000 ps
CPU time 4.68 seconds
Started Jun 23 05:49:35 PM PDT 24
Finished Jun 23 05:49:45 PM PDT 24
Peak memory 164944 kb
Host smart-3140ad83-46ef-489b-9386-6040fa99722c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504409250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1504409250
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4131924775
Short name T117
Test name
Test status
Simulation time 1442430000 ps
CPU time 4.65 seconds
Started Jun 23 05:49:34 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 164976 kb
Host smart-55f3ebd3-0cf5-48e4-9d4a-b0df01b09434
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131924775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.4131924775
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3227181916
Short name T118
Test name
Test status
Simulation time 1102430000 ps
CPU time 3.38 seconds
Started Jun 23 05:49:30 PM PDT 24
Finished Jun 23 05:49:38 PM PDT 24
Peak memory 164976 kb
Host smart-bd498cf8-ffea-4874-ac72-c232901f2de8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3227181916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3227181916
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2850883183
Short name T113
Test name
Test status
Simulation time 1496790000 ps
CPU time 3.06 seconds
Started Jun 23 05:49:35 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164900 kb
Host smart-64880180-0293-4824-b2f2-7e37589917c5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2850883183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2850883183
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2953115601
Short name T102
Test name
Test status
Simulation time 1512910000 ps
CPU time 4.46 seconds
Started Jun 23 05:49:34 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 164852 kb
Host smart-fe32b1b8-0f4d-40ae-9e29-1aaa961b9bb7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953115601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2953115601
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.497811425
Short name T84
Test name
Test status
Simulation time 1335530000 ps
CPU time 4.33 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164968 kb
Host smart-ce4fe6db-8082-4e60-85c6-fc66feb0a8cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=497811425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.497811425
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2351045768
Short name T111
Test name
Test status
Simulation time 1580850000 ps
CPU time 4.34 seconds
Started Jun 23 05:49:34 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 164976 kb
Host smart-ff2ae606-0adf-4443-9ddc-be22a1483722
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2351045768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2351045768
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3563677859
Short name T30
Test name
Test status
Simulation time 1505410000 ps
CPU time 3.79 seconds
Started Jun 23 05:49:37 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164892 kb
Host smart-d449e2cd-f8cb-49c6-961a-ff978cada2a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3563677859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3563677859
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.4248096942
Short name T25
Test name
Test status
Simulation time 1491970000 ps
CPU time 3.61 seconds
Started Jun 23 05:49:35 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 164968 kb
Host smart-8e6ce5fa-14a8-4532-88db-349988b7b258
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4248096942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.4248096942
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2573493466
Short name T81
Test name
Test status
Simulation time 1549150000 ps
CPU time 4.35 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 164952 kb
Host smart-46a29f6a-d0ae-4263-92e9-14f6bad7303a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2573493466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2573493466
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.637622463
Short name T27
Test name
Test status
Simulation time 1573510000 ps
CPU time 5.07 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 164972 kb
Host smart-0d0e7ed7-8bcd-4e1f-9a17-56d9d26dcc2b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637622463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.637622463
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2006163816
Short name T110
Test name
Test status
Simulation time 1494110000 ps
CPU time 4.61 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164976 kb
Host smart-5d38a5da-3333-49e4-aac1-2725d90a1b61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2006163816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2006163816
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1087660828
Short name T85
Test name
Test status
Simulation time 1505310000 ps
CPU time 4.13 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164940 kb
Host smart-1a3de1ec-9738-403f-9cd7-110bb38b7e96
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087660828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1087660828
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2797902239
Short name T88
Test name
Test status
Simulation time 1542270000 ps
CPU time 4.46 seconds
Started Jun 23 05:49:31 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164920 kb
Host smart-66d5627c-b208-4023-ad5f-ec973f90784b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2797902239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2797902239
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.632674550
Short name T100
Test name
Test status
Simulation time 1386030000 ps
CPU time 4.84 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164944 kb
Host smart-ef5125bd-f7be-4da2-a5d0-4e255a8ce53a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=632674550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.632674550
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3315802000
Short name T87
Test name
Test status
Simulation time 1528290000 ps
CPU time 4.91 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 164988 kb
Host smart-6d32c30c-eea3-48d6-8b6b-b023960ae395
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315802000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3315802000
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.831049835
Short name T107
Test name
Test status
Simulation time 1199650000 ps
CPU time 3.59 seconds
Started Jun 23 05:49:34 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164968 kb
Host smart-ca28a463-5ee7-40f4-aed6-622a65cf91a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=831049835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.831049835
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.834246525
Short name T119
Test name
Test status
Simulation time 1538150000 ps
CPU time 4.8 seconds
Started Jun 23 05:49:33 PM PDT 24
Finished Jun 23 05:49:44 PM PDT 24
Peak memory 164940 kb
Host smart-5a035c71-df52-4d2e-a2f5-1be7e5a8f205
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=834246525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.834246525
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.512263987
Short name T26
Test name
Test status
Simulation time 1417410000 ps
CPU time 4.05 seconds
Started Jun 23 05:49:38 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164980 kb
Host smart-d931c03d-72d7-443e-b8e9-7f269cc076f6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512263987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.512263987
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2783388815
Short name T114
Test name
Test status
Simulation time 1464250000 ps
CPU time 3.19 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:40 PM PDT 24
Peak memory 164976 kb
Host smart-ae239e8b-1bfb-4280-8ad5-1622fd8f9a21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2783388815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2783388815
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.844455302
Short name T115
Test name
Test status
Simulation time 1442970000 ps
CPU time 4.97 seconds
Started Jun 23 05:49:36 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164944 kb
Host smart-bdb59d89-88b1-4053-8a17-4be7d7d95911
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=844455302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.844455302
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1828802561
Short name T82
Test name
Test status
Simulation time 1594850000 ps
CPU time 4.03 seconds
Started Jun 23 05:49:37 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164984 kb
Host smart-504f55c0-573e-43df-80aa-4a9f17963284
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828802561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1828802561
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2735916991
Short name T89
Test name
Test status
Simulation time 1535690000 ps
CPU time 4.34 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 164896 kb
Host smart-710162c0-59d8-4dfd-9b94-76b5377609dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2735916991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2735916991
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2116125409
Short name T109
Test name
Test status
Simulation time 1585890000 ps
CPU time 3.11 seconds
Started Jun 23 05:49:39 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164976 kb
Host smart-bf90afae-67cc-4495-8def-729e127e3584
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2116125409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2116125409
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3352933782
Short name T98
Test name
Test status
Simulation time 1471770000 ps
CPU time 4.52 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164916 kb
Host smart-43971fde-cbca-486c-9750-c42873acb440
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3352933782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3352933782
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3724877688
Short name T5
Test name
Test status
Simulation time 1352110000 ps
CPU time 3.9 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 164896 kb
Host smart-7b8d76b8-8eba-4c94-b815-05a42dd00c1e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3724877688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.3724877688
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3582380286
Short name T83
Test name
Test status
Simulation time 1352870000 ps
CPU time 4.83 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:52 PM PDT 24
Peak memory 164948 kb
Host smart-e44c9e0c-2087-4cd9-9cea-d583d4dc37ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3582380286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3582380286
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1481475426
Short name T6
Test name
Test status
Simulation time 1155290000 ps
CPU time 3.66 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 164988 kb
Host smart-6c78b984-8b06-479c-8a27-e605173a979e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1481475426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1481475426
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.4223704958
Short name T94
Test name
Test status
Simulation time 1515410000 ps
CPU time 4.19 seconds
Started Jun 23 05:49:39 PM PDT 24
Finished Jun 23 05:49:49 PM PDT 24
Peak memory 164976 kb
Host smart-cc94dc0a-3a58-47d8-b072-41c130fc25f8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4223704958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.4223704958
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2742742330
Short name T93
Test name
Test status
Simulation time 1463990000 ps
CPU time 3.67 seconds
Started Jun 23 05:49:39 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164956 kb
Host smart-34ec9a80-f111-4e60-a542-97e5cb692b93
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2742742330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2742742330
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.4196977428
Short name T96
Test name
Test status
Simulation time 1480050000 ps
CPU time 4.41 seconds
Started Jun 23 05:49:42 PM PDT 24
Finished Jun 23 05:49:52 PM PDT 24
Peak memory 164944 kb
Host smart-688f5b7c-8076-4286-866f-d4bafbe27e31
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4196977428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.4196977428
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2065229681
Short name T92
Test name
Test status
Simulation time 1311870000 ps
CPU time 3.65 seconds
Started Jun 23 05:49:39 PM PDT 24
Finished Jun 23 05:49:47 PM PDT 24
Peak memory 164972 kb
Host smart-769068a0-fd09-4eb9-ae19-b9ff72312f02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2065229681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2065229681
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.67165141
Short name T97
Test name
Test status
Simulation time 1459250000 ps
CPU time 3.63 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 164864 kb
Host smart-03a7e2c9-310e-472b-ab7d-a77ca1407c57
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67165141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.67165141
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4043067663
Short name T120
Test name
Test status
Simulation time 1454450000 ps
CPU time 3.98 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 164852 kb
Host smart-f4617b5f-d471-48dc-ab11-d95a1b76b7a3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4043067663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4043067663
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2373691755
Short name T106
Test name
Test status
Simulation time 1481430000 ps
CPU time 3.75 seconds
Started Jun 23 05:49:41 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 164956 kb
Host smart-be0a47a0-b2d9-48b3-98ce-c8fc1f939e66
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2373691755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2373691755
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1240247687
Short name T95
Test name
Test status
Simulation time 1478390000 ps
CPU time 3.99 seconds
Started Jun 23 05:49:32 PM PDT 24
Finished Jun 23 05:49:41 PM PDT 24
Peak memory 164972 kb
Host smart-8e52571a-5e05-49ee-8a53-fa8cda3c169d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1240247687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1240247687
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2981671843
Short name T104
Test name
Test status
Simulation time 1554230000 ps
CPU time 4.72 seconds
Started Jun 23 05:49:35 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164972 kb
Host smart-aa195eaf-536f-4694-ba59-1389e2bd9458
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2981671843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2981671843
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3531191599
Short name T90
Test name
Test status
Simulation time 1333530000 ps
CPU time 3.77 seconds
Started Jun 23 05:49:37 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 164960 kb
Host smart-ec3b5e94-1e80-45c3-9bd0-204d41934350
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3531191599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3531191599
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3162094070
Short name T91
Test name
Test status
Simulation time 1590550000 ps
CPU time 3.2 seconds
Started Jun 23 05:49:35 PM PDT 24
Finished Jun 23 05:49:42 PM PDT 24
Peak memory 164948 kb
Host smart-3172e3fb-c278-4e9b-9c88-db568d628d61
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3162094070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3162094070
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.4092122662
Short name T24
Test name
Test status
Simulation time 1458310000 ps
CPU time 4.04 seconds
Started Jun 23 05:49:40 PM PDT 24
Finished Jun 23 05:49:50 PM PDT 24
Peak memory 164848 kb
Host smart-f35582f1-8567-4b20-9dfc-a48f80966780
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092122662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.4092122662
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.47662237
Short name T78
Test name
Test status
Simulation time 1454590000 ps
CPU time 5.2 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 05:52:33 PM PDT 24
Peak memory 164896 kb
Host smart-847d4db4-7cd1-4b43-b7d9-f581ed4e7d47
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47662237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.47662237
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.231223346
Short name T53
Test name
Test status
Simulation time 1445290000 ps
CPU time 5.09 seconds
Started Jun 23 05:52:19 PM PDT 24
Finished Jun 23 05:52:31 PM PDT 24
Peak memory 164900 kb
Host smart-ffa8f22a-decf-4e84-8661-f5ae0e3ae188
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231223346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.231223346
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.288221597
Short name T70
Test name
Test status
Simulation time 1567470000 ps
CPU time 4.97 seconds
Started Jun 23 05:52:24 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164968 kb
Host smart-605326c3-904d-4db1-ae02-8a66519b3bd2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288221597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.288221597
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1771684378
Short name T58
Test name
Test status
Simulation time 1481510000 ps
CPU time 5.13 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 05:52:32 PM PDT 24
Peak memory 164952 kb
Host smart-439c35e3-60e7-4046-8454-ab02d286634c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1771684378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1771684378
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2229475597
Short name T68
Test name
Test status
Simulation time 1541390000 ps
CPU time 4.8 seconds
Started Jun 23 05:52:27 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164972 kb
Host smart-9c754ee9-de38-4565-8170-bec849b24f33
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2229475597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2229475597
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1390499468
Short name T73
Test name
Test status
Simulation time 1315950000 ps
CPU time 3.08 seconds
Started Jun 23 05:52:31 PM PDT 24
Finished Jun 23 05:52:38 PM PDT 24
Peak memory 164972 kb
Host smart-a7c384ee-058e-4d4e-96e8-7a63fd55b707
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1390499468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1390499468
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1014150579
Short name T67
Test name
Test status
Simulation time 1663970000 ps
CPU time 5.14 seconds
Started Jun 23 05:52:23 PM PDT 24
Finished Jun 23 05:52:35 PM PDT 24
Peak memory 164916 kb
Host smart-f8dcad46-917a-4771-9f5d-38fdac9d613f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1014150579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1014150579
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1591146026
Short name T42
Test name
Test status
Simulation time 1266430000 ps
CPU time 4.24 seconds
Started Jun 23 05:52:25 PM PDT 24
Finished Jun 23 05:52:35 PM PDT 24
Peak memory 164988 kb
Host smart-a649e871-54d5-4892-999d-b47b4f223b71
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1591146026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1591146026
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3408658878
Short name T45
Test name
Test status
Simulation time 1471610000 ps
CPU time 4.95 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:40 PM PDT 24
Peak memory 164892 kb
Host smart-5f675770-fa89-45c9-9209-0f49223983eb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408658878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3408658878
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2674984360
Short name T3
Test name
Test status
Simulation time 1500990000 ps
CPU time 4.99 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 05:52:32 PM PDT 24
Peak memory 164960 kb
Host smart-b863eb32-82ac-44fc-b867-fb4d9fa1f0f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674984360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2674984360
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.239007932
Short name T44
Test name
Test status
Simulation time 1506350000 ps
CPU time 5.37 seconds
Started Jun 23 05:52:25 PM PDT 24
Finished Jun 23 05:52:37 PM PDT 24
Peak memory 164968 kb
Host smart-db71e83b-49ba-4c34-94e2-8ab8599391d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=239007932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.239007932
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2307440493
Short name T43
Test name
Test status
Simulation time 1320250000 ps
CPU time 3.72 seconds
Started Jun 23 05:52:23 PM PDT 24
Finished Jun 23 05:52:32 PM PDT 24
Peak memory 164972 kb
Host smart-66ce04cc-1ddb-4793-963d-9cf763f7a4b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2307440493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2307440493
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2309079014
Short name T66
Test name
Test status
Simulation time 1058390000 ps
CPU time 4.68 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164976 kb
Host smart-3d955503-f7a2-486b-9b62-27aaf9465807
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2309079014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2309079014
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.407648674
Short name T2
Test name
Test status
Simulation time 1389570000 ps
CPU time 5.19 seconds
Started Jun 23 05:52:25 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164968 kb
Host smart-ca4079d7-93da-4cbe-83a6-8dc8969addbf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=407648674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.407648674
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.933002651
Short name T8
Test name
Test status
Simulation time 1557250000 ps
CPU time 6.57 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164924 kb
Host smart-1669af2d-ecb4-47dd-84bb-c928dda36cd4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933002651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.933002651
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3644730705
Short name T57
Test name
Test status
Simulation time 1573390000 ps
CPU time 3.92 seconds
Started Jun 23 05:52:29 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164972 kb
Host smart-da9dc676-ce30-4f88-894d-671ae865c4b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3644730705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3644730705
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2880199571
Short name T54
Test name
Test status
Simulation time 1489730000 ps
CPU time 3.84 seconds
Started Jun 23 05:52:29 PM PDT 24
Finished Jun 23 05:52:38 PM PDT 24
Peak memory 164948 kb
Host smart-d91942f6-84ba-4b3a-9b08-8373a3ab1554
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2880199571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2880199571
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.658525705
Short name T69
Test name
Test status
Simulation time 1370050000 ps
CPU time 4.88 seconds
Started Jun 23 05:52:27 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164936 kb
Host smart-8814a1a4-75f9-47df-9d1f-680737278c7e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=658525705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.658525705
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.951972089
Short name T56
Test name
Test status
Simulation time 1194590000 ps
CPU time 3.42 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164936 kb
Host smart-f689d37d-a818-4dc5-ae57-5bc42c6a43d2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=951972089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.951972089
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2671547531
Short name T50
Test name
Test status
Simulation time 1331050000 ps
CPU time 4.44 seconds
Started Jun 23 05:52:34 PM PDT 24
Finished Jun 23 05:52:44 PM PDT 24
Peak memory 164928 kb
Host smart-8d4988c3-a863-4342-9c9a-fbd405e0d9b9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2671547531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2671547531
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.4133368637
Short name T79
Test name
Test status
Simulation time 1507530000 ps
CPU time 4.25 seconds
Started Jun 23 05:52:30 PM PDT 24
Finished Jun 23 05:52:40 PM PDT 24
Peak memory 164976 kb
Host smart-3450dacc-c474-4e87-8d99-9da3c6809c67
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4133368637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.4133368637
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1407770958
Short name T55
Test name
Test status
Simulation time 1317770000 ps
CPU time 4.33 seconds
Started Jun 23 05:52:35 PM PDT 24
Finished Jun 23 05:52:45 PM PDT 24
Peak memory 164944 kb
Host smart-ca1d0ade-2952-4e0a-952d-1fee3244a5e9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1407770958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1407770958
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.3791505384
Short name T7
Test name
Test status
Simulation time 1475670000 ps
CPU time 6.39 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:43 PM PDT 24
Peak memory 164976 kb
Host smart-ba5d33bc-600c-4d10-8d2d-4110b0008d36
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3791505384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.3791505384
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3309732901
Short name T75
Test name
Test status
Simulation time 1471930000 ps
CPU time 5.73 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164956 kb
Host smart-9766f839-ce3f-42c6-8788-62bc23b9347a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3309732901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3309732901
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.649447450
Short name T10
Test name
Test status
Simulation time 1604710000 ps
CPU time 5.66 seconds
Started Jun 23 05:52:30 PM PDT 24
Finished Jun 23 05:52:42 PM PDT 24
Peak memory 164984 kb
Host smart-cd309449-1a91-4e5f-9a81-c1bda045b360
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=649447450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.649447450
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.66092260
Short name T49
Test name
Test status
Simulation time 1442110000 ps
CPU time 4.46 seconds
Started Jun 23 05:52:30 PM PDT 24
Finished Jun 23 05:52:41 PM PDT 24
Peak memory 164900 kb
Host smart-dd66c9c1-a2ee-42c9-89bd-8396323fcacd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66092260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.66092260
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4288727647
Short name T41
Test name
Test status
Simulation time 1249650000 ps
CPU time 3.91 seconds
Started Jun 23 05:52:38 PM PDT 24
Finished Jun 23 05:52:47 PM PDT 24
Peak memory 164948 kb
Host smart-f777b91f-58cb-4c5b-a98e-7a3e817bf94d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288727647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4288727647
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.180849904
Short name T72
Test name
Test status
Simulation time 1352930000 ps
CPU time 4.26 seconds
Started Jun 23 05:52:34 PM PDT 24
Finished Jun 23 05:52:43 PM PDT 24
Peak memory 164936 kb
Host smart-225ace31-48e5-4710-97c0-d05fd977716a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=180849904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.180849904
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.824728329
Short name T59
Test name
Test status
Simulation time 1511190000 ps
CPU time 4.66 seconds
Started Jun 23 05:52:23 PM PDT 24
Finished Jun 23 05:52:34 PM PDT 24
Peak memory 164968 kb
Host smart-a8fe5cb0-7edb-482f-b85f-291018eabc88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824728329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.824728329
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1394146099
Short name T48
Test name
Test status
Simulation time 1615110000 ps
CPU time 5.27 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 05:52:38 PM PDT 24
Peak memory 164976 kb
Host smart-d4251044-a435-4331-a4ab-d62038c0515c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394146099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1394146099
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3891764335
Short name T13
Test name
Test status
Simulation time 1291370000 ps
CPU time 4.13 seconds
Started Jun 23 05:52:31 PM PDT 24
Finished Jun 23 05:52:41 PM PDT 24
Peak memory 164852 kb
Host smart-28317104-9de5-4795-8bf6-63531fdb8336
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3891764335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3891764335
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1726125894
Short name T46
Test name
Test status
Simulation time 1048250000 ps
CPU time 2.83 seconds
Started Jun 23 05:52:35 PM PDT 24
Finished Jun 23 05:52:42 PM PDT 24
Peak memory 164972 kb
Host smart-9d839a52-ae96-4aea-b0d8-93eb074eb70c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1726125894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1726125894
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.837379040
Short name T71
Test name
Test status
Simulation time 1397530000 ps
CPU time 4.27 seconds
Started Jun 23 05:52:27 PM PDT 24
Finished Jun 23 05:52:37 PM PDT 24
Peak memory 164972 kb
Host smart-b7085b0b-51b8-4ad6-9b51-476a8cbd6885
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=837379040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.837379040
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.899257956
Short name T9
Test name
Test status
Simulation time 941270000 ps
CPU time 3.39 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164900 kb
Host smart-abd669d4-0066-46e3-bc0f-5139f7ca4097
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899257956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.899257956
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.903772994
Short name T62
Test name
Test status
Simulation time 1259790000 ps
CPU time 4.6 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:40 PM PDT 24
Peak memory 164892 kb
Host smart-95f8711e-99a3-4a1c-bd2d-e106df7a5e65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=903772994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.903772994
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1842644227
Short name T47
Test name
Test status
Simulation time 1447870000 ps
CPU time 4.94 seconds
Started Jun 23 05:52:28 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164920 kb
Host smart-eb916631-94cc-4680-a51f-cba92c109d73
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1842644227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1842644227
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2409803534
Short name T63
Test name
Test status
Simulation time 1470730000 ps
CPU time 4.16 seconds
Started Jun 23 05:52:30 PM PDT 24
Finished Jun 23 05:52:40 PM PDT 24
Peak memory 164960 kb
Host smart-98c4257f-e5ce-4124-9cb7-053e6a99361c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2409803534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2409803534
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3557868625
Short name T64
Test name
Test status
Simulation time 1489710000 ps
CPU time 4.75 seconds
Started Jun 23 05:52:34 PM PDT 24
Finished Jun 23 05:52:45 PM PDT 24
Peak memory 164976 kb
Host smart-b5eb6295-92a6-4dda-86c9-f1f701a27141
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3557868625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3557868625
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2109343340
Short name T51
Test name
Test status
Simulation time 1422170000 ps
CPU time 4.92 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 05:52:38 PM PDT 24
Peak memory 164976 kb
Host smart-d68bf86b-94b6-4bb8-b259-f67ed4b1ab85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2109343340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2109343340
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3288590244
Short name T11
Test name
Test status
Simulation time 1554650000 ps
CPU time 5.02 seconds
Started Jun 23 05:52:34 PM PDT 24
Finished Jun 23 05:52:46 PM PDT 24
Peak memory 164948 kb
Host smart-148d8c5b-9071-47e9-8bea-e339ab44c8b7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3288590244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3288590244
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1690190282
Short name T80
Test name
Test status
Simulation time 1299770000 ps
CPU time 5.22 seconds
Started Jun 23 05:52:27 PM PDT 24
Finished Jun 23 05:52:39 PM PDT 24
Peak memory 164928 kb
Host smart-a1e393f2-a353-482f-8512-d0816e142af7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1690190282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1690190282
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.133440729
Short name T74
Test name
Test status
Simulation time 1401250000 ps
CPU time 4.79 seconds
Started Jun 23 05:52:29 PM PDT 24
Finished Jun 23 05:52:40 PM PDT 24
Peak memory 164888 kb
Host smart-b78bb1f9-d780-48f0-b859-5db3dd0debf0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=133440729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.133440729
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3803026813
Short name T1
Test name
Test status
Simulation time 1368790000 ps
CPU time 3.84 seconds
Started Jun 23 05:52:27 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164972 kb
Host smart-34c5cedb-1b43-44bb-85fb-96d69f18085d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3803026813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3803026813
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3881083876
Short name T77
Test name
Test status
Simulation time 1344770000 ps
CPU time 4.95 seconds
Started Jun 23 05:52:30 PM PDT 24
Finished Jun 23 05:52:41 PM PDT 24
Peak memory 164972 kb
Host smart-d7319595-3d73-4838-98b5-7c983b944f2b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881083876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3881083876
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2509155176
Short name T76
Test name
Test status
Simulation time 1341110000 ps
CPU time 4.22 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 05:52:31 PM PDT 24
Peak memory 164976 kb
Host smart-d8d0bb38-3349-4969-82ca-f087960c19cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2509155176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2509155176
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.4014357662
Short name T52
Test name
Test status
Simulation time 1263150000 ps
CPU time 4.52 seconds
Started Jun 23 05:52:24 PM PDT 24
Finished Jun 23 05:52:34 PM PDT 24
Peak memory 164944 kb
Host smart-9250fd7f-d70d-4ce5-a35c-006ed7a2b513
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4014357662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.4014357662
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.315069671
Short name T60
Test name
Test status
Simulation time 1545530000 ps
CPU time 4.01 seconds
Started Jun 23 05:52:21 PM PDT 24
Finished Jun 23 05:52:30 PM PDT 24
Peak memory 164872 kb
Host smart-f2001b51-de0a-4716-a397-346192fc3df5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315069671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.315069671
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2934672422
Short name T61
Test name
Test status
Simulation time 1276970000 ps
CPU time 4.03 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 164988 kb
Host smart-9754da40-6f3c-4de4-a6d5-e5b3a5f769a0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2934672422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2934672422
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1470854011
Short name T65
Test name
Test status
Simulation time 1509870000 ps
CPU time 4.92 seconds
Started Jun 23 05:52:26 PM PDT 24
Finished Jun 23 05:52:38 PM PDT 24
Peak memory 164988 kb
Host smart-aab5a89f-7b6b-4140-8574-45e66b34f741
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470854011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1470854011
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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