Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.487471627
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.705328462
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1500076958
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.244123932

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.832133756
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2856387546
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1456654069
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.205281033
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2467157700
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1546160730
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3091880172
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3691722135
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2102532567
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1554713684
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3836226107
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3910427492
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2787781354
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2393993453
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2717203542
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3470402392
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1811069828
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2060545011
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.44383192
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4070472434
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3677695455
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3529599903
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2178271952
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2927004318
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1119064169
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1762591948
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.235074632
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3209971708
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1355664186
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.552376420
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2432688857
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1848562197
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3307532943
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4209752254
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.763527794
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1997035364
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.140427841
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.169864351
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1387049100
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.534569174
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4270934298
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3699314948
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2133675665
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1053810843
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3791319210
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3243474337
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3365338678
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2355619510
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3575348078
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4056525127
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2453325474
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2064633815
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1510981090
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.131271361
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2731230622
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2644724603
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4186934554
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.842519844
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1986423329
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4113580512
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2899326142
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3661146212
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.261354007
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3535619108
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.620019348
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2160195320
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3413723226
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1241424557
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2275225874
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1998258926
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.167781441
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1880491550
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3604966911
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.572331707
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2438418007
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1522611914
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2622927702
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1950225480
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3941004011
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1833129566
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1589814149
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2216588944
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1353655363
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2989965966
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4209404994
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2765650816
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.526613246
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1397209240
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3590875023
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2319863831
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2017298084
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1221384656
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.275090671
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2453280411
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3222207780
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3367799157
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3856646705
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1854689720
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1735703749
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.914707327
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.986679786
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3056478238
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1370300477
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2364991511
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2141174607
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3277718543
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1162216194
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1501689748
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3081886427
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3291403431
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.917695393
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3528758585
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.762668934
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.601574227
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1367196306
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1944314467
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4294253729
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3226985073
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.290802826
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.514472739
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1894210461
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.45785604
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3411269619
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2417636872
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.781538603
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1569600787
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2955969966
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2404600947
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3977177856
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2572286187
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2967134218
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2540148703
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.815702982
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3374134683
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1085329893
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.752946186
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1711606236
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1980736244
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.714124720
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.386607909
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2176857660
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1719816990
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1857530047
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.58449901
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4178450487
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.645640702
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.532952895
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2339317737
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2841544792
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.669708141
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2997579287
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3781627300
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.775352359
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.982512315
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3015531332
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1662186035
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4011780170
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3303644975
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1083224819
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4205604562
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.537396514
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2570668880
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2087192919
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3067288009
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.833838392
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1405606783
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2500794872
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.965724898
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.304199420
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4202594775
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.601255759
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1352326298
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1109764439
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2065238661
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3538740100
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2049560340
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2372310842
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2838488782
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.259050663
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1476790558
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.487583375
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3690427187
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1003214367
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.184449379
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3379399058
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.397414581
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2554424711
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3148908035
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2252297725
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.300183715
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1538597005
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3435562661
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3787005529
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.275752716
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.730828799
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1188614254



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.601255759 Jun 24 05:15:18 PM PDT 24 Jun 24 05:15:26 PM PDT 24 1347170000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3379399058 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:28 PM PDT 24 1525310000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3538740100 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:25 PM PDT 24 1411430000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.487471627 Jun 24 05:15:14 PM PDT 24 Jun 24 05:15:25 PM PDT 24 1461990000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3015531332 Jun 24 05:15:09 PM PDT 24 Jun 24 05:15:18 PM PDT 24 1263730000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3787005529 Jun 24 05:15:09 PM PDT 24 Jun 24 05:15:17 PM PDT 24 1384350000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.965724898 Jun 24 05:15:17 PM PDT 24 Jun 24 05:15:28 PM PDT 24 1544830000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1662186035 Jun 24 05:15:08 PM PDT 24 Jun 24 05:15:21 PM PDT 24 1459310000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.300183715 Jun 24 05:15:18 PM PDT 24 Jun 24 05:15:31 PM PDT 24 1572130000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2252297725 Jun 24 05:15:17 PM PDT 24 Jun 24 05:15:26 PM PDT 24 1468090000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4011780170 Jun 24 05:15:12 PM PDT 24 Jun 24 05:15:25 PM PDT 24 1459050000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1188614254 Jun 24 05:15:09 PM PDT 24 Jun 24 05:15:20 PM PDT 24 1418010000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.259050663 Jun 24 05:15:18 PM PDT 24 Jun 24 05:15:27 PM PDT 24 1451050000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1109764439 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:27 PM PDT 24 1364670000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3435562661 Jun 24 05:15:08 PM PDT 24 Jun 24 05:15:21 PM PDT 24 1527050000 ps
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T47 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3781627300 Jun 24 05:15:08 PM PDT 24 Jun 24 05:15:20 PM PDT 24 1559990000 ps
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T59 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2049560340 Jun 24 05:15:15 PM PDT 24 Jun 24 05:15:29 PM PDT 24 1516770000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2087192919 Jun 24 05:15:19 PM PDT 24 Jun 24 05:15:30 PM PDT 24 1491650000 ps
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T62 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2065238661 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:28 PM PDT 24 1431070000 ps
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T64 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1405606783 Jun 24 05:15:20 PM PDT 24 Jun 24 05:15:29 PM PDT 24 1521870000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.775352359 Jun 24 05:15:10 PM PDT 24 Jun 24 05:15:18 PM PDT 24 1397010000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.275752716 Jun 24 05:15:08 PM PDT 24 Jun 24 05:15:19 PM PDT 24 1425750000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2838488782 Jun 24 05:15:14 PM PDT 24 Jun 24 05:15:26 PM PDT 24 1565610000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2500794872 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:26 PM PDT 24 1040730000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3690427187 Jun 24 05:15:17 PM PDT 24 Jun 24 05:15:29 PM PDT 24 1371650000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4205604562 Jun 24 05:15:09 PM PDT 24 Jun 24 05:15:19 PM PDT 24 1108410000 ps
T71 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2841544792 Jun 24 05:15:09 PM PDT 24 Jun 24 05:15:23 PM PDT 24 1334730000 ps
T72 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.184449379 Jun 24 05:15:17 PM PDT 24 Jun 24 05:15:28 PM PDT 24 1474550000 ps
T73 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1003214367 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:28 PM PDT 24 1327370000 ps
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T75 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3148908035 Jun 24 05:15:14 PM PDT 24 Jun 24 05:15:24 PM PDT 24 1562810000 ps
T76 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2554424711 Jun 24 05:15:16 PM PDT 24 Jun 24 05:15:30 PM PDT 24 1543150000 ps
T77 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.304199420 Jun 24 05:15:14 PM PDT 24 Jun 24 05:15:22 PM PDT 24 1571210000 ps
T78 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3303644975 Jun 24 05:15:10 PM PDT 24 Jun 24 05:15:18 PM PDT 24 1440030000 ps
T79 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4202594775 Jun 24 05:15:13 PM PDT 24 Jun 24 05:15:27 PM PDT 24 1627050000 ps
T80 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.537396514 Jun 24 05:15:11 PM PDT 24 Jun 24 05:15:22 PM PDT 24 1533790000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1980736244 Jun 24 05:17:12 PM PDT 24 Jun 24 05:17:23 PM PDT 24 1346310000 ps
T5 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2364991511 Jun 24 05:17:04 PM PDT 24 Jun 24 05:17:15 PM PDT 24 1395210000 ps
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T24 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.386607909 Jun 24 05:17:14 PM PDT 24 Jun 24 05:17:24 PM PDT 24 1218730000 ps
T25 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.244123932 Jun 24 05:17:04 PM PDT 24 Jun 24 05:17:14 PM PDT 24 1469210000 ps
T26 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2404600947 Jun 24 05:17:13 PM PDT 24 Jun 24 05:17:21 PM PDT 24 1381570000 ps
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T28 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3411269619 Jun 24 05:17:07 PM PDT 24 Jun 24 05:17:21 PM PDT 24 1527850000 ps
T29 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1569600787 Jun 24 05:17:06 PM PDT 24 Jun 24 05:17:16 PM PDT 24 1437390000 ps
T30 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2572286187 Jun 24 05:17:13 PM PDT 24 Jun 24 05:17:24 PM PDT 24 1381910000 ps
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T14 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2453280411 Jun 24 05:17:12 PM PDT 24 Jun 24 05:48:42 PM PDT 24 337093750000 ps
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T18 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1833129566 Jun 24 05:17:20 PM PDT 24 Jun 24 05:45:26 PM PDT 24 336579490000 ps
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T22 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.705328462 Jun 24 05:17:18 PM PDT 24 Jun 24 05:49:57 PM PDT 24 336326870000 ps
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T130 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1950225480 Jun 24 05:17:24 PM PDT 24 Jun 24 05:49:04 PM PDT 24 336668510000 ps
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T133 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1221384656 Jun 24 05:17:25 PM PDT 24 Jun 24 05:50:10 PM PDT 24 336576090000 ps
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T135 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3222207780 Jun 24 05:17:16 PM PDT 24 Jun 24 05:52:19 PM PDT 24 336976470000 ps
T136 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1998258926 Jun 24 05:17:21 PM PDT 24 Jun 24 05:52:49 PM PDT 24 336895770000 ps
T137 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3661146212 Jun 24 05:17:15 PM PDT 24 Jun 24 05:45:03 PM PDT 24 336609090000 ps
T138 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2017298084 Jun 24 05:17:21 PM PDT 24 Jun 24 05:54:52 PM PDT 24 336857950000 ps
T139 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.842519844 Jun 24 05:17:14 PM PDT 24 Jun 24 05:46:44 PM PDT 24 336853010000 ps
T140 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4186934554 Jun 24 05:17:15 PM PDT 24 Jun 24 05:46:06 PM PDT 24 336784430000 ps
T141 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.261354007 Jun 24 05:17:16 PM PDT 24 Jun 24 05:49:59 PM PDT 24 336342210000 ps
T142 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1522611914 Jun 24 05:17:22 PM PDT 24 Jun 24 05:52:25 PM PDT 24 336839590000 ps
T143 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4209404994 Jun 24 05:17:23 PM PDT 24 Jun 24 05:48:51 PM PDT 24 336383250000 ps
T144 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3367799157 Jun 24 05:17:13 PM PDT 24 Jun 24 05:48:36 PM PDT 24 336314070000 ps
T145 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2453325474 Jun 24 05:17:16 PM PDT 24 Jun 24 05:43:27 PM PDT 24 337006010000 ps
T146 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1589814149 Jun 24 05:17:22 PM PDT 24 Jun 24 05:51:31 PM PDT 24 337010950000 ps
T147 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2899326142 Jun 24 05:17:15 PM PDT 24 Jun 24 05:51:44 PM PDT 24 336751370000 ps
T148 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1510981090 Jun 24 05:17:16 PM PDT 24 Jun 24 05:53:18 PM PDT 24 336562110000 ps
T149 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.526613246 Jun 24 05:17:25 PM PDT 24 Jun 24 05:50:14 PM PDT 24 336567610000 ps
T150 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2216588944 Jun 24 05:17:23 PM PDT 24 Jun 24 05:48:27 PM PDT 24 336581850000 ps
T151 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3535619108 Jun 24 05:17:13 PM PDT 24 Jun 24 05:50:00 PM PDT 24 336647450000 ps
T152 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.620019348 Jun 24 05:17:15 PM PDT 24 Jun 24 05:48:24 PM PDT 24 337152430000 ps
T153 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4056525127 Jun 24 05:17:14 PM PDT 24 Jun 24 05:53:53 PM PDT 24 336637330000 ps
T154 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3856646705 Jun 24 05:17:15 PM PDT 24 Jun 24 05:48:48 PM PDT 24 336795550000 ps
T155 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1854689720 Jun 24 05:17:13 PM PDT 24 Jun 24 05:45:31 PM PDT 24 336978070000 ps
T156 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1880491550 Jun 24 05:17:14 PM PDT 24 Jun 24 05:53:29 PM PDT 24 336321770000 ps
T157 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2765650816 Jun 24 05:17:22 PM PDT 24 Jun 24 05:46:59 PM PDT 24 336779130000 ps
T158 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1397209240 Jun 24 05:17:23 PM PDT 24 Jun 24 05:55:07 PM PDT 24 336739570000 ps
T159 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2438418007 Jun 24 05:17:22 PM PDT 24 Jun 24 05:48:21 PM PDT 24 336437250000 ps
T160 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4113580512 Jun 24 05:17:17 PM PDT 24 Jun 24 05:49:21 PM PDT 24 336396250000 ps
T31 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2927004318 Jun 24 04:21:05 PM PDT 24 Jun 24 04:50:23 PM PDT 24 337083170000 ps
T32 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3470402392 Jun 24 04:21:22 PM PDT 24 Jun 24 04:49:10 PM PDT 24 336613310000 ps
T33 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4209752254 Jun 24 04:22:12 PM PDT 24 Jun 24 04:54:16 PM PDT 24 336736870000 ps
T34 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2133675665 Jun 24 04:20:16 PM PDT 24 Jun 24 04:54:36 PM PDT 24 337004430000 ps
T35 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1500076958 Jun 24 04:21:38 PM PDT 24 Jun 24 04:47:04 PM PDT 24 336579910000 ps
T36 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3575348078 Jun 24 04:22:13 PM PDT 24 Jun 24 04:48:24 PM PDT 24 336965150000 ps
T37 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3910427492 Jun 24 04:19:31 PM PDT 24 Jun 24 04:49:05 PM PDT 24 336421490000 ps
T38 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2060545011 Jun 24 04:20:57 PM PDT 24 Jun 24 04:53:24 PM PDT 24 337116030000 ps
T39 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2393993453 Jun 24 04:22:13 PM PDT 24 Jun 24 04:54:34 PM PDT 24 337090890000 ps
T40 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2717203542 Jun 24 04:21:44 PM PDT 24 Jun 24 04:49:03 PM PDT 24 336794410000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2355619510 Jun 24 04:21:24 PM PDT 24 Jun 24 04:51:00 PM PDT 24 336591870000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2787781354 Jun 24 04:22:13 PM PDT 24 Jun 24 04:54:26 PM PDT 24 337130430000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1811069828 Jun 24 04:16:45 PM PDT 24 Jun 24 04:48:45 PM PDT 24 336937210000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.235074632 Jun 24 04:21:42 PM PDT 24 Jun 24 04:55:03 PM PDT 24 336728750000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4070472434 Jun 24 04:16:35 PM PDT 24 Jun 24 04:49:26 PM PDT 24 336685610000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3699314948 Jun 24 04:22:02 PM PDT 24 Jun 24 04:51:06 PM PDT 24 336332890000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1997035364 Jun 24 04:19:10 PM PDT 24 Jun 24 04:51:22 PM PDT 24 337075290000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1554713684 Jun 24 04:22:16 PM PDT 24 Jun 24 04:47:32 PM PDT 24 337079210000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.169864351 Jun 24 04:22:04 PM PDT 24 Jun 24 04:53:13 PM PDT 24 336442470000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3677695455 Jun 24 04:21:50 PM PDT 24 Jun 24 04:55:18 PM PDT 24 336482030000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1546160730 Jun 24 04:21:23 PM PDT 24 Jun 24 04:45:46 PM PDT 24 336343270000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.552376420 Jun 24 04:22:55 PM PDT 24 Jun 24 04:50:49 PM PDT 24 336890210000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3091880172 Jun 24 04:21:37 PM PDT 24 Jun 24 04:53:06 PM PDT 24 336361830000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.44383192 Jun 24 04:21:22 PM PDT 24 Jun 24 04:48:55 PM PDT 24 336919950000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1119064169 Jun 24 04:17:16 PM PDT 24 Jun 24 04:46:51 PM PDT 24 336983310000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2856387546 Jun 24 04:19:10 PM PDT 24 Jun 24 04:52:11 PM PDT 24 336617450000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1848562197 Jun 24 04:19:03 PM PDT 24 Jun 24 04:50:49 PM PDT 24 336818670000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1762591948 Jun 24 04:22:49 PM PDT 24 Jun 24 04:51:58 PM PDT 24 336743510000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3209971708 Jun 24 04:18:49 PM PDT 24 Jun 24 04:51:46 PM PDT 24 336877910000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.534569174 Jun 24 04:22:38 PM PDT 24 Jun 24 04:50:09 PM PDT 24 336429910000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.832133756 Jun 24 04:22:08 PM PDT 24 Jun 24 04:53:59 PM PDT 24 336944110000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1456654069 Jun 24 04:21:24 PM PDT 24 Jun 24 04:50:57 PM PDT 24 336734110000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3243474337 Jun 24 04:22:45 PM PDT 24 Jun 24 04:55:00 PM PDT 24 336483690000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3691722135 Jun 24 04:18:53 PM PDT 24 Jun 24 04:48:23 PM PDT 24 336893490000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2432688857 Jun 24 04:21:59 PM PDT 24 Jun 24 04:47:21 PM PDT 24 336808890000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1387049100 Jun 24 04:22:03 PM PDT 24 Jun 24 04:53:05 PM PDT 24 336409690000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3791319210 Jun 24 04:22:03 PM PDT 24 Jun 24 04:55:30 PM PDT 24 336571770000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3307532943 Jun 24 04:22:23 PM PDT 24 Jun 24 04:51:10 PM PDT 24 336394810000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2178271952 Jun 24 04:22:04 PM PDT 24 Jun 24 04:54:44 PM PDT 24 336701310000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2102532567 Jun 24 04:22:24 PM PDT 24 Jun 24 04:48:59 PM PDT 24 336864190000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.205281033 Jun 24 04:22:24 PM PDT 24 Jun 24 04:49:04 PM PDT 24 336569830000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1053810843 Jun 24 04:21:34 PM PDT 24 Jun 24 04:51:41 PM PDT 24 337107730000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1355664186 Jun 24 04:21:16 PM PDT 24 Jun 24 04:46:27 PM PDT 24 336630610000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3529599903 Jun 24 04:23:18 PM PDT 24 Jun 24 04:52:05 PM PDT 24 336831930000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.140427841 Jun 24 04:17:46 PM PDT 24 Jun 24 04:48:42 PM PDT 24 336472770000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3836226107 Jun 24 04:16:42 PM PDT 24 Jun 24 04:47:45 PM PDT 24 336515890000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2467157700 Jun 24 04:21:36 PM PDT 24 Jun 24 04:51:02 PM PDT 24 336500630000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.763527794 Jun 24 04:22:13 PM PDT 24 Jun 24 04:54:34 PM PDT 24 336874530000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3365338678 Jun 24 04:22:45 PM PDT 24 Jun 24 04:55:25 PM PDT 24 337044270000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4270934298 Jun 24 04:17:23 PM PDT 24 Jun 24 04:50:38 PM PDT 24 336714070000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.487471627
Short name T7
Test name
Test status
Simulation time 1461990000 ps
CPU time 5.22 seconds
Started Jun 24 05:15:14 PM PDT 24
Finished Jun 24 05:15:25 PM PDT 24
Peak memory 164968 kb
Host smart-c1fd43b0-187b-485b-b6b2-ff059cbd58f9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487471627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.487471627
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.705328462
Short name T22
Test name
Test status
Simulation time 336326870000 ps
CPU time 798.67 seconds
Started Jun 24 05:17:18 PM PDT 24
Finished Jun 24 05:49:57 PM PDT 24
Peak memory 160812 kb
Host smart-44f1544c-784c-40e9-9558-3ab81bd8fb46
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=705328462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.705328462
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1500076958
Short name T35
Test name
Test status
Simulation time 336579910000 ps
CPU time 622.39 seconds
Started Jun 24 04:21:38 PM PDT 24
Finished Jun 24 04:47:04 PM PDT 24
Peak memory 159768 kb
Host smart-eb6b905c-9ce7-4f77-8cbd-c4d5b6e3fb6c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1500076958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1500076958
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.244123932
Short name T25
Test name
Test status
Simulation time 1469210000 ps
CPU time 3.79 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:14 PM PDT 24
Peak memory 164880 kb
Host smart-7a78fae1-33aa-4abc-b573-d70041058b0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=244123932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.244123932
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.832133756
Short name T181
Test name
Test status
Simulation time 336944110000 ps
CPU time 782.87 seconds
Started Jun 24 04:22:08 PM PDT 24
Finished Jun 24 04:53:59 PM PDT 24
Peak memory 160624 kb
Host smart-44abf199-ea90-404d-aaf9-b531f345d3e1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=832133756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.832133756
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2856387546
Short name T176
Test name
Test status
Simulation time 336617450000 ps
CPU time 813.76 seconds
Started Jun 24 04:19:10 PM PDT 24
Finished Jun 24 04:52:11 PM PDT 24
Peak memory 160892 kb
Host smart-26dcb467-044b-4582-ab9e-4482709de871
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2856387546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2856387546
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1456654069
Short name T182
Test name
Test status
Simulation time 336734110000 ps
CPU time 720.79 seconds
Started Jun 24 04:21:24 PM PDT 24
Finished Jun 24 04:50:57 PM PDT 24
Peak memory 159368 kb
Host smart-82fcd8f7-6bc1-4e24-a584-647d01461d9b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1456654069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1456654069
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.205281033
Short name T191
Test name
Test status
Simulation time 336569830000 ps
CPU time 645.2 seconds
Started Jun 24 04:22:24 PM PDT 24
Finished Jun 24 04:49:04 PM PDT 24
Peak memory 160004 kb
Host smart-80df7025-5cda-4eb5-a6c1-3320c7b637fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=205281033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.205281033
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2467157700
Short name T197
Test name
Test status
Simulation time 336500630000 ps
CPU time 713.25 seconds
Started Jun 24 04:21:36 PM PDT 24
Finished Jun 24 04:51:02 PM PDT 24
Peak memory 159768 kb
Host smart-ad2bb911-aa63-4c18-a164-2e375e25aa81
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2467157700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2467157700
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.1546160730
Short name T171
Test name
Test status
Simulation time 336343270000 ps
CPU time 593.83 seconds
Started Jun 24 04:21:23 PM PDT 24
Finished Jun 24 04:45:46 PM PDT 24
Peak memory 159296 kb
Host smart-805f294a-53bf-4d06-a708-0ab44c494f9b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1546160730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.1546160730
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3091880172
Short name T173
Test name
Test status
Simulation time 336361830000 ps
CPU time 769.8 seconds
Started Jun 24 04:21:37 PM PDT 24
Finished Jun 24 04:53:06 PM PDT 24
Peak memory 160196 kb
Host smart-e86a1d66-39b8-454b-8e33-52fae8e369e0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3091880172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3091880172
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3691722135
Short name T184
Test name
Test status
Simulation time 336893490000 ps
CPU time 722.34 seconds
Started Jun 24 04:18:53 PM PDT 24
Finished Jun 24 04:48:23 PM PDT 24
Peak memory 160900 kb
Host smart-b710d298-61d4-46b4-b74e-b4db644098e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3691722135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3691722135
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2102532567
Short name T190
Test name
Test status
Simulation time 336864190000 ps
CPU time 643.3 seconds
Started Jun 24 04:22:24 PM PDT 24
Finished Jun 24 04:48:59 PM PDT 24
Peak memory 159976 kb
Host smart-afc65bd5-8880-4940-b3ee-68a8728a1b7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2102532567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2102532567
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1554713684
Short name T168
Test name
Test status
Simulation time 337079210000 ps
CPU time 612.81 seconds
Started Jun 24 04:22:16 PM PDT 24
Finished Jun 24 04:47:32 PM PDT 24
Peak memory 159204 kb
Host smart-8b434b06-692d-4ee2-b749-e7eb7af451ec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1554713684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1554713684
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3836226107
Short name T196
Test name
Test status
Simulation time 336515890000 ps
CPU time 768.27 seconds
Started Jun 24 04:16:42 PM PDT 24
Finished Jun 24 04:47:45 PM PDT 24
Peak memory 160232 kb
Host smart-d302eaf4-7147-4010-8422-567af546b0e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3836226107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3836226107
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3910427492
Short name T37
Test name
Test status
Simulation time 336421490000 ps
CPU time 720.34 seconds
Started Jun 24 04:19:31 PM PDT 24
Finished Jun 24 04:49:05 PM PDT 24
Peak memory 160568 kb
Host smart-7538e2e8-e738-4377-89bf-1a61e19a2838
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3910427492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3910427492
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2787781354
Short name T162
Test name
Test status
Simulation time 337130430000 ps
CPU time 802.41 seconds
Started Jun 24 04:22:13 PM PDT 24
Finished Jun 24 04:54:26 PM PDT 24
Peak memory 159340 kb
Host smart-74ec8a9a-05e6-426f-a9de-d18ded457b9e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2787781354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2787781354
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2393993453
Short name T39
Test name
Test status
Simulation time 337090890000 ps
CPU time 798.3 seconds
Started Jun 24 04:22:13 PM PDT 24
Finished Jun 24 04:54:34 PM PDT 24
Peak memory 159332 kb
Host smart-e97c9ac3-6953-469c-928e-9f5d03924f0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2393993453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2393993453
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2717203542
Short name T40
Test name
Test status
Simulation time 336794410000 ps
CPU time 672.05 seconds
Started Jun 24 04:21:44 PM PDT 24
Finished Jun 24 04:49:03 PM PDT 24
Peak memory 159768 kb
Host smart-739b984e-3461-48eb-9838-96fb7f4fd5bf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2717203542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2717203542
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3470402392
Short name T32
Test name
Test status
Simulation time 336613310000 ps
CPU time 679.94 seconds
Started Jun 24 04:21:22 PM PDT 24
Finished Jun 24 04:49:10 PM PDT 24
Peak memory 159768 kb
Host smart-41186d09-a326-41f1-a13d-aaff7cf47716
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3470402392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3470402392
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1811069828
Short name T163
Test name
Test status
Simulation time 336937210000 ps
CPU time 791.14 seconds
Started Jun 24 04:16:45 PM PDT 24
Finished Jun 24 04:48:45 PM PDT 24
Peak memory 160328 kb
Host smart-3467cec1-897f-459a-8d72-87651da2e105
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1811069828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1811069828
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2060545011
Short name T38
Test name
Test status
Simulation time 337116030000 ps
CPU time 801.66 seconds
Started Jun 24 04:20:57 PM PDT 24
Finished Jun 24 04:53:24 PM PDT 24
Peak memory 160632 kb
Host smart-d0a259cc-b9dd-4ba4-846c-2b590683a1b7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2060545011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2060545011
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.44383192
Short name T174
Test name
Test status
Simulation time 336919950000 ps
CPU time 669.38 seconds
Started Jun 24 04:21:22 PM PDT 24
Finished Jun 24 04:48:55 PM PDT 24
Peak memory 160160 kb
Host smart-00d41e40-ce6b-4393-82a4-6e6f5ad73651
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=44383192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.44383192
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4070472434
Short name T165
Test name
Test status
Simulation time 336685610000 ps
CPU time 805.79 seconds
Started Jun 24 04:16:35 PM PDT 24
Finished Jun 24 04:49:26 PM PDT 24
Peak memory 160540 kb
Host smart-73126f55-cfc7-4c37-bc8f-f14f326a4ddd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4070472434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4070472434
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3677695455
Short name T170
Test name
Test status
Simulation time 336482030000 ps
CPU time 820.1 seconds
Started Jun 24 04:21:50 PM PDT 24
Finished Jun 24 04:55:18 PM PDT 24
Peak memory 159768 kb
Host smart-ba2c03f2-c3b5-48e6-9158-dfc9968dbb69
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3677695455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3677695455
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3529599903
Short name T194
Test name
Test status
Simulation time 336831930000 ps
CPU time 699.45 seconds
Started Jun 24 04:23:18 PM PDT 24
Finished Jun 24 04:52:05 PM PDT 24
Peak memory 160264 kb
Host smart-1930447f-25ea-4ca2-ab9f-a7d5af4cd31a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3529599903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3529599903
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2178271952
Short name T189
Test name
Test status
Simulation time 336701310000 ps
CPU time 799.36 seconds
Started Jun 24 04:22:04 PM PDT 24
Finished Jun 24 04:54:44 PM PDT 24
Peak memory 160252 kb
Host smart-a3cd644f-8e4a-46a9-9b4f-d932584a62eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2178271952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2178271952
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2927004318
Short name T31
Test name
Test status
Simulation time 337083170000 ps
CPU time 713.04 seconds
Started Jun 24 04:21:05 PM PDT 24
Finished Jun 24 04:50:23 PM PDT 24
Peak memory 160588 kb
Host smart-03985c54-42b2-434c-9eb9-058887da3f23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2927004318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2927004318
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1119064169
Short name T175
Test name
Test status
Simulation time 336983310000 ps
CPU time 730.27 seconds
Started Jun 24 04:17:16 PM PDT 24
Finished Jun 24 04:46:51 PM PDT 24
Peak memory 160900 kb
Host smart-11471037-2073-4737-9204-c7a8824acd5b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1119064169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1119064169
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1762591948
Short name T178
Test name
Test status
Simulation time 336743510000 ps
CPU time 712.52 seconds
Started Jun 24 04:22:49 PM PDT 24
Finished Jun 24 04:51:58 PM PDT 24
Peak memory 159768 kb
Host smart-deec5b6c-6e72-46f5-911e-2f80bbc19b55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1762591948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1762591948
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.235074632
Short name T164
Test name
Test status
Simulation time 336728750000 ps
CPU time 822.54 seconds
Started Jun 24 04:21:42 PM PDT 24
Finished Jun 24 04:55:03 PM PDT 24
Peak memory 160896 kb
Host smart-f5a0c815-2eb0-411d-b456-5e229c9083e9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=235074632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.235074632
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3209971708
Short name T179
Test name
Test status
Simulation time 336877910000 ps
CPU time 804.61 seconds
Started Jun 24 04:18:49 PM PDT 24
Finished Jun 24 04:51:46 PM PDT 24
Peak memory 160636 kb
Host smart-e0d13cc7-8706-4450-b80f-964eb059f117
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3209971708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3209971708
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1355664186
Short name T193
Test name
Test status
Simulation time 336630610000 ps
CPU time 614.3 seconds
Started Jun 24 04:21:16 PM PDT 24
Finished Jun 24 04:46:27 PM PDT 24
Peak memory 159768 kb
Host smart-02212bcc-5e60-4a1c-b7da-d963222cde1f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1355664186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1355664186
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.552376420
Short name T172
Test name
Test status
Simulation time 336890210000 ps
CPU time 680.98 seconds
Started Jun 24 04:22:55 PM PDT 24
Finished Jun 24 04:50:49 PM PDT 24
Peak memory 160548 kb
Host smart-462a2564-0079-44f9-97cf-45a675c78515
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=552376420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.552376420
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2432688857
Short name T185
Test name
Test status
Simulation time 336808890000 ps
CPU time 620.21 seconds
Started Jun 24 04:21:59 PM PDT 24
Finished Jun 24 04:47:21 PM PDT 24
Peak memory 160548 kb
Host smart-7a74e150-91d6-4f1a-8af0-174e0f74a458
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2432688857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2432688857
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1848562197
Short name T177
Test name
Test status
Simulation time 336818670000 ps
CPU time 787.9 seconds
Started Jun 24 04:19:03 PM PDT 24
Finished Jun 24 04:50:49 PM PDT 24
Peak memory 160532 kb
Host smart-2cbb368c-dc08-423c-b3b7-98d4c20696b8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1848562197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1848562197
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3307532943
Short name T188
Test name
Test status
Simulation time 336394810000 ps
CPU time 705.76 seconds
Started Jun 24 04:22:23 PM PDT 24
Finished Jun 24 04:51:10 PM PDT 24
Peak memory 159768 kb
Host smart-5bdac594-37f2-4d2d-aac9-589dd20a5f96
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3307532943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3307532943
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.4209752254
Short name T33
Test name
Test status
Simulation time 336736870000 ps
CPU time 788.43 seconds
Started Jun 24 04:22:12 PM PDT 24
Finished Jun 24 04:54:16 PM PDT 24
Peak memory 159760 kb
Host smart-f93dda8d-916c-4d79-89c2-769e51da8588
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4209752254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.4209752254
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.763527794
Short name T198
Test name
Test status
Simulation time 336874530000 ps
CPU time 793.57 seconds
Started Jun 24 04:22:13 PM PDT 24
Finished Jun 24 04:54:34 PM PDT 24
Peak memory 160188 kb
Host smart-eed89374-f3f6-4827-824b-48d82360c519
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=763527794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.763527794
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1997035364
Short name T167
Test name
Test status
Simulation time 337075290000 ps
CPU time 785.2 seconds
Started Jun 24 04:19:10 PM PDT 24
Finished Jun 24 04:51:22 PM PDT 24
Peak memory 160636 kb
Host smart-29946149-ef6e-4799-8c5c-1c5a1c60e5ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997035364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1997035364
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.140427841
Short name T195
Test name
Test status
Simulation time 336472770000 ps
CPU time 761.45 seconds
Started Jun 24 04:17:46 PM PDT 24
Finished Jun 24 04:48:42 PM PDT 24
Peak memory 160580 kb
Host smart-4b267f76-2f44-4039-814a-0c364d8c4bf6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=140427841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.140427841
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.169864351
Short name T169
Test name
Test status
Simulation time 336442470000 ps
CPU time 763.83 seconds
Started Jun 24 04:22:04 PM PDT 24
Finished Jun 24 04:53:13 PM PDT 24
Peak memory 160152 kb
Host smart-d45f38df-6928-4eec-82dc-2d8cc3c85c64
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=169864351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.169864351
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1387049100
Short name T186
Test name
Test status
Simulation time 336409690000 ps
CPU time 772.68 seconds
Started Jun 24 04:22:03 PM PDT 24
Finished Jun 24 04:53:05 PM PDT 24
Peak memory 159768 kb
Host smart-977802c3-647c-46ec-83d9-91e1ec142280
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1387049100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1387049100
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.534569174
Short name T180
Test name
Test status
Simulation time 336429910000 ps
CPU time 673.84 seconds
Started Jun 24 04:22:38 PM PDT 24
Finished Jun 24 04:50:09 PM PDT 24
Peak memory 159760 kb
Host smart-0c8c2c2c-257c-4412-95a6-cf0337f83002
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=534569174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.534569174
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.4270934298
Short name T200
Test name
Test status
Simulation time 336714070000 ps
CPU time 825.6 seconds
Started Jun 24 04:17:23 PM PDT 24
Finished Jun 24 04:50:38 PM PDT 24
Peak memory 160904 kb
Host smart-c77999a3-05f7-459f-a784-2ad597560ef8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270934298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.4270934298
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3699314948
Short name T166
Test name
Test status
Simulation time 336332890000 ps
CPU time 709.95 seconds
Started Jun 24 04:22:02 PM PDT 24
Finished Jun 24 04:51:06 PM PDT 24
Peak memory 160536 kb
Host smart-334f4f93-f6c0-4ae6-bbdf-e524b4749034
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3699314948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3699314948
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2133675665
Short name T34
Test name
Test status
Simulation time 337004430000 ps
CPU time 844.69 seconds
Started Jun 24 04:20:16 PM PDT 24
Finished Jun 24 04:54:36 PM PDT 24
Peak memory 160896 kb
Host smart-e9bce41f-3e27-4180-9c8b-1ccb8339324a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2133675665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2133675665
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1053810843
Short name T192
Test name
Test status
Simulation time 337107730000 ps
CPU time 727.01 seconds
Started Jun 24 04:21:34 PM PDT 24
Finished Jun 24 04:51:41 PM PDT 24
Peak memory 159712 kb
Host smart-2e888a21-6b7a-4d25-9c81-b3128df665ea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1053810843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1053810843
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.3791319210
Short name T187
Test name
Test status
Simulation time 336571770000 ps
CPU time 829.66 seconds
Started Jun 24 04:22:03 PM PDT 24
Finished Jun 24 04:55:30 PM PDT 24
Peak memory 159760 kb
Host smart-c6f64b38-3f04-4e24-8ac7-8974c05a558d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3791319210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.3791319210
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3243474337
Short name T183
Test name
Test status
Simulation time 336483690000 ps
CPU time 784.69 seconds
Started Jun 24 04:22:45 PM PDT 24
Finished Jun 24 04:55:00 PM PDT 24
Peak memory 159392 kb
Host smart-1e3a7d58-2cd5-4b17-8dd1-cc5c7076de9e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3243474337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3243474337
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3365338678
Short name T199
Test name
Test status
Simulation time 337044270000 ps
CPU time 791.34 seconds
Started Jun 24 04:22:45 PM PDT 24
Finished Jun 24 04:55:25 PM PDT 24
Peak memory 159400 kb
Host smart-d53321a4-c02e-4491-873b-6d703ecfe8d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3365338678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3365338678
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2355619510
Short name T161
Test name
Test status
Simulation time 336591870000 ps
CPU time 722.97 seconds
Started Jun 24 04:21:24 PM PDT 24
Finished Jun 24 04:51:00 PM PDT 24
Peak memory 159316 kb
Host smart-70dd87e6-ed98-4109-aa60-80c62dc5bcde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2355619510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2355619510
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3575348078
Short name T36
Test name
Test status
Simulation time 336965150000 ps
CPU time 644.42 seconds
Started Jun 24 04:22:13 PM PDT 24
Finished Jun 24 04:48:24 PM PDT 24
Peak memory 159760 kb
Host smart-76b8e71c-cfb2-4219-a4b9-b6012882e2e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3575348078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3575348078
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4056525127
Short name T153
Test name
Test status
Simulation time 336637330000 ps
CPU time 901.87 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:53:53 PM PDT 24
Peak memory 160728 kb
Host smart-a07d1126-0004-4c70-b3e7-7ad431324fd2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4056525127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4056525127
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2453325474
Short name T145
Test name
Test status
Simulation time 337006010000 ps
CPU time 621.51 seconds
Started Jun 24 05:17:16 PM PDT 24
Finished Jun 24 05:43:27 PM PDT 24
Peak memory 160832 kb
Host smart-e88b250a-d0fe-4c00-94a9-dcece5c3a89e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2453325474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2453325474
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2064633815
Short name T129
Test name
Test status
Simulation time 336723210000 ps
CPU time 794.94 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:50:07 PM PDT 24
Peak memory 160812 kb
Host smart-e1afbf09-bbec-4083-9827-2a6cd5cd6c8b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2064633815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2064633815
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1510981090
Short name T148
Test name
Test status
Simulation time 336562110000 ps
CPU time 881.34 seconds
Started Jun 24 05:17:16 PM PDT 24
Finished Jun 24 05:53:18 PM PDT 24
Peak memory 160736 kb
Host smart-03cc3d46-8ce3-4078-8b20-bbe93ebff10d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1510981090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1510981090
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.131271361
Short name T125
Test name
Test status
Simulation time 336792670000 ps
CPU time 856.37 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:51:43 PM PDT 24
Peak memory 160784 kb
Host smart-11cda52e-f023-4dee-bc46-99236d3a9b74
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=131271361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.131271361
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2731230622
Short name T122
Test name
Test status
Simulation time 336959470000 ps
CPU time 799.28 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:49:56 PM PDT 24
Peak memory 160812 kb
Host smart-a5348e62-8127-4baf-b162-b3685eb8ce30
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2731230622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2731230622
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2644724603
Short name T132
Test name
Test status
Simulation time 336739170000 ps
CPU time 780.84 seconds
Started Jun 24 05:17:17 PM PDT 24
Finished Jun 24 05:49:08 PM PDT 24
Peak memory 160816 kb
Host smart-d3b79cd9-5e74-4e7f-a5a2-6d1d89764d95
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2644724603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2644724603
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4186934554
Short name T140
Test name
Test status
Simulation time 336784430000 ps
CPU time 704.19 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:46:06 PM PDT 24
Peak memory 160816 kb
Host smart-65e2e741-69bf-4fa7-a2d5-8d05e35e598b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4186934554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4186934554
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.842519844
Short name T139
Test name
Test status
Simulation time 336853010000 ps
CPU time 720.6 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:46:44 PM PDT 24
Peak memory 160728 kb
Host smart-d124e1d4-597b-4c8c-90e1-37791fd63fd3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=842519844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.842519844
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1986423329
Short name T128
Test name
Test status
Simulation time 336651730000 ps
CPU time 917.32 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:54:22 PM PDT 24
Peak memory 160816 kb
Host smart-f49d5528-6bfd-4cc6-95f3-9825a4706a69
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1986423329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1986423329
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.4113580512
Short name T160
Test name
Test status
Simulation time 336396250000 ps
CPU time 782.88 seconds
Started Jun 24 05:17:17 PM PDT 24
Finished Jun 24 05:49:21 PM PDT 24
Peak memory 160820 kb
Host smart-febf2b2f-ef30-437e-a5ee-913d4b56f70c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4113580512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.4113580512
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2899326142
Short name T147
Test name
Test status
Simulation time 336751370000 ps
CPU time 856.1 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:51:44 PM PDT 24
Peak memory 160784 kb
Host smart-0ecaee98-1c8d-43a1-a96b-d6bace3a20cc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2899326142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2899326142
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.3661146212
Short name T137
Test name
Test status
Simulation time 336609090000 ps
CPU time 677.09 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:45:03 PM PDT 24
Peak memory 160816 kb
Host smart-60acb2d0-fe28-43fd-823e-08489c9cffeb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3661146212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.3661146212
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.261354007
Short name T141
Test name
Test status
Simulation time 336342210000 ps
CPU time 799.71 seconds
Started Jun 24 05:17:16 PM PDT 24
Finished Jun 24 05:49:59 PM PDT 24
Peak memory 160812 kb
Host smart-23010cef-5533-4e22-a3da-972e7962404b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=261354007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.261354007
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3535619108
Short name T151
Test name
Test status
Simulation time 336647450000 ps
CPU time 797.66 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:50:00 PM PDT 24
Peak memory 160820 kb
Host smart-7d830e19-51c7-4229-8055-2a7209bb41e7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3535619108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3535619108
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.620019348
Short name T152
Test name
Test status
Simulation time 337152430000 ps
CPU time 741.01 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:48:24 PM PDT 24
Peak memory 160728 kb
Host smart-1830bc22-ff31-4ee9-9b2c-819d2e526189
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=620019348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.620019348
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2160195320
Short name T20
Test name
Test status
Simulation time 336931570000 ps
CPU time 702.27 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:46:05 PM PDT 24
Peak memory 160772 kb
Host smart-047bbdc2-1b69-414e-b9e8-cbd717f54c53
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2160195320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2160195320
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3413723226
Short name T124
Test name
Test status
Simulation time 336972030000 ps
CPU time 916.62 seconds
Started Jun 24 05:17:12 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 160736 kb
Host smart-a93df202-e09d-426d-adaf-9d15e9aba5da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3413723226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3413723226
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1241424557
Short name T21
Test name
Test status
Simulation time 336674790000 ps
CPU time 859.81 seconds
Started Jun 24 05:17:26 PM PDT 24
Finished Jun 24 05:52:59 PM PDT 24
Peak memory 160816 kb
Host smart-80e55d44-98ec-4040-b9d3-50e09c7afd4b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1241424557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1241424557
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2275225874
Short name T123
Test name
Test status
Simulation time 336380590000 ps
CPU time 782 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:49:09 PM PDT 24
Peak memory 160816 kb
Host smart-9984c7ea-2f35-43b9-9428-fb7a7b8eae33
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2275225874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2275225874
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1998258926
Short name T136
Test name
Test status
Simulation time 336895770000 ps
CPU time 873.76 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:52:49 PM PDT 24
Peak memory 160816 kb
Host smart-87c7fb03-595b-42b0-b194-ab191d063c41
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1998258926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1998258926
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.167781441
Short name T127
Test name
Test status
Simulation time 336622110000 ps
CPU time 816.3 seconds
Started Jun 24 05:17:19 PM PDT 24
Finished Jun 24 05:50:42 PM PDT 24
Peak memory 160728 kb
Host smart-17b41a85-23f2-43bd-90da-f6f0f08ea06e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=167781441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.167781441
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1880491550
Short name T156
Test name
Test status
Simulation time 336321770000 ps
CPU time 893.37 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:53:29 PM PDT 24
Peak memory 160808 kb
Host smart-91456b27-b9c6-4a56-b56b-712659cbf524
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1880491550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1880491550
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3604966911
Short name T121
Test name
Test status
Simulation time 336768590000 ps
CPU time 716.47 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:46:50 PM PDT 24
Peak memory 160816 kb
Host smart-b6786198-ea81-49ba-afa2-fa8894602411
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3604966911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3604966911
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.572331707
Short name T15
Test name
Test status
Simulation time 336736810000 ps
CPU time 911.21 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:54:04 PM PDT 24
Peak memory 160808 kb
Host smart-6ea2916c-9ae2-4fb9-8883-65c5bd1d9d77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=572331707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.572331707
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2438418007
Short name T159
Test name
Test status
Simulation time 336437250000 ps
CPU time 760.4 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:48:21 PM PDT 24
Peak memory 160744 kb
Host smart-c2c5c470-42c4-4bc2-8be4-995b46251e89
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2438418007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2438418007
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1522611914
Short name T142
Test name
Test status
Simulation time 336839590000 ps
CPU time 852.98 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:52:25 PM PDT 24
Peak memory 160728 kb
Host smart-96adbe4f-5f60-418b-837a-4cf1a121b639
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1522611914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1522611914
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2622927702
Short name T16
Test name
Test status
Simulation time 337110190000 ps
CPU time 914.81 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:55:03 PM PDT 24
Peak memory 160812 kb
Host smart-b3570e01-26d0-4b13-a731-499420409cd0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2622927702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2622927702
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1950225480
Short name T130
Test name
Test status
Simulation time 336668510000 ps
CPU time 775.52 seconds
Started Jun 24 05:17:24 PM PDT 24
Finished Jun 24 05:49:04 PM PDT 24
Peak memory 160704 kb
Host smart-d219f8dd-b7ca-4504-b67c-fab8cba7b011
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1950225480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1950225480
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3941004011
Short name T126
Test name
Test status
Simulation time 337077190000 ps
CPU time 688.17 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:45:43 PM PDT 24
Peak memory 160804 kb
Host smart-0e419950-f979-44aa-9b6d-08de8df8b3c8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3941004011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3941004011
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1833129566
Short name T18
Test name
Test status
Simulation time 336579490000 ps
CPU time 681.72 seconds
Started Jun 24 05:17:20 PM PDT 24
Finished Jun 24 05:45:26 PM PDT 24
Peak memory 160816 kb
Host smart-570c9686-a2c5-4ce6-aedd-df5c9167fe6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1833129566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1833129566
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.1589814149
Short name T146
Test name
Test status
Simulation time 337010950000 ps
CPU time 843.06 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:51:31 PM PDT 24
Peak memory 160816 kb
Host smart-0ef1b892-144e-43eb-98fa-778a90bff1c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1589814149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.1589814149
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2216588944
Short name T150
Test name
Test status
Simulation time 336581850000 ps
CPU time 749.04 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:48:27 PM PDT 24
Peak memory 160820 kb
Host smart-d994215f-2f38-4956-ac45-630e1860146a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2216588944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2216588944
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1353655363
Short name T134
Test name
Test status
Simulation time 336863330000 ps
CPU time 877.74 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:52:54 PM PDT 24
Peak memory 160808 kb
Host smart-7fcd5864-b257-4044-8791-5721becee26a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1353655363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1353655363
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2989965966
Short name T17
Test name
Test status
Simulation time 336646810000 ps
CPU time 870.94 seconds
Started Jun 24 05:17:25 PM PDT 24
Finished Jun 24 05:53:23 PM PDT 24
Peak memory 160816 kb
Host smart-8ba72aca-f81a-4814-a739-73f4effbf3c1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2989965966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2989965966
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.4209404994
Short name T143
Test name
Test status
Simulation time 336383250000 ps
CPU time 771.18 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:48:51 PM PDT 24
Peak memory 160816 kb
Host smart-e2c4e4d3-891d-4d36-859f-364b7123b82c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4209404994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.4209404994
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2765650816
Short name T157
Test name
Test status
Simulation time 336779130000 ps
CPU time 725.55 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:46:59 PM PDT 24
Peak memory 160816 kb
Host smart-a14c3700-d6ab-4a54-bbac-4511600d5c9d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2765650816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2765650816
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.526613246
Short name T149
Test name
Test status
Simulation time 336567610000 ps
CPU time 813.05 seconds
Started Jun 24 05:17:25 PM PDT 24
Finished Jun 24 05:50:14 PM PDT 24
Peak memory 160712 kb
Host smart-34f842c6-495c-40d4-a387-1074f422a3f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=526613246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.526613246
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1397209240
Short name T158
Test name
Test status
Simulation time 336739570000 ps
CPU time 913.96 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 160812 kb
Host smart-d727aed2-791d-446a-bc5f-d590df42ec65
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1397209240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.1397209240
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3590875023
Short name T19
Test name
Test status
Simulation time 336717110000 ps
CPU time 706.6 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:46:36 PM PDT 24
Peak memory 160816 kb
Host smart-1e16a81c-f6ca-4193-8d17-76a159309d5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3590875023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3590875023
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2319863831
Short name T131
Test name
Test status
Simulation time 336646250000 ps
CPU time 917.11 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:54:15 PM PDT 24
Peak memory 160816 kb
Host smart-77c6f221-63e7-4979-a298-d60124a8fa7f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2319863831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2319863831
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2017298084
Short name T138
Test name
Test status
Simulation time 336857950000 ps
CPU time 927.48 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 160736 kb
Host smart-e73b8496-4e0c-4c79-bf39-fa0536b475de
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2017298084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2017298084
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1221384656
Short name T133
Test name
Test status
Simulation time 336576090000 ps
CPU time 808.49 seconds
Started Jun 24 05:17:25 PM PDT 24
Finished Jun 24 05:50:10 PM PDT 24
Peak memory 160720 kb
Host smart-e1bb57b6-1a1b-4cbe-8fbb-5eac3bc6a2c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1221384656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1221384656
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.275090671
Short name T23
Test name
Test status
Simulation time 336985730000 ps
CPU time 799.41 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:49:49 PM PDT 24
Peak memory 160812 kb
Host smart-bf6df820-19d9-4d88-ab2b-2eb49db571d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=275090671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.275090671
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2453280411
Short name T14
Test name
Test status
Simulation time 337093750000 ps
CPU time 771.04 seconds
Started Jun 24 05:17:12 PM PDT 24
Finished Jun 24 05:48:42 PM PDT 24
Peak memory 160812 kb
Host smart-ef1188b6-fbb7-49ca-81d0-574275ded97e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2453280411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2453280411
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3222207780
Short name T135
Test name
Test status
Simulation time 336976470000 ps
CPU time 851.64 seconds
Started Jun 24 05:17:16 PM PDT 24
Finished Jun 24 05:52:19 PM PDT 24
Peak memory 160728 kb
Host smart-6b3d324c-5b86-4913-a739-1f49491464ee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3222207780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3222207780
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3367799157
Short name T144
Test name
Test status
Simulation time 336314070000 ps
CPU time 765.4 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:48:36 PM PDT 24
Peak memory 160808 kb
Host smart-7b900919-7e2a-418d-a4d8-9c5efcb93de9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3367799157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3367799157
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3856646705
Short name T154
Test name
Test status
Simulation time 336795550000 ps
CPU time 770.45 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:48:48 PM PDT 24
Peak memory 160808 kb
Host smart-b4fae514-bb74-4329-8280-3de5fd2a5dec
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3856646705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3856646705
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1854689720
Short name T155
Test name
Test status
Simulation time 336978070000 ps
CPU time 683.74 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:45:31 PM PDT 24
Peak memory 160800 kb
Host smart-aff9984d-834a-423b-85d9-acc91236925c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1854689720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1854689720
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1735703749
Short name T103
Test name
Test status
Simulation time 1520470000 ps
CPU time 6.18 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:20 PM PDT 24
Peak memory 164920 kb
Host smart-f1af3d3d-034b-4125-ae86-3e7205527eb7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1735703749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1735703749
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.914707327
Short name T92
Test name
Test status
Simulation time 1390370000 ps
CPU time 4.69 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:15 PM PDT 24
Peak memory 164792 kb
Host smart-0a1b8559-6f32-4802-bc23-d76ea6131247
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=914707327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.914707327
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.986679786
Short name T116
Test name
Test status
Simulation time 1513430000 ps
CPU time 3.8 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:15 PM PDT 24
Peak memory 164932 kb
Host smart-771a8b22-90bf-4b45-b65f-cc1760fb57b6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=986679786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.986679786
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3056478238
Short name T86
Test name
Test status
Simulation time 1402230000 ps
CPU time 3.79 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:14 PM PDT 24
Peak memory 164904 kb
Host smart-1bb050f5-8924-4ae1-9132-7dc1e06b24ee
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3056478238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3056478238
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1370300477
Short name T82
Test name
Test status
Simulation time 1511850000 ps
CPU time 3.53 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:16 PM PDT 24
Peak memory 164904 kb
Host smart-407c671b-ccf7-4d4f-88a5-a05e06954239
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1370300477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1370300477
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2364991511
Short name T5
Test name
Test status
Simulation time 1395210000 ps
CPU time 4.7 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:15 PM PDT 24
Peak memory 164936 kb
Host smart-3a195d56-e216-4008-8512-f674989d0285
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2364991511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2364991511
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2141174607
Short name T102
Test name
Test status
Simulation time 1448890000 ps
CPU time 4.6 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 164920 kb
Host smart-a0e6aa26-1fa7-4ac9-b19a-620387207c8b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2141174607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2141174607
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3277718543
Short name T115
Test name
Test status
Simulation time 1588530000 ps
CPU time 5.74 seconds
Started Jun 24 05:17:08 PM PDT 24
Finished Jun 24 05:17:21 PM PDT 24
Peak memory 164932 kb
Host smart-af66c3c7-3dbd-4d59-9b44-256548de31c0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3277718543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3277718543
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1162216194
Short name T111
Test name
Test status
Simulation time 1259910000 ps
CPU time 3.98 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:15 PM PDT 24
Peak memory 164920 kb
Host smart-ea792f3c-3e85-41a0-9ce5-588daf6b97e6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1162216194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1162216194
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1501689748
Short name T105
Test name
Test status
Simulation time 1363770000 ps
CPU time 4.77 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:19 PM PDT 24
Peak memory 164836 kb
Host smart-40100474-2bc2-45d4-b638-20b94f45277b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1501689748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1501689748
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3081886427
Short name T91
Test name
Test status
Simulation time 1334130000 ps
CPU time 6.3 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:18 PM PDT 24
Peak memory 164864 kb
Host smart-59ee2090-b8b4-4501-bb17-f47365edc599
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3081886427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3081886427
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3291403431
Short name T27
Test name
Test status
Simulation time 1409010000 ps
CPU time 4.56 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 164932 kb
Host smart-410a5d13-9e48-45d6-83e4-750389f28f19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3291403431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3291403431
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.917695393
Short name T118
Test name
Test status
Simulation time 1305690000 ps
CPU time 4.36 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:16 PM PDT 24
Peak memory 164452 kb
Host smart-ff2de15d-5ce8-4b33-96ea-a8dcfb020000
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917695393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.917695393
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3528758585
Short name T88
Test name
Test status
Simulation time 1300630000 ps
CPU time 3.89 seconds
Started Jun 24 05:17:03 PM PDT 24
Finished Jun 24 05:17:13 PM PDT 24
Peak memory 164920 kb
Host smart-3b859f88-13ca-4194-a93b-cdda7b405903
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3528758585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3528758585
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.762668934
Short name T99
Test name
Test status
Simulation time 1521670000 ps
CPU time 5.83 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:19 PM PDT 24
Peak memory 164916 kb
Host smart-551bfd14-4584-44fe-aea2-e857f69f1941
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=762668934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.762668934
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.601574227
Short name T6
Test name
Test status
Simulation time 1421530000 ps
CPU time 3.59 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:14 PM PDT 24
Peak memory 164860 kb
Host smart-f15296b9-574c-4340-9c97-46ddef12523a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601574227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.601574227
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1367196306
Short name T100
Test name
Test status
Simulation time 1513130000 ps
CPU time 5.78 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:20 PM PDT 24
Peak memory 164920 kb
Host smart-c0e577b3-a9bf-4857-adb9-aeb412feab85
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1367196306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1367196306
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1944314467
Short name T96
Test name
Test status
Simulation time 1513450000 ps
CPU time 3.33 seconds
Started Jun 24 05:17:02 PM PDT 24
Finished Jun 24 05:17:10 PM PDT 24
Peak memory 164904 kb
Host smart-b2a92760-2817-4e81-b08c-b8600012e430
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1944314467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1944314467
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4294253729
Short name T89
Test name
Test status
Simulation time 1587450000 ps
CPU time 4.38 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:16 PM PDT 24
Peak memory 164864 kb
Host smart-3caa8b28-f302-429d-b220-a37d64fccd7d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4294253729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4294253729
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3226985073
Short name T94
Test name
Test status
Simulation time 1453470000 ps
CPU time 4.67 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 164520 kb
Host smart-49c4803a-e77e-4f13-b390-933619c047e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226985073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3226985073
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.290802826
Short name T109
Test name
Test status
Simulation time 1268990000 ps
CPU time 4.33 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:15 PM PDT 24
Peak memory 164928 kb
Host smart-eae38828-b95b-4421-a681-0d7156c12c0d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=290802826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.290802826
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.514472739
Short name T95
Test name
Test status
Simulation time 1531950000 ps
CPU time 4.92 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:16 PM PDT 24
Peak memory 164924 kb
Host smart-1dc98fc1-97b7-445e-8542-b389c6e1987c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=514472739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.514472739
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1894210461
Short name T84
Test name
Test status
Simulation time 1218810000 ps
CPU time 4.73 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 164864 kb
Host smart-9f0c7cf0-239a-4e77-b8cc-ca241b5e2f63
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1894210461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1894210461
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.45785604
Short name T107
Test name
Test status
Simulation time 1274110000 ps
CPU time 5.5 seconds
Started Jun 24 05:17:03 PM PDT 24
Finished Jun 24 05:17:16 PM PDT 24
Peak memory 164848 kb
Host smart-f8111b28-92b8-49de-a9e7-d5945dd01c3f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=45785604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.45785604
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3411269619
Short name T28
Test name
Test status
Simulation time 1527850000 ps
CPU time 5.85 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:21 PM PDT 24
Peak memory 164932 kb
Host smart-9a3df11e-b0c0-42ef-b040-979bd96487fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3411269619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3411269619
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2417636872
Short name T85
Test name
Test status
Simulation time 1512490000 ps
CPU time 5.63 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 164920 kb
Host smart-0dc027ed-08e3-4da5-a4c8-25dbc307cb34
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417636872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2417636872
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.781538603
Short name T104
Test name
Test status
Simulation time 1354870000 ps
CPU time 4.4 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 164916 kb
Host smart-92fb7de9-3c08-43b0-a6fc-c0c677baff7b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=781538603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.781538603
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1569600787
Short name T29
Test name
Test status
Simulation time 1437390000 ps
CPU time 4.25 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:16 PM PDT 24
Peak memory 164936 kb
Host smart-6bc6735c-b021-438c-bc7e-7524f06013ae
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1569600787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1569600787
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2955969966
Short name T81
Test name
Test status
Simulation time 1557010000 ps
CPU time 6.6 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:17:28 PM PDT 24
Peak memory 164848 kb
Host smart-7f2aba9d-5313-464a-b237-861cd6a33906
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2955969966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2955969966
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2404600947
Short name T26
Test name
Test status
Simulation time 1381570000 ps
CPU time 3.45 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:17:21 PM PDT 24
Peak memory 164920 kb
Host smart-2af18305-d9aa-4ea5-82a5-88ad5dba3891
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2404600947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2404600947
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3977177856
Short name T117
Test name
Test status
Simulation time 1278550000 ps
CPU time 4.41 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:17:24 PM PDT 24
Peak memory 164980 kb
Host smart-ab3b56db-89d3-498b-865b-395165d11dd4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977177856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3977177856
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2572286187
Short name T30
Test name
Test status
Simulation time 1381910000 ps
CPU time 4.57 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:17:24 PM PDT 24
Peak memory 164904 kb
Host smart-0169cc14-211c-4a4b-9e68-52ba3d18df76
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2572286187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2572286187
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2967134218
Short name T113
Test name
Test status
Simulation time 1035790000 ps
CPU time 4.21 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:17:24 PM PDT 24
Peak memory 164864 kb
Host smart-8768102d-35cb-45e9-bb50-35b2239c8f3a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2967134218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2967134218
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2540148703
Short name T110
Test name
Test status
Simulation time 1523070000 ps
CPU time 4.6 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:18 PM PDT 24
Peak memory 164956 kb
Host smart-b3631f4f-97ed-45dd-b3a7-496a54c799fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2540148703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2540148703
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.815702982
Short name T119
Test name
Test status
Simulation time 1165110000 ps
CPU time 4.09 seconds
Started Jun 24 05:17:13 PM PDT 24
Finished Jun 24 05:17:23 PM PDT 24
Peak memory 164916 kb
Host smart-bbea79f3-5deb-4656-80b2-19113fe6e845
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=815702982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.815702982
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3374134683
Short name T114
Test name
Test status
Simulation time 1183470000 ps
CPU time 3.67 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:17:25 PM PDT 24
Peak memory 164940 kb
Host smart-05500e92-509c-473c-ac5a-f20663a92c3e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3374134683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3374134683
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1085329893
Short name T106
Test name
Test status
Simulation time 1204390000 ps
CPU time 4.02 seconds
Started Jun 24 05:17:17 PM PDT 24
Finished Jun 24 05:17:27 PM PDT 24
Peak memory 164864 kb
Host smart-ac67eb69-9483-4725-99ae-bfc0ff7ab686
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085329893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1085329893
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.752946186
Short name T120
Test name
Test status
Simulation time 1409710000 ps
CPU time 3.8 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:17:26 PM PDT 24
Peak memory 164952 kb
Host smart-9feef869-e4d8-496e-b86c-ed6e5627c3f4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=752946186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.752946186
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1711606236
Short name T93
Test name
Test status
Simulation time 1529310000 ps
CPU time 5.24 seconds
Started Jun 24 05:17:15 PM PDT 24
Finished Jun 24 05:17:29 PM PDT 24
Peak memory 164864 kb
Host smart-0b4b4a22-ee27-4fb7-beda-342764eb0400
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1711606236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1711606236
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1980736244
Short name T4
Test name
Test status
Simulation time 1346310000 ps
CPU time 4.67 seconds
Started Jun 24 05:17:12 PM PDT 24
Finished Jun 24 05:17:23 PM PDT 24
Peak memory 164832 kb
Host smart-c9ed4c74-9365-47d5-b335-b01bb5468fd3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980736244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1980736244
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.714124720
Short name T108
Test name
Test status
Simulation time 1145390000 ps
CPU time 3.49 seconds
Started Jun 24 05:17:17 PM PDT 24
Finished Jun 24 05:17:26 PM PDT 24
Peak memory 164916 kb
Host smart-1f422f0b-22ec-45a3-a3c3-151cd60bb2fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=714124720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.714124720
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.386607909
Short name T24
Test name
Test status
Simulation time 1218730000 ps
CPU time 4.25 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:17:24 PM PDT 24
Peak memory 164928 kb
Host smart-5b678501-bf3f-4c00-a38c-b93ae8d0bc29
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=386607909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.386607909
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2176857660
Short name T97
Test name
Test status
Simulation time 1523890000 ps
CPU time 4.22 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:17:25 PM PDT 24
Peak memory 164920 kb
Host smart-7ab437c7-6c49-43ec-8f25-7cb118aff0a4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2176857660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2176857660
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1719816990
Short name T90
Test name
Test status
Simulation time 1387150000 ps
CPU time 4.25 seconds
Started Jun 24 05:17:14 PM PDT 24
Finished Jun 24 05:17:24 PM PDT 24
Peak memory 164880 kb
Host smart-77fef827-f551-497e-9366-44a8cec0722d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1719816990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1719816990
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1857530047
Short name T98
Test name
Test status
Simulation time 1364610000 ps
CPU time 5.19 seconds
Started Jun 24 05:17:05 PM PDT 24
Finished Jun 24 05:17:18 PM PDT 24
Peak memory 164864 kb
Host smart-f94847ce-3a9b-42f7-ba3c-7b742dbcd6df
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857530047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1857530047
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.58449901
Short name T83
Test name
Test status
Simulation time 1461170000 ps
CPU time 4.56 seconds
Started Jun 24 05:17:04 PM PDT 24
Finished Jun 24 05:17:15 PM PDT 24
Peak memory 164788 kb
Host smart-28f263ae-bcf9-4f28-9fa2-4ebcf88b8cdf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58449901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.58449901
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.4178450487
Short name T101
Test name
Test status
Simulation time 1494090000 ps
CPU time 4.74 seconds
Started Jun 24 05:17:06 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 165040 kb
Host smart-11687840-97dc-401a-a8b8-f4c158372880
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4178450487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.4178450487
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.645640702
Short name T87
Test name
Test status
Simulation time 1369170000 ps
CPU time 3.94 seconds
Started Jun 24 05:17:03 PM PDT 24
Finished Jun 24 05:17:13 PM PDT 24
Peak memory 164856 kb
Host smart-f13d2b82-0015-4e82-a4dc-298261785f5a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=645640702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.645640702
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.532952895
Short name T112
Test name
Test status
Simulation time 1543750000 ps
CPU time 5.06 seconds
Started Jun 24 05:17:07 PM PDT 24
Finished Jun 24 05:17:19 PM PDT 24
Peak memory 164760 kb
Host smart-5576250f-707c-403d-9617-a4ab3afab761
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=532952895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.532952895
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2339317737
Short name T54
Test name
Test status
Simulation time 1624770000 ps
CPU time 4 seconds
Started Jun 24 05:15:08 PM PDT 24
Finished Jun 24 05:15:18 PM PDT 24
Peak memory 164948 kb
Host smart-88f6980b-1883-46f6-83e3-feff632ee5d4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2339317737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2339317737
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.2841544792
Short name T71
Test name
Test status
Simulation time 1334730000 ps
CPU time 5.94 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:23 PM PDT 24
Peak memory 164920 kb
Host smart-f629f7c7-82f4-4acf-819b-eedb5f9747d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2841544792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.2841544792
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.669708141
Short name T74
Test name
Test status
Simulation time 1362370000 ps
CPU time 4.71 seconds
Started Jun 24 05:15:11 PM PDT 24
Finished Jun 24 05:15:22 PM PDT 24
Peak memory 164916 kb
Host smart-3f75d696-4b5c-411e-9ed0-c91748e3d633
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=669708141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.669708141
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2997579287
Short name T46
Test name
Test status
Simulation time 1406230000 ps
CPU time 4.72 seconds
Started Jun 24 05:15:10 PM PDT 24
Finished Jun 24 05:15:21 PM PDT 24
Peak memory 164920 kb
Host smart-54a4c259-3cd0-4692-9278-6097033b8462
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997579287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2997579287
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3781627300
Short name T47
Test name
Test status
Simulation time 1559990000 ps
CPU time 4.86 seconds
Started Jun 24 05:15:08 PM PDT 24
Finished Jun 24 05:15:20 PM PDT 24
Peak memory 164864 kb
Host smart-d02688ee-ba7f-4e97-92bc-50dfb5080f0c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3781627300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3781627300
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.775352359
Short name T65
Test name
Test status
Simulation time 1397010000 ps
CPU time 3.1 seconds
Started Jun 24 05:15:10 PM PDT 24
Finished Jun 24 05:15:18 PM PDT 24
Peak memory 164916 kb
Host smart-b236dfc1-e7c3-4405-bf97-92b173f9f9d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=775352359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.775352359
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.982512315
Short name T50
Test name
Test status
Simulation time 1357610000 ps
CPU time 3.24 seconds
Started Jun 24 05:15:08 PM PDT 24
Finished Jun 24 05:15:17 PM PDT 24
Peak memory 164952 kb
Host smart-0d693876-f001-44e1-aab8-c7cd066124c9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982512315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.982512315
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3015531332
Short name T8
Test name
Test status
Simulation time 1263730000 ps
CPU time 4.01 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:18 PM PDT 24
Peak memory 164900 kb
Host smart-90fbc32d-153c-4bca-a177-ce8168522797
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3015531332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3015531332
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1662186035
Short name T11
Test name
Test status
Simulation time 1459310000 ps
CPU time 5.18 seconds
Started Jun 24 05:15:08 PM PDT 24
Finished Jun 24 05:15:21 PM PDT 24
Peak memory 164940 kb
Host smart-ff214692-cead-426e-a49b-0c9d855e217c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1662186035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1662186035
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.4011780170
Short name T41
Test name
Test status
Simulation time 1459050000 ps
CPU time 5.42 seconds
Started Jun 24 05:15:12 PM PDT 24
Finished Jun 24 05:15:25 PM PDT 24
Peak memory 164980 kb
Host smart-859f18a8-3e60-4cdb-92c2-ae7cd0643bf6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4011780170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.4011780170
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3303644975
Short name T78
Test name
Test status
Simulation time 1440030000 ps
CPU time 3.25 seconds
Started Jun 24 05:15:10 PM PDT 24
Finished Jun 24 05:15:18 PM PDT 24
Peak memory 164920 kb
Host smart-f193afbe-5fb8-40c6-b451-30b46d7c5264
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3303644975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3303644975
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1083224819
Short name T57
Test name
Test status
Simulation time 1444050000 ps
CPU time 4.76 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:20 PM PDT 24
Peak memory 164864 kb
Host smart-db40e552-8029-4bf7-b909-0a8313c8a7db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1083224819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1083224819
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4205604562
Short name T70
Test name
Test status
Simulation time 1108410000 ps
CPU time 4.33 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:19 PM PDT 24
Peak memory 164920 kb
Host smart-049fe2dc-1f47-4b57-82c8-d721d6c4cc12
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205604562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4205604562
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.537396514
Short name T80
Test name
Test status
Simulation time 1533790000 ps
CPU time 4.7 seconds
Started Jun 24 05:15:11 PM PDT 24
Finished Jun 24 05:15:22 PM PDT 24
Peak memory 164932 kb
Host smart-3b415612-648d-476a-a25d-6b92ee3b4aa8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=537396514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.537396514
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2570668880
Short name T56
Test name
Test status
Simulation time 1516570000 ps
CPU time 4.32 seconds
Started Jun 24 05:15:17 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164916 kb
Host smart-673ae1a4-43fc-428b-a4bd-bfb3c416df9d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570668880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2570668880
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2087192919
Short name T60
Test name
Test status
Simulation time 1491650000 ps
CPU time 4.65 seconds
Started Jun 24 05:15:19 PM PDT 24
Finished Jun 24 05:15:30 PM PDT 24
Peak memory 164980 kb
Host smart-ea6bfad2-88bb-46c7-9648-25237937b289
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087192919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2087192919
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3067288009
Short name T51
Test name
Test status
Simulation time 1637990000 ps
CPU time 4.9 seconds
Started Jun 24 05:15:18 PM PDT 24
Finished Jun 24 05:15:30 PM PDT 24
Peak memory 164936 kb
Host smart-4e6df43a-5403-4511-af71-485b890eb9cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3067288009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3067288009
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.833838392
Short name T52
Test name
Test status
Simulation time 1579230000 ps
CPU time 4.68 seconds
Started Jun 24 05:15:18 PM PDT 24
Finished Jun 24 05:15:30 PM PDT 24
Peak memory 164920 kb
Host smart-9f3d24ee-92a4-4861-9691-280a6ee5f977
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=833838392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.833838392
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1405606783
Short name T64
Test name
Test status
Simulation time 1521870000 ps
CPU time 4.02 seconds
Started Jun 24 05:15:20 PM PDT 24
Finished Jun 24 05:15:29 PM PDT 24
Peak memory 164916 kb
Host smart-3cccaf2c-8209-4e58-ac89-b136aee82a26
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1405606783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1405606783
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2500794872
Short name T68
Test name
Test status
Simulation time 1040730000 ps
CPU time 4.4 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:26 PM PDT 24
Peak memory 164932 kb
Host smart-510b0795-8167-4c53-aff2-914ce8ef98d1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2500794872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2500794872
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.965724898
Short name T10
Test name
Test status
Simulation time 1544830000 ps
CPU time 4.43 seconds
Started Jun 24 05:15:17 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164860 kb
Host smart-baeb7e8c-cec6-4983-8a33-e44a14431dae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=965724898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.965724898
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.304199420
Short name T77
Test name
Test status
Simulation time 1571210000 ps
CPU time 3.39 seconds
Started Jun 24 05:15:14 PM PDT 24
Finished Jun 24 05:15:22 PM PDT 24
Peak memory 164876 kb
Host smart-a6886c69-66a7-469c-bd3e-b2eedb391713
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=304199420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.304199420
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.4202594775
Short name T79
Test name
Test status
Simulation time 1627050000 ps
CPU time 5.92 seconds
Started Jun 24 05:15:13 PM PDT 24
Finished Jun 24 05:15:27 PM PDT 24
Peak memory 165040 kb
Host smart-620684ee-9444-41f5-a97f-7029361c1bda
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4202594775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.4202594775
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.601255759
Short name T1
Test name
Test status
Simulation time 1347170000 ps
CPU time 3.05 seconds
Started Jun 24 05:15:18 PM PDT 24
Finished Jun 24 05:15:26 PM PDT 24
Peak memory 164972 kb
Host smart-2415b9ae-0d15-42e0-9a78-2ef0671314cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=601255759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.601255759
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1352326298
Short name T48
Test name
Test status
Simulation time 1315870000 ps
CPU time 3.83 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:25 PM PDT 24
Peak memory 164836 kb
Host smart-f3325cb6-698d-458e-898e-5c4a1dcbdf38
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1352326298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1352326298
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1109764439
Short name T44
Test name
Test status
Simulation time 1364670000 ps
CPU time 4.21 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:27 PM PDT 24
Peak memory 164884 kb
Host smart-326f349e-1060-4d8f-9514-0febee32d95d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109764439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1109764439
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2065238661
Short name T62
Test name
Test status
Simulation time 1431070000 ps
CPU time 5.1 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164920 kb
Host smart-2c712fd9-1cc4-43bf-a9c0-119ffc9259c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2065238661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2065238661
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3538740100
Short name T3
Test name
Test status
Simulation time 1411430000 ps
CPU time 3.71 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:25 PM PDT 24
Peak memory 164832 kb
Host smart-3501405f-a9b0-4e7b-9a00-7b54e7ffe583
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3538740100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3538740100
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2049560340
Short name T59
Test name
Test status
Simulation time 1516770000 ps
CPU time 5.94 seconds
Started Jun 24 05:15:15 PM PDT 24
Finished Jun 24 05:15:29 PM PDT 24
Peak memory 164916 kb
Host smart-627f9190-f477-48dc-8bdc-38dd449e1024
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2049560340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2049560340
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2372310842
Short name T53
Test name
Test status
Simulation time 1515610000 ps
CPU time 5.73 seconds
Started Jun 24 05:15:15 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164948 kb
Host smart-6c748093-db9b-4139-b0b6-7806163704db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372310842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2372310842
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2838488782
Short name T67
Test name
Test status
Simulation time 1565610000 ps
CPU time 4.89 seconds
Started Jun 24 05:15:14 PM PDT 24
Finished Jun 24 05:15:26 PM PDT 24
Peak memory 164968 kb
Host smart-c3c993bc-cce0-4e60-878a-f1b5c65a283b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2838488782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2838488782
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.259050663
Short name T43
Test name
Test status
Simulation time 1451050000 ps
CPU time 4.06 seconds
Started Jun 24 05:15:18 PM PDT 24
Finished Jun 24 05:15:27 PM PDT 24
Peak memory 164816 kb
Host smart-7a8317df-cd1c-40c2-a196-2473539b427b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=259050663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.259050663
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1476790558
Short name T63
Test name
Test status
Simulation time 1652410000 ps
CPU time 5.07 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164928 kb
Host smart-a7749138-2224-476a-b73b-bc9f46528677
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1476790558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1476790558
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.487583375
Short name T58
Test name
Test status
Simulation time 1532270000 ps
CPU time 4.19 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:20 PM PDT 24
Peak memory 164852 kb
Host smart-4e4ff790-7c6d-4426-9cf8-915367ad71ec
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487583375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.487583375
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3690427187
Short name T69
Test name
Test status
Simulation time 1371650000 ps
CPU time 4.8 seconds
Started Jun 24 05:15:17 PM PDT 24
Finished Jun 24 05:15:29 PM PDT 24
Peak memory 164920 kb
Host smart-1fc70e7f-4d3e-4a02-9738-4213179f520c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3690427187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3690427187
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1003214367
Short name T73
Test name
Test status
Simulation time 1327370000 ps
CPU time 5.06 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164864 kb
Host smart-abdc2ffe-4c58-4e5f-9896-ffd5c7f85b2b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1003214367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1003214367
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.184449379
Short name T72
Test name
Test status
Simulation time 1474550000 ps
CPU time 4.42 seconds
Started Jun 24 05:15:17 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164832 kb
Host smart-4904c92c-cf8d-49f4-825d-bae3236eb65d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=184449379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.184449379
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3379399058
Short name T2
Test name
Test status
Simulation time 1525310000 ps
CPU time 4.91 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:28 PM PDT 24
Peak memory 164948 kb
Host smart-99e03183-0e10-4c9a-8f1d-33b09d03d2c8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3379399058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3379399058
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.397414581
Short name T55
Test name
Test status
Simulation time 1504210000 ps
CPU time 4.39 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:27 PM PDT 24
Peak memory 164800 kb
Host smart-01575000-1ae7-4973-bf20-522437838439
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=397414581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.397414581
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2554424711
Short name T76
Test name
Test status
Simulation time 1543150000 ps
CPU time 5.82 seconds
Started Jun 24 05:15:16 PM PDT 24
Finished Jun 24 05:15:30 PM PDT 24
Peak memory 164936 kb
Host smart-56da98ca-5995-4a4b-a35b-f474c6050590
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2554424711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2554424711
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3148908035
Short name T75
Test name
Test status
Simulation time 1562810000 ps
CPU time 4.4 seconds
Started Jun 24 05:15:14 PM PDT 24
Finished Jun 24 05:15:24 PM PDT 24
Peak memory 164936 kb
Host smart-cb1cf976-f5be-4353-814c-59dee1aa83df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3148908035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3148908035
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.2252297725
Short name T13
Test name
Test status
Simulation time 1468090000 ps
CPU time 3.71 seconds
Started Jun 24 05:15:17 PM PDT 24
Finished Jun 24 05:15:26 PM PDT 24
Peak memory 164832 kb
Host smart-d41f1f83-33b3-4720-a31e-3d8554e68e96
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252297725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.2252297725
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.300183715
Short name T12
Test name
Test status
Simulation time 1572130000 ps
CPU time 5.51 seconds
Started Jun 24 05:15:18 PM PDT 24
Finished Jun 24 05:15:31 PM PDT 24
Peak memory 164916 kb
Host smart-fd43a352-9691-4a0f-8012-1b4ba6dc1475
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300183715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.300183715
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1538597005
Short name T49
Test name
Test status
Simulation time 1408930000 ps
CPU time 5.14 seconds
Started Jun 24 05:15:19 PM PDT 24
Finished Jun 24 05:15:31 PM PDT 24
Peak memory 164920 kb
Host smart-762e86f3-4f61-445f-96f6-f8ce44b6e4ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1538597005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1538597005
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3435562661
Short name T45
Test name
Test status
Simulation time 1527050000 ps
CPU time 5.94 seconds
Started Jun 24 05:15:08 PM PDT 24
Finished Jun 24 05:15:21 PM PDT 24
Peak memory 164916 kb
Host smart-4cc838f7-e8ce-4850-bb4d-eaf0d5ef2c36
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3435562661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3435562661
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.3787005529
Short name T9
Test name
Test status
Simulation time 1384350000 ps
CPU time 3.23 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:17 PM PDT 24
Peak memory 164880 kb
Host smart-b465f9d4-0ff3-4861-8d41-625f3b1ccb98
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3787005529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.3787005529
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.275752716
Short name T66
Test name
Test status
Simulation time 1425750000 ps
CPU time 4.14 seconds
Started Jun 24 05:15:08 PM PDT 24
Finished Jun 24 05:15:19 PM PDT 24
Peak memory 164820 kb
Host smart-c02298a6-8e71-4150-a270-a6088b6a5264
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275752716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.275752716
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.730828799
Short name T61
Test name
Test status
Simulation time 1547350000 ps
CPU time 5.08 seconds
Started Jun 24 05:15:11 PM PDT 24
Finished Jun 24 05:15:23 PM PDT 24
Peak memory 164860 kb
Host smart-0d8c7abe-b289-4cc9-b5c2-539e176e22d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=730828799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.730828799
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1188614254
Short name T42
Test name
Test status
Simulation time 1418010000 ps
CPU time 4.67 seconds
Started Jun 24 05:15:09 PM PDT 24
Finished Jun 24 05:15:20 PM PDT 24
Peak memory 164880 kb
Host smart-4c70466e-ff13-4122-ae65-9883274471fc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188614254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1188614254
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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