| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1552200969 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1163847953 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3989746524 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1996624997 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3713215259 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3283777553 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1783641972 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3396109343 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3687546537 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1459667456 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2137303356 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2731819294 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2449163132 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1092952872 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3918605773 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4011059013 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2101268795 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2887135239 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.37319531 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2320815359 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1842922278 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.5603847 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.788456629 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.828046057 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.156247230 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2702293446 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2876190128 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1861444597 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2169242878 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1841213527 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.820333023 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.219792117 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1147721471 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3469255757 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.244868588 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3947891614 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2184617600 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2451190572 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2350432622 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4178988261 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.842813535 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2583968059 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.522139682 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2366722147 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1057379953 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1464916390 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2262087082 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2546385694 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1011131275 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.651053847 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1121344685 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3755740441 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1383413141 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2092173705 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3988350009 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2543052679 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4154332310 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3422150874 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1328015981 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4130952768 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3699618715 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1853781427 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2392573976 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3436478019 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.47950480 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2230710499 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2897740126 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1151005671 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.702130180 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3719233157 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3139402040 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2688069155 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2425039242 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4243179189 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3606881123 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1461658971 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2858132394 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.686230097 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.876378932 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.959211426 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1874850793 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.834017689 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2877775243 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4282874156 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.465226477 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2327199283 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2960329867 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4251086580 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1621328578 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.303075785 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3844844936 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3165078144 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2924584664 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2285885689 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2523183408 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1913396830 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4112535789 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2809138098 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3461985147 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3856934512 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.969723360 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3188895972 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2837823193 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1052177184 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.998875330 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.26557738 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3687208701 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2272836628 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2249026065 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1199861196 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3886311584 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1106819944 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2127951274 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1169869368 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1081587461 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4164288112 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.73778726 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2347065085 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.750760004 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1823988018 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2293202408 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4059481335 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2063943426 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3078568440 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2656912431 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3254662681 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2877210942 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2536099478 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.257548952 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3645065968 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2268651198 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1806103823 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1048537872 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.938524601 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1378830278 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1619844857 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1490792043 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2052047135 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3857076846 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2464623223 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.722972253 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1670215553 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2175854384 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4128263161 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.32277930 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3271055283 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.427460216 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2156330861 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3181564469 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.464152601 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1642636451 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3275327421 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1101039253 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1238549635 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3816800916 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1806300972 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.420101591 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1412570915 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3284694226 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3461943393 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.509522812 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2592018492 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3875408959 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.588660400 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3328426582 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3078834294 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3243323324 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1654156610 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3370684112 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2279230064 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3450295209 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1486438397 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4204694236 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.325901253 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.761098413 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3597413519 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1653261738 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3211248426 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.299410625 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1791420526 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.490641540 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2804332932 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1179074456 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2236904340 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.585535810 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2136567238 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.961354405 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2235773960 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.410534086 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.832587944 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3834761944 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3881096445 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.978146675 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.618402688 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1886303698 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2608132684 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2995063252 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1695610147 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2031361480 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.813935922 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2608132684 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1446390000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1179074456 | Jun 25 04:42:12 PM PDT 24 | Jun 25 04:42:24 PM PDT 24 | 1476550000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1238549635 | Jun 25 04:42:05 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 1595310000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3816800916 | Jun 25 04:42:08 PM PDT 24 | Jun 25 04:42:22 PM PDT 24 | 1534170000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2995063252 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1539410000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.978146675 | Jun 25 04:42:08 PM PDT 24 | Jun 25 04:42:20 PM PDT 24 | 1341490000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.299410625 | Jun 25 04:42:12 PM PDT 24 | Jun 25 04:42:24 PM PDT 24 | 1505770000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1552200969 | Jun 25 04:42:41 PM PDT 24 | Jun 25 04:42:50 PM PDT 24 | 1507090000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3211248426 | Jun 25 04:42:09 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 1375130000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3450295209 | Jun 25 04:42:05 PM PDT 24 | Jun 25 04:42:17 PM PDT 24 | 1495330000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3284694226 | Jun 25 04:42:07 PM PDT 24 | Jun 25 04:42:18 PM PDT 24 | 1327110000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1695610147 | Jun 25 04:42:03 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1549370000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.961354405 | Jun 25 04:42:10 PM PDT 24 | Jun 25 04:42:22 PM PDT 24 | 1544910000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3243323324 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:17 PM PDT 24 | 1502610000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1101039253 | Jun 25 04:42:18 PM PDT 24 | Jun 25 04:42:32 PM PDT 24 | 1465290000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1806300972 | Jun 25 04:42:07 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 1463390000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1654156610 | Jun 25 04:42:03 PM PDT 24 | Jun 25 04:42:13 PM PDT 24 | 1497190000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3834761944 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:16 PM PDT 24 | 1513870000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3370684112 | Jun 25 04:42:18 PM PDT 24 | Jun 25 04:42:32 PM PDT 24 | 1580210000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.509522812 | Jun 25 04:42:10 PM PDT 24 | Jun 25 04:42:20 PM PDT 24 | 1498210000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1886303698 | Jun 25 04:42:27 PM PDT 24 | Jun 25 04:42:37 PM PDT 24 | 1498570000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.325901253 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1656930000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2279230064 | Jun 25 04:42:57 PM PDT 24 | Jun 25 04:43:07 PM PDT 24 | 1428250000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.490641540 | Jun 25 04:42:18 PM PDT 24 | Jun 25 04:42:30 PM PDT 24 | 1335790000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2592018492 | Jun 25 04:42:06 PM PDT 24 | Jun 25 04:42:20 PM PDT 24 | 1570670000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3078834294 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:12 PM PDT 24 | 1483750000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2031361480 | Jun 25 04:42:01 PM PDT 24 | Jun 25 04:42:10 PM PDT 24 | 1392930000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.585535810 | Jun 25 04:41:58 PM PDT 24 | Jun 25 04:42:12 PM PDT 24 | 1601310000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.410534086 | Jun 25 04:42:03 PM PDT 24 | Jun 25 04:42:14 PM PDT 24 | 1452330000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2804332932 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:16 PM PDT 24 | 1582090000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1653261738 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:17 PM PDT 24 | 1443130000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2236904340 | Jun 25 04:42:06 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 1412910000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.420101591 | Jun 25 04:42:06 PM PDT 24 | Jun 25 04:42:20 PM PDT 24 | 1509590000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3881096445 | Jun 25 04:42:07 PM PDT 24 | Jun 25 04:42:18 PM PDT 24 | 1572110000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1791420526 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:16 PM PDT 24 | 1364890000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2136567238 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:14 PM PDT 24 | 1488930000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3275327421 | Jun 25 04:41:58 PM PDT 24 | Jun 25 04:42:13 PM PDT 24 | 1552070000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2235773960 | Jun 25 04:42:05 PM PDT 24 | Jun 25 04:42:19 PM PDT 24 | 1465350000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.832587944 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:14 PM PDT 24 | 1358470000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1486438397 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:16 PM PDT 24 | 1242910000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1412570915 | Jun 25 04:42:06 PM PDT 24 | Jun 25 04:42:18 PM PDT 24 | 1321770000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.813935922 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1443730000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4204694236 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1309710000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.588660400 | Jun 25 04:42:05 PM PDT 24 | Jun 25 04:42:17 PM PDT 24 | 1344550000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3597413519 | Jun 25 04:42:04 PM PDT 24 | Jun 25 04:42:17 PM PDT 24 | 1497010000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.761098413 | Jun 25 04:42:11 PM PDT 24 | Jun 25 04:42:21 PM PDT 24 | 1149590000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3875408959 | Jun 25 04:42:00 PM PDT 24 | Jun 25 04:42:12 PM PDT 24 | 1212910000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3328426582 | Jun 25 04:42:06 PM PDT 24 | Jun 25 04:42:20 PM PDT 24 | 1555770000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3461943393 | Jun 25 04:42:05 PM PDT 24 | Jun 25 04:42:17 PM PDT 24 | 1517890000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.618402688 | Jun 25 04:42:11 PM PDT 24 | Jun 25 04:42:23 PM PDT 24 | 1514970000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.464152601 | Jun 25 04:41:51 PM PDT 24 | Jun 25 04:42:03 PM PDT 24 | 1459310000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1670215553 | Jun 25 04:42:02 PM PDT 24 | Jun 25 04:42:15 PM PDT 24 | 1575090000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1490792043 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:06 PM PDT 24 | 1457770000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.26557738 | Jun 25 04:41:50 PM PDT 24 | Jun 25 04:42:00 PM PDT 24 | 1190530000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3886311584 | Jun 25 04:41:46 PM PDT 24 | Jun 25 04:41:54 PM PDT 24 | 1466110000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1996624997 | Jun 25 04:41:47 PM PDT 24 | Jun 25 04:41:59 PM PDT 24 | 1467890000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1823988018 | Jun 25 04:41:54 PM PDT 24 | Jun 25 04:42:06 PM PDT 24 | 1618990000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2063943426 | Jun 25 04:41:46 PM PDT 24 | Jun 25 04:41:59 PM PDT 24 | 1618050000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2249026065 | Jun 25 04:41:48 PM PDT 24 | Jun 25 04:41:58 PM PDT 24 | 1525710000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1619844857 | Jun 25 04:41:44 PM PDT 24 | Jun 25 04:41:56 PM PDT 24 | 1518930000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.998875330 | Jun 25 04:41:54 PM PDT 24 | Jun 25 04:42:04 PM PDT 24 | 1374670000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3078568440 | Jun 25 04:41:51 PM PDT 24 | Jun 25 04:42:01 PM PDT 24 | 1399910000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1048537872 | Jun 25 04:41:56 PM PDT 24 | Jun 25 04:42:06 PM PDT 24 | 1562290000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1081587461 | Jun 25 04:41:49 PM PDT 24 | Jun 25 04:42:01 PM PDT 24 | 1273890000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2156330861 | Jun 25 04:41:42 PM PDT 24 | Jun 25 04:41:53 PM PDT 24 | 1341430000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1806103823 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:08 PM PDT 24 | 1545050000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2464623223 | Jun 25 04:42:00 PM PDT 24 | Jun 25 04:42:10 PM PDT 24 | 1387550000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2656912431 | Jun 25 04:41:54 PM PDT 24 | Jun 25 04:42:04 PM PDT 24 | 1539410000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.257548952 | Jun 25 04:41:59 PM PDT 24 | Jun 25 04:42:09 PM PDT 24 | 1405970000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4059481335 | Jun 25 04:41:50 PM PDT 24 | Jun 25 04:42:01 PM PDT 24 | 1242190000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2293202408 | Jun 25 04:41:47 PM PDT 24 | Jun 25 04:41:57 PM PDT 24 | 1527630000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1378830278 | Jun 25 04:41:53 PM PDT 24 | Jun 25 04:42:05 PM PDT 24 | 1398910000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2837823193 | Jun 25 04:42:22 PM PDT 24 | Jun 25 04:42:30 PM PDT 24 | 1083470000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4128263161 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:06 PM PDT 24 | 1586250000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3271055283 | Jun 25 04:41:58 PM PDT 24 | Jun 25 04:42:08 PM PDT 24 | 1378170000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3857076846 | Jun 25 04:41:58 PM PDT 24 | Jun 25 04:42:09 PM PDT 24 | 1357310000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2127951274 | Jun 25 04:41:55 PM PDT 24 | Jun 25 04:42:07 PM PDT 24 | 1479570000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4164288112 | Jun 25 04:41:55 PM PDT 24 | Jun 25 04:42:06 PM PDT 24 | 1301850000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1052177184 | Jun 25 04:41:43 PM PDT 24 | Jun 25 04:41:55 PM PDT 24 | 1559530000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2052047135 | Jun 25 04:41:56 PM PDT 24 | Jun 25 04:42:07 PM PDT 24 | 1518790000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.750760004 | Jun 25 04:42:42 PM PDT 24 | Jun 25 04:42:51 PM PDT 24 | 1528670000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3645065968 | Jun 25 04:41:59 PM PDT 24 | Jun 25 04:42:09 PM PDT 24 | 1471610000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2272836628 | Jun 25 04:41:51 PM PDT 24 | Jun 25 04:42:02 PM PDT 24 | 1439250000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.427460216 | Jun 25 04:41:42 PM PDT 24 | Jun 25 04:41:54 PM PDT 24 | 1446370000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.722972253 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:12 PM PDT 24 | 1381310000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2175854384 | Jun 25 04:41:56 PM PDT 24 | Jun 25 04:42:06 PM PDT 24 | 1382330000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1642636451 | Jun 25 04:41:49 PM PDT 24 | Jun 25 04:42:02 PM PDT 24 | 1482130000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3181564469 | Jun 25 04:41:50 PM PDT 24 | Jun 25 04:42:01 PM PDT 24 | 1505510000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2536099478 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:10 PM PDT 24 | 1422890000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3254662681 | Jun 25 04:41:56 PM PDT 24 | Jun 25 04:42:08 PM PDT 24 | 1427210000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2877210942 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:07 PM PDT 24 | 1458890000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2347065085 | Jun 25 04:41:46 PM PDT 24 | Jun 25 04:41:58 PM PDT 24 | 1424810000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.73778726 | Jun 25 04:41:50 PM PDT 24 | Jun 25 04:42:03 PM PDT 24 | 1588050000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.32277930 | Jun 25 04:41:58 PM PDT 24 | Jun 25 04:42:08 PM PDT 24 | 1376550000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.938524601 | Jun 25 04:41:59 PM PDT 24 | Jun 25 04:42:12 PM PDT 24 | 1558170000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1106819944 | Jun 25 04:41:50 PM PDT 24 | Jun 25 04:42:01 PM PDT 24 | 1371130000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3687208701 | Jun 25 04:41:51 PM PDT 24 | Jun 25 04:42:03 PM PDT 24 | 1456030000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2268651198 | Jun 25 04:41:57 PM PDT 24 | Jun 25 04:42:07 PM PDT 24 | 1557710000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1199861196 | Jun 25 04:41:55 PM PDT 24 | Jun 25 04:42:08 PM PDT 24 | 1512610000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1169869368 | Jun 25 04:41:54 PM PDT 24 | Jun 25 04:42:04 PM PDT 24 | 1456910000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1328015981 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:56:00 PM PDT 24 | 336891390000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3436478019 | Jun 25 05:22:27 PM PDT 24 | Jun 25 06:04:35 PM PDT 24 | 337048790000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1163847953 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:56:17 PM PDT 24 | 336558070000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2230710499 | Jun 25 05:22:27 PM PDT 24 | Jun 25 06:04:45 PM PDT 24 | 336962870000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.702130180 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:55:57 PM PDT 24 | 336995350000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.303075785 | Jun 25 05:22:29 PM PDT 24 | Jun 25 05:56:39 PM PDT 24 | 336302550000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.969723360 | Jun 25 05:22:22 PM PDT 24 | Jun 25 05:49:21 PM PDT 24 | 336692390000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1151005671 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:56:25 PM PDT 24 | 336851450000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4130952768 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:56:30 PM PDT 24 | 336538890000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3856934512 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:56:01 PM PDT 24 | 336677570000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2688069155 | Jun 25 05:22:19 PM PDT 24 | Jun 25 06:00:18 PM PDT 24 | 336869830000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1913396830 | Jun 25 05:22:32 PM PDT 24 | Jun 25 06:05:04 PM PDT 24 | 336964750000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.876378932 | Jun 25 05:22:20 PM PDT 24 | Jun 25 06:00:41 PM PDT 24 | 336747270000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3988350009 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:55:22 PM PDT 24 | 336707990000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.47950480 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:56:31 PM PDT 24 | 337123550000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2924584664 | Jun 25 05:22:29 PM PDT 24 | Jun 25 06:00:42 PM PDT 24 | 336376890000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1874850793 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:54:49 PM PDT 24 | 336539850000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4112535789 | Jun 25 05:22:31 PM PDT 24 | Jun 25 05:57:55 PM PDT 24 | 336753870000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4251086580 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:56:04 PM PDT 24 | 336739430000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3719233157 | Jun 25 05:22:22 PM PDT 24 | Jun 25 05:57:00 PM PDT 24 | 336904170000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3139402040 | Jun 25 05:22:27 PM PDT 24 | Jun 25 06:04:29 PM PDT 24 | 336545530000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2092173705 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:54:58 PM PDT 24 | 337032870000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1853781427 | Jun 25 05:22:25 PM PDT 24 | Jun 25 06:03:34 PM PDT 24 | 336807890000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.959211426 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:55:56 PM PDT 24 | 336402530000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2858132394 | Jun 25 05:22:21 PM PDT 24 | Jun 25 06:00:30 PM PDT 24 | 336867450000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2327199283 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:54:48 PM PDT 24 | 336725010000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2877775243 | Jun 25 05:22:25 PM PDT 24 | Jun 25 06:03:44 PM PDT 24 | 336728950000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4154332310 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:53:58 PM PDT 24 | 337001550000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3606881123 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:57:01 PM PDT 24 | 337014930000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.834017689 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:55:14 PM PDT 24 | 336496350000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2960329867 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:57:24 PM PDT 24 | 336739950000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3461985147 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:55:25 PM PDT 24 | 336741090000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3188895972 | Jun 25 05:22:21 PM PDT 24 | Jun 25 06:00:27 PM PDT 24 | 336494390000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1621328578 | Jun 25 05:22:21 PM PDT 24 | Jun 25 05:52:35 PM PDT 24 | 336943370000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3844844936 | Jun 25 05:22:28 PM PDT 24 | Jun 25 05:56:39 PM PDT 24 | 336553990000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3422150874 | Jun 25 05:22:18 PM PDT 24 | Jun 25 05:52:09 PM PDT 24 | 336552630000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2285885689 | Jun 25 05:22:31 PM PDT 24 | Jun 25 05:57:36 PM PDT 24 | 336966150000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2392573976 | Jun 25 05:22:25 PM PDT 24 | Jun 25 06:03:31 PM PDT 24 | 337145450000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.686230097 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:47:46 PM PDT 24 | 336991410000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2897740126 | Jun 25 05:22:27 PM PDT 24 | Jun 25 06:04:47 PM PDT 24 | 336942590000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3699618715 | Jun 25 05:22:19 PM PDT 24 | Jun 25 05:52:56 PM PDT 24 | 336688330000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4282874156 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:52:48 PM PDT 24 | 336885050000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1461658971 | Jun 25 05:22:22 PM PDT 24 | Jun 25 05:55:02 PM PDT 24 | 337115590000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.465226477 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:54:29 PM PDT 24 | 336913590000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4243179189 | Jun 25 05:22:23 PM PDT 24 | Jun 25 05:56:16 PM PDT 24 | 336404950000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3165078144 | Jun 25 05:22:32 PM PDT 24 | Jun 25 05:53:10 PM PDT 24 | 336613230000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2809138098 | Jun 25 05:22:20 PM PDT 24 | Jun 25 05:55:46 PM PDT 24 | 336558550000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2425039242 | Jun 25 05:22:22 PM PDT 24 | Jun 25 06:00:36 PM PDT 24 | 336412250000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2523183408 | Jun 25 05:22:30 PM PDT 24 | Jun 25 05:55:09 PM PDT 24 | 336362550000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2543052679 | Jun 25 05:22:23 PM PDT 24 | Jun 25 05:57:06 PM PDT 24 | 336494890000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2451190572 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:17:59 PM PDT 24 | 336554650000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1464916390 | Jun 25 04:42:31 PM PDT 24 | Jun 25 05:16:28 PM PDT 24 | 336592070000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2702293446 | Jun 25 04:41:56 PM PDT 24 | Jun 25 05:13:08 PM PDT 24 | 336403550000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1842922278 | Jun 25 04:41:54 PM PDT 24 | Jun 25 05:21:20 PM PDT 24 | 336831270000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.5603847 | Jun 25 04:41:59 PM PDT 24 | Jun 25 05:17:36 PM PDT 24 | 336633030000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3989746524 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:12:54 PM PDT 24 | 336983250000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2583968059 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:18:34 PM PDT 24 | 337063250000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1121344685 | Jun 25 04:41:55 PM PDT 24 | Jun 25 05:17:46 PM PDT 24 | 336460550000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1841213527 | Jun 25 04:42:02 PM PDT 24 | Jun 25 05:17:47 PM PDT 24 | 336484470000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2546385694 | Jun 25 04:42:01 PM PDT 24 | Jun 25 05:15:44 PM PDT 24 | 336600990000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3396109343 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:18:31 PM PDT 24 | 336755130000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2366722147 | Jun 25 04:42:39 PM PDT 24 | Jun 25 05:16:35 PM PDT 24 | 336606710000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2350432622 | Jun 25 04:42:36 PM PDT 24 | Jun 25 05:20:40 PM PDT 24 | 336438070000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2169242878 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:14:57 PM PDT 24 | 336843150000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.156247230 | Jun 25 04:41:59 PM PDT 24 | Jun 25 05:17:23 PM PDT 24 | 336789010000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.842813535 | Jun 25 04:42:02 PM PDT 24 | Jun 25 05:17:05 PM PDT 24 | 336477810000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1459667456 | Jun 25 04:41:53 PM PDT 24 | Jun 25 05:13:43 PM PDT 24 | 336726210000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.828046057 | Jun 25 04:42:37 PM PDT 24 | Jun 25 05:16:22 PM PDT 24 | 336859870000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2262087082 | Jun 25 04:42:00 PM PDT 24 | Jun 25 05:12:07 PM PDT 24 | 336785510000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4178988261 | Jun 25 04:42:50 PM PDT 24 | Jun 25 05:17:38 PM PDT 24 | 336661150000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.820333023 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:16:20 PM PDT 24 | 336478350000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2320815359 | Jun 25 04:42:02 PM PDT 24 | Jun 25 05:16:14 PM PDT 24 | 336606350000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2449163132 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:15:43 PM PDT 24 | 336537390000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2137303356 | Jun 25 04:42:02 PM PDT 24 | Jun 25 05:16:05 PM PDT 24 | 336491990000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3755740441 | Jun 25 04:41:59 PM PDT 24 | Jun 25 05:20:11 PM PDT 24 | 336574490000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1092952872 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:16:18 PM PDT 24 | 336743290000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1147721471 | Jun 25 04:42:40 PM PDT 24 | Jun 25 05:20:36 PM PDT 24 | 336888890000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4011059013 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:11:01 PM PDT 24 | 336847370000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3469255757 | Jun 25 04:42:01 PM PDT 24 | Jun 25 05:11:11 PM PDT 24 | 336806330000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.37319531 | Jun 25 04:41:59 PM PDT 24 | Jun 25 05:17:40 PM PDT 24 | 336711950000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.522139682 | Jun 25 04:42:27 PM PDT 24 | Jun 25 05:17:14 PM PDT 24 | 336902230000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.244868588 | Jun 25 04:42:41 PM PDT 24 | Jun 25 05:17:31 PM PDT 24 | 336518410000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3687546537 | Jun 25 04:41:55 PM PDT 24 | Jun 25 05:21:15 PM PDT 24 | 336960750000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2101268795 | Jun 25 04:41:59 PM PDT 24 | Jun 25 05:16:50 PM PDT 24 | 336405450000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2876190128 | Jun 25 04:42:56 PM PDT 24 | Jun 25 05:14:56 PM PDT 24 | 336418830000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2184617600 | Jun 25 04:42:02 PM PDT 24 | Jun 25 05:17:35 PM PDT 24 | 336454030000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.788456629 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:12:59 PM PDT 24 | 336476170000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1011131275 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:15:06 PM PDT 24 | 337038290000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3713215259 | Jun 25 04:42:04 PM PDT 24 | Jun 25 05:16:17 PM PDT 24 | 336794450000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2887135239 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:15:43 PM PDT 24 | 336573430000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.219792117 | Jun 25 04:42:01 PM PDT 24 | Jun 25 05:11:37 PM PDT 24 | 336980250000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1383413141 | Jun 25 04:41:58 PM PDT 24 | Jun 25 05:16:12 PM PDT 24 | 337027670000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1057379953 | Jun 25 04:41:55 PM PDT 24 | Jun 25 05:15:03 PM PDT 24 | 336375710000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.651053847 | Jun 25 04:42:02 PM PDT 24 | Jun 25 05:16:29 PM PDT 24 | 336904010000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2731819294 | Jun 25 04:41:59 PM PDT 24 | Jun 25 05:17:02 PM PDT 24 | 336449970000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3918605773 | Jun 25 04:41:55 PM PDT 24 | Jun 25 05:17:46 PM PDT 24 | 336685210000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3947891614 | Jun 25 04:42:38 PM PDT 24 | Jun 25 05:17:20 PM PDT 24 | 336783650000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3283777553 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:17:15 PM PDT 24 | 337031710000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1861444597 | Jun 25 04:41:57 PM PDT 24 | Jun 25 05:11:52 PM PDT 24 | 336736630000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1783641972 | Jun 25 04:42:30 PM PDT 24 | Jun 25 05:14:07 PM PDT 24 | 336588370000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1552200969 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1507090000 ps |
| CPU time | 3.56 seconds |
| Started | Jun 25 04:42:41 PM PDT 24 |
| Finished | Jun 25 04:42:50 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-b81ffe6d-59de-4df2-8c24-919fec165213 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1552200969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1552200969 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1163847953 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336558070000 ps |
| CPU time | 836.89 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:56:17 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-7659a5c1-aab4-4ad1-b93c-532ef95ada76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1163847953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1163847953 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3989746524 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336983250000 ps |
| CPU time | 759.55 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:12:54 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-24f94845-580e-461c-b93f-579005bd4d87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3989746524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3989746524 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1996624997 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1467890000 ps |
| CPU time | 4.99 seconds |
| Started | Jun 25 04:41:47 PM PDT 24 |
| Finished | Jun 25 04:41:59 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-9544e031-b605-41b9-8bb7-1dcb26a866b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1996624997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1996624997 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.3713215259 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336794450000 ps |
| CPU time | 848.33 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 05:16:17 PM PDT 24 |
| Peak memory | 160908 kb |
| Host | smart-26fe4f24-9272-4f90-9a38-6b7d98332e3e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3713215259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3713215259 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3283777553 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 337031710000 ps |
| CPU time | 879.07 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:17:15 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-d684789d-e88f-436e-912a-5b1295206060 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3283777553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3283777553 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1783641972 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336588370000 ps |
| CPU time | 778.56 seconds |
| Started | Jun 25 04:42:30 PM PDT 24 |
| Finished | Jun 25 05:14:07 PM PDT 24 |
| Peak memory | 160620 kb |
| Host | smart-7ddda09b-cc0c-41ad-b620-a42286152e44 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1783641972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1783641972 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3396109343 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336755130000 ps |
| CPU time | 898.64 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:18:31 PM PDT 24 |
| Peak memory | 160064 kb |
| Host | smart-c28f0e31-cb69-4101-bc56-cab092d6f164 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3396109343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3396109343 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3687546537 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336960750000 ps |
| CPU time | 967.54 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 05:21:15 PM PDT 24 |
| Peak memory | 160376 kb |
| Host | smart-2d2cecb4-ac24-4abb-afe5-2d55a7ae144e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3687546537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3687546537 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1459667456 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336726210000 ps |
| CPU time | 767.66 seconds |
| Started | Jun 25 04:41:53 PM PDT 24 |
| Finished | Jun 25 05:13:43 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-5c972650-1de6-4825-9c82-7e9baaca9147 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1459667456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1459667456 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2137303356 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336491990000 ps |
| CPU time | 849.51 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 05:16:05 PM PDT 24 |
| Peak memory | 159268 kb |
| Host | smart-98b25b32-d1d8-4859-b5f5-4ec961a763bf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2137303356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2137303356 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2731819294 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336449970000 ps |
| CPU time | 852.78 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 05:17:02 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-a3e67d9a-d10c-42fc-8a35-a578c770dcf1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2731819294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2731819294 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2449163132 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336537390000 ps |
| CPU time | 834.33 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:15:43 PM PDT 24 |
| Peak memory | 160264 kb |
| Host | smart-b97386e1-74c4-49ad-a662-e89c302e1d06 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2449163132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2449163132 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1092952872 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336743290000 ps |
| CPU time | 831.6 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:16:18 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-4ca151ef-7215-48b1-bec9-6c357ac07806 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1092952872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1092952872 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3918605773 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336685210000 ps |
| CPU time | 876.78 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 05:17:46 PM PDT 24 |
| Peak memory | 160348 kb |
| Host | smart-55017eb1-8e91-4443-9102-e407f4e9f21f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3918605773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3918605773 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.4011059013 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336847370000 ps |
| CPU time | 695.94 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:11:01 PM PDT 24 |
| Peak memory | 160368 kb |
| Host | smart-f39566c3-ac39-43b5-92f2-698c5512ba8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4011059013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.4011059013 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2101268795 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336405450000 ps |
| CPU time | 848.57 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 05:16:50 PM PDT 24 |
| Peak memory | 160376 kb |
| Host | smart-d94006c0-b96b-4098-a4ef-76f4f8ee67f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2101268795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2101268795 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2887135239 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336573430000 ps |
| CPU time | 841.51 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:15:43 PM PDT 24 |
| Peak memory | 160264 kb |
| Host | smart-43df8f68-0a58-4709-a0fb-9837faa9f9a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2887135239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2887135239 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.37319531 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336711950000 ps |
| CPU time | 881.67 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 05:17:40 PM PDT 24 |
| Peak memory | 160524 kb |
| Host | smart-fe46450b-a6ea-4e33-9828-87eb5d225372 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=37319531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.37319531 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.2320815359 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336606350000 ps |
| CPU time | 851.88 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 05:16:14 PM PDT 24 |
| Peak memory | 160912 kb |
| Host | smart-ee033448-e244-4eaf-8dde-858f16631269 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2320815359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.2320815359 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1842922278 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336831270000 ps |
| CPU time | 972.84 seconds |
| Started | Jun 25 04:41:54 PM PDT 24 |
| Finished | Jun 25 05:21:20 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-5018dd8f-a69f-4f5c-a1ce-94b524f14b4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1842922278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1842922278 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.5603847 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336633030000 ps |
| CPU time | 892.45 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 05:17:36 PM PDT 24 |
| Peak memory | 160360 kb |
| Host | smart-70e33663-ea1f-4c34-9eaa-ebaba3102b9e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=5603847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.5603847 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.788456629 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336476170000 ps |
| CPU time | 762.48 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:12:59 PM PDT 24 |
| Peak memory | 160272 kb |
| Host | smart-08874cf0-8457-47a6-a5b6-4136ab192bec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=788456629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.788456629 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.828046057 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336859870000 ps |
| CPU time | 820.62 seconds |
| Started | Jun 25 04:42:37 PM PDT 24 |
| Finished | Jun 25 05:16:22 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-e7f1346c-1a24-4555-8d08-f7e0f651ccae |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=828046057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.828046057 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.156247230 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336789010000 ps |
| CPU time | 869.66 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 05:17:23 PM PDT 24 |
| Peak memory | 160368 kb |
| Host | smart-664ef028-760c-4470-90ed-5e014c52bd70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=156247230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.156247230 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2702293446 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336403550000 ps |
| CPU time | 761.5 seconds |
| Started | Jun 25 04:41:56 PM PDT 24 |
| Finished | Jun 25 05:13:08 PM PDT 24 |
| Peak memory | 160328 kb |
| Host | smart-5ceaf8eb-1d6d-4ce1-a843-45c53e92a4ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2702293446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2702293446 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2876190128 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336418830000 ps |
| CPU time | 784.75 seconds |
| Started | Jun 25 04:42:56 PM PDT 24 |
| Finished | Jun 25 05:14:56 PM PDT 24 |
| Peak memory | 160472 kb |
| Host | smart-6a9817ca-5ce1-4e90-a08c-0bbafac5655f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2876190128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2876190128 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1861444597 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336736630000 ps |
| CPU time | 743.34 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:11:52 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-f23e95b9-2fc9-4512-97ea-c21021245aaf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1861444597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1861444597 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2169242878 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336843150000 ps |
| CPU time | 805.3 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:14:57 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-3e1cdf5a-3d4d-4dcb-bbbd-597e2ce40eef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2169242878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2169242878 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1841213527 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336484470000 ps |
| CPU time | 862.12 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 05:17:47 PM PDT 24 |
| Peak memory | 160280 kb |
| Host | smart-e352e88c-66fd-4f4d-b7d2-344623ebc3bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1841213527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1841213527 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.820333023 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336478350000 ps |
| CPU time | 835.33 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:16:20 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-69c85e35-3cc3-4c32-8825-a9e742c7ab0e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=820333023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.820333023 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.219792117 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336980250000 ps |
| CPU time | 726.17 seconds |
| Started | Jun 25 04:42:01 PM PDT 24 |
| Finished | Jun 25 05:11:37 PM PDT 24 |
| Peak memory | 159512 kb |
| Host | smart-cc0a0730-3f31-4c59-8adb-bb1aee5e861e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=219792117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.219792117 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1147721471 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336888890000 ps |
| CPU time | 916.11 seconds |
| Started | Jun 25 04:42:40 PM PDT 24 |
| Finished | Jun 25 05:20:36 PM PDT 24 |
| Peak memory | 160564 kb |
| Host | smart-53c95129-9def-4323-ba25-4b3db972df23 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1147721471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1147721471 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.3469255757 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336806330000 ps |
| CPU time | 721.68 seconds |
| Started | Jun 25 04:42:01 PM PDT 24 |
| Finished | Jun 25 05:11:11 PM PDT 24 |
| Peak memory | 159440 kb |
| Host | smart-d2d84a2e-30d9-4d27-8a9c-1f63ca0bdc6f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3469255757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.3469255757 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.244868588 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336518410000 ps |
| CPU time | 866.23 seconds |
| Started | Jun 25 04:42:41 PM PDT 24 |
| Finished | Jun 25 05:17:31 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-f10e6a9d-8f90-4fd0-bfcb-c5847d9fb740 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=244868588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.244868588 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3947891614 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336783650000 ps |
| CPU time | 838.61 seconds |
| Started | Jun 25 04:42:38 PM PDT 24 |
| Finished | Jun 25 05:17:20 PM PDT 24 |
| Peak memory | 160564 kb |
| Host | smart-3e47d57c-ca78-4c9a-a1b3-681ada7062b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3947891614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3947891614 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2184617600 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336454030000 ps |
| CPU time | 853.96 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 05:17:35 PM PDT 24 |
| Peak memory | 160376 kb |
| Host | smart-912d2e36-cf29-47b9-ac86-7a90530d84d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2184617600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2184617600 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2451190572 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336554650000 ps |
| CPU time | 892.94 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:17:59 PM PDT 24 |
| Peak memory | 160528 kb |
| Host | smart-00f1c41f-4fed-41fe-9adf-72685e63f38b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2451190572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2451190572 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2350432622 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336438070000 ps |
| CPU time | 916.26 seconds |
| Started | Jun 25 04:42:36 PM PDT 24 |
| Finished | Jun 25 05:20:40 PM PDT 24 |
| Peak memory | 160564 kb |
| Host | smart-e8001697-5122-431b-a5d1-ab7cb5828460 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2350432622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2350432622 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4178988261 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336661150000 ps |
| CPU time | 841.88 seconds |
| Started | Jun 25 04:42:50 PM PDT 24 |
| Finished | Jun 25 05:17:38 PM PDT 24 |
| Peak memory | 160564 kb |
| Host | smart-ed2f7088-8d55-4b67-b7aa-fbdb2cf7a487 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4178988261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4178988261 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.842813535 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336477810000 ps |
| CPU time | 844.82 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 05:17:05 PM PDT 24 |
| Peak memory | 160368 kb |
| Host | smart-e74c7cf3-c358-48f7-b072-8a3ac8b41c67 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=842813535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.842813535 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2583968059 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 337063250000 ps |
| CPU time | 896.37 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:18:34 PM PDT 24 |
| Peak memory | 160196 kb |
| Host | smart-26165597-1dbe-4e66-af1a-f8a0f3e7f5a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2583968059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2583968059 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.522139682 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336902230000 ps |
| CPU time | 848.5 seconds |
| Started | Jun 25 04:42:27 PM PDT 24 |
| Finished | Jun 25 05:17:14 PM PDT 24 |
| Peak memory | 160556 kb |
| Host | smart-71d3b52b-fc9c-4668-be94-5b4f753883f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=522139682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.522139682 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2366722147 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336606710000 ps |
| CPU time | 825.19 seconds |
| Started | Jun 25 04:42:39 PM PDT 24 |
| Finished | Jun 25 05:16:35 PM PDT 24 |
| Peak memory | 160540 kb |
| Host | smart-587073e7-df86-4810-969c-5523f6e5c232 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2366722147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2366722147 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1057379953 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336375710000 ps |
| CPU time | 815.94 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 05:15:03 PM PDT 24 |
| Peak memory | 160536 kb |
| Host | smart-d5e267ca-98e3-41c6-b301-e6d7751915ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1057379953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1057379953 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1464916390 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336592070000 ps |
| CPU time | 827.06 seconds |
| Started | Jun 25 04:42:31 PM PDT 24 |
| Finished | Jun 25 05:16:28 PM PDT 24 |
| Peak memory | 160540 kb |
| Host | smart-89c458bb-0cf2-4014-9f77-9694564fdcfc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1464916390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1464916390 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2262087082 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336785510000 ps |
| CPU time | 734.19 seconds |
| Started | Jun 25 04:42:00 PM PDT 24 |
| Finished | Jun 25 05:12:07 PM PDT 24 |
| Peak memory | 159768 kb |
| Host | smart-ab848bc9-60f7-4ceb-a1ad-426b547b2d15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2262087082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2262087082 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2546385694 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336600990000 ps |
| CPU time | 829.56 seconds |
| Started | Jun 25 04:42:01 PM PDT 24 |
| Finished | Jun 25 05:15:44 PM PDT 24 |
| Peak memory | 160172 kb |
| Host | smart-a0fc8150-373e-4445-8525-20a6a82f5a6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2546385694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2546385694 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1011131275 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 337038290000 ps |
| CPU time | 812.6 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 05:15:06 PM PDT 24 |
| Peak memory | 160520 kb |
| Host | smart-3da95bc8-a8bd-4e1d-b788-1ba605974785 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1011131275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1011131275 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.651053847 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336904010000 ps |
| CPU time | 861.4 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 05:16:29 PM PDT 24 |
| Peak memory | 159244 kb |
| Host | smart-552df520-b833-4290-8e63-e05cbb813ee1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=651053847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.651053847 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1121344685 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336460550000 ps |
| CPU time | 879.88 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 05:17:46 PM PDT 24 |
| Peak memory | 160244 kb |
| Host | smart-8098f992-7019-4b32-928f-8f0682a8776a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1121344685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1121344685 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3755740441 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336574490000 ps |
| CPU time | 922.75 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 05:20:11 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-0e2d9d94-8940-4e38-87e0-80c6dfc2573e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3755740441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3755740441 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1383413141 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 337027670000 ps |
| CPU time | 840.58 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 05:16:12 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-2a49831c-008d-44ea-9145-ef30364ab8a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1383413141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1383413141 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2092173705 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 337032870000 ps |
| CPU time | 801.82 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:54:58 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-5cc5f5ea-ed18-42db-b32b-f8bf695c8c4c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2092173705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2092173705 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3988350009 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336707990000 ps |
| CPU time | 819.83 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:55:22 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-4f8a7782-9330-463b-89d6-c365482e3059 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3988350009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3988350009 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2543052679 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 336494890000 ps |
| CPU time | 843.76 seconds |
| Started | Jun 25 05:22:23 PM PDT 24 |
| Finished | Jun 25 05:57:06 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-06438c09-ceee-4b2f-9990-a3b1ffb0e7c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2543052679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2543052679 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.4154332310 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 337001550000 ps |
| CPU time | 781.26 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:53:58 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-dfa6eb77-ec62-4ab9-8254-f4bf6feb5343 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4154332310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.4154332310 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3422150874 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 336552630000 ps |
| CPU time | 727.12 seconds |
| Started | Jun 25 05:22:18 PM PDT 24 |
| Finished | Jun 25 05:52:09 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-7a34c818-74a4-4440-8729-ed52c435c2ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3422150874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3422150874 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1328015981 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336891390000 ps |
| CPU time | 823.84 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:56:00 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-8053a795-f75e-4e68-a079-e559e7609da8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1328015981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1328015981 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4130952768 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336538890000 ps |
| CPU time | 835.63 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:56:30 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-e6a0a9ff-b8a4-4ae9-ab28-3309740a20f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4130952768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4130952768 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3699618715 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 336688330000 ps |
| CPU time | 738.68 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:52:56 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-670a8762-0ec8-4aa4-9085-0d01582ed37b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3699618715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3699618715 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1853781427 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336807890000 ps |
| CPU time | 1005.03 seconds |
| Started | Jun 25 05:22:25 PM PDT 24 |
| Finished | Jun 25 06:03:34 PM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-bc1cdd8b-3954-4c75-9674-eb76b4e58ce6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1853781427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1853781427 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2392573976 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 337145450000 ps |
| CPU time | 1002.23 seconds |
| Started | Jun 25 05:22:25 PM PDT 24 |
| Finished | Jun 25 06:03:31 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-52300262-767a-4821-a9ae-e2c1980c45b3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2392573976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2392573976 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3436478019 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 337048790000 ps |
| CPU time | 992.21 seconds |
| Started | Jun 25 05:22:27 PM PDT 24 |
| Finished | Jun 25 06:04:35 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-899e3cbd-a4ef-41aa-b0d7-46a2bfa7810e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3436478019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3436478019 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.47950480 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 337123550000 ps |
| CPU time | 854.78 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:56:31 PM PDT 24 |
| Peak memory | 160760 kb |
| Host | smart-02c844de-6cf3-41c4-a25d-2a64e9aed488 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=47950480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.47950480 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2230710499 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336962870000 ps |
| CPU time | 998.33 seconds |
| Started | Jun 25 05:22:27 PM PDT 24 |
| Finished | Jun 25 06:04:45 PM PDT 24 |
| Peak memory | 160544 kb |
| Host | smart-c63b2699-a255-4c24-bd39-f7b595d2a8ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2230710499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2230710499 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2897740126 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336942590000 ps |
| CPU time | 999.33 seconds |
| Started | Jun 25 05:22:27 PM PDT 24 |
| Finished | Jun 25 06:04:47 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-fd5ec3f6-9419-4e82-ad72-0b4376fb6978 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2897740126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2897740126 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1151005671 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336851450000 ps |
| CPU time | 825.77 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:56:25 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-e9387bc1-fba8-4892-b28a-71bd015b213f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1151005671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1151005671 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.702130180 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336995350000 ps |
| CPU time | 822.29 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:55:57 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-6b5955a1-7fc0-4adb-8695-3de38f250637 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=702130180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.702130180 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3719233157 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336904170000 ps |
| CPU time | 850.73 seconds |
| Started | Jun 25 05:22:22 PM PDT 24 |
| Finished | Jun 25 05:57:00 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-f142658f-8092-48d2-a4d7-6944ffafed18 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3719233157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3719233157 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3139402040 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336545530000 ps |
| CPU time | 991.55 seconds |
| Started | Jun 25 05:22:27 PM PDT 24 |
| Finished | Jun 25 06:04:29 PM PDT 24 |
| Peak memory | 160532 kb |
| Host | smart-094f7c24-e7d8-484c-88fa-3e10f130996f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3139402040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3139402040 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2688069155 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336869830000 ps |
| CPU time | 925.97 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 06:00:18 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-1e5f9e96-86ff-4b7d-87de-6113953e1003 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2688069155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2688069155 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2425039242 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336412250000 ps |
| CPU time | 937.42 seconds |
| Started | Jun 25 05:22:22 PM PDT 24 |
| Finished | Jun 25 06:00:36 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-e8bad001-d8f8-44cc-a3a7-81fbb1dbc963 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2425039242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2425039242 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.4243179189 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336404950000 ps |
| CPU time | 819.62 seconds |
| Started | Jun 25 05:22:23 PM PDT 24 |
| Finished | Jun 25 05:56:16 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-c0b24ebb-ac3a-4a6d-aec7-84b7edefbb31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4243179189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.4243179189 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3606881123 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 337014930000 ps |
| CPU time | 840.04 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:57:01 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-1580caa6-dfb4-42ae-8085-46d425ea9803 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3606881123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3606881123 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1461658971 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 337115590000 ps |
| CPU time | 805.7 seconds |
| Started | Jun 25 05:22:22 PM PDT 24 |
| Finished | Jun 25 05:55:02 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-8a3d62bb-b997-4ecf-b922-b2207f6a0391 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1461658971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1461658971 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2858132394 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336867450000 ps |
| CPU time | 951.74 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 06:00:30 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-420b1fec-4ce9-4993-9fbf-0e4efbeab05d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2858132394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2858132394 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.686230097 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 336991410000 ps |
| CPU time | 601.18 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:47:46 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-5d970294-ca2d-42eb-b763-381f9a230ae1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=686230097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.686230097 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.876378932 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 336747270000 ps |
| CPU time | 936.79 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 06:00:41 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-41c07f8e-d698-4cbb-b7f2-91105ac4e49d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=876378932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.876378932 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.959211426 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336402530000 ps |
| CPU time | 821.78 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:55:56 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-44254129-86b5-43e8-aff4-81c35791ce8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=959211426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.959211426 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1874850793 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336539850000 ps |
| CPU time | 781.99 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:54:49 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-0b6acb67-83c6-4eca-b1bc-b9766a988990 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1874850793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1874850793 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.834017689 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336496350000 ps |
| CPU time | 801.33 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:55:14 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-1fb3d4a7-1b21-4bf4-889a-831b80612ed1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=834017689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.834017689 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2877775243 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 336728950000 ps |
| CPU time | 1001.57 seconds |
| Started | Jun 25 05:22:25 PM PDT 24 |
| Finished | Jun 25 06:03:44 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-500fe3b7-af39-4317-b356-96b88b066cf6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2877775243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2877775243 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.4282874156 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336885050000 ps |
| CPU time | 736.63 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:52:48 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-4bd68453-7c46-46c2-ae8d-6b8e73c27a61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4282874156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.4282874156 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.465226477 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336913590000 ps |
| CPU time | 780.49 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:54:29 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-bc844b95-a862-4e9e-a18d-62623201a904 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=465226477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.465226477 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2327199283 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336725010000 ps |
| CPU time | 801.91 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:54:48 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-478a9bfe-45a8-4f3b-bd4d-563172211fa2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2327199283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2327199283 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2960329867 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336739950000 ps |
| CPU time | 868.01 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:57:24 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-f19d4820-7f5b-4cc0-919f-d50ac0fafb5f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2960329867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2960329867 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.4251086580 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336739430000 ps |
| CPU time | 817.89 seconds |
| Started | Jun 25 05:22:19 PM PDT 24 |
| Finished | Jun 25 05:56:04 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-390e4c6c-5a78-4d99-a790-e5667ec6408c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4251086580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.4251086580 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1621328578 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336943370000 ps |
| CPU time | 749.03 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:52:35 PM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-cff9e895-949a-4a4b-974b-03f9fa3fc864 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1621328578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1621328578 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.303075785 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336302550000 ps |
| CPU time | 829.52 seconds |
| Started | Jun 25 05:22:29 PM PDT 24 |
| Finished | Jun 25 05:56:39 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-63275df2-e248-4a38-bcb1-32d9bcf3c3c7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=303075785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.303075785 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3844844936 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336553990000 ps |
| CPU time | 844.32 seconds |
| Started | Jun 25 05:22:28 PM PDT 24 |
| Finished | Jun 25 05:56:39 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-b9217554-9b49-4af5-9191-5ed00dc95cfe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3844844936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3844844936 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3165078144 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336613230000 ps |
| CPU time | 742.18 seconds |
| Started | Jun 25 05:22:32 PM PDT 24 |
| Finished | Jun 25 05:53:10 PM PDT 24 |
| Peak memory | 160916 kb |
| Host | smart-0ad60273-7e66-4353-b713-c4e19815d362 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3165078144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3165078144 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2924584664 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336376890000 ps |
| CPU time | 923.99 seconds |
| Started | Jun 25 05:22:29 PM PDT 24 |
| Finished | Jun 25 06:00:42 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-f1f30aed-130c-4273-97cf-368911f74dfe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2924584664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2924584664 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.2285885689 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336966150000 ps |
| CPU time | 859.03 seconds |
| Started | Jun 25 05:22:31 PM PDT 24 |
| Finished | Jun 25 05:57:36 PM PDT 24 |
| Peak memory | 160748 kb |
| Host | smart-9679eede-016a-45b9-9f14-b69e88aefd6a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2285885689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.2285885689 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2523183408 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336362550000 ps |
| CPU time | 803.02 seconds |
| Started | Jun 25 05:22:30 PM PDT 24 |
| Finished | Jun 25 05:55:09 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-1c2e9cd6-b71e-46b5-a02d-4997335d3d68 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2523183408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2523183408 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1913396830 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336964750000 ps |
| CPU time | 1004.75 seconds |
| Started | Jun 25 05:22:32 PM PDT 24 |
| Finished | Jun 25 06:05:04 PM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-3a94036b-ba06-4252-8860-46835baa78c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1913396830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1913396830 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4112535789 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336753870000 ps |
| CPU time | 875.05 seconds |
| Started | Jun 25 05:22:31 PM PDT 24 |
| Finished | Jun 25 05:57:55 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-62c19a00-42a4-40a1-b182-fb11814bc287 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4112535789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.4112535789 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2809138098 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336558550000 ps |
| CPU time | 812.27 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:55:46 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-a43190fd-f15a-4139-996e-d40acb816030 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2809138098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2809138098 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3461985147 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336741090000 ps |
| CPU time | 813 seconds |
| Started | Jun 25 05:22:20 PM PDT 24 |
| Finished | Jun 25 05:55:25 PM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-89f2dcf5-ac23-42d4-bc60-5c680affbf2b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3461985147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3461985147 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3856934512 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336677570000 ps |
| CPU time | 831.81 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 05:56:01 PM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-1916af80-638b-4b3a-a60f-44faea242985 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3856934512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3856934512 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.969723360 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336692390000 ps |
| CPU time | 633.89 seconds |
| Started | Jun 25 05:22:22 PM PDT 24 |
| Finished | Jun 25 05:49:21 PM PDT 24 |
| Peak memory | 160768 kb |
| Host | smart-67ac2af3-93bc-468e-ba9f-110f4fbb8b78 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=969723360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.969723360 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3188895972 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336494390000 ps |
| CPU time | 946.9 seconds |
| Started | Jun 25 05:22:21 PM PDT 24 |
| Finished | Jun 25 06:00:27 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-0bb92509-acc5-4ec3-8564-0cdf199a0f61 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3188895972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3188895972 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2837823193 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1083470000 ps |
| CPU time | 2.58 seconds |
| Started | Jun 25 04:42:22 PM PDT 24 |
| Finished | Jun 25 04:42:30 PM PDT 24 |
| Peak memory | 164648 kb |
| Host | smart-c7202528-b250-44c2-a1a2-1517be2bebc6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2837823193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2837823193 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1052177184 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1559530000 ps |
| CPU time | 5.38 seconds |
| Started | Jun 25 04:41:43 PM PDT 24 |
| Finished | Jun 25 04:41:55 PM PDT 24 |
| Peak memory | 165080 kb |
| Host | smart-99f03286-5d9c-49ec-91e0-830a8ae82208 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1052177184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1052177184 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.998875330 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1374670000 ps |
| CPU time | 4.31 seconds |
| Started | Jun 25 04:41:54 PM PDT 24 |
| Finished | Jun 25 04:42:04 PM PDT 24 |
| Peak memory | 163868 kb |
| Host | smart-ffa144e4-1961-485a-8861-4184e5ac1d2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=998875330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.998875330 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.26557738 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1190530000 ps |
| CPU time | 3.56 seconds |
| Started | Jun 25 04:41:50 PM PDT 24 |
| Finished | Jun 25 04:42:00 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-31ad369d-ffb6-43e5-816b-f5928ab81943 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=26557738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.26557738 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3687208701 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1456030000 ps |
| CPU time | 4.55 seconds |
| Started | Jun 25 04:41:51 PM PDT 24 |
| Finished | Jun 25 04:42:03 PM PDT 24 |
| Peak memory | 164388 kb |
| Host | smart-160aa70a-d7ae-42fe-8941-e540eb38b157 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3687208701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3687208701 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2272836628 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1439250000 ps |
| CPU time | 4.29 seconds |
| Started | Jun 25 04:41:51 PM PDT 24 |
| Finished | Jun 25 04:42:02 PM PDT 24 |
| Peak memory | 164456 kb |
| Host | smart-a6537552-9781-4a77-9612-c3771b198677 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2272836628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2272836628 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2249026065 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1525710000 ps |
| CPU time | 3.87 seconds |
| Started | Jun 25 04:41:48 PM PDT 24 |
| Finished | Jun 25 04:41:58 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-c1eb886f-6ce5-43c2-913b-6d15287a6a1a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2249026065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2249026065 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1199861196 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1512610000 ps |
| CPU time | 5.37 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 04:42:08 PM PDT 24 |
| Peak memory | 164400 kb |
| Host | smart-8241f55a-a571-4d02-a975-dd25b2b38e96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1199861196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1199861196 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3886311584 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1466110000 ps |
| CPU time | 3.08 seconds |
| Started | Jun 25 04:41:46 PM PDT 24 |
| Finished | Jun 25 04:41:54 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-ce52e9a1-ffb4-48c8-8300-84d012519830 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3886311584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3886311584 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1106819944 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1371130000 ps |
| CPU time | 4.17 seconds |
| Started | Jun 25 04:41:50 PM PDT 24 |
| Finished | Jun 25 04:42:01 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-f8f3d47a-c4b7-478d-b8cb-0c12c2e87c73 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1106819944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1106819944 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2127951274 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1479570000 ps |
| CPU time | 5.38 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 04:42:07 PM PDT 24 |
| Peak memory | 163704 kb |
| Host | smart-ad961e19-e558-482a-9acf-4a2fd2522241 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2127951274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2127951274 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1169869368 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1456910000 ps |
| CPU time | 4.3 seconds |
| Started | Jun 25 04:41:54 PM PDT 24 |
| Finished | Jun 25 04:42:04 PM PDT 24 |
| Peak memory | 164208 kb |
| Host | smart-0c41946d-e8f9-487d-b8e9-5a3bfa630350 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1169869368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1169869368 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1081587461 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1273890000 ps |
| CPU time | 4.93 seconds |
| Started | Jun 25 04:41:49 PM PDT 24 |
| Finished | Jun 25 04:42:01 PM PDT 24 |
| Peak memory | 164988 kb |
| Host | smart-4cc42980-ade5-4813-8324-a58427586a79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1081587461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.1081587461 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4164288112 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1301850000 ps |
| CPU time | 4.84 seconds |
| Started | Jun 25 04:41:55 PM PDT 24 |
| Finished | Jun 25 04:42:06 PM PDT 24 |
| Peak memory | 163632 kb |
| Host | smart-8a02d727-ce58-4bf8-ae95-278a567014ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4164288112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4164288112 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.73778726 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1588050000 ps |
| CPU time | 5.01 seconds |
| Started | Jun 25 04:41:50 PM PDT 24 |
| Finished | Jun 25 04:42:03 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-ad62e34e-ac0e-405a-b943-bad969aeb3e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=73778726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.73778726 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2347065085 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1424810000 ps |
| CPU time | 5.21 seconds |
| Started | Jun 25 04:41:46 PM PDT 24 |
| Finished | Jun 25 04:41:58 PM PDT 24 |
| Peak memory | 165052 kb |
| Host | smart-ba6f81b8-e79d-4e66-90df-e0ca5ff7acb8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2347065085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2347065085 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.750760004 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1528670000 ps |
| CPU time | 3.32 seconds |
| Started | Jun 25 04:42:42 PM PDT 24 |
| Finished | Jun 25 04:42:51 PM PDT 24 |
| Peak memory | 164664 kb |
| Host | smart-1c95c71c-1fe6-44a7-ae58-3d1fd837ded9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=750760004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.750760004 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1823988018 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1618990000 ps |
| CPU time | 4.92 seconds |
| Started | Jun 25 04:41:54 PM PDT 24 |
| Finished | Jun 25 04:42:06 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-49a140a4-b402-4681-9334-fa24d1dc5f8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1823988018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1823988018 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2293202408 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1527630000 ps |
| CPU time | 3.77 seconds |
| Started | Jun 25 04:41:47 PM PDT 24 |
| Finished | Jun 25 04:41:57 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-99e82ab4-b119-43a3-b4c1-d77def306187 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2293202408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2293202408 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4059481335 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1242190000 ps |
| CPU time | 4.03 seconds |
| Started | Jun 25 04:41:50 PM PDT 24 |
| Finished | Jun 25 04:42:01 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-6b77e623-8ac1-405f-b385-d2f81117f2fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4059481335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.4059481335 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2063943426 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1618050000 ps |
| CPU time | 5.46 seconds |
| Started | Jun 25 04:41:46 PM PDT 24 |
| Finished | Jun 25 04:41:59 PM PDT 24 |
| Peak memory | 164988 kb |
| Host | smart-17f3df2a-244e-48c9-ba72-23e0be25ab63 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2063943426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2063943426 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3078568440 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1399910000 ps |
| CPU time | 3.77 seconds |
| Started | Jun 25 04:41:51 PM PDT 24 |
| Finished | Jun 25 04:42:01 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-f497edca-f5c1-4769-bce4-92fbcd301b9d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3078568440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3078568440 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2656912431 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1539410000 ps |
| CPU time | 4.62 seconds |
| Started | Jun 25 04:41:54 PM PDT 24 |
| Finished | Jun 25 04:42:04 PM PDT 24 |
| Peak memory | 163132 kb |
| Host | smart-64eea947-5921-4c7f-a04a-feabd6ff8c15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2656912431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2656912431 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3254662681 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1427210000 ps |
| CPU time | 4.92 seconds |
| Started | Jun 25 04:41:56 PM PDT 24 |
| Finished | Jun 25 04:42:08 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-b86aa6e5-23f0-4692-bc0d-7f8d01b923b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3254662681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3254662681 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2877210942 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1458890000 ps |
| CPU time | 4.27 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:07 PM PDT 24 |
| Peak memory | 165072 kb |
| Host | smart-96e86810-4951-4a27-b024-52fcb108fc27 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2877210942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2877210942 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2536099478 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1422890000 ps |
| CPU time | 5.3 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:10 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-ecb00810-eeb4-4f4d-91d0-ee402d6a119c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2536099478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2536099478 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.257548952 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1405970000 ps |
| CPU time | 3.67 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 04:42:09 PM PDT 24 |
| Peak memory | 164392 kb |
| Host | smart-2b8364ca-0852-4fa6-a6d0-3ae447add40f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=257548952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.257548952 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3645065968 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1471610000 ps |
| CPU time | 4.12 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 04:42:09 PM PDT 24 |
| Peak memory | 163732 kb |
| Host | smart-35a55316-fde7-4434-99ce-58921308797b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3645065968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3645065968 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2268651198 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1557710000 ps |
| CPU time | 4.42 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:07 PM PDT 24 |
| Peak memory | 164388 kb |
| Host | smart-cfd12c95-f952-48af-99b6-80cf01046a1e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2268651198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2268651198 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1806103823 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1545050000 ps |
| CPU time | 4.96 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:08 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-f23202c7-7684-45f3-93d7-93b29a6caef1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1806103823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1806103823 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1048537872 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1562290000 ps |
| CPU time | 4.27 seconds |
| Started | Jun 25 04:41:56 PM PDT 24 |
| Finished | Jun 25 04:42:06 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-063e2fee-4377-4a91-928b-44372040f25d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1048537872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1048537872 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.938524601 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1558170000 ps |
| CPU time | 5.71 seconds |
| Started | Jun 25 04:41:59 PM PDT 24 |
| Finished | Jun 25 04:42:12 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-ee72aa9e-e11e-4cff-9302-91f66fcaeb82 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=938524601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.938524601 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1378830278 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1398910000 ps |
| CPU time | 5.22 seconds |
| Started | Jun 25 04:41:53 PM PDT 24 |
| Finished | Jun 25 04:42:05 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-97a601bb-5cfa-464b-8aa2-ebaaa6631e80 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1378830278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1378830278 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1619844857 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1518930000 ps |
| CPU time | 4.96 seconds |
| Started | Jun 25 04:41:44 PM PDT 24 |
| Finished | Jun 25 04:41:56 PM PDT 24 |
| Peak memory | 164508 kb |
| Host | smart-4da30773-58c0-41d8-aacd-b165b20acbca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1619844857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1619844857 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1490792043 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1457770000 ps |
| CPU time | 3.43 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:06 PM PDT 24 |
| Peak memory | 164352 kb |
| Host | smart-2b609b13-a95a-4040-992c-a9c1627469da |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1490792043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1490792043 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2052047135 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1518790000 ps |
| CPU time | 4.81 seconds |
| Started | Jun 25 04:41:56 PM PDT 24 |
| Finished | Jun 25 04:42:07 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-dc4833c2-c75c-4346-8b4d-caeb1ddeb07a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2052047135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2052047135 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3857076846 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1357310000 ps |
| CPU time | 4.04 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 04:42:09 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-fa5c1ba4-3d84-4e29-b303-82dc55d22b34 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3857076846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3857076846 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2464623223 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1387550000 ps |
| CPU time | 4.11 seconds |
| Started | Jun 25 04:42:00 PM PDT 24 |
| Finished | Jun 25 04:42:10 PM PDT 24 |
| Peak memory | 164400 kb |
| Host | smart-864ee8f9-6080-423b-b2e6-db9b9a93ef90 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2464623223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2464623223 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.722972253 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1381310000 ps |
| CPU time | 4.33 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:12 PM PDT 24 |
| Peak memory | 164392 kb |
| Host | smart-d97a01af-6b32-411c-b569-7593f84e6f68 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=722972253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.722972253 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1670215553 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1575090000 ps |
| CPU time | 5.35 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 164552 kb |
| Host | smart-e5b5d6c8-209f-4e9c-b8e1-553ae4c54ae7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1670215553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1670215553 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2175854384 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1382330000 ps |
| CPU time | 4.02 seconds |
| Started | Jun 25 04:41:56 PM PDT 24 |
| Finished | Jun 25 04:42:06 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-2101bb73-bc0a-43a3-957e-587bf220a215 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2175854384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2175854384 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4128263161 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1586250000 ps |
| CPU time | 3.44 seconds |
| Started | Jun 25 04:41:57 PM PDT 24 |
| Finished | Jun 25 04:42:06 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-f5b0e56b-d98c-44c0-9a63-d2d54db8700f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4128263161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.4128263161 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.32277930 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1376550000 ps |
| CPU time | 4.21 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 04:42:08 PM PDT 24 |
| Peak memory | 164312 kb |
| Host | smart-9d28ebb2-cfd3-4472-a504-abcdeb411b5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=32277930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.32277930 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3271055283 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1378170000 ps |
| CPU time | 3.45 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 04:42:08 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-f1992ee8-a59c-4474-9751-c89d98bbc76f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3271055283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3271055283 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.427460216 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1446370000 ps |
| CPU time | 4.76 seconds |
| Started | Jun 25 04:41:42 PM PDT 24 |
| Finished | Jun 25 04:41:54 PM PDT 24 |
| Peak memory | 164316 kb |
| Host | smart-79ea28fd-a2c2-489f-a12f-60a36da2b728 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=427460216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.427460216 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2156330861 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1341430000 ps |
| CPU time | 4.73 seconds |
| Started | Jun 25 04:41:42 PM PDT 24 |
| Finished | Jun 25 04:41:53 PM PDT 24 |
| Peak memory | 164148 kb |
| Host | smart-525d5c4e-d959-4673-b450-f00c7ec6d9ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2156330861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2156330861 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3181564469 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1505510000 ps |
| CPU time | 4.16 seconds |
| Started | Jun 25 04:41:50 PM PDT 24 |
| Finished | Jun 25 04:42:01 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-e6f5ae0c-915f-454d-94e0-4f75e448bfb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3181564469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3181564469 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.464152601 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1459310000 ps |
| CPU time | 4.8 seconds |
| Started | Jun 25 04:41:51 PM PDT 24 |
| Finished | Jun 25 04:42:03 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-c8b6aa8d-87f2-4648-aa79-884220cb5179 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=464152601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.464152601 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1642636451 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1482130000 ps |
| CPU time | 5.02 seconds |
| Started | Jun 25 04:41:49 PM PDT 24 |
| Finished | Jun 25 04:42:02 PM PDT 24 |
| Peak memory | 165068 kb |
| Host | smart-01526ee7-1844-4266-87e7-014658eff298 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1642636451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.1642636451 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3275327421 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1552070000 ps |
| CPU time | 5.86 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 04:42:13 PM PDT 24 |
| Peak memory | 165020 kb |
| Host | smart-0b501423-05ba-4fca-8ac9-7aa5eed916b6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3275327421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3275327421 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1101039253 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1465290000 ps |
| CPU time | 4.79 seconds |
| Started | Jun 25 04:42:18 PM PDT 24 |
| Finished | Jun 25 04:42:32 PM PDT 24 |
| Peak memory | 165044 kb |
| Host | smart-f222ef6f-c2c2-47fa-b627-c2bd22c073c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1101039253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1101039253 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1238549635 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1595310000 ps |
| CPU time | 5.36 seconds |
| Started | Jun 25 04:42:05 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 164564 kb |
| Host | smart-bf7ba5e4-a527-4f8f-8586-4b4dafd85c7a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1238549635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1238549635 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3816800916 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1534170000 ps |
| CPU time | 5.73 seconds |
| Started | Jun 25 04:42:08 PM PDT 24 |
| Finished | Jun 25 04:42:22 PM PDT 24 |
| Peak memory | 164384 kb |
| Host | smart-3f090582-869d-4c10-b1d0-2a901c27b681 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3816800916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3816800916 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1806300972 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1463390000 ps |
| CPU time | 4.81 seconds |
| Started | Jun 25 04:42:07 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 164388 kb |
| Host | smart-7ab542cc-9ca2-450c-a4c4-a30f55c666f3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1806300972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.1806300972 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.420101591 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1509590000 ps |
| CPU time | 5.31 seconds |
| Started | Jun 25 04:42:06 PM PDT 24 |
| Finished | Jun 25 04:42:20 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-f243e712-9dee-4c5c-99fe-c8365caccbd8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=420101591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.420101591 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1412570915 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1321770000 ps |
| CPU time | 4.83 seconds |
| Started | Jun 25 04:42:06 PM PDT 24 |
| Finished | Jun 25 04:42:18 PM PDT 24 |
| Peak memory | 165012 kb |
| Host | smart-3a2f83b6-1269-4a40-a482-e33d69c9afa7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1412570915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1412570915 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3284694226 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1327110000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 25 04:42:07 PM PDT 24 |
| Finished | Jun 25 04:42:18 PM PDT 24 |
| Peak memory | 164420 kb |
| Host | smart-42ec6e19-7331-47fa-b7a1-8209b3318ccd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3284694226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3284694226 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.3461943393 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1517890000 ps |
| CPU time | 4.42 seconds |
| Started | Jun 25 04:42:05 PM PDT 24 |
| Finished | Jun 25 04:42:17 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-58380a1a-e5f5-4a92-973d-4beb30e3a796 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3461943393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.3461943393 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.509522812 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1498210000 ps |
| CPU time | 4.27 seconds |
| Started | Jun 25 04:42:10 PM PDT 24 |
| Finished | Jun 25 04:42:20 PM PDT 24 |
| Peak memory | 164536 kb |
| Host | smart-31db271c-e4bf-4cac-b2e4-e0b81da19ad2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=509522812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.509522812 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2592018492 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1570670000 ps |
| CPU time | 5.84 seconds |
| Started | Jun 25 04:42:06 PM PDT 24 |
| Finished | Jun 25 04:42:20 PM PDT 24 |
| Peak memory | 164372 kb |
| Host | smart-35345630-d3c5-4831-b54b-57bfa8529a47 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2592018492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2592018492 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3875408959 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1212910000 ps |
| CPU time | 4.79 seconds |
| Started | Jun 25 04:42:00 PM PDT 24 |
| Finished | Jun 25 04:42:12 PM PDT 24 |
| Peak memory | 164400 kb |
| Host | smart-8eebb369-3daf-4a35-bc99-3fed8f8c43bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3875408959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3875408959 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.588660400 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1344550000 ps |
| CPU time | 4.69 seconds |
| Started | Jun 25 04:42:05 PM PDT 24 |
| Finished | Jun 25 04:42:17 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-ffa5866a-b47b-4de2-b19a-596c03fd0d10 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=588660400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.588660400 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3328426582 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1555770000 ps |
| CPU time | 5.66 seconds |
| Started | Jun 25 04:42:06 PM PDT 24 |
| Finished | Jun 25 04:42:20 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-d9f0913d-6109-46db-b6a1-50790fd1387d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3328426582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3328426582 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3078834294 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1483750000 ps |
| CPU time | 3.21 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:12 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-1206a425-bb37-4f64-ac29-61894762cbc8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3078834294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3078834294 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3243323324 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1502610000 ps |
| CPU time | 5.48 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:17 PM PDT 24 |
| Peak memory | 164388 kb |
| Host | smart-9670ed19-2a93-4ec5-b1b2-aa14e398febc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3243323324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3243323324 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1654156610 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1497190000 ps |
| CPU time | 3.96 seconds |
| Started | Jun 25 04:42:03 PM PDT 24 |
| Finished | Jun 25 04:42:13 PM PDT 24 |
| Peak memory | 164564 kb |
| Host | smart-d06d1026-915d-4b85-979f-81cb541cda91 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1654156610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1654156610 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3370684112 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1580210000 ps |
| CPU time | 5.1 seconds |
| Started | Jun 25 04:42:18 PM PDT 24 |
| Finished | Jun 25 04:42:32 PM PDT 24 |
| Peak memory | 165044 kb |
| Host | smart-65629be8-c825-4598-9500-c38dbb238283 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3370684112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3370684112 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2279230064 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1428250000 ps |
| CPU time | 4.14 seconds |
| Started | Jun 25 04:42:57 PM PDT 24 |
| Finished | Jun 25 04:43:07 PM PDT 24 |
| Peak memory | 164664 kb |
| Host | smart-b6360112-232a-4a78-8be6-efe73f6cb657 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2279230064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2279230064 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3450295209 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1495330000 ps |
| CPU time | 4.62 seconds |
| Started | Jun 25 04:42:05 PM PDT 24 |
| Finished | Jun 25 04:42:17 PM PDT 24 |
| Peak memory | 164268 kb |
| Host | smart-61a8a433-b97a-466b-989f-8619f079e76a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3450295209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3450295209 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1486438397 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1242910000 ps |
| CPU time | 4.58 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:16 PM PDT 24 |
| Peak memory | 164564 kb |
| Host | smart-c5692163-0d59-4e2a-9277-0f9bb030192a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1486438397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1486438397 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.4204694236 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1309710000 ps |
| CPU time | 4.17 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-556ca729-55c8-4486-86ff-4049e81671d1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4204694236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.4204694236 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.325901253 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1656930000 ps |
| CPU time | 5.04 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 163260 kb |
| Host | smart-2ef1989d-7093-4c15-baca-7d10c97c7138 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=325901253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.325901253 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.761098413 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1149590000 ps |
| CPU time | 4.19 seconds |
| Started | Jun 25 04:42:11 PM PDT 24 |
| Finished | Jun 25 04:42:21 PM PDT 24 |
| Peak memory | 164724 kb |
| Host | smart-3fadcea9-e9e9-41a1-a6f7-d855323fd360 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=761098413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.761098413 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3597413519 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1497010000 ps |
| CPU time | 4.96 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:17 PM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-b1e19608-177c-43a4-9637-c2b3d9769448 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3597413519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3597413519 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1653261738 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1443130000 ps |
| CPU time | 4.87 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:17 PM PDT 24 |
| Peak memory | 164368 kb |
| Host | smart-c4a37cf6-bfc2-4a47-a947-5501f8b91f98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1653261738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1653261738 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3211248426 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1375130000 ps |
| CPU time | 4.25 seconds |
| Started | Jun 25 04:42:09 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-2dbb6604-9d94-43d3-a0bc-97d6e60698f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3211248426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3211248426 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.299410625 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1505770000 ps |
| CPU time | 4.75 seconds |
| Started | Jun 25 04:42:12 PM PDT 24 |
| Finished | Jun 25 04:42:24 PM PDT 24 |
| Peak memory | 164356 kb |
| Host | smart-bb6716cd-920c-4517-beb8-5360de10ba1f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=299410625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.299410625 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1791420526 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1364890000 ps |
| CPU time | 4.74 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:16 PM PDT 24 |
| Peak memory | 165012 kb |
| Host | smart-b257896b-5d3d-406b-9943-6efce1d8d713 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1791420526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1791420526 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.490641540 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1335790000 ps |
| CPU time | 4.3 seconds |
| Started | Jun 25 04:42:18 PM PDT 24 |
| Finished | Jun 25 04:42:30 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-5ba68d75-48b0-4f48-9b12-f4998c81778e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=490641540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.490641540 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2804332932 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1582090000 ps |
| CPU time | 4.78 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:16 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-0893fe5c-c952-47de-bfd6-d127409ce265 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2804332932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2804332932 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1179074456 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1476550000 ps |
| CPU time | 4.91 seconds |
| Started | Jun 25 04:42:12 PM PDT 24 |
| Finished | Jun 25 04:42:24 PM PDT 24 |
| Peak memory | 165044 kb |
| Host | smart-dc6063f3-1463-4fe8-933f-80ee2f3bc6ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1179074456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1179074456 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2236904340 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1412910000 ps |
| CPU time | 5.12 seconds |
| Started | Jun 25 04:42:06 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 165092 kb |
| Host | smart-14cfcf6a-3a3a-4b68-aa44-659cd0df67df |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2236904340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2236904340 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.585535810 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1601310000 ps |
| CPU time | 5.53 seconds |
| Started | Jun 25 04:41:58 PM PDT 24 |
| Finished | Jun 25 04:42:12 PM PDT 24 |
| Peak memory | 164312 kb |
| Host | smart-05ec2885-1d22-4f7e-848e-4d95e838cfb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=585535810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.585535810 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2136567238 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1488930000 ps |
| CPU time | 4.51 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:14 PM PDT 24 |
| Peak memory | 164540 kb |
| Host | smart-e77f70a1-2b37-4878-a797-6249601be111 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2136567238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2136567238 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.961354405 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1544910000 ps |
| CPU time | 5.07 seconds |
| Started | Jun 25 04:42:10 PM PDT 24 |
| Finished | Jun 25 04:42:22 PM PDT 24 |
| Peak memory | 164544 kb |
| Host | smart-510e5e88-838d-421d-905b-2ad077791e40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=961354405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.961354405 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2235773960 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1465350000 ps |
| CPU time | 5.13 seconds |
| Started | Jun 25 04:42:05 PM PDT 24 |
| Finished | Jun 25 04:42:19 PM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-3f20f690-7048-4a89-bd93-a34cda880015 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2235773960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2235773960 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.410534086 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1452330000 ps |
| CPU time | 4.17 seconds |
| Started | Jun 25 04:42:03 PM PDT 24 |
| Finished | Jun 25 04:42:14 PM PDT 24 |
| Peak memory | 164392 kb |
| Host | smart-4e939090-166d-457c-b750-f3ae305640a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=410534086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.410534086 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.832587944 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1358470000 ps |
| CPU time | 3.48 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:14 PM PDT 24 |
| Peak memory | 164536 kb |
| Host | smart-7a909dd6-6b40-443c-a994-72c62427f568 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=832587944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.832587944 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3834761944 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1513870000 ps |
| CPU time | 4.79 seconds |
| Started | Jun 25 04:42:04 PM PDT 24 |
| Finished | Jun 25 04:42:16 PM PDT 24 |
| Peak memory | 164352 kb |
| Host | smart-88414653-3b60-410a-95e8-0b82946170ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3834761944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3834761944 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3881096445 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1572110000 ps |
| CPU time | 4.29 seconds |
| Started | Jun 25 04:42:07 PM PDT 24 |
| Finished | Jun 25 04:42:18 PM PDT 24 |
| Peak memory | 164352 kb |
| Host | smart-52647315-9e4e-453d-a4ab-69c9453b00a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3881096445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3881096445 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.978146675 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1341490000 ps |
| CPU time | 4.8 seconds |
| Started | Jun 25 04:42:08 PM PDT 24 |
| Finished | Jun 25 04:42:20 PM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-049d4cbd-6ff5-462b-a3d5-ae27319e8040 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=978146675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.978146675 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.618402688 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1514970000 ps |
| CPU time | 5.23 seconds |
| Started | Jun 25 04:42:11 PM PDT 24 |
| Finished | Jun 25 04:42:23 PM PDT 24 |
| Peak memory | 164484 kb |
| Host | smart-a92e1016-0ece-4a06-91e2-25d876a153d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=618402688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.618402688 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1886303698 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1498570000 ps |
| CPU time | 3.96 seconds |
| Started | Jun 25 04:42:27 PM PDT 24 |
| Finished | Jun 25 04:42:37 PM PDT 24 |
| Peak memory | 164728 kb |
| Host | smart-36ae37dd-a92c-4f8a-acd7-95caaa884e79 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1886303698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1886303698 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2608132684 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1446390000 ps |
| CPU time | 4.78 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 163576 kb |
| Host | smart-57f6e494-ca45-4563-af6d-fe9742ee77c3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2608132684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2608132684 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2995063252 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1539410000 ps |
| CPU time | 5.01 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 164184 kb |
| Host | smart-ef38fe0b-ae28-43a8-8ee6-e7037f70c2a8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2995063252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2995063252 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1695610147 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1549370000 ps |
| CPU time | 4.69 seconds |
| Started | Jun 25 04:42:03 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 164232 kb |
| Host | smart-4b4f9e47-8c2a-4581-854a-f1a25bc1bc7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1695610147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1695610147 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2031361480 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1392930000 ps |
| CPU time | 3.65 seconds |
| Started | Jun 25 04:42:01 PM PDT 24 |
| Finished | Jun 25 04:42:10 PM PDT 24 |
| Peak memory | 164396 kb |
| Host | smart-4ce8af51-3163-4066-8822-99cad0e7b91d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2031361480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2031361480 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.813935922 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1443730000 ps |
| CPU time | 4.91 seconds |
| Started | Jun 25 04:42:02 PM PDT 24 |
| Finished | Jun 25 04:42:15 PM PDT 24 |
| Peak memory | 164276 kb |
| Host | smart-211ad1a9-954f-429d-b562-06bd2afb0e5c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=813935922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.813935922 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
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