| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.871659003 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1699656402 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1487019375 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2720127059 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1838339591 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.507776303 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.75676434 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4213442562 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1480493452 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3976821525 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4016172851 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1668400821 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.252533494 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3272612511 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1300613112 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3587421203 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1893743791 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1050616834 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2528064774 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1404789123 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3121696935 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1994505981 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2826091505 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1110922744 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2496393755 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3882090059 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2567133094 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.457627173 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2476625126 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2477221908 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2738384742 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1694411849 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.987120420 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2572219224 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3593552330 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1978261886 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1297522612 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2505759131 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3428417877 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1430944007 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2542216148 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3885302552 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1825417427 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3989020773 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3605254402 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.738901349 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1209657466 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2789914141 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2830329122 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1020668380 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1944006548 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.442259554 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4192860518 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3478541840 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3396722032 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.16515614 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3528110837 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2562322265 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4227057440 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2676506846 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2492077506 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4265929951 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1575493795 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2902488158 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3211638848 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2475716543 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2170667955 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2966109130 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2894428432 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4095267860 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2035736464 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3726452647 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3218665863 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3367851036 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2524701792 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3760651153 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1125984554 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.565453332 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2475629898 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1627339941 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.46612123 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1654572892 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3631276126 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3810638577 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.491995742 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2530705622 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1007483767 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1039734425 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3451110933 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1540716402 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3218351239 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3604768535 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2676005918 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3928358967 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3924294545 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1056251814 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1595109635 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1875187410 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3074856536 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2843803871 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3593685987 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.304707895 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2023068038 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1770546599 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1587536414 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2679496607 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2183101849 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2366696347 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3234813119 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3680971367 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1980478048 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4269903492 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1067882138 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.564977407 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.504454722 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4287739430 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2922352625 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.314617105 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3363919411 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.546608708 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4079770111 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.231568657 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.349519180 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4090647337 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3520656404 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3714504992 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1864095121 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2006340566 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.885018365 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4055009696 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2087125250 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1072706872 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3730764136 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2265953706 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1071126441 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.555019820 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.678670283 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3750756374 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2423165155 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1661052752 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1550090481 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1251393839 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4081602725 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1450829336 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.47879941 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1233562630 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1364562437 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.411050948 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.678345729 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1718973540 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2804492605 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.228635249 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3138655119 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2999190693 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1421493108 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2809844623 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4059559915 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.752701654 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1063556052 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.276157091 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2010323121 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2233926913 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.764416802 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.582484234 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2661523233 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1379104628 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2848034254 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1020438840 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1030032453 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1050316115 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1074964016 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1380472269 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2368434753 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1012137566 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3089401621 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2168846558 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2075342918 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2414157357 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2312805835 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2036896421 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1722172930 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2888839223 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1236306359 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2301557337 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3115784493 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.523705792 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4273681191 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.264265416 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2951138799 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.428040264 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4260425402 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1236159529 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.980696971 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2289234033 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3561485067 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.341956401 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2073088510 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.698855644 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2416943471 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3139847674 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3115784493 | Jun 27 05:43:54 PM PDT 24 | Jun 27 05:44:09 PM PDT 24 | 1507970000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.276157091 | Jun 27 05:44:26 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1555450000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1063556052 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:44 PM PDT 24 | 1145610000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2809844623 | Jun 27 05:44:26 PM PDT 24 | Jun 27 05:44:45 PM PDT 24 | 1424890000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.523705792 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:50 PM PDT 24 | 1603310000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2289234033 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:52 PM PDT 24 | 1472650000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1421493108 | Jun 27 05:44:23 PM PDT 24 | Jun 27 05:44:42 PM PDT 24 | 1311130000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.871659003 | Jun 27 05:44:26 PM PDT 24 | Jun 27 05:44:45 PM PDT 24 | 1346910000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2848034254 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:47 PM PDT 24 | 1370030000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2414157357 | Jun 27 05:44:31 PM PDT 24 | Jun 27 05:44:48 PM PDT 24 | 1366670000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.980696971 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:52 PM PDT 24 | 1540210000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3138655119 | Jun 27 05:43:54 PM PDT 24 | Jun 27 05:44:09 PM PDT 24 | 1486490000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.582484234 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1530170000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1236306359 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:50 PM PDT 24 | 1553370000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2951138799 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:50 PM PDT 24 | 1547350000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.764416802 | Jun 27 05:43:48 PM PDT 24 | Jun 27 05:44:01 PM PDT 24 | 1368310000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.264265416 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:48 PM PDT 24 | 1440390000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1030032453 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1502610000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1379104628 | Jun 27 05:44:28 PM PDT 24 | Jun 27 05:44:51 PM PDT 24 | 1524530000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3089401621 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:48 PM PDT 24 | 1263550000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2075342918 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:48 PM PDT 24 | 1453370000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3139847674 | Jun 27 05:44:25 PM PDT 24 | Jun 27 05:44:45 PM PDT 24 | 1458110000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.341956401 | Jun 27 05:43:53 PM PDT 24 | Jun 27 05:44:09 PM PDT 24 | 1350390000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2416943471 | Jun 27 05:44:24 PM PDT 24 | Jun 27 05:44:44 PM PDT 24 | 1472130000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1074964016 | Jun 27 05:44:28 PM PDT 24 | Jun 27 05:44:51 PM PDT 24 | 1487930000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2888839223 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:47 PM PDT 24 | 1519830000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1020438840 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:49 PM PDT 24 | 1580690000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4260425402 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:51 PM PDT 24 | 1564230000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2368434753 | Jun 27 05:44:28 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1595370000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3561485067 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:48 PM PDT 24 | 1384270000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.752701654 | Jun 27 05:44:25 PM PDT 24 | Jun 27 05:44:44 PM PDT 24 | 1353490000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1722172930 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:50 PM PDT 24 | 1507030000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2168846558 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:49 PM PDT 24 | 1516130000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4059559915 | Jun 27 05:44:25 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1528430000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1236159529 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:48 PM PDT 24 | 1371670000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1380472269 | Jun 27 05:44:32 PM PDT 24 | Jun 27 05:44:50 PM PDT 24 | 1554130000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2301557337 | Jun 27 05:44:30 PM PDT 24 | Jun 27 05:44:45 PM PDT 24 | 1517650000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1050316115 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1569550000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.228635249 | Jun 27 05:43:54 PM PDT 24 | Jun 27 05:44:08 PM PDT 24 | 1579810000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2073088510 | Jun 27 05:44:24 PM PDT 24 | Jun 27 05:44:41 PM PDT 24 | 1207810000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2312805835 | Jun 27 05:44:28 PM PDT 24 | Jun 27 05:44:44 PM PDT 24 | 1273210000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.428040264 | Jun 27 05:44:33 PM PDT 24 | Jun 27 05:44:51 PM PDT 24 | 1451150000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2999190693 | Jun 27 05:44:25 PM PDT 24 | Jun 27 05:44:45 PM PDT 24 | 1344490000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.698855644 | Jun 27 05:44:23 PM PDT 24 | Jun 27 05:44:41 PM PDT 24 | 1308490000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2661523233 | Jun 27 05:44:27 PM PDT 24 | Jun 27 05:44:45 PM PDT 24 | 1415890000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2010323121 | Jun 27 05:44:25 PM PDT 24 | Jun 27 05:44:46 PM PDT 24 | 1467870000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1012137566 | Jun 27 05:43:55 PM PDT 24 | Jun 27 05:44:09 PM PDT 24 | 1382210000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2233926913 | Jun 27 05:44:28 PM PDT 24 | Jun 27 05:44:51 PM PDT 24 | 1501030000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2036896421 | Jun 27 05:44:29 PM PDT 24 | Jun 27 05:44:47 PM PDT 24 | 1470370000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4273681191 | Jun 27 05:44:29 PM PDT 24 | Jun 27 05:44:47 PM PDT 24 | 1497930000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2265953706 | Jun 27 05:43:48 PM PDT 24 | Jun 27 05:43:57 PM PDT 24 | 1278530000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2804492605 | Jun 27 05:43:39 PM PDT 24 | Jun 27 05:43:54 PM PDT 24 | 1600990000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3714504992 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:49 PM PDT 24 | 1487510000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1587536414 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:50 PM PDT 24 | 1487670000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2183101849 | Jun 27 05:43:40 PM PDT 24 | Jun 27 05:43:53 PM PDT 24 | 1385550000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2366696347 | Jun 27 05:43:39 PM PDT 24 | Jun 27 05:43:54 PM PDT 24 | 1499270000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2720127059 | Jun 27 05:43:37 PM PDT 24 | Jun 27 05:43:48 PM PDT 24 | 1483030000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1067882138 | Jun 27 05:43:32 PM PDT 24 | Jun 27 05:43:45 PM PDT 24 | 1515010000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3750756374 | Jun 27 05:43:49 PM PDT 24 | Jun 27 05:43:59 PM PDT 24 | 1559910000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.546608708 | Jun 27 05:43:34 PM PDT 24 | Jun 27 05:43:46 PM PDT 24 | 1343150000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1718973540 | Jun 27 05:43:42 PM PDT 24 | Jun 27 05:43:52 PM PDT 24 | 1581290000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1251393839 | Jun 27 05:43:48 PM PDT 24 | Jun 27 05:43:59 PM PDT 24 | 1444550000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.504454722 | Jun 27 05:43:31 PM PDT 24 | Jun 27 05:43:44 PM PDT 24 | 1536550000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4090647337 | Jun 27 05:43:33 PM PDT 24 | Jun 27 05:43:46 PM PDT 24 | 1515350000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.678345729 | Jun 27 05:43:37 PM PDT 24 | Jun 27 05:43:48 PM PDT 24 | 1505150000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3520656404 | Jun 27 05:43:42 PM PDT 24 | Jun 27 05:43:52 PM PDT 24 | 1572390000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2087125250 | Jun 27 05:43:52 PM PDT 24 | Jun 27 05:44:06 PM PDT 24 | 1455270000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4055009696 | Jun 27 05:43:52 PM PDT 24 | Jun 27 05:44:03 PM PDT 24 | 1169290000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1364562437 | Jun 27 05:43:37 PM PDT 24 | Jun 27 05:43:47 PM PDT 24 | 1513350000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1864095121 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:49 PM PDT 24 | 1529310000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.411050948 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:51 PM PDT 24 | 1548050000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.349519180 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:48 PM PDT 24 | 1361930000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1661052752 | Jun 27 05:43:54 PM PDT 24 | Jun 27 05:44:08 PM PDT 24 | 1345570000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1980478048 | Jun 27 05:43:36 PM PDT 24 | Jun 27 05:43:49 PM PDT 24 | 1516450000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.314617105 | Jun 27 05:43:36 PM PDT 24 | Jun 27 05:43:47 PM PDT 24 | 1551970000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1770546599 | Jun 27 05:43:40 PM PDT 24 | Jun 27 05:43:52 PM PDT 24 | 1251790000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4079770111 | Jun 27 05:43:41 PM PDT 24 | Jun 27 05:43:51 PM PDT 24 | 1498830000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1071126441 | Jun 27 05:43:47 PM PDT 24 | Jun 27 05:43:56 PM PDT 24 | 1427130000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2922352625 | Jun 27 05:43:36 PM PDT 24 | Jun 27 05:43:47 PM PDT 24 | 1389090000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.231568657 | Jun 27 05:43:41 PM PDT 24 | Jun 27 05:43:51 PM PDT 24 | 1504810000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3730764136 | Jun 27 05:43:51 PM PDT 24 | Jun 27 05:44:05 PM PDT 24 | 1476730000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.885018365 | Jun 27 05:43:51 PM PDT 24 | Jun 27 05:44:04 PM PDT 24 | 1512430000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3363919411 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:50 PM PDT 24 | 1518770000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1072706872 | Jun 27 05:43:49 PM PDT 24 | Jun 27 05:43:57 PM PDT 24 | 1447770000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4269903492 | Jun 27 05:43:35 PM PDT 24 | Jun 27 05:43:45 PM PDT 24 | 1331070000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1550090481 | Jun 27 05:43:52 PM PDT 24 | Jun 27 05:44:04 PM PDT 24 | 1364910000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2023068038 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:50 PM PDT 24 | 1489450000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4081602725 | Jun 27 05:43:51 PM PDT 24 | Jun 27 05:44:04 PM PDT 24 | 1343630000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1233562630 | Jun 27 05:43:52 PM PDT 24 | Jun 27 05:44:06 PM PDT 24 | 1577850000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.47879941 | Jun 27 05:43:48 PM PDT 24 | Jun 27 05:43:57 PM PDT 24 | 1510850000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3234813119 | Jun 27 05:43:33 PM PDT 24 | Jun 27 05:43:46 PM PDT 24 | 1482650000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2006340566 | Jun 27 05:43:54 PM PDT 24 | Jun 27 05:44:09 PM PDT 24 | 1391490000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.678670283 | Jun 27 05:43:50 PM PDT 24 | Jun 27 05:44:00 PM PDT 24 | 1558430000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3680971367 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:50 PM PDT 24 | 1534810000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2423165155 | Jun 27 05:43:53 PM PDT 24 | Jun 27 05:44:08 PM PDT 24 | 1512810000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4287739430 | Jun 27 05:43:35 PM PDT 24 | Jun 27 05:43:47 PM PDT 24 | 1518190000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2679496607 | Jun 27 05:43:35 PM PDT 24 | Jun 27 05:43:47 PM PDT 24 | 1515270000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.555019820 | Jun 27 05:43:37 PM PDT 24 | Jun 27 05:43:48 PM PDT 24 | 1463890000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.564977407 | Jun 27 05:43:38 PM PDT 24 | Jun 27 05:43:51 PM PDT 24 | 1593730000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1450829336 | Jun 27 05:43:53 PM PDT 24 | Jun 27 05:44:09 PM PDT 24 | 1456890000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3924294545 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:17:47 PM PDT 24 | 336908070000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1699656402 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:21:00 PM PDT 24 | 337013130000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2530705622 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:21:16 PM PDT 24 | 336706310000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4265929951 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:07:50 PM PDT 24 | 336968830000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3396722032 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:16:09 PM PDT 24 | 336660530000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2676506846 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:19:15 PM PDT 24 | 337098630000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1875187410 | Jun 27 05:43:48 PM PDT 24 | Jun 27 06:16:55 PM PDT 24 | 336379370000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3604768535 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:18:05 PM PDT 24 | 336783330000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2676005918 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:20:54 PM PDT 24 | 337128210000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3478541840 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:19:29 PM PDT 24 | 336773310000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2843803871 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:15:59 PM PDT 24 | 336365890000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4095267860 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:16:05 PM PDT 24 | 336903730000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2492077506 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:15:05 PM PDT 24 | 337037050000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3631276126 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:11:15 PM PDT 24 | 336820730000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2902488158 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:22:32 PM PDT 24 | 336476350000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4227057440 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:19:31 PM PDT 24 | 336918790000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1007483767 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:21:28 PM PDT 24 | 336732630000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.304707895 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:22:13 PM PDT 24 | 336886670000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3528110837 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:18:12 PM PDT 24 | 336354870000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3810638577 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:16:31 PM PDT 24 | 336974070000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3218665863 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:18:31 PM PDT 24 | 336650390000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3760651153 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:15:48 PM PDT 24 | 336613050000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1056251814 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:17:41 PM PDT 24 | 336774650000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2170667955 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:20:59 PM PDT 24 | 336513330000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.46612123 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:18:10 PM PDT 24 | 336312690000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2562322265 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:15:40 PM PDT 24 | 336478410000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3211638848 | Jun 27 05:43:46 PM PDT 24 | Jun 27 06:12:12 PM PDT 24 | 337041550000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3451110933 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:22:04 PM PDT 24 | 336822370000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1627339941 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:19:24 PM PDT 24 | 336728210000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.16515614 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:15:37 PM PDT 24 | 336802510000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3367851036 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:20:54 PM PDT 24 | 336961130000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2475716543 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:16:22 PM PDT 24 | 336528010000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1654572892 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:21:13 PM PDT 24 | 336466770000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1039734425 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:21:17 PM PDT 24 | 336908790000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3928358967 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:18:09 PM PDT 24 | 336986590000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1575493795 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:22:28 PM PDT 24 | 337074430000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3593685987 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:21:51 PM PDT 24 | 336907710000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2966109130 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:15:10 PM PDT 24 | 336777610000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3726452647 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:20:58 PM PDT 24 | 337030090000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2524701792 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:17:39 PM PDT 24 | 336509070000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1540716402 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:16:04 PM PDT 24 | 337046550000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2894428432 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:15:19 PM PDT 24 | 336429090000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.491995742 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:20:36 PM PDT 24 | 336984010000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.565453332 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:22:15 PM PDT 24 | 336989730000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3218351239 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:20:58 PM PDT 24 | 336701790000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3074856536 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:18:55 PM PDT 24 | 336330170000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1125984554 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:17:37 PM PDT 24 | 336423630000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2035736464 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:15:32 PM PDT 24 | 337036870000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1595109635 | Jun 27 05:43:48 PM PDT 24 | Jun 27 06:13:38 PM PDT 24 | 336495750000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2475629898 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:20:46 PM PDT 24 | 337126090000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3976821525 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:14:05 PM PDT 24 | 336393450000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2830329122 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:18:45 PM PDT 24 | 336699590000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.738901349 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:13:34 PM PDT 24 | 336898490000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1487019375 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:16:12 PM PDT 24 | 336760710000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2477221908 | Jun 27 05:43:49 PM PDT 24 | Jun 27 06:18:30 PM PDT 24 | 336729130000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2542216148 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:15:37 PM PDT 24 | 336407510000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.987120420 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:19:27 PM PDT 24 | 336790250000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2505759131 | Jun 27 05:43:48 PM PDT 24 | Jun 27 06:15:00 PM PDT 24 | 336606190000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2826091505 | Jun 27 05:43:49 PM PDT 24 | Jun 27 06:15:33 PM PDT 24 | 336392510000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1430944007 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:19:31 PM PDT 24 | 336617910000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.507776303 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:17:44 PM PDT 24 | 336868770000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4213442562 | Jun 27 05:43:49 PM PDT 24 | Jun 27 06:12:41 PM PDT 24 | 336481090000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2789914141 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:16:04 PM PDT 24 | 336752370000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3605254402 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:14:50 PM PDT 24 | 337071690000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3587421203 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:18:40 PM PDT 24 | 336753830000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2476625126 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:18:51 PM PDT 24 | 336665950000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1944006548 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:17:49 PM PDT 24 | 336769330000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1825417427 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:19:12 PM PDT 24 | 336919030000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4016172851 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:17:58 PM PDT 24 | 337097070000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2496393755 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:17:17 PM PDT 24 | 336884750000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1838339591 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:18:34 PM PDT 24 | 336490270000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1050616834 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:16:48 PM PDT 24 | 336868810000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1020668380 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:18:38 PM PDT 24 | 336504150000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2567133094 | Jun 27 05:43:54 PM PDT 24 | Jun 27 06:18:34 PM PDT 24 | 336896770000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1404789123 | Jun 27 05:43:49 PM PDT 24 | Jun 27 06:18:33 PM PDT 24 | 336658150000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1978261886 | Jun 27 05:43:57 PM PDT 24 | Jun 27 06:19:32 PM PDT 24 | 337112510000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.75676434 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:15:26 PM PDT 24 | 336423350000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3885302552 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:15:33 PM PDT 24 | 336908010000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1994505981 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:19:45 PM PDT 24 | 337036610000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3882090059 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:13:30 PM PDT 24 | 336756150000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4192860518 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:17:52 PM PDT 24 | 336363050000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3428417877 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:15:46 PM PDT 24 | 336732750000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.457627173 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:19:07 PM PDT 24 | 336480270000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1209657466 | Jun 27 05:43:48 PM PDT 24 | Jun 27 06:16:09 PM PDT 24 | 336711570000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1110922744 | Jun 27 05:43:51 PM PDT 24 | Jun 27 06:15:15 PM PDT 24 | 336715410000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3121696935 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:17:04 PM PDT 24 | 336407410000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1300613112 | Jun 27 05:43:49 PM PDT 24 | Jun 27 06:17:53 PM PDT 24 | 336951490000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3593552330 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:16:21 PM PDT 24 | 336463130000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.252533494 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:20:47 PM PDT 24 | 337017590000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2528064774 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:19:39 PM PDT 24 | 336737010000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1480493452 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:19:49 PM PDT 24 | 336365950000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1694411849 | Jun 27 05:43:56 PM PDT 24 | Jun 27 06:19:38 PM PDT 24 | 336607690000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2572219224 | Jun 27 05:43:52 PM PDT 24 | Jun 27 06:16:42 PM PDT 24 | 336773630000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1297522612 | Jun 27 05:43:53 PM PDT 24 | Jun 27 06:16:23 PM PDT 24 | 336789190000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3272612511 | Jun 27 05:43:55 PM PDT 24 | Jun 27 06:15:51 PM PDT 24 | 336598550000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3989020773 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:14:42 PM PDT 24 | 336713590000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2738384742 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:16:47 PM PDT 24 | 336559430000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1668400821 | Jun 27 05:43:50 PM PDT 24 | Jun 27 06:15:48 PM PDT 24 | 336700490000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.442259554 | Jun 27 05:43:49 PM PDT 24 | Jun 27 06:11:52 PM PDT 24 | 336794230000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1893743791 | Jun 27 05:43:57 PM PDT 24 | Jun 27 06:19:28 PM PDT 24 | 336338910000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.871659003 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1346910000 ps |
| CPU time | 4.86 seconds |
| Started | Jun 27 05:44:26 PM PDT 24 |
| Finished | Jun 27 05:44:45 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-c34c4e4f-8315-47ca-8391-d0ca8fb2c589 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=871659003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.871659003 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1699656402 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 337013130000 ps |
| CPU time | 863 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:21:00 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-336afb94-fc50-4985-8ef5-15d5a0217a98 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1699656402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1699656402 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1487019375 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336760710000 ps |
| CPU time | 793.48 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:16:12 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-1834581e-4fc9-4bbb-b01b-420937dbef1a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1487019375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1487019375 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2720127059 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1483030000 ps |
| CPU time | 4.06 seconds |
| Started | Jun 27 05:43:37 PM PDT 24 |
| Finished | Jun 27 05:43:48 PM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-d95bcf0d-4930-449a-8da5-3f52e2146724 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2720127059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2720127059 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1838339591 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336490270000 ps |
| CPU time | 831.38 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:18:34 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-ab056716-1e21-469c-a2d1-985f76d81ddc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1838339591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1838339591 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.507776303 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336868770000 ps |
| CPU time | 814.45 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:17:44 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-6a252936-63a6-4ed2-b3dc-c2fbed42055b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=507776303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.507776303 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.75676434 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336423350000 ps |
| CPU time | 776.43 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:15:26 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-2b970a76-a5a0-4660-970d-111398b4c83b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=75676434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.75676434 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4213442562 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336481090000 ps |
| CPU time | 699.77 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 06:12:41 PM PDT 24 |
| Peak memory | 160764 kb |
| Host | smart-38b80d02-058e-4764-a632-0cf0157463af |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4213442562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.4213442562 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1480493452 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336365950000 ps |
| CPU time | 856.23 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:19:49 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-0ebcc2ae-dc9a-4873-b10c-302a7733a438 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1480493452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1480493452 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.3976821525 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336393450000 ps |
| CPU time | 734.66 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:14:05 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-5bff308e-b2a6-4be6-a05c-62204082a5d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3976821525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.3976821525 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.4016172851 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 337097070000 ps |
| CPU time | 834.64 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:17:58 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-1f3e357b-460d-4437-b59e-af72b7c8097a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4016172851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.4016172851 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1668400821 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336700490000 ps |
| CPU time | 785.72 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:15:48 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-f66e38fc-a5bc-4610-b7ab-ce33a9d5bbba |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1668400821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1668400821 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.252533494 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 337017590000 ps |
| CPU time | 903.78 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:20:47 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-ae536485-2637-4587-917f-3a64a994daa8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=252533494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.252533494 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3272612511 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336598550000 ps |
| CPU time | 779.68 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:15:51 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-2b7b0d03-79f9-4c08-8964-33f8bd94d7cc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3272612511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3272612511 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1300613112 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336951490000 ps |
| CPU time | 837.9 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 06:17:53 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-187f1527-5a77-4e81-bbc1-a9d589fb58e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1300613112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1300613112 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.3587421203 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336753830000 ps |
| CPU time | 834.77 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:18:40 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-b9d91e2d-35af-4f85-960f-ff84ee2f9999 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3587421203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.3587421203 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1893743791 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336338910000 ps |
| CPU time | 845.95 seconds |
| Started | Jun 27 05:43:57 PM PDT 24 |
| Finished | Jun 27 06:19:28 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-1455b6a4-6e41-4ae0-9703-1014f8ffdb46 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1893743791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1893743791 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1050616834 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336868810000 ps |
| CPU time | 797.62 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:16:48 PM PDT 24 |
| Peak memory | 160892 kb |
| Host | smart-022a2561-3a01-492f-8970-d8f9081e54c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1050616834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1050616834 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2528064774 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336737010000 ps |
| CPU time | 848.85 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:19:39 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-798eb606-e655-492d-b280-af3f20b5fa70 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2528064774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2528064774 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1404789123 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336658150000 ps |
| CPU time | 850.15 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 06:18:33 PM PDT 24 |
| Peak memory | 160864 kb |
| Host | smart-9321cd1a-5d49-443e-8984-903050849582 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1404789123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1404789123 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3121696935 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336407410000 ps |
| CPU time | 808.73 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:17:04 PM PDT 24 |
| Peak memory | 160908 kb |
| Host | smart-6941aa48-80a4-4b57-830c-1e5ae533d192 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3121696935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3121696935 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1994505981 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 337036610000 ps |
| CPU time | 855.59 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:19:45 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-2eaf3189-5bb4-45db-8df8-e7aa093db66a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1994505981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1994505981 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2826091505 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336392510000 ps |
| CPU time | 783.59 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 06:15:33 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-8e3a9dd6-e45e-41b8-881e-02e9d206b2cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2826091505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2826091505 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1110922744 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336715410000 ps |
| CPU time | 769.54 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:15:15 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-226e8eb5-731a-42ce-adc7-4b0f602e5b53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1110922744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1110922744 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2496393755 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336884750000 ps |
| CPU time | 834.48 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:17:17 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-22b9b0b5-431c-4376-8864-317664df23e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2496393755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2496393755 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3882090059 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336756150000 ps |
| CPU time | 718.61 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:13:30 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-7509251c-be41-4e24-8621-9ba3880c87a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3882090059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3882090059 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2567133094 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336896770000 ps |
| CPU time | 843.44 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:18:34 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-4686e64f-4708-4bdb-8651-507a84ab2565 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2567133094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2567133094 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.457627173 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336480270000 ps |
| CPU time | 858.96 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:19:07 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-1ff32367-6720-484b-8579-0a23619b4b1f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=457627173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.457627173 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.2476625126 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336665950000 ps |
| CPU time | 856.15 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:18:51 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-1ffdbbe3-7180-4e49-81ca-36bbbe72846a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2476625126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.2476625126 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2477221908 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336729130000 ps |
| CPU time | 847.06 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 06:18:30 PM PDT 24 |
| Peak memory | 160864 kb |
| Host | smart-3d03371a-d676-46ff-b99e-407d81a695ef |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2477221908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2477221908 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2738384742 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336559430000 ps |
| CPU time | 796.91 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:16:47 PM PDT 24 |
| Peak memory | 160892 kb |
| Host | smart-d0fc3d34-461b-4bba-8519-f1066b959808 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2738384742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2738384742 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1694411849 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336607690000 ps |
| CPU time | 851.71 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:19:38 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-7a6238b5-f20e-4fe9-9e6f-176d500ff982 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1694411849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1694411849 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.987120420 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336790250000 ps |
| CPU time | 869.61 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:19:27 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-e3b6a775-af62-48ad-a811-8d196af66479 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=987120420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.987120420 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2572219224 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 336773630000 ps |
| CPU time | 814.81 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:16:42 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-bb6bd988-0971-4f5d-ba9d-3ee0b9468607 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2572219224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2572219224 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3593552330 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336463130000 ps |
| CPU time | 802.69 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:16:21 PM PDT 24 |
| Peak memory | 160844 kb |
| Host | smart-7a3906b2-0eab-412e-b1f3-e9067bca4283 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3593552330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3593552330 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1978261886 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337112510000 ps |
| CPU time | 846.55 seconds |
| Started | Jun 27 05:43:57 PM PDT 24 |
| Finished | Jun 27 06:19:32 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-4fb28163-1088-4dc4-a1a5-7136f6cb5dde |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1978261886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1978261886 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.1297522612 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336789190000 ps |
| CPU time | 781.71 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:16:23 PM PDT 24 |
| Peak memory | 160892 kb |
| Host | smart-e42cd914-ac78-4bb8-98c2-1d83bada4717 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1297522612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.1297522612 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2505759131 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336606190000 ps |
| CPU time | 761.1 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 06:15:00 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-b944e666-05f2-4776-9090-b26bb02fa576 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2505759131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2505759131 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3428417877 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336732750000 ps |
| CPU time | 780.06 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:15:46 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-6ad541c7-5ab7-42b6-999f-c464676cd14f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3428417877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3428417877 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1430944007 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336617910000 ps |
| CPU time | 874.37 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:19:31 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-604b9ebd-60e7-4cc3-9d85-31b697e82325 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1430944007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1430944007 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2542216148 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336407510000 ps |
| CPU time | 782.87 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:15:37 PM PDT 24 |
| Peak memory | 160852 kb |
| Host | smart-0b514ffd-2670-4753-ba96-015af1bfa593 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2542216148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2542216148 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3885302552 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336908010000 ps |
| CPU time | 777.92 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:15:33 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-336c0c0f-727a-4f9a-8f36-736d833e5362 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3885302552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3885302552 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1825417427 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336919030000 ps |
| CPU time | 867.04 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:19:12 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-780ed3ab-80d0-4a4d-b9f8-b24d9b1308ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1825417427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1825417427 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3989020773 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336713590000 ps |
| CPU time | 751.21 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 06:14:42 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-a4aac127-bcf0-4c3a-bc0f-b6ed1a9dd660 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3989020773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3989020773 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3605254402 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 337071690000 ps |
| CPU time | 757.89 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:14:50 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-4817f65b-5d82-47fe-853d-11d7e6dff9bb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3605254402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3605254402 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.738901349 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336898490000 ps |
| CPU time | 726.1 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:13:34 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-d3d1d4df-6048-4df8-ab68-3adca9aa140e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=738901349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.738901349 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1209657466 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336711570000 ps |
| CPU time | 799.62 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 06:16:09 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-13e57925-2ae2-4aa0-a012-69084fab6a7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1209657466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1209657466 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2789914141 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336752370000 ps |
| CPU time | 786.15 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:16:04 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-5d9d6111-6afe-43c7-93e0-8cced1ef0fc1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2789914141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2789914141 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2830329122 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336699590000 ps |
| CPU time | 838.62 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:18:45 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-0c9565ec-0ad4-4faa-ab24-ef52a5873028 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2830329122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2830329122 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1020668380 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336504150000 ps |
| CPU time | 843.89 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:18:38 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-5c402a11-ce17-4d93-99d3-772dc5e59c7e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1020668380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1020668380 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1944006548 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336769330000 ps |
| CPU time | 820.32 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:17:49 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-d7858c24-5518-40f4-bb15-25babaaeee7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1944006548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1944006548 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.442259554 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336794230000 ps |
| CPU time | 687.86 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 06:11:52 PM PDT 24 |
| Peak memory | 160812 kb |
| Host | smart-7195f2b7-dbf7-41d4-929f-1fe5ae89b33a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=442259554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.442259554 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.4192860518 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336363050000 ps |
| CPU time | 825.82 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:17:52 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-fba52ba7-ea71-49f5-8661-7d3e5d7cc21b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4192860518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.4192860518 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3478541840 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336773310000 ps |
| CPU time | 865.14 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:19:29 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-e56818f0-ca61-4ed1-a82a-15167b7cb75e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3478541840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3478541840 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3396722032 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336660530000 ps |
| CPU time | 783.31 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:16:09 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-102430b4-774d-439f-8238-755ebcd76409 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3396722032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3396722032 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.16515614 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 336802510000 ps |
| CPU time | 750.78 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:15:37 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-7e4ce8fb-16f5-4bf9-b1b4-848445ad8410 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=16515614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.16515614 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3528110837 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 336354870000 ps |
| CPU time | 816.09 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:18:12 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-5cce5d42-5653-4662-a71d-2cb563e9b0c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3528110837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3528110837 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2562322265 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 336478410000 ps |
| CPU time | 757.54 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:15:40 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-eea989bf-e332-4fc0-8afe-8c6ed8f073e0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2562322265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2562322265 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.4227057440 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 336918790000 ps |
| CPU time | 855.99 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:19:31 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-642f092b-c193-4760-8ec9-90fc32fe667d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4227057440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.4227057440 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2676506846 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 337098630000 ps |
| CPU time | 850.34 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:19:15 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-e7d1af74-561e-4604-bf25-0a6a32390e8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2676506846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2676506846 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2492077506 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 337037050000 ps |
| CPU time | 752.99 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:15:05 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-630facb1-1109-4612-9dc3-d30ad09d100f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2492077506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2492077506 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4265929951 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336968830000 ps |
| CPU time | 563.33 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:07:50 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-bf302cae-72fc-49e1-92c7-6fbeba307465 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4265929951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4265929951 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1575493795 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 337074430000 ps |
| CPU time | 922.29 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:22:28 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-04e789e0-e9a9-4c9b-93d3-5af0a5b351cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1575493795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1575493795 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2902488158 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 336476350000 ps |
| CPU time | 920.2 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:22:32 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-d57da1d5-f218-4604-97ff-cbf376af70a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2902488158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.2902488158 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3211638848 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 337041550000 ps |
| CPU time | 693.6 seconds |
| Started | Jun 27 05:43:46 PM PDT 24 |
| Finished | Jun 27 06:12:12 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-6f254904-7868-4bda-8922-8c8b225b551c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3211638848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3211638848 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2475716543 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 336528010000 ps |
| CPU time | 784.73 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:16:22 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-356f1f1a-6c3b-4e1b-a895-77b7b2b1cfb4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2475716543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2475716543 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.2170667955 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 336513330000 ps |
| CPU time | 882.31 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:20:59 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-fe4213f0-c0fe-4259-814b-6958076bac20 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2170667955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.2170667955 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2966109130 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 336777610000 ps |
| CPU time | 757.55 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:15:10 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-cc5d8673-fc5c-484b-8fb4-3a64850686b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2966109130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2966109130 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2894428432 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 336429090000 ps |
| CPU time | 758 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:15:19 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-2b75341f-c203-43f9-9509-34334d87c1fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2894428432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2894428432 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.4095267860 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 336903730000 ps |
| CPU time | 779.21 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:16:05 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-0cab886c-f7df-4c6e-8e87-9036164ba8c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4095267860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.4095267860 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.2035736464 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 337036870000 ps |
| CPU time | 753.26 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:15:32 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-7f612dfd-0a73-4491-b3c1-e3a7ee6d6624 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2035736464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.2035736464 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.3726452647 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 337030090000 ps |
| CPU time | 862.06 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:20:58 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-4b79dbf2-94ef-4967-b7ae-da61a5c2745c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3726452647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.3726452647 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3218665863 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 336650390000 ps |
| CPU time | 827.01 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:18:31 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-051d8b49-d4d2-4415-9e55-4f9865740744 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3218665863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3218665863 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3367851036 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 336961130000 ps |
| CPU time | 905.8 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:20:54 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-e271fd6e-9363-4a74-a3e0-676ccd2963c2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3367851036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3367851036 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2524701792 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 336509070000 ps |
| CPU time | 811.98 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:17:39 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-ac359432-d922-4f14-b899-2d3757ccf911 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2524701792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2524701792 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3760651153 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 336613050000 ps |
| CPU time | 762.45 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:15:48 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-fb9544b4-b153-41a7-b22d-026629501534 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3760651153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3760651153 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1125984554 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 336423630000 ps |
| CPU time | 814.03 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:17:37 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-880a50c1-482b-44a8-81a5-7dffc57d1192 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1125984554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1125984554 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.565453332 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 336989730000 ps |
| CPU time | 909.7 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:22:15 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-44ac4f02-4157-4a08-874a-5fb618faa667 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=565453332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.565453332 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2475629898 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 337126090000 ps |
| CPU time | 868.38 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:20:46 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-dc6d83e7-1d6a-41c5-af38-d20ece69fb8f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2475629898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2475629898 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1627339941 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 336728210000 ps |
| CPU time | 861.33 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:19:24 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-49db3e8e-12af-4763-b67d-be218d793559 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1627339941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1627339941 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.46612123 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 336312690000 ps |
| CPU time | 811.72 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:18:10 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-88078565-5df7-4b7f-8fd3-27aef4421aea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=46612123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.46612123 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1654572892 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 336466770000 ps |
| CPU time | 855.47 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:21:13 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-91e38f2d-9248-4b26-979a-c01169e397d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1654572892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1654572892 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.3631276126 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 336820730000 ps |
| CPU time | 668.42 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:11:15 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-a9d7f64d-2819-43c3-9606-ed30f2bc0fce |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3631276126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.3631276126 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.3810638577 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 336974070000 ps |
| CPU time | 788.3 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:16:31 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-490b92c4-721a-4d72-9cb9-e7edb744416b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3810638577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.3810638577 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.491995742 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 336984010000 ps |
| CPU time | 861.03 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:20:36 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-770210df-52ec-475f-8483-ffe748e59808 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=491995742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.491995742 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2530705622 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336706310000 ps |
| CPU time | 868.42 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:21:16 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-c765a867-9f06-4fb5-9083-6c34f8e93e88 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2530705622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2530705622 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.1007483767 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 336732630000 ps |
| CPU time | 866.16 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:21:28 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-8199cbdb-2e75-46bb-b3f6-492f22e81c95 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1007483767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.1007483767 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1039734425 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 336908790000 ps |
| CPU time | 868.5 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:21:17 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-553cc4e1-0492-4116-9389-44492e69fb91 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1039734425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1039734425 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3451110933 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 336822370000 ps |
| CPU time | 895.31 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:22:04 PM PDT 24 |
| Peak memory | 160828 kb |
| Host | smart-076f3f88-e99d-48f7-9a9a-8a956fa16f66 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3451110933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3451110933 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1540716402 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 337046550000 ps |
| CPU time | 760.62 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:16:04 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-90494e5b-7ae3-4985-ab73-42e40d353435 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1540716402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1540716402 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3218351239 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 336701790000 ps |
| CPU time | 881.54 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:20:58 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-bf8d9397-8690-45e4-bb74-a7ef3de760d2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3218351239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3218351239 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3604768535 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336783330000 ps |
| CPU time | 823.83 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:18:05 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-d66184b9-2a12-48b5-9d53-31aba500147a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3604768535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3604768535 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2676005918 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 337128210000 ps |
| CPU time | 869.74 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:20:54 PM PDT 24 |
| Peak memory | 160816 kb |
| Host | smart-a3088c4b-7e02-488c-9062-13513e8b44cc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2676005918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2676005918 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3928358967 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 336986590000 ps |
| CPU time | 824.74 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 06:18:09 PM PDT 24 |
| Peak memory | 160832 kb |
| Host | smart-72ac0eb8-6e70-4c36-9a5d-bba2f6048297 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3928358967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3928358967 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3924294545 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336908070000 ps |
| CPU time | 812.7 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 06:17:47 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-b77d0ece-4c94-4c66-9d7b-e0725b2b3c60 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3924294545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3924294545 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1056251814 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 336774650000 ps |
| CPU time | 814.49 seconds |
| Started | Jun 27 05:43:56 PM PDT 24 |
| Finished | Jun 27 06:17:41 PM PDT 24 |
| Peak memory | 160840 kb |
| Host | smart-46101308-93c5-472f-a696-e5ef7c8a8bfd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1056251814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1056251814 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.1595109635 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 336495750000 ps |
| CPU time | 729.55 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 06:13:38 PM PDT 24 |
| Peak memory | 160824 kb |
| Host | smart-a0d82b46-a8f9-4fcf-be64-1a4d58ce5c57 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1595109635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.1595109635 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1875187410 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336379370000 ps |
| CPU time | 806.55 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 06:16:55 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-b633a215-7ed1-418c-86ca-fb9dd4154269 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1875187410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1875187410 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.3074856536 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 336330170000 ps |
| CPU time | 826.27 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 06:18:55 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-2f087b83-8e39-4f44-b927-247defbb24fc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3074856536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.3074856536 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2843803871 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 336365890000 ps |
| CPU time | 762.52 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 06:15:59 PM PDT 24 |
| Peak memory | 160808 kb |
| Host | smart-5b4da1fd-9e88-4d91-adf5-40726710744e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2843803871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2843803871 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3593685987 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 336907710000 ps |
| CPU time | 898.66 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:21:51 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-67c06bdf-9e47-4fab-93f0-51d98abc4a62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3593685987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3593685987 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.304707895 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 336886670000 ps |
| CPU time | 909.83 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 06:22:13 PM PDT 24 |
| Peak memory | 160820 kb |
| Host | smart-ac9e44bb-cfdb-4d21-8ec0-1f6e2ae0fd7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=304707895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.304707895 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2023068038 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1489450000 ps |
| CPU time | 4.43 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:50 PM PDT 24 |
| Peak memory | 164932 kb |
| Host | smart-067026f0-4362-45bc-b886-1c2cf6853647 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2023068038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2023068038 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1770546599 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1251790000 ps |
| CPU time | 4.84 seconds |
| Started | Jun 27 05:43:40 PM PDT 24 |
| Finished | Jun 27 05:43:52 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-bb9df7be-c9a6-4d12-a21a-575e1fcc873d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1770546599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1770546599 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1587536414 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1487670000 ps |
| CPU time | 4.59 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:50 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-60875f53-d474-41a0-b1e8-6a9c655b4525 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1587536414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1587536414 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2679496607 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1515270000 ps |
| CPU time | 4.61 seconds |
| Started | Jun 27 05:43:35 PM PDT 24 |
| Finished | Jun 27 05:43:47 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-372bff3f-c2aa-42d1-988d-e003dec7e705 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2679496607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2679496607 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2183101849 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1385550000 ps |
| CPU time | 5.41 seconds |
| Started | Jun 27 05:43:40 PM PDT 24 |
| Finished | Jun 27 05:43:53 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-060402c1-8984-4149-850b-9d24cab48794 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2183101849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2183101849 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2366696347 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1499270000 ps |
| CPU time | 5.61 seconds |
| Started | Jun 27 05:43:39 PM PDT 24 |
| Finished | Jun 27 05:43:54 PM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-3ceb43a0-51e0-4e4a-ad61-c7fa0f9e41b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2366696347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2366696347 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3234813119 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1482650000 ps |
| CPU time | 4.97 seconds |
| Started | Jun 27 05:43:33 PM PDT 24 |
| Finished | Jun 27 05:43:46 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-76d592da-753e-4aa7-8b00-5a082afd7661 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3234813119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.3234813119 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3680971367 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1534810000 ps |
| CPU time | 4.54 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:50 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-873ea964-e7c6-42fe-8f27-6f1a14e093e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3680971367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3680971367 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1980478048 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1516450000 ps |
| CPU time | 5.07 seconds |
| Started | Jun 27 05:43:36 PM PDT 24 |
| Finished | Jun 27 05:43:49 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-93af4a91-5647-4878-bebd-577405db5d9a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1980478048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1980478048 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.4269903492 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1331070000 ps |
| CPU time | 4.01 seconds |
| Started | Jun 27 05:43:35 PM PDT 24 |
| Finished | Jun 27 05:43:45 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-c02e8a09-41ca-40f7-a985-981bbdd4bdc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4269903492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.4269903492 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1067882138 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1515010000 ps |
| CPU time | 4.9 seconds |
| Started | Jun 27 05:43:32 PM PDT 24 |
| Finished | Jun 27 05:43:45 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-b85b4d04-c275-4fa9-802a-de810b3f681c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1067882138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1067882138 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.564977407 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1593730000 ps |
| CPU time | 4.84 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:51 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-4a74c817-8970-49ba-8224-652b4ac839a5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=564977407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.564977407 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.504454722 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1536550000 ps |
| CPU time | 4.89 seconds |
| Started | Jun 27 05:43:31 PM PDT 24 |
| Finished | Jun 27 05:43:44 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-2b280b48-9205-42f2-ba2a-0b93d90fd61e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=504454722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.504454722 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4287739430 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1518190000 ps |
| CPU time | 4.52 seconds |
| Started | Jun 27 05:43:35 PM PDT 24 |
| Finished | Jun 27 05:43:47 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-b61f9a86-dfe6-44f3-be65-9a9156b6896d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4287739430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4287739430 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2922352625 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1389090000 ps |
| CPU time | 4.48 seconds |
| Started | Jun 27 05:43:36 PM PDT 24 |
| Finished | Jun 27 05:43:47 PM PDT 24 |
| Peak memory | 164924 kb |
| Host | smart-f88d235a-eb72-4356-b925-9c224cdc2a3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2922352625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2922352625 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.314617105 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1551970000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 27 05:43:36 PM PDT 24 |
| Finished | Jun 27 05:43:47 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-032947b8-8f26-4831-9a30-bf3addf1e29b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=314617105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.314617105 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.3363919411 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1518770000 ps |
| CPU time | 4.68 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:50 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-5cc7ffb2-41e5-4e49-b103-62206219ed20 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3363919411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.3363919411 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.546608708 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1343150000 ps |
| CPU time | 4.52 seconds |
| Started | Jun 27 05:43:34 PM PDT 24 |
| Finished | Jun 27 05:43:46 PM PDT 24 |
| Peak memory | 164912 kb |
| Host | smart-843ed25f-9aa0-4a7a-8add-7f757e8d17e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=546608708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.546608708 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4079770111 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1498830000 ps |
| CPU time | 4.11 seconds |
| Started | Jun 27 05:43:41 PM PDT 24 |
| Finished | Jun 27 05:43:51 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-d19bf2f0-0545-4665-8364-050c90c89201 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4079770111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4079770111 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.231568657 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1504810000 ps |
| CPU time | 3.98 seconds |
| Started | Jun 27 05:43:41 PM PDT 24 |
| Finished | Jun 27 05:43:51 PM PDT 24 |
| Peak memory | 164884 kb |
| Host | smart-559f8daa-0e39-49b8-9a20-2de416fe329f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=231568657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.231568657 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.349519180 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1361930000 ps |
| CPU time | 4.09 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:48 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-bcae0621-5304-44ca-bf77-54adb051166d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=349519180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.349519180 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.4090647337 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1515350000 ps |
| CPU time | 4.92 seconds |
| Started | Jun 27 05:43:33 PM PDT 24 |
| Finished | Jun 27 05:43:46 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-4d32ec1c-431b-494d-8c84-baf1e0098ec0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4090647337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.4090647337 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.3520656404 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1572390000 ps |
| CPU time | 4.24 seconds |
| Started | Jun 27 05:43:42 PM PDT 24 |
| Finished | Jun 27 05:43:52 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-30501207-cc81-4d79-8db8-5a7584967273 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3520656404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.3520656404 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3714504992 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1487510000 ps |
| CPU time | 4.41 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:49 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-f6bcaae9-270a-48eb-beff-4682ee24be38 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3714504992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3714504992 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1864095121 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1529310000 ps |
| CPU time | 4.39 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:49 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-82025f45-3cfb-448b-8669-2147ebbc4566 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1864095121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1864095121 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2006340566 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1391490000 ps |
| CPU time | 4.6 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 05:44:09 PM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-157ea3d6-f08a-4902-9e53-438c2b90c9f9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2006340566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2006340566 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.885018365 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1512430000 ps |
| CPU time | 4.32 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 05:44:04 PM PDT 24 |
| Peak memory | 164956 kb |
| Host | smart-5268529f-c254-4c75-baac-9d9fcfab7aad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=885018365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.885018365 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4055009696 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1169290000 ps |
| CPU time | 3.32 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 05:44:03 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-a32c993b-a8b2-453e-bf8e-cffead330ae4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4055009696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4055009696 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2087125250 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1455270000 ps |
| CPU time | 4.25 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 05:44:06 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-302c6e0e-e0ce-4fcc-8333-36d2a945f306 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2087125250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2087125250 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1072706872 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1447770000 ps |
| CPU time | 2.93 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 05:43:57 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-ae6b637e-c464-43cd-bfcf-d2c3d9d0f320 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1072706872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1072706872 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.3730764136 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1476730000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 05:44:05 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-5fcd331e-0ebd-4f7a-a79b-b412c1c8c44b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3730764136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.3730764136 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2265953706 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1278530000 ps |
| CPU time | 3.16 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 05:43:57 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-f3437dc1-8b2c-4e03-8fdf-1aa7b7d5643f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2265953706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2265953706 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1071126441 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1427130000 ps |
| CPU time | 3.49 seconds |
| Started | Jun 27 05:43:47 PM PDT 24 |
| Finished | Jun 27 05:43:56 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-4fa9983e-1d79-4cf9-9f85-192135553bad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1071126441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1071126441 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.555019820 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1463890000 ps |
| CPU time | 4.18 seconds |
| Started | Jun 27 05:43:37 PM PDT 24 |
| Finished | Jun 27 05:43:48 PM PDT 24 |
| Peak memory | 164808 kb |
| Host | smart-dcf53972-262a-4697-a184-6236c5ad6f6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=555019820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.555019820 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.678670283 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1558430000 ps |
| CPU time | 3.39 seconds |
| Started | Jun 27 05:43:50 PM PDT 24 |
| Finished | Jun 27 05:44:00 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-3718d36e-4794-4f82-81b5-52a2024bbd53 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=678670283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.678670283 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3750756374 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1559910000 ps |
| CPU time | 3.79 seconds |
| Started | Jun 27 05:43:49 PM PDT 24 |
| Finished | Jun 27 05:43:59 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-5de3ecf9-c73c-488f-a675-c4968aee46e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3750756374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3750756374 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2423165155 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1512810000 ps |
| CPU time | 4.59 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 05:44:08 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-e4acdd5d-1e2b-4bbe-9bce-2a8f2b8e1059 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2423165155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2423165155 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1661052752 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1345570000 ps |
| CPU time | 4.29 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 05:44:08 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-6805b357-23fb-4ac2-9210-91b1a779024b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1661052752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1661052752 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1550090481 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1364910000 ps |
| CPU time | 3.81 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 05:44:04 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-b19e5958-7450-4076-90b9-9c21f8b0ca81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1550090481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1550090481 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1251393839 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1444550000 ps |
| CPU time | 4.76 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 05:43:59 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-5730ddcc-427b-4559-8632-8db9dfa1a254 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1251393839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1251393839 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4081602725 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1343630000 ps |
| CPU time | 4.09 seconds |
| Started | Jun 27 05:43:51 PM PDT 24 |
| Finished | Jun 27 05:44:04 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-5b646ed2-a9b2-48d4-a4d8-ce30829fa846 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4081602725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4081602725 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1450829336 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1456890000 ps |
| CPU time | 4.69 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 05:44:09 PM PDT 24 |
| Peak memory | 164936 kb |
| Host | smart-c2a1ccc5-612a-4da4-a1fb-b26272150107 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1450829336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1450829336 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.47879941 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1510850000 ps |
| CPU time | 3.45 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 05:43:57 PM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-69af3bc8-893d-4cb2-9fa0-e2eee4759348 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=47879941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.47879941 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1233562630 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1577850000 ps |
| CPU time | 4.55 seconds |
| Started | Jun 27 05:43:52 PM PDT 24 |
| Finished | Jun 27 05:44:06 PM PDT 24 |
| Peak memory | 164960 kb |
| Host | smart-ab848177-da46-49ba-bc61-467919a4994c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1233562630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1233562630 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1364562437 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1513350000 ps |
| CPU time | 3.64 seconds |
| Started | Jun 27 05:43:37 PM PDT 24 |
| Finished | Jun 27 05:43:47 PM PDT 24 |
| Peak memory | 164916 kb |
| Host | smart-da57978a-0839-4ddf-b7aa-5f4a8081193d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1364562437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1364562437 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.411050948 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1548050000 ps |
| CPU time | 4.92 seconds |
| Started | Jun 27 05:43:38 PM PDT 24 |
| Finished | Jun 27 05:43:51 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-bd2830b1-5da5-4420-828b-1f9a55ae2152 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=411050948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.411050948 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.678345729 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1505150000 ps |
| CPU time | 4.39 seconds |
| Started | Jun 27 05:43:37 PM PDT 24 |
| Finished | Jun 27 05:43:48 PM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-3325f2a8-e5ab-4a9b-ae1e-5dc01c7bdcf0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=678345729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.678345729 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1718973540 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1581290000 ps |
| CPU time | 4.22 seconds |
| Started | Jun 27 05:43:42 PM PDT 24 |
| Finished | Jun 27 05:43:52 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-f8919351-c759-4f38-9f83-94eddd4ebae5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1718973540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1718973540 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2804492605 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1600990000 ps |
| CPU time | 5.73 seconds |
| Started | Jun 27 05:43:39 PM PDT 24 |
| Finished | Jun 27 05:43:54 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-08293146-0baf-453e-9e84-31e85d6f55ce |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2804492605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2804492605 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.228635249 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1579810000 ps |
| CPU time | 4.43 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 05:44:08 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-18a5bc49-7cf8-49d1-97b6-c8cc2540270c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=228635249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.228635249 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3138655119 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1486490000 ps |
| CPU time | 4.82 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 05:44:09 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-81b1544c-baa9-4cd3-96c1-d57bb9d5a345 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3138655119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3138655119 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2999190693 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1344490000 ps |
| CPU time | 5.02 seconds |
| Started | Jun 27 05:44:25 PM PDT 24 |
| Finished | Jun 27 05:44:45 PM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-e7434d76-43d4-4bed-87de-d17335f4cbb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2999190693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2999190693 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1421493108 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1311130000 ps |
| CPU time | 5.2 seconds |
| Started | Jun 27 05:44:23 PM PDT 24 |
| Finished | Jun 27 05:44:42 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-24a5dda1-955b-4921-ab4b-0963e9ae1f71 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1421493108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1421493108 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2809844623 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1424890000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 27 05:44:26 PM PDT 24 |
| Finished | Jun 27 05:44:45 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-b7599c36-7211-4191-b854-a58a71cbc107 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2809844623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2809844623 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.4059559915 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1528430000 ps |
| CPU time | 5.19 seconds |
| Started | Jun 27 05:44:25 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164964 kb |
| Host | smart-3b287c5f-72cf-4bb9-9dc2-93b6d3e707c3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4059559915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.4059559915 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.752701654 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1353490000 ps |
| CPU time | 4.32 seconds |
| Started | Jun 27 05:44:25 PM PDT 24 |
| Finished | Jun 27 05:44:44 PM PDT 24 |
| Peak memory | 164992 kb |
| Host | smart-f5731fee-5358-4465-b8b2-fcaf611383d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=752701654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.752701654 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1063556052 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1145610000 ps |
| CPU time | 3.68 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:44 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-b540e3e6-405c-4b2a-bd4b-404bd58aabbc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1063556052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1063556052 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.276157091 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1555450000 ps |
| CPU time | 5.19 seconds |
| Started | Jun 27 05:44:26 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-2c7571d5-2331-45db-b540-59e09e7c15d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=276157091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.276157091 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2010323121 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1467870000 ps |
| CPU time | 5.36 seconds |
| Started | Jun 27 05:44:25 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-8bc1ad67-c308-418b-a290-936dce291376 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2010323121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2010323121 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2233926913 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1501030000 ps |
| CPU time | 6.33 seconds |
| Started | Jun 27 05:44:28 PM PDT 24 |
| Finished | Jun 27 05:44:51 PM PDT 24 |
| Peak memory | 165052 kb |
| Host | smart-fff68358-f7c7-4878-9ef3-b04a81409bed |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2233926913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2233926913 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.764416802 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1368310000 ps |
| CPU time | 5.81 seconds |
| Started | Jun 27 05:43:48 PM PDT 24 |
| Finished | Jun 27 05:44:01 PM PDT 24 |
| Peak memory | 164828 kb |
| Host | smart-3081727f-4c3b-4708-9ac1-945f3373c27d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=764416802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.764416802 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.582484234 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1530170000 ps |
| CPU time | 4.22 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-131430c2-9e4a-4113-a014-f2a4e18533bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=582484234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.582484234 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2661523233 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1415890000 ps |
| CPU time | 4.19 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:45 PM PDT 24 |
| Peak memory | 164944 kb |
| Host | smart-2a9e2f37-f010-456a-86e9-6f3de2dcc3ae |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2661523233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.2661523233 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1379104628 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1524530000 ps |
| CPU time | 6.31 seconds |
| Started | Jun 27 05:44:28 PM PDT 24 |
| Finished | Jun 27 05:44:51 PM PDT 24 |
| Peak memory | 165052 kb |
| Host | smart-494eef56-5273-4940-a989-1bd931a51cdc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1379104628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1379104628 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2848034254 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1370030000 ps |
| CPU time | 4.95 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:47 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-64539db1-6d4d-4c20-8cdc-2884d706f4bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2848034254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2848034254 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1020438840 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1580690000 ps |
| CPU time | 4.3 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:49 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-67b7da07-1a6a-4f2c-aae2-c46877d91676 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1020438840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1020438840 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.1030032453 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1502610000 ps |
| CPU time | 4.71 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-97b23558-d3de-4c83-a495-5eadc8abafa2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1030032453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.1030032453 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1050316115 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1569550000 ps |
| CPU time | 4.48 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-0f170f52-56ea-4ed6-9bb9-08120a6a83f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1050316115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1050316115 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1074964016 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1487930000 ps |
| CPU time | 6.14 seconds |
| Started | Jun 27 05:44:28 PM PDT 24 |
| Finished | Jun 27 05:44:51 PM PDT 24 |
| Peak memory | 165052 kb |
| Host | smart-26313b70-a3ad-45c5-8b1d-43fc4f091923 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1074964016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1074964016 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1380472269 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1554130000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:50 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-a59c9311-c68b-4224-8787-71fe532ac4fd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1380472269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1380472269 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2368434753 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1595370000 ps |
| CPU time | 4.19 seconds |
| Started | Jun 27 05:44:28 PM PDT 24 |
| Finished | Jun 27 05:44:46 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-bc49c895-8d75-404b-9b42-eee48cd4b98b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2368434753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2368434753 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1012137566 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1382210000 ps |
| CPU time | 4.34 seconds |
| Started | Jun 27 05:43:55 PM PDT 24 |
| Finished | Jun 27 05:44:09 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-0e93dfb4-817d-49e9-936a-723a28ba4156 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1012137566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1012137566 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.3089401621 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1263550000 ps |
| CPU time | 4.29 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:48 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-788bcaff-1826-4c25-b9ad-d6960aa59664 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3089401621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.3089401621 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2168846558 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1516130000 ps |
| CPU time | 4.63 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:49 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-9988f202-48da-449c-ac33-2a0aea55db1d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2168846558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2168846558 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2075342918 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1453370000 ps |
| CPU time | 4.17 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:48 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-1ab9f75f-54a0-4f13-800e-7a2a8d68c824 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2075342918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2075342918 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2414157357 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1366670000 ps |
| CPU time | 4.19 seconds |
| Started | Jun 27 05:44:31 PM PDT 24 |
| Finished | Jun 27 05:44:48 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-3a74483f-59fc-442f-b895-e79e6e032213 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2414157357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2414157357 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2312805835 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1273210000 ps |
| CPU time | 3.58 seconds |
| Started | Jun 27 05:44:28 PM PDT 24 |
| Finished | Jun 27 05:44:44 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-c91aaac4-4233-4ef2-b786-7570bff7ef6b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2312805835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2312805835 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2036896421 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1470370000 ps |
| CPU time | 4.33 seconds |
| Started | Jun 27 05:44:29 PM PDT 24 |
| Finished | Jun 27 05:44:47 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-9685e97c-8ea4-4d52-98d6-5b67311d647a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2036896421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2036896421 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1722172930 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1507030000 ps |
| CPU time | 4.62 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:50 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-6bf245d3-8bca-40cd-9c6e-000c7dbd9868 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1722172930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1722172930 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2888839223 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1519830000 ps |
| CPU time | 6.11 seconds |
| Started | Jun 27 05:44:27 PM PDT 24 |
| Finished | Jun 27 05:44:47 PM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-22ae737a-11d5-48af-a360-983274c0bace |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2888839223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2888839223 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1236306359 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1553370000 ps |
| CPU time | 4.83 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:50 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-aead4a3a-6fdc-4f66-98cc-0ff449145072 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1236306359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1236306359 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2301557337 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1517650000 ps |
| CPU time | 3.53 seconds |
| Started | Jun 27 05:44:30 PM PDT 24 |
| Finished | Jun 27 05:44:45 PM PDT 24 |
| Peak memory | 164972 kb |
| Host | smart-37240f55-0c13-43b0-9f02-b77e8156cc9f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2301557337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2301557337 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3115784493 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1507970000 ps |
| CPU time | 4.47 seconds |
| Started | Jun 27 05:43:54 PM PDT 24 |
| Finished | Jun 27 05:44:09 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-424a4d5e-331d-4f88-83f7-e29dd0d8562b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3115784493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3115784493 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.523705792 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1603310000 ps |
| CPU time | 5.02 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:50 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-04ce939f-9ea0-485c-acc6-e476bc522421 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=523705792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.523705792 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4273681191 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1497930000 ps |
| CPU time | 4.5 seconds |
| Started | Jun 27 05:44:29 PM PDT 24 |
| Finished | Jun 27 05:44:47 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-185c5f53-2376-4b97-b098-501ce73d7c8b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4273681191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4273681191 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.264265416 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1440390000 ps |
| CPU time | 3.8 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:48 PM PDT 24 |
| Peak memory | 164896 kb |
| Host | smart-1dd60f57-6269-4272-af20-9cf8fde8fe18 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=264265416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.264265416 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2951138799 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1547350000 ps |
| CPU time | 4.44 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:50 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-f2915d14-76eb-4599-85c1-7538673900ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2951138799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2951138799 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.428040264 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1451150000 ps |
| CPU time | 4.78 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:51 PM PDT 24 |
| Peak memory | 164904 kb |
| Host | smart-bade158f-b79d-4328-bf43-3cd901e2d95e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=428040264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.428040264 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4260425402 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1564230000 ps |
| CPU time | 4.88 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:51 PM PDT 24 |
| Peak memory | 164908 kb |
| Host | smart-227d988b-fd6a-497d-9250-e482674482b7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4260425402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4260425402 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1236159529 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1371670000 ps |
| CPU time | 4.05 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:48 PM PDT 24 |
| Peak memory | 164900 kb |
| Host | smart-af0ef56f-9404-49ff-a59d-bd5e11d1a181 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1236159529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1236159529 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.980696971 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1540210000 ps |
| CPU time | 5.7 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:52 PM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-2472cb9c-7e82-40fb-869e-f2bb1c7c537e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=980696971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.980696971 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2289234033 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1472650000 ps |
| CPU time | 5.41 seconds |
| Started | Jun 27 05:44:33 PM PDT 24 |
| Finished | Jun 27 05:44:52 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-290abd12-0d56-4f59-9732-c410001ee061 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2289234033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2289234033 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3561485067 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1384270000 ps |
| CPU time | 4.19 seconds |
| Started | Jun 27 05:44:32 PM PDT 24 |
| Finished | Jun 27 05:44:48 PM PDT 24 |
| Peak memory | 164976 kb |
| Host | smart-a146864a-4fbd-46cb-bd26-b3f4a8fb626d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3561485067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3561485067 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.341956401 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1350390000 ps |
| CPU time | 4.7 seconds |
| Started | Jun 27 05:43:53 PM PDT 24 |
| Finished | Jun 27 05:44:09 PM PDT 24 |
| Peak memory | 164888 kb |
| Host | smart-0f5dfb71-f1ed-40d6-b8b4-20745bd32880 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=341956401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.341956401 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2073088510 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1207810000 ps |
| CPU time | 3.62 seconds |
| Started | Jun 27 05:44:24 PM PDT 24 |
| Finished | Jun 27 05:44:41 PM PDT 24 |
| Peak memory | 164940 kb |
| Host | smart-00b5312e-4f40-467c-b06d-3efa45260804 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2073088510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2073088510 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.698855644 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1308490000 ps |
| CPU time | 4.71 seconds |
| Started | Jun 27 05:44:23 PM PDT 24 |
| Finished | Jun 27 05:44:41 PM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-9bb96c82-db3e-4e5a-8dc3-0fbbbad2e009 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=698855644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.698855644 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.2416943471 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1472130000 ps |
| CPU time | 4.82 seconds |
| Started | Jun 27 05:44:24 PM PDT 24 |
| Finished | Jun 27 05:44:44 PM PDT 24 |
| Peak memory | 164968 kb |
| Host | smart-6c8535e5-8a64-431d-b088-23218dd9c64c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2416943471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.2416943471 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3139847674 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1458110000 ps |
| CPU time | 5.5 seconds |
| Started | Jun 27 05:44:25 PM PDT 24 |
| Finished | Jun 27 05:44:45 PM PDT 24 |
| Peak memory | 164920 kb |
| Host | smart-ba0a21b0-6742-4709-92b6-92e6e985d2f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3139847674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3139847674 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |