Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1698592505
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2798374732
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1487367707

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.9267725
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1447446348
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3680578939
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1121246868
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1089489375
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4143880144
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3663675368
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3109756507
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1186015590
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3473222233
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1353685575
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1038162094
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3800597279
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2019792616
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2870440256
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1987605715
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3278882802
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4060521890
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2493498327
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.885810202
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2280033088
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.280170914
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1413895500
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1355267678
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1797845334
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.413961108
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3555564967
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.858769318
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.409060815
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2253240368
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2834973232
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2335907266
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3985198984
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1455756475
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3348696538
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4227939992
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3030985115
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2963227231
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1113788347
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2068970647
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1907428574
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1289753346
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3124606752
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2375303159
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.478194338
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1553577144
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2006288163
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1224256829
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1512123226
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.74333619
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.815562367
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2007808957
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.852802536
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2560652993
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1053551075
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.292757910
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1114381641
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2352817864
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3986623699
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.532663374
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1609211925
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1822473432
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1467795341
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1886603871
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.480158494
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3126942663
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.352178315
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2723696238
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.245123747
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1997701535
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.394326930
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.166560149
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3789741653
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1032340597
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1186633611
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3281229686
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1736352199
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2125901013
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1473179764
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1750329697
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.630503991
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1271816464
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2967055367
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1236350896
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3538058050
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4107531169
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3215938416
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3732973777
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1643197637
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1333764624
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.452019018
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2110943432
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2227361929
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4278185912
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1465553955
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.791867846
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.319907278
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1147610681
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2605008110
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3541909201
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4225523394
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1219750013
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1442618660
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1171518528
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1968705686
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4235483463
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4170754261
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1654775663
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1186619141
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2649339462
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3783244785
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2765340060
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1311499174
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2874508139
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.340676873
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4100036043
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3271419240
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2381194525
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3347098155
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2526541001
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1505747059
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1630739122
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2564391895
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2267490400
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.52655379
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2642420612
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2132518123
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2751309994
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2639937814
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1686712721
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.689718761
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3472900341
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1537333588
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1132755809
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3338992834
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.982405587
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1563107806
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2435660399
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1955904442
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2467309731
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1875250583
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3562967045
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.428605299
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2477564669
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2177722844
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.199624915
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1703168271
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.617640889
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1956217910
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1061825173
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1173526858
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4064521222
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.335196457
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3362059154
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3389384875
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2760902340
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.336366060
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2762349527
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3778102861
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4203241814
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2012326428
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1228074740
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2399353005
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.219507331
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3208650047
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4105703350
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3366453270
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1729276455
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2134295114
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.499589651
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1463776930
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2863537919
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1876955804
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.363271541
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1227977564
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2870673884
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1826061713
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2967742954
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.299094362
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3528360893
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1395389090
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.9907582
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2824481557
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2039682889
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2553263457
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2612526835
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2153307179
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1929130623
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3254691235
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3699835651
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2647836758
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2815413241
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2338674031
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1607556891
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3967493410
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1910532307
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.69738078



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2870673884 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:16 PM PDT 24 1547850000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1607556891 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:19 PM PDT 24 1492190000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3967493410 Jun 28 06:07:01 PM PDT 24 Jun 28 06:07:10 PM PDT 24 1364830000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2553263457 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:23 PM PDT 24 1522310000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1698592505 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:13 PM PDT 24 1170810000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2863537919 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:21 PM PDT 24 1298450000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1729276455 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1349690000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.299094362 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1535510000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2612526835 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:16 PM PDT 24 1396150000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2039682889 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:16 PM PDT 24 1275530000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2824481557 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:23 PM PDT 24 1616330000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3254691235 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:17 PM PDT 24 1440050000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2647836758 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:15 PM PDT 24 1394610000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2762349527 Jun 28 06:07:02 PM PDT 24 Jun 28 06:07:12 PM PDT 24 1559230000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3389384875 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:15 PM PDT 24 1481890000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1956217910 Jun 28 06:07:02 PM PDT 24 Jun 28 06:07:12 PM PDT 24 1428590000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1463776930 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1471230000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1826061713 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1335550000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.499589651 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1337590000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4064521222 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1378150000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.363271541 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:24 PM PDT 24 1573990000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4203241814 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:15 PM PDT 24 1364570000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3366453270 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:16 PM PDT 24 1528430000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1173526858 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:19 PM PDT 24 1576810000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.9907582 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:12 PM PDT 24 1264490000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1061825173 Jun 28 06:07:00 PM PDT 24 Jun 28 06:07:10 PM PDT 24 1520390000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2153307179 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1573330000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1910532307 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:17 PM PDT 24 1255190000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2399353005 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:19 PM PDT 24 1516910000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.336366060 Jun 28 06:07:01 PM PDT 24 Jun 28 06:07:11 PM PDT 24 1353250000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2134295114 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1461710000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3528360893 Jun 28 06:07:07 PM PDT 24 Jun 28 06:07:20 PM PDT 24 1494630000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2012326428 Jun 28 06:07:08 PM PDT 24 Jun 28 06:07:19 PM PDT 24 1320670000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1227977564 Jun 28 06:07:00 PM PDT 24 Jun 28 06:07:08 PM PDT 24 1429790000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1228074740 Jun 28 06:07:01 PM PDT 24 Jun 28 06:07:13 PM PDT 24 1552350000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2815413241 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1380490000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1876955804 Jun 28 06:07:02 PM PDT 24 Jun 28 06:07:12 PM PDT 24 1343290000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4105703350 Jun 28 06:07:01 PM PDT 24 Jun 28 06:07:13 PM PDT 24 1493890000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.219507331 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1387490000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3778102861 Jun 28 06:07:02 PM PDT 24 Jun 28 06:07:13 PM PDT 24 1492670000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3362059154 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1573350000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2338674031 Jun 28 06:07:02 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1485630000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.335196457 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1527410000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2760902340 Jun 28 06:07:02 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1646570000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3699835651 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:19 PM PDT 24 1568590000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1395389090 Jun 28 06:07:03 PM PDT 24 Jun 28 06:07:14 PM PDT 24 1516990000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1929130623 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1596690000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3208650047 Jun 28 06:07:08 PM PDT 24 Jun 28 06:07:21 PM PDT 24 1527130000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.69738078 Jun 28 06:07:05 PM PDT 24 Jun 28 06:07:17 PM PDT 24 1326130000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2967742954 Jun 28 06:07:04 PM PDT 24 Jun 28 06:07:18 PM PDT 24 1440110000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2493498327 Jun 28 05:50:20 PM PDT 24 Jun 28 06:24:34 PM PDT 24 336913070000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.280170914 Jun 28 05:50:20 PM PDT 24 Jun 28 06:19:16 PM PDT 24 336409950000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1907428574 Jun 28 05:50:24 PM PDT 24 Jun 28 06:20:03 PM PDT 24 336591190000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1121246868 Jun 28 05:50:12 PM PDT 24 Jun 28 06:23:59 PM PDT 24 336882710000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1186015590 Jun 28 05:50:14 PM PDT 24 Jun 28 06:28:11 PM PDT 24 336491350000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1987605715 Jun 28 05:50:25 PM PDT 24 Jun 28 06:22:38 PM PDT 24 336940250000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1553577144 Jun 28 05:50:10 PM PDT 24 Jun 28 06:21:21 PM PDT 24 336876190000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3663675368 Jun 28 05:50:10 PM PDT 24 Jun 28 06:20:45 PM PDT 24 336489270000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2798374732 Jun 28 05:50:13 PM PDT 24 Jun 28 06:28:17 PM PDT 24 336710130000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1038162094 Jun 28 05:50:10 PM PDT 24 Jun 28 06:18:47 PM PDT 24 336658550000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2834973232 Jun 28 05:50:20 PM PDT 24 Jun 28 06:24:46 PM PDT 24 337107470000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.409060815 Jun 28 05:50:21 PM PDT 24 Jun 28 06:17:48 PM PDT 24 336650130000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.9267725 Jun 28 05:50:12 PM PDT 24 Jun 28 06:23:44 PM PDT 24 336533350000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2375303159 Jun 28 05:50:20 PM PDT 24 Jun 28 06:20:47 PM PDT 24 336469090000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3109756507 Jun 28 05:50:11 PM PDT 24 Jun 28 06:21:41 PM PDT 24 336933370000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2963227231 Jun 28 05:50:21 PM PDT 24 Jun 28 06:20:47 PM PDT 24 336942770000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1355267678 Jun 28 05:50:20 PM PDT 24 Jun 28 06:28:41 PM PDT 24 336770870000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2068970647 Jun 28 05:50:20 PM PDT 24 Jun 28 06:20:26 PM PDT 24 337150850000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2870440256 Jun 28 05:50:20 PM PDT 24 Jun 28 06:20:39 PM PDT 24 336669970000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2019792616 Jun 28 05:50:19 PM PDT 24 Jun 28 06:26:07 PM PDT 24 336953130000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1089489375 Jun 28 05:50:11 PM PDT 24 Jun 28 06:25:45 PM PDT 24 337154890000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3124606752 Jun 28 05:50:18 PM PDT 24 Jun 28 06:18:40 PM PDT 24 336720430000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2006288163 Jun 28 05:50:11 PM PDT 24 Jun 28 06:21:06 PM PDT 24 336398310000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.478194338 Jun 28 05:50:12 PM PDT 24 Jun 28 06:26:54 PM PDT 24 336441090000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3985198984 Jun 28 05:50:23 PM PDT 24 Jun 28 06:18:25 PM PDT 24 336710970000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4227939992 Jun 28 05:50:20 PM PDT 24 Jun 28 06:22:12 PM PDT 24 336848490000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1224256829 Jun 28 05:50:10 PM PDT 24 Jun 28 06:20:20 PM PDT 24 336451930000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1447446348 Jun 28 05:50:10 PM PDT 24 Jun 28 06:22:47 PM PDT 24 337019090000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.413961108 Jun 28 05:50:20 PM PDT 24 Jun 28 06:20:41 PM PDT 24 336378770000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1289753346 Jun 28 05:50:19 PM PDT 24 Jun 28 06:18:32 PM PDT 24 336349410000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2280033088 Jun 28 05:50:20 PM PDT 24 Jun 28 06:16:34 PM PDT 24 336965210000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2253240368 Jun 28 05:50:20 PM PDT 24 Jun 28 06:19:46 PM PDT 24 336949710000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3278882802 Jun 28 05:50:20 PM PDT 24 Jun 28 06:20:11 PM PDT 24 336764810000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3348696538 Jun 28 05:50:21 PM PDT 24 Jun 28 06:26:59 PM PDT 24 336595570000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3473222233 Jun 28 05:50:13 PM PDT 24 Jun 28 06:27:05 PM PDT 24 336755790000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3680578939 Jun 28 05:50:12 PM PDT 24 Jun 28 06:23:02 PM PDT 24 336496430000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.885810202 Jun 28 05:50:20 PM PDT 24 Jun 28 06:23:16 PM PDT 24 336549090000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1413895500 Jun 28 05:50:10 PM PDT 24 Jun 28 06:20:18 PM PDT 24 336362270000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1455756475 Jun 28 05:50:11 PM PDT 24 Jun 28 06:20:02 PM PDT 24 336437650000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4060521890 Jun 28 05:50:20 PM PDT 24 Jun 28 06:20:38 PM PDT 24 337115770000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3030985115 Jun 28 05:50:21 PM PDT 24 Jun 28 06:22:11 PM PDT 24 336639110000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2335907266 Jun 28 05:50:21 PM PDT 24 Jun 28 06:19:45 PM PDT 24 336790090000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4143880144 Jun 28 05:50:14 PM PDT 24 Jun 28 06:25:19 PM PDT 24 336855410000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1512123226 Jun 28 05:50:10 PM PDT 24 Jun 28 06:18:09 PM PDT 24 336710630000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1353685575 Jun 28 05:50:12 PM PDT 24 Jun 28 06:26:00 PM PDT 24 336440870000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1797845334 Jun 28 05:50:22 PM PDT 24 Jun 28 06:22:18 PM PDT 24 336835370000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1113788347 Jun 28 05:50:19 PM PDT 24 Jun 28 06:21:04 PM PDT 24 336981810000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3555564967 Jun 28 05:50:21 PM PDT 24 Jun 28 06:26:10 PM PDT 24 336744830000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3800597279 Jun 28 05:50:14 PM PDT 24 Jun 28 06:25:51 PM PDT 24 336477030000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.858769318 Jun 28 05:50:20 PM PDT 24 Jun 28 06:26:24 PM PDT 24 336768950000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3562967045 Jun 28 06:12:00 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1044350000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2564391895 Jun 28 06:11:58 PM PDT 24 Jun 28 06:12:15 PM PDT 24 1441690000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.52655379 Jun 28 06:12:03 PM PDT 24 Jun 28 06:12:18 PM PDT 24 1426170000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3347098155 Jun 28 06:11:58 PM PDT 24 Jun 28 06:12:14 PM PDT 24 1246810000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.340676873 Jun 28 06:12:01 PM PDT 24 Jun 28 06:12:15 PM PDT 24 1529390000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1219750013 Jun 28 06:11:42 PM PDT 24 Jun 28 06:11:53 PM PDT 24 1204370000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.689718761 Jun 28 06:12:01 PM PDT 24 Jun 28 06:12:15 PM PDT 24 1460710000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2639937814 Jun 28 06:12:09 PM PDT 24 Jun 28 06:12:25 PM PDT 24 1553750000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1630739122 Jun 28 06:11:42 PM PDT 24 Jun 28 06:11:55 PM PDT 24 1367630000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2605008110 Jun 28 06:11:52 PM PDT 24 Jun 28 06:12:04 PM PDT 24 1421890000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1505747059 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:09 PM PDT 24 1452750000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.617640889 Jun 28 06:11:43 PM PDT 24 Jun 28 06:11:56 PM PDT 24 1507270000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2751309994 Jun 28 06:11:55 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1447250000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2177722844 Jun 28 06:11:45 PM PDT 24 Jun 28 06:11:57 PM PDT 24 1407930000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.982405587 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1487610000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4225523394 Jun 28 06:11:49 PM PDT 24 Jun 28 06:11:59 PM PDT 24 1530890000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1186619141 Jun 28 06:11:59 PM PDT 24 Jun 28 06:12:14 PM PDT 24 1421910000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3541909201 Jun 28 06:11:42 PM PDT 24 Jun 28 06:11:55 PM PDT 24 1424290000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2267490400 Jun 28 06:11:55 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1475950000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.199624915 Jun 28 06:11:50 PM PDT 24 Jun 28 06:12:02 PM PDT 24 1505490000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3338992834 Jun 28 06:11:59 PM PDT 24 Jun 28 06:12:16 PM PDT 24 1469070000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3472900341 Jun 28 06:12:00 PM PDT 24 Jun 28 06:12:17 PM PDT 24 1505830000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4100036043 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:08 PM PDT 24 1190030000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2642420612 Jun 28 06:11:55 PM PDT 24 Jun 28 06:12:08 PM PDT 24 1544490000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2765340060 Jun 28 06:11:52 PM PDT 24 Jun 28 06:12:01 PM PDT 24 1479390000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1171518528 Jun 28 06:11:42 PM PDT 24 Jun 28 06:11:54 PM PDT 24 1451930000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1703168271 Jun 28 06:11:50 PM PDT 24 Jun 28 06:12:01 PM PDT 24 1411070000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2132518123 Jun 28 06:11:59 PM PDT 24 Jun 28 06:12:15 PM PDT 24 1501530000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2381194525 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1350490000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2477564669 Jun 28 06:11:50 PM PDT 24 Jun 28 06:12:03 PM PDT 24 1575950000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4170754261 Jun 28 06:11:54 PM PDT 24 Jun 28 06:12:06 PM PDT 24 1556050000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2526541001 Jun 28 06:11:57 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1520870000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3783244785 Jun 28 06:11:49 PM PDT 24 Jun 28 06:12:00 PM PDT 24 1464870000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4235483463 Jun 28 06:11:53 PM PDT 24 Jun 28 06:12:06 PM PDT 24 1585250000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.428605299 Jun 28 06:11:54 PM PDT 24 Jun 28 06:12:05 PM PDT 24 1445670000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2435660399 Jun 28 06:12:01 PM PDT 24 Jun 28 06:12:17 PM PDT 24 1484110000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3271419240 Jun 28 06:11:54 PM PDT 24 Jun 28 06:12:05 PM PDT 24 1478170000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1875250583 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:13 PM PDT 24 1577630000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1442618660 Jun 28 06:11:37 PM PDT 24 Jun 28 06:11:49 PM PDT 24 1323170000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1563107806 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:09 PM PDT 24 1400950000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2467309731 Jun 28 06:11:57 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1263730000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1968705686 Jun 28 06:11:55 PM PDT 24 Jun 28 06:12:09 PM PDT 24 1549430000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1955904442 Jun 28 06:12:04 PM PDT 24 Jun 28 06:12:19 PM PDT 24 1486790000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1132755809 Jun 28 06:11:54 PM PDT 24 Jun 28 06:12:06 PM PDT 24 1209730000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1686712721 Jun 28 06:12:01 PM PDT 24 Jun 28 06:12:17 PM PDT 24 1451610000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1311499174 Jun 28 06:11:55 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1420190000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1537333588 Jun 28 06:11:39 PM PDT 24 Jun 28 06:11:52 PM PDT 24 1434430000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2874508139 Jun 28 06:11:58 PM PDT 24 Jun 28 06:12:15 PM PDT 24 1252570000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1654775663 Jun 28 06:12:00 PM PDT 24 Jun 28 06:12:17 PM PDT 24 1533650000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2649339462 Jun 28 06:11:56 PM PDT 24 Jun 28 06:12:11 PM PDT 24 1472230000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1487367707 Jun 28 06:18:15 PM PDT 24 Jun 28 06:54:45 PM PDT 24 336522470000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2352817864 Jun 28 06:18:09 PM PDT 24 Jun 28 06:50:29 PM PDT 24 337012350000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1053551075 Jun 28 06:18:12 PM PDT 24 Jun 28 06:47:06 PM PDT 24 336934270000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1736352199 Jun 28 06:18:17 PM PDT 24 Jun 28 06:47:10 PM PDT 24 336577310000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1236350896 Jun 28 06:18:22 PM PDT 24 Jun 28 06:54:14 PM PDT 24 336690690000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2560652993 Jun 28 06:18:12 PM PDT 24 Jun 28 06:48:58 PM PDT 24 336303670000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2110943432 Jun 28 06:18:17 PM PDT 24 Jun 28 06:53:58 PM PDT 24 336855050000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1186633611 Jun 28 06:18:21 PM PDT 24 Jun 28 06:47:23 PM PDT 24 336714270000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.630503991 Jun 28 06:18:15 PM PDT 24 Jun 28 06:54:15 PM PDT 24 336415850000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.452019018 Jun 28 06:18:17 PM PDT 24 Jun 28 07:00:12 PM PDT 24 336950850000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1822473432 Jun 28 06:18:19 PM PDT 24 Jun 28 06:47:58 PM PDT 24 336924850000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3789741653 Jun 28 06:18:17 PM PDT 24 Jun 28 06:47:50 PM PDT 24 336362590000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1032340597 Jun 28 06:18:17 PM PDT 24 Jun 28 06:49:13 PM PDT 24 336815330000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3215938416 Jun 28 06:18:15 PM PDT 24 Jun 28 06:52:26 PM PDT 24 336703630000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2125901013 Jun 28 06:18:27 PM PDT 24 Jun 28 06:54:04 PM PDT 24 336495970000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3986623699 Jun 28 06:18:20 PM PDT 24 Jun 28 07:00:15 PM PDT 24 336689550000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.532663374 Jun 28 06:18:17 PM PDT 24 Jun 28 06:57:04 PM PDT 24 336796590000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3538058050 Jun 28 06:18:21 PM PDT 24 Jun 28 06:49:39 PM PDT 24 337082370000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1750329697 Jun 28 06:18:17 PM PDT 24 Jun 28 06:49:05 PM PDT 24 336640590000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2007808957 Jun 28 06:18:17 PM PDT 24 Jun 28 06:48:13 PM PDT 24 336913230000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3732973777 Jun 28 06:18:14 PM PDT 24 Jun 28 06:54:21 PM PDT 24 336659230000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.166560149 Jun 28 06:18:13 PM PDT 24 Jun 28 06:46:47 PM PDT 24 337109450000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1609211925 Jun 28 06:18:10 PM PDT 24 Jun 28 06:49:02 PM PDT 24 336936450000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3281229686 Jun 28 06:18:16 PM PDT 24 Jun 28 07:00:17 PM PDT 24 336991770000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1333764624 Jun 28 06:18:20 PM PDT 24 Jun 28 06:48:38 PM PDT 24 336482330000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.394326930 Jun 28 06:18:23 PM PDT 24 Jun 28 06:47:11 PM PDT 24 336631110000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1467795341 Jun 28 06:18:11 PM PDT 24 Jun 28 06:47:43 PM PDT 24 336497770000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2227361929 Jun 28 06:18:18 PM PDT 24 Jun 28 06:49:43 PM PDT 24 336667890000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.74333619 Jun 28 06:18:06 PM PDT 24 Jun 28 06:50:59 PM PDT 24 336654770000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.815562367 Jun 28 06:18:18 PM PDT 24 Jun 28 06:48:46 PM PDT 24 337106610000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1465553955 Jun 28 06:18:14 PM PDT 24 Jun 28 06:53:27 PM PDT 24 336657990000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1997701535 Jun 28 06:18:17 PM PDT 24 Jun 28 06:50:20 PM PDT 24 336804770000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.319907278 Jun 28 06:18:11 PM PDT 24 Jun 28 06:53:41 PM PDT 24 336412170000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1886603871 Jun 28 06:18:15 PM PDT 24 Jun 28 06:54:44 PM PDT 24 336506230000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.480158494 Jun 28 06:18:17 PM PDT 24 Jun 28 06:50:40 PM PDT 24 336430350000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2967055367 Jun 28 06:18:09 PM PDT 24 Jun 28 06:53:39 PM PDT 24 336466730000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3126942663 Jun 28 06:18:09 PM PDT 24 Jun 28 06:56:45 PM PDT 24 336792350000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1643197637 Jun 28 06:18:19 PM PDT 24 Jun 28 06:48:40 PM PDT 24 336488970000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.245123747 Jun 28 06:18:14 PM PDT 24 Jun 28 06:57:26 PM PDT 24 337083890000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.852802536 Jun 28 06:18:12 PM PDT 24 Jun 28 06:54:08 PM PDT 24 336665310000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.791867846 Jun 28 06:18:18 PM PDT 24 Jun 28 06:53:16 PM PDT 24 337014790000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4278185912 Jun 28 06:18:15 PM PDT 24 Jun 28 07:00:05 PM PDT 24 336897530000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1473179764 Jun 28 06:18:25 PM PDT 24 Jun 28 06:50:56 PM PDT 24 336423070000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2723696238 Jun 28 06:18:20 PM PDT 24 Jun 28 06:50:00 PM PDT 24 336991610000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4107531169 Jun 28 06:18:24 PM PDT 24 Jun 28 06:50:41 PM PDT 24 336977290000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.292757910 Jun 28 06:18:19 PM PDT 24 Jun 28 06:54:55 PM PDT 24 336619590000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.352178315 Jun 28 06:18:08 PM PDT 24 Jun 28 06:49:55 PM PDT 24 336499950000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1114381641 Jun 28 06:18:13 PM PDT 24 Jun 28 06:52:16 PM PDT 24 336574110000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1147610681 Jun 28 06:18:21 PM PDT 24 Jun 28 06:53:53 PM PDT 24 336488230000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1271816464 Jun 28 06:18:23 PM PDT 24 Jun 28 06:49:56 PM PDT 24 336474090000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1698592505
Short name T8
Test name
Test status
Simulation time 1170810000 ps
CPU time 3.61 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:13 PM PDT 24
Peak memory 164992 kb
Host smart-f764f15f-aadb-494b-a7bc-5279aa332fc5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1698592505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1698592505
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2798374732
Short name T19
Test name
Test status
Simulation time 336710130000 ps
CPU time 916.12 seconds
Started Jun 28 05:50:13 PM PDT 24
Finished Jun 28 06:28:17 PM PDT 24
Peak memory 160812 kb
Host smart-2bb3198d-450b-413b-a179-4eb011ab7b23
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2798374732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2798374732
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1487367707
Short name T21
Test name
Test status
Simulation time 336522470000 ps
CPU time 868.38 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:54:45 PM PDT 24
Peak memory 160820 kb
Host smart-902d0c83-57af-4f87-a122-b9b6ad3dba5b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1487367707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.1487367707
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.9267725
Short name T73
Test name
Test status
Simulation time 336533350000 ps
CPU time 818.83 seconds
Started Jun 28 05:50:12 PM PDT 24
Finished Jun 28 06:23:44 PM PDT 24
Peak memory 160800 kb
Host smart-fc906ff9-57f6-49fa-8459-54b780caf5b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=9267725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.9267725
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1447446348
Short name T88
Test name
Test status
Simulation time 337019090000 ps
CPU time 801.92 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:22:47 PM PDT 24
Peak memory 160772 kb
Host smart-79d055f3-1c5c-4a58-baba-6fa3966632ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1447446348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1447446348
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3680578939
Short name T96
Test name
Test status
Simulation time 336496430000 ps
CPU time 801.64 seconds
Started Jun 28 05:50:12 PM PDT 24
Finished Jun 28 06:23:02 PM PDT 24
Peak memory 160816 kb
Host smart-aab64fa9-e7b6-4e8c-86c1-7fdb35f1fe6b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3680578939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3680578939
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1121246868
Short name T14
Test name
Test status
Simulation time 336882710000 ps
CPU time 809.27 seconds
Started Jun 28 05:50:12 PM PDT 24
Finished Jun 28 06:23:59 PM PDT 24
Peak memory 160820 kb
Host smart-be5d206a-bbbb-4717-bb24-6f4e47dd1923
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1121246868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1121246868
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1089489375
Short name T81
Test name
Test status
Simulation time 337154890000 ps
CPU time 890.64 seconds
Started Jun 28 05:50:11 PM PDT 24
Finished Jun 28 06:25:45 PM PDT 24
Peak memory 160828 kb
Host smart-74cb2f39-41d1-4e12-ade7-9c17eb02b6cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1089489375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1089489375
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4143880144
Short name T103
Test name
Test status
Simulation time 336855410000 ps
CPU time 857.26 seconds
Started Jun 28 05:50:14 PM PDT 24
Finished Jun 28 06:25:19 PM PDT 24
Peak memory 160780 kb
Host smart-ed4a6ed7-8b69-4c11-8af7-12e36a9b33f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4143880144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4143880144
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.3663675368
Short name T18
Test name
Test status
Simulation time 336489270000 ps
CPU time 756.17 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:20:45 PM PDT 24
Peak memory 160848 kb
Host smart-e362530b-09da-453f-9664-8f4c7022a1fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3663675368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.3663675368
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.3109756507
Short name T75
Test name
Test status
Simulation time 336933370000 ps
CPU time 761.52 seconds
Started Jun 28 05:50:11 PM PDT 24
Finished Jun 28 06:21:41 PM PDT 24
Peak memory 160876 kb
Host smart-ea33531b-3c74-4ef7-ae86-6dd648a42a14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3109756507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.3109756507
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1186015590
Short name T15
Test name
Test status
Simulation time 336491350000 ps
CPU time 910.35 seconds
Started Jun 28 05:50:14 PM PDT 24
Finished Jun 28 06:28:11 PM PDT 24
Peak memory 160820 kb
Host smart-b0c604c7-0544-466b-a6f3-97a6e7a2c644
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1186015590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1186015590
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3473222233
Short name T95
Test name
Test status
Simulation time 336755790000 ps
CPU time 904.49 seconds
Started Jun 28 05:50:13 PM PDT 24
Finished Jun 28 06:27:05 PM PDT 24
Peak memory 160776 kb
Host smart-2ab32af6-d79e-4ea8-b38c-5641654e26ec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3473222233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3473222233
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1353685575
Short name T105
Test name
Test status
Simulation time 336440870000 ps
CPU time 866.84 seconds
Started Jun 28 05:50:12 PM PDT 24
Finished Jun 28 06:26:00 PM PDT 24
Peak memory 160792 kb
Host smart-96ad34ba-5516-4358-9329-3ea0d5c7e665
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1353685575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1353685575
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1038162094
Short name T20
Test name
Test status
Simulation time 336658550000 ps
CPU time 691.08 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:18:47 PM PDT 24
Peak memory 160816 kb
Host smart-d16c8740-6c2a-4c18-9271-e73ca2d55c7a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1038162094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1038162094
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3800597279
Short name T109
Test name
Test status
Simulation time 336477030000 ps
CPU time 865.79 seconds
Started Jun 28 05:50:14 PM PDT 24
Finished Jun 28 06:25:51 PM PDT 24
Peak memory 160780 kb
Host smart-5e2b1008-d961-4a67-9a14-bcaf9d0d83a9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800597279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3800597279
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2019792616
Short name T80
Test name
Test status
Simulation time 336953130000 ps
CPU time 862.93 seconds
Started Jun 28 05:50:19 PM PDT 24
Finished Jun 28 06:26:07 PM PDT 24
Peak memory 160792 kb
Host smart-84e1b492-f983-416a-a9a1-461794c18fbf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2019792616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2019792616
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2870440256
Short name T79
Test name
Test status
Simulation time 336669970000 ps
CPU time 734.85 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:20:39 PM PDT 24
Peak memory 160816 kb
Host smart-bf8b8033-bfcc-405e-b130-bf62d29a613e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2870440256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2870440256
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1987605715
Short name T16
Test name
Test status
Simulation time 336940250000 ps
CPU time 786.52 seconds
Started Jun 28 05:50:25 PM PDT 24
Finished Jun 28 06:22:38 PM PDT 24
Peak memory 160820 kb
Host smart-3e4c4e0b-6d90-4137-b565-ef4d7593b37e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1987605715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1987605715
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3278882802
Short name T93
Test name
Test status
Simulation time 336764810000 ps
CPU time 728.13 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:20:11 PM PDT 24
Peak memory 160824 kb
Host smart-451657f4-21ad-4ae3-84c0-2c5ca2f61964
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3278882802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3278882802
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.4060521890
Short name T100
Test name
Test status
Simulation time 337115770000 ps
CPU time 738.13 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:20:38 PM PDT 24
Peak memory 160816 kb
Host smart-c0803656-11af-466b-a6bd-1e969273b9ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4060521890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.4060521890
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2493498327
Short name T5
Test name
Test status
Simulation time 336913070000 ps
CPU time 828.61 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:24:34 PM PDT 24
Peak memory 160820 kb
Host smart-e01f92cc-08c7-4759-9757-5b1d3d4a2baa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2493498327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2493498327
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.885810202
Short name T97
Test name
Test status
Simulation time 336549090000 ps
CPU time 802.39 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:23:16 PM PDT 24
Peak memory 160764 kb
Host smart-9851fd81-f8a0-48e1-9509-9c7a6c8a09d0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=885810202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.885810202
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2280033088
Short name T91
Test name
Test status
Simulation time 336965210000 ps
CPU time 634.01 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:16:34 PM PDT 24
Peak memory 160820 kb
Host smart-b0febca4-f513-409f-8464-d47b5b13615c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2280033088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2280033088
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.280170914
Short name T6
Test name
Test status
Simulation time 336409950000 ps
CPU time 698.2 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:19:16 PM PDT 24
Peak memory 160812 kb
Host smart-03f8d3a4-f9df-445a-9344-e45933819fb9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=280170914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.280170914
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1413895500
Short name T98
Test name
Test status
Simulation time 336362270000 ps
CPU time 724.42 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:20:18 PM PDT 24
Peak memory 160808 kb
Host smart-1a92235c-5a8f-4795-85da-72355c3bc5ac
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1413895500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1413895500
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1355267678
Short name T77
Test name
Test status
Simulation time 336770870000 ps
CPU time 913.28 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:28:41 PM PDT 24
Peak memory 160820 kb
Host smart-63b62b5c-b00c-4a98-b7f1-ca8bda3b19eb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1355267678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1355267678
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1797845334
Short name T106
Test name
Test status
Simulation time 336835370000 ps
CPU time 784.8 seconds
Started Jun 28 05:50:22 PM PDT 24
Finished Jun 28 06:22:18 PM PDT 24
Peak memory 160820 kb
Host smart-09e29e24-5d2e-4d14-8bde-0688ad2879e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1797845334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1797845334
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.413961108
Short name T89
Test name
Test status
Simulation time 336378770000 ps
CPU time 747.75 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:20:41 PM PDT 24
Peak memory 160844 kb
Host smart-0242727c-97f8-4e67-808b-a4644b20d8b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=413961108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.413961108
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3555564967
Short name T108
Test name
Test status
Simulation time 336744830000 ps
CPU time 871.76 seconds
Started Jun 28 05:50:21 PM PDT 24
Finished Jun 28 06:26:10 PM PDT 24
Peak memory 160780 kb
Host smart-8ea5b976-a1ee-4a19-aee3-3ea552c378e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3555564967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3555564967
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.858769318
Short name T110
Test name
Test status
Simulation time 336768950000 ps
CPU time 881.11 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:26:24 PM PDT 24
Peak memory 160808 kb
Host smart-78b19596-5e5f-4c08-b4a4-1b20350a3cd8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=858769318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.858769318
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.409060815
Short name T72
Test name
Test status
Simulation time 336650130000 ps
CPU time 675.11 seconds
Started Jun 28 05:50:21 PM PDT 24
Finished Jun 28 06:17:48 PM PDT 24
Peak memory 160816 kb
Host smart-0591cedf-063c-47e7-b740-af159d6aff60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=409060815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.409060815
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2253240368
Short name T92
Test name
Test status
Simulation time 336949710000 ps
CPU time 720.2 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:19:46 PM PDT 24
Peak memory 160780 kb
Host smart-b09bbc58-20b1-4fc4-b60f-85a383d66082
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2253240368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2253240368
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2834973232
Short name T71
Test name
Test status
Simulation time 337107470000 ps
CPU time 859.57 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:24:46 PM PDT 24
Peak memory 160828 kb
Host smart-6e374567-2f73-4a0e-90c9-3bb5a15553c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2834973232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2834973232
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2335907266
Short name T102
Test name
Test status
Simulation time 336790090000 ps
CPU time 716.5 seconds
Started Jun 28 05:50:21 PM PDT 24
Finished Jun 28 06:19:45 PM PDT 24
Peak memory 160780 kb
Host smart-e96d281c-caf5-4012-85d5-fc1f1beb0c5a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2335907266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2335907266
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3985198984
Short name T85
Test name
Test status
Simulation time 336710970000 ps
CPU time 671.03 seconds
Started Jun 28 05:50:23 PM PDT 24
Finished Jun 28 06:18:25 PM PDT 24
Peak memory 160824 kb
Host smart-fb03ca90-ea50-4561-9848-99b3eddb6d7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3985198984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3985198984
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1455756475
Short name T99
Test name
Test status
Simulation time 336437650000 ps
CPU time 726.51 seconds
Started Jun 28 05:50:11 PM PDT 24
Finished Jun 28 06:20:02 PM PDT 24
Peak memory 160816 kb
Host smart-6b37be7e-d46d-41a6-b9ac-f11bd5f48ed2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1455756475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1455756475
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3348696538
Short name T94
Test name
Test status
Simulation time 336595570000 ps
CPU time 896.18 seconds
Started Jun 28 05:50:21 PM PDT 24
Finished Jun 28 06:26:59 PM PDT 24
Peak memory 160816 kb
Host smart-b54ae772-6aea-44be-9213-35ca03917847
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3348696538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3348696538
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4227939992
Short name T86
Test name
Test status
Simulation time 336848490000 ps
CPU time 779.08 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:22:12 PM PDT 24
Peak memory 160824 kb
Host smart-22baac10-1072-4215-8d35-714ba81c227f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4227939992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4227939992
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3030985115
Short name T101
Test name
Test status
Simulation time 336639110000 ps
CPU time 777.15 seconds
Started Jun 28 05:50:21 PM PDT 24
Finished Jun 28 06:22:11 PM PDT 24
Peak memory 160824 kb
Host smart-f54f4c2f-c7ea-439d-83ed-9a1523bcbff4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3030985115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3030985115
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2963227231
Short name T76
Test name
Test status
Simulation time 336942770000 ps
CPU time 752.29 seconds
Started Jun 28 05:50:21 PM PDT 24
Finished Jun 28 06:20:47 PM PDT 24
Peak memory 160820 kb
Host smart-4f71891b-22aa-4d86-90a4-ae3a4b51fe3b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2963227231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2963227231
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1113788347
Short name T107
Test name
Test status
Simulation time 336981810000 ps
CPU time 751.05 seconds
Started Jun 28 05:50:19 PM PDT 24
Finished Jun 28 06:21:04 PM PDT 24
Peak memory 160808 kb
Host smart-4c06da6d-7446-450f-bed8-42b4dcfeaa49
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1113788347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1113788347
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2068970647
Short name T78
Test name
Test status
Simulation time 337150850000 ps
CPU time 715.92 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:20:26 PM PDT 24
Peak memory 160820 kb
Host smart-56f496b9-5b52-473c-bd26-fde7dd54ac62
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2068970647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2068970647
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1907428574
Short name T7
Test name
Test status
Simulation time 336591190000 ps
CPU time 722.9 seconds
Started Jun 28 05:50:24 PM PDT 24
Finished Jun 28 06:20:03 PM PDT 24
Peak memory 160820 kb
Host smart-06ed4257-29d3-4bd3-bc97-082e233c38f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1907428574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1907428574
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1289753346
Short name T90
Test name
Test status
Simulation time 336349410000 ps
CPU time 694.14 seconds
Started Jun 28 05:50:19 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 160808 kb
Host smart-7d0d9a10-2fb3-49fa-8200-b4468aafd6d6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1289753346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1289753346
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3124606752
Short name T82
Test name
Test status
Simulation time 336720430000 ps
CPU time 678.75 seconds
Started Jun 28 05:50:18 PM PDT 24
Finished Jun 28 06:18:40 PM PDT 24
Peak memory 160816 kb
Host smart-30533972-7471-4b8a-8d64-af953ea87de2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3124606752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3124606752
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.2375303159
Short name T74
Test name
Test status
Simulation time 336469090000 ps
CPU time 733.63 seconds
Started Jun 28 05:50:20 PM PDT 24
Finished Jun 28 06:20:47 PM PDT 24
Peak memory 160824 kb
Host smart-abd48d3b-6df7-489b-9651-3badcf3d4282
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2375303159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.2375303159
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.478194338
Short name T84
Test name
Test status
Simulation time 336441090000 ps
CPU time 904.21 seconds
Started Jun 28 05:50:12 PM PDT 24
Finished Jun 28 06:26:54 PM PDT 24
Peak memory 160760 kb
Host smart-d66402b8-3e62-496c-86f1-b099cb636dfd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=478194338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.478194338
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1553577144
Short name T17
Test name
Test status
Simulation time 336876190000 ps
CPU time 762.69 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:21:21 PM PDT 24
Peak memory 160812 kb
Host smart-bdf3fb48-3243-4a28-b449-93dd16fb81d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1553577144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1553577144
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2006288163
Short name T83
Test name
Test status
Simulation time 336398310000 ps
CPU time 754.75 seconds
Started Jun 28 05:50:11 PM PDT 24
Finished Jun 28 06:21:06 PM PDT 24
Peak memory 160816 kb
Host smart-e639277f-c49b-46f7-9287-83f39b1fb952
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2006288163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2006288163
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1224256829
Short name T87
Test name
Test status
Simulation time 336451930000 ps
CPU time 729.83 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:20:20 PM PDT 24
Peak memory 160816 kb
Host smart-31d42e8b-f5a6-42a1-bf2c-bf97cc0e46c9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1224256829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1224256829
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1512123226
Short name T104
Test name
Test status
Simulation time 336710630000 ps
CPU time 671.62 seconds
Started Jun 28 05:50:10 PM PDT 24
Finished Jun 28 06:18:09 PM PDT 24
Peak memory 160804 kb
Host smart-4d3e119b-0ab7-44d5-962d-53b18dbcbdf2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1512123226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1512123226
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.74333619
Short name T179
Test name
Test status
Simulation time 336654770000 ps
CPU time 790.31 seconds
Started Jun 28 06:18:06 PM PDT 24
Finished Jun 28 06:50:59 PM PDT 24
Peak memory 160800 kb
Host smart-76152857-9519-4817-8685-c7ea41c716a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=74333619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.74333619
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.815562367
Short name T180
Test name
Test status
Simulation time 337106610000 ps
CPU time 734 seconds
Started Jun 28 06:18:18 PM PDT 24
Finished Jun 28 06:48:46 PM PDT 24
Peak memory 160816 kb
Host smart-bd22e614-bfbe-4c92-81c1-384f09866e16
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=815562367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.815562367
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2007808957
Short name T170
Test name
Test status
Simulation time 336913230000 ps
CPU time 727.93 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:48:13 PM PDT 24
Peak memory 160824 kb
Host smart-598bbae7-9e2a-4805-bb17-64ebe16c6c8a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2007808957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2007808957
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.852802536
Short name T190
Test name
Test status
Simulation time 336665310000 ps
CPU time 881.89 seconds
Started Jun 28 06:18:12 PM PDT 24
Finished Jun 28 06:54:08 PM PDT 24
Peak memory 160820 kb
Host smart-199c3c63-8d8e-4dd4-aa76-f4ac4bf356ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=852802536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.852802536
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2560652993
Short name T26
Test name
Test status
Simulation time 336303670000 ps
CPU time 739.51 seconds
Started Jun 28 06:18:12 PM PDT 24
Finished Jun 28 06:48:58 PM PDT 24
Peak memory 160820 kb
Host smart-527a61e4-f8f0-4efb-80d1-0609044e3c78
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2560652993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2560652993
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1053551075
Short name T23
Test name
Test status
Simulation time 336934270000 ps
CPU time 707.91 seconds
Started Jun 28 06:18:12 PM PDT 24
Finished Jun 28 06:47:06 PM PDT 24
Peak memory 160856 kb
Host smart-e9040eb1-680f-4d35-b5f2-1f41c31a66fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1053551075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1053551075
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.292757910
Short name T196
Test name
Test status
Simulation time 336619590000 ps
CPU time 869.39 seconds
Started Jun 28 06:18:19 PM PDT 24
Finished Jun 28 06:54:55 PM PDT 24
Peak memory 160812 kb
Host smart-bcc8583d-414b-4a06-9f62-0a0da6ecb7bb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=292757910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.292757910
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1114381641
Short name T198
Test name
Test status
Simulation time 336574110000 ps
CPU time 825.37 seconds
Started Jun 28 06:18:13 PM PDT 24
Finished Jun 28 06:52:16 PM PDT 24
Peak memory 160836 kb
Host smart-f863f4b5-56f8-4d98-a6c7-2168a90a92a7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1114381641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1114381641
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2352817864
Short name T22
Test name
Test status
Simulation time 337012350000 ps
CPU time 795.24 seconds
Started Jun 28 06:18:09 PM PDT 24
Finished Jun 28 06:50:29 PM PDT 24
Peak memory 160804 kb
Host smart-901e416e-3e20-41ef-a66f-d69813f1dcc6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2352817864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2352817864
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3986623699
Short name T166
Test name
Test status
Simulation time 336689550000 ps
CPU time 973.23 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 07:00:15 PM PDT 24
Peak memory 160824 kb
Host smart-ff5723d3-68d1-4a77-86ba-56908df37053
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3986623699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3986623699
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.532663374
Short name T167
Test name
Test status
Simulation time 336796590000 ps
CPU time 926.2 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:57:04 PM PDT 24
Peak memory 160772 kb
Host smart-fe06273b-3109-482a-8272-6e668b1da715
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=532663374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.532663374
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.1609211925
Short name T173
Test name
Test status
Simulation time 336936450000 ps
CPU time 750.94 seconds
Started Jun 28 06:18:10 PM PDT 24
Finished Jun 28 06:49:02 PM PDT 24
Peak memory 160808 kb
Host smart-029e5e0e-5eb0-46ef-bae8-0d9b7a0ef381
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1609211925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.1609211925
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1822473432
Short name T161
Test name
Test status
Simulation time 336924850000 ps
CPU time 722.46 seconds
Started Jun 28 06:18:19 PM PDT 24
Finished Jun 28 06:47:58 PM PDT 24
Peak memory 160828 kb
Host smart-f70744b7-28e0-4e57-b701-d2a2b81d8d8f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1822473432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1822473432
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1467795341
Short name T177
Test name
Test status
Simulation time 336497770000 ps
CPU time 714.34 seconds
Started Jun 28 06:18:11 PM PDT 24
Finished Jun 28 06:47:43 PM PDT 24
Peak memory 160824 kb
Host smart-fdbab488-302e-4ba9-b71f-1e1b3e96a898
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1467795341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1467795341
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1886603871
Short name T184
Test name
Test status
Simulation time 336506230000 ps
CPU time 864.22 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:54:44 PM PDT 24
Peak memory 160820 kb
Host smart-084623d5-8be1-4208-8d27-0422ede4ec1e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1886603871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1886603871
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.480158494
Short name T185
Test name
Test status
Simulation time 336430350000 ps
CPU time 796.07 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:50:40 PM PDT 24
Peak memory 160816 kb
Host smart-39bdb131-17bd-42aa-bc75-f0af513dd7da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=480158494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.480158494
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3126942663
Short name T187
Test name
Test status
Simulation time 336792350000 ps
CPU time 928.17 seconds
Started Jun 28 06:18:09 PM PDT 24
Finished Jun 28 06:56:45 PM PDT 24
Peak memory 160780 kb
Host smart-a21d5496-3dd7-4a55-bceb-7f34509a3618
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3126942663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3126942663
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.352178315
Short name T197
Test name
Test status
Simulation time 336499950000 ps
CPU time 774.77 seconds
Started Jun 28 06:18:08 PM PDT 24
Finished Jun 28 06:49:55 PM PDT 24
Peak memory 160824 kb
Host smart-f82c990f-3c95-45fe-aba8-67bfd9bcadf8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=352178315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.352178315
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2723696238
Short name T194
Test name
Test status
Simulation time 336991610000 ps
CPU time 764.96 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:50:00 PM PDT 24
Peak memory 160828 kb
Host smart-03d9be41-6c4d-4aa4-ad5b-b23136d502d0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2723696238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2723696238
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.245123747
Short name T189
Test name
Test status
Simulation time 337083890000 ps
CPU time 939.92 seconds
Started Jun 28 06:18:14 PM PDT 24
Finished Jun 28 06:57:26 PM PDT 24
Peak memory 160772 kb
Host smart-f7a4e2e0-f525-4fad-8483-430c205c6961
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=245123747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.245123747
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1997701535
Short name T182
Test name
Test status
Simulation time 336804770000 ps
CPU time 789.34 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:50:20 PM PDT 24
Peak memory 160828 kb
Host smart-5800a261-6297-4b1c-9bb4-21ff8a895ee0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997701535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1997701535
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.394326930
Short name T176
Test name
Test status
Simulation time 336631110000 ps
CPU time 694.55 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:47:11 PM PDT 24
Peak memory 160816 kb
Host smart-8fecd867-aa25-4a7a-9d5a-6c6d43ce1779
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=394326930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.394326930
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.166560149
Short name T172
Test name
Test status
Simulation time 337109450000 ps
CPU time 678.83 seconds
Started Jun 28 06:18:13 PM PDT 24
Finished Jun 28 06:46:47 PM PDT 24
Peak memory 160832 kb
Host smart-14c6723c-0d0b-4df8-9556-23c175d7bb5f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=166560149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.166560149
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3789741653
Short name T162
Test name
Test status
Simulation time 336362590000 ps
CPU time 705.28 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:47:50 PM PDT 24
Peak memory 160828 kb
Host smart-09ff8283-cd68-40cf-9276-1b948615aaf5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3789741653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3789741653
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1032340597
Short name T163
Test name
Test status
Simulation time 336815330000 ps
CPU time 755.61 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:49:13 PM PDT 24
Peak memory 160828 kb
Host smart-c1696b36-e643-424b-95b6-b5d149ab963a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1032340597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1032340597
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1186633611
Short name T28
Test name
Test status
Simulation time 336714270000 ps
CPU time 701.56 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:47:23 PM PDT 24
Peak memory 160828 kb
Host smart-1bcd9378-0516-430a-b2c9-d4c6c0cae21f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1186633611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1186633611
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3281229686
Short name T174
Test name
Test status
Simulation time 336991770000 ps
CPU time 969.58 seconds
Started Jun 28 06:18:16 PM PDT 24
Finished Jun 28 07:00:17 PM PDT 24
Peak memory 160824 kb
Host smart-51ce7c41-550a-4867-a758-9ca151667469
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3281229686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3281229686
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1736352199
Short name T24
Test name
Test status
Simulation time 336577310000 ps
CPU time 694.88 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:47:10 PM PDT 24
Peak memory 160824 kb
Host smart-068833a9-1ab8-4a47-ac04-cc04837af7b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1736352199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1736352199
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2125901013
Short name T165
Test name
Test status
Simulation time 336495970000 ps
CPU time 850.82 seconds
Started Jun 28 06:18:27 PM PDT 24
Finished Jun 28 06:54:04 PM PDT 24
Peak memory 160824 kb
Host smart-1a79c7fb-7465-4746-89eb-b2785661231d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2125901013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2125901013
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1473179764
Short name T193
Test name
Test status
Simulation time 336423070000 ps
CPU time 781.84 seconds
Started Jun 28 06:18:25 PM PDT 24
Finished Jun 28 06:50:56 PM PDT 24
Peak memory 160820 kb
Host smart-d9fe8a42-1d20-434b-8c7a-0aa0b70bcd03
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1473179764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1473179764
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1750329697
Short name T169
Test name
Test status
Simulation time 336640590000 ps
CPU time 748 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:49:05 PM PDT 24
Peak memory 160820 kb
Host smart-6c966d88-8e0e-44e4-a9b2-561ecda8e0df
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1750329697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1750329697
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.630503991
Short name T29
Test name
Test status
Simulation time 336415850000 ps
CPU time 870.5 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:54:15 PM PDT 24
Peak memory 160820 kb
Host smart-b20ea56d-909e-45af-912e-33011fbf7646
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=630503991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.630503991
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1271816464
Short name T200
Test name
Test status
Simulation time 336474090000 ps
CPU time 773.13 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:49:56 PM PDT 24
Peak memory 160832 kb
Host smart-0753a766-1485-4457-bdd6-a5424f5776c2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1271816464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1271816464
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2967055367
Short name T186
Test name
Test status
Simulation time 336466730000 ps
CPU time 849.8 seconds
Started Jun 28 06:18:09 PM PDT 24
Finished Jun 28 06:53:39 PM PDT 24
Peak memory 160820 kb
Host smart-f8d4f20e-ef75-45a8-84fb-919ca8939de3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2967055367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2967055367
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1236350896
Short name T25
Test name
Test status
Simulation time 336690690000 ps
CPU time 866.08 seconds
Started Jun 28 06:18:22 PM PDT 24
Finished Jun 28 06:54:14 PM PDT 24
Peak memory 160828 kb
Host smart-fde98101-cb66-4bf1-a9db-0e60ca1e8d87
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1236350896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1236350896
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.3538058050
Short name T168
Test name
Test status
Simulation time 337082370000 ps
CPU time 758.51 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:49:39 PM PDT 24
Peak memory 160824 kb
Host smart-b0096359-4dc0-4b9c-8826-07d67e34ffb8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3538058050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.3538058050
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.4107531169
Short name T195
Test name
Test status
Simulation time 336977290000 ps
CPU time 798.29 seconds
Started Jun 28 06:18:24 PM PDT 24
Finished Jun 28 06:50:41 PM PDT 24
Peak memory 160820 kb
Host smart-90e99bee-b7dd-4839-8c19-539c0e4bf860
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4107531169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.4107531169
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3215938416
Short name T164
Test name
Test status
Simulation time 336703630000 ps
CPU time 825.76 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:52:26 PM PDT 24
Peak memory 160836 kb
Host smart-0138a343-9b62-44c0-a2a1-7acbaa55b444
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3215938416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3215938416
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3732973777
Short name T171
Test name
Test status
Simulation time 336659230000 ps
CPU time 885.44 seconds
Started Jun 28 06:18:14 PM PDT 24
Finished Jun 28 06:54:21 PM PDT 24
Peak memory 160828 kb
Host smart-2ea59163-bd28-4dd0-8072-542a2d676d91
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3732973777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3732973777
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1643197637
Short name T188
Test name
Test status
Simulation time 336488970000 ps
CPU time 727.74 seconds
Started Jun 28 06:18:19 PM PDT 24
Finished Jun 28 06:48:40 PM PDT 24
Peak memory 160832 kb
Host smart-3785a3c7-9e40-421f-9822-eaa7ac09c811
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643197637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1643197637
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1333764624
Short name T175
Test name
Test status
Simulation time 336482330000 ps
CPU time 735.99 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:48:38 PM PDT 24
Peak memory 160832 kb
Host smart-d79ee318-b83a-4c2f-adab-09976cfd7657
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1333764624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1333764624
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.452019018
Short name T30
Test name
Test status
Simulation time 336950850000 ps
CPU time 975.01 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 07:00:12 PM PDT 24
Peak memory 160816 kb
Host smart-e1ac6ae7-4667-40f2-884a-e1244b157b50
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=452019018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.452019018
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2110943432
Short name T27
Test name
Test status
Simulation time 336855050000 ps
CPU time 849.64 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:53:58 PM PDT 24
Peak memory 160824 kb
Host smart-8a024b99-c07d-487f-b773-047773626b6d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2110943432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2110943432
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2227361929
Short name T178
Test name
Test status
Simulation time 336667890000 ps
CPU time 755.78 seconds
Started Jun 28 06:18:18 PM PDT 24
Finished Jun 28 06:49:43 PM PDT 24
Peak memory 160824 kb
Host smart-30da86eb-10fd-48ca-b9fc-673b8dad48e8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2227361929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2227361929
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4278185912
Short name T192
Test name
Test status
Simulation time 336897530000 ps
CPU time 968.6 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 07:00:05 PM PDT 24
Peak memory 160816 kb
Host smart-b6472bb3-4d23-49ec-9d02-98bd5ea2d188
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4278185912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.4278185912
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1465553955
Short name T181
Test name
Test status
Simulation time 336657990000 ps
CPU time 865.47 seconds
Started Jun 28 06:18:14 PM PDT 24
Finished Jun 28 06:53:27 PM PDT 24
Peak memory 160816 kb
Host smart-5c63c074-b166-44f5-a90e-bdd649ef5613
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1465553955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1465553955
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.791867846
Short name T191
Test name
Test status
Simulation time 337014790000 ps
CPU time 847.66 seconds
Started Jun 28 06:18:18 PM PDT 24
Finished Jun 28 06:53:16 PM PDT 24
Peak memory 160808 kb
Host smart-5fda36c9-0540-446f-918f-e6bea1adab0a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=791867846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.791867846
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.319907278
Short name T183
Test name
Test status
Simulation time 336412170000 ps
CPU time 854.12 seconds
Started Jun 28 06:18:11 PM PDT 24
Finished Jun 28 06:53:41 PM PDT 24
Peak memory 160820 kb
Host smart-d79cebe3-c58f-42ac-98e1-e366f2f029fc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=319907278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.319907278
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1147610681
Short name T199
Test name
Test status
Simulation time 336488230000 ps
CPU time 843.44 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:53:53 PM PDT 24
Peak memory 160816 kb
Host smart-7d99802f-9081-4678-8bf1-4ceaf7c335b5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1147610681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1147610681
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2605008110
Short name T120
Test name
Test status
Simulation time 1421890000 ps
CPU time 4.78 seconds
Started Jun 28 06:11:52 PM PDT 24
Finished Jun 28 06:12:04 PM PDT 24
Peak memory 164944 kb
Host smart-202a66ac-7f43-4326-a040-59150009b1a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2605008110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2605008110
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3541909201
Short name T128
Test name
Test status
Simulation time 1424290000 ps
CPU time 4.59 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:55 PM PDT 24
Peak memory 164948 kb
Host smart-f695cd70-c4d5-48c5-af15-e37a0bbc9ded
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3541909201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3541909201
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4225523394
Short name T126
Test name
Test status
Simulation time 1530890000 ps
CPU time 4.19 seconds
Started Jun 28 06:11:49 PM PDT 24
Finished Jun 28 06:11:59 PM PDT 24
Peak memory 164884 kb
Host smart-6cab1076-cc48-4c18-b6a7-70eecf949e6a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4225523394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4225523394
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1219750013
Short name T116
Test name
Test status
Simulation time 1204370000 ps
CPU time 3.59 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:53 PM PDT 24
Peak memory 164948 kb
Host smart-218bc3d3-14e9-4701-b6c4-9063f7af4634
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1219750013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1219750013
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1442618660
Short name T149
Test name
Test status
Simulation time 1323170000 ps
CPU time 4.61 seconds
Started Jun 28 06:11:37 PM PDT 24
Finished Jun 28 06:11:49 PM PDT 24
Peak memory 164944 kb
Host smart-45cdb065-9a39-47e0-88e8-c294ce78c708
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442618660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1442618660
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1171518528
Short name T136
Test name
Test status
Simulation time 1451930000 ps
CPU time 4.28 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:54 PM PDT 24
Peak memory 164948 kb
Host smart-b65b6c28-5260-4c11-a53e-573d6e5ffdcd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1171518528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1171518528
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1968705686
Short name T152
Test name
Test status
Simulation time 1549430000 ps
CPU time 4.85 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 164952 kb
Host smart-4d51832a-b92c-431a-8ee9-aa7df0d147e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968705686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1968705686
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.4235483463
Short name T144
Test name
Test status
Simulation time 1585250000 ps
CPU time 5.61 seconds
Started Jun 28 06:11:53 PM PDT 24
Finished Jun 28 06:12:06 PM PDT 24
Peak memory 164948 kb
Host smart-e1a3cbd0-033c-40a3-82e1-25d8999b1b5f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4235483463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.4235483463
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4170754261
Short name T141
Test name
Test status
Simulation time 1556050000 ps
CPU time 4.43 seconds
Started Jun 28 06:11:54 PM PDT 24
Finished Jun 28 06:12:06 PM PDT 24
Peak memory 164944 kb
Host smart-1186b485-df50-428d-a927-c41ed5593999
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4170754261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.4170754261
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1654775663
Short name T159
Test name
Test status
Simulation time 1533650000 ps
CPU time 4.47 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 164940 kb
Host smart-0cb72cc1-92cf-46a6-adb5-861d06305978
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1654775663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1654775663
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1186619141
Short name T127
Test name
Test status
Simulation time 1421910000 ps
CPU time 3.89 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:14 PM PDT 24
Peak memory 164940 kb
Host smart-4ae6e750-43f7-494f-a554-6c967223b322
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1186619141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1186619141
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.2649339462
Short name T160
Test name
Test status
Simulation time 1472230000 ps
CPU time 4.23 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164944 kb
Host smart-ac3b23c9-de94-49eb-9360-99f493a6534f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2649339462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.2649339462
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.3783244785
Short name T143
Test name
Test status
Simulation time 1464870000 ps
CPU time 4.59 seconds
Started Jun 28 06:11:49 PM PDT 24
Finished Jun 28 06:12:00 PM PDT 24
Peak memory 164944 kb
Host smart-0d8f642b-ab22-433e-a06d-dcb626c5ebb6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3783244785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.3783244785
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2765340060
Short name T135
Test name
Test status
Simulation time 1479390000 ps
CPU time 3.81 seconds
Started Jun 28 06:11:52 PM PDT 24
Finished Jun 28 06:12:01 PM PDT 24
Peak memory 164944 kb
Host smart-8400a1a6-149e-4791-8bcc-8bc278a011ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2765340060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2765340060
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1311499174
Short name T156
Test name
Test status
Simulation time 1420190000 ps
CPU time 5.73 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164864 kb
Host smart-a823abfa-4455-4439-8250-10462bf611e2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1311499174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1311499174
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2874508139
Short name T158
Test name
Test status
Simulation time 1252570000 ps
CPU time 5.33 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 164960 kb
Host smart-c3790272-57ad-4ed2-874a-c02e2f71278c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2874508139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2874508139
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.340676873
Short name T115
Test name
Test status
Simulation time 1529390000 ps
CPU time 3.38 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 164940 kb
Host smart-5d9f70fc-345e-4880-905b-a4e24c066707
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=340676873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.340676873
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4100036043
Short name T133
Test name
Test status
Simulation time 1190030000 ps
CPU time 3.75 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 164944 kb
Host smart-b7d9c43c-6267-4a4b-90bc-52d4b55ecc98
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4100036043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4100036043
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3271419240
Short name T147
Test name
Test status
Simulation time 1478170000 ps
CPU time 4.67 seconds
Started Jun 28 06:11:54 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 164948 kb
Host smart-489a0d5e-b274-4e57-90e8-1d2051406076
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3271419240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3271419240
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2381194525
Short name T139
Test name
Test status
Simulation time 1350490000 ps
CPU time 5.51 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164948 kb
Host smart-a766fe28-b187-47d7-b042-389de97ebc37
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2381194525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.2381194525
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3347098155
Short name T114
Test name
Test status
Simulation time 1246810000 ps
CPU time 4.44 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:14 PM PDT 24
Peak memory 164948 kb
Host smart-33b7ae81-0d66-4012-bf27-e163979b2251
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347098155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3347098155
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.2526541001
Short name T142
Test name
Test status
Simulation time 1520870000 ps
CPU time 4.25 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164948 kb
Host smart-9ffcffdd-b001-40a3-bd96-9d54c396114c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526541001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.2526541001
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1505747059
Short name T121
Test name
Test status
Simulation time 1452750000 ps
CPU time 4.35 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 164956 kb
Host smart-60ba2805-5680-484a-a016-592bb8f863a9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505747059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1505747059
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1630739122
Short name T119
Test name
Test status
Simulation time 1367630000 ps
CPU time 4.64 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:55 PM PDT 24
Peak memory 164948 kb
Host smart-877d1c7a-9030-4c35-9553-8950e5706202
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1630739122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1630739122
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2564391895
Short name T112
Test name
Test status
Simulation time 1441690000 ps
CPU time 4.92 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 164964 kb
Host smart-fda303d6-5382-4236-b5dc-448868125747
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2564391895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2564391895
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2267490400
Short name T129
Test name
Test status
Simulation time 1475950000 ps
CPU time 5.26 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164944 kb
Host smart-4e6d6671-508b-489f-b81a-90b2eff63561
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2267490400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2267490400
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.52655379
Short name T113
Test name
Test status
Simulation time 1426170000 ps
CPU time 3.94 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 164872 kb
Host smart-e4ae60be-a27b-4bc4-93b5-5a9ccfc1fa3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52655379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.52655379
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2642420612
Short name T134
Test name
Test status
Simulation time 1544490000 ps
CPU time 4.47 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 164940 kb
Host smart-7a09b946-c084-42d5-a7e3-9a9ce1ff9b64
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2642420612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2642420612
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.2132518123
Short name T138
Test name
Test status
Simulation time 1501530000 ps
CPU time 4.22 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 164940 kb
Host smart-87b58408-99a8-4810-9e01-bc76f17dac9f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132518123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.2132518123
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2751309994
Short name T123
Test name
Test status
Simulation time 1447250000 ps
CPU time 5.72 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164844 kb
Host smart-ecc80f66-677c-4c81-84e5-44ab34fc52b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2751309994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2751309994
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.2639937814
Short name T118
Test name
Test status
Simulation time 1553750000 ps
CPU time 3.99 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 164900 kb
Host smart-3723dd85-5118-40d6-949b-c4f354ce0219
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2639937814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.2639937814
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1686712721
Short name T155
Test name
Test status
Simulation time 1451610000 ps
CPU time 4.21 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 164944 kb
Host smart-480e761c-7a1c-4d5d-ba3e-54f6af11e4fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1686712721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1686712721
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.689718761
Short name T117
Test name
Test status
Simulation time 1460710000 ps
CPU time 3.69 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 164900 kb
Host smart-b085a1f7-6132-45cf-9f80-67eb4692333f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=689718761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.689718761
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3472900341
Short name T132
Test name
Test status
Simulation time 1505830000 ps
CPU time 5.01 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 164944 kb
Host smart-cad0fe97-b58d-4d37-a74f-d2b02762ea0f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3472900341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3472900341
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1537333588
Short name T157
Test name
Test status
Simulation time 1434430000 ps
CPU time 5.39 seconds
Started Jun 28 06:11:39 PM PDT 24
Finished Jun 28 06:11:52 PM PDT 24
Peak memory 164948 kb
Host smart-7b242823-9fb9-4e71-90cd-1adeb0a55064
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1537333588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1537333588
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1132755809
Short name T154
Test name
Test status
Simulation time 1209730000 ps
CPU time 4.27 seconds
Started Jun 28 06:11:54 PM PDT 24
Finished Jun 28 06:12:06 PM PDT 24
Peak memory 164956 kb
Host smart-0e1c1dee-8507-47e0-bd73-f9fba71b5a56
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132755809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1132755809
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3338992834
Short name T131
Test name
Test status
Simulation time 1469070000 ps
CPU time 4.48 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:16 PM PDT 24
Peak memory 164948 kb
Host smart-9fc16254-0b7a-4221-9eb8-7994a75824de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338992834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3338992834
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.982405587
Short name T125
Test name
Test status
Simulation time 1487610000 ps
CPU time 5.25 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164944 kb
Host smart-40d59f8b-f6fc-4274-9e8c-0b2541dd87d6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982405587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.982405587
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1563107806
Short name T150
Test name
Test status
Simulation time 1400950000 ps
CPU time 4.25 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 164932 kb
Host smart-fa339ce1-220c-45e4-95b3-9cb89941e3b5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1563107806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1563107806
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2435660399
Short name T146
Test name
Test status
Simulation time 1484110000 ps
CPU time 4.42 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 164948 kb
Host smart-3370a630-83bf-41da-b589-ffc6373a9fdb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435660399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2435660399
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1955904442
Short name T153
Test name
Test status
Simulation time 1486790000 ps
CPU time 3.69 seconds
Started Jun 28 06:12:04 PM PDT 24
Finished Jun 28 06:12:19 PM PDT 24
Peak memory 164944 kb
Host smart-9f7fefc2-14ef-4ce4-af3f-b9be1e23f378
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955904442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1955904442
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2467309731
Short name T151
Test name
Test status
Simulation time 1263730000 ps
CPU time 3.88 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164952 kb
Host smart-d58341f8-e3b7-4e8d-9beb-624c906f5d6a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2467309731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2467309731
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.1875250583
Short name T148
Test name
Test status
Simulation time 1577630000 ps
CPU time 5.43 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:13 PM PDT 24
Peak memory 164944 kb
Host smart-5bcb92b9-45bc-4bbf-bbae-50d0d1be9c27
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1875250583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.1875250583
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3562967045
Short name T111
Test name
Test status
Simulation time 1044350000 ps
CPU time 2.62 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 164900 kb
Host smart-a6ce4ec7-e642-4947-9a74-9e0ae495efb1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3562967045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3562967045
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.428605299
Short name T145
Test name
Test status
Simulation time 1445670000 ps
CPU time 3.52 seconds
Started Jun 28 06:11:54 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 164944 kb
Host smart-2f2ac9d0-9001-43a4-a3dd-547fa2b3b293
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=428605299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.428605299
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2477564669
Short name T140
Test name
Test status
Simulation time 1575950000 ps
CPU time 5.49 seconds
Started Jun 28 06:11:50 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 164940 kb
Host smart-379be39a-303e-4dbb-bd49-56775d94ae22
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477564669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2477564669
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2177722844
Short name T124
Test name
Test status
Simulation time 1407930000 ps
CPU time 4.37 seconds
Started Jun 28 06:11:45 PM PDT 24
Finished Jun 28 06:11:57 PM PDT 24
Peak memory 164944 kb
Host smart-96f0f719-b00f-4ac8-bf22-2ef962f28c2b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177722844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2177722844
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.199624915
Short name T130
Test name
Test status
Simulation time 1505490000 ps
CPU time 4.82 seconds
Started Jun 28 06:11:50 PM PDT 24
Finished Jun 28 06:12:02 PM PDT 24
Peak memory 164848 kb
Host smart-ec6f3f0e-e8ae-40f9-9bb2-edb8ad275d89
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=199624915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.199624915
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1703168271
Short name T137
Test name
Test status
Simulation time 1411070000 ps
CPU time 4.53 seconds
Started Jun 28 06:11:50 PM PDT 24
Finished Jun 28 06:12:01 PM PDT 24
Peak memory 164944 kb
Host smart-541a0422-8c90-45bc-8e3e-ac8896f44c3a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1703168271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1703168271
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.617640889
Short name T122
Test name
Test status
Simulation time 1507270000 ps
CPU time 4.51 seconds
Started Jun 28 06:11:43 PM PDT 24
Finished Jun 28 06:11:56 PM PDT 24
Peak memory 164872 kb
Host smart-009ee3d3-de1d-494b-9378-111d075b6c2e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=617640889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.617640889
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1956217910
Short name T36
Test name
Test status
Simulation time 1428590000 ps
CPU time 4.27 seconds
Started Jun 28 06:07:02 PM PDT 24
Finished Jun 28 06:07:12 PM PDT 24
Peak memory 164916 kb
Host smart-1924a9df-16e0-4a96-881d-b33aeba0ae32
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1956217910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1956217910
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1061825173
Short name T46
Test name
Test status
Simulation time 1520390000 ps
CPU time 3.9 seconds
Started Jun 28 06:07:00 PM PDT 24
Finished Jun 28 06:07:10 PM PDT 24
Peak memory 164952 kb
Host smart-44eb3f74-bead-4066-a346-23120c6466c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1061825173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1061825173
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1173526858
Short name T44
Test name
Test status
Simulation time 1576810000 ps
CPU time 5.91 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:19 PM PDT 24
Peak memory 164948 kb
Host smart-c39e9683-85fc-4b0b-ac5a-ea8f8ca60e6d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1173526858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1173526858
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4064521222
Short name T40
Test name
Test status
Simulation time 1378150000 ps
CPU time 4.76 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164944 kb
Host smart-f8b9a9e7-4aec-4696-bf87-c7be19e6a079
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4064521222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4064521222
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.335196457
Short name T63
Test name
Test status
Simulation time 1527410000 ps
CPU time 5.03 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164924 kb
Host smart-4328bd73-f815-49fd-8173-704102bf62fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=335196457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.335196457
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3362059154
Short name T61
Test name
Test status
Simulation time 1573350000 ps
CPU time 5.53 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164940 kb
Host smart-02f938f6-4857-416a-b857-6c9361c38a34
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3362059154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3362059154
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.3389384875
Short name T35
Test name
Test status
Simulation time 1481890000 ps
CPU time 3.84 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:15 PM PDT 24
Peak memory 164896 kb
Host smart-b87030c5-6631-44dd-935b-79ed31957852
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3389384875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.3389384875
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2760902340
Short name T64
Test name
Test status
Simulation time 1646570000 ps
CPU time 4.96 seconds
Started Jun 28 06:07:02 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164920 kb
Host smart-2a2c2737-20e9-4c91-974f-dc49dcbb4842
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2760902340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2760902340
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.336366060
Short name T50
Test name
Test status
Simulation time 1353250000 ps
CPU time 4.41 seconds
Started Jun 28 06:07:01 PM PDT 24
Finished Jun 28 06:07:11 PM PDT 24
Peak memory 164944 kb
Host smart-6cee21c6-6d4a-484a-9860-29b545a18340
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=336366060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.336366060
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2762349527
Short name T34
Test name
Test status
Simulation time 1559230000 ps
CPU time 4.06 seconds
Started Jun 28 06:07:02 PM PDT 24
Finished Jun 28 06:07:12 PM PDT 24
Peak memory 164956 kb
Host smart-a1677019-8092-4976-9cfe-a6cd41f79cd4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2762349527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2762349527
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3778102861
Short name T60
Test name
Test status
Simulation time 1492670000 ps
CPU time 4.67 seconds
Started Jun 28 06:07:02 PM PDT 24
Finished Jun 28 06:07:13 PM PDT 24
Peak memory 164924 kb
Host smart-c3941b08-5417-4740-aeef-7c3dda659945
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3778102861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3778102861
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.4203241814
Short name T42
Test name
Test status
Simulation time 1364570000 ps
CPU time 4.91 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:15 PM PDT 24
Peak memory 164944 kb
Host smart-452e9605-9c4e-4dc9-9eee-e9948e4d0de9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4203241814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.4203241814
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2012326428
Short name T53
Test name
Test status
Simulation time 1320670000 ps
CPU time 4.56 seconds
Started Jun 28 06:07:08 PM PDT 24
Finished Jun 28 06:07:19 PM PDT 24
Peak memory 164948 kb
Host smart-6b446de2-38b5-43b2-97bd-1cf6863424eb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2012326428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2012326428
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1228074740
Short name T55
Test name
Test status
Simulation time 1552350000 ps
CPU time 5.05 seconds
Started Jun 28 06:07:01 PM PDT 24
Finished Jun 28 06:07:13 PM PDT 24
Peak memory 164948 kb
Host smart-1db5ab7c-f1ec-46db-b28d-3f4ae2f1b44c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1228074740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1228074740
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2399353005
Short name T49
Test name
Test status
Simulation time 1516910000 ps
CPU time 4.88 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:19 PM PDT 24
Peak memory 164912 kb
Host smart-2883e963-679e-4dab-9724-067ee8d356ae
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2399353005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2399353005
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.219507331
Short name T59
Test name
Test status
Simulation time 1387490000 ps
CPU time 4.51 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164940 kb
Host smart-1fea4575-5cf3-4cfb-a4b4-60324951504f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=219507331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.219507331
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3208650047
Short name T68
Test name
Test status
Simulation time 1527130000 ps
CPU time 5.17 seconds
Started Jun 28 06:07:08 PM PDT 24
Finished Jun 28 06:07:21 PM PDT 24
Peak memory 164948 kb
Host smart-0a55f0d1-b550-4919-910e-bdcfa7877c6d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3208650047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3208650047
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4105703350
Short name T58
Test name
Test status
Simulation time 1493890000 ps
CPU time 4.81 seconds
Started Jun 28 06:07:01 PM PDT 24
Finished Jun 28 06:07:13 PM PDT 24
Peak memory 164924 kb
Host smart-0cbd56d0-8ad5-4b43-b8d9-2170ef44da36
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4105703350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4105703350
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3366453270
Short name T43
Test name
Test status
Simulation time 1528430000 ps
CPU time 3.99 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:16 PM PDT 24
Peak memory 164900 kb
Host smart-744acd9a-2d26-41a1-93a3-1fae92c0b963
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366453270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3366453270
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.1729276455
Short name T10
Test name
Test status
Simulation time 1349690000 ps
CPU time 5.12 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164948 kb
Host smart-3590e2f1-20f4-450f-a1d9-35cd6d610100
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1729276455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.1729276455
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2134295114
Short name T51
Test name
Test status
Simulation time 1461710000 ps
CPU time 4.82 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164924 kb
Host smart-84b2c136-1fd3-45f8-a930-8230bcab7cd8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2134295114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2134295114
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.499589651
Short name T39
Test name
Test status
Simulation time 1337590000 ps
CPU time 4.33 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164900 kb
Host smart-b49928a3-ddfb-4446-9d32-453797e23f82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=499589651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.499589651
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1463776930
Short name T37
Test name
Test status
Simulation time 1471230000 ps
CPU time 5.68 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164944 kb
Host smart-5ddc64e9-8717-45f9-bb16-48b0449df9af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463776930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1463776930
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2863537919
Short name T9
Test name
Test status
Simulation time 1298450000 ps
CPU time 5.4 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:21 PM PDT 24
Peak memory 164868 kb
Host smart-a7932016-648b-4778-8cd5-66c9c3c88d83
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2863537919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2863537919
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1876955804
Short name T57
Test name
Test status
Simulation time 1343290000 ps
CPU time 4.12 seconds
Started Jun 28 06:07:02 PM PDT 24
Finished Jun 28 06:07:12 PM PDT 24
Peak memory 164916 kb
Host smart-5a9c22d2-1826-43d5-b33f-d7c31fa0342d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1876955804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1876955804
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.363271541
Short name T41
Test name
Test status
Simulation time 1573990000 ps
CPU time 6.74 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:24 PM PDT 24
Peak memory 164932 kb
Host smart-c59191a8-424e-4ed1-be53-330c3cd8e862
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=363271541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.363271541
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1227977564
Short name T54
Test name
Test status
Simulation time 1429790000 ps
CPU time 3.33 seconds
Started Jun 28 06:07:00 PM PDT 24
Finished Jun 28 06:07:08 PM PDT 24
Peak memory 164952 kb
Host smart-2cb16948-dd69-47ce-ada2-7ec1dbe470c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1227977564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1227977564
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2870673884
Short name T1
Test name
Test status
Simulation time 1547850000 ps
CPU time 5.39 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:16 PM PDT 24
Peak memory 164948 kb
Host smart-df98ec30-dd01-4db1-8d72-fe936a639a57
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2870673884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2870673884
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1826061713
Short name T38
Test name
Test status
Simulation time 1335550000 ps
CPU time 4.13 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164932 kb
Host smart-8a0e7aa7-4fdf-4f0a-ac88-d5f9029a9c1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1826061713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1826061713
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.2967742954
Short name T70
Test name
Test status
Simulation time 1440110000 ps
CPU time 5.28 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164948 kb
Host smart-fa1d962a-01ed-4c21-a1f3-74fc2bcad2e1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2967742954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.2967742954
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.299094362
Short name T11
Test name
Test status
Simulation time 1535510000 ps
CPU time 3.58 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164940 kb
Host smart-13bb5da2-7875-403b-ae89-a3e156199fdc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299094362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.299094362
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.3528360893
Short name T52
Test name
Test status
Simulation time 1494630000 ps
CPU time 5.08 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:20 PM PDT 24
Peak memory 164948 kb
Host smart-de576063-4f9e-47a3-8d1c-1a4ed08667bf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3528360893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.3528360893
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1395389090
Short name T66
Test name
Test status
Simulation time 1516990000 ps
CPU time 4 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164936 kb
Host smart-fe70ad47-1475-4d02-a258-a1d980ee8861
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1395389090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1395389090
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.9907582
Short name T45
Test name
Test status
Simulation time 1264490000 ps
CPU time 3.84 seconds
Started Jun 28 06:07:03 PM PDT 24
Finished Jun 28 06:07:12 PM PDT 24
Peak memory 164900 kb
Host smart-8cabf339-7535-4379-9099-f537197efcd6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=9907582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.9907582
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.2824481557
Short name T31
Test name
Test status
Simulation time 1616330000 ps
CPU time 6.24 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:23 PM PDT 24
Peak memory 164696 kb
Host smart-91dacadc-ebd5-4b4d-9399-026525739f1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2824481557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.2824481557
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.2039682889
Short name T13
Test name
Test status
Simulation time 1275530000 ps
CPU time 4.04 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:16 PM PDT 24
Peak memory 164796 kb
Host smart-ff4b1030-51a9-43dc-8d20-e6e83a48315a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2039682889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.2039682889
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2553263457
Short name T4
Test name
Test status
Simulation time 1522310000 ps
CPU time 6.11 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:23 PM PDT 24
Peak memory 164740 kb
Host smart-4af93825-e059-44aa-8b48-d8920fed61ea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2553263457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2553263457
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2612526835
Short name T12
Test name
Test status
Simulation time 1396150000 ps
CPU time 4.59 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:16 PM PDT 24
Peak memory 164944 kb
Host smart-34917d4f-8c5c-4132-b67c-6085a27ae1ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2612526835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2612526835
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2153307179
Short name T47
Test name
Test status
Simulation time 1573330000 ps
CPU time 6.16 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164944 kb
Host smart-8016d0de-89d7-431d-aefb-0406dba3d20c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2153307179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2153307179
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1929130623
Short name T67
Test name
Test status
Simulation time 1596690000 ps
CPU time 5.77 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:18 PM PDT 24
Peak memory 164944 kb
Host smart-107f37c7-75c4-4b13-ab53-bd750d96d0cf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1929130623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1929130623
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3254691235
Short name T32
Test name
Test status
Simulation time 1440050000 ps
CPU time 4.68 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:17 PM PDT 24
Peak memory 164952 kb
Host smart-e2c2ceca-197d-491e-aac4-1fa42c4f853a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3254691235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3254691235
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3699835651
Short name T65
Test name
Test status
Simulation time 1568590000 ps
CPU time 6.08 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:19 PM PDT 24
Peak memory 164944 kb
Host smart-118ad74d-c1aa-4d70-9fbc-1203d805e2e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699835651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3699835651
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2647836758
Short name T33
Test name
Test status
Simulation time 1394610000 ps
CPU time 4.03 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:15 PM PDT 24
Peak memory 164944 kb
Host smart-827ca645-5b4c-40bf-bf77-67fac45865fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2647836758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2647836758
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2815413241
Short name T56
Test name
Test status
Simulation time 1380490000 ps
CPU time 3.72 seconds
Started Jun 28 06:07:04 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164944 kb
Host smart-c9a290ec-2ff9-467e-aaea-8c3acd2e9f44
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2815413241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2815413241
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2338674031
Short name T62
Test name
Test status
Simulation time 1485630000 ps
CPU time 4.97 seconds
Started Jun 28 06:07:02 PM PDT 24
Finished Jun 28 06:07:14 PM PDT 24
Peak memory 164944 kb
Host smart-702f913a-aaaa-490c-81a0-c7a371ab1c65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2338674031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2338674031
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1607556891
Short name T2
Test name
Test status
Simulation time 1492190000 ps
CPU time 4.66 seconds
Started Jun 28 06:07:07 PM PDT 24
Finished Jun 28 06:07:19 PM PDT 24
Peak memory 164972 kb
Host smart-4be6cce8-a1dc-4cf4-b839-8429ff313fa1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1607556891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.1607556891
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3967493410
Short name T3
Test name
Test status
Simulation time 1364830000 ps
CPU time 4.08 seconds
Started Jun 28 06:07:01 PM PDT 24
Finished Jun 28 06:07:10 PM PDT 24
Peak memory 164964 kb
Host smart-f9286fb0-b231-4870-bcd7-8d4a92450007
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967493410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3967493410
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1910532307
Short name T48
Test name
Test status
Simulation time 1255190000 ps
CPU time 4.78 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:17 PM PDT 24
Peak memory 164948 kb
Host smart-f3e35864-41e1-45ce-98f0-03c81b61a5f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910532307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1910532307
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.69738078
Short name T69
Test name
Test status
Simulation time 1326130000 ps
CPU time 4.41 seconds
Started Jun 28 06:07:05 PM PDT 24
Finished Jun 28 06:07:17 PM PDT 24
Peak memory 164732 kb
Host smart-e8f44c0e-0e82-476f-a26e-08c67e0973ba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69738078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.69738078
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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