Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.195771315
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.99935260
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.496150747

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1883591781
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3828305700
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.253574587
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3355392414
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2082957764
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1774258732
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2754580001
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1371569267
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.833228805
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2116630374
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2118289102
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3545641911
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3107838533
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1538941772
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1384780740
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.285389402
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3028043470
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.955653273
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.612789173
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3652604126
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2621889964
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1885064493
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1686041617
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4051059479
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3709131353
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3227843271
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2063383703
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1801020090
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.4279262997
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2785474080
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2630293806
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.873696570
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3772762312
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1669725522
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.921110061
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2157920472
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2877365874
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3053423589
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.822624535
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3833740742
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3385166687
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3228188681
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2445862633
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3016368129
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1932419753
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2325294113
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3509880995
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1228740903
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3421518845
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1812217116
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.155784572
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2851960477
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2587697762
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2241695049
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1928952916
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2982743783
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3353779729
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.53354995
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.44134666
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1981042801
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4006712668
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.429892105
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3258336900
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2453182774
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.941814105
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2636821891
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4187507698
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2895483264
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3097406354
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2818209672
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2562971983
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2908271879
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1881218880
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2147421896
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2230634456
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2737931914
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3683377112
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2422325823
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1206922640
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.914241533
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2006427211
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2325204767
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2309893509
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3793987529
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2009977114
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1491798427
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2654323963
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2960244414
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3580954646
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1841274311
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4017078490
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.330642942
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3544344144
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1671179933
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1517462283
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3545296347
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3607720308
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1030634523
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1816448568
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1332863089
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4114461634
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.103283281
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.229026267
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3633233554
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.141287142
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.667509411
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3926528683
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1548631406
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2904777506
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1587185914
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.321665313
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2315434011
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3177523248
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.502395393
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2905892838
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4076310890
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3248639132
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.55646522
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1607078342
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1947532698
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1054553567
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1577724079
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.186127783
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.395638321
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.429719448
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2722238512
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3822458894
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.804532568
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1570603219
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1397817852
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2798230710
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2487448307
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2758740793
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2200787674
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.910036849
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3710256848
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3488128346
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1733727338
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.642032424
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.47649841
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4097675104
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3633618759
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2895539172
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1101290026
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2618916200
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1139136374
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1845848297
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2089491507
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3968041734
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1580718248
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1515317628
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.915858223
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4281313373
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3920238031
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.803003610
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.379925388
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2032825250
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2942836280
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.214515972
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2896673831
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.997896829
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3940817832
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.454558039
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1070400769
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1257626792
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3118454257
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3788825811
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.681531895
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3780385555
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.731198538
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1672584959
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1407515114
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.504601749
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2468424517
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3391557885
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1694596870
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3726048705
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1630730608
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1887524707
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1388305414
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2622491366
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2125085102
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3376557534
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1868453968
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1484430018
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1747567479
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2046692757
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3212574968
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4016585838
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1586020876
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1968972381
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4233921859
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3425234498
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2107141393
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4232730452
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4104707747
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2898800549



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1868453968 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1594130000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.195771315 Jun 29 06:16:12 PM PDT 24 Jun 29 06:16:23 PM PDT 24 1517270000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3788825811 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:31 PM PDT 24 1172410000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.379925388 Jun 29 06:16:11 PM PDT 24 Jun 29 06:16:23 PM PDT 24 1406190000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2046692757 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:31 PM PDT 24 1366530000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2896673831 Jun 29 06:16:01 PM PDT 24 Jun 29 06:16:13 PM PDT 24 1235070000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3376557534 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:35 PM PDT 24 1447010000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1694596870 Jun 29 06:16:22 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1204290000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1968972381 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1362950000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1586020876 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:32 PM PDT 24 1553890000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4281313373 Jun 29 06:16:13 PM PDT 24 Jun 29 06:16:22 PM PDT 24 1516930000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2032825250 Jun 29 06:16:15 PM PDT 24 Jun 29 06:16:28 PM PDT 24 1434910000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1747567479 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:28 PM PDT 24 1090830000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1388305414 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:30 PM PDT 24 1382670000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3920238031 Jun 29 06:16:11 PM PDT 24 Jun 29 06:16:23 PM PDT 24 1408310000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1887524707 Jun 29 06:16:25 PM PDT 24 Jun 29 06:16:36 PM PDT 24 1540270000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2107141393 Jun 29 06:16:01 PM PDT 24 Jun 29 06:16:13 PM PDT 24 1382690000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3780385555 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1473250000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.915858223 Jun 29 06:16:12 PM PDT 24 Jun 29 06:16:24 PM PDT 24 1602990000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1407515114 Jun 29 06:16:19 PM PDT 24 Jun 29 06:16:26 PM PDT 24 1126250000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4233921859 Jun 29 06:16:23 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1178270000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2898800549 Jun 29 06:16:15 PM PDT 24 Jun 29 06:16:27 PM PDT 24 1497670000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.504601749 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:32 PM PDT 24 1477870000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1672584959 Jun 29 06:16:05 PM PDT 24 Jun 29 06:16:15 PM PDT 24 1577490000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.454558039 Jun 29 06:16:19 PM PDT 24 Jun 29 06:16:31 PM PDT 24 1313990000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.803003610 Jun 29 06:16:10 PM PDT 24 Jun 29 06:16:21 PM PDT 24 1455730000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4104707747 Jun 29 06:16:13 PM PDT 24 Jun 29 06:16:22 PM PDT 24 1297570000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1257626792 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:30 PM PDT 24 1497050000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2125085102 Jun 29 06:16:09 PM PDT 24 Jun 29 06:16:20 PM PDT 24 1333710000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.681531895 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:33 PM PDT 24 1426230000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3212574968 Jun 29 06:16:23 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1521910000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1484430018 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:35 PM PDT 24 1579950000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.997896829 Jun 29 06:16:09 PM PDT 24 Jun 29 06:16:19 PM PDT 24 1413410000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.731198538 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1358590000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2942836280 Jun 29 06:16:11 PM PDT 24 Jun 29 06:16:21 PM PDT 24 1546550000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.214515972 Jun 29 06:16:11 PM PDT 24 Jun 29 06:16:22 PM PDT 24 1282150000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3391557885 Jun 29 06:16:23 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1582750000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3968041734 Jun 29 06:16:04 PM PDT 24 Jun 29 06:16:14 PM PDT 24 1318850000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4016585838 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1530830000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1630730608 Jun 29 06:16:23 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1415890000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2622491366 Jun 29 06:16:19 PM PDT 24 Jun 29 06:16:34 PM PDT 24 1624690000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1580718248 Jun 29 06:16:06 PM PDT 24 Jun 29 06:16:14 PM PDT 24 1190530000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1515317628 Jun 29 06:16:11 PM PDT 24 Jun 29 06:16:23 PM PDT 24 1349830000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1070400769 Jun 29 06:16:20 PM PDT 24 Jun 29 06:16:32 PM PDT 24 1468730000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3726048705 Jun 29 06:16:27 PM PDT 24 Jun 29 06:16:38 PM PDT 24 1529150000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4232730452 Jun 29 06:16:10 PM PDT 24 Jun 29 06:16:23 PM PDT 24 1572830000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3425234498 Jun 29 06:16:03 PM PDT 24 Jun 29 06:16:17 PM PDT 24 1554230000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3118454257 Jun 29 06:16:22 PM PDT 24 Jun 29 06:16:31 PM PDT 24 1358450000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3940817832 Jun 29 06:16:19 PM PDT 24 Jun 29 06:16:31 PM PDT 24 1522830000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2468424517 Jun 29 06:16:21 PM PDT 24 Jun 29 06:16:30 PM PDT 24 1255090000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2785474080 Jun 29 06:14:05 PM PDT 24 Jun 29 06:44:08 PM PDT 24 336830270000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4051059479 Jun 29 06:14:07 PM PDT 24 Jun 29 06:55:53 PM PDT 24 336470410000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.99935260 Jun 29 06:13:52 PM PDT 24 Jun 29 06:55:42 PM PDT 24 336532390000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3107838533 Jun 29 06:13:51 PM PDT 24 Jun 29 06:46:42 PM PDT 24 336765930000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3509880995 Jun 29 06:13:54 PM PDT 24 Jun 29 06:55:51 PM PDT 24 336883370000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3053423589 Jun 29 06:14:05 PM PDT 24 Jun 29 06:46:04 PM PDT 24 336843230000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1538941772 Jun 29 06:13:55 PM PDT 24 Jun 29 06:48:22 PM PDT 24 336784990000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1686041617 Jun 29 06:13:52 PM PDT 24 Jun 29 06:56:25 PM PDT 24 336761650000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1932419753 Jun 29 06:13:56 PM PDT 24 Jun 29 06:48:02 PM PDT 24 336559850000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3421518845 Jun 29 06:13:53 PM PDT 24 Jun 29 06:49:27 PM PDT 24 336649750000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2621889964 Jun 29 06:14:02 PM PDT 24 Jun 29 06:52:06 PM PDT 24 336558830000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1228740903 Jun 29 06:13:53 PM PDT 24 Jun 29 06:47:47 PM PDT 24 336555350000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3227843271 Jun 29 06:14:01 PM PDT 24 Jun 29 06:44:40 PM PDT 24 336338730000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.955653273 Jun 29 06:14:02 PM PDT 24 Jun 29 06:43:29 PM PDT 24 336914650000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1669725522 Jun 29 06:13:52 PM PDT 24 Jun 29 06:56:23 PM PDT 24 336429150000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3016368129 Jun 29 06:14:02 PM PDT 24 Jun 29 06:55:44 PM PDT 24 336879570000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.833228805 Jun 29 06:13:51 PM PDT 24 Jun 29 06:53:38 PM PDT 24 336789790000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1801020090 Jun 29 06:14:01 PM PDT 24 Jun 29 06:45:43 PM PDT 24 336684670000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3772762312 Jun 29 06:14:01 PM PDT 24 Jun 29 06:50:12 PM PDT 24 336706590000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2445862633 Jun 29 06:14:01 PM PDT 24 Jun 29 06:46:52 PM PDT 24 337032690000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3545641911 Jun 29 06:13:53 PM PDT 24 Jun 29 06:49:31 PM PDT 24 336464950000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3652604126 Jun 29 06:14:03 PM PDT 24 Jun 29 06:49:09 PM PDT 24 336715210000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3833740742 Jun 29 06:14:03 PM PDT 24 Jun 29 06:49:43 PM PDT 24 336845770000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1774258732 Jun 29 06:13:55 PM PDT 24 Jun 29 06:49:40 PM PDT 24 336584210000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2630293806 Jun 29 06:14:03 PM PDT 24 Jun 29 06:49:57 PM PDT 24 336459110000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2877365874 Jun 29 06:14:02 PM PDT 24 Jun 29 06:44:45 PM PDT 24 336386050000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.873696570 Jun 29 06:14:07 PM PDT 24 Jun 29 06:56:19 PM PDT 24 336815090000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3228188681 Jun 29 06:14:02 PM PDT 24 Jun 29 06:44:46 PM PDT 24 336448470000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2754580001 Jun 29 06:13:53 PM PDT 24 Jun 29 06:50:20 PM PDT 24 336820350000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1885064493 Jun 29 06:14:03 PM PDT 24 Jun 29 06:48:26 PM PDT 24 336835590000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2063383703 Jun 29 06:14:03 PM PDT 24 Jun 29 06:44:52 PM PDT 24 337102490000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3028043470 Jun 29 06:14:04 PM PDT 24 Jun 29 06:47:31 PM PDT 24 336958010000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.253574587 Jun 29 06:13:53 PM PDT 24 Jun 29 06:47:46 PM PDT 24 336662850000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3828305700 Jun 29 06:13:56 PM PDT 24 Jun 29 06:51:30 PM PDT 24 336717930000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2118289102 Jun 29 06:13:52 PM PDT 24 Jun 29 06:47:33 PM PDT 24 336439250000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.822624535 Jun 29 06:14:07 PM PDT 24 Jun 29 06:47:53 PM PDT 24 337022490000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2157920472 Jun 29 06:14:03 PM PDT 24 Jun 29 06:47:46 PM PDT 24 336741910000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.921110061 Jun 29 06:14:02 PM PDT 24 Jun 29 06:45:24 PM PDT 24 336773970000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1371569267 Jun 29 06:13:52 PM PDT 24 Jun 29 06:53:28 PM PDT 24 336688490000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3709131353 Jun 29 06:14:04 PM PDT 24 Jun 29 06:50:40 PM PDT 24 336360790000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.285389402 Jun 29 06:13:54 PM PDT 24 Jun 29 06:50:16 PM PDT 24 336873790000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3355392414 Jun 29 06:13:56 PM PDT 24 Jun 29 06:51:04 PM PDT 24 336685470000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1883591781 Jun 29 06:13:52 PM PDT 24 Jun 29 06:51:12 PM PDT 24 337011510000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2325294113 Jun 29 06:13:51 PM PDT 24 Jun 29 06:49:22 PM PDT 24 336994830000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2116630374 Jun 29 06:13:52 PM PDT 24 Jun 29 06:50:07 PM PDT 24 336821170000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.4279262997 Jun 29 06:14:06 PM PDT 24 Jun 29 06:50:22 PM PDT 24 336478930000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.612789173 Jun 29 06:14:01 PM PDT 24 Jun 29 06:44:33 PM PDT 24 336996270000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3385166687 Jun 29 06:14:05 PM PDT 24 Jun 29 06:46:49 PM PDT 24 336988910000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1384780740 Jun 29 06:13:56 PM PDT 24 Jun 29 06:51:19 PM PDT 24 336708130000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2082957764 Jun 29 06:13:57 PM PDT 24 Jun 29 06:51:07 PM PDT 24 336958550000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.186127783 Jun 29 06:14:14 PM PDT 24 Jun 29 06:14:24 PM PDT 24 1533710000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2200787674 Jun 29 06:14:13 PM PDT 24 Jun 29 06:14:26 PM PDT 24 1379810000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.55646522 Jun 29 06:14:13 PM PDT 24 Jun 29 06:14:24 PM PDT 24 1327530000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1548631406 Jun 29 06:14:07 PM PDT 24 Jun 29 06:14:19 PM PDT 24 1414830000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.395638321 Jun 29 06:14:14 PM PDT 24 Jun 29 06:14:28 PM PDT 24 1539210000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1397817852 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:31 PM PDT 24 1625670000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.667509411 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:17 PM PDT 24 1509430000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3926528683 Jun 29 06:14:05 PM PDT 24 Jun 29 06:14:17 PM PDT 24 1447090000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1816448568 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:18 PM PDT 24 1431810000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2487448307 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:28 PM PDT 24 1235270000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1054553567 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:25 PM PDT 24 1504770000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.321665313 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:17 PM PDT 24 1240270000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3488128346 Jun 29 06:14:13 PM PDT 24 Jun 29 06:14:25 PM PDT 24 1502290000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.804532568 Jun 29 06:14:11 PM PDT 24 Jun 29 06:14:22 PM PDT 24 1285430000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1607078342 Jun 29 06:14:12 PM PDT 24 Jun 29 06:14:23 PM PDT 24 1506650000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.229026267 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:13 PM PDT 24 1537830000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3633233554 Jun 29 06:14:02 PM PDT 24 Jun 29 06:14:15 PM PDT 24 1531390000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1733727338 Jun 29 06:14:16 PM PDT 24 Jun 29 06:14:29 PM PDT 24 1560210000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.47649841 Jun 29 06:14:16 PM PDT 24 Jun 29 06:14:24 PM PDT 24 1140570000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3633618759 Jun 29 06:14:16 PM PDT 24 Jun 29 06:14:29 PM PDT 24 1516050000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.141287142 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:16 PM PDT 24 1403830000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2798230710 Jun 29 06:14:11 PM PDT 24 Jun 29 06:14:25 PM PDT 24 1454170000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.103283281 Jun 29 06:14:07 PM PDT 24 Jun 29 06:14:18 PM PDT 24 1308350000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4076310890 Jun 29 06:14:13 PM PDT 24 Jun 29 06:14:27 PM PDT 24 1638870000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2905892838 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:15 PM PDT 24 1403270000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.502395393 Jun 29 06:14:02 PM PDT 24 Jun 29 06:14:15 PM PDT 24 1269330000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2904777506 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:17 PM PDT 24 1609890000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1577724079 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:14 PM PDT 24 1402530000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2089491507 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:18 PM PDT 24 1402410000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1101290026 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:15 PM PDT 24 1491350000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3822458894 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:27 PM PDT 24 1477270000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3710256848 Jun 29 06:14:16 PM PDT 24 Jun 29 06:14:28 PM PDT 24 1394210000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.429719448 Jun 29 06:14:12 PM PDT 24 Jun 29 06:14:19 PM PDT 24 1429230000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1139136374 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:18 PM PDT 24 1377070000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4097675104 Jun 29 06:14:11 PM PDT 24 Jun 29 06:14:21 PM PDT 24 1499010000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1587185914 Jun 29 06:14:07 PM PDT 24 Jun 29 06:14:19 PM PDT 24 1379470000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.910036849 Jun 29 06:14:11 PM PDT 24 Jun 29 06:14:26 PM PDT 24 1389630000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1570603219 Jun 29 06:14:10 PM PDT 24 Jun 29 06:14:21 PM PDT 24 1324990000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2618916200 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:14 PM PDT 24 1282530000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1845848297 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:16 PM PDT 24 1425370000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3248639132 Jun 29 06:14:13 PM PDT 24 Jun 29 06:14:26 PM PDT 24 1482130000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1332863089 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:18 PM PDT 24 1554010000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2895539172 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:26 PM PDT 24 1613510000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2315434011 Jun 29 06:14:06 PM PDT 24 Jun 29 06:14:16 PM PDT 24 1119190000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4114461634 Jun 29 06:14:03 PM PDT 24 Jun 29 06:14:16 PM PDT 24 1399270000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1947532698 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:26 PM PDT 24 1305690000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2722238512 Jun 29 06:14:12 PM PDT 24 Jun 29 06:14:22 PM PDT 24 1440910000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3177523248 Jun 29 06:14:04 PM PDT 24 Jun 29 06:14:15 PM PDT 24 1332190000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2758740793 Jun 29 06:14:02 PM PDT 24 Jun 29 06:14:15 PM PDT 24 1537570000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.642032424 Jun 29 06:14:15 PM PDT 24 Jun 29 06:14:27 PM PDT 24 1516090000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1671179933 Jun 29 05:13:54 PM PDT 24 Jun 29 05:50:00 PM PDT 24 336529070000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1928952916 Jun 29 05:14:02 PM PDT 24 Jun 29 05:48:07 PM PDT 24 336972490000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1881218880 Jun 29 05:14:04 PM PDT 24 Jun 29 05:47:12 PM PDT 24 336974450000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2818209672 Jun 29 05:14:06 PM PDT 24 Jun 29 05:52:53 PM PDT 24 336426570000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2009977114 Jun 29 05:14:06 PM PDT 24 Jun 29 05:48:50 PM PDT 24 336387090000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2895483264 Jun 29 05:14:05 PM PDT 24 Jun 29 05:50:24 PM PDT 24 337038690000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1841274311 Jun 29 05:14:13 PM PDT 24 Jun 29 05:48:50 PM PDT 24 337133750000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4006712668 Jun 29 05:13:58 PM PDT 24 Jun 29 05:47:42 PM PDT 24 336530910000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.496150747 Jun 29 05:14:05 PM PDT 24 Jun 29 05:49:31 PM PDT 24 336750310000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2422325823 Jun 29 05:14:03 PM PDT 24 Jun 29 05:49:02 PM PDT 24 336959110000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2982743783 Jun 29 05:14:04 PM PDT 24 Jun 29 05:43:15 PM PDT 24 337009170000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.941814105 Jun 29 05:14:05 PM PDT 24 Jun 29 05:48:55 PM PDT 24 336432550000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4017078490 Jun 29 05:14:12 PM PDT 24 Jun 29 05:50:39 PM PDT 24 336918610000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2309893509 Jun 29 05:13:57 PM PDT 24 Jun 29 05:56:46 PM PDT 24 337074890000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2230634456 Jun 29 05:14:04 PM PDT 24 Jun 29 05:46:54 PM PDT 24 336788490000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3258336900 Jun 29 05:14:02 PM PDT 24 Jun 29 05:49:48 PM PDT 24 336950290000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3793987529 Jun 29 05:14:06 PM PDT 24 Jun 29 05:52:03 PM PDT 24 336856970000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2453182774 Jun 29 05:14:05 PM PDT 24 Jun 29 05:49:22 PM PDT 24 336314290000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.914241533 Jun 29 05:14:09 PM PDT 24 Jun 29 05:55:58 PM PDT 24 336936170000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3353779729 Jun 29 05:14:05 PM PDT 24 Jun 29 05:47:35 PM PDT 24 336911590000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3544344144 Jun 29 05:14:13 PM PDT 24 Jun 29 05:51:29 PM PDT 24 336796010000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2562971983 Jun 29 05:14:05 PM PDT 24 Jun 29 05:48:43 PM PDT 24 336851830000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2241695049 Jun 29 05:14:03 PM PDT 24 Jun 29 05:47:37 PM PDT 24 336861850000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.429892105 Jun 29 05:14:06 PM PDT 24 Jun 29 05:49:46 PM PDT 24 336485530000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3545296347 Jun 29 05:13:57 PM PDT 24 Jun 29 05:56:28 PM PDT 24 336748090000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3607720308 Jun 29 05:14:04 PM PDT 24 Jun 29 05:49:11 PM PDT 24 337035490000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2737931914 Jun 29 05:14:05 PM PDT 24 Jun 29 05:49:31 PM PDT 24 336580850000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2908271879 Jun 29 05:13:56 PM PDT 24 Jun 29 05:59:53 PM PDT 24 337044090000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3683377112 Jun 29 05:14:05 PM PDT 24 Jun 29 05:59:48 PM PDT 24 336498010000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1206922640 Jun 29 05:14:07 PM PDT 24 Jun 29 05:52:16 PM PDT 24 336599810000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3097406354 Jun 29 05:14:05 PM PDT 24 Jun 29 05:51:46 PM PDT 24 336425550000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1981042801 Jun 29 05:14:02 PM PDT 24 Jun 29 05:48:38 PM PDT 24 336615130000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2587697762 Jun 29 05:14:07 PM PDT 24 Jun 29 05:57:00 PM PDT 24 336624310000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2006427211 Jun 29 05:14:02 PM PDT 24 Jun 29 05:49:29 PM PDT 24 336460770000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4187507698 Jun 29 05:14:05 PM PDT 24 Jun 29 05:42:20 PM PDT 24 336516730000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2654323963 Jun 29 05:14:12 PM PDT 24 Jun 29 05:45:22 PM PDT 24 336597850000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1812217116 Jun 29 05:13:56 PM PDT 24 Jun 29 05:59:55 PM PDT 24 336698890000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.330642942 Jun 29 05:14:17 PM PDT 24 Jun 29 05:50:46 PM PDT 24 336604550000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.53354995 Jun 29 05:14:05 PM PDT 24 Jun 29 05:51:00 PM PDT 24 336665130000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3580954646 Jun 29 05:14:13 PM PDT 24 Jun 29 05:52:54 PM PDT 24 337103270000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.155784572 Jun 29 05:13:57 PM PDT 24 Jun 29 05:56:22 PM PDT 24 336566690000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2325204767 Jun 29 05:14:04 PM PDT 24 Jun 29 05:45:32 PM PDT 24 336749790000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1491798427 Jun 29 05:14:13 PM PDT 24 Jun 29 05:43:33 PM PDT 24 336704370000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2851960477 Jun 29 05:14:04 PM PDT 24 Jun 29 05:50:10 PM PDT 24 336578930000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2960244414 Jun 29 05:14:12 PM PDT 24 Jun 29 05:49:10 PM PDT 24 337064390000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2636821891 Jun 29 05:14:04 PM PDT 24 Jun 29 05:50:47 PM PDT 24 336449650000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1517462283 Jun 29 05:13:58 PM PDT 24 Jun 29 05:48:28 PM PDT 24 336292730000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2147421896 Jun 29 05:14:07 PM PDT 24 Jun 29 05:52:39 PM PDT 24 336823750000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1030634523 Jun 29 05:14:03 PM PDT 24 Jun 29 05:46:05 PM PDT 24 336744410000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.44134666 Jun 29 05:14:05 PM PDT 24 Jun 29 05:50:13 PM PDT 24 336750610000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.195771315
Short name T2
Test name
Test status
Simulation time 1517270000 ps
CPU time 4.88 seconds
Started Jun 29 06:16:12 PM PDT 24
Finished Jun 29 06:16:23 PM PDT 24
Peak memory 164924 kb
Host smart-6861b845-62b3-4e1d-8643-20a22241047b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=195771315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.195771315
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.99935260
Short name T6
Test name
Test status
Simulation time 336532390000 ps
CPU time 1006.07 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:55:42 PM PDT 24
Peak memory 160816 kb
Host smart-f4df91d6-f950-4c98-97ce-5079d3bb1e8d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=99935260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.99935260
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.496150747
Short name T29
Test name
Test status
Simulation time 336750310000 ps
CPU time 874.62 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 160812 kb
Host smart-654fa3e5-c933-429c-a0f9-93660822fde5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=496150747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.496150747
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1883591781
Short name T103
Test name
Test status
Simulation time 337011510000 ps
CPU time 925.66 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:51:12 PM PDT 24
Peak memory 160808 kb
Host smart-6f750779-c29b-4575-bd53-1dbd9f3f00aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1883591781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1883591781
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3828305700
Short name T94
Test name
Test status
Simulation time 336717930000 ps
CPU time 904.6 seconds
Started Jun 29 06:13:56 PM PDT 24
Finished Jun 29 06:51:30 PM PDT 24
Peak memory 160804 kb
Host smart-87957ad8-6851-4003-aaed-da1ebea493b9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3828305700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3828305700
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.253574587
Short name T93
Test name
Test status
Simulation time 336662850000 ps
CPU time 835.14 seconds
Started Jun 29 06:13:53 PM PDT 24
Finished Jun 29 06:47:46 PM PDT 24
Peak memory 160812 kb
Host smart-4f5527b6-ca13-46ef-bbd9-fa8cdcfbe3ea
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=253574587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.253574587
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3355392414
Short name T102
Test name
Test status
Simulation time 336685470000 ps
CPU time 901.9 seconds
Started Jun 29 06:13:56 PM PDT 24
Finished Jun 29 06:51:04 PM PDT 24
Peak memory 160812 kb
Host smart-9c752698-17ee-427c-80fc-8efb80800bfb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3355392414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3355392414
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2082957764
Short name T110
Test name
Test status
Simulation time 336958550000 ps
CPU time 901.53 seconds
Started Jun 29 06:13:57 PM PDT 24
Finished Jun 29 06:51:07 PM PDT 24
Peak memory 160816 kb
Host smart-e3e1345d-2b90-4bc4-ad8b-e39acd8f3f09
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2082957764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2082957764
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1774258732
Short name T84
Test name
Test status
Simulation time 336584210000 ps
CPU time 875.11 seconds
Started Jun 29 06:13:55 PM PDT 24
Finished Jun 29 06:49:40 PM PDT 24
Peak memory 160816 kb
Host smart-523dc608-bcbc-444f-b922-ba173f91b792
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1774258732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1774258732
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2754580001
Short name T89
Test name
Test status
Simulation time 336820350000 ps
CPU time 892.1 seconds
Started Jun 29 06:13:53 PM PDT 24
Finished Jun 29 06:50:20 PM PDT 24
Peak memory 160816 kb
Host smart-241e4d26-17c1-4391-8278-1bb60f64f51a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754580001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2754580001
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1371569267
Short name T99
Test name
Test status
Simulation time 336688490000 ps
CPU time 973.17 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:53:28 PM PDT 24
Peak memory 160816 kb
Host smart-a0ac02a4-06dd-4797-bb7a-4e4525bd7aa5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1371569267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1371569267
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.833228805
Short name T77
Test name
Test status
Simulation time 336789790000 ps
CPU time 977.25 seconds
Started Jun 29 06:13:51 PM PDT 24
Finished Jun 29 06:53:38 PM PDT 24
Peak memory 160812 kb
Host smart-49b2bae3-cc94-465f-8c81-e50084652cfe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=833228805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.833228805
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2116630374
Short name T105
Test name
Test status
Simulation time 336821170000 ps
CPU time 898.45 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:50:07 PM PDT 24
Peak memory 160808 kb
Host smart-6a9bb32a-5d6f-4720-b42a-f47d4c8adce4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2116630374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2116630374
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2118289102
Short name T95
Test name
Test status
Simulation time 336439250000 ps
CPU time 828.77 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:47:33 PM PDT 24
Peak memory 160816 kb
Host smart-1c800ef3-6fa7-454b-a5cc-cf4e954a76b1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2118289102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2118289102
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3545641911
Short name T81
Test name
Test status
Simulation time 336464950000 ps
CPU time 872.5 seconds
Started Jun 29 06:13:53 PM PDT 24
Finished Jun 29 06:49:31 PM PDT 24
Peak memory 160816 kb
Host smart-4aafe7bf-9910-4377-b5dc-7b42cda0d82f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3545641911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3545641911
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3107838533
Short name T14
Test name
Test status
Simulation time 336765930000 ps
CPU time 808.96 seconds
Started Jun 29 06:13:51 PM PDT 24
Finished Jun 29 06:46:42 PM PDT 24
Peak memory 160816 kb
Host smart-a68eb8f2-49bb-46b3-b1b9-142c65d5a55d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3107838533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3107838533
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1538941772
Short name T17
Test name
Test status
Simulation time 336784990000 ps
CPU time 849.12 seconds
Started Jun 29 06:13:55 PM PDT 24
Finished Jun 29 06:48:22 PM PDT 24
Peak memory 160772 kb
Host smart-8f36a0e4-0932-42b4-ae17-9f25fd23d73e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1538941772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.1538941772
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1384780740
Short name T109
Test name
Test status
Simulation time 336708130000 ps
CPU time 902.57 seconds
Started Jun 29 06:13:56 PM PDT 24
Finished Jun 29 06:51:19 PM PDT 24
Peak memory 160816 kb
Host smart-80aa4e69-3ea5-4575-acba-7b320f07738a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1384780740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1384780740
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.285389402
Short name T101
Test name
Test status
Simulation time 336873790000 ps
CPU time 887.07 seconds
Started Jun 29 06:13:54 PM PDT 24
Finished Jun 29 06:50:16 PM PDT 24
Peak memory 160812 kb
Host smart-43b2de69-a376-4748-88f4-2f6e28c7f784
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=285389402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.285389402
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3028043470
Short name T92
Test name
Test status
Simulation time 336958010000 ps
CPU time 812.49 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:47:31 PM PDT 24
Peak memory 160820 kb
Host smart-a1abe1cf-8f8d-480c-babd-c16de1ecb27f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3028043470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3028043470
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.955653273
Short name T74
Test name
Test status
Simulation time 336914650000 ps
CPU time 723.3 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:43:29 PM PDT 24
Peak memory 160800 kb
Host smart-8c625d21-6668-4171-a839-2c829d079a58
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=955653273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.955653273
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.612789173
Short name T107
Test name
Test status
Simulation time 336996270000 ps
CPU time 753.56 seconds
Started Jun 29 06:14:01 PM PDT 24
Finished Jun 29 06:44:33 PM PDT 24
Peak memory 160808 kb
Host smart-19876a39-b2fd-4145-b33e-7331e84bc4d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=612789173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.612789173
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3652604126
Short name T82
Test name
Test status
Simulation time 336715210000 ps
CPU time 872.9 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:49:09 PM PDT 24
Peak memory 160844 kb
Host smart-2dee1f59-0436-437d-8df1-6d57fa9ddf98
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652604126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3652604126
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2621889964
Short name T71
Test name
Test status
Simulation time 336558830000 ps
CPU time 936.08 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:52:06 PM PDT 24
Peak memory 160816 kb
Host smart-53858e38-ee61-412d-ac09-4349f8816b0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2621889964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2621889964
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1885064493
Short name T90
Test name
Test status
Simulation time 336835590000 ps
CPU time 856.56 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:48:26 PM PDT 24
Peak memory 160804 kb
Host smart-4259fb5e-7083-465b-beaf-5ef328cebeab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1885064493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1885064493
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1686041617
Short name T18
Test name
Test status
Simulation time 336761650000 ps
CPU time 1023.59 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:56:25 PM PDT 24
Peak memory 160808 kb
Host smart-2f0ff0e5-fa84-4407-9aa7-eaaff5b06c50
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1686041617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.1686041617
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.4051059479
Short name T5
Test name
Test status
Simulation time 336470410000 ps
CPU time 1004.43 seconds
Started Jun 29 06:14:07 PM PDT 24
Finished Jun 29 06:55:53 PM PDT 24
Peak memory 160816 kb
Host smart-a9c35abb-b4f2-4442-9f06-acd078546da4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4051059479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.4051059479
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3709131353
Short name T100
Test name
Test status
Simulation time 336360790000 ps
CPU time 902.66 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:50:40 PM PDT 24
Peak memory 160792 kb
Host smart-22744ef6-d6ba-4cbb-9e72-0a7daa9008a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3709131353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3709131353
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3227843271
Short name T73
Test name
Test status
Simulation time 336338730000 ps
CPU time 751.32 seconds
Started Jun 29 06:14:01 PM PDT 24
Finished Jun 29 06:44:40 PM PDT 24
Peak memory 160816 kb
Host smart-2ab03394-8929-4b5d-9196-f9ba6a424581
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3227843271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3227843271
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.2063383703
Short name T91
Test name
Test status
Simulation time 337102490000 ps
CPU time 755.45 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:44:52 PM PDT 24
Peak memory 160816 kb
Host smart-e9a4a1a0-9731-4687-b2c0-590abd35b301
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2063383703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.2063383703
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1801020090
Short name T78
Test name
Test status
Simulation time 336684670000 ps
CPU time 780.68 seconds
Started Jun 29 06:14:01 PM PDT 24
Finished Jun 29 06:45:43 PM PDT 24
Peak memory 160816 kb
Host smart-f1607949-f1ff-4b43-90e3-ed8158672fd8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1801020090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1801020090
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.4279262997
Short name T106
Test name
Test status
Simulation time 336478930000 ps
CPU time 895.61 seconds
Started Jun 29 06:14:06 PM PDT 24
Finished Jun 29 06:50:22 PM PDT 24
Peak memory 160792 kb
Host smart-e3e45922-aee9-406b-a5a5-4ca5e9731731
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4279262997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.4279262997
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2785474080
Short name T4
Test name
Test status
Simulation time 336830270000 ps
CPU time 721.9 seconds
Started Jun 29 06:14:05 PM PDT 24
Finished Jun 29 06:44:08 PM PDT 24
Peak memory 160740 kb
Host smart-45c7e948-3773-4af8-99c3-861c2229dcc4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2785474080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2785474080
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2630293806
Short name T85
Test name
Test status
Simulation time 336459110000 ps
CPU time 883.3 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:49:57 PM PDT 24
Peak memory 160816 kb
Host smart-7a795c61-22c5-4ce7-8e8c-64a12c8a3c47
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2630293806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2630293806
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.873696570
Short name T87
Test name
Test status
Simulation time 336815090000 ps
CPU time 1003.3 seconds
Started Jun 29 06:14:07 PM PDT 24
Finished Jun 29 06:56:19 PM PDT 24
Peak memory 160812 kb
Host smart-2ac21025-388c-45de-b074-98bf17547eae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=873696570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.873696570
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3772762312
Short name T79
Test name
Test status
Simulation time 336706590000 ps
CPU time 889.2 seconds
Started Jun 29 06:14:01 PM PDT 24
Finished Jun 29 06:50:12 PM PDT 24
Peak memory 160816 kb
Host smart-c915aee2-27f8-4c83-ad68-d5172f4d2cde
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3772762312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3772762312
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1669725522
Short name T75
Test name
Test status
Simulation time 336429150000 ps
CPU time 1010.74 seconds
Started Jun 29 06:13:52 PM PDT 24
Finished Jun 29 06:56:23 PM PDT 24
Peak memory 160808 kb
Host smart-12c8624b-0e73-4457-a6f2-3fe8d1a93927
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1669725522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1669725522
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.921110061
Short name T98
Test name
Test status
Simulation time 336773970000 ps
CPU time 780.9 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:45:24 PM PDT 24
Peak memory 160816 kb
Host smart-b4522cbe-1fd2-437b-8841-11d5b8ae976f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=921110061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.921110061
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2157920472
Short name T97
Test name
Test status
Simulation time 336741910000 ps
CPU time 828.12 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:47:46 PM PDT 24
Peak memory 160816 kb
Host smart-e004c200-3581-4180-81ee-acb3ab642628
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2157920472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2157920472
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2877365874
Short name T86
Test name
Test status
Simulation time 336386050000 ps
CPU time 763.28 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:44:45 PM PDT 24
Peak memory 160816 kb
Host smart-f454f8e3-df6c-4a95-878d-de87c06a4fd5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2877365874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2877365874
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3053423589
Short name T16
Test name
Test status
Simulation time 336843230000 ps
CPU time 781.99 seconds
Started Jun 29 06:14:05 PM PDT 24
Finished Jun 29 06:46:04 PM PDT 24
Peak memory 160816 kb
Host smart-9b98ffde-e296-448f-804d-bfcb6d818a44
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3053423589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3053423589
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.822624535
Short name T96
Test name
Test status
Simulation time 337022490000 ps
CPU time 831.09 seconds
Started Jun 29 06:14:07 PM PDT 24
Finished Jun 29 06:47:53 PM PDT 24
Peak memory 160812 kb
Host smart-4ddd209b-07aa-4dc6-aa2d-1473b40dae8b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=822624535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.822624535
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3833740742
Short name T83
Test name
Test status
Simulation time 336845770000 ps
CPU time 875.6 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:49:43 PM PDT 24
Peak memory 160820 kb
Host smart-331736a0-4ec9-4cf9-af7e-e82bf99c9594
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3833740742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3833740742
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3385166687
Short name T108
Test name
Test status
Simulation time 336988910000 ps
CPU time 804.67 seconds
Started Jun 29 06:14:05 PM PDT 24
Finished Jun 29 06:46:49 PM PDT 24
Peak memory 160804 kb
Host smart-b92862c5-262d-451f-ba50-f30d4f6fde18
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3385166687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3385166687
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3228188681
Short name T88
Test name
Test status
Simulation time 336448470000 ps
CPU time 764.8 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:44:46 PM PDT 24
Peak memory 160828 kb
Host smart-c1f152cb-8733-474d-a0b2-b628f9b846bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3228188681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3228188681
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.2445862633
Short name T80
Test name
Test status
Simulation time 337032690000 ps
CPU time 808.66 seconds
Started Jun 29 06:14:01 PM PDT 24
Finished Jun 29 06:46:52 PM PDT 24
Peak memory 160816 kb
Host smart-0087818b-8a8e-4e79-b9c4-1f93dd2002e4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2445862633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.2445862633
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3016368129
Short name T76
Test name
Test status
Simulation time 336879570000 ps
CPU time 999.84 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:55:44 PM PDT 24
Peak memory 160832 kb
Host smart-261fa7fd-ee3f-4c96-a9cc-8d36a41c6c7b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3016368129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3016368129
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1932419753
Short name T19
Test name
Test status
Simulation time 336559850000 ps
CPU time 836.1 seconds
Started Jun 29 06:13:56 PM PDT 24
Finished Jun 29 06:48:02 PM PDT 24
Peak memory 160728 kb
Host smart-c95d79bd-35a6-4176-86ff-b6555cc8b0d9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1932419753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1932419753
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.2325294113
Short name T104
Test name
Test status
Simulation time 336994830000 ps
CPU time 868.99 seconds
Started Jun 29 06:13:51 PM PDT 24
Finished Jun 29 06:49:22 PM PDT 24
Peak memory 160808 kb
Host smart-678d9524-2410-4d71-836a-113fab66760b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2325294113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.2325294113
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3509880995
Short name T15
Test name
Test status
Simulation time 336883370000 ps
CPU time 1007.66 seconds
Started Jun 29 06:13:54 PM PDT 24
Finished Jun 29 06:55:51 PM PDT 24
Peak memory 160824 kb
Host smart-abd0a3ed-b0ee-42a2-b52b-ce027fab3b9e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3509880995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3509880995
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1228740903
Short name T72
Test name
Test status
Simulation time 336555350000 ps
CPU time 833.66 seconds
Started Jun 29 06:13:53 PM PDT 24
Finished Jun 29 06:47:47 PM PDT 24
Peak memory 160808 kb
Host smart-11a31352-8a9b-496c-8449-5fa7461b366c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1228740903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1228740903
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3421518845
Short name T20
Test name
Test status
Simulation time 336649750000 ps
CPU time 880.94 seconds
Started Jun 29 06:13:53 PM PDT 24
Finished Jun 29 06:49:27 PM PDT 24
Peak memory 160808 kb
Host smart-5c30d705-1c8c-4ad1-ab7d-ac1192d5e8de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3421518845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3421518845
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1812217116
Short name T187
Test name
Test status
Simulation time 336698890000 ps
CPU time 1102.55 seconds
Started Jun 29 05:13:56 PM PDT 24
Finished Jun 29 05:59:55 PM PDT 24
Peak memory 160808 kb
Host smart-9c3c92da-8bd8-4d58-961c-64dbbd0d93b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1812217116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1812217116
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.155784572
Short name T191
Test name
Test status
Simulation time 336566690000 ps
CPU time 1023.83 seconds
Started Jun 29 05:13:57 PM PDT 24
Finished Jun 29 05:56:22 PM PDT 24
Peak memory 160808 kb
Host smart-27be2020-61a8-4754-bb31-950009de21c4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=155784572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.155784572
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2851960477
Short name T194
Test name
Test status
Simulation time 336578930000 ps
CPU time 890.59 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:50:10 PM PDT 24
Peak memory 160736 kb
Host smart-f9a254e9-8cf0-430a-8504-d4abc3892e1c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2851960477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2851960477
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2587697762
Short name T183
Test name
Test status
Simulation time 336624310000 ps
CPU time 1043.34 seconds
Started Jun 29 05:14:07 PM PDT 24
Finished Jun 29 05:57:00 PM PDT 24
Peak memory 160816 kb
Host smart-9aec123e-f124-4849-94d2-81b9526382da
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2587697762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2587697762
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.2241695049
Short name T173
Test name
Test status
Simulation time 336861850000 ps
CPU time 826.79 seconds
Started Jun 29 05:14:03 PM PDT 24
Finished Jun 29 05:47:37 PM PDT 24
Peak memory 160736 kb
Host smart-7ce29538-b6e5-4581-8f34-87998d41e4a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2241695049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.2241695049
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1928952916
Short name T22
Test name
Test status
Simulation time 336972490000 ps
CPU time 842.99 seconds
Started Jun 29 05:14:02 PM PDT 24
Finished Jun 29 05:48:07 PM PDT 24
Peak memory 160740 kb
Host smart-3785a5f2-0f6a-49a3-b8f9-b44c6e1891e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1928952916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1928952916
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2982743783
Short name T161
Test name
Test status
Simulation time 337009170000 ps
CPU time 721.43 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:43:15 PM PDT 24
Peak memory 160812 kb
Host smart-9d92e4ff-631d-4775-a8f1-5fade48d85e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2982743783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.2982743783
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3353779729
Short name T170
Test name
Test status
Simulation time 336911590000 ps
CPU time 829.77 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:47:35 PM PDT 24
Peak memory 160796 kb
Host smart-9e978ba3-0ec3-4363-9bce-aad19dc63dfe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3353779729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.3353779729
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.53354995
Short name T189
Test name
Test status
Simulation time 336665130000 ps
CPU time 913.09 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:51:00 PM PDT 24
Peak memory 160812 kb
Host smart-63b5825f-f45f-49d8-ba95-37d718d17b21
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=53354995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.53354995
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.44134666
Short name T200
Test name
Test status
Simulation time 336750610000 ps
CPU time 900.78 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:50:13 PM PDT 24
Peak memory 160808 kb
Host smart-cb45809e-b7d6-4309-a870-db8ca41e26de
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=44134666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.44134666
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1981042801
Short name T182
Test name
Test status
Simulation time 336615130000 ps
CPU time 852.75 seconds
Started Jun 29 05:14:02 PM PDT 24
Finished Jun 29 05:48:38 PM PDT 24
Peak memory 160816 kb
Host smart-bb95cad8-87fa-4c73-9a1a-9f755e62e4d6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1981042801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1981042801
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4006712668
Short name T28
Test name
Test status
Simulation time 336530910000 ps
CPU time 821 seconds
Started Jun 29 05:13:58 PM PDT 24
Finished Jun 29 05:47:42 PM PDT 24
Peak memory 160812 kb
Host smart-fdd91684-4bf0-4933-9c7c-f7173759c353
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4006712668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.4006712668
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.429892105
Short name T174
Test name
Test status
Simulation time 336485530000 ps
CPU time 872.93 seconds
Started Jun 29 05:14:06 PM PDT 24
Finished Jun 29 05:49:46 PM PDT 24
Peak memory 160904 kb
Host smart-748bfeb2-751e-490e-a5f2-398688fa59b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=429892105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.429892105
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3258336900
Short name T166
Test name
Test status
Simulation time 336950290000 ps
CPU time 897.59 seconds
Started Jun 29 05:14:02 PM PDT 24
Finished Jun 29 05:49:48 PM PDT 24
Peak memory 160800 kb
Host smart-2ebd8360-663c-44c5-8a01-d0dc517b8e56
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3258336900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3258336900
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2453182774
Short name T168
Test name
Test status
Simulation time 336314290000 ps
CPU time 866.68 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:49:22 PM PDT 24
Peak memory 160828 kb
Host smart-b314a325-3cbb-4fe4-8c7c-9c7800a0c117
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2453182774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2453182774
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.941814105
Short name T162
Test name
Test status
Simulation time 336432550000 ps
CPU time 863.71 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:48:55 PM PDT 24
Peak memory 160812 kb
Host smart-ed39bd9b-5eb2-4b75-8ff9-94378d30aa23
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=941814105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.941814105
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2636821891
Short name T196
Test name
Test status
Simulation time 336449650000 ps
CPU time 917.63 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:50:47 PM PDT 24
Peak memory 160816 kb
Host smart-9d3dda43-bb37-44e4-bcb3-a8c412ef8c02
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2636821891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2636821891
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4187507698
Short name T185
Test name
Test status
Simulation time 336516730000 ps
CPU time 683.3 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:42:20 PM PDT 24
Peak memory 160800 kb
Host smart-35cebb57-acf7-4f6b-84df-1fb67d7b74fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4187507698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.4187507698
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2895483264
Short name T26
Test name
Test status
Simulation time 337038690000 ps
CPU time 896.34 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:50:24 PM PDT 24
Peak memory 160828 kb
Host smart-71f115c0-1ba3-4124-bf38-4223cfe7925a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2895483264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2895483264
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.3097406354
Short name T181
Test name
Test status
Simulation time 336425550000 ps
CPU time 948.63 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:51:46 PM PDT 24
Peak memory 160720 kb
Host smart-09cc2e71-dcd3-4fae-be5d-7ea283d3a2bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3097406354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.3097406354
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2818209672
Short name T24
Test name
Test status
Simulation time 336426570000 ps
CPU time 953.97 seconds
Started Jun 29 05:14:06 PM PDT 24
Finished Jun 29 05:52:53 PM PDT 24
Peak memory 160816 kb
Host smart-c1b78f94-2f27-4473-8f4c-05082bfbb41c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2818209672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.2818209672
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2562971983
Short name T172
Test name
Test status
Simulation time 336851830000 ps
CPU time 857.9 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:48:43 PM PDT 24
Peak memory 160816 kb
Host smart-61ea820b-dd79-4f12-a22e-01057dfcac61
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2562971983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2562971983
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.2908271879
Short name T178
Test name
Test status
Simulation time 337044090000 ps
CPU time 1097.73 seconds
Started Jun 29 05:13:56 PM PDT 24
Finished Jun 29 05:59:53 PM PDT 24
Peak memory 160808 kb
Host smart-34d60173-d150-4a3c-99b7-8068689bdd87
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2908271879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.2908271879
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1881218880
Short name T23
Test name
Test status
Simulation time 336974450000 ps
CPU time 806.57 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:47:12 PM PDT 24
Peak memory 160724 kb
Host smart-ae4de57f-5d7e-44cb-ae2e-bcc369bc7ccb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1881218880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1881218880
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2147421896
Short name T198
Test name
Test status
Simulation time 336823750000 ps
CPU time 941.35 seconds
Started Jun 29 05:14:07 PM PDT 24
Finished Jun 29 05:52:39 PM PDT 24
Peak memory 160816 kb
Host smart-e3b6a241-ed4b-4795-95e1-1849ee9f7ba3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2147421896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2147421896
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2230634456
Short name T165
Test name
Test status
Simulation time 336788490000 ps
CPU time 815.05 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:46:54 PM PDT 24
Peak memory 160744 kb
Host smart-f8765a2a-36a5-4bc7-b79a-3dbd4fb0d29c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2230634456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2230634456
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2737931914
Short name T177
Test name
Test status
Simulation time 336580850000 ps
CPU time 877.14 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 160828 kb
Host smart-b639f223-f881-4833-86f4-226ef51fd2d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2737931914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2737931914
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3683377112
Short name T179
Test name
Test status
Simulation time 336498010000 ps
CPU time 1093.89 seconds
Started Jun 29 05:14:05 PM PDT 24
Finished Jun 29 05:59:48 PM PDT 24
Peak memory 160816 kb
Host smart-5aa95dc0-0a50-4b5c-a164-f30c29f251a2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3683377112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3683377112
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2422325823
Short name T30
Test name
Test status
Simulation time 336959110000 ps
CPU time 868.56 seconds
Started Jun 29 05:14:03 PM PDT 24
Finished Jun 29 05:49:02 PM PDT 24
Peak memory 160816 kb
Host smart-e7757922-ba2e-4f6a-8a56-f8604af83446
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2422325823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2422325823
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1206922640
Short name T180
Test name
Test status
Simulation time 336599810000 ps
CPU time 924.27 seconds
Started Jun 29 05:14:07 PM PDT 24
Finished Jun 29 05:52:16 PM PDT 24
Peak memory 160816 kb
Host smart-e579279a-7985-472a-a09c-1e69af0fe3b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1206922640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1206922640
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.914241533
Short name T169
Test name
Test status
Simulation time 336936170000 ps
CPU time 1002 seconds
Started Jun 29 05:14:09 PM PDT 24
Finished Jun 29 05:55:58 PM PDT 24
Peak memory 160812 kb
Host smart-d9407ed6-d278-4b63-95ef-acc25a52850e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=914241533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.914241533
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2006427211
Short name T184
Test name
Test status
Simulation time 336460770000 ps
CPU time 892.21 seconds
Started Jun 29 05:14:02 PM PDT 24
Finished Jun 29 05:49:29 PM PDT 24
Peak memory 160816 kb
Host smart-b1d6a4ec-0897-45e5-a09a-28c795c7cd5e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2006427211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2006427211
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2325204767
Short name T192
Test name
Test status
Simulation time 336749790000 ps
CPU time 772.01 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:45:32 PM PDT 24
Peak memory 160744 kb
Host smart-090c7cd9-df33-43f4-9ea2-55a2cadc9f88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2325204767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2325204767
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2309893509
Short name T164
Test name
Test status
Simulation time 337074890000 ps
CPU time 1040.81 seconds
Started Jun 29 05:13:57 PM PDT 24
Finished Jun 29 05:56:46 PM PDT 24
Peak memory 160808 kb
Host smart-e967531c-9a98-4fd6-b808-f9f726e752d0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2309893509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2309893509
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3793987529
Short name T167
Test name
Test status
Simulation time 336856970000 ps
CPU time 940.51 seconds
Started Jun 29 05:14:06 PM PDT 24
Finished Jun 29 05:52:03 PM PDT 24
Peak memory 160816 kb
Host smart-d05d734e-7f5c-46bf-86fe-1a07b6283949
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3793987529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3793987529
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2009977114
Short name T25
Test name
Test status
Simulation time 336387090000 ps
CPU time 853.74 seconds
Started Jun 29 05:14:06 PM PDT 24
Finished Jun 29 05:48:50 PM PDT 24
Peak memory 160808 kb
Host smart-0eef69ff-8a9c-40bf-a12d-8e13c2279ebf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2009977114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2009977114
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.1491798427
Short name T193
Test name
Test status
Simulation time 336704370000 ps
CPU time 712.55 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:43:33 PM PDT 24
Peak memory 160816 kb
Host smart-ee2892ac-b7ef-4eef-9a94-d1679c3a276b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1491798427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.1491798427
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.2654323963
Short name T186
Test name
Test status
Simulation time 336597850000 ps
CPU time 770.87 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:45:22 PM PDT 24
Peak memory 160828 kb
Host smart-90e474d2-fb83-49f3-a67b-e1a53bb2089d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2654323963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.2654323963
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.2960244414
Short name T195
Test name
Test status
Simulation time 337064390000 ps
CPU time 856.8 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:49:10 PM PDT 24
Peak memory 160740 kb
Host smart-d4a29917-5df6-4c62-8798-0fe42b170964
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2960244414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.2960244414
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3580954646
Short name T190
Test name
Test status
Simulation time 337103270000 ps
CPU time 940.54 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:52:54 PM PDT 24
Peak memory 160816 kb
Host smart-1121c105-3334-4da7-b333-2f3156df8f63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3580954646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3580954646
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1841274311
Short name T27
Test name
Test status
Simulation time 337133750000 ps
CPU time 850.21 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:48:50 PM PDT 24
Peak memory 160736 kb
Host smart-7942d8a0-501c-478e-99f3-50d078422222
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1841274311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1841274311
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4017078490
Short name T163
Test name
Test status
Simulation time 336918610000 ps
CPU time 891.52 seconds
Started Jun 29 05:14:12 PM PDT 24
Finished Jun 29 05:50:39 PM PDT 24
Peak memory 160808 kb
Host smart-827c8522-e880-4cb7-bfe5-873748af8a8f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4017078490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4017078490
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.330642942
Short name T188
Test name
Test status
Simulation time 336604550000 ps
CPU time 903.55 seconds
Started Jun 29 05:14:17 PM PDT 24
Finished Jun 29 05:50:46 PM PDT 24
Peak memory 160812 kb
Host smart-f2decd1a-6af0-46f7-bdfc-a05440a5564b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=330642942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.330642942
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3544344144
Short name T171
Test name
Test status
Simulation time 336796010000 ps
CPU time 908.21 seconds
Started Jun 29 05:14:13 PM PDT 24
Finished Jun 29 05:51:29 PM PDT 24
Peak memory 160816 kb
Host smart-f2368d04-fa36-4224-b457-b9b11ac39388
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3544344144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3544344144
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1671179933
Short name T21
Test name
Test status
Simulation time 336529070000 ps
CPU time 886.42 seconds
Started Jun 29 05:13:54 PM PDT 24
Finished Jun 29 05:50:00 PM PDT 24
Peak memory 160800 kb
Host smart-d2a91597-586b-4620-9968-f2c6515ced02
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1671179933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1671179933
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1517462283
Short name T197
Test name
Test status
Simulation time 336292730000 ps
CPU time 848.65 seconds
Started Jun 29 05:13:58 PM PDT 24
Finished Jun 29 05:48:28 PM PDT 24
Peak memory 160812 kb
Host smart-2989b09e-7d1c-4da8-8433-305de0df5c69
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1517462283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1517462283
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3545296347
Short name T175
Test name
Test status
Simulation time 336748090000 ps
CPU time 1023.84 seconds
Started Jun 29 05:13:57 PM PDT 24
Finished Jun 29 05:56:28 PM PDT 24
Peak memory 160808 kb
Host smart-2646f7c5-6816-44ed-bb35-ac6612c10ccf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3545296347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3545296347
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3607720308
Short name T176
Test name
Test status
Simulation time 337035490000 ps
CPU time 874.03 seconds
Started Jun 29 05:14:04 PM PDT 24
Finished Jun 29 05:49:11 PM PDT 24
Peak memory 160808 kb
Host smart-df940ea4-7b9c-4a0b-b431-5cb10c6e8862
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3607720308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3607720308
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1030634523
Short name T199
Test name
Test status
Simulation time 336744410000 ps
CPU time 775.56 seconds
Started Jun 29 05:14:03 PM PDT 24
Finished Jun 29 05:46:05 PM PDT 24
Peak memory 160808 kb
Host smart-d6aa482e-ec25-4e4b-9922-3878eee2a4c9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1030634523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1030634523
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1816448568
Short name T119
Test name
Test status
Simulation time 1431810000 ps
CPU time 5.36 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:18 PM PDT 24
Peak memory 164336 kb
Host smart-aefc668c-b2e4-4355-9060-21977a7d3ff9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1816448568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1816448568
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1332863089
Short name T152
Test name
Test status
Simulation time 1554010000 ps
CPU time 5.96 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:18 PM PDT 24
Peak memory 164948 kb
Host smart-b33fd9c3-af2a-4fef-93d5-7ac27864f2d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332863089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1332863089
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4114461634
Short name T155
Test name
Test status
Simulation time 1399270000 ps
CPU time 5.01 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:16 PM PDT 24
Peak memory 164892 kb
Host smart-cb4fd209-ae3d-4d3c-8111-a6857e7665c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4114461634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4114461634
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.103283281
Short name T133
Test name
Test status
Simulation time 1308350000 ps
CPU time 4.85 seconds
Started Jun 29 06:14:07 PM PDT 24
Finished Jun 29 06:14:18 PM PDT 24
Peak memory 164952 kb
Host smart-3d39ef6f-583b-44d3-8fc5-88e4e8af78cd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103283281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.103283281
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.229026267
Short name T126
Test name
Test status
Simulation time 1537830000 ps
CPU time 3.59 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:13 PM PDT 24
Peak memory 164952 kb
Host smart-7ac6b174-9f6e-49c8-b222-561607f8c0b3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=229026267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.229026267
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3633233554
Short name T127
Test name
Test status
Simulation time 1531390000 ps
CPU time 5.13 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:14:15 PM PDT 24
Peak memory 164904 kb
Host smart-4bbe4534-bf50-4564-a719-501cf431d14c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3633233554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3633233554
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.141287142
Short name T131
Test name
Test status
Simulation time 1403830000 ps
CPU time 5.02 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:16 PM PDT 24
Peak memory 164900 kb
Host smart-f5544336-7801-421c-9b65-e49dcbc4adb9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=141287142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.141287142
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.667509411
Short name T117
Test name
Test status
Simulation time 1509430000 ps
CPU time 5.55 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:17 PM PDT 24
Peak memory 164932 kb
Host smart-6d56e5a7-7f27-4a7c-9116-83635d0f1990
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=667509411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.667509411
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3926528683
Short name T118
Test name
Test status
Simulation time 1447090000 ps
CPU time 4.52 seconds
Started Jun 29 06:14:05 PM PDT 24
Finished Jun 29 06:14:17 PM PDT 24
Peak memory 164904 kb
Host smart-835022ff-dc24-4abc-bf64-e58753832bfc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3926528683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3926528683
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1548631406
Short name T114
Test name
Test status
Simulation time 1414830000 ps
CPU time 5.36 seconds
Started Jun 29 06:14:07 PM PDT 24
Finished Jun 29 06:14:19 PM PDT 24
Peak memory 164944 kb
Host smart-94b41ffb-39f6-482c-b562-c553118e74ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1548631406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1548631406
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2904777506
Short name T137
Test name
Test status
Simulation time 1609890000 ps
CPU time 4.73 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:17 PM PDT 24
Peak memory 164904 kb
Host smart-cb8e06d5-1086-4715-a50a-52ca9e274cc5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2904777506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.2904777506
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1587185914
Short name T146
Test name
Test status
Simulation time 1379470000 ps
CPU time 5.28 seconds
Started Jun 29 06:14:07 PM PDT 24
Finished Jun 29 06:14:19 PM PDT 24
Peak memory 164944 kb
Host smart-de522fbf-bdda-4007-874f-8cf1cd71d097
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1587185914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1587185914
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.321665313
Short name T122
Test name
Test status
Simulation time 1240270000 ps
CPU time 4.83 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:17 PM PDT 24
Peak memory 164296 kb
Host smart-46b5db97-0f97-4eb5-9330-054b025a3d59
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=321665313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.321665313
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2315434011
Short name T154
Test name
Test status
Simulation time 1119190000 ps
CPU time 4.58 seconds
Started Jun 29 06:14:06 PM PDT 24
Finished Jun 29 06:14:16 PM PDT 24
Peak memory 164944 kb
Host smart-3f5d41d5-ecb2-4407-8502-85fd588d2765
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2315434011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2315434011
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.3177523248
Short name T158
Test name
Test status
Simulation time 1332190000 ps
CPU time 4.51 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:15 PM PDT 24
Peak memory 164944 kb
Host smart-302144f8-1b41-4f25-8790-a3050b8dcd65
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3177523248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.3177523248
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.502395393
Short name T136
Test name
Test status
Simulation time 1269330000 ps
CPU time 5.12 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:14:15 PM PDT 24
Peak memory 164952 kb
Host smart-4149bc14-61bb-45e9-8821-ba9c806ce7af
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=502395393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.502395393
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2905892838
Short name T135
Test name
Test status
Simulation time 1403270000 ps
CPU time 4.79 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:15 PM PDT 24
Peak memory 164940 kb
Host smart-d8974e0d-b79f-4397-8ae2-3eb068c26ef8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2905892838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2905892838
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4076310890
Short name T134
Test name
Test status
Simulation time 1638870000 ps
CPU time 6.04 seconds
Started Jun 29 06:14:13 PM PDT 24
Finished Jun 29 06:14:27 PM PDT 24
Peak memory 164944 kb
Host smart-cd3c21a2-04ec-4788-b4fc-82fb07c55ae8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4076310890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.4076310890
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3248639132
Short name T151
Test name
Test status
Simulation time 1482130000 ps
CPU time 5 seconds
Started Jun 29 06:14:13 PM PDT 24
Finished Jun 29 06:14:26 PM PDT 24
Peak memory 164952 kb
Host smart-2904be9b-4296-495e-ad0b-252087e25998
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3248639132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3248639132
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.55646522
Short name T113
Test name
Test status
Simulation time 1327530000 ps
CPU time 4.78 seconds
Started Jun 29 06:14:13 PM PDT 24
Finished Jun 29 06:14:24 PM PDT 24
Peak memory 164836 kb
Host smart-636eaf9b-de34-4e72-b2c9-29f2c39f1355
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=55646522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.55646522
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1607078342
Short name T125
Test name
Test status
Simulation time 1506650000 ps
CPU time 4.77 seconds
Started Jun 29 06:14:12 PM PDT 24
Finished Jun 29 06:14:23 PM PDT 24
Peak memory 164944 kb
Host smart-98543df3-864f-4c74-876b-e32f7a53b5f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1607078342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1607078342
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1947532698
Short name T156
Test name
Test status
Simulation time 1305690000 ps
CPU time 4.25 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:26 PM PDT 24
Peak memory 164944 kb
Host smart-82f5a1d5-ee68-498b-9c11-4e287ab206f2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947532698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1947532698
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1054553567
Short name T121
Test name
Test status
Simulation time 1504770000 ps
CPU time 4.14 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:25 PM PDT 24
Peak memory 164916 kb
Host smart-0bb675ab-78de-4c82-a8f1-544d03ccfdb7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1054553567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1054553567
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.1577724079
Short name T138
Test name
Test status
Simulation time 1402530000 ps
CPU time 4 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:14 PM PDT 24
Peak memory 164872 kb
Host smart-4a128357-4713-4c8b-bddd-8556b9c77a3c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577724079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.1577724079
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.186127783
Short name T111
Test name
Test status
Simulation time 1533710000 ps
CPU time 4.63 seconds
Started Jun 29 06:14:14 PM PDT 24
Finished Jun 29 06:14:24 PM PDT 24
Peak memory 164912 kb
Host smart-6e4f740f-2264-458e-b466-be73d3442793
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=186127783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.186127783
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.395638321
Short name T115
Test name
Test status
Simulation time 1539210000 ps
CPU time 5.99 seconds
Started Jun 29 06:14:14 PM PDT 24
Finished Jun 29 06:14:28 PM PDT 24
Peak memory 165036 kb
Host smart-e1b5b840-b79f-4cb5-b2a6-75c76b6c8bf4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=395638321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.395638321
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.429719448
Short name T143
Test name
Test status
Simulation time 1429230000 ps
CPU time 3.26 seconds
Started Jun 29 06:14:12 PM PDT 24
Finished Jun 29 06:14:19 PM PDT 24
Peak memory 164932 kb
Host smart-cf235961-8265-40e4-ace6-ff9a08cd716e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=429719448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.429719448
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2722238512
Short name T157
Test name
Test status
Simulation time 1440910000 ps
CPU time 4.3 seconds
Started Jun 29 06:14:12 PM PDT 24
Finished Jun 29 06:14:22 PM PDT 24
Peak memory 164944 kb
Host smart-33e68eb9-7e10-4c58-8952-b85d3b310cc3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722238512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2722238512
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3822458894
Short name T141
Test name
Test status
Simulation time 1477270000 ps
CPU time 4.98 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:27 PM PDT 24
Peak memory 164944 kb
Host smart-f4a38e93-866c-4ebb-b422-3942403bc346
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3822458894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3822458894
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.804532568
Short name T124
Test name
Test status
Simulation time 1285430000 ps
CPU time 4.77 seconds
Started Jun 29 06:14:11 PM PDT 24
Finished Jun 29 06:14:22 PM PDT 24
Peak memory 164912 kb
Host smart-c7f0bbcf-a363-4f75-8172-da9b4481817f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=804532568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.804532568
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1570603219
Short name T148
Test name
Test status
Simulation time 1324990000 ps
CPU time 4.62 seconds
Started Jun 29 06:14:10 PM PDT 24
Finished Jun 29 06:14:21 PM PDT 24
Peak memory 164928 kb
Host smart-e220100d-b96c-4eaa-b27f-9f384b6e65e3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1570603219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1570603219
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1397817852
Short name T116
Test name
Test status
Simulation time 1625670000 ps
CPU time 6.38 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:31 PM PDT 24
Peak memory 164940 kb
Host smart-2b243ec9-ce1c-484a-8c22-298506418ccc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1397817852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1397817852
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2798230710
Short name T132
Test name
Test status
Simulation time 1454170000 ps
CPU time 6.06 seconds
Started Jun 29 06:14:11 PM PDT 24
Finished Jun 29 06:14:25 PM PDT 24
Peak memory 164940 kb
Host smart-992c0cb6-f879-4a31-abd5-c516a988d881
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2798230710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2798230710
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.2487448307
Short name T120
Test name
Test status
Simulation time 1235270000 ps
CPU time 5.48 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:28 PM PDT 24
Peak memory 164940 kb
Host smart-db754743-3edc-4e52-880e-40a5b8176b8f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2487448307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.2487448307
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2758740793
Short name T159
Test name
Test status
Simulation time 1537570000 ps
CPU time 5.77 seconds
Started Jun 29 06:14:02 PM PDT 24
Finished Jun 29 06:14:15 PM PDT 24
Peak memory 164948 kb
Host smart-32f9905c-e534-48a9-9a08-0167c0c8c379
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2758740793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2758740793
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2200787674
Short name T112
Test name
Test status
Simulation time 1379810000 ps
CPU time 4.97 seconds
Started Jun 29 06:14:13 PM PDT 24
Finished Jun 29 06:14:26 PM PDT 24
Peak memory 164944 kb
Host smart-e05b3576-ba2e-417b-b82f-0ed837c4b441
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2200787674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2200787674
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.910036849
Short name T147
Test name
Test status
Simulation time 1389630000 ps
CPU time 6.69 seconds
Started Jun 29 06:14:11 PM PDT 24
Finished Jun 29 06:14:26 PM PDT 24
Peak memory 164964 kb
Host smart-9a021dd0-1c53-4af7-8985-420bb857e21b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=910036849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.910036849
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3710256848
Short name T142
Test name
Test status
Simulation time 1394210000 ps
CPU time 4.85 seconds
Started Jun 29 06:14:16 PM PDT 24
Finished Jun 29 06:14:28 PM PDT 24
Peak memory 164944 kb
Host smart-3f0470a0-ad66-461a-b201-719703c44473
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3710256848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3710256848
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3488128346
Short name T123
Test name
Test status
Simulation time 1502290000 ps
CPU time 5.09 seconds
Started Jun 29 06:14:13 PM PDT 24
Finished Jun 29 06:14:25 PM PDT 24
Peak memory 164952 kb
Host smart-6d40a2c7-3da4-4233-859e-73818cbd1d3d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3488128346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3488128346
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1733727338
Short name T128
Test name
Test status
Simulation time 1560210000 ps
CPU time 5.33 seconds
Started Jun 29 06:14:16 PM PDT 24
Finished Jun 29 06:14:29 PM PDT 24
Peak memory 164944 kb
Host smart-fc64dd8c-8efc-45c6-82bb-65e5a128a499
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1733727338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1733727338
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.642032424
Short name T160
Test name
Test status
Simulation time 1516090000 ps
CPU time 4.73 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:27 PM PDT 24
Peak memory 164952 kb
Host smart-9fa96f94-fc59-41a4-b97a-25b368a29530
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=642032424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.642032424
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.47649841
Short name T129
Test name
Test status
Simulation time 1140570000 ps
CPU time 3.19 seconds
Started Jun 29 06:14:16 PM PDT 24
Finished Jun 29 06:14:24 PM PDT 24
Peak memory 164864 kb
Host smart-0330c3e2-d943-40d0-af86-e10b584b0d39
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47649841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.47649841
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.4097675104
Short name T145
Test name
Test status
Simulation time 1499010000 ps
CPU time 4.02 seconds
Started Jun 29 06:14:11 PM PDT 24
Finished Jun 29 06:14:21 PM PDT 24
Peak memory 164944 kb
Host smart-40231c90-caec-4adb-8e4d-bbead268ec2e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4097675104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.4097675104
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3633618759
Short name T130
Test name
Test status
Simulation time 1516050000 ps
CPU time 5.12 seconds
Started Jun 29 06:14:16 PM PDT 24
Finished Jun 29 06:14:29 PM PDT 24
Peak memory 164944 kb
Host smart-41ac8325-14ff-4d02-8251-d9775642301e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3633618759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3633618759
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2895539172
Short name T153
Test name
Test status
Simulation time 1613510000 ps
CPU time 4.38 seconds
Started Jun 29 06:14:15 PM PDT 24
Finished Jun 29 06:14:26 PM PDT 24
Peak memory 164916 kb
Host smart-b9fa97df-bb9c-4906-9a05-6a08774f0276
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895539172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2895539172
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1101290026
Short name T140
Test name
Test status
Simulation time 1491350000 ps
CPU time 4.44 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:15 PM PDT 24
Peak memory 164948 kb
Host smart-695e431d-da98-42fc-8e42-d9acb3380767
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1101290026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1101290026
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2618916200
Short name T149
Test name
Test status
Simulation time 1282530000 ps
CPU time 4.23 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:14 PM PDT 24
Peak memory 164948 kb
Host smart-865fc382-1190-43f9-af01-2da820dc7fdb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2618916200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2618916200
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1139136374
Short name T144
Test name
Test status
Simulation time 1377070000 ps
CPU time 6.06 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:18 PM PDT 24
Peak memory 164920 kb
Host smart-0373fa21-3e2b-41fc-ab9f-94f404813280
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1139136374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1139136374
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1845848297
Short name T150
Test name
Test status
Simulation time 1425370000 ps
CPU time 4.48 seconds
Started Jun 29 06:14:04 PM PDT 24
Finished Jun 29 06:14:16 PM PDT 24
Peak memory 164836 kb
Host smart-b01bd277-f64b-4f08-a414-9ee2166071ba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1845848297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1845848297
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2089491507
Short name T139
Test name
Test status
Simulation time 1402410000 ps
CPU time 5.62 seconds
Started Jun 29 06:14:03 PM PDT 24
Finished Jun 29 06:14:18 PM PDT 24
Peak memory 164920 kb
Host smart-3f5f5995-6391-46bf-a2df-bf230bdbd6f0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089491507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2089491507
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3968041734
Short name T58
Test name
Test status
Simulation time 1318850000 ps
CPU time 4.24 seconds
Started Jun 29 06:16:04 PM PDT 24
Finished Jun 29 06:16:14 PM PDT 24
Peak memory 164944 kb
Host smart-a20611ab-120b-457c-85b3-e2a60db13647
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3968041734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3968041734
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1580718248
Short name T62
Test name
Test status
Simulation time 1190530000 ps
CPU time 3.2 seconds
Started Jun 29 06:16:06 PM PDT 24
Finished Jun 29 06:16:14 PM PDT 24
Peak memory 164884 kb
Host smart-6b82c238-4626-487c-bbaa-3004fda51979
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580718248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1580718248
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.1515317628
Short name T63
Test name
Test status
Simulation time 1349830000 ps
CPU time 4.8 seconds
Started Jun 29 06:16:11 PM PDT 24
Finished Jun 29 06:16:23 PM PDT 24
Peak memory 164944 kb
Host smart-66106631-5f15-43b1-89aa-5b0d911ab0f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1515317628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.1515317628
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.915858223
Short name T39
Test name
Test status
Simulation time 1602990000 ps
CPU time 4.97 seconds
Started Jun 29 06:16:12 PM PDT 24
Finished Jun 29 06:16:24 PM PDT 24
Peak memory 164864 kb
Host smart-c7beadf6-417a-4017-bebc-0335e129b8bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=915858223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.915858223
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.4281313373
Short name T31
Test name
Test status
Simulation time 1516930000 ps
CPU time 3.95 seconds
Started Jun 29 06:16:13 PM PDT 24
Finished Jun 29 06:16:22 PM PDT 24
Peak memory 164944 kb
Host smart-baa5f81d-c8ce-4b25-8edf-e26a20070a1c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4281313373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.4281313373
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3920238031
Short name T35
Test name
Test status
Simulation time 1408310000 ps
CPU time 5.11 seconds
Started Jun 29 06:16:11 PM PDT 24
Finished Jun 29 06:16:23 PM PDT 24
Peak memory 164904 kb
Host smart-2b5bba0d-725b-44ed-b394-ff0a97c8521a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3920238031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3920238031
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.803003610
Short name T46
Test name
Test status
Simulation time 1455730000 ps
CPU time 4.51 seconds
Started Jun 29 06:16:10 PM PDT 24
Finished Jun 29 06:16:21 PM PDT 24
Peak memory 164952 kb
Host smart-70c1952f-d44b-4e89-b32e-3822f5359aa9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=803003610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.803003610
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.379925388
Short name T7
Test name
Test status
Simulation time 1406190000 ps
CPU time 4.99 seconds
Started Jun 29 06:16:11 PM PDT 24
Finished Jun 29 06:16:23 PM PDT 24
Peak memory 164924 kb
Host smart-03d17655-e0de-4236-be74-8cf0f1fc5a40
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=379925388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.379925388
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2032825250
Short name T32
Test name
Test status
Simulation time 1434910000 ps
CPU time 5.08 seconds
Started Jun 29 06:16:15 PM PDT 24
Finished Jun 29 06:16:28 PM PDT 24
Peak memory 164932 kb
Host smart-80d10d15-d1f5-4167-8872-b8efb14064b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2032825250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2032825250
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2942836280
Short name T55
Test name
Test status
Simulation time 1546550000 ps
CPU time 4.13 seconds
Started Jun 29 06:16:11 PM PDT 24
Finished Jun 29 06:16:21 PM PDT 24
Peak memory 164952 kb
Host smart-456fd273-5cf9-475f-9f53-2ccd67298747
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2942836280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2942836280
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.214515972
Short name T56
Test name
Test status
Simulation time 1282150000 ps
CPU time 4.71 seconds
Started Jun 29 06:16:11 PM PDT 24
Finished Jun 29 06:16:22 PM PDT 24
Peak memory 164952 kb
Host smart-a8bf7f2a-aa6d-42d7-bd40-074bf7a67210
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214515972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.214515972
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2896673831
Short name T9
Test name
Test status
Simulation time 1235070000 ps
CPU time 5.77 seconds
Started Jun 29 06:16:01 PM PDT 24
Finished Jun 29 06:16:13 PM PDT 24
Peak memory 164820 kb
Host smart-cf0c6949-29e3-4194-b643-e097495a9ddb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2896673831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2896673831
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.997896829
Short name T53
Test name
Test status
Simulation time 1413410000 ps
CPU time 4.75 seconds
Started Jun 29 06:16:09 PM PDT 24
Finished Jun 29 06:16:19 PM PDT 24
Peak memory 164856 kb
Host smart-c83d4e0b-a9f6-47a2-82c2-fded2aaee96e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=997896829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.997896829
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3940817832
Short name T69
Test name
Test status
Simulation time 1522830000 ps
CPU time 5.21 seconds
Started Jun 29 06:16:19 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 164944 kb
Host smart-075c8d69-909f-43d0-a4b3-e8fbe5a5580f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3940817832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3940817832
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.454558039
Short name T45
Test name
Test status
Simulation time 1313990000 ps
CPU time 4.7 seconds
Started Jun 29 06:16:19 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 164952 kb
Host smart-ca5ca9fb-831b-465e-a927-1fe51842128b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454558039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.454558039
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1070400769
Short name T64
Test name
Test status
Simulation time 1468730000 ps
CPU time 4.62 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 164944 kb
Host smart-c6e4499c-9ba7-48ec-befc-f5d81fa66205
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1070400769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1070400769
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1257626792
Short name T48
Test name
Test status
Simulation time 1497050000 ps
CPU time 4.17 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 164944 kb
Host smart-1dd92ddb-d2ae-4cec-850a-314d84c12d92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1257626792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1257626792
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3118454257
Short name T68
Test name
Test status
Simulation time 1358450000 ps
CPU time 3.66 seconds
Started Jun 29 06:16:22 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 164916 kb
Host smart-ae6a1b0e-ddff-4f38-a9fd-d3ed1770953b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118454257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3118454257
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3788825811
Short name T3
Test name
Test status
Simulation time 1172410000 ps
CPU time 4.54 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 164944 kb
Host smart-a84f9aa6-ce40-4e04-a4e7-656c3173f747
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788825811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3788825811
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.681531895
Short name T50
Test name
Test status
Simulation time 1426230000 ps
CPU time 4.45 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:33 PM PDT 24
Peak memory 164952 kb
Host smart-9b5a4fad-7090-4e5e-9352-5181f6644cb0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=681531895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.681531895
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3780385555
Short name T38
Test name
Test status
Simulation time 1473250000 ps
CPU time 5.25 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164904 kb
Host smart-2f4a82b7-814c-411f-bb08-40d30d649a9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3780385555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3780385555
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.731198538
Short name T54
Test name
Test status
Simulation time 1358590000 ps
CPU time 5.68 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164952 kb
Host smart-82d21938-5ae5-40b8-8637-7fbe3d103f9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=731198538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.731198538
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1672584959
Short name T44
Test name
Test status
Simulation time 1577490000 ps
CPU time 4.6 seconds
Started Jun 29 06:16:05 PM PDT 24
Finished Jun 29 06:16:15 PM PDT 24
Peak memory 164944 kb
Host smart-20b60294-06b9-4568-98d2-fffef32918f3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1672584959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1672584959
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1407515114
Short name T40
Test name
Test status
Simulation time 1126250000 ps
CPU time 3.16 seconds
Started Jun 29 06:16:19 PM PDT 24
Finished Jun 29 06:16:26 PM PDT 24
Peak memory 164944 kb
Host smart-1a46b968-a931-465d-9b3a-11a051bb7dd5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1407515114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1407515114
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.504601749
Short name T43
Test name
Test status
Simulation time 1477870000 ps
CPU time 4.69 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 164912 kb
Host smart-efa9fd49-c1b1-44e7-8d76-757bd159db42
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=504601749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.504601749
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2468424517
Short name T70
Test name
Test status
Simulation time 1255090000 ps
CPU time 3.73 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 164944 kb
Host smart-3bdce092-41f4-4785-b416-e2b607ba7d2f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468424517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2468424517
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3391557885
Short name T57
Test name
Test status
Simulation time 1582750000 ps
CPU time 4.95 seconds
Started Jun 29 06:16:23 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164816 kb
Host smart-2c969c97-1c2b-4996-b496-d053984c9bc3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3391557885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3391557885
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1694596870
Short name T11
Test name
Test status
Simulation time 1204290000 ps
CPU time 4.84 seconds
Started Jun 29 06:16:22 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164940 kb
Host smart-b9c06e31-e50b-493f-bc43-11d4861d6a11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1694596870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1694596870
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3726048705
Short name T65
Test name
Test status
Simulation time 1529150000 ps
CPU time 4.83 seconds
Started Jun 29 06:16:27 PM PDT 24
Finished Jun 29 06:16:38 PM PDT 24
Peak memory 164904 kb
Host smart-934dcd11-b5d5-4cc4-9d17-5bd4d808a629
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3726048705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3726048705
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1630730608
Short name T60
Test name
Test status
Simulation time 1415890000 ps
CPU time 4.59 seconds
Started Jun 29 06:16:23 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164940 kb
Host smart-45f92987-8f17-4ebf-91ad-6737c9586fbf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1630730608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1630730608
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1887524707
Short name T36
Test name
Test status
Simulation time 1540270000 ps
CPU time 4.78 seconds
Started Jun 29 06:16:25 PM PDT 24
Finished Jun 29 06:16:36 PM PDT 24
Peak memory 164940 kb
Host smart-c515a780-80a7-4625-847e-8c5ec1b30520
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1887524707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1887524707
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1388305414
Short name T34
Test name
Test status
Simulation time 1382670000 ps
CPU time 4.67 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:30 PM PDT 24
Peak memory 164944 kb
Host smart-42d18805-43bf-465c-890a-17c6ea511807
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1388305414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1388305414
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2622491366
Short name T61
Test name
Test status
Simulation time 1624690000 ps
CPU time 6.19 seconds
Started Jun 29 06:16:19 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164944 kb
Host smart-65b6c20f-2b46-430c-8715-bdab0666907f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622491366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2622491366
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2125085102
Short name T49
Test name
Test status
Simulation time 1333710000 ps
CPU time 4.67 seconds
Started Jun 29 06:16:09 PM PDT 24
Finished Jun 29 06:16:20 PM PDT 24
Peak memory 164948 kb
Host smart-414822c3-eab1-4d36-ad8f-96ace9f93778
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2125085102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2125085102
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3376557534
Short name T10
Test name
Test status
Simulation time 1447010000 ps
CPU time 5.6 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:35 PM PDT 24
Peak memory 164940 kb
Host smart-d7db96b9-32cb-4c07-97ec-07fae715f1fe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376557534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3376557534
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1868453968
Short name T1
Test name
Test status
Simulation time 1594130000 ps
CPU time 5.28 seconds
Started Jun 29 06:16:21 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164944 kb
Host smart-6e919a10-f15b-408f-b8e5-6908c8151e55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1868453968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1868453968
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1484430018
Short name T52
Test name
Test status
Simulation time 1579950000 ps
CPU time 6.4 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:35 PM PDT 24
Peak memory 164904 kb
Host smart-efefa7f3-4794-4c9a-ba3b-fa27c71eca87
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1484430018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1484430018
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1747567479
Short name T33
Test name
Test status
Simulation time 1090830000 ps
CPU time 3.15 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:28 PM PDT 24
Peak memory 164944 kb
Host smart-23b88c4d-d13f-4c82-b154-ded8acae2afb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1747567479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1747567479
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2046692757
Short name T8
Test name
Test status
Simulation time 1366530000 ps
CPU time 4.69 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:31 PM PDT 24
Peak memory 164868 kb
Host smart-b4e8e62c-a20e-4be0-90c7-c67dff81f08a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2046692757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2046692757
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3212574968
Short name T51
Test name
Test status
Simulation time 1521910000 ps
CPU time 4.72 seconds
Started Jun 29 06:16:23 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164848 kb
Host smart-bec6fa97-c5da-4723-bf46-a7c114877b78
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3212574968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.3212574968
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4016585838
Short name T59
Test name
Test status
Simulation time 1530830000 ps
CPU time 6.21 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164912 kb
Host smart-3ad73c33-bad6-4c7d-a234-7f681b4e190d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4016585838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4016585838
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1586020876
Short name T13
Test name
Test status
Simulation time 1553890000 ps
CPU time 4.75 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:32 PM PDT 24
Peak memory 164944 kb
Host smart-c5a04b7d-2e71-4323-9595-1a32937bdc38
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586020876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1586020876
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1968972381
Short name T12
Test name
Test status
Simulation time 1362950000 ps
CPU time 5.64 seconds
Started Jun 29 06:16:20 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164944 kb
Host smart-2e37f01e-e64f-4504-aa3f-8f893453918c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968972381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1968972381
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.4233921859
Short name T41
Test name
Test status
Simulation time 1178270000 ps
CPU time 4.78 seconds
Started Jun 29 06:16:23 PM PDT 24
Finished Jun 29 06:16:34 PM PDT 24
Peak memory 164952 kb
Host smart-f5d8c061-288d-4407-89fe-2cfff6dc9270
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4233921859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.4233921859
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3425234498
Short name T67
Test name
Test status
Simulation time 1554230000 ps
CPU time 6.05 seconds
Started Jun 29 06:16:03 PM PDT 24
Finished Jun 29 06:16:17 PM PDT 24
Peak memory 164948 kb
Host smart-10d08867-00f1-4717-a66f-f6aed451e248
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425234498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3425234498
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2107141393
Short name T37
Test name
Test status
Simulation time 1382690000 ps
CPU time 5.31 seconds
Started Jun 29 06:16:01 PM PDT 24
Finished Jun 29 06:16:13 PM PDT 24
Peak memory 164948 kb
Host smart-b94d2211-c75d-47d5-9240-75e540dffef7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2107141393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2107141393
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4232730452
Short name T66
Test name
Test status
Simulation time 1572830000 ps
CPU time 5.85 seconds
Started Jun 29 06:16:10 PM PDT 24
Finished Jun 29 06:16:23 PM PDT 24
Peak memory 164856 kb
Host smart-7062483e-4958-4a0b-b7f4-5b10f15c907c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4232730452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.4232730452
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.4104707747
Short name T47
Test name
Test status
Simulation time 1297570000 ps
CPU time 4.3 seconds
Started Jun 29 06:16:13 PM PDT 24
Finished Jun 29 06:16:22 PM PDT 24
Peak memory 164932 kb
Host smart-07e4c911-df8b-4ed6-9dcd-6bd4e5b0479c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4104707747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.4104707747
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2898800549
Short name T42
Test name
Test status
Simulation time 1497670000 ps
CPU time 5.02 seconds
Started Jun 29 06:16:15 PM PDT 24
Finished Jun 29 06:16:27 PM PDT 24
Peak memory 164936 kb
Host smart-3b74bbba-9879-44f7-940a-ce40fea481f7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2898800549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2898800549
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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