Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.396670689
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2393567288
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2230735197

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2842167591
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2257591737
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1080215749
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3263993253
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3510427869
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.375431148
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2935473647
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2458617724
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3587335288
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2800052362
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.131844572
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2941527770
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3678728977
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3103798331
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3207645829
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3128898901
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1371252043
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3401196022
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.538233003
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1587139460
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3825631334
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1400093940
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2913680999
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2500697720
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.251791431
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3778609713
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1462465397
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2028199426
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.545464924
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1122555287
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.280185281
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1306542447
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2141595409
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.355790165
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1742069181
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4156546387
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2558831698
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.731576433
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.108894919
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2078384090
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1535351398
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3818893982
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1219058529
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1723114952
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1043387061
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3466887505
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1430082052
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1014630315
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1537201362
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1242050288
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1629166402
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2256187251
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1310206789
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1569737284
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2962333803
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3010004494
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2873545599
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3516525722
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2782326666
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1091334999
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3041249050
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.817341177
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3737532439
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.827713414
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2523180324
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3660705867
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.520151733
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2304114970
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1104144135
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1473579224
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2658073962
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.730477730
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1053532084
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1213460651
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2800732191
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.755582893
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3526702132
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4084985895
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1650431737
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2584784961
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2447714194
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1851183458
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2811706084
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1845530428
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1040824252
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2090867783
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.254953866
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.588875128
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3908863308
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3571144438
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1727919700
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1717219408
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2808897936
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2767497254
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1600431680
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1680578040
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3238990844
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2085792372
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1904141063
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4019142305
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4247559495
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2376648830
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2328278228
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.703459312
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3699468972
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1142945311
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.35915271
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1123004703
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1436359989
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3514454867
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1637103964
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2316479735
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4237302961
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2311844091
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.649445947
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.954838753
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1040189355
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1163298497
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3044247472
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3728605444
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1044181217
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.662310346
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.801201954
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.480857549
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2267038423
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2512378336
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.701895975
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.205497680
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1310321563
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4185255035
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2875700714
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1257901349
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3405404192
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2583671420
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2091454919
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1861727269
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1273343448
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2754342366
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2618748496
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.426862888
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2755988124
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.135772942
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3839728204
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2015413462
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1877477637
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.525665614
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.505910236
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3885115672
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.155386827
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3730662393
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.840593935
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4099809097
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2682388722
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3347976010
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1498537103
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3058664679
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1055936561
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1661012946
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3753528322
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1451456568
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2638098918
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1508916414
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2816020873
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4147376470
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.746770695
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.882445189
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3316370386
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3004090026
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2681674913
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.928267621
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.446829986
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4154092320
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2363804060
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4253519973
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3718055422
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1232792672
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1460638266
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3223773396
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1573424934
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2242947867
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.352218818
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.123030939
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3648492391
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.881659873
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.746383929
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2984681306
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2961645471
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2747003820
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1064136495
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3187428954
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.257363576
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1498455860
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1434744402
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.268055432
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3658074200
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3052579489
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1744054546



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.396670689 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:27 PM PDT 24 1462550000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2681674913 Jun 30 05:47:20 PM PDT 24 Jun 30 05:47:29 PM PDT 24 1439030000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3753528322 Jun 30 05:47:17 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1492710000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1498537103 Jun 30 05:47:22 PM PDT 24 Jun 30 05:47:34 PM PDT 24 1570310000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4147376470 Jun 30 05:47:18 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1418850000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4099809097 Jun 30 05:47:15 PM PDT 24 Jun 30 05:47:24 PM PDT 24 1619450000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.746383929 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1560370000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2961645471 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:31 PM PDT 24 1527210000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1451456568 Jun 30 05:47:20 PM PDT 24 Jun 30 05:47:29 PM PDT 24 1483410000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.268055432 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:30 PM PDT 24 1152750000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3648492391 Jun 30 05:47:19 PM PDT 24 Jun 30 05:47:28 PM PDT 24 1414310000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3730662393 Jun 30 05:47:19 PM PDT 24 Jun 30 05:47:30 PM PDT 24 1545030000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2747003820 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:27 PM PDT 24 1464850000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1661012946 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:32 PM PDT 24 1344890000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.882445189 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:32 PM PDT 24 1494410000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4154092320 Jun 30 05:47:15 PM PDT 24 Jun 30 05:47:25 PM PDT 24 1535190000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.123030939 Jun 30 05:47:15 PM PDT 24 Jun 30 05:47:23 PM PDT 24 1361710000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3004090026 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1585250000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1055936561 Jun 30 05:47:15 PM PDT 24 Jun 30 05:47:27 PM PDT 24 1492790000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3058664679 Jun 30 05:47:18 PM PDT 24 Jun 30 05:47:27 PM PDT 24 1268150000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2363804060 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:28 PM PDT 24 1398790000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3658074200 Jun 30 05:47:19 PM PDT 24 Jun 30 05:47:27 PM PDT 24 1453190000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3223773396 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:30 PM PDT 24 1476390000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3187428954 Jun 30 05:47:15 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1402270000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1064136495 Jun 30 05:47:22 PM PDT 24 Jun 30 05:47:35 PM PDT 24 1507450000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2242947867 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:34 PM PDT 24 1517470000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3052579489 Jun 30 05:47:09 PM PDT 24 Jun 30 05:47:16 PM PDT 24 1324510000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.155386827 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:25 PM PDT 24 1327690000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.746770695 Jun 30 05:47:19 PM PDT 24 Jun 30 05:47:30 PM PDT 24 1313630000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1744054546 Jun 30 05:47:18 PM PDT 24 Jun 30 05:47:25 PM PDT 24 1214030000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2638098918 Jun 30 05:47:14 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1619470000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.352218818 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1458530000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4253519973 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:29 PM PDT 24 1460990000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.257363576 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1302690000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.881659873 Jun 30 05:47:20 PM PDT 24 Jun 30 05:47:31 PM PDT 24 1589230000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2816020873 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:32 PM PDT 24 1408110000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1460638266 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:31 PM PDT 24 1080750000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1573424934 Jun 30 05:47:17 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1386110000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.928267621 Jun 30 05:47:15 PM PDT 24 Jun 30 05:47:24 PM PDT 24 1380490000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.446829986 Jun 30 05:47:18 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1427730000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2984681306 Jun 30 05:47:17 PM PDT 24 Jun 30 05:47:28 PM PDT 24 1367530000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1434744402 Jun 30 05:47:19 PM PDT 24 Jun 30 05:47:25 PM PDT 24 1171010000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1508916414 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:30 PM PDT 24 1476770000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1232792672 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:24 PM PDT 24 1275270000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.840593935 Jun 30 05:47:18 PM PDT 24 Jun 30 05:47:29 PM PDT 24 1522230000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2682388722 Jun 30 05:47:22 PM PDT 24 Jun 30 05:47:29 PM PDT 24 1094790000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1498455860 Jun 30 05:47:18 PM PDT 24 Jun 30 05:47:28 PM PDT 24 1446290000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3718055422 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:35 PM PDT 24 1669050000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3316370386 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:26 PM PDT 24 1355910000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3347976010 Jun 30 05:47:17 PM PDT 24 Jun 30 05:47:31 PM PDT 24 1518790000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3207645829 Jun 30 05:46:41 PM PDT 24 Jun 30 06:22:49 PM PDT 24 336624990000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2458617724 Jun 30 05:46:35 PM PDT 24 Jun 30 06:22:35 PM PDT 24 336987390000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1430082052 Jun 30 05:46:31 PM PDT 24 Jun 30 06:27:32 PM PDT 24 336477350000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3401196022 Jun 30 05:46:34 PM PDT 24 Jun 30 06:15:51 PM PDT 24 336953490000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2393567288 Jun 30 05:46:36 PM PDT 24 Jun 30 06:21:59 PM PDT 24 336436010000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2078384090 Jun 30 05:46:33 PM PDT 24 Jun 30 06:22:39 PM PDT 24 336879930000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1371252043 Jun 30 05:46:37 PM PDT 24 Jun 30 06:16:04 PM PDT 24 336501130000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.251791431 Jun 30 05:46:35 PM PDT 24 Jun 30 06:28:10 PM PDT 24 336428130000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3778609713 Jun 30 05:46:48 PM PDT 24 Jun 30 06:24:10 PM PDT 24 336392590000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2941527770 Jun 30 05:46:32 PM PDT 24 Jun 30 06:27:40 PM PDT 24 336765430000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3678728977 Jun 30 05:46:31 PM PDT 24 Jun 30 06:27:42 PM PDT 24 336904750000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3825631334 Jun 30 05:46:45 PM PDT 24 Jun 30 06:22:50 PM PDT 24 336818110000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3263993253 Jun 30 05:46:31 PM PDT 24 Jun 30 06:21:42 PM PDT 24 337051890000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1014630315 Jun 30 05:46:32 PM PDT 24 Jun 30 06:19:49 PM PDT 24 337057850000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.731576433 Jun 30 05:46:35 PM PDT 24 Jun 30 06:22:30 PM PDT 24 336409530000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1306542447 Jun 30 05:46:35 PM PDT 24 Jun 30 06:19:51 PM PDT 24 336494330000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2558831698 Jun 30 05:46:31 PM PDT 24 Jun 30 06:19:19 PM PDT 24 336816310000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2935473647 Jun 30 05:46:46 PM PDT 24 Jun 30 06:24:08 PM PDT 24 336677130000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.375431148 Jun 30 05:46:33 PM PDT 24 Jun 30 06:15:21 PM PDT 24 336933630000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2257591737 Jun 30 05:46:32 PM PDT 24 Jun 30 06:21:04 PM PDT 24 336293590000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1462465397 Jun 30 05:46:33 PM PDT 24 Jun 30 06:16:07 PM PDT 24 337166630000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3818893982 Jun 30 05:46:31 PM PDT 24 Jun 30 06:17:22 PM PDT 24 336730210000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4156546387 Jun 30 05:46:36 PM PDT 24 Jun 30 06:22:38 PM PDT 24 336981990000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.538233003 Jun 30 05:46:35 PM PDT 24 Jun 30 06:22:10 PM PDT 24 336588210000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2500697720 Jun 30 05:46:35 PM PDT 24 Jun 30 06:19:39 PM PDT 24 336653350000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3128898901 Jun 30 05:46:31 PM PDT 24 Jun 30 06:21:59 PM PDT 24 336891730000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1742069181 Jun 30 05:46:35 PM PDT 24 Jun 30 06:16:53 PM PDT 24 336941870000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3510427869 Jun 30 05:46:32 PM PDT 24 Jun 30 06:24:34 PM PDT 24 336882530000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1122555287 Jun 30 05:46:35 PM PDT 24 Jun 30 06:16:57 PM PDT 24 336719690000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2028199426 Jun 30 05:46:35 PM PDT 24 Jun 30 06:22:18 PM PDT 24 337040190000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1219058529 Jun 30 05:46:43 PM PDT 24 Jun 30 06:22:54 PM PDT 24 336711330000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1723114952 Jun 30 05:46:33 PM PDT 24 Jun 30 06:18:57 PM PDT 24 336383730000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2141595409 Jun 30 05:46:43 PM PDT 24 Jun 30 06:24:09 PM PDT 24 336748770000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2800052362 Jun 30 05:46:34 PM PDT 24 Jun 30 06:20:06 PM PDT 24 336609190000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3587335288 Jun 30 05:46:33 PM PDT 24 Jun 30 06:16:36 PM PDT 24 337085530000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3103798331 Jun 30 05:46:36 PM PDT 24 Jun 30 06:28:10 PM PDT 24 336758170000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2913680999 Jun 30 05:46:35 PM PDT 24 Jun 30 06:19:57 PM PDT 24 337082010000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.131844572 Jun 30 05:46:43 PM PDT 24 Jun 30 06:24:04 PM PDT 24 336740490000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1043387061 Jun 30 05:46:36 PM PDT 24 Jun 30 06:28:13 PM PDT 24 336945010000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.545464924 Jun 30 05:46:35 PM PDT 24 Jun 30 06:19:46 PM PDT 24 336603290000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.108894919 Jun 30 05:46:52 PM PDT 24 Jun 30 06:22:51 PM PDT 24 336481430000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1587139460 Jun 30 05:46:45 PM PDT 24 Jun 30 06:22:52 PM PDT 24 336808150000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1537201362 Jun 30 05:46:33 PM PDT 24 Jun 30 06:22:12 PM PDT 24 336708890000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1400093940 Jun 30 05:46:33 PM PDT 24 Jun 30 06:22:25 PM PDT 24 337061610000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2842167591 Jun 30 05:46:33 PM PDT 24 Jun 30 06:18:36 PM PDT 24 336774450000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3466887505 Jun 30 05:46:36 PM PDT 24 Jun 30 06:28:13 PM PDT 24 336922410000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1535351398 Jun 30 05:46:37 PM PDT 24 Jun 30 06:16:31 PM PDT 24 336432030000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1080215749 Jun 30 05:46:49 PM PDT 24 Jun 30 06:24:17 PM PDT 24 336654290000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.355790165 Jun 30 05:46:32 PM PDT 24 Jun 30 06:17:58 PM PDT 24 336414950000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.280185281 Jun 30 05:46:30 PM PDT 24 Jun 30 06:12:54 PM PDT 24 336616370000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1273343448 Jun 30 05:47:36 PM PDT 24 Jun 30 05:47:46 PM PDT 24 1556990000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4185255035 Jun 30 05:47:36 PM PDT 24 Jun 30 05:47:45 PM PDT 24 1264770000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3514454867 Jun 30 05:47:26 PM PDT 24 Jun 30 05:47:36 PM PDT 24 1395070000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1436359989 Jun 30 05:47:29 PM PDT 24 Jun 30 05:47:39 PM PDT 24 1408810000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2316479735 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:32 PM PDT 24 1458930000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2311844091 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:40 PM PDT 24 1631830000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1142945311 Jun 30 05:47:27 PM PDT 24 Jun 30 05:47:35 PM PDT 24 1547490000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.525665614 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:37 PM PDT 24 1292930000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1637103964 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:35 PM PDT 24 1584090000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2583671420 Jun 30 05:47:38 PM PDT 24 Jun 30 05:47:49 PM PDT 24 1313890000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2015413462 Jun 30 05:47:29 PM PDT 24 Jun 30 05:47:39 PM PDT 24 1458470000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4247559495 Jun 30 05:47:26 PM PDT 24 Jun 30 05:47:38 PM PDT 24 1279470000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2618748496 Jun 30 05:47:34 PM PDT 24 Jun 30 05:47:42 PM PDT 24 1516890000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1123004703 Jun 30 05:47:27 PM PDT 24 Jun 30 05:47:43 PM PDT 24 1538750000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2267038423 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:37 PM PDT 24 1128750000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1040189355 Jun 30 05:47:30 PM PDT 24 Jun 30 05:47:40 PM PDT 24 1349790000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2376648830 Jun 30 05:47:24 PM PDT 24 Jun 30 05:47:34 PM PDT 24 1194350000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.480857549 Jun 30 05:47:30 PM PDT 24 Jun 30 05:47:40 PM PDT 24 1391550000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.649445947 Jun 30 05:47:30 PM PDT 24 Jun 30 05:47:39 PM PDT 24 1266110000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4237302961 Jun 30 05:47:29 PM PDT 24 Jun 30 05:47:40 PM PDT 24 1433770000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.662310346 Jun 30 05:47:25 PM PDT 24 Jun 30 05:47:35 PM PDT 24 1557750000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3699468972 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1507210000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1861727269 Jun 30 05:47:38 PM PDT 24 Jun 30 05:47:49 PM PDT 24 1546210000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3044247472 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:38 PM PDT 24 1260650000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.205497680 Jun 30 05:47:36 PM PDT 24 Jun 30 05:47:47 PM PDT 24 1260430000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1257901349 Jun 30 05:47:34 PM PDT 24 Jun 30 05:47:44 PM PDT 24 1453250000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2755988124 Jun 30 05:47:35 PM PDT 24 Jun 30 05:47:43 PM PDT 24 1396030000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1904141063 Jun 30 05:47:16 PM PDT 24 Jun 30 05:47:25 PM PDT 24 1385150000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1163298497 Jun 30 05:47:29 PM PDT 24 Jun 30 05:47:40 PM PDT 24 1557130000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4019142305 Jun 30 05:47:24 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1294270000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.954838753 Jun 30 05:47:30 PM PDT 24 Jun 30 05:47:39 PM PDT 24 1488190000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1044181217 Jun 30 05:47:31 PM PDT 24 Jun 30 05:47:39 PM PDT 24 1168190000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.135772942 Jun 30 05:47:34 PM PDT 24 Jun 30 05:47:45 PM PDT 24 1410470000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3405404192 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:34 PM PDT 24 1442330000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.701895975 Jun 30 05:47:35 PM PDT 24 Jun 30 05:47:43 PM PDT 24 1166210000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1877477637 Jun 30 05:47:23 PM PDT 24 Jun 30 05:47:32 PM PDT 24 1407770000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2875700714 Jun 30 05:47:34 PM PDT 24 Jun 30 05:47:42 PM PDT 24 1602450000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2091454919 Jun 30 05:47:36 PM PDT 24 Jun 30 05:47:45 PM PDT 24 1564050000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.703459312 Jun 30 05:47:22 PM PDT 24 Jun 30 05:47:34 PM PDT 24 1438290000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3885115672 Jun 30 05:47:26 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1468710000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.35915271 Jun 30 05:47:21 PM PDT 24 Jun 30 05:47:32 PM PDT 24 1496770000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.801201954 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:38 PM PDT 24 1517270000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.505910236 Jun 30 05:47:24 PM PDT 24 Jun 30 05:47:33 PM PDT 24 1553290000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2754342366 Jun 30 05:47:35 PM PDT 24 Jun 30 05:47:46 PM PDT 24 1497310000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1310321563 Jun 30 05:47:36 PM PDT 24 Jun 30 05:47:44 PM PDT 24 1445090000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2512378336 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:36 PM PDT 24 1436210000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2328278228 Jun 30 05:47:25 PM PDT 24 Jun 30 05:47:35 PM PDT 24 1167710000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3839728204 Jun 30 05:47:37 PM PDT 24 Jun 30 05:47:46 PM PDT 24 1259190000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.426862888 Jun 30 05:47:35 PM PDT 24 Jun 30 05:47:45 PM PDT 24 1461810000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3728605444 Jun 30 05:47:28 PM PDT 24 Jun 30 05:47:39 PM PDT 24 1557150000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4084985895 Jun 30 05:51:18 PM PDT 24 Jun 30 06:23:31 PM PDT 24 336630130000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3010004494 Jun 30 05:51:11 PM PDT 24 Jun 30 06:19:51 PM PDT 24 336369970000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.520151733 Jun 30 05:51:13 PM PDT 24 Jun 30 06:29:03 PM PDT 24 337045710000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1650431737 Jun 30 05:51:20 PM PDT 24 Jun 30 06:24:28 PM PDT 24 336703370000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2230735197 Jun 30 05:51:12 PM PDT 24 Jun 30 06:24:50 PM PDT 24 336934950000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1717219408 Jun 30 05:51:27 PM PDT 24 Jun 30 06:29:07 PM PDT 24 337055010000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3737532439 Jun 30 05:51:10 PM PDT 24 Jun 30 06:26:01 PM PDT 24 336742470000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2873545599 Jun 30 05:51:12 PM PDT 24 Jun 30 06:24:53 PM PDT 24 336758670000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1091334999 Jun 30 05:51:10 PM PDT 24 Jun 30 06:31:11 PM PDT 24 336758350000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.730477730 Jun 30 05:51:12 PM PDT 24 Jun 30 06:20:41 PM PDT 24 336559610000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1473579224 Jun 30 05:51:19 PM PDT 24 Jun 30 06:23:17 PM PDT 24 336868570000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3041249050 Jun 30 05:51:13 PM PDT 24 Jun 30 06:29:05 PM PDT 24 336904970000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2658073962 Jun 30 05:51:16 PM PDT 24 Jun 30 06:26:48 PM PDT 24 336748910000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.827713414 Jun 30 05:51:11 PM PDT 24 Jun 30 06:22:51 PM PDT 24 337043470000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2767497254 Jun 30 05:51:12 PM PDT 24 Jun 30 06:25:27 PM PDT 24 337169750000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2256187251 Jun 30 05:51:09 PM PDT 24 Jun 30 06:24:58 PM PDT 24 336857030000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.817341177 Jun 30 05:51:12 PM PDT 24 Jun 30 06:21:17 PM PDT 24 336706030000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1680578040 Jun 30 05:51:10 PM PDT 24 Jun 30 06:27:13 PM PDT 24 336440530000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3516525722 Jun 30 05:51:10 PM PDT 24 Jun 30 06:26:28 PM PDT 24 336851850000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3526702132 Jun 30 05:51:19 PM PDT 24 Jun 30 06:27:04 PM PDT 24 336385250000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3571144438 Jun 30 05:51:17 PM PDT 24 Jun 30 06:24:17 PM PDT 24 336688450000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2523180324 Jun 30 05:51:10 PM PDT 24 Jun 30 06:23:46 PM PDT 24 336508830000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.755582893 Jun 30 05:51:19 PM PDT 24 Jun 30 06:29:13 PM PDT 24 336957470000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2811706084 Jun 30 05:51:12 PM PDT 24 Jun 30 06:26:47 PM PDT 24 336967750000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3908863308 Jun 30 05:51:19 PM PDT 24 Jun 30 06:24:36 PM PDT 24 336490830000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2304114970 Jun 30 05:51:17 PM PDT 24 Jun 30 06:21:45 PM PDT 24 336960230000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1727919700 Jun 30 05:51:27 PM PDT 24 Jun 30 06:29:28 PM PDT 24 337115690000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1104144135 Jun 30 05:51:19 PM PDT 24 Jun 30 06:23:25 PM PDT 24 336425130000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1040824252 Jun 30 05:51:18 PM PDT 24 Jun 30 06:25:32 PM PDT 24 336533890000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1310206789 Jun 30 05:51:12 PM PDT 24 Jun 30 06:26:54 PM PDT 24 336655330000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1851183458 Jun 30 05:51:20 PM PDT 24 Jun 30 06:25:12 PM PDT 24 336676370000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1629166402 Jun 30 05:51:11 PM PDT 24 Jun 30 06:21:06 PM PDT 24 336399290000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1569737284 Jun 30 05:51:09 PM PDT 24 Jun 30 06:22:24 PM PDT 24 336767290000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1600431680 Jun 30 05:51:10 PM PDT 24 Jun 30 06:22:03 PM PDT 24 337116350000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2584784961 Jun 30 05:51:18 PM PDT 24 Jun 30 06:27:15 PM PDT 24 336397850000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2085792372 Jun 30 05:51:12 PM PDT 24 Jun 30 06:23:16 PM PDT 24 336620910000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2447714194 Jun 30 05:51:18 PM PDT 24 Jun 30 06:24:37 PM PDT 24 336915330000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2962333803 Jun 30 05:51:10 PM PDT 24 Jun 30 06:20:50 PM PDT 24 337032830000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.254953866 Jun 30 05:51:18 PM PDT 24 Jun 30 06:25:10 PM PDT 24 336952610000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.588875128 Jun 30 05:51:19 PM PDT 24 Jun 30 06:24:04 PM PDT 24 336358050000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1845530428 Jun 30 05:51:18 PM PDT 24 Jun 30 06:25:39 PM PDT 24 336642370000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2782326666 Jun 30 05:51:11 PM PDT 24 Jun 30 06:21:13 PM PDT 24 336605370000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3238990844 Jun 30 05:51:13 PM PDT 24 Jun 30 06:26:27 PM PDT 24 336442910000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1213460651 Jun 30 05:51:19 PM PDT 24 Jun 30 06:27:06 PM PDT 24 337053430000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1242050288 Jun 30 05:51:11 PM PDT 24 Jun 30 06:26:25 PM PDT 24 336497910000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1053532084 Jun 30 05:51:17 PM PDT 24 Jun 30 06:13:33 PM PDT 24 336763650000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3660705867 Jun 30 05:51:12 PM PDT 24 Jun 30 06:28:55 PM PDT 24 336380550000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2800732191 Jun 30 05:51:19 PM PDT 24 Jun 30 06:22:15 PM PDT 24 337131070000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2808897936 Jun 30 05:51:27 PM PDT 24 Jun 30 06:28:33 PM PDT 24 336791530000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2090867783 Jun 30 05:51:18 PM PDT 24 Jun 30 06:21:20 PM PDT 24 337076970000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.396670689
Short name T1
Test name
Test status
Simulation time 1462550000 ps
CPU time 4.71 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:27 PM PDT 24
Peak memory 164936 kb
Host smart-23035b96-22d2-43bf-b838-a1b8fca20e3b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=396670689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.396670689
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2393567288
Short name T15
Test name
Test status
Simulation time 336436010000 ps
CPU time 842.69 seconds
Started Jun 30 05:46:36 PM PDT 24
Finished Jun 30 06:21:59 PM PDT 24
Peak memory 160788 kb
Host smart-1c217e9f-aaf7-4e69-99a3-e698e5e8fa55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2393567288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2393567288
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2230735197
Short name T25
Test name
Test status
Simulation time 336934950000 ps
CPU time 820.83 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:24:50 PM PDT 24
Peak memory 160816 kb
Host smart-393a3419-3a96-4e1f-a92c-4904ed6792e4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2230735197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2230735197
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2842167591
Short name T105
Test name
Test status
Simulation time 336774450000 ps
CPU time 779.66 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:18:36 PM PDT 24
Peak memory 160820 kb
Host smart-ab578eb0-5dbf-41ab-ad6e-c44a7059a936
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2842167591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2842167591
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2257591737
Short name T80
Test name
Test status
Simulation time 336293590000 ps
CPU time 862.46 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 06:21:04 PM PDT 24
Peak memory 160784 kb
Host smart-677d1ad8-5b8d-45a5-a7d7-3a9d7b03227c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2257591737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2257591737
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1080215749
Short name T108
Test name
Test status
Simulation time 336654290000 ps
CPU time 896.18 seconds
Started Jun 30 05:46:49 PM PDT 24
Finished Jun 30 06:24:17 PM PDT 24
Peak memory 160828 kb
Host smart-3a3b2452-af9d-4613-ad1f-ed13fb65215f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1080215749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1080215749
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3263993253
Short name T73
Test name
Test status
Simulation time 337051890000 ps
CPU time 856.34 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 06:21:42 PM PDT 24
Peak memory 160824 kb
Host smart-19324327-fb89-46c8-a9e3-9da6f0c51a53
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3263993253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3263993253
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3510427869
Short name T88
Test name
Test status
Simulation time 336882530000 ps
CPU time 918.98 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 06:24:34 PM PDT 24
Peak memory 160796 kb
Host smart-5becd52b-fa69-49aa-8e05-818259f8ccaa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3510427869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3510427869
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.375431148
Short name T79
Test name
Test status
Simulation time 336933630000 ps
CPU time 705.53 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:15:21 PM PDT 24
Peak memory 160816 kb
Host smart-5f5beb79-b002-4fc1-a2f9-2c74eaa4398e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=375431148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.375431148
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2935473647
Short name T78
Test name
Test status
Simulation time 336677130000 ps
CPU time 905.56 seconds
Started Jun 30 05:46:46 PM PDT 24
Finished Jun 30 06:24:08 PM PDT 24
Peak memory 160828 kb
Host smart-c96daaa2-70b4-4bf2-abfb-b81525f62e34
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2935473647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2935473647
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2458617724
Short name T5
Test name
Test status
Simulation time 336987390000 ps
CPU time 859.51 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:22:35 PM PDT 24
Peak memory 160788 kb
Host smart-1dab404f-87d8-4f1d-a244-30dfe8b86bf2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2458617724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2458617724
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3587335288
Short name T95
Test name
Test status
Simulation time 337085530000 ps
CPU time 745.84 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:16:36 PM PDT 24
Peak memory 160816 kb
Host smart-ee249e62-ef02-4c7f-9718-c8d76cd36982
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3587335288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3587335288
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2800052362
Short name T94
Test name
Test status
Simulation time 336609190000 ps
CPU time 827.33 seconds
Started Jun 30 05:46:34 PM PDT 24
Finished Jun 30 06:20:06 PM PDT 24
Peak memory 160820 kb
Host smart-0903f829-0401-4ca2-97bc-069c2b1002fb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2800052362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2800052362
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.131844572
Short name T98
Test name
Test status
Simulation time 336740490000 ps
CPU time 908.3 seconds
Started Jun 30 05:46:43 PM PDT 24
Finished Jun 30 06:24:04 PM PDT 24
Peak memory 160820 kb
Host smart-dd66d902-17a2-49b4-a1fb-c5dac23485fc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=131844572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.131844572
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2941527770
Short name T20
Test name
Test status
Simulation time 336765430000 ps
CPU time 987.61 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 06:27:40 PM PDT 24
Peak memory 160816 kb
Host smart-771297f1-9eec-4e12-81a7-98b523a426ab
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2941527770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2941527770
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3678728977
Short name T71
Test name
Test status
Simulation time 336904750000 ps
CPU time 980.76 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 06:27:42 PM PDT 24
Peak memory 160824 kb
Host smart-84c6c3d2-4594-4d58-9627-6d032dcef342
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3678728977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3678728977
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3103798331
Short name T96
Test name
Test status
Simulation time 336758170000 ps
CPU time 982.75 seconds
Started Jun 30 05:46:36 PM PDT 24
Finished Jun 30 06:28:10 PM PDT 24
Peak memory 160832 kb
Host smart-cac3cf50-1091-4e3d-9c5f-f762c4ccf9a1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3103798331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3103798331
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3207645829
Short name T4
Test name
Test status
Simulation time 336624990000 ps
CPU time 873 seconds
Started Jun 30 05:46:41 PM PDT 24
Finished Jun 30 06:22:49 PM PDT 24
Peak memory 160824 kb
Host smart-f727e863-4ee3-4253-9aa0-569c65c134e3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3207645829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.3207645829
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3128898901
Short name T86
Test name
Test status
Simulation time 336891730000 ps
CPU time 845.23 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 06:21:59 PM PDT 24
Peak memory 160784 kb
Host smart-58d4c6e2-e32c-4c82-ac2b-a63cd8f50467
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3128898901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3128898901
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1371252043
Short name T17
Test name
Test status
Simulation time 336501130000 ps
CPU time 716.22 seconds
Started Jun 30 05:46:37 PM PDT 24
Finished Jun 30 06:16:04 PM PDT 24
Peak memory 160820 kb
Host smart-fa1d2534-b681-4663-8b51-27789102092e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1371252043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1371252043
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3401196022
Short name T14
Test name
Test status
Simulation time 336953490000 ps
CPU time 715.89 seconds
Started Jun 30 05:46:34 PM PDT 24
Finished Jun 30 06:15:51 PM PDT 24
Peak memory 160816 kb
Host smart-9082806c-e73c-4dd0-a89a-9026ddd65fb6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3401196022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.3401196022
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.538233003
Short name T84
Test name
Test status
Simulation time 336588210000 ps
CPU time 846.43 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:22:10 PM PDT 24
Peak memory 160780 kb
Host smart-b34b5a12-88e0-4f51-8975-396044b4d727
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=538233003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.538233003
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1587139460
Short name T102
Test name
Test status
Simulation time 336808150000 ps
CPU time 870.78 seconds
Started Jun 30 05:46:45 PM PDT 24
Finished Jun 30 06:22:52 PM PDT 24
Peak memory 160824 kb
Host smart-ad070c57-83a4-41e6-b644-8378a309e668
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1587139460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1587139460
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3825631334
Short name T72
Test name
Test status
Simulation time 336818110000 ps
CPU time 871.85 seconds
Started Jun 30 05:46:45 PM PDT 24
Finished Jun 30 06:22:50 PM PDT 24
Peak memory 160824 kb
Host smart-24ed2f54-0838-47cf-b265-c3b87d8f7c13
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3825631334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3825631334
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1400093940
Short name T104
Test name
Test status
Simulation time 337061610000 ps
CPU time 883.14 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:22:25 PM PDT 24
Peak memory 160816 kb
Host smart-e357f9a3-f876-496e-8c79-dd4338f782ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1400093940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1400093940
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2913680999
Short name T97
Test name
Test status
Simulation time 337082010000 ps
CPU time 802.57 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:19:57 PM PDT 24
Peak memory 160816 kb
Host smart-9e34b380-c592-4c62-8f52-8627a347e01f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2913680999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2913680999
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2500697720
Short name T85
Test name
Test status
Simulation time 336653350000 ps
CPU time 819.64 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:19:39 PM PDT 24
Peak memory 160820 kb
Host smart-bc893f2d-0d09-468c-9ed4-a609b642a31e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2500697720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2500697720
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.251791431
Short name T18
Test name
Test status
Simulation time 336428130000 ps
CPU time 990.56 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:28:10 PM PDT 24
Peak memory 160824 kb
Host smart-add0501b-1565-4e01-84ee-ebd1a93c14bb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=251791431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.251791431
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.3778609713
Short name T19
Test name
Test status
Simulation time 336392590000 ps
CPU time 904.78 seconds
Started Jun 30 05:46:48 PM PDT 24
Finished Jun 30 06:24:10 PM PDT 24
Peak memory 160828 kb
Host smart-9b3277f2-f85a-499f-809a-37c5bce0e93c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3778609713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.3778609713
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1462465397
Short name T81
Test name
Test status
Simulation time 337166630000 ps
CPU time 720.98 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:16:07 PM PDT 24
Peak memory 160780 kb
Host smart-3bf1b1c3-e288-4f21-9107-c28328f8d2ef
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1462465397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1462465397
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2028199426
Short name T90
Test name
Test status
Simulation time 337040190000 ps
CPU time 850.8 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:22:18 PM PDT 24
Peak memory 160932 kb
Host smart-4c6f15fe-ddf8-42da-976e-775141fa6e58
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2028199426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2028199426
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.545464924
Short name T100
Test name
Test status
Simulation time 336603290000 ps
CPU time 797.49 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:19:46 PM PDT 24
Peak memory 160816 kb
Host smart-7b229ecf-9c71-4eea-9a9e-7d5a093c44e7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=545464924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.545464924
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1122555287
Short name T89
Test name
Test status
Simulation time 336719690000 ps
CPU time 738.41 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:16:57 PM PDT 24
Peak memory 160844 kb
Host smart-f1e2610f-8d0e-4c40-9795-c3898503cb6e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1122555287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1122555287
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.280185281
Short name T110
Test name
Test status
Simulation time 336616370000 ps
CPU time 632.03 seconds
Started Jun 30 05:46:30 PM PDT 24
Finished Jun 30 06:12:54 PM PDT 24
Peak memory 160816 kb
Host smart-4318aabe-29a1-48d0-b0e0-96a5a91e11ae
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=280185281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.280185281
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1306542447
Short name T76
Test name
Test status
Simulation time 336494330000 ps
CPU time 799.83 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:19:51 PM PDT 24
Peak memory 160824 kb
Host smart-48d5cb10-03b9-42de-9e31-683a86959d86
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1306542447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1306542447
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2141595409
Short name T93
Test name
Test status
Simulation time 336748770000 ps
CPU time 896.22 seconds
Started Jun 30 05:46:43 PM PDT 24
Finished Jun 30 06:24:09 PM PDT 24
Peak memory 160828 kb
Host smart-0ed12570-b386-46c6-995f-79decd88c5bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2141595409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2141595409
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.355790165
Short name T109
Test name
Test status
Simulation time 336414950000 ps
CPU time 772.21 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 06:17:58 PM PDT 24
Peak memory 160820 kb
Host smart-a4175f27-a593-4cd9-a104-a6cc88a9a092
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=355790165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.355790165
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1742069181
Short name T87
Test name
Test status
Simulation time 336941870000 ps
CPU time 734.25 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:16:53 PM PDT 24
Peak memory 160844 kb
Host smart-4f9b713a-27d8-46de-bdfa-341a001b1900
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1742069181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.1742069181
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4156546387
Short name T83
Test name
Test status
Simulation time 336981990000 ps
CPU time 859.23 seconds
Started Jun 30 05:46:36 PM PDT 24
Finished Jun 30 06:22:38 PM PDT 24
Peak memory 160932 kb
Host smart-c7f4ef73-d1ed-4817-8843-f1f20a717616
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4156546387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4156546387
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2558831698
Short name T77
Test name
Test status
Simulation time 336816310000 ps
CPU time 801.85 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 06:19:19 PM PDT 24
Peak memory 160828 kb
Host smart-6e1be43d-bc1f-49e4-becb-a309a4e12352
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2558831698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2558831698
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.731576433
Short name T75
Test name
Test status
Simulation time 336409530000 ps
CPU time 856.35 seconds
Started Jun 30 05:46:35 PM PDT 24
Finished Jun 30 06:22:30 PM PDT 24
Peak memory 160780 kb
Host smart-0c2b6215-930c-4aae-ae89-cefd4e7a4c19
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=731576433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.731576433
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.108894919
Short name T101
Test name
Test status
Simulation time 336481430000 ps
CPU time 871.82 seconds
Started Jun 30 05:46:52 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 160816 kb
Host smart-50a1de99-6fd2-4a36-b603-f93577b4ee14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=108894919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.108894919
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2078384090
Short name T16
Test name
Test status
Simulation time 336879930000 ps
CPU time 883.03 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:22:39 PM PDT 24
Peak memory 160720 kb
Host smart-1a33b278-567d-4deb-9fa3-0f9c8fe3d2cd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2078384090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2078384090
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1535351398
Short name T107
Test name
Test status
Simulation time 336432030000 ps
CPU time 728.28 seconds
Started Jun 30 05:46:37 PM PDT 24
Finished Jun 30 06:16:31 PM PDT 24
Peak memory 160820 kb
Host smart-315366f6-692e-49fd-9f31-d481dde1a3d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1535351398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1535351398
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.3818893982
Short name T82
Test name
Test status
Simulation time 336730210000 ps
CPU time 758.43 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 06:17:22 PM PDT 24
Peak memory 160828 kb
Host smart-322194d9-eb8f-45c6-a4ed-a6ea56bdfc2a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3818893982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.3818893982
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1219058529
Short name T91
Test name
Test status
Simulation time 336711330000 ps
CPU time 874.45 seconds
Started Jun 30 05:46:43 PM PDT 24
Finished Jun 30 06:22:54 PM PDT 24
Peak memory 160824 kb
Host smart-d9b58516-23f0-40b1-8e1d-95dcbeb78a77
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219058529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1219058529
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1723114952
Short name T92
Test name
Test status
Simulation time 336383730000 ps
CPU time 793.14 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:18:57 PM PDT 24
Peak memory 160828 kb
Host smart-6b207a8d-e5c7-44e9-b365-867066e564d2
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1723114952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1723114952
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.1043387061
Short name T99
Test name
Test status
Simulation time 336945010000 ps
CPU time 985.25 seconds
Started Jun 30 05:46:36 PM PDT 24
Finished Jun 30 06:28:13 PM PDT 24
Peak memory 160824 kb
Host smart-957fa7ca-cdaf-4de0-b33c-609b780a1474
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1043387061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.1043387061
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3466887505
Short name T106
Test name
Test status
Simulation time 336922410000 ps
CPU time 983.35 seconds
Started Jun 30 05:46:36 PM PDT 24
Finished Jun 30 06:28:13 PM PDT 24
Peak memory 160824 kb
Host smart-59ca4d9f-3276-4434-98e6-e6590f25dadb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3466887505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3466887505
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1430082052
Short name T6
Test name
Test status
Simulation time 336477350000 ps
CPU time 988.12 seconds
Started Jun 30 05:46:31 PM PDT 24
Finished Jun 30 06:27:32 PM PDT 24
Peak memory 160816 kb
Host smart-fab1b2af-3b28-4abd-ba9f-dac08334025a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1430082052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1430082052
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1014630315
Short name T74
Test name
Test status
Simulation time 337057850000 ps
CPU time 830.83 seconds
Started Jun 30 05:46:32 PM PDT 24
Finished Jun 30 06:19:49 PM PDT 24
Peak memory 160820 kb
Host smart-bc2626f6-d326-4c71-96e2-8ea7411d36cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1014630315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1014630315
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1537201362
Short name T103
Test name
Test status
Simulation time 336708890000 ps
CPU time 867.05 seconds
Started Jun 30 05:46:33 PM PDT 24
Finished Jun 30 06:22:12 PM PDT 24
Peak memory 160676 kb
Host smart-56e37805-893c-4498-bb6a-98b697f6f73d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1537201362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1537201362
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.1242050288
Short name T195
Test name
Test status
Simulation time 336497910000 ps
CPU time 875.61 seconds
Started Jun 30 05:51:11 PM PDT 24
Finished Jun 30 06:26:25 PM PDT 24
Peak memory 160816 kb
Host smart-6edbd07a-c9de-459c-b7b8-40cf6bbbb249
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1242050288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.1242050288
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1629166402
Short name T182
Test name
Test status
Simulation time 336399290000 ps
CPU time 731.52 seconds
Started Jun 30 05:51:11 PM PDT 24
Finished Jun 30 06:21:06 PM PDT 24
Peak memory 160824 kb
Host smart-b940bb2e-a4c6-4671-835b-2762941bb419
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1629166402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1629166402
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2256187251
Short name T166
Test name
Test status
Simulation time 336857030000 ps
CPU time 823.8 seconds
Started Jun 30 05:51:09 PM PDT 24
Finished Jun 30 06:24:58 PM PDT 24
Peak memory 160828 kb
Host smart-37552690-7cc6-4914-9895-8c6c618969e5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2256187251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2256187251
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.1310206789
Short name T180
Test name
Test status
Simulation time 336655330000 ps
CPU time 849.53 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:26:54 PM PDT 24
Peak memory 160788 kb
Host smart-e4d7e69a-3dcf-4b84-a306-0284f4c1d6ae
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1310206789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.1310206789
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1569737284
Short name T183
Test name
Test status
Simulation time 336767290000 ps
CPU time 778.83 seconds
Started Jun 30 05:51:09 PM PDT 24
Finished Jun 30 06:22:24 PM PDT 24
Peak memory 160784 kb
Host smart-fbe87fe0-9da2-494e-9f8a-784e69eaefac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1569737284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1569737284
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2962333803
Short name T188
Test name
Test status
Simulation time 337032830000 ps
CPU time 733 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:20:50 PM PDT 24
Peak memory 160808 kb
Host smart-9f274662-493e-41cf-8870-3a7c8444f3b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2962333803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2962333803
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3010004494
Short name T22
Test name
Test status
Simulation time 336369970000 ps
CPU time 700.25 seconds
Started Jun 30 05:51:11 PM PDT 24
Finished Jun 30 06:19:51 PM PDT 24
Peak memory 160840 kb
Host smart-0a515893-5fc7-45f6-a21f-c97c8d1c69a4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3010004494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3010004494
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2873545599
Short name T28
Test name
Test status
Simulation time 336758670000 ps
CPU time 817.87 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:24:53 PM PDT 24
Peak memory 160824 kb
Host smart-51935276-de07-419b-b9c7-bf18d30023a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2873545599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2873545599
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3516525722
Short name T169
Test name
Test status
Simulation time 336851850000 ps
CPU time 880.85 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:26:28 PM PDT 24
Peak memory 160804 kb
Host smart-73ab8376-0d96-4dbc-971b-e06c944c58ef
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3516525722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3516525722
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2782326666
Short name T192
Test name
Test status
Simulation time 336605370000 ps
CPU time 738.1 seconds
Started Jun 30 05:51:11 PM PDT 24
Finished Jun 30 06:21:13 PM PDT 24
Peak memory 160828 kb
Host smart-3c5b287d-724c-47a4-a859-4838e6e1c23a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2782326666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2782326666
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1091334999
Short name T29
Test name
Test status
Simulation time 336758350000 ps
CPU time 952.54 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:31:11 PM PDT 24
Peak memory 160836 kb
Host smart-179782ea-b22d-47b0-b20f-1705e269bb32
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1091334999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1091334999
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3041249050
Short name T162
Test name
Test status
Simulation time 336904970000 ps
CPU time 903.33 seconds
Started Jun 30 05:51:13 PM PDT 24
Finished Jun 30 06:29:05 PM PDT 24
Peak memory 160812 kb
Host smart-a49f4a85-79a3-4a0e-aa98-a7e515811177
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3041249050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3041249050
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.817341177
Short name T167
Test name
Test status
Simulation time 336706030000 ps
CPU time 745.93 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:21:17 PM PDT 24
Peak memory 160832 kb
Host smart-1d25c119-59df-4815-a8c8-5baac6568f12
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=817341177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.817341177
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3737532439
Short name T27
Test name
Test status
Simulation time 336742470000 ps
CPU time 853.65 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:26:01 PM PDT 24
Peak memory 160828 kb
Host smart-32a7853f-ac2c-48da-bc7e-5ca0a08b64d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3737532439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3737532439
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.827713414
Short name T164
Test name
Test status
Simulation time 337043470000 ps
CPU time 776.93 seconds
Started Jun 30 05:51:11 PM PDT 24
Finished Jun 30 06:22:51 PM PDT 24
Peak memory 160820 kb
Host smart-55575eb2-c74c-4fad-8a05-54a0ea07c7a6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=827713414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.827713414
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2523180324
Short name T172
Test name
Test status
Simulation time 336508830000 ps
CPU time 823.78 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:23:46 PM PDT 24
Peak memory 160828 kb
Host smart-a0e17a49-fd0b-4c39-b21d-c7ca4f68bbfe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2523180324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2523180324
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3660705867
Short name T197
Test name
Test status
Simulation time 336380550000 ps
CPU time 907.16 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:28:55 PM PDT 24
Peak memory 160800 kb
Host smart-7daa7ff4-3e53-478c-9a3f-3cefad02f22a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3660705867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3660705867
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.520151733
Short name T23
Test name
Test status
Simulation time 337045710000 ps
CPU time 907.19 seconds
Started Jun 30 05:51:13 PM PDT 24
Finished Jun 30 06:29:03 PM PDT 24
Peak memory 160812 kb
Host smart-072c6880-6436-444c-9490-5a1721df85b6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=520151733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.520151733
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.2304114970
Short name T176
Test name
Test status
Simulation time 336960230000 ps
CPU time 742.07 seconds
Started Jun 30 05:51:17 PM PDT 24
Finished Jun 30 06:21:45 PM PDT 24
Peak memory 160828 kb
Host smart-e4d4bb8e-3123-4158-8909-9217e8fb8937
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2304114970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.2304114970
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1104144135
Short name T178
Test name
Test status
Simulation time 336425130000 ps
CPU time 778.57 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:23:25 PM PDT 24
Peak memory 160780 kb
Host smart-7d61c267-92bf-45a2-8f20-202a0c672bff
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1104144135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1104144135
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1473579224
Short name T161
Test name
Test status
Simulation time 336868570000 ps
CPU time 773.43 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:23:17 PM PDT 24
Peak memory 160760 kb
Host smart-6884f6b1-4c48-4030-a92e-62a8a254a495
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1473579224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1473579224
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2658073962
Short name T163
Test name
Test status
Simulation time 336748910000 ps
CPU time 845.53 seconds
Started Jun 30 05:51:16 PM PDT 24
Finished Jun 30 06:26:48 PM PDT 24
Peak memory 160936 kb
Host smart-e36170ee-5096-4f08-8cc1-6c7c5a9d74fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2658073962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2658073962
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.730477730
Short name T30
Test name
Test status
Simulation time 336559610000 ps
CPU time 704.91 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:20:41 PM PDT 24
Peak memory 160820 kb
Host smart-0cbd7779-48c8-4445-9f41-42feb735242a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=730477730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.730477730
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1053532084
Short name T196
Test name
Test status
Simulation time 336763650000 ps
CPU time 524.53 seconds
Started Jun 30 05:51:17 PM PDT 24
Finished Jun 30 06:13:33 PM PDT 24
Peak memory 160832 kb
Host smart-b7fb19ba-23af-4fff-8992-aa53997c725c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1053532084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1053532084
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1213460651
Short name T194
Test name
Test status
Simulation time 337053430000 ps
CPU time 873.93 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:27:06 PM PDT 24
Peak memory 160776 kb
Host smart-e36c6945-2d34-41ca-bc94-84d96fb48b77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1213460651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1213460651
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2800732191
Short name T198
Test name
Test status
Simulation time 337131070000 ps
CPU time 768.5 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:22:15 PM PDT 24
Peak memory 160784 kb
Host smart-3ab751b1-4bcc-46ea-8ff6-2073a87870f3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2800732191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2800732191
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.755582893
Short name T173
Test name
Test status
Simulation time 336957470000 ps
CPU time 908.72 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:29:13 PM PDT 24
Peak memory 160812 kb
Host smart-f551bd91-a5cc-4de1-aa10-bed286011a07
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=755582893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.755582893
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3526702132
Short name T170
Test name
Test status
Simulation time 336385250000 ps
CPU time 875.79 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:27:04 PM PDT 24
Peak memory 160776 kb
Host smart-e90b3c9f-a3b6-45e2-b3b0-d1824a55c5fd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3526702132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.3526702132
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4084985895
Short name T21
Test name
Test status
Simulation time 336630130000 ps
CPU time 784.93 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:23:31 PM PDT 24
Peak memory 160828 kb
Host smart-9d7a8c82-4a63-4e10-a5b9-f07a76247dd6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4084985895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.4084985895
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1650431737
Short name T24
Test name
Test status
Simulation time 336703370000 ps
CPU time 805.14 seconds
Started Jun 30 05:51:20 PM PDT 24
Finished Jun 30 06:24:28 PM PDT 24
Peak memory 160816 kb
Host smart-a84e5139-2179-4d54-96a6-b3c8d4e669a1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1650431737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1650431737
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2584784961
Short name T185
Test name
Test status
Simulation time 336397850000 ps
CPU time 864.62 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:27:15 PM PDT 24
Peak memory 160852 kb
Host smart-68a90c47-8dae-4971-95fa-75ed9360d6fa
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2584784961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2584784961
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2447714194
Short name T187
Test name
Test status
Simulation time 336915330000 ps
CPU time 817.1 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:24:37 PM PDT 24
Peak memory 160832 kb
Host smart-1ddc29fc-40b7-478d-8d0b-7c61828a7229
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2447714194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2447714194
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1851183458
Short name T181
Test name
Test status
Simulation time 336676370000 ps
CPU time 819.32 seconds
Started Jun 30 05:51:20 PM PDT 24
Finished Jun 30 06:25:12 PM PDT 24
Peak memory 160824 kb
Host smart-6759e4a3-ea29-4c48-9d6b-4f02337f7e88
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1851183458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1851183458
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2811706084
Short name T174
Test name
Test status
Simulation time 336967750000 ps
CPU time 848.61 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:26:47 PM PDT 24
Peak memory 160780 kb
Host smart-35804bfa-82e3-4318-ac96-1e278dcd7fd8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2811706084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2811706084
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1845530428
Short name T191
Test name
Test status
Simulation time 336642370000 ps
CPU time 858.81 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:25:39 PM PDT 24
Peak memory 160824 kb
Host smart-3744405b-263f-47c0-859f-affac2155763
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1845530428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1845530428
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1040824252
Short name T179
Test name
Test status
Simulation time 336533890000 ps
CPU time 827.17 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:25:32 PM PDT 24
Peak memory 160840 kb
Host smart-e3d31a79-47b1-442d-b648-67745bb12152
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1040824252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1040824252
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2090867783
Short name T200
Test name
Test status
Simulation time 337076970000 ps
CPU time 735.8 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:21:20 PM PDT 24
Peak memory 160828 kb
Host smart-5be94ad7-e3c5-4c3b-8a98-d37583194771
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2090867783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2090867783
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.254953866
Short name T189
Test name
Test status
Simulation time 336952610000 ps
CPU time 841.17 seconds
Started Jun 30 05:51:18 PM PDT 24
Finished Jun 30 06:25:10 PM PDT 24
Peak memory 160816 kb
Host smart-cd32841a-4c60-4b32-a9c4-47df20901043
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=254953866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.254953866
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.588875128
Short name T190
Test name
Test status
Simulation time 336358050000 ps
CPU time 785.22 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:24:04 PM PDT 24
Peak memory 160820 kb
Host smart-64dc04e5-c37e-45f3-b59a-475de0b5a3a0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=588875128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.588875128
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3908863308
Short name T175
Test name
Test status
Simulation time 336490830000 ps
CPU time 819.08 seconds
Started Jun 30 05:51:19 PM PDT 24
Finished Jun 30 06:24:36 PM PDT 24
Peak memory 160816 kb
Host smart-33da685d-ca24-4784-afbe-027cceaa67eb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3908863308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.3908863308
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3571144438
Short name T171
Test name
Test status
Simulation time 336688450000 ps
CPU time 825.72 seconds
Started Jun 30 05:51:17 PM PDT 24
Finished Jun 30 06:24:17 PM PDT 24
Peak memory 160788 kb
Host smart-d8fa721a-1686-4936-a5ab-7590c11aa0e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3571144438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3571144438
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1727919700
Short name T177
Test name
Test status
Simulation time 337115690000 ps
CPU time 908.57 seconds
Started Jun 30 05:51:27 PM PDT 24
Finished Jun 30 06:29:28 PM PDT 24
Peak memory 160820 kb
Host smart-234e9f1a-e5cc-4c7c-a708-1cb7cf85e544
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1727919700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1727919700
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1717219408
Short name T26
Test name
Test status
Simulation time 337055010000 ps
CPU time 907.95 seconds
Started Jun 30 05:51:27 PM PDT 24
Finished Jun 30 06:29:07 PM PDT 24
Peak memory 160800 kb
Host smart-2a007218-1f3b-4258-92f8-939e9016ca23
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1717219408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1717219408
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2808897936
Short name T199
Test name
Test status
Simulation time 336791530000 ps
CPU time 927.09 seconds
Started Jun 30 05:51:27 PM PDT 24
Finished Jun 30 06:28:33 PM PDT 24
Peak memory 160832 kb
Host smart-1a64507b-0798-4189-8b40-b9f9783c38b8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2808897936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2808897936
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2767497254
Short name T165
Test name
Test status
Simulation time 337169750000 ps
CPU time 832.54 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:25:27 PM PDT 24
Peak memory 160832 kb
Host smart-fa7c62eb-e326-4e71-8dd0-fbeb0e6f8f3b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2767497254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.2767497254
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1600431680
Short name T184
Test name
Test status
Simulation time 337116350000 ps
CPU time 758.03 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:22:03 PM PDT 24
Peak memory 160804 kb
Host smart-4f8f8ba2-c272-42d3-9c68-ffb6a275bfe9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1600431680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1600431680
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.1680578040
Short name T168
Test name
Test status
Simulation time 336440530000 ps
CPU time 867.72 seconds
Started Jun 30 05:51:10 PM PDT 24
Finished Jun 30 06:27:13 PM PDT 24
Peak memory 160840 kb
Host smart-31e49422-9d5e-4ccb-b687-6dea1eead16d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1680578040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.1680578040
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3238990844
Short name T193
Test name
Test status
Simulation time 336442910000 ps
CPU time 861.27 seconds
Started Jun 30 05:51:13 PM PDT 24
Finished Jun 30 06:26:27 PM PDT 24
Peak memory 160812 kb
Host smart-0f811f12-c904-4450-a18a-a1fd91e73e29
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3238990844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3238990844
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2085792372
Short name T186
Test name
Test status
Simulation time 336620910000 ps
CPU time 803.16 seconds
Started Jun 30 05:51:12 PM PDT 24
Finished Jun 30 06:23:16 PM PDT 24
Peak memory 160820 kb
Host smart-19e8b29e-5fe9-4a94-a237-c5f1153321d1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2085792372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2085792372
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.1904141063
Short name T138
Test name
Test status
Simulation time 1385150000 ps
CPU time 3.86 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:25 PM PDT 24
Peak memory 164892 kb
Host smart-d989c841-09fa-4c4d-b3da-16c480ef3279
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1904141063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.1904141063
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4019142305
Short name T140
Test name
Test status
Simulation time 1294270000 ps
CPU time 4.33 seconds
Started Jun 30 05:47:24 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164936 kb
Host smart-8696e97c-9337-4bc8-a786-5f7e3a55c4b8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4019142305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.4019142305
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4247559495
Short name T122
Test name
Test status
Simulation time 1279470000 ps
CPU time 5.03 seconds
Started Jun 30 05:47:26 PM PDT 24
Finished Jun 30 05:47:38 PM PDT 24
Peak memory 164956 kb
Host smart-b83b64d4-514f-482f-9330-9b59c189921f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4247559495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4247559495
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2376648830
Short name T127
Test name
Test status
Simulation time 1194350000 ps
CPU time 4.64 seconds
Started Jun 30 05:47:24 PM PDT 24
Finished Jun 30 05:47:34 PM PDT 24
Peak memory 164936 kb
Host smart-aec46399-0dd3-4843-8a5b-aece231de8e6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2376648830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2376648830
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2328278228
Short name T157
Test name
Test status
Simulation time 1167710000 ps
CPU time 4.52 seconds
Started Jun 30 05:47:25 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 164956 kb
Host smart-70d60a0c-9cd3-43d9-989a-1bd52da80f82
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328278228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.2328278228
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.703459312
Short name T149
Test name
Test status
Simulation time 1438290000 ps
CPU time 5.47 seconds
Started Jun 30 05:47:22 PM PDT 24
Finished Jun 30 05:47:34 PM PDT 24
Peak memory 164956 kb
Host smart-8f0f0a87-9c89-4200-ba04-154f74fbe9b2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=703459312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.703459312
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3699468972
Short name T132
Test name
Test status
Simulation time 1507210000 ps
CPU time 4.38 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164948 kb
Host smart-e2535138-c940-413a-9057-a30d336a29e7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699468972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3699468972
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1142945311
Short name T117
Test name
Test status
Simulation time 1547490000 ps
CPU time 3.4 seconds
Started Jun 30 05:47:27 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 164948 kb
Host smart-85c634ab-f64a-410b-9005-96f7eadb4bfe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1142945311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1142945311
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.35915271
Short name T151
Test name
Test status
Simulation time 1496770000 ps
CPU time 4.87 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:32 PM PDT 24
Peak memory 164864 kb
Host smart-2246f546-c5b8-4f98-b4da-b12325a79db2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35915271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.35915271
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1123004703
Short name T124
Test name
Test status
Simulation time 1538750000 ps
CPU time 7.16 seconds
Started Jun 30 05:47:27 PM PDT 24
Finished Jun 30 05:47:43 PM PDT 24
Peak memory 164944 kb
Host smart-e2978c03-5caf-4e85-a2b9-cf9f1cef6059
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1123004703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.1123004703
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1436359989
Short name T114
Test name
Test status
Simulation time 1408810000 ps
CPU time 4.25 seconds
Started Jun 30 05:47:29 PM PDT 24
Finished Jun 30 05:47:39 PM PDT 24
Peak memory 164920 kb
Host smart-e78c6aa0-83c9-4625-a3d7-8ad41bc8f59a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1436359989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1436359989
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3514454867
Short name T113
Test name
Test status
Simulation time 1395070000 ps
CPU time 4.51 seconds
Started Jun 30 05:47:26 PM PDT 24
Finished Jun 30 05:47:36 PM PDT 24
Peak memory 164944 kb
Host smart-148a0285-af5e-4682-af4e-729311c3b4ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3514454867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3514454867
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1637103964
Short name T119
Test name
Test status
Simulation time 1584090000 ps
CPU time 5.12 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 164960 kb
Host smart-aff58277-43e9-4483-93a7-4f890856b22f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1637103964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1637103964
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2316479735
Short name T115
Test name
Test status
Simulation time 1458930000 ps
CPU time 3.89 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:32 PM PDT 24
Peak memory 164964 kb
Host smart-d7392cb6-a964-4b7f-b7b9-95256b123c1d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2316479735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2316479735
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.4237302961
Short name T130
Test name
Test status
Simulation time 1433770000 ps
CPU time 4.89 seconds
Started Jun 30 05:47:29 PM PDT 24
Finished Jun 30 05:47:40 PM PDT 24
Peak memory 164960 kb
Host smart-b6afd6ab-20e1-4653-8db6-9e754226d90d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4237302961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.4237302961
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2311844091
Short name T116
Test name
Test status
Simulation time 1631830000 ps
CPU time 5.24 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:40 PM PDT 24
Peak memory 164932 kb
Host smart-17360a7b-5168-451c-a8f0-74efcf7d5f02
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2311844091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2311844091
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.649445947
Short name T129
Test name
Test status
Simulation time 1266110000 ps
CPU time 4.1 seconds
Started Jun 30 05:47:30 PM PDT 24
Finished Jun 30 05:47:39 PM PDT 24
Peak memory 164964 kb
Host smart-8367891e-4c6e-4977-8684-3d41d1891dab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=649445947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.649445947
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.954838753
Short name T141
Test name
Test status
Simulation time 1488190000 ps
CPU time 3.93 seconds
Started Jun 30 05:47:30 PM PDT 24
Finished Jun 30 05:47:39 PM PDT 24
Peak memory 164916 kb
Host smart-2beb9e09-67a8-431c-9584-0d522954330c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=954838753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.954838753
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1040189355
Short name T126
Test name
Test status
Simulation time 1349790000 ps
CPU time 4.32 seconds
Started Jun 30 05:47:30 PM PDT 24
Finished Jun 30 05:47:40 PM PDT 24
Peak memory 164936 kb
Host smart-62bd4db6-dafb-4b17-a0d5-73d42115a829
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1040189355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1040189355
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1163298497
Short name T139
Test name
Test status
Simulation time 1557130000 ps
CPU time 4.73 seconds
Started Jun 30 05:47:29 PM PDT 24
Finished Jun 30 05:47:40 PM PDT 24
Peak memory 164904 kb
Host smart-5becd237-c3dd-4fe5-a511-86a3f3a1892d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1163298497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1163298497
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3044247472
Short name T134
Test name
Test status
Simulation time 1260650000 ps
CPU time 4.35 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:38 PM PDT 24
Peak memory 164940 kb
Host smart-a9a1fd4a-efc8-4c05-809b-e8469b64dc39
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3044247472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.3044247472
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3728605444
Short name T160
Test name
Test status
Simulation time 1557150000 ps
CPU time 4.54 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:39 PM PDT 24
Peak memory 164960 kb
Host smart-d4d1196f-9710-4104-a8b5-e90f59e2b404
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3728605444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3728605444
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1044181217
Short name T142
Test name
Test status
Simulation time 1168190000 ps
CPU time 3.48 seconds
Started Jun 30 05:47:31 PM PDT 24
Finished Jun 30 05:47:39 PM PDT 24
Peak memory 164880 kb
Host smart-07a7f35c-ccb8-4542-8113-3b6864f25d6a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1044181217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1044181217
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.662310346
Short name T131
Test name
Test status
Simulation time 1557750000 ps
CPU time 4.2 seconds
Started Jun 30 05:47:25 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 164888 kb
Host smart-b74c1970-254a-415f-a506-107418201400
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=662310346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.662310346
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.801201954
Short name T152
Test name
Test status
Simulation time 1517270000 ps
CPU time 4.12 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:38 PM PDT 24
Peak memory 164980 kb
Host smart-4848bd7c-b3af-47d2-80f6-4d1bba56b522
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=801201954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.801201954
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.480857549
Short name T128
Test name
Test status
Simulation time 1391550000 ps
CPU time 4.4 seconds
Started Jun 30 05:47:30 PM PDT 24
Finished Jun 30 05:47:40 PM PDT 24
Peak memory 164964 kb
Host smart-d6f51c26-3226-4985-a2b3-a9b14403ab74
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=480857549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.480857549
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.2267038423
Short name T125
Test name
Test status
Simulation time 1128750000 ps
CPU time 3.91 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:37 PM PDT 24
Peak memory 164928 kb
Host smart-2d6cec4b-55d0-40da-8e5d-ff4ef6bd1b65
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2267038423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.2267038423
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2512378336
Short name T156
Test name
Test status
Simulation time 1436210000 ps
CPU time 3.1 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:36 PM PDT 24
Peak memory 164892 kb
Host smart-94c2f4a4-128e-46cf-802c-c28392299755
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512378336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2512378336
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.701895975
Short name T145
Test name
Test status
Simulation time 1166210000 ps
CPU time 3.4 seconds
Started Jun 30 05:47:35 PM PDT 24
Finished Jun 30 05:47:43 PM PDT 24
Peak memory 164928 kb
Host smart-938e6b67-be48-4bc5-b3e3-b6a2d48aa701
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=701895975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.701895975
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.205497680
Short name T135
Test name
Test status
Simulation time 1260430000 ps
CPU time 5.25 seconds
Started Jun 30 05:47:36 PM PDT 24
Finished Jun 30 05:47:47 PM PDT 24
Peak memory 164936 kb
Host smart-65ee8577-5449-4499-bd24-29c49d61fd9f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=205497680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.205497680
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1310321563
Short name T155
Test name
Test status
Simulation time 1445090000 ps
CPU time 3.57 seconds
Started Jun 30 05:47:36 PM PDT 24
Finished Jun 30 05:47:44 PM PDT 24
Peak memory 164876 kb
Host smart-e3aea46b-8874-4d89-b916-272d4823c7fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1310321563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1310321563
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.4185255035
Short name T112
Test name
Test status
Simulation time 1264770000 ps
CPU time 4.26 seconds
Started Jun 30 05:47:36 PM PDT 24
Finished Jun 30 05:47:45 PM PDT 24
Peak memory 164928 kb
Host smart-14c0478d-2287-4d63-b219-e4403f327dce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185255035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.4185255035
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2875700714
Short name T147
Test name
Test status
Simulation time 1602450000 ps
CPU time 3.47 seconds
Started Jun 30 05:47:34 PM PDT 24
Finished Jun 30 05:47:42 PM PDT 24
Peak memory 164924 kb
Host smart-3b2a9f4d-2477-4724-9e72-62820b94b2ed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2875700714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2875700714
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1257901349
Short name T136
Test name
Test status
Simulation time 1453250000 ps
CPU time 4.34 seconds
Started Jun 30 05:47:34 PM PDT 24
Finished Jun 30 05:47:44 PM PDT 24
Peak memory 164964 kb
Host smart-11bb0414-5b87-4ade-a45c-75568f9ff627
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1257901349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1257901349
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3405404192
Short name T144
Test name
Test status
Simulation time 1442330000 ps
CPU time 4.56 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:34 PM PDT 24
Peak memory 164936 kb
Host smart-6950e2b3-d430-4c37-af64-78a9a88d18a0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3405404192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3405404192
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2583671420
Short name T120
Test name
Test status
Simulation time 1313890000 ps
CPU time 5.2 seconds
Started Jun 30 05:47:38 PM PDT 24
Finished Jun 30 05:47:49 PM PDT 24
Peak memory 164960 kb
Host smart-9c3d214c-9cc6-436b-8bd9-384b1889d40f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2583671420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2583671420
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2091454919
Short name T148
Test name
Test status
Simulation time 1564050000 ps
CPU time 4.06 seconds
Started Jun 30 05:47:36 PM PDT 24
Finished Jun 30 05:47:45 PM PDT 24
Peak memory 164920 kb
Host smart-69905552-32a5-46dd-b60b-503c880788fb
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2091454919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2091454919
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1861727269
Short name T133
Test name
Test status
Simulation time 1546210000 ps
CPU time 4.82 seconds
Started Jun 30 05:47:38 PM PDT 24
Finished Jun 30 05:47:49 PM PDT 24
Peak memory 164932 kb
Host smart-0cc5de9c-fcba-4c30-9c4c-e383525642fd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1861727269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1861727269
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1273343448
Short name T111
Test name
Test status
Simulation time 1556990000 ps
CPU time 4.57 seconds
Started Jun 30 05:47:36 PM PDT 24
Finished Jun 30 05:47:46 PM PDT 24
Peak memory 164984 kb
Host smart-2af15ff6-9442-4b8f-8f6a-89ef861a119b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273343448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1273343448
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2754342366
Short name T154
Test name
Test status
Simulation time 1497310000 ps
CPU time 4.76 seconds
Started Jun 30 05:47:35 PM PDT 24
Finished Jun 30 05:47:46 PM PDT 24
Peak memory 164924 kb
Host smart-c3666267-098e-477a-9105-6208265facd7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2754342366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2754342366
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2618748496
Short name T123
Test name
Test status
Simulation time 1516890000 ps
CPU time 3.44 seconds
Started Jun 30 05:47:34 PM PDT 24
Finished Jun 30 05:47:42 PM PDT 24
Peak memory 164908 kb
Host smart-f6beca5c-ddf9-4a3b-aacc-544e7c67c544
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2618748496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2618748496
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.426862888
Short name T159
Test name
Test status
Simulation time 1461810000 ps
CPU time 4.32 seconds
Started Jun 30 05:47:35 PM PDT 24
Finished Jun 30 05:47:45 PM PDT 24
Peak memory 164960 kb
Host smart-8a30451a-757a-4a02-bfc5-a76e85ce45ac
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=426862888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.426862888
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2755988124
Short name T137
Test name
Test status
Simulation time 1396030000 ps
CPU time 3.41 seconds
Started Jun 30 05:47:35 PM PDT 24
Finished Jun 30 05:47:43 PM PDT 24
Peak memory 164976 kb
Host smart-8b552e60-3b37-4465-a402-e9912634aad6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2755988124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2755988124
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.135772942
Short name T143
Test name
Test status
Simulation time 1410470000 ps
CPU time 4.84 seconds
Started Jun 30 05:47:34 PM PDT 24
Finished Jun 30 05:47:45 PM PDT 24
Peak memory 164944 kb
Host smart-52592a14-6abb-4163-856a-698f5d0f7a84
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=135772942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.135772942
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3839728204
Short name T158
Test name
Test status
Simulation time 1259190000 ps
CPU time 4.35 seconds
Started Jun 30 05:47:37 PM PDT 24
Finished Jun 30 05:47:46 PM PDT 24
Peak memory 164952 kb
Host smart-79f7e139-2483-43ca-a7f7-b74d6c7dcfbc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3839728204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.3839728204
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2015413462
Short name T121
Test name
Test status
Simulation time 1458470000 ps
CPU time 4.34 seconds
Started Jun 30 05:47:29 PM PDT 24
Finished Jun 30 05:47:39 PM PDT 24
Peak memory 164960 kb
Host smart-5acd3449-962a-477a-bf8e-559a0709b8b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015413462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2015413462
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1877477637
Short name T146
Test name
Test status
Simulation time 1407770000 ps
CPU time 3.83 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:32 PM PDT 24
Peak memory 164924 kb
Host smart-76ce5693-9b02-4b51-8d61-1528b5f74e7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877477637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1877477637
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.525665614
Short name T118
Test name
Test status
Simulation time 1292930000 ps
CPU time 3.82 seconds
Started Jun 30 05:47:28 PM PDT 24
Finished Jun 30 05:47:37 PM PDT 24
Peak memory 164844 kb
Host smart-1841f44d-1571-4645-9b6d-bcd7d15c1a28
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=525665614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.525665614
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.505910236
Short name T153
Test name
Test status
Simulation time 1553290000 ps
CPU time 4.13 seconds
Started Jun 30 05:47:24 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164888 kb
Host smart-ff22badb-450c-47e1-a233-ad5e9008ef41
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=505910236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.505910236
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3885115672
Short name T150
Test name
Test status
Simulation time 1468710000 ps
CPU time 2.99 seconds
Started Jun 30 05:47:26 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164960 kb
Host smart-f5e20016-f2d9-4a20-bbed-22b8672a2bb5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3885115672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3885115672
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.155386827
Short name T48
Test name
Test status
Simulation time 1327690000 ps
CPU time 3.74 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:25 PM PDT 24
Peak memory 164868 kb
Host smart-91b3bb57-7f9f-4cd4-abd6-e2cca8ef79cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=155386827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.155386827
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3730662393
Short name T32
Test name
Test status
Simulation time 1545030000 ps
CPU time 4.95 seconds
Started Jun 30 05:47:19 PM PDT 24
Finished Jun 30 05:47:30 PM PDT 24
Peak memory 164940 kb
Host smart-811247a0-c65e-499f-9855-e4a430eb3aea
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3730662393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3730662393
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.840593935
Short name T65
Test name
Test status
Simulation time 1522230000 ps
CPU time 4.72 seconds
Started Jun 30 05:47:18 PM PDT 24
Finished Jun 30 05:47:29 PM PDT 24
Peak memory 164936 kb
Host smart-6fecfd23-a564-4c97-95ca-46cc2d5f275f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840593935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.840593935
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.4099809097
Short name T9
Test name
Test status
Simulation time 1619450000 ps
CPU time 3.7 seconds
Started Jun 30 05:47:15 PM PDT 24
Finished Jun 30 05:47:24 PM PDT 24
Peak memory 164964 kb
Host smart-276f2399-8776-4970-a47a-a362425b33b4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4099809097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.4099809097
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.2682388722
Short name T66
Test name
Test status
Simulation time 1094790000 ps
CPU time 2.95 seconds
Started Jun 30 05:47:22 PM PDT 24
Finished Jun 30 05:47:29 PM PDT 24
Peak memory 164964 kb
Host smart-83f27190-4b68-444c-88bd-66b57d0e31ab
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2682388722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.2682388722
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3347976010
Short name T70
Test name
Test status
Simulation time 1518790000 ps
CPU time 5.56 seconds
Started Jun 30 05:47:17 PM PDT 24
Finished Jun 30 05:47:31 PM PDT 24
Peak memory 165064 kb
Host smart-30577033-0fb0-432d-92b8-5f6ba5cdcd1d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347976010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3347976010
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1498537103
Short name T7
Test name
Test status
Simulation time 1570310000 ps
CPU time 5.19 seconds
Started Jun 30 05:47:22 PM PDT 24
Finished Jun 30 05:47:34 PM PDT 24
Peak memory 164940 kb
Host smart-2dbb83cd-928c-4e0e-a395-a24821ebdf33
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1498537103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1498537103
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3058664679
Short name T40
Test name
Test status
Simulation time 1268150000 ps
CPU time 3.78 seconds
Started Jun 30 05:47:18 PM PDT 24
Finished Jun 30 05:47:27 PM PDT 24
Peak memory 164928 kb
Host smart-47e60c5b-a4b1-4198-b041-d901e3750bb2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3058664679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3058664679
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1055936561
Short name T39
Test name
Test status
Simulation time 1492790000 ps
CPU time 4.92 seconds
Started Jun 30 05:47:15 PM PDT 24
Finished Jun 30 05:47:27 PM PDT 24
Peak memory 164964 kb
Host smart-50d81ccd-536e-48a0-81d3-d17f02ae2a22
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1055936561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1055936561
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1661012946
Short name T34
Test name
Test status
Simulation time 1344890000 ps
CPU time 3.84 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:32 PM PDT 24
Peak memory 164932 kb
Host smart-b7dc5e71-4b1b-4a66-affe-e0f738052eba
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1661012946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1661012946
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3753528322
Short name T3
Test name
Test status
Simulation time 1492710000 ps
CPU time 3.93 seconds
Started Jun 30 05:47:17 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164924 kb
Host smart-d02efbf9-a280-419b-b8b9-6b55bf20921b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3753528322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3753528322
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1451456568
Short name T12
Test name
Test status
Simulation time 1483410000 ps
CPU time 3.52 seconds
Started Jun 30 05:47:20 PM PDT 24
Finished Jun 30 05:47:29 PM PDT 24
Peak memory 164964 kb
Host smart-ed3fb93c-cbda-4f6a-a93f-a0dc26189bdf
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1451456568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1451456568
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2638098918
Short name T51
Test name
Test status
Simulation time 1619470000 ps
CPU time 4.95 seconds
Started Jun 30 05:47:14 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164952 kb
Host smart-0bf0b024-de32-4aa1-9212-c5a8cf0b8a30
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2638098918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2638098918
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1508916414
Short name T63
Test name
Test status
Simulation time 1476770000 ps
CPU time 3.98 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:30 PM PDT 24
Peak memory 164964 kb
Host smart-3742ef77-a978-4a60-839c-097fc05b36f4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1508916414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1508916414
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2816020873
Short name T56
Test name
Test status
Simulation time 1408110000 ps
CPU time 4.86 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:32 PM PDT 24
Peak memory 164932 kb
Host smart-56f66d8a-150a-4a1f-b45d-2cd55d77908b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816020873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2816020873
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.4147376470
Short name T8
Test name
Test status
Simulation time 1418850000 ps
CPU time 3.24 seconds
Started Jun 30 05:47:18 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164876 kb
Host smart-44eba0a4-2252-4add-83f4-182788c97fee
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4147376470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.4147376470
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.746770695
Short name T49
Test name
Test status
Simulation time 1313630000 ps
CPU time 4.96 seconds
Started Jun 30 05:47:19 PM PDT 24
Finished Jun 30 05:47:30 PM PDT 24
Peak memory 164908 kb
Host smart-a041b0b2-45a2-4e33-b5ab-2ef5bb38428d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=746770695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.746770695
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.882445189
Short name T35
Test name
Test status
Simulation time 1494410000 ps
CPU time 4.66 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:32 PM PDT 24
Peak memory 164876 kb
Host smart-703cadfe-4958-4d8d-8488-11fa9f6619cb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=882445189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.882445189
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3316370386
Short name T69
Test name
Test status
Simulation time 1355910000 ps
CPU time 3.68 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164924 kb
Host smart-21ad79f1-d31c-492e-9517-b94322080683
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3316370386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3316370386
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3004090026
Short name T38
Test name
Test status
Simulation time 1585250000 ps
CPU time 5.12 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164968 kb
Host smart-9f9a50ae-7bb7-4439-a85f-a83867b84c55
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3004090026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3004090026
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2681674913
Short name T2
Test name
Test status
Simulation time 1439030000 ps
CPU time 3.85 seconds
Started Jun 30 05:47:20 PM PDT 24
Finished Jun 30 05:47:29 PM PDT 24
Peak memory 164964 kb
Host smart-180ae9fd-663c-455b-8dc6-ee0704cab4ce
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2681674913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.2681674913
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.928267621
Short name T59
Test name
Test status
Simulation time 1380490000 ps
CPU time 3.79 seconds
Started Jun 30 05:47:15 PM PDT 24
Finished Jun 30 05:47:24 PM PDT 24
Peak memory 164952 kb
Host smart-f1ba8703-5cad-4289-801b-cd01269faa9e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=928267621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.928267621
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.446829986
Short name T60
Test name
Test status
Simulation time 1427730000 ps
CPU time 3.66 seconds
Started Jun 30 05:47:18 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164880 kb
Host smart-edf796e2-f00d-42e9-ace1-5f0fa28cc407
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=446829986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.446829986
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.4154092320
Short name T36
Test name
Test status
Simulation time 1535190000 ps
CPU time 4.16 seconds
Started Jun 30 05:47:15 PM PDT 24
Finished Jun 30 05:47:25 PM PDT 24
Peak memory 164944 kb
Host smart-f7255c6b-6c29-4dc0-b427-a73b38529512
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4154092320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.4154092320
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2363804060
Short name T41
Test name
Test status
Simulation time 1398790000 ps
CPU time 4.61 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:28 PM PDT 24
Peak memory 164944 kb
Host smart-3ceeba3c-8251-49b6-8939-2510ebbd4877
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2363804060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2363804060
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4253519973
Short name T53
Test name
Test status
Simulation time 1460990000 ps
CPU time 3.53 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:29 PM PDT 24
Peak memory 164920 kb
Host smart-55f4c4c0-e7e6-4371-a125-d2c98c7b0492
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4253519973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4253519973
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3718055422
Short name T68
Test name
Test status
Simulation time 1669050000 ps
CPU time 5.53 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 164936 kb
Host smart-a512443d-8be3-4742-8576-3411bb4c8412
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3718055422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3718055422
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1232792672
Short name T64
Test name
Test status
Simulation time 1275270000 ps
CPU time 3.3 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:24 PM PDT 24
Peak memory 164964 kb
Host smart-6df944c1-0883-4c53-868d-ddebb697db21
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1232792672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1232792672
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1460638266
Short name T57
Test name
Test status
Simulation time 1080750000 ps
CPU time 3.4 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:31 PM PDT 24
Peak memory 164940 kb
Host smart-6181bf99-dab5-4b9d-a44a-31f9d59be231
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460638266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1460638266
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3223773396
Short name T43
Test name
Test status
Simulation time 1476390000 ps
CPU time 5.26 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:30 PM PDT 24
Peak memory 165064 kb
Host smart-2903d3b8-6ed6-4c02-a465-faf98127fa6b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223773396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.3223773396
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1573424934
Short name T58
Test name
Test status
Simulation time 1386110000 ps
CPU time 3.94 seconds
Started Jun 30 05:47:17 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164960 kb
Host smart-9b90e323-0c20-4ef9-9adc-c3eb541bb1a6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573424934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1573424934
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2242947867
Short name T46
Test name
Test status
Simulation time 1517470000 ps
CPU time 4.86 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:34 PM PDT 24
Peak memory 164956 kb
Host smart-defe707d-c329-47b3-a79a-54209fcb464d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2242947867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2242947867
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.352218818
Short name T52
Test name
Test status
Simulation time 1458530000 ps
CPU time 3.8 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164960 kb
Host smart-0d627c68-74d7-4493-afdc-d84fe76120ef
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=352218818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.352218818
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.123030939
Short name T37
Test name
Test status
Simulation time 1361710000 ps
CPU time 3.42 seconds
Started Jun 30 05:47:15 PM PDT 24
Finished Jun 30 05:47:23 PM PDT 24
Peak memory 164852 kb
Host smart-fabe1aed-afca-4535-b58f-721d40a1b92b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123030939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.123030939
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3648492391
Short name T31
Test name
Test status
Simulation time 1414310000 ps
CPU time 3.89 seconds
Started Jun 30 05:47:19 PM PDT 24
Finished Jun 30 05:47:28 PM PDT 24
Peak memory 164960 kb
Host smart-dfbdb695-fa60-4ef6-903c-11bc0b950794
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3648492391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3648492391
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.881659873
Short name T55
Test name
Test status
Simulation time 1589230000 ps
CPU time 4.63 seconds
Started Jun 30 05:47:20 PM PDT 24
Finished Jun 30 05:47:31 PM PDT 24
Peak memory 164980 kb
Host smart-7a16e1c4-5e4f-4b22-a570-a9c769643239
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881659873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.881659873
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.746383929
Short name T10
Test name
Test status
Simulation time 1560370000 ps
CPU time 4.97 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164964 kb
Host smart-a7ec5d31-0897-4b5a-8477-c10539c12b62
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=746383929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.746383929
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2984681306
Short name T61
Test name
Test status
Simulation time 1367530000 ps
CPU time 4.73 seconds
Started Jun 30 05:47:17 PM PDT 24
Finished Jun 30 05:47:28 PM PDT 24
Peak memory 164940 kb
Host smart-b2ac4294-cd75-41c4-80c0-ed94bdda6f02
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984681306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2984681306
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2961645471
Short name T11
Test name
Test status
Simulation time 1527210000 ps
CPU time 4.45 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:31 PM PDT 24
Peak memory 164984 kb
Host smart-a7c38974-ef2d-4ce8-9101-9eca24dde709
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2961645471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2961645471
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2747003820
Short name T33
Test name
Test status
Simulation time 1464850000 ps
CPU time 4.91 seconds
Started Jun 30 05:47:16 PM PDT 24
Finished Jun 30 05:47:27 PM PDT 24
Peak memory 164936 kb
Host smart-b75b35e9-2d63-426a-a412-4e1dacecaf8f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2747003820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2747003820
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.1064136495
Short name T45
Test name
Test status
Simulation time 1507450000 ps
CPU time 5.56 seconds
Started Jun 30 05:47:22 PM PDT 24
Finished Jun 30 05:47:35 PM PDT 24
Peak memory 164932 kb
Host smart-b6ae9547-0b1e-4ee3-b61e-b9d9ce30784f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1064136495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.1064136495
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3187428954
Short name T44
Test name
Test status
Simulation time 1402270000 ps
CPU time 4.75 seconds
Started Jun 30 05:47:15 PM PDT 24
Finished Jun 30 05:47:26 PM PDT 24
Peak memory 164948 kb
Host smart-e5230af3-0c37-4563-a879-672c091f72ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187428954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3187428954
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.257363576
Short name T54
Test name
Test status
Simulation time 1302690000 ps
CPU time 4.14 seconds
Started Jun 30 05:47:23 PM PDT 24
Finished Jun 30 05:47:33 PM PDT 24
Peak memory 164936 kb
Host smart-a55899e6-415a-4bbe-bd5a-89832a0763de
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=257363576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.257363576
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.1498455860
Short name T67
Test name
Test status
Simulation time 1446290000 ps
CPU time 4.31 seconds
Started Jun 30 05:47:18 PM PDT 24
Finished Jun 30 05:47:28 PM PDT 24
Peak memory 164936 kb
Host smart-0230fe58-08d5-4316-a097-591c5dbfcc78
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1498455860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.1498455860
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1434744402
Short name T62
Test name
Test status
Simulation time 1171010000 ps
CPU time 2.89 seconds
Started Jun 30 05:47:19 PM PDT 24
Finished Jun 30 05:47:25 PM PDT 24
Peak memory 164968 kb
Host smart-106f5739-1a93-42c0-b5e3-b34f0645b92b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1434744402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1434744402
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.268055432
Short name T13
Test name
Test status
Simulation time 1152750000 ps
CPU time 3.96 seconds
Started Jun 30 05:47:21 PM PDT 24
Finished Jun 30 05:47:30 PM PDT 24
Peak memory 164864 kb
Host smart-1c3580ca-1143-42b0-8b62-8e7a03056e43
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=268055432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.268055432
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.3658074200
Short name T42
Test name
Test status
Simulation time 1453190000 ps
CPU time 3.52 seconds
Started Jun 30 05:47:19 PM PDT 24
Finished Jun 30 05:47:27 PM PDT 24
Peak memory 164968 kb
Host smart-b4f8bf3d-a864-4d78-85b5-9f8c1066d8fb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658074200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.3658074200
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3052579489
Short name T47
Test name
Test status
Simulation time 1324510000 ps
CPU time 2.89 seconds
Started Jun 30 05:47:09 PM PDT 24
Finished Jun 30 05:47:16 PM PDT 24
Peak memory 164964 kb
Host smart-9baf32ea-3c3d-48c8-9afb-fad3dd1077a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3052579489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3052579489
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1744054546
Short name T50
Test name
Test status
Simulation time 1214030000 ps
CPU time 2.93 seconds
Started Jun 30 05:47:18 PM PDT 24
Finished Jun 30 05:47:25 PM PDT 24
Peak memory 164968 kb
Host smart-3fb4fe4c-e977-45b3-9fba-a949ce23d15c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1744054546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.1744054546
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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