| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1774835452 | ||
| 96.81 | 9.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 47.50 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1224399705 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2013413301 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.93964069 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.316107357 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2770884383 |
| /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2240286768 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3779782344 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1965114865 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.250904726 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2132679813 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1636936328 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.314917519 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.638405482 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.577335210 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1726022347 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.254141734 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.5004339 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3411986398 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2377956191 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1943621972 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3900735796 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4241722291 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2216286876 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2701982925 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3630502189 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1332427137 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.737824935 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.259467243 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3841986167 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3468101027 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3470001397 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1651965305 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1845985262 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.779035643 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2319662518 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3639430649 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4140619350 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2776580688 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2321371123 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4281555739 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3311754290 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1148249325 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2510941620 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1657791366 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1896463573 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4089476007 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2063689874 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.678730005 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3183764090 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2402045190 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.118875849 |
| /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2899729478 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1293528279 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.613230848 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2908313786 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3163281128 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1156167262 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.714664281 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4204152701 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2859024640 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2463262060 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1759160417 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2587077842 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1067631147 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3219701369 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2398431807 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3997673144 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2821009184 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.846777871 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4141963751 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1555187105 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1165076720 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4067252007 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.987185452 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2305258711 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.178798303 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3571606987 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1273858544 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2232197 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1080799796 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2236049419 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2823209127 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2600457359 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1525706474 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2455264636 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2543943360 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1081180883 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.900195845 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1126597729 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.710101181 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2060642756 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3879972636 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3223251606 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.483267893 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.440178262 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4021272004 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2856165635 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4181734295 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2566991478 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1073723877 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.216668658 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4289928452 |
| /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4210928592 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2491665371 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1512956176 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2475749539 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1781266035 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2060391741 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1932364744 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3599827184 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3888107303 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1445539190 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.308199188 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3377817030 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2079451756 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3874845172 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1902900140 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.931300343 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2872777087 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4265884764 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4288084054 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1476293683 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3196322862 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4151047599 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2654239243 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3282994152 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4016766310 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2055343802 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.435783242 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.136469304 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3146990829 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1550174854 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3130737746 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.148063056 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3952387387 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2933355460 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2805495697 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2782616138 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1853024522 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2226166043 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2167785561 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4193508033 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2200196784 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.148133871 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2015462767 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3426795417 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1503950303 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2162428173 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4273502908 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3582981054 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2262888899 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3720855196 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1283801426 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.838947096 |
| /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1027595975 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3734529649 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3859793758 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1107429154 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1229269547 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2394990346 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.169570098 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1577605948 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4048173483 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3634302816 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1453358864 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1624858247 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1297941686 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3874170602 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1534949795 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3408419322 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1821712388 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3239594575 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.124438428 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1532427564 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1203494575 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1103793250 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1472319894 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3383175492 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2312892963 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.972256984 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1520228304 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4091046827 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.464189882 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1790363747 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.262388665 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1013932086 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.250494145 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3440168598 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3513879747 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.968149748 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.893284803 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3321433123 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1890224863 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.900162784 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3076382841 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.66585902 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1615193973 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.282167703 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4177533670 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1203494575 | Jul 01 10:27:45 AM PDT 24 | Jul 01 10:27:52 AM PDT 24 | 1213770000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.169570098 | Jul 01 10:24:07 AM PDT 24 | Jul 01 10:24:16 AM PDT 24 | 1478370000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.893284803 | Jul 01 10:23:34 AM PDT 24 | Jul 01 10:23:44 AM PDT 24 | 1543110000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.124438428 | Jul 01 10:27:57 AM PDT 24 | Jul 01 10:28:07 AM PDT 24 | 1575270000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1297941686 | Jul 01 10:28:05 AM PDT 24 | Jul 01 10:28:14 AM PDT 24 | 1407610000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1107429154 | Jul 01 10:24:58 AM PDT 24 | Jul 01 10:25:08 AM PDT 24 | 1258030000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4177533670 | Jul 01 10:27:45 AM PDT 24 | Jul 01 10:27:55 AM PDT 24 | 1524910000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1774835452 | Jul 01 10:23:47 AM PDT 24 | Jul 01 10:23:57 AM PDT 24 | 1370670000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3440168598 | Jul 01 10:26:06 AM PDT 24 | Jul 01 10:26:17 AM PDT 24 | 1484610000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3408419322 | Jul 01 10:27:57 AM PDT 24 | Jul 01 10:28:07 AM PDT 24 | 1600470000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1790363747 | Jul 01 10:28:01 AM PDT 24 | Jul 01 10:28:09 AM PDT 24 | 1474050000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3076382841 | Jul 01 10:27:56 AM PDT 24 | Jul 01 10:28:05 AM PDT 24 | 1407030000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1520228304 | Jul 01 10:27:45 AM PDT 24 | Jul 01 10:27:57 AM PDT 24 | 1524190000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3734529649 | Jul 01 10:28:05 AM PDT 24 | Jul 01 10:28:14 AM PDT 24 | 1463490000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2394990346 | Jul 01 10:24:39 AM PDT 24 | Jul 01 10:24:47 AM PDT 24 | 1480670000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1577605948 | Jul 01 10:23:18 AM PDT 24 | Jul 01 10:23:26 AM PDT 24 | 1281770000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3383175492 | Jul 01 10:28:01 AM PDT 24 | Jul 01 10:28:11 AM PDT 24 | 1529710000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3321433123 | Jul 01 10:28:02 AM PDT 24 | Jul 01 10:28:11 AM PDT 24 | 1558630000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1624858247 | Jul 01 10:28:05 AM PDT 24 | Jul 01 10:28:14 AM PDT 24 | 1301470000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1472319894 | Jul 01 10:28:17 AM PDT 24 | Jul 01 10:28:27 AM PDT 24 | 1572270000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1890224863 | Jul 01 10:22:46 AM PDT 24 | Jul 01 10:22:53 AM PDT 24 | 1221650000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1229269547 | Jul 01 10:23:47 AM PDT 24 | Jul 01 10:23:58 AM PDT 24 | 1497930000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4091046827 | Jul 01 10:28:17 AM PDT 24 | Jul 01 10:28:25 AM PDT 24 | 1173650000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3513879747 | Jul 01 10:23:03 AM PDT 24 | Jul 01 10:23:12 AM PDT 24 | 1567910000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2262888899 | Jul 01 10:23:59 AM PDT 24 | Jul 01 10:24:07 AM PDT 24 | 1529870000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1532427564 | Jul 01 10:27:45 AM PDT 24 | Jul 01 10:27:55 AM PDT 24 | 1311510000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.968149748 | Jul 01 10:28:15 AM PDT 24 | Jul 01 10:28:25 AM PDT 24 | 1553110000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2312892963 | Jul 01 10:29:42 AM PDT 24 | Jul 01 10:29:53 AM PDT 24 | 1559430000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3874170602 | Jul 01 10:27:34 AM PDT 24 | Jul 01 10:27:45 AM PDT 24 | 1540670000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.838947096 | Jul 01 10:23:47 AM PDT 24 | Jul 01 10:23:57 AM PDT 24 | 1453050000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3859793758 | Jul 01 10:28:05 AM PDT 24 | Jul 01 10:28:15 AM PDT 24 | 1402870000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.262388665 | Jul 01 10:28:02 AM PDT 24 | Jul 01 10:28:11 AM PDT 24 | 1502190000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1821712388 | Jul 01 10:23:21 AM PDT 24 | Jul 01 10:23:28 AM PDT 24 | 1385750000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1283801426 | Jul 01 10:22:35 AM PDT 24 | Jul 01 10:22:44 AM PDT 24 | 1573090000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.66585902 | Jul 01 10:28:16 AM PDT 24 | Jul 01 10:28:25 AM PDT 24 | 1272610000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.250494145 | Jul 01 10:22:49 AM PDT 24 | Jul 01 10:22:58 AM PDT 24 | 1502330000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1534949795 | Jul 01 10:27:33 AM PDT 24 | Jul 01 10:27:45 AM PDT 24 | 1618970000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3720855196 | Jul 01 10:27:39 AM PDT 24 | Jul 01 10:27:52 AM PDT 24 | 1563910000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1013932086 | Jul 01 10:23:20 AM PDT 24 | Jul 01 10:23:27 AM PDT 24 | 1339290000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.900162784 | Jul 01 10:24:05 AM PDT 24 | Jul 01 10:24:15 AM PDT 24 | 1533750000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4048173483 | Jul 01 10:27:33 AM PDT 24 | Jul 01 10:27:44 AM PDT 24 | 1470070000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.972256984 | Jul 01 10:26:19 AM PDT 24 | Jul 01 10:26:27 AM PDT 24 | 1417790000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1453358864 | Jul 01 10:23:47 AM PDT 24 | Jul 01 10:23:58 AM PDT 24 | 1464710000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1027595975 | Jul 01 10:23:47 AM PDT 24 | Jul 01 10:23:56 AM PDT 24 | 1282150000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3239594575 | Jul 01 10:27:46 AM PDT 24 | Jul 01 10:27:56 AM PDT 24 | 1470710000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1103793250 | Jul 01 10:28:01 AM PDT 24 | Jul 01 10:28:11 AM PDT 24 | 1443750000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.282167703 | Jul 01 10:23:18 AM PDT 24 | Jul 01 10:23:26 AM PDT 24 | 1305790000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1615193973 | Jul 01 10:28:04 AM PDT 24 | Jul 01 10:28:15 AM PDT 24 | 1546950000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.464189882 | Jul 01 10:23:38 AM PDT 24 | Jul 01 10:23:45 AM PDT 24 | 1250810000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3634302816 | Jul 01 10:27:46 AM PDT 24 | Jul 01 10:27:54 AM PDT 24 | 1526230000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1332427137 | Jul 01 10:35:12 AM PDT 24 | Jul 01 11:02:29 AM PDT 24 | 336632670000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1224399705 | Jul 01 10:34:55 AM PDT 24 | Jul 01 11:02:17 AM PDT 24 | 337095630000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2321371123 | Jul 01 10:34:58 AM PDT 24 | Jul 01 11:07:46 AM PDT 24 | 336485210000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.118875849 | Jul 01 10:34:52 AM PDT 24 | Jul 01 11:07:41 AM PDT 24 | 336479410000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3470001397 | Jul 01 10:35:06 AM PDT 24 | Jul 01 11:09:35 AM PDT 24 | 336425670000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2377956191 | Jul 01 10:35:06 AM PDT 24 | Jul 01 11:04:22 AM PDT 24 | 336764970000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2063689874 | Jul 01 10:35:03 AM PDT 24 | Jul 01 11:03:09 AM PDT 24 | 336560110000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3841986167 | Jul 01 10:35:04 AM PDT 24 | Jul 01 11:08:48 AM PDT 24 | 336732910000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2216286876 | Jul 01 10:35:04 AM PDT 24 | Jul 01 11:02:17 AM PDT 24 | 336380730000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.638405482 | Jul 01 10:35:02 AM PDT 24 | Jul 01 11:03:42 AM PDT 24 | 336581850000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3639430649 | Jul 01 10:35:14 AM PDT 24 | Jul 01 11:07:26 AM PDT 24 | 336499050000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1651965305 | Jul 01 10:35:03 AM PDT 24 | Jul 01 11:09:30 AM PDT 24 | 336573770000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.259467243 | Jul 01 10:35:08 AM PDT 24 | Jul 01 11:09:30 AM PDT 24 | 336807950000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1726022347 | Jul 01 10:35:01 AM PDT 24 | Jul 01 11:00:24 AM PDT 24 | 336359430000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2776580688 | Jul 01 10:35:01 AM PDT 24 | Jul 01 11:14:09 AM PDT 24 | 336431610000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1845985262 | Jul 01 10:35:05 AM PDT 24 | Jul 01 11:03:28 AM PDT 24 | 336782410000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3311754290 | Jul 01 10:35:04 AM PDT 24 | Jul 01 10:59:32 AM PDT 24 | 336438330000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.779035643 | Jul 01 10:35:02 AM PDT 24 | Jul 01 11:09:41 AM PDT 24 | 336838410000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.316107357 | Jul 01 10:35:03 AM PDT 24 | Jul 01 11:03:22 AM PDT 24 | 336580250000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.254141734 | Jul 01 10:34:56 AM PDT 24 | Jul 01 11:07:05 AM PDT 24 | 336885150000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.5004339 | Jul 01 10:34:59 AM PDT 24 | Jul 01 11:06:10 AM PDT 24 | 337046870000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.678730005 | Jul 01 10:35:04 AM PDT 24 | Jul 01 11:01:14 AM PDT 24 | 336411350000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1965114865 | Jul 01 10:35:08 AM PDT 24 | Jul 01 11:06:23 AM PDT 24 | 336932410000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4089476007 | Jul 01 10:34:58 AM PDT 24 | Jul 01 11:07:23 AM PDT 24 | 336574250000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3183764090 | Jul 01 10:35:06 AM PDT 24 | Jul 01 11:11:48 AM PDT 24 | 336675650000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1943621972 | Jul 01 10:35:06 AM PDT 24 | Jul 01 11:07:01 AM PDT 24 | 336866870000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2240286768 | Jul 01 10:34:49 AM PDT 24 | Jul 01 11:04:10 AM PDT 24 | 336922090000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2510941620 | Jul 01 10:35:07 AM PDT 24 | Jul 01 11:03:10 AM PDT 24 | 336851670000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1148249325 | Jul 01 10:35:05 AM PDT 24 | Jul 01 11:03:45 AM PDT 24 | 336451110000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.93964069 | Jul 01 10:35:05 AM PDT 24 | Jul 01 11:04:13 AM PDT 24 | 336503990000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1657791366 | Jul 01 10:35:07 AM PDT 24 | Jul 01 11:08:57 AM PDT 24 | 337135430000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4140619350 | Jul 01 10:35:04 AM PDT 24 | Jul 01 11:03:10 AM PDT 24 | 336722350000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.737824935 | Jul 01 10:35:04 AM PDT 24 | Jul 01 11:10:04 AM PDT 24 | 336912910000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3630502189 | Jul 01 10:34:55 AM PDT 24 | Jul 01 11:06:48 AM PDT 24 | 336695850000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3779782344 | Jul 01 10:35:08 AM PDT 24 | Jul 01 11:01:59 AM PDT 24 | 336709810000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2770884383 | Jul 01 10:34:57 AM PDT 24 | Jul 01 11:07:03 AM PDT 24 | 336600390000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1896463573 | Jul 01 10:35:08 AM PDT 24 | Jul 01 11:06:56 AM PDT 24 | 336498170000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2701982925 | Jul 01 10:35:01 AM PDT 24 | Jul 01 11:00:38 AM PDT 24 | 336746390000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1636936328 | Jul 01 10:35:10 AM PDT 24 | Jul 01 11:06:20 AM PDT 24 | 336577990000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.250904726 | Jul 01 10:35:00 AM PDT 24 | Jul 01 11:04:24 AM PDT 24 | 337078490000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2319662518 | Jul 01 10:35:09 AM PDT 24 | Jul 01 11:07:53 AM PDT 24 | 337104890000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4241722291 | Jul 01 10:35:09 AM PDT 24 | Jul 01 11:04:05 AM PDT 24 | 336486070000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3900735796 | Jul 01 10:34:57 AM PDT 24 | Jul 01 11:07:04 AM PDT 24 | 336506890000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.577335210 | Jul 01 10:34:53 AM PDT 24 | Jul 01 11:03:11 AM PDT 24 | 336752790000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3468101027 | Jul 01 10:35:02 AM PDT 24 | Jul 01 11:03:29 AM PDT 24 | 336433990000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4281555739 | Jul 01 10:35:36 AM PDT 24 | Jul 01 11:01:05 AM PDT 24 | 337097610000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.314917519 | Jul 01 10:35:00 AM PDT 24 | Jul 01 11:06:17 AM PDT 24 | 336730770000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2402045190 | Jul 01 10:35:03 AM PDT 24 | Jul 01 11:04:58 AM PDT 24 | 336787310000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2132679813 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:59:59 AM PDT 24 | 336921990000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3411986398 | Jul 01 10:35:09 AM PDT 24 | Jul 01 11:12:04 AM PDT 24 | 336413870000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.931300343 | Jul 01 10:35:40 AM PDT 24 | Jul 01 10:35:50 AM PDT 24 | 1519970000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2060391741 | Jul 01 10:35:28 AM PDT 24 | Jul 01 10:35:38 AM PDT 24 | 1513010000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1445539190 | Jul 01 10:35:34 AM PDT 24 | Jul 01 10:35:43 AM PDT 24 | 1416650000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2162428173 | Jul 01 10:35:37 AM PDT 24 | Jul 01 10:35:48 AM PDT 24 | 1443930000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1932364744 | Jul 01 10:35:18 AM PDT 24 | Jul 01 10:35:30 AM PDT 24 | 1455010000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4016766310 | Jul 01 10:35:17 AM PDT 24 | Jul 01 10:35:31 AM PDT 24 | 1342590000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1476293683 | Jul 01 10:35:48 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 1279890000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2805495697 | Jul 01 10:35:48 AM PDT 24 | Jul 01 10:35:59 AM PDT 24 | 1568570000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3146990829 | Jul 01 10:35:31 AM PDT 24 | Jul 01 10:35:38 AM PDT 24 | 1458050000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4289928452 | Jul 01 10:35:22 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 1534770000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3952387387 | Jul 01 10:35:48 AM PDT 24 | Jul 01 10:35:59 AM PDT 24 | 1073990000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4151047599 | Jul 01 10:37:16 AM PDT 24 | Jul 01 10:37:24 AM PDT 24 | 1512170000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2933355460 | Jul 01 10:35:51 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 1168250000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2079451756 | Jul 01 10:35:20 AM PDT 24 | Jul 01 10:35:31 AM PDT 24 | 1466490000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4193508033 | Jul 01 10:35:31 AM PDT 24 | Jul 01 10:35:41 AM PDT 24 | 1436730000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4210928592 | Jul 01 10:35:22 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 1531270000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3426795417 | Jul 01 10:35:47 AM PDT 24 | Jul 01 10:35:59 AM PDT 24 | 1473730000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.308199188 | Jul 01 10:35:16 AM PDT 24 | Jul 01 10:35:28 AM PDT 24 | 1478790000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2475749539 | Jul 01 10:35:15 AM PDT 24 | Jul 01 10:35:28 AM PDT 24 | 1468650000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.435783242 | Jul 01 10:35:18 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 1521170000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1512956176 | Jul 01 10:35:50 AM PDT 24 | Jul 01 10:36:04 AM PDT 24 | 1484690000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2491665371 | Jul 01 10:35:25 AM PDT 24 | Jul 01 10:35:37 AM PDT 24 | 1598150000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1902900140 | Jul 01 10:35:28 AM PDT 24 | Jul 01 10:35:38 AM PDT 24 | 1519210000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2654239243 | Jul 01 10:35:31 AM PDT 24 | Jul 01 10:35:41 AM PDT 24 | 1438510000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2015462767 | Jul 01 10:35:24 AM PDT 24 | Jul 01 10:35:33 AM PDT 24 | 1411910000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2872777087 | Jul 01 10:35:29 AM PDT 24 | Jul 01 10:35:39 AM PDT 24 | 1332870000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1550174854 | Jul 01 10:35:39 AM PDT 24 | Jul 01 10:35:47 AM PDT 24 | 1569710000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3582981054 | Jul 01 10:35:34 AM PDT 24 | Jul 01 10:35:44 AM PDT 24 | 1299910000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3599827184 | Jul 01 10:35:53 AM PDT 24 | Jul 01 10:36:05 AM PDT 24 | 1313190000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1781266035 | Jul 01 10:35:19 AM PDT 24 | Jul 01 10:35:31 AM PDT 24 | 1441870000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4265884764 | Jul 01 10:35:28 AM PDT 24 | Jul 01 10:35:40 AM PDT 24 | 1564410000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2055343802 | Jul 01 10:35:29 AM PDT 24 | Jul 01 10:35:38 AM PDT 24 | 1225450000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4273502908 | Jul 01 10:35:24 AM PDT 24 | Jul 01 10:35:33 AM PDT 24 | 1604410000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.148063056 | Jul 01 10:36:03 AM PDT 24 | Jul 01 10:36:18 AM PDT 24 | 1459250000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1503950303 | Jul 01 10:35:20 AM PDT 24 | Jul 01 10:35:30 AM PDT 24 | 1414550000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2167785561 | Jul 01 10:35:26 AM PDT 24 | Jul 01 10:35:35 AM PDT 24 | 1197710000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3874845172 | Jul 01 10:37:06 AM PDT 24 | Jul 01 10:37:15 AM PDT 24 | 1499150000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3377817030 | Jul 01 10:35:27 AM PDT 24 | Jul 01 10:35:38 AM PDT 24 | 1453170000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3282994152 | Jul 01 10:35:47 AM PDT 24 | Jul 01 10:35:57 AM PDT 24 | 1495510000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2226166043 | Jul 01 10:35:55 AM PDT 24 | Jul 01 10:36:06 AM PDT 24 | 1366770000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3130737746 | Jul 01 10:35:56 AM PDT 24 | Jul 01 10:36:07 AM PDT 24 | 1613270000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.216668658 | Jul 01 10:35:28 AM PDT 24 | Jul 01 10:35:39 AM PDT 24 | 1532010000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2782616138 | Jul 01 10:35:27 AM PDT 24 | Jul 01 10:35:36 AM PDT 24 | 1529230000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.148133871 | Jul 01 10:36:04 AM PDT 24 | Jul 01 10:36:14 AM PDT 24 | 1432090000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2200196784 | Jul 01 10:35:50 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 1437590000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1853024522 | Jul 01 10:35:18 AM PDT 24 | Jul 01 10:35:30 AM PDT 24 | 1365070000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3196322862 | Jul 01 10:35:18 AM PDT 24 | Jul 01 10:35:31 AM PDT 24 | 1576390000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4288084054 | Jul 01 10:35:30 AM PDT 24 | Jul 01 10:35:40 AM PDT 24 | 1332110000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3888107303 | Jul 01 10:35:16 AM PDT 24 | Jul 01 10:35:30 AM PDT 24 | 1362030000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.136469304 | Jul 01 10:36:00 AM PDT 24 | Jul 01 10:36:12 AM PDT 24 | 1171930000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1759160417 | Jul 01 10:35:53 AM PDT 24 | Jul 01 11:03:40 AM PDT 24 | 336618490000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2823209127 | Jul 01 10:35:39 AM PDT 24 | Jul 01 11:09:07 AM PDT 24 | 336354890000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4204152701 | Jul 01 10:35:35 AM PDT 24 | Jul 01 11:06:55 AM PDT 24 | 337030270000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1525706474 | Jul 01 10:35:43 AM PDT 24 | Jul 01 11:10:46 AM PDT 24 | 336531810000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2013413301 | Jul 01 10:35:55 AM PDT 24 | Jul 01 11:05:12 AM PDT 24 | 336682630000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2305258711 | Jul 01 10:35:41 AM PDT 24 | Jul 01 11:07:23 AM PDT 24 | 336842330000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3163281128 | Jul 01 10:35:25 AM PDT 24 | Jul 01 11:03:41 AM PDT 24 | 336737530000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3879972636 | Jul 01 10:35:47 AM PDT 24 | Jul 01 11:05:42 AM PDT 24 | 336400890000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.440178262 | Jul 01 10:35:33 AM PDT 24 | Jul 01 11:08:11 AM PDT 24 | 337025210000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4067252007 | Jul 01 10:35:28 AM PDT 24 | Jul 01 11:08:54 AM PDT 24 | 336942750000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2859024640 | Jul 01 10:35:21 AM PDT 24 | Jul 01 11:06:15 AM PDT 24 | 336649850000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3223251606 | Jul 01 10:35:48 AM PDT 24 | Jul 01 11:08:07 AM PDT 24 | 336749870000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2398431807 | Jul 01 10:35:29 AM PDT 24 | Jul 01 11:08:07 AM PDT 24 | 336721070000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.900195845 | Jul 01 10:35:30 AM PDT 24 | Jul 01 11:12:19 AM PDT 24 | 336815550000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1293528279 | Jul 01 10:35:49 AM PDT 24 | Jul 01 11:05:18 AM PDT 24 | 337183830000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1081180883 | Jul 01 10:35:16 AM PDT 24 | Jul 01 11:05:36 AM PDT 24 | 337097350000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2899729478 | Jul 01 10:35:26 AM PDT 24 | Jul 01 11:02:27 AM PDT 24 | 337137190000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.613230848 | Jul 01 10:35:46 AM PDT 24 | Jul 01 11:07:29 AM PDT 24 | 336411230000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3997673144 | Jul 01 10:35:22 AM PDT 24 | Jul 01 11:15:30 AM PDT 24 | 336859230000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2455264636 | Jul 01 10:35:58 AM PDT 24 | Jul 01 11:02:41 AM PDT 24 | 336726910000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4021272004 | Jul 01 10:35:36 AM PDT 24 | Jul 01 11:04:15 AM PDT 24 | 336621210000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1165076720 | Jul 01 10:35:29 AM PDT 24 | Jul 01 11:07:45 AM PDT 24 | 336591310000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1073723877 | Jul 01 10:35:24 AM PDT 24 | Jul 01 11:06:46 AM PDT 24 | 336804110000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2908313786 | Jul 01 10:35:55 AM PDT 24 | Jul 01 11:02:52 AM PDT 24 | 336372590000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2587077842 | Jul 01 10:35:58 AM PDT 24 | Jul 01 11:04:00 AM PDT 24 | 336907510000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1555187105 | Jul 01 10:35:30 AM PDT 24 | Jul 01 11:06:20 AM PDT 24 | 336668730000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.714664281 | Jul 01 10:35:28 AM PDT 24 | Jul 01 11:06:25 AM PDT 24 | 336647970000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1067631147 | Jul 01 10:35:26 AM PDT 24 | Jul 01 11:06:55 AM PDT 24 | 336444470000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2060642756 | Jul 01 10:35:28 AM PDT 24 | Jul 01 11:15:04 AM PDT 24 | 336516590000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1273858544 | Jul 01 10:35:40 AM PDT 24 | Jul 01 11:07:31 AM PDT 24 | 336742690000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1126597729 | Jul 01 10:35:28 AM PDT 24 | Jul 01 11:07:36 AM PDT 24 | 337084590000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2566991478 | Jul 01 10:35:52 AM PDT 24 | Jul 01 11:07:43 AM PDT 24 | 336426330000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1080799796 | Jul 01 10:35:23 AM PDT 24 | Jul 01 11:10:41 AM PDT 24 | 336323390000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1156167262 | Jul 01 10:35:39 AM PDT 24 | Jul 01 11:07:01 AM PDT 24 | 336631630000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.846777871 | Jul 01 10:35:34 AM PDT 24 | Jul 01 11:06:29 AM PDT 24 | 336772410000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4141963751 | Jul 01 10:35:52 AM PDT 24 | Jul 01 11:06:58 AM PDT 24 | 337062370000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.178798303 | Jul 01 10:35:24 AM PDT 24 | Jul 01 11:00:32 AM PDT 24 | 336527050000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2600457359 | Jul 01 10:35:24 AM PDT 24 | Jul 01 11:15:30 AM PDT 24 | 336723270000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3571606987 | Jul 01 10:35:31 AM PDT 24 | Jul 01 11:05:02 AM PDT 24 | 336514130000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2543943360 | Jul 01 10:35:58 AM PDT 24 | Jul 01 11:06:11 AM PDT 24 | 336474410000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4181734295 | Jul 01 10:35:54 AM PDT 24 | Jul 01 11:04:45 AM PDT 24 | 336994870000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.987185452 | Jul 01 10:35:55 AM PDT 24 | Jul 01 11:01:17 AM PDT 24 | 336396330000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2232197 | Jul 01 10:35:30 AM PDT 24 | Jul 01 11:12:19 AM PDT 24 | 337036430000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.483267893 | Jul 01 10:35:48 AM PDT 24 | Jul 01 11:03:07 AM PDT 24 | 336788910000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3219701369 | Jul 01 10:35:27 AM PDT 24 | Jul 01 11:09:02 AM PDT 24 | 337025310000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.710101181 | Jul 01 10:35:28 AM PDT 24 | Jul 01 11:07:25 AM PDT 24 | 336355650000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2463262060 | Jul 01 10:35:45 AM PDT 24 | Jul 01 11:10:29 AM PDT 24 | 336905170000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2236049419 | Jul 01 10:35:43 AM PDT 24 | Jul 01 11:02:48 AM PDT 24 | 336771810000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2821009184 | Jul 01 10:35:27 AM PDT 24 | Jul 01 11:12:22 AM PDT 24 | 336988170000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2856165635 | Jul 01 10:35:51 AM PDT 24 | Jul 01 11:03:46 AM PDT 24 | 336517630000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1774835452 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1370670000 ps |
| CPU time | 3.99 seconds |
| Started | Jul 01 10:23:47 AM PDT 24 |
| Finished | Jul 01 10:23:57 AM PDT 24 |
| Peak memory | 164228 kb |
| Host | smart-3953d7d0-5186-4b84-a4c5-39a8a6c67386 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1774835452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1774835452 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.1224399705 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 337095630000 ps |
| CPU time | 666.84 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 11:02:17 AM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-2525cb7c-2805-492d-a2ee-11ad93bd6a42 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1224399705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.1224399705 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2013413301 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 336682630000 ps |
| CPU time | 711.49 seconds |
| Started | Jul 01 10:35:55 AM PDT 24 |
| Finished | Jul 01 11:05:12 AM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-e6560ea2-50f4-4ab8-91ac-9cca4dd2fc68 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2013413301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2013413301 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.93964069 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336503990000 ps |
| CPU time | 707.29 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 11:04:13 AM PDT 24 |
| Peak memory | 160576 kb |
| Host | smart-60621b91-532c-47f0-8325-2ff81d3a2bd7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=93964069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.93964069 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.316107357 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 336580250000 ps |
| CPU time | 704.27 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 11:03:22 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-e2e408df-6fdf-44e1-a0e4-a94c09e924e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=316107357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.316107357 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2770884383 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336600390000 ps |
| CPU time | 788.86 seconds |
| Started | Jul 01 10:34:57 AM PDT 24 |
| Finished | Jul 01 11:07:03 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-72492963-38a0-4902-81fe-561f817cbfb6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2770884383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2770884383 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.2240286768 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336922090000 ps |
| CPU time | 715.39 seconds |
| Started | Jul 01 10:34:49 AM PDT 24 |
| Finished | Jul 01 11:04:10 AM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-eb60f6b2-b4eb-4010-bca8-c41c72b98289 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2240286768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.2240286768 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3779782344 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336709810000 ps |
| CPU time | 647.47 seconds |
| Started | Jul 01 10:35:08 AM PDT 24 |
| Finished | Jul 01 11:01:59 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-7f9a3a57-b8c9-45e0-b880-0dcf3c13138d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3779782344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3779782344 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.1965114865 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336932410000 ps |
| CPU time | 771.44 seconds |
| Started | Jul 01 10:35:08 AM PDT 24 |
| Finished | Jul 01 11:06:23 AM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-008069ed-546a-493c-81ea-9976afafc4df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1965114865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.1965114865 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.250904726 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 337078490000 ps |
| CPU time | 711.35 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 11:04:24 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-cf75f439-6548-495a-817b-3c247cdc7c24 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=250904726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.250904726 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2132679813 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336921990000 ps |
| CPU time | 598.06 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:59:59 AM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-c087b466-c5ea-4185-b8c5-d78155f53cda |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2132679813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2132679813 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1636936328 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336577990000 ps |
| CPU time | 765.25 seconds |
| Started | Jul 01 10:35:10 AM PDT 24 |
| Finished | Jul 01 11:06:20 AM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-cc4a73b4-6b17-468c-a673-b968efffc2d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1636936328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.1636936328 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.314917519 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 336730770000 ps |
| CPU time | 769.02 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 11:06:17 AM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-617a5956-3777-475f-b714-a30d71fb9374 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=314917519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.314917519 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.638405482 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336581850000 ps |
| CPU time | 695.78 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 11:03:42 AM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-e8891dc4-7583-4594-8337-e14aeda988f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=638405482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.638405482 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.577335210 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336752790000 ps |
| CPU time | 691.65 seconds |
| Started | Jul 01 10:34:53 AM PDT 24 |
| Finished | Jul 01 11:03:11 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-2bc06ee5-27be-4bcb-81de-eef76a4c2061 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=577335210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.577335210 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.1726022347 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 336359430000 ps |
| CPU time | 615.73 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 11:00:24 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-4ee68a6b-6569-40b3-8c5c-b6b008fe83dd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1726022347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.1726022347 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.254141734 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 336885150000 ps |
| CPU time | 796.11 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 11:07:05 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-7b8bfae7-37b7-47b3-9667-b22de75cf96a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=254141734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.254141734 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.5004339 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 337046870000 ps |
| CPU time | 767.87 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 11:06:10 AM PDT 24 |
| Peak memory | 160632 kb |
| Host | smart-2670417f-c5ce-4ff4-8888-a4c3aaff0ad4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=5004339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.5004339 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3411986398 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336413870000 ps |
| CPU time | 899.79 seconds |
| Started | Jul 01 10:35:09 AM PDT 24 |
| Finished | Jul 01 11:12:04 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-d369ba5b-b8f9-4bad-8e36-b4764a7ccace |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3411986398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3411986398 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2377956191 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336764970000 ps |
| CPU time | 710.19 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 11:04:22 AM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-178df65f-cf56-4f05-9d1e-0ec2b4247f3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2377956191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2377956191 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1943621972 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336866870000 ps |
| CPU time | 785.97 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 11:07:01 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-55412ab3-0ce1-4ed2-8293-7b083986c942 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1943621972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1943621972 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.3900735796 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 336506890000 ps |
| CPU time | 791.97 seconds |
| Started | Jul 01 10:34:57 AM PDT 24 |
| Finished | Jul 01 11:07:04 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-5434d0e5-d129-4fce-88ab-e1159bc295c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3900735796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.3900735796 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.4241722291 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336486070000 ps |
| CPU time | 699.37 seconds |
| Started | Jul 01 10:35:09 AM PDT 24 |
| Finished | Jul 01 11:04:05 AM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-d4fdfa04-226f-4324-ac9a-f1c6ef1278c8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4241722291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.4241722291 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2216286876 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336380730000 ps |
| CPU time | 663.94 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 11:02:17 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-21695991-d2e9-43ac-88a3-56ed928bb594 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2216286876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2216286876 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2701982925 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 336746390000 ps |
| CPU time | 619.87 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 11:00:38 AM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-6c5b5631-4335-407d-ae16-fdc0d3aa0eb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2701982925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2701982925 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3630502189 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336695850000 ps |
| CPU time | 779.77 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 11:06:48 AM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-9187130d-4bff-4018-a302-5e66ceb8b761 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3630502189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3630502189 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1332427137 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 336632670000 ps |
| CPU time | 659.09 seconds |
| Started | Jul 01 10:35:12 AM PDT 24 |
| Finished | Jul 01 11:02:29 AM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-083856d9-4601-4705-b7ab-8b9d01efbb0b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1332427137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1332427137 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.737824935 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336912910000 ps |
| CPU time | 862.93 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 11:10:04 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-2a9404e2-0735-4304-87b2-24ea49c2c99f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=737824935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.737824935 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.259467243 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 336807950000 ps |
| CPU time | 838.51 seconds |
| Started | Jul 01 10:35:08 AM PDT 24 |
| Finished | Jul 01 11:09:30 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-eb010950-2fe0-437a-a663-09e92cdf383a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=259467243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.259467243 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3841986167 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336732910000 ps |
| CPU time | 820.89 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 11:08:48 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-3fac5520-d1d8-4455-bd89-868f4af15baf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3841986167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.3841986167 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3468101027 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336433990000 ps |
| CPU time | 693.4 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 11:03:29 AM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-547a22dd-9ac4-44b0-98d0-b581273a5c0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3468101027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3468101027 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3470001397 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336425670000 ps |
| CPU time | 834.48 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 11:09:35 AM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-66365c88-4751-4051-af08-eeea20dcbed7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3470001397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.3470001397 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1651965305 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 336573770000 ps |
| CPU time | 845.47 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 11:09:30 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-4e684c73-fc22-4cff-b64b-d73d8c3a86d3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1651965305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1651965305 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1845985262 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 336782410000 ps |
| CPU time | 691.39 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 11:03:28 AM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-5c2da525-fb8d-4ab6-b468-4a025b225e2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1845985262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1845985262 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.779035643 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 336838410000 ps |
| CPU time | 839.53 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 11:09:41 AM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-83bd2c6f-eda2-40dc-a0f9-b95e4badcbeb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=779035643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.779035643 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2319662518 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 337104890000 ps |
| CPU time | 792.72 seconds |
| Started | Jul 01 10:35:09 AM PDT 24 |
| Finished | Jul 01 11:07:53 AM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-2bea7925-f2cf-4ea3-bfa9-2573ea043b37 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2319662518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.2319662518 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3639430649 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 336499050000 ps |
| CPU time | 786.9 seconds |
| Started | Jul 01 10:35:14 AM PDT 24 |
| Finished | Jul 01 11:07:26 AM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-963fce93-8084-4cbf-b791-865b974e8307 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3639430649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3639430649 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4140619350 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336722350000 ps |
| CPU time | 678.22 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 11:03:10 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-0cd7fe14-5ae8-4289-95d2-dfee0b3a138d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4140619350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4140619350 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2776580688 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 336431610000 ps |
| CPU time | 940.64 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 11:14:09 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-83e182ea-c743-42de-b523-767e20e5a6f1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2776580688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2776580688 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.2321371123 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 336485210000 ps |
| CPU time | 803.27 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 11:07:46 AM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-fe48c2ab-17be-4d17-a37d-a9f87b644bf8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2321371123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.2321371123 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4281555739 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 337097610000 ps |
| CPU time | 612.23 seconds |
| Started | Jul 01 10:35:36 AM PDT 24 |
| Finished | Jul 01 11:01:05 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-81e4a0cd-6041-42dc-b53e-8d3e34c45be2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4281555739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.4281555739 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.3311754290 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 336438330000 ps |
| CPU time | 588.42 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 10:59:32 AM PDT 24 |
| Peak memory | 160656 kb |
| Host | smart-2a727505-ba0e-4962-a52c-c5b3b9fb0b5e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3311754290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.3311754290 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1148249325 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336451110000 ps |
| CPU time | 693.92 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 11:03:45 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-c1eba04b-4b3d-4bd0-aa67-c8587619a62c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1148249325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1148249325 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2510941620 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 336851670000 ps |
| CPU time | 677.77 seconds |
| Started | Jul 01 10:35:07 AM PDT 24 |
| Finished | Jul 01 11:03:10 AM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-93a0142a-4d13-4904-aafd-2db14cd31abf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2510941620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2510941620 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1657791366 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 337135430000 ps |
| CPU time | 826.86 seconds |
| Started | Jul 01 10:35:07 AM PDT 24 |
| Finished | Jul 01 11:08:57 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-80769e93-0ff2-4694-bedc-aff652066860 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1657791366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1657791366 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1896463573 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336498170000 ps |
| CPU time | 773 seconds |
| Started | Jul 01 10:35:08 AM PDT 24 |
| Finished | Jul 01 11:06:56 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-8be6470c-c332-483b-9a64-d1c42b89e070 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1896463573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1896463573 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4089476007 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336574250000 ps |
| CPU time | 789.39 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 11:07:23 AM PDT 24 |
| Peak memory | 160644 kb |
| Host | smart-556db19d-a62d-4d69-b046-560a545f0959 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4089476007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4089476007 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2063689874 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 336560110000 ps |
| CPU time | 680.8 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 11:03:09 AM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-361c6799-bf5b-4122-997a-4c5bdf8c82ec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2063689874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2063689874 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.678730005 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336411350000 ps |
| CPU time | 631.13 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 11:01:14 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-bad8745d-86bb-4a08-b879-ece9d9066cb5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=678730005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.678730005 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3183764090 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 336675650000 ps |
| CPU time | 898.01 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 11:11:48 AM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-54b2a330-2164-41ed-ab85-f01214046dec |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3183764090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3183764090 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.2402045190 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336787310000 ps |
| CPU time | 727.41 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 11:04:58 AM PDT 24 |
| Peak memory | 160664 kb |
| Host | smart-0053fb99-e352-41a7-ade0-82f98e71ba11 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2402045190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.2402045190 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.118875849 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336479410000 ps |
| CPU time | 800.25 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 11:07:41 AM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-80695a77-729a-4379-9778-01b119cc03da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=118875849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.118875849 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2899729478 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 337137190000 ps |
| CPU time | 655.02 seconds |
| Started | Jul 01 10:35:26 AM PDT 24 |
| Finished | Jul 01 11:02:27 AM PDT 24 |
| Peak memory | 160728 kb |
| Host | smart-8231e065-510e-42e1-90ca-59f9f8c5d4fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2899729478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2899729478 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1293528279 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 337183830000 ps |
| CPU time | 710.2 seconds |
| Started | Jul 01 10:35:49 AM PDT 24 |
| Finished | Jul 01 11:05:18 AM PDT 24 |
| Peak memory | 160736 kb |
| Host | smart-7f95a9a2-ed5d-4082-af5a-fa535f019b91 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1293528279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1293528279 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.613230848 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336411230000 ps |
| CPU time | 786.13 seconds |
| Started | Jul 01 10:35:46 AM PDT 24 |
| Finished | Jul 01 11:07:29 AM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-9e050c87-a32d-4f1a-b01c-292dd1643704 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=613230848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.613230848 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2908313786 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336372590000 ps |
| CPU time | 651.78 seconds |
| Started | Jul 01 10:35:55 AM PDT 24 |
| Finished | Jul 01 11:02:52 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-f02ec64f-00b3-418c-8c3b-33144f76c991 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2908313786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2908313786 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3163281128 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 336737530000 ps |
| CPU time | 691.34 seconds |
| Started | Jul 01 10:35:25 AM PDT 24 |
| Finished | Jul 01 11:03:41 AM PDT 24 |
| Peak memory | 160596 kb |
| Host | smart-370bebf5-c8f6-453e-98ab-4d98e3d216a7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3163281128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.3163281128 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1156167262 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336631630000 ps |
| CPU time | 760.66 seconds |
| Started | Jul 01 10:35:39 AM PDT 24 |
| Finished | Jul 01 11:07:01 AM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-b3e3b4e1-a5c9-4d44-8521-f0e20cc680fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1156167262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1156167262 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.714664281 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336647970000 ps |
| CPU time | 751.84 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 11:06:25 AM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-b3f6c4f3-446c-4a45-8f22-cfe8ea402f1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=714664281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.714664281 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.4204152701 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 337030270000 ps |
| CPU time | 771.48 seconds |
| Started | Jul 01 10:35:35 AM PDT 24 |
| Finished | Jul 01 11:06:55 AM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-3a64ec14-a157-45ea-86c2-13a639e7e376 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4204152701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.4204152701 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.2859024640 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336649850000 ps |
| CPU time | 763.53 seconds |
| Started | Jul 01 10:35:21 AM PDT 24 |
| Finished | Jul 01 11:06:15 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-2579723f-5e22-4a73-b8ec-84f7c3794d62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2859024640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.2859024640 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2463262060 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336905170000 ps |
| CPU time | 853.52 seconds |
| Started | Jul 01 10:35:45 AM PDT 24 |
| Finished | Jul 01 11:10:29 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-86bf10bd-d319-4a57-9a5e-46c593d8ce7d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2463262060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2463262060 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1759160417 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 336618490000 ps |
| CPU time | 672.76 seconds |
| Started | Jul 01 10:35:53 AM PDT 24 |
| Finished | Jul 01 11:03:40 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-25367594-54f0-4cb9-94f4-fb513a3151e8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1759160417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1759160417 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2587077842 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336907510000 ps |
| CPU time | 672.49 seconds |
| Started | Jul 01 10:35:58 AM PDT 24 |
| Finished | Jul 01 11:04:00 AM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-97b09e5d-976c-4bda-aae4-7268937532fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2587077842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2587077842 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1067631147 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336444470000 ps |
| CPU time | 773.16 seconds |
| Started | Jul 01 10:35:26 AM PDT 24 |
| Finished | Jul 01 11:06:55 AM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-747ef46a-1867-49e8-8086-ed26b5617aa4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1067631147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1067631147 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3219701369 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 337025310000 ps |
| CPU time | 836.15 seconds |
| Started | Jul 01 10:35:27 AM PDT 24 |
| Finished | Jul 01 11:09:02 AM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-187acfef-3273-405f-ab36-ffb2af969cac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3219701369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3219701369 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2398431807 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336721070000 ps |
| CPU time | 795.27 seconds |
| Started | Jul 01 10:35:29 AM PDT 24 |
| Finished | Jul 01 11:08:07 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-6ef9782c-e1a4-498d-a18d-4be65e44be02 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2398431807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2398431807 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3997673144 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336859230000 ps |
| CPU time | 959.98 seconds |
| Started | Jul 01 10:35:22 AM PDT 24 |
| Finished | Jul 01 11:15:30 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-ab214232-57f1-4f33-b681-db147f29d637 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3997673144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3997673144 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2821009184 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336988170000 ps |
| CPU time | 904.98 seconds |
| Started | Jul 01 10:35:27 AM PDT 24 |
| Finished | Jul 01 11:12:22 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-3b56800e-0a84-43cf-8d62-10365570ae52 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2821009184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2821009184 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.846777871 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336772410000 ps |
| CPU time | 751.17 seconds |
| Started | Jul 01 10:35:34 AM PDT 24 |
| Finished | Jul 01 11:06:29 AM PDT 24 |
| Peak memory | 160640 kb |
| Host | smart-6a6eee01-5449-40b9-b415-68379448fff3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=846777871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.846777871 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4141963751 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 337062370000 ps |
| CPU time | 758.93 seconds |
| Started | Jul 01 10:35:52 AM PDT 24 |
| Finished | Jul 01 11:06:58 AM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-75a9f81a-51be-47d6-8803-10429bab08c6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4141963751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4141963751 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.1555187105 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 336668730000 ps |
| CPU time | 757.78 seconds |
| Started | Jul 01 10:35:30 AM PDT 24 |
| Finished | Jul 01 11:06:20 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-c1343b90-8478-4c7c-89fd-679bf888925d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1555187105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.1555187105 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1165076720 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336591310000 ps |
| CPU time | 791.61 seconds |
| Started | Jul 01 10:35:29 AM PDT 24 |
| Finished | Jul 01 11:07:45 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-0740c9d3-c8b1-4ea6-993e-7cb2f9ad31bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1165076720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1165076720 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.4067252007 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336942750000 ps |
| CPU time | 816.02 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 11:08:54 AM PDT 24 |
| Peak memory | 160668 kb |
| Host | smart-fab989ff-b47a-4a99-99e4-57471c200881 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4067252007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.4067252007 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.987185452 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336396330000 ps |
| CPU time | 608.3 seconds |
| Started | Jul 01 10:35:55 AM PDT 24 |
| Finished | Jul 01 11:01:17 AM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-8a81e129-0862-4564-8fe3-d83d5e43aab3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=987185452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.987185452 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2305258711 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 336842330000 ps |
| CPU time | 766.19 seconds |
| Started | Jul 01 10:35:41 AM PDT 24 |
| Finished | Jul 01 11:07:23 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-df21cc0e-eceb-49ec-962d-1dacd49fe547 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2305258711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2305258711 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.178798303 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336527050000 ps |
| CPU time | 619.86 seconds |
| Started | Jul 01 10:35:24 AM PDT 24 |
| Finished | Jul 01 11:00:32 AM PDT 24 |
| Peak memory | 160732 kb |
| Host | smart-00bd1e20-9337-4bf2-97b9-b2894ee870c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=178798303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.178798303 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.3571606987 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336514130000 ps |
| CPU time | 718.43 seconds |
| Started | Jul 01 10:35:31 AM PDT 24 |
| Finished | Jul 01 11:05:02 AM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-9c51153b-468c-4f1a-89e4-d49758f01eb4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3571606987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.3571606987 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.1273858544 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336742690000 ps |
| CPU time | 779.71 seconds |
| Started | Jul 01 10:35:40 AM PDT 24 |
| Finished | Jul 01 11:07:31 AM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-2af09015-7d1c-48eb-8f0f-a6981a93a43b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1273858544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.1273858544 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2232197 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 337036430000 ps |
| CPU time | 899.97 seconds |
| Started | Jul 01 10:35:30 AM PDT 24 |
| Finished | Jul 01 11:12:19 AM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-c6346804-b94c-427b-a8c2-db6d53d99c42 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2232197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2232197 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1080799796 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 336323390000 ps |
| CPU time | 885.1 seconds |
| Started | Jul 01 10:35:23 AM PDT 24 |
| Finished | Jul 01 11:10:41 AM PDT 24 |
| Peak memory | 160888 kb |
| Host | smart-80b32ced-c3d1-4a35-b703-a1f4c5e95c33 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1080799796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1080799796 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2236049419 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336771810000 ps |
| CPU time | 658.9 seconds |
| Started | Jul 01 10:35:43 AM PDT 24 |
| Finished | Jul 01 11:02:48 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-4323d1a8-263d-4015-b88c-20b72a54a364 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2236049419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2236049419 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2823209127 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336354890000 ps |
| CPU time | 814.78 seconds |
| Started | Jul 01 10:35:39 AM PDT 24 |
| Finished | Jul 01 11:09:07 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-0e386f37-3f51-4d8e-b5a5-706456a8c192 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2823209127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2823209127 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2600457359 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336723270000 ps |
| CPU time | 961.42 seconds |
| Started | Jul 01 10:35:24 AM PDT 24 |
| Finished | Jul 01 11:15:30 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-04abc487-1a6e-4d94-8e61-f909e009218f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2600457359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2600457359 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.1525706474 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336531810000 ps |
| CPU time | 848.5 seconds |
| Started | Jul 01 10:35:43 AM PDT 24 |
| Finished | Jul 01 11:10:46 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-eacdd1ef-2bca-4c7e-a5c6-b85d619ac68e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1525706474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.1525706474 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2455264636 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 336726910000 ps |
| CPU time | 646.2 seconds |
| Started | Jul 01 10:35:58 AM PDT 24 |
| Finished | Jul 01 11:02:41 AM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-e64a55b2-2064-4492-acea-a373c55dc628 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2455264636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2455264636 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2543943360 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336474410000 ps |
| CPU time | 740.14 seconds |
| Started | Jul 01 10:35:58 AM PDT 24 |
| Finished | Jul 01 11:06:11 AM PDT 24 |
| Peak memory | 160772 kb |
| Host | smart-a3961364-11e7-48ae-b09c-06ae530d1659 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2543943360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2543943360 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1081180883 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 337097350000 ps |
| CPU time | 740.29 seconds |
| Started | Jul 01 10:35:16 AM PDT 24 |
| Finished | Jul 01 11:05:36 AM PDT 24 |
| Peak memory | 160680 kb |
| Host | smart-ac9f001b-0ee1-4f9c-8400-4bb15a05f989 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1081180883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1081180883 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.900195845 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336815550000 ps |
| CPU time | 907.78 seconds |
| Started | Jul 01 10:35:30 AM PDT 24 |
| Finished | Jul 01 11:12:19 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-9282c501-4776-4a61-a18b-0befd8926679 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=900195845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.900195845 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1126597729 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 337084590000 ps |
| CPU time | 786.61 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 11:07:36 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-6edd897a-567a-4b9b-95f8-8ac0363b709f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1126597729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1126597729 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.710101181 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336355650000 ps |
| CPU time | 784.33 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 11:07:25 AM PDT 24 |
| Peak memory | 160672 kb |
| Host | smart-2863ee2f-782f-4a54-bcfa-b296d5f76c1b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=710101181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.710101181 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2060642756 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336516590000 ps |
| CPU time | 951.11 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 11:15:04 AM PDT 24 |
| Peak memory | 160720 kb |
| Host | smart-4778efd0-1487-43dc-8b69-245a47ff57e1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2060642756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2060642756 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3879972636 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 336400890000 ps |
| CPU time | 729.77 seconds |
| Started | Jul 01 10:35:47 AM PDT 24 |
| Finished | Jul 01 11:05:42 AM PDT 24 |
| Peak memory | 160724 kb |
| Host | smart-7fa9d92c-2d9b-4bea-aaea-9380fe16c78e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3879972636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3879972636 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.3223251606 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336749870000 ps |
| CPU time | 782.1 seconds |
| Started | Jul 01 10:35:48 AM PDT 24 |
| Finished | Jul 01 11:08:07 AM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-0da8fa1d-91bc-42d1-a5ff-2a823ac59f29 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3223251606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.3223251606 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.483267893 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336788910000 ps |
| CPU time | 659.77 seconds |
| Started | Jul 01 10:35:48 AM PDT 24 |
| Finished | Jul 01 11:03:07 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-015cbf87-256d-469a-b0b7-1d2e1fa8bb31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=483267893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.483267893 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.440178262 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 337025210000 ps |
| CPU time | 796.01 seconds |
| Started | Jul 01 10:35:33 AM PDT 24 |
| Finished | Jul 01 11:08:11 AM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-687f364e-671d-47b1-bae2-37c6ea60fa85 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=440178262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.440178262 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.4021272004 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336621210000 ps |
| CPU time | 693.86 seconds |
| Started | Jul 01 10:35:36 AM PDT 24 |
| Finished | Jul 01 11:04:15 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-0ae143c6-4b65-4203-8e25-8578a4249032 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4021272004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.4021272004 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2856165635 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336517630000 ps |
| CPU time | 674.2 seconds |
| Started | Jul 01 10:35:51 AM PDT 24 |
| Finished | Jul 01 11:03:46 AM PDT 24 |
| Peak memory | 160624 kb |
| Host | smart-d3e72d18-cf7e-413e-ae1b-b0e9ef40fbe2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2856165635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2856165635 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.4181734295 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336994870000 ps |
| CPU time | 695.97 seconds |
| Started | Jul 01 10:35:54 AM PDT 24 |
| Finished | Jul 01 11:04:45 AM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-d9723fee-b711-4530-b336-6273a409a961 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4181734295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.4181734295 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2566991478 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 336426330000 ps |
| CPU time | 778.46 seconds |
| Started | Jul 01 10:35:52 AM PDT 24 |
| Finished | Jul 01 11:07:43 AM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-c8fb7c85-5758-48e6-abb5-646f14d3051b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2566991478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2566991478 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1073723877 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336804110000 ps |
| CPU time | 771.96 seconds |
| Started | Jul 01 10:35:24 AM PDT 24 |
| Finished | Jul 01 11:06:46 AM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-dac96564-1c34-4491-8959-198ff963c6ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1073723877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1073723877 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.216668658 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1532010000 ps |
| CPU time | 4.34 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 10:35:39 AM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-413ef2e8-76a8-46ce-bfd6-b80acc5ef873 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=216668658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.216668658 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4289928452 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1534770000 ps |
| CPU time | 3.43 seconds |
| Started | Jul 01 10:35:22 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-f46e766b-68dc-4ad2-9849-f6f859961b4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4289928452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.4289928452 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4210928592 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1531270000 ps |
| CPU time | 3.84 seconds |
| Started | Jul 01 10:35:22 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-9d97f9c3-d01c-4b41-814f-842820e3bbee |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4210928592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4210928592 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.2491665371 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1598150000 ps |
| CPU time | 5.02 seconds |
| Started | Jul 01 10:35:25 AM PDT 24 |
| Finished | Jul 01 10:35:37 AM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-e7c32e26-6f93-4282-98df-0cd9fa6a7e8a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2491665371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.2491665371 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1512956176 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1484690000 ps |
| CPU time | 4.89 seconds |
| Started | Jul 01 10:35:50 AM PDT 24 |
| Finished | Jul 01 10:36:04 AM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-9e6d38f6-fa57-436d-abb2-24c6d6d2dd66 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1512956176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1512956176 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.2475749539 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1468650000 ps |
| CPU time | 3.55 seconds |
| Started | Jul 01 10:35:15 AM PDT 24 |
| Finished | Jul 01 10:35:28 AM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-e9144fad-666a-40e6-9af0-7a816d04543d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2475749539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.2475749539 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1781266035 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1441870000 ps |
| CPU time | 4.02 seconds |
| Started | Jul 01 10:35:19 AM PDT 24 |
| Finished | Jul 01 10:35:31 AM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-b86bd0de-7270-41c2-9578-1bbd0f7016ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1781266035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1781266035 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2060391741 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1513010000 ps |
| CPU time | 3.86 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 10:35:38 AM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-451fbd8f-b430-4387-88e8-62615aacb122 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2060391741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2060391741 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1932364744 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1455010000 ps |
| CPU time | 3.87 seconds |
| Started | Jul 01 10:35:18 AM PDT 24 |
| Finished | Jul 01 10:35:30 AM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-1e72ab1f-338c-4f0d-8b8d-1af99a0c3896 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1932364744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1932364744 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3599827184 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1313190000 ps |
| CPU time | 4 seconds |
| Started | Jul 01 10:35:53 AM PDT 24 |
| Finished | Jul 01 10:36:05 AM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-e2ef24e4-e730-456e-a14b-e2ad2b2627a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3599827184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3599827184 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3888107303 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1362030000 ps |
| CPU time | 4.19 seconds |
| Started | Jul 01 10:35:16 AM PDT 24 |
| Finished | Jul 01 10:35:30 AM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-a1c4ec48-78af-4b4e-96f2-7150c8073d9a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3888107303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3888107303 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1445539190 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1416650000 ps |
| CPU time | 3.75 seconds |
| Started | Jul 01 10:35:34 AM PDT 24 |
| Finished | Jul 01 10:35:43 AM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-54b14c60-0884-4d8c-93fd-9487820086d0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1445539190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1445539190 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.308199188 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1478790000 ps |
| CPU time | 3.11 seconds |
| Started | Jul 01 10:35:16 AM PDT 24 |
| Finished | Jul 01 10:35:28 AM PDT 24 |
| Peak memory | 164664 kb |
| Host | smart-fe65d95f-89f8-437d-823e-322ad1ebd020 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=308199188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.308199188 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3377817030 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1453170000 ps |
| CPU time | 4.56 seconds |
| Started | Jul 01 10:35:27 AM PDT 24 |
| Finished | Jul 01 10:35:38 AM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-eb1c0be3-b097-4120-8014-0791aa3003cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3377817030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3377817030 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2079451756 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1466490000 ps |
| CPU time | 3.81 seconds |
| Started | Jul 01 10:35:20 AM PDT 24 |
| Finished | Jul 01 10:35:31 AM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-4555e874-e3ac-46b5-8506-defdbd67c0b0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2079451756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2079451756 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3874845172 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1499150000 ps |
| CPU time | 2.97 seconds |
| Started | Jul 01 10:37:06 AM PDT 24 |
| Finished | Jul 01 10:37:15 AM PDT 24 |
| Peak memory | 164692 kb |
| Host | smart-b34770ae-6215-4d96-8e81-cd715f2d5539 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3874845172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3874845172 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1902900140 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1519210000 ps |
| CPU time | 3.97 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 10:35:38 AM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-21ac788b-63de-44a8-abba-d7494f0daf15 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1902900140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1902900140 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.931300343 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1519970000 ps |
| CPU time | 4.29 seconds |
| Started | Jul 01 10:35:40 AM PDT 24 |
| Finished | Jul 01 10:35:50 AM PDT 24 |
| Peak memory | 164708 kb |
| Host | smart-249c6b86-3cdb-489f-aca9-7569af0cece8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=931300343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.931300343 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2872777087 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1332870000 ps |
| CPU time | 3.98 seconds |
| Started | Jul 01 10:35:29 AM PDT 24 |
| Finished | Jul 01 10:35:39 AM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-c4780823-5f9d-452c-bea1-26025e703cfe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2872777087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2872777087 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.4265884764 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1564410000 ps |
| CPU time | 4.81 seconds |
| Started | Jul 01 10:35:28 AM PDT 24 |
| Finished | Jul 01 10:35:40 AM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-b8992518-140c-43cd-82d7-f3b229669e43 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4265884764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.4265884764 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.4288084054 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1332110000 ps |
| CPU time | 3.88 seconds |
| Started | Jul 01 10:35:30 AM PDT 24 |
| Finished | Jul 01 10:35:40 AM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-8c0c89b3-8be6-4b65-9c45-1dfbf5fa39b9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4288084054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.4288084054 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1476293683 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1279890000 ps |
| CPU time | 3.81 seconds |
| Started | Jul 01 10:35:48 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-dd5ce9b5-da09-40f6-911d-3788ddcd0eec |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1476293683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1476293683 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3196322862 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1576390000 ps |
| CPU time | 3.98 seconds |
| Started | Jul 01 10:35:18 AM PDT 24 |
| Finished | Jul 01 10:35:31 AM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-71849ba8-b57d-440c-8154-e48725010a81 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3196322862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.3196322862 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4151047599 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1512170000 ps |
| CPU time | 3.09 seconds |
| Started | Jul 01 10:37:16 AM PDT 24 |
| Finished | Jul 01 10:37:24 AM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-5191bb74-08c8-47a8-80b9-c14afc34d64c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4151047599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.4151047599 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2654239243 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1438510000 ps |
| CPU time | 3.93 seconds |
| Started | Jul 01 10:35:31 AM PDT 24 |
| Finished | Jul 01 10:35:41 AM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-5dcbb2cf-88d0-4c09-9419-40a0e5401559 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2654239243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2654239243 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3282994152 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1495510000 ps |
| CPU time | 3.67 seconds |
| Started | Jul 01 10:35:47 AM PDT 24 |
| Finished | Jul 01 10:35:57 AM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-52ea8e04-6dbf-468c-bf85-c2e423404a92 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3282994152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3282994152 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4016766310 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1342590000 ps |
| CPU time | 4.29 seconds |
| Started | Jul 01 10:35:17 AM PDT 24 |
| Finished | Jul 01 10:35:31 AM PDT 24 |
| Peak memory | 164860 kb |
| Host | smart-26d6c2bb-adaf-47bf-b29c-38670102c863 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4016766310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4016766310 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.2055343802 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1225450000 ps |
| CPU time | 3.6 seconds |
| Started | Jul 01 10:35:29 AM PDT 24 |
| Finished | Jul 01 10:35:38 AM PDT 24 |
| Peak memory | 164844 kb |
| Host | smart-8f1b9b57-ca10-4674-80f8-338ba4f9f0a6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2055343802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.2055343802 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.435783242 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1521170000 ps |
| CPU time | 4.67 seconds |
| Started | Jul 01 10:35:18 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-33755ef2-9925-4089-a0c2-2cd174350e76 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=435783242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.435783242 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.136469304 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1171930000 ps |
| CPU time | 2.71 seconds |
| Started | Jul 01 10:36:00 AM PDT 24 |
| Finished | Jul 01 10:36:12 AM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-b2998ac9-d321-4b83-9d3a-855f0fa174f4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=136469304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.136469304 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3146990829 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1458050000 ps |
| CPU time | 2.94 seconds |
| Started | Jul 01 10:35:31 AM PDT 24 |
| Finished | Jul 01 10:35:38 AM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-d096a33a-1084-469e-b9e0-e18d61cc4c93 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3146990829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3146990829 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1550174854 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1569710000 ps |
| CPU time | 3.23 seconds |
| Started | Jul 01 10:35:39 AM PDT 24 |
| Finished | Jul 01 10:35:47 AM PDT 24 |
| Peak memory | 164848 kb |
| Host | smart-c6129704-bcfa-4e6f-a991-a48196a83315 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1550174854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1550174854 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3130737746 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1613270000 ps |
| CPU time | 3.51 seconds |
| Started | Jul 01 10:35:56 AM PDT 24 |
| Finished | Jul 01 10:36:07 AM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-e789c0b0-2843-4ef2-932a-10353a8e6ad2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3130737746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3130737746 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.148063056 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1459250000 ps |
| CPU time | 4.11 seconds |
| Started | Jul 01 10:36:03 AM PDT 24 |
| Finished | Jul 01 10:36:18 AM PDT 24 |
| Peak memory | 164764 kb |
| Host | smart-64077697-906e-4024-9982-39a1f1bb5cad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=148063056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.148063056 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3952387387 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1073990000 ps |
| CPU time | 3.03 seconds |
| Started | Jul 01 10:35:48 AM PDT 24 |
| Finished | Jul 01 10:35:59 AM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-12423237-0588-4d51-8fa0-5760fc1d23be |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3952387387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.3952387387 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.2933355460 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1168250000 ps |
| CPU time | 2.62 seconds |
| Started | Jul 01 10:35:51 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-c0b7feaa-ae21-4fa4-91da-0e21c0699ce2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2933355460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.2933355460 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2805495697 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1568570000 ps |
| CPU time | 3.38 seconds |
| Started | Jul 01 10:35:48 AM PDT 24 |
| Finished | Jul 01 10:35:59 AM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-fff8dc3d-1875-433b-b65b-c2f21d49cb16 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2805495697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2805495697 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.2782616138 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1529230000 ps |
| CPU time | 4.25 seconds |
| Started | Jul 01 10:35:27 AM PDT 24 |
| Finished | Jul 01 10:35:36 AM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-01acfe0c-c5cc-4e3e-9a46-6b426b03cdcc |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2782616138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.2782616138 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1853024522 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1365070000 ps |
| CPU time | 3.63 seconds |
| Started | Jul 01 10:35:18 AM PDT 24 |
| Finished | Jul 01 10:35:30 AM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-c3c28027-b250-4fca-b7e7-86f5745dd622 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1853024522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1853024522 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2226166043 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1366770000 ps |
| CPU time | 3.42 seconds |
| Started | Jul 01 10:35:55 AM PDT 24 |
| Finished | Jul 01 10:36:06 AM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-a8c9a8ba-2c6b-4e86-82e0-461dd9cb9b33 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2226166043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2226166043 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.2167785561 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1197710000 ps |
| CPU time | 3.54 seconds |
| Started | Jul 01 10:35:26 AM PDT 24 |
| Finished | Jul 01 10:35:35 AM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-6bac6932-2bb5-4e2e-965f-6fde8b6b2275 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2167785561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.2167785561 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4193508033 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1436730000 ps |
| CPU time | 4.09 seconds |
| Started | Jul 01 10:35:31 AM PDT 24 |
| Finished | Jul 01 10:35:41 AM PDT 24 |
| Peak memory | 164836 kb |
| Host | smart-aeef794e-d3c6-4c42-a684-5e5df58302a1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4193508033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4193508033 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2200196784 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1437590000 ps |
| CPU time | 3.13 seconds |
| Started | Jul 01 10:35:50 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 164832 kb |
| Host | smart-bb5983c8-3a67-4360-bd68-556b8e825792 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2200196784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2200196784 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.148133871 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1432090000 ps |
| CPU time | 3.19 seconds |
| Started | Jul 01 10:36:04 AM PDT 24 |
| Finished | Jul 01 10:36:14 AM PDT 24 |
| Peak memory | 164840 kb |
| Host | smart-5c1d9c49-114c-437b-8cb9-3c9310f95e87 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=148133871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.148133871 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2015462767 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1411910000 ps |
| CPU time | 4 seconds |
| Started | Jul 01 10:35:24 AM PDT 24 |
| Finished | Jul 01 10:35:33 AM PDT 24 |
| Peak memory | 164824 kb |
| Host | smart-3737b82c-c0e0-409b-abd2-4d17f9db01f2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2015462767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2015462767 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.3426795417 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1473730000 ps |
| CPU time | 4.08 seconds |
| Started | Jul 01 10:35:47 AM PDT 24 |
| Finished | Jul 01 10:35:59 AM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-416cdb6e-e653-44d7-b1ce-b1fec38bfe29 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3426795417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.3426795417 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1503950303 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1414550000 ps |
| CPU time | 3.15 seconds |
| Started | Jul 01 10:35:20 AM PDT 24 |
| Finished | Jul 01 10:35:30 AM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-c798cdd7-bda4-4f76-ad9e-67dd3aa80f07 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1503950303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1503950303 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2162428173 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1443930000 ps |
| CPU time | 3.77 seconds |
| Started | Jul 01 10:35:37 AM PDT 24 |
| Finished | Jul 01 10:35:48 AM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-7c35ff13-655a-41a3-ac29-82ce360db26d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2162428173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2162428173 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.4273502908 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1604410000 ps |
| CPU time | 3.77 seconds |
| Started | Jul 01 10:35:24 AM PDT 24 |
| Finished | Jul 01 10:35:33 AM PDT 24 |
| Peak memory | 164864 kb |
| Host | smart-cb3551a5-4295-42f7-9bb7-97e1408a1d0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4273502908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.4273502908 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3582981054 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1299910000 ps |
| CPU time | 3.45 seconds |
| Started | Jul 01 10:35:34 AM PDT 24 |
| Finished | Jul 01 10:35:44 AM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-5e259506-a961-4e4f-ba91-5b5bb5bdd851 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3582981054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3582981054 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2262888899 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1529870000 ps |
| CPU time | 3.6 seconds |
| Started | Jul 01 10:23:59 AM PDT 24 |
| Finished | Jul 01 10:24:07 AM PDT 24 |
| Peak memory | 164580 kb |
| Host | smart-0438bfce-6f73-4a81-9209-8df6e69be879 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2262888899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2262888899 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.3720855196 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1563910000 ps |
| CPU time | 6.24 seconds |
| Started | Jul 01 10:27:39 AM PDT 24 |
| Finished | Jul 01 10:27:52 AM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-f8d58bd4-e955-4a90-bc63-bc3dbc39d431 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3720855196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.3720855196 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.1283801426 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1573090000 ps |
| CPU time | 4.24 seconds |
| Started | Jul 01 10:22:35 AM PDT 24 |
| Finished | Jul 01 10:22:44 AM PDT 24 |
| Peak memory | 163708 kb |
| Host | smart-98751806-7200-410d-89ac-f40d8604a445 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1283801426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.1283801426 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.838947096 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1453050000 ps |
| CPU time | 4.38 seconds |
| Started | Jul 01 10:23:47 AM PDT 24 |
| Finished | Jul 01 10:23:57 AM PDT 24 |
| Peak memory | 162260 kb |
| Host | smart-5c9914e9-bb64-4812-9569-5e4a3eb32e6e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=838947096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.838947096 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1027595975 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1282150000 ps |
| CPU time | 3.93 seconds |
| Started | Jul 01 10:23:47 AM PDT 24 |
| Finished | Jul 01 10:23:56 AM PDT 24 |
| Peak memory | 162688 kb |
| Host | smart-e229c91c-9e14-4bad-9479-433dbf65cb3c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1027595975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1027595975 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3734529649 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1463490000 ps |
| CPU time | 4.22 seconds |
| Started | Jul 01 10:28:05 AM PDT 24 |
| Finished | Jul 01 10:28:14 AM PDT 24 |
| Peak memory | 164476 kb |
| Host | smart-b3880263-7c40-4291-a669-058aace267c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3734529649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3734529649 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.3859793758 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1402870000 ps |
| CPU time | 4.45 seconds |
| Started | Jul 01 10:28:05 AM PDT 24 |
| Finished | Jul 01 10:28:15 AM PDT 24 |
| Peak memory | 164480 kb |
| Host | smart-b4a66508-e90b-46d5-b193-c1a8948b946a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3859793758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.3859793758 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1107429154 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1258030000 ps |
| CPU time | 4.65 seconds |
| Started | Jul 01 10:24:58 AM PDT 24 |
| Finished | Jul 01 10:25:08 AM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-e0508380-2cd1-41b0-8790-34d616b86926 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1107429154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1107429154 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1229269547 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1497930000 ps |
| CPU time | 4.29 seconds |
| Started | Jul 01 10:23:47 AM PDT 24 |
| Finished | Jul 01 10:23:58 AM PDT 24 |
| Peak memory | 164220 kb |
| Host | smart-9961b336-153c-43cb-b216-1b8b5eec5d22 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1229269547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1229269547 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2394990346 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1480670000 ps |
| CPU time | 3.47 seconds |
| Started | Jul 01 10:24:39 AM PDT 24 |
| Finished | Jul 01 10:24:47 AM PDT 24 |
| Peak memory | 164876 kb |
| Host | smart-9e41c0a6-dce1-474d-b5ae-68a696f6d597 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2394990346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2394990346 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.169570098 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1478370000 ps |
| CPU time | 3.92 seconds |
| Started | Jul 01 10:24:07 AM PDT 24 |
| Finished | Jul 01 10:24:16 AM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-5a3a2078-6fed-4922-9720-09041da33c3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=169570098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.169570098 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1577605948 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1281770000 ps |
| CPU time | 3.75 seconds |
| Started | Jul 01 10:23:18 AM PDT 24 |
| Finished | Jul 01 10:23:26 AM PDT 24 |
| Peak memory | 164580 kb |
| Host | smart-84220352-66ed-4082-a107-3e2d9da212de |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1577605948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.1577605948 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.4048173483 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1470070000 ps |
| CPU time | 5.03 seconds |
| Started | Jul 01 10:27:33 AM PDT 24 |
| Finished | Jul 01 10:27:44 AM PDT 24 |
| Peak memory | 163304 kb |
| Host | smart-397e6752-e921-44aa-97c5-274f843f8880 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4048173483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.4048173483 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3634302816 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1526230000 ps |
| CPU time | 3.73 seconds |
| Started | Jul 01 10:27:46 AM PDT 24 |
| Finished | Jul 01 10:27:54 AM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-88c76dfd-798c-47d7-9f70-e4c9a499cd68 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3634302816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3634302816 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1453358864 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1464710000 ps |
| CPU time | 4.61 seconds |
| Started | Jul 01 10:23:47 AM PDT 24 |
| Finished | Jul 01 10:23:58 AM PDT 24 |
| Peak memory | 162616 kb |
| Host | smart-86b79522-d8ca-4d60-a7b8-704daaca6ac1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1453358864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1453358864 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1624858247 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1301470000 ps |
| CPU time | 4.18 seconds |
| Started | Jul 01 10:28:05 AM PDT 24 |
| Finished | Jul 01 10:28:14 AM PDT 24 |
| Peak memory | 164472 kb |
| Host | smart-535977cf-961d-4ca1-a7ba-6c44e46524e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1624858247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1624858247 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1297941686 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1407610000 ps |
| CPU time | 3.99 seconds |
| Started | Jul 01 10:28:05 AM PDT 24 |
| Finished | Jul 01 10:28:14 AM PDT 24 |
| Peak memory | 164460 kb |
| Host | smart-0dea96dd-e055-4df9-9b77-434546af7151 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1297941686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1297941686 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.3874170602 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1540670000 ps |
| CPU time | 5.32 seconds |
| Started | Jul 01 10:27:34 AM PDT 24 |
| Finished | Jul 01 10:27:45 AM PDT 24 |
| Peak memory | 164252 kb |
| Host | smart-778e1abc-95d0-4706-98cb-9816c0d4cf31 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3874170602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.3874170602 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.1534949795 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1618970000 ps |
| CPU time | 5.5 seconds |
| Started | Jul 01 10:27:33 AM PDT 24 |
| Finished | Jul 01 10:27:45 AM PDT 24 |
| Peak memory | 163116 kb |
| Host | smart-e6153524-3a6b-412d-a1c1-bd8016b51e0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1534949795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.1534949795 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3408419322 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1600470000 ps |
| CPU time | 4.3 seconds |
| Started | Jul 01 10:27:57 AM PDT 24 |
| Finished | Jul 01 10:28:07 AM PDT 24 |
| Peak memory | 163332 kb |
| Host | smart-fbe016df-dcd6-448c-ad78-c8c1e19b138f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3408419322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3408419322 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1821712388 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1385750000 ps |
| CPU time | 3.07 seconds |
| Started | Jul 01 10:23:21 AM PDT 24 |
| Finished | Jul 01 10:23:28 AM PDT 24 |
| Peak memory | 164728 kb |
| Host | smart-80c68e8a-9f6d-4db0-9997-b078aa2c1809 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1821712388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1821712388 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3239594575 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1470710000 ps |
| CPU time | 4.34 seconds |
| Started | Jul 01 10:27:46 AM PDT 24 |
| Finished | Jul 01 10:27:56 AM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-88ade03a-7b20-447c-8cb6-07a441ada217 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3239594575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3239594575 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.124438428 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1575270000 ps |
| CPU time | 4.2 seconds |
| Started | Jul 01 10:27:57 AM PDT 24 |
| Finished | Jul 01 10:28:07 AM PDT 24 |
| Peak memory | 163908 kb |
| Host | smart-518f0fde-7f52-4fd8-806c-41b23e34f18d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=124438428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.124438428 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1532427564 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1311510000 ps |
| CPU time | 4.43 seconds |
| Started | Jul 01 10:27:45 AM PDT 24 |
| Finished | Jul 01 10:27:55 AM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-62e187e2-7c2c-4c26-ac00-f8a78392115f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1532427564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1532427564 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1203494575 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1213770000 ps |
| CPU time | 2.98 seconds |
| Started | Jul 01 10:27:45 AM PDT 24 |
| Finished | Jul 01 10:27:52 AM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-60ad975a-dd42-4c23-8ad5-3e1131504213 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1203494575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1203494575 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1103793250 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1443750000 ps |
| CPU time | 3.98 seconds |
| Started | Jul 01 10:28:01 AM PDT 24 |
| Finished | Jul 01 10:28:11 AM PDT 24 |
| Peak memory | 163304 kb |
| Host | smart-76807201-b5ef-4ac5-80a2-0f9d7948e950 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1103793250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1103793250 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.1472319894 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1572270000 ps |
| CPU time | 3.98 seconds |
| Started | Jul 01 10:28:17 AM PDT 24 |
| Finished | Jul 01 10:28:27 AM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-a2ba6b72-4db8-4692-b4df-c2992bf0202c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1472319894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.1472319894 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.3383175492 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1529710000 ps |
| CPU time | 4.24 seconds |
| Started | Jul 01 10:28:01 AM PDT 24 |
| Finished | Jul 01 10:28:11 AM PDT 24 |
| Peak memory | 163268 kb |
| Host | smart-d65328e6-b70f-4524-aa38-0f0abc4f25d6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3383175492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.3383175492 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2312892963 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1559430000 ps |
| CPU time | 4.58 seconds |
| Started | Jul 01 10:29:42 AM PDT 24 |
| Finished | Jul 01 10:29:53 AM PDT 24 |
| Peak memory | 165080 kb |
| Host | smart-5ba83d0e-7d26-4f06-9e0c-83307f9944b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2312892963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2312892963 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.972256984 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1417790000 ps |
| CPU time | 3.4 seconds |
| Started | Jul 01 10:26:19 AM PDT 24 |
| Finished | Jul 01 10:26:27 AM PDT 24 |
| Peak memory | 164928 kb |
| Host | smart-8945d786-6c55-46a4-93a8-830a398f28ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=972256984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.972256984 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1520228304 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1524190000 ps |
| CPU time | 5.07 seconds |
| Started | Jul 01 10:27:45 AM PDT 24 |
| Finished | Jul 01 10:27:57 AM PDT 24 |
| Peak memory | 164948 kb |
| Host | smart-619acab0-ca10-485a-972a-9964aef57519 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1520228304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1520228304 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.4091046827 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1173650000 ps |
| CPU time | 3.41 seconds |
| Started | Jul 01 10:28:17 AM PDT 24 |
| Finished | Jul 01 10:28:25 AM PDT 24 |
| Peak memory | 164652 kb |
| Host | smart-e5179c50-4292-428f-9ee6-ef956ba6cbc5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4091046827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.4091046827 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.464189882 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1250810000 ps |
| CPU time | 3.13 seconds |
| Started | Jul 01 10:23:38 AM PDT 24 |
| Finished | Jul 01 10:23:45 AM PDT 24 |
| Peak memory | 164872 kb |
| Host | smart-f6ac2a94-a58c-4a57-83d6-ee199df8ae72 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=464189882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.464189882 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.1790363747 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1474050000 ps |
| CPU time | 3.18 seconds |
| Started | Jul 01 10:28:01 AM PDT 24 |
| Finished | Jul 01 10:28:09 AM PDT 24 |
| Peak memory | 164324 kb |
| Host | smart-5772f771-345b-4b7a-955d-1e64dafd8287 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1790363747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.1790363747 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.262388665 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1502190000 ps |
| CPU time | 4.09 seconds |
| Started | Jul 01 10:28:02 AM PDT 24 |
| Finished | Jul 01 10:28:11 AM PDT 24 |
| Peak memory | 164012 kb |
| Host | smart-bc6360c6-5748-44eb-bbf9-2e5379c786fa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=262388665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.262388665 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.1013932086 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1339290000 ps |
| CPU time | 3.2 seconds |
| Started | Jul 01 10:23:20 AM PDT 24 |
| Finished | Jul 01 10:23:27 AM PDT 24 |
| Peak memory | 164768 kb |
| Host | smart-df8a5ede-1525-40ef-b49b-c5dfd395c52e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1013932086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.1013932086 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.250494145 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1502330000 ps |
| CPU time | 4.1 seconds |
| Started | Jul 01 10:22:49 AM PDT 24 |
| Finished | Jul 01 10:22:58 AM PDT 24 |
| Peak memory | 164592 kb |
| Host | smart-da3de903-6a93-4bb2-8546-62d40fcf820c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=250494145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.250494145 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.3440168598 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1484610000 ps |
| CPU time | 4.94 seconds |
| Started | Jul 01 10:26:06 AM PDT 24 |
| Finished | Jul 01 10:26:17 AM PDT 24 |
| Peak memory | 164868 kb |
| Host | smart-c993af3b-63e8-4c4d-8d7b-7b80d0117be4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3440168598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.3440168598 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3513879747 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1567910000 ps |
| CPU time | 3.94 seconds |
| Started | Jul 01 10:23:03 AM PDT 24 |
| Finished | Jul 01 10:23:12 AM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-43567a41-6b04-48b7-a4c0-8e5fc145df95 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3513879747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3513879747 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.968149748 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1553110000 ps |
| CPU time | 3.84 seconds |
| Started | Jul 01 10:28:15 AM PDT 24 |
| Finished | Jul 01 10:28:25 AM PDT 24 |
| Peak memory | 164672 kb |
| Host | smart-4c2e1159-7977-4346-9409-c432570eb46c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=968149748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.968149748 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.893284803 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1543110000 ps |
| CPU time | 4.23 seconds |
| Started | Jul 01 10:23:34 AM PDT 24 |
| Finished | Jul 01 10:23:44 AM PDT 24 |
| Peak memory | 164680 kb |
| Host | smart-2cd45def-0f07-4d20-9634-c88eca4dd410 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=893284803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.893284803 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.3321433123 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1558630000 ps |
| CPU time | 3.46 seconds |
| Started | Jul 01 10:28:02 AM PDT 24 |
| Finished | Jul 01 10:28:11 AM PDT 24 |
| Peak memory | 164372 kb |
| Host | smart-41b9e6bd-7070-428d-943d-566c16242e97 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3321433123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.3321433123 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1890224863 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1221650000 ps |
| CPU time | 3.13 seconds |
| Started | Jul 01 10:22:46 AM PDT 24 |
| Finished | Jul 01 10:22:53 AM PDT 24 |
| Peak memory | 164616 kb |
| Host | smart-d0f02782-b4c7-48f4-a0a5-06ad475875fe |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1890224863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1890224863 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.900162784 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1533750000 ps |
| CPU time | 4.21 seconds |
| Started | Jul 01 10:24:05 AM PDT 24 |
| Finished | Jul 01 10:24:15 AM PDT 24 |
| Peak memory | 164732 kb |
| Host | smart-c53a57ad-f3e5-499a-a095-488aeef0681e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=900162784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.900162784 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3076382841 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1407030000 ps |
| CPU time | 3.42 seconds |
| Started | Jul 01 10:27:56 AM PDT 24 |
| Finished | Jul 01 10:28:05 AM PDT 24 |
| Peak memory | 163500 kb |
| Host | smart-aba13ad4-3e49-44bb-a5a0-b54cc6e2ff03 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3076382841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3076382841 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.66585902 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1272610000 ps |
| CPU time | 3.31 seconds |
| Started | Jul 01 10:28:16 AM PDT 24 |
| Finished | Jul 01 10:28:25 AM PDT 24 |
| Peak memory | 164636 kb |
| Host | smart-ca00b32b-436d-4282-a095-78bb49e04a26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=66585902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.66585902 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1615193973 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1546950000 ps |
| CPU time | 4.97 seconds |
| Started | Jul 01 10:28:04 AM PDT 24 |
| Finished | Jul 01 10:28:15 AM PDT 24 |
| Peak memory | 164240 kb |
| Host | smart-77e9c703-c164-4fb0-9232-db0967fbc14a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1615193973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1615193973 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.282167703 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1305790000 ps |
| CPU time | 3.58 seconds |
| Started | Jul 01 10:23:18 AM PDT 24 |
| Finished | Jul 01 10:23:26 AM PDT 24 |
| Peak memory | 164548 kb |
| Host | smart-662bcf8b-a85b-4731-b266-74da484f2520 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=282167703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.282167703 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4177533670 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1524910000 ps |
| CPU time | 4.67 seconds |
| Started | Jul 01 10:27:45 AM PDT 24 |
| Finished | Jul 01 10:27:55 AM PDT 24 |
| Peak memory | 164820 kb |
| Host | smart-3375356f-1e53-4ee2-875b-e51e4643b83c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4177533670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4177533670 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
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